Intel-XE Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Cc: ville.syrjala@linux.intel.com,
	Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Subject: [PATCH 8/8] drm/i915/display: Prepare for vblank_delay for LRR
Date: Thu,  9 Oct 2025 14:31:02 +0530	[thread overview]
Message-ID: <20251009090102.850344-9-ankit.k.nautiyal@intel.com> (raw)
In-Reply-To: <20251009090102.850344-1-ankit.k.nautiyal@intel.com>

Update allow_vblank_delay_fastset() to permit vblank delay adjustments
during with LRR when VRR TG is always active.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index cd499e58bed3..1426218c01d2 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4958,9 +4958,15 @@ static bool allow_vblank_delay_fastset(const struct intel_crtc_state *old_crtc_s
 	 * Allow fastboot to fix up vblank delay (handled via LRR
 	 * codepaths), a bit dodgy as the registers aren't
 	 * double buffered but seems to be working more or less...
+	 *
+	 * Also allow this when the VRR timing generator is always on,
+	 * and optimized guardband is used. In such cases,
+	 * vblank delay may vary even without inherited state, but it's
+	 * still safe as VRR guardband is still same.
 	 */
-	return HAS_LRR(display) && old_crtc_state->inherited &&
-		!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI);
+	return HAS_LRR(display) &&
+	       (old_crtc_state->inherited || intel_vrr_always_use_vrr_tg(display)) &&
+	       !intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI);
 }
 
 bool
-- 
2.45.2


  parent reply	other threads:[~2025-10-09  9:14 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-09  9:00 [PATCH 0/8] Preparatory patches for guardband optimization Ankit Nautiyal
2025-10-09  9:00 ` [PATCH 1/8] drm/i915/vrr: Use crtc_vsync_start/end for computing vrr.vsync_start/end Ankit Nautiyal
2025-10-09  9:00 ` [PATCH 2/8] drm/i915/vrr: s/intel_vrr_compute_config_late/intel_vrr_compute_guardband Ankit Nautiyal
2025-10-10 14:53   ` Ville Syrjälä
2025-10-13  2:31     ` Nautiyal, Ankit K
2025-10-09  9:00 ` [PATCH 3/8] drm/i915/vblank: Add helper to get correct vblank length Ankit Nautiyal
2025-10-10 14:54   ` Ville Syrjälä
2025-10-09  9:00 ` [PATCH 4/8] drm/i915/psr: Consider SCL lines when validating vblank for wake latency Ankit Nautiyal
2025-10-10  6:40   ` Hogander, Jouni
2025-10-10 13:01     ` Nautiyal, Ankit K
2025-10-09  9:00 ` [PATCH 5/8] drm/i915/display: Check if final vblank is sufficient for PSR features Ankit Nautiyal
2025-10-10  6:53   ` Hogander, Jouni
2025-10-10 13:42     ` Nautiyal, Ankit K
2025-10-13 10:57       ` Hogander, Jouni
2025-10-13 12:29         ` Nautiyal, Ankit K
2025-10-09  9:01 ` [PATCH 6/8] drm/i915/vrr: Recompute vblank_start for platforms with always-on VRR TG Ankit Nautiyal
2025-10-09  9:01 ` [PATCH 7/8] drm/i915/display: Add vblank_start adjustment logic for " Ankit Nautiyal
2025-10-10 15:05   ` Ville Syrjälä
2025-10-13  2:23     ` Nautiyal, Ankit K
2025-10-09  9:01 ` Ankit Nautiyal [this message]
2025-10-09  9:22 ` ✓ CI.KUnit: success for Preparatory patches for guardband optimization (rev2) Patchwork
2025-10-09  9:37 ` ✗ CI.checksparse: warning " Patchwork
2025-10-09 10:14 ` ✓ Xe.CI.BAT: success " Patchwork
2025-10-09 12:42 ` ✓ Xe.CI.Full: " Patchwork
  -- strict thread matches above, loose matches on Subject: below --
2025-10-14  4:16 [PATCH 0/8] Preparatory patches for guardband optimization Ankit Nautiyal
2025-10-14  4:16 ` [PATCH 8/8] drm/i915/display: Prepare for vblank_delay for LRR Ankit Nautiyal
2025-10-09  7:17 [PATCH 0/8] Preparatory patches for guardband optimization Ankit Nautiyal
2025-10-09  7:17 ` [PATCH 8/8] drm/i915/display: Prepare for vblank_delay for LRR Ankit Nautiyal

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20251009090102.850344-9-ankit.k.nautiyal@intel.com \
    --to=ankit.k.nautiyal@intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=intel-xe@lists.freedesktop.org \
    --cc=ville.syrjala@linux.intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox