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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org
Subject: [PATCH 4/8] drm/i915: Start checking plane min size for the chroma plane
Date: Fri, 10 Oct 2025 00:13:08 +0300	[thread overview]
Message-ID: <20251009211313.30234-5-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20251009211313.30234-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Currently we check the plane min size only for the Y plane.
Extend the check to the CbCr plane as well.

This will also allow us to remove the planar format check from
icl_plane_min_width() since the +2 on the CbCr plane is equivalent
to +4 on the Y plane. I suspect this approach actually models the
hardware issue more accurately.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 .../gpu/drm/i915/display/skl_universal_plane.c | 18 +++++-------------
 1 file changed, 5 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 9049cd79a29f..6f187e14f9ae 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -400,17 +400,8 @@ static int icl_plane_min_width(const struct drm_framebuffer *fb,
 			       int color_plane,
 			       unsigned int rotation)
 {
-	int min_width;
-
-	min_width = 16 / fb->format->cpp[color_plane];
-
 	/* Wa_14011264657, Wa_14011050563: gen11+ */
-	if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
-		min_width += 4;
-	else
-		min_width += 2;
-
-	return min_width;
+	return 16 / fb->format->cpp[color_plane] + 2;
 }
 
 static int xe3_plane_max_width(const struct drm_framebuffer *fb,
@@ -2070,6 +2061,7 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
 	int uv_plane = 1;
 	int ccs_plane = intel_fb_is_ccs_modifier(fb->modifier) ?
 			skl_main_to_aux_plane(fb, uv_plane) : 0;
+	int min_width = intel_plane_min_width(plane, fb, uv_plane, rotation);
 	int max_width = intel_plane_max_width(plane, fb, uv_plane, rotation);
 	int max_height = intel_plane_max_height(plane, fb, uv_plane, rotation);
 	int x = plane_state->uapi.src.x1 >> 17;
@@ -2079,11 +2071,11 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
 	u32 offset;
 
 	/* FIXME not quite sure how/if these apply to the chroma plane */
-	if (w > max_width || h > max_height) {
+	if (w > max_width || w < min_width || h > max_height || h < 1) {
 		drm_dbg_kms(display->drm,
-			    "[PLANE:%d:%s] CbCr source size %dx%d too big (limit %dx%d)\n",
+			    "[PLANE:%d:%s] requested CbCr source size %dx%d outside limits (min: %dx1 max: %dx%d)\n",
 			    plane->base.base.id, plane->base.name,
-			    w, h, max_width, max_height);
+			    w, h, min_width, max_width, max_height);
 		return -EINVAL;
 	}
 
-- 
2.49.1


  parent reply	other threads:[~2025-10-09 21:13 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-09 21:13 [PATCH 0/8] drm/i915: Some universal plane fixes and cleanups Ville Syrjala
2025-10-09 21:13 ` [PATCH 1/8] drm/i915: Rewrite icl_min_plane_width() Ville Syrjala
2025-10-09 21:13 ` [PATCH 2/8] drm/i915: Drop the min plane width w/a adl+ Ville Syrjala
2025-10-09 22:38   ` Matt Roper
2025-10-10 23:33     ` Ville Syrjälä
2025-10-09 21:13 ` [PATCH 3/8] drm/i915: Implement .min_plane_width() for PTL+ Ville Syrjala
2025-10-09 21:13 ` Ville Syrjala [this message]
2025-10-09 21:13 ` [PATCH 5/8] drm/i915: Introduce intel_plane_min_height() Ville Syrjala
2025-10-09 21:13 ` [PATCH 6/8] drm/i915: Remove pointless crtc hw.enable check Ville Syrjala
2025-10-09 21:13 ` [PATCH 7/8] drm/i915: Extract glk_plane_has_planar() Ville Syrjala
2025-10-09 21:13 ` [PATCH 8/8] drm/i915: Unify the logic in {skl,glk}_plane_has_*() Ville Syrjala
2025-10-09 21:37 ` ✓ CI.KUnit: success for drm/i915: Some universal plane fixes and cleanups Patchwork
2025-10-09 22:23 ` ✓ Xe.CI.BAT: " Patchwork
2025-10-10  6:33 ` ✗ Xe.CI.Full: failure " Patchwork
2025-10-28  9:36 ` [PATCH 0/8] " Juha-Pekka Heikkilä
2025-10-28 20:58   ` Ville Syrjälä

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