* [PATCH 1/7] drm/i915/display: Sanitize PHY_C20_VDR_CUSTOM_SERDES_RATE/DP_RATE field macros
2025-10-13 9:50 [PATCH 0/7] drm/i915/display: Fix C20 PHY PLL DP/HDMI mode programming Mika Kahola
@ 2025-10-13 9:50 ` Mika Kahola
2025-10-15 11:52 ` Luca Coelho
2025-10-13 9:50 ` [PATCH 2/7] drm/i915/display: Sanitize PHY_C20_VDR_CUSTOM_SERDES_RATE/IS_DP flag macro Mika Kahola
` (6 subsequent siblings)
7 siblings, 1 reply; 16+ messages in thread
From: Mika Kahola @ 2025-10-13 9:50 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: Imre Deak, Mika Kahola
From: Imre Deak <imre.deak@intel.com>
Rename the PHY_C20_CUSTOM_SERDES / PHY_C20_CUSTOM_SERDES_MASK register
field names to PHY_C20_DP_RATE / PHY_C20_DP_RATE_MASK, and move the
definitions under the actual register containing the fields.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 6 +++---
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h | 4 ++--
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index a2d2cecf7121..0d83145eff41 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2700,12 +2700,12 @@ static void intel_c20_pll_program(struct intel_display *display,
/* 5. For DP or 6. For HDMI */
if (is_dp) {
intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE,
- BIT(6) | PHY_C20_CUSTOM_SERDES_MASK,
- BIT(6) | PHY_C20_CUSTOM_SERDES(intel_c20_get_dp_rate(port_clock)),
+ BIT(6) | PHY_C20_DP_RATE_MASK,
+ BIT(6) | PHY_C20_DP_RATE(intel_c20_get_dp_rate(port_clock)),
MB_WRITE_COMMITTED);
} else {
intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE,
- BIT(7) | PHY_C20_CUSTOM_SERDES_MASK,
+ BIT(7) | PHY_C20_DP_RATE_MASK,
is_hdmi_frl(port_clock) ? BIT(7) : 0,
MB_WRITE_COMMITTED);
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
index 77eae1d845f7..25ab8808e548 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
@@ -298,10 +298,10 @@
#define PHY_C20_RD_DATA_L 0xC08
#define PHY_C20_RD_DATA_H 0xC09
#define PHY_C20_VDR_CUSTOM_SERDES_RATE 0xD00
+#define PHY_C20_DP_RATE_MASK REG_GENMASK8(4, 1)
+#define PHY_C20_DP_RATE(val) REG_FIELD_PREP8(PHY_C20_DP_RATE_MASK, val)
#define PHY_C20_VDR_HDMI_RATE 0xD01
#define PHY_C20_CONTEXT_TOGGLE REG_BIT8(0)
-#define PHY_C20_CUSTOM_SERDES_MASK REG_GENMASK8(4, 1)
-#define PHY_C20_CUSTOM_SERDES(val) REG_FIELD_PREP8(PHY_C20_CUSTOM_SERDES_MASK, val)
#define PHY_C20_VDR_CUSTOM_WIDTH 0xD02
#define PHY_C20_CUSTOM_WIDTH_MASK REG_GENMASK(1, 0)
#define PHY_C20_CUSTOM_WIDTH(val) REG_FIELD_PREP8(PHY_C20_CUSTOM_WIDTH_MASK, val)
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH 1/7] drm/i915/display: Sanitize PHY_C20_VDR_CUSTOM_SERDES_RATE/DP_RATE field macros
2025-10-13 9:50 ` [PATCH 1/7] drm/i915/display: Sanitize PHY_C20_VDR_CUSTOM_SERDES_RATE/DP_RATE field macros Mika Kahola
@ 2025-10-15 11:52 ` Luca Coelho
0 siblings, 0 replies; 16+ messages in thread
From: Luca Coelho @ 2025-10-15 11:52 UTC (permalink / raw)
To: Mika Kahola, intel-gfx, intel-xe; +Cc: Imre Deak
On Mon, 2025-10-13 at 12:50 +0300, Mika Kahola wrote:
> From: Imre Deak <imre.deak@intel.com>
>
> Rename the PHY_C20_CUSTOM_SERDES / PHY_C20_CUSTOM_SERDES_MASK register
> field names to PHY_C20_DP_RATE / PHY_C20_DP_RATE_MASK, and move the
> definitions under the actual register containing the fields.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 6 +++---
> drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h | 4 ++--
> 2 files changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index a2d2cecf7121..0d83145eff41 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2700,12 +2700,12 @@ static void intel_c20_pll_program(struct intel_display *display,
> /* 5. For DP or 6. For HDMI */
> if (is_dp) {
> intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE,
> - BIT(6) | PHY_C20_CUSTOM_SERDES_MASK,
> - BIT(6) | PHY_C20_CUSTOM_SERDES(intel_c20_get_dp_rate(port_clock)),
> + BIT(6) | PHY_C20_DP_RATE_MASK,
> + BIT(6) | PHY_C20_DP_RATE(intel_c20_get_dp_rate(port_clock)),
> MB_WRITE_COMMITTED);
> } else {
> intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE,
> - BIT(7) | PHY_C20_CUSTOM_SERDES_MASK,
> + BIT(7) | PHY_C20_DP_RATE_MASK,
> is_hdmi_frl(port_clock) ? BIT(7) : 0,
> MB_WRITE_COMMITTED);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> index 77eae1d845f7..25ab8808e548 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> @@ -298,10 +298,10 @@
> #define PHY_C20_RD_DATA_L 0xC08
> #define PHY_C20_RD_DATA_H 0xC09
> #define PHY_C20_VDR_CUSTOM_SERDES_RATE 0xD00
> +#define PHY_C20_DP_RATE_MASK REG_GENMASK8(4, 1)
> +#define PHY_C20_DP_RATE(val) REG_FIELD_PREP8(PHY_C20_DP_RATE_MASK, val)
> #define PHY_C20_VDR_HDMI_RATE 0xD01
> #define PHY_C20_CONTEXT_TOGGLE REG_BIT8(0)
> -#define PHY_C20_CUSTOM_SERDES_MASK REG_GENMASK8(4, 1)
> -#define PHY_C20_CUSTOM_SERDES(val) REG_FIELD_PREP8(PHY_C20_CUSTOM_SERDES_MASK, val)
> #define PHY_C20_VDR_CUSTOM_WIDTH 0xD02
> #define PHY_C20_CUSTOM_WIDTH_MASK REG_GENMASK(1, 0)
> #define PHY_C20_CUSTOM_WIDTH(val) REG_FIELD_PREP8(PHY_C20_CUSTOM_WIDTH_MASK, val)
Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
--
Cheers,
Luca.
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 2/7] drm/i915/display: Sanitize PHY_C20_VDR_CUSTOM_SERDES_RATE/IS_DP flag macro
2025-10-13 9:50 [PATCH 0/7] drm/i915/display: Fix C20 PHY PLL DP/HDMI mode programming Mika Kahola
2025-10-13 9:50 ` [PATCH 1/7] drm/i915/display: Sanitize PHY_C20_VDR_CUSTOM_SERDES_RATE/DP_RATE field macros Mika Kahola
@ 2025-10-13 9:50 ` Mika Kahola
2025-10-15 11:52 ` Luca Coelho
2025-10-13 9:50 ` [PATCH 3/7] drm/i915/display: Sanitize PHY_C20_VDR_CUSTOM_SERDES_RATE/CONTEXT_TOGGLE " Mika Kahola
` (5 subsequent siblings)
7 siblings, 1 reply; 16+ messages in thread
From: Mika Kahola @ 2025-10-13 9:50 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: Imre Deak, Mika Kahola
From: Imre Deak <imre.deak@intel.com>
Define PHY_C20_IS_DP, so it can be used instead of the plain bit number.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 4 ++--
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h | 1 +
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 0d83145eff41..9492661f1645 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2700,8 +2700,8 @@ static void intel_c20_pll_program(struct intel_display *display,
/* 5. For DP or 6. For HDMI */
if (is_dp) {
intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE,
- BIT(6) | PHY_C20_DP_RATE_MASK,
- BIT(6) | PHY_C20_DP_RATE(intel_c20_get_dp_rate(port_clock)),
+ PHY_C20_IS_DP | PHY_C20_DP_RATE_MASK,
+ PHY_C20_IS_DP | PHY_C20_DP_RATE(intel_c20_get_dp_rate(port_clock)),
MB_WRITE_COMMITTED);
} else {
intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE,
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
index 25ab8808e548..ad2f7fb3beae 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
@@ -298,6 +298,7 @@
#define PHY_C20_RD_DATA_L 0xC08
#define PHY_C20_RD_DATA_H 0xC09
#define PHY_C20_VDR_CUSTOM_SERDES_RATE 0xD00
+#define PHY_C20_IS_DP REG_BIT8(6)
#define PHY_C20_DP_RATE_MASK REG_GENMASK8(4, 1)
#define PHY_C20_DP_RATE(val) REG_FIELD_PREP8(PHY_C20_DP_RATE_MASK, val)
#define PHY_C20_VDR_HDMI_RATE 0xD01
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH 2/7] drm/i915/display: Sanitize PHY_C20_VDR_CUSTOM_SERDES_RATE/IS_DP flag macro
2025-10-13 9:50 ` [PATCH 2/7] drm/i915/display: Sanitize PHY_C20_VDR_CUSTOM_SERDES_RATE/IS_DP flag macro Mika Kahola
@ 2025-10-15 11:52 ` Luca Coelho
0 siblings, 0 replies; 16+ messages in thread
From: Luca Coelho @ 2025-10-15 11:52 UTC (permalink / raw)
To: Mika Kahola, intel-gfx, intel-xe; +Cc: Imre Deak
On Mon, 2025-10-13 at 12:50 +0300, Mika Kahola wrote:
> From: Imre Deak <imre.deak@intel.com>
>
> Define PHY_C20_IS_DP, so it can be used instead of the plain bit number.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 4 ++--
> drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h | 1 +
> 2 files changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 0d83145eff41..9492661f1645 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2700,8 +2700,8 @@ static void intel_c20_pll_program(struct intel_display *display,
> /* 5. For DP or 6. For HDMI */
> if (is_dp) {
> intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE,
> - BIT(6) | PHY_C20_DP_RATE_MASK,
> - BIT(6) | PHY_C20_DP_RATE(intel_c20_get_dp_rate(port_clock)),
> + PHY_C20_IS_DP | PHY_C20_DP_RATE_MASK,
> + PHY_C20_IS_DP | PHY_C20_DP_RATE(intel_c20_get_dp_rate(port_clock)),
> MB_WRITE_COMMITTED);
> } else {
> intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE,
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> index 25ab8808e548..ad2f7fb3beae 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> @@ -298,6 +298,7 @@
> #define PHY_C20_RD_DATA_L 0xC08
> #define PHY_C20_RD_DATA_H 0xC09
> #define PHY_C20_VDR_CUSTOM_SERDES_RATE 0xD00
> +#define PHY_C20_IS_DP REG_BIT8(6)
> #define PHY_C20_DP_RATE_MASK REG_GENMASK8(4, 1)
> #define PHY_C20_DP_RATE(val) REG_FIELD_PREP8(PHY_C20_DP_RATE_MASK, val)
> #define PHY_C20_VDR_HDMI_RATE 0xD01
Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
--
Cheers,
Luca.
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 3/7] drm/i915/display: Sanitize PHY_C20_VDR_CUSTOM_SERDES_RATE/CONTEXT_TOGGLE flag macro
2025-10-13 9:50 [PATCH 0/7] drm/i915/display: Fix C20 PHY PLL DP/HDMI mode programming Mika Kahola
2025-10-13 9:50 ` [PATCH 1/7] drm/i915/display: Sanitize PHY_C20_VDR_CUSTOM_SERDES_RATE/DP_RATE field macros Mika Kahola
2025-10-13 9:50 ` [PATCH 2/7] drm/i915/display: Sanitize PHY_C20_VDR_CUSTOM_SERDES_RATE/IS_DP flag macro Mika Kahola
@ 2025-10-13 9:50 ` Mika Kahola
2025-10-15 11:57 ` Luca Coelho
2025-10-13 9:50 ` [PATCH 4/7] drm/i915/display: Sanitize PHY_C20_VDR_CUSTOM_SERDES_RATE/IS_HDMI_FRL " Mika Kahola
` (4 subsequent siblings)
7 siblings, 1 reply; 16+ messages in thread
From: Mika Kahola @ 2025-10-13 9:50 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: Imre Deak, Jani Nikula, Mika Kahola
From: Imre Deak <imre.deak@intel.com>
Move the PHY_C20_CONTEXT_TOGGLE flag's definition under the register containing
the flag and refer to the flag always by its name instead of a plain bit number.
v2: Amend commit log to match what the patch does. (Jani)
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 6 ++++--
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h | 2 +-
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 9492661f1645..a7aee098e7b9 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2628,7 +2628,8 @@ static void intel_c20_pll_program(struct intel_display *display,
int i;
/* 1. Read current context selection */
- cntx = intel_cx0_read(encoder, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE) & BIT(0);
+ cntx = intel_cx0_read(encoder, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE) &
+ PHY_C20_CONTEXT_TOGGLE;
/*
* 2. If there is a protocol switch from HDMI to DP or vice versa, clear
@@ -2719,7 +2720,8 @@ static void intel_c20_pll_program(struct intel_display *display,
* the updated programming toggle context bit
*/
intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE,
- BIT(0), cntx ? 0 : 1, MB_WRITE_COMMITTED);
+ PHY_C20_CONTEXT_TOGGLE, cntx ? 0 : PHY_C20_CONTEXT_TOGGLE,
+ MB_WRITE_COMMITTED);
}
static int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
index ad2f7fb3beae..5bd1e02b5313 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
@@ -301,8 +301,8 @@
#define PHY_C20_IS_DP REG_BIT8(6)
#define PHY_C20_DP_RATE_MASK REG_GENMASK8(4, 1)
#define PHY_C20_DP_RATE(val) REG_FIELD_PREP8(PHY_C20_DP_RATE_MASK, val)
-#define PHY_C20_VDR_HDMI_RATE 0xD01
#define PHY_C20_CONTEXT_TOGGLE REG_BIT8(0)
+#define PHY_C20_VDR_HDMI_RATE 0xD01
#define PHY_C20_VDR_CUSTOM_WIDTH 0xD02
#define PHY_C20_CUSTOM_WIDTH_MASK REG_GENMASK(1, 0)
#define PHY_C20_CUSTOM_WIDTH(val) REG_FIELD_PREP8(PHY_C20_CUSTOM_WIDTH_MASK, val)
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH 3/7] drm/i915/display: Sanitize PHY_C20_VDR_CUSTOM_SERDES_RATE/CONTEXT_TOGGLE flag macro
2025-10-13 9:50 ` [PATCH 3/7] drm/i915/display: Sanitize PHY_C20_VDR_CUSTOM_SERDES_RATE/CONTEXT_TOGGLE " Mika Kahola
@ 2025-10-15 11:57 ` Luca Coelho
0 siblings, 0 replies; 16+ messages in thread
From: Luca Coelho @ 2025-10-15 11:57 UTC (permalink / raw)
To: Mika Kahola, intel-gfx, intel-xe; +Cc: Imre Deak, Jani Nikula
On Mon, 2025-10-13 at 12:50 +0300, Mika Kahola wrote:
> From: Imre Deak <imre.deak@intel.com>
>
> Move the PHY_C20_CONTEXT_TOGGLE flag's definition under the register containing
> the flag and refer to the flag always by its name instead of a plain bit number.
>
> v2: Amend commit log to match what the patch does. (Jani)
>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 6 ++++--
> drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h | 2 +-
> 2 files changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 9492661f1645..a7aee098e7b9 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2628,7 +2628,8 @@ static void intel_c20_pll_program(struct intel_display *display,
> int i;
>
> /* 1. Read current context selection */
> - cntx = intel_cx0_read(encoder, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE) & BIT(0);
> + cntx = intel_cx0_read(encoder, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE) &
> + PHY_C20_CONTEXT_TOGGLE;
>
> /*
> * 2. If there is a protocol switch from HDMI to DP or vice versa, clear
> @@ -2719,7 +2720,8 @@ static void intel_c20_pll_program(struct intel_display *display,
> * the updated programming toggle context bit
> */
> intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE,
> - BIT(0), cntx ? 0 : 1, MB_WRITE_COMMITTED);
> + PHY_C20_CONTEXT_TOGGLE, cntx ? 0 : PHY_C20_CONTEXT_TOGGLE,
> + MB_WRITE_COMMITTED);
> }
>
> static int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> index ad2f7fb3beae..5bd1e02b5313 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> @@ -301,8 +301,8 @@
> #define PHY_C20_IS_DP REG_BIT8(6)
> #define PHY_C20_DP_RATE_MASK REG_GENMASK8(4, 1)
> #define PHY_C20_DP_RATE(val) REG_FIELD_PREP8(PHY_C20_DP_RATE_MASK, val)
> -#define PHY_C20_VDR_HDMI_RATE 0xD01
> #define PHY_C20_CONTEXT_TOGGLE REG_BIT8(0)
> +#define PHY_C20_VDR_HDMI_RATE 0xD01
> #define PHY_C20_VDR_CUSTOM_WIDTH 0xD02
> #define PHY_C20_CUSTOM_WIDTH_MASK REG_GENMASK(1, 0)
> #define PHY_C20_CUSTOM_WIDTH(val) REG_FIELD_PREP8(PHY_C20_CUSTOM_WIDTH_MASK, val)
Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
--
Cheers,
Luca.
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 4/7] drm/i915/display: Sanitize PHY_C20_VDR_CUSTOM_SERDES_RATE/IS_HDMI_FRL flag macro
2025-10-13 9:50 [PATCH 0/7] drm/i915/display: Fix C20 PHY PLL DP/HDMI mode programming Mika Kahola
` (2 preceding siblings ...)
2025-10-13 9:50 ` [PATCH 3/7] drm/i915/display: Sanitize PHY_C20_VDR_CUSTOM_SERDES_RATE/CONTEXT_TOGGLE " Mika Kahola
@ 2025-10-13 9:50 ` Mika Kahola
2025-10-15 12:01 ` Luca Coelho
2025-10-13 9:50 ` [PATCH 5/7] drm/i915/display: Fix PHY_C20_VDR_CUSTOM_SERDES_RATE programming Mika Kahola
` (3 subsequent siblings)
7 siblings, 1 reply; 16+ messages in thread
From: Mika Kahola @ 2025-10-13 9:50 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: Imre Deak, Mika Kahola
From: Imre Deak <imre.deak@intel.com>
Define PHY_C20_IS_HDMI_FRL, so it can be used instead of the plain bit number.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 4 ++--
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h | 1 +
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index a7aee098e7b9..9be7e155a584 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2706,8 +2706,8 @@ static void intel_c20_pll_program(struct intel_display *display,
MB_WRITE_COMMITTED);
} else {
intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE,
- BIT(7) | PHY_C20_DP_RATE_MASK,
- is_hdmi_frl(port_clock) ? BIT(7) : 0,
+ PHY_C20_IS_HDMI_FRL | PHY_C20_DP_RATE_MASK,
+ is_hdmi_frl(port_clock) ? PHY_C20_IS_HDMI_FRL : 0,
MB_WRITE_COMMITTED);
intel_cx0_write(encoder, INTEL_CX0_BOTH_LANES, PHY_C20_VDR_HDMI_RATE,
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
index 5bd1e02b5313..0743a3e2d15f 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
@@ -298,6 +298,7 @@
#define PHY_C20_RD_DATA_L 0xC08
#define PHY_C20_RD_DATA_H 0xC09
#define PHY_C20_VDR_CUSTOM_SERDES_RATE 0xD00
+#define PHY_C20_IS_HDMI_FRL REG_BIT8(7)
#define PHY_C20_IS_DP REG_BIT8(6)
#define PHY_C20_DP_RATE_MASK REG_GENMASK8(4, 1)
#define PHY_C20_DP_RATE(val) REG_FIELD_PREP8(PHY_C20_DP_RATE_MASK, val)
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH 4/7] drm/i915/display: Sanitize PHY_C20_VDR_CUSTOM_SERDES_RATE/IS_HDMI_FRL flag macro
2025-10-13 9:50 ` [PATCH 4/7] drm/i915/display: Sanitize PHY_C20_VDR_CUSTOM_SERDES_RATE/IS_HDMI_FRL " Mika Kahola
@ 2025-10-15 12:01 ` Luca Coelho
0 siblings, 0 replies; 16+ messages in thread
From: Luca Coelho @ 2025-10-15 12:01 UTC (permalink / raw)
To: Mika Kahola, intel-gfx, intel-xe; +Cc: Imre Deak
On Mon, 2025-10-13 at 12:50 +0300, Mika Kahola wrote:
> From: Imre Deak <imre.deak@intel.com>
>
> Define PHY_C20_IS_HDMI_FRL, so it can be used instead of the plain bit number.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 4 ++--
> drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h | 1 +
> 2 files changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index a7aee098e7b9..9be7e155a584 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2706,8 +2706,8 @@ static void intel_c20_pll_program(struct intel_display *display,
> MB_WRITE_COMMITTED);
> } else {
> intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE,
> - BIT(7) | PHY_C20_DP_RATE_MASK,
> - is_hdmi_frl(port_clock) ? BIT(7) : 0,
> + PHY_C20_IS_HDMI_FRL | PHY_C20_DP_RATE_MASK,
> + is_hdmi_frl(port_clock) ? PHY_C20_IS_HDMI_FRL : 0,
> MB_WRITE_COMMITTED);
>
> intel_cx0_write(encoder, INTEL_CX0_BOTH_LANES, PHY_C20_VDR_HDMI_RATE,
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> index 5bd1e02b5313..0743a3e2d15f 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> @@ -298,6 +298,7 @@
> #define PHY_C20_RD_DATA_L 0xC08
> #define PHY_C20_RD_DATA_H 0xC09
> #define PHY_C20_VDR_CUSTOM_SERDES_RATE 0xD00
> +#define PHY_C20_IS_HDMI_FRL REG_BIT8(7)
> #define PHY_C20_IS_DP REG_BIT8(6)
> #define PHY_C20_DP_RATE_MASK REG_GENMASK8(4, 1)
> #define PHY_C20_DP_RATE(val) REG_FIELD_PREP8(PHY_C20_DP_RATE_MASK, val)
Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
--
Cheers,
Luca.
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 5/7] drm/i915/display: Fix PHY_C20_VDR_CUSTOM_SERDES_RATE programming
2025-10-13 9:50 [PATCH 0/7] drm/i915/display: Fix C20 PHY PLL DP/HDMI mode programming Mika Kahola
` (3 preceding siblings ...)
2025-10-13 9:50 ` [PATCH 4/7] drm/i915/display: Sanitize PHY_C20_VDR_CUSTOM_SERDES_RATE/IS_HDMI_FRL " Mika Kahola
@ 2025-10-13 9:50 ` Mika Kahola
2025-10-15 12:14 ` Luca Coelho
2025-10-13 9:50 ` [PATCH 6/7] drm/i915/display: Fix PHY_C20_VDR_HDMI_RATE programming Mika Kahola
` (2 subsequent siblings)
7 siblings, 1 reply; 16+ messages in thread
From: Mika Kahola @ 2025-10-13 9:50 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: Imre Deak, Mika Kahola
From: Imre Deak <imre.deak@intel.com>
Make sure all the DP/HDMI/HDMI-FRL flags are programmed in all the modes
the PLL is configured.
Atm the DP mode flag is not programmed in case the PLL is configured for
HDMI mode for instance. This is incorrect after HW reset, since the DP
mode flag is asserted after reset, hence would need to be cleared for
HDMI, but also incorrect because of the same reason after configuring
the PLL to HDMI mode after it was used in DP mode (for instance on a
DP++ connector).
There is a similar issue with the HDMI-FRL flag, potentially remaining
set when configuring the PLL in DP mode.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 25 +++++++++++---------
1 file changed, 14 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 9be7e155a584..6e49659d2f17 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2624,6 +2624,7 @@ static void intel_c20_pll_program(struct intel_display *display,
bool is_dp, int port_clock)
{
u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder);
+ u8 serdes;
bool cntx;
int i;
@@ -2699,21 +2700,23 @@ static void intel_c20_pll_program(struct intel_display *display,
MB_WRITE_COMMITTED);
/* 5. For DP or 6. For HDMI */
- if (is_dp) {
- intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE,
- PHY_C20_IS_DP | PHY_C20_DP_RATE_MASK,
- PHY_C20_IS_DP | PHY_C20_DP_RATE(intel_c20_get_dp_rate(port_clock)),
- MB_WRITE_COMMITTED);
- } else {
- intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE,
- PHY_C20_IS_HDMI_FRL | PHY_C20_DP_RATE_MASK,
- is_hdmi_frl(port_clock) ? PHY_C20_IS_HDMI_FRL : 0,
- MB_WRITE_COMMITTED);
+ serdes = 0;
+
+ if (is_dp)
+ serdes = PHY_C20_IS_DP |
+ PHY_C20_DP_RATE(intel_c20_get_dp_rate(port_clock));
+ else if (is_hdmi_frl(port_clock))
+ serdes = PHY_C20_IS_HDMI_FRL;
+ intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE,
+ PHY_C20_IS_DP | PHY_C20_DP_RATE_MASK | PHY_C20_IS_HDMI_FRL,
+ serdes,
+ MB_WRITE_COMMITTED);
+
+ if (!is_dp)
intel_cx0_write(encoder, INTEL_CX0_BOTH_LANES, PHY_C20_VDR_HDMI_RATE,
intel_c20_get_hdmi_rate(port_clock),
MB_WRITE_COMMITTED);
- }
/*
* 7. Write Vendor specific registers to toggle context setting to load
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH 5/7] drm/i915/display: Fix PHY_C20_VDR_CUSTOM_SERDES_RATE programming
2025-10-13 9:50 ` [PATCH 5/7] drm/i915/display: Fix PHY_C20_VDR_CUSTOM_SERDES_RATE programming Mika Kahola
@ 2025-10-15 12:14 ` Luca Coelho
0 siblings, 0 replies; 16+ messages in thread
From: Luca Coelho @ 2025-10-15 12:14 UTC (permalink / raw)
To: Mika Kahola, intel-gfx, intel-xe; +Cc: Imre Deak
On Mon, 2025-10-13 at 12:50 +0300, Mika Kahola wrote:
> From: Imre Deak <imre.deak@intel.com>
>
> Make sure all the DP/HDMI/HDMI-FRL flags are programmed in all the modes
> the PLL is configured.
>
> Atm the DP mode flag is not programmed in case the PLL is configured for
> HDMI mode for instance. This is incorrect after HW reset, since the DP
> mode flag is asserted after reset, hence would need to be cleared for
> HDMI, but also incorrect because of the same reason after configuring
> the PLL to HDMI mode after it was used in DP mode (for instance on a
> DP++ connector).
>
> There is a similar issue with the HDMI-FRL flag, potentially remaining
> set when configuring the PLL in DP mode.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 25 +++++++++++---------
> 1 file changed, 14 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 9be7e155a584..6e49659d2f17 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2624,6 +2624,7 @@ static void intel_c20_pll_program(struct intel_display *display,
> bool is_dp, int port_clock)
> {
> u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder);
> + u8 serdes;
> bool cntx;
> int i;
>
> @@ -2699,21 +2700,23 @@ static void intel_c20_pll_program(struct intel_display *display,
> MB_WRITE_COMMITTED);
>
> /* 5. For DP or 6. For HDMI */
> - if (is_dp) {
> - intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE,
> - PHY_C20_IS_DP | PHY_C20_DP_RATE_MASK,
> - PHY_C20_IS_DP | PHY_C20_DP_RATE(intel_c20_get_dp_rate(port_clock)),
> - MB_WRITE_COMMITTED);
> - } else {
> - intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE,
> - PHY_C20_IS_HDMI_FRL | PHY_C20_DP_RATE_MASK,
> - is_hdmi_frl(port_clock) ? PHY_C20_IS_HDMI_FRL : 0,
> - MB_WRITE_COMMITTED);
> + serdes = 0;
> +
> + if (is_dp)
> + serdes = PHY_C20_IS_DP |
> + PHY_C20_DP_RATE(intel_c20_get_dp_rate(port_clock));
> + else if (is_hdmi_frl(port_clock))
> + serdes = PHY_C20_IS_HDMI_FRL;
>
> + intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE,
> + PHY_C20_IS_DP | PHY_C20_DP_RATE_MASK | PHY_C20_IS_HDMI_FRL,
> + serdes,
> + MB_WRITE_COMMITTED);
> +
> + if (!is_dp)
> intel_cx0_write(encoder, INTEL_CX0_BOTH_LANES, PHY_C20_VDR_HDMI_RATE,
> intel_c20_get_hdmi_rate(port_clock),
> MB_WRITE_COMMITTED);
> - }
>
> /*
> * 7. Write Vendor specific registers to toggle context setting to load
Seems to match the bspec.
Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
--
Cheers,
Luca.
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 6/7] drm/i915/display: Fix PHY_C20_VDR_HDMI_RATE programming
2025-10-13 9:50 [PATCH 0/7] drm/i915/display: Fix C20 PHY PLL DP/HDMI mode programming Mika Kahola
` (4 preceding siblings ...)
2025-10-13 9:50 ` [PATCH 5/7] drm/i915/display: Fix PHY_C20_VDR_CUSTOM_SERDES_RATE programming Mika Kahola
@ 2025-10-13 9:50 ` Mika Kahola
2025-10-15 12:20 ` Luca Coelho
2025-10-13 9:50 ` [PATCH 7/7] drm/i915/display: Add missing clock to C10 PHY state compute/HW readout Mika Kahola
2025-10-16 10:55 ` [PATCH 0/7] drm/i915/display: Fix C20 PHY PLL DP/HDMI mode programming Kahola, Mika
7 siblings, 1 reply; 16+ messages in thread
From: Mika Kahola @ 2025-10-13 9:50 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: Imre Deak, Mika Kahola
From: Imre Deak <imre.deak@intel.com>
The PHY_C20_VDR_HDMI_RATE registers 7:2 bits are reserved and they are
not specified as a must-be-zero field. Accordingly this reserved field
shouldn't be zeroed; to ensure that use an RMW to update the
PHY_C20_HDMI_RATE field (which is bits 1:0 of the register).
Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 7 ++++---
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h | 2 ++
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 6e49659d2f17..f8c1338f9053 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2714,9 +2714,10 @@ static void intel_c20_pll_program(struct intel_display *display,
MB_WRITE_COMMITTED);
if (!is_dp)
- intel_cx0_write(encoder, INTEL_CX0_BOTH_LANES, PHY_C20_VDR_HDMI_RATE,
- intel_c20_get_hdmi_rate(port_clock),
- MB_WRITE_COMMITTED);
+ intel_cx0_rmw(encoder, INTEL_CX0_BOTH_LANES, PHY_C20_VDR_HDMI_RATE,
+ PHY_C20_HDMI_RATE_MASK,
+ intel_c20_get_hdmi_rate(port_clock),
+ MB_WRITE_COMMITTED);
/*
* 7. Write Vendor specific registers to toggle context setting to load
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
index 0743a3e2d15f..86e2e1c7babf 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
@@ -304,6 +304,8 @@
#define PHY_C20_DP_RATE(val) REG_FIELD_PREP8(PHY_C20_DP_RATE_MASK, val)
#define PHY_C20_CONTEXT_TOGGLE REG_BIT8(0)
#define PHY_C20_VDR_HDMI_RATE 0xD01
+#define PHY_C20_HDMI_RATE_MASK REG_GENMASK8(1, 0)
+#define PHY_C20_HDMI_RATE(val) REG_FIELD_PREP8(PHY_C20_HDMI_RATE_MASK, val)
#define PHY_C20_VDR_CUSTOM_WIDTH 0xD02
#define PHY_C20_CUSTOM_WIDTH_MASK REG_GENMASK(1, 0)
#define PHY_C20_CUSTOM_WIDTH(val) REG_FIELD_PREP8(PHY_C20_CUSTOM_WIDTH_MASK, val)
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH 6/7] drm/i915/display: Fix PHY_C20_VDR_HDMI_RATE programming
2025-10-13 9:50 ` [PATCH 6/7] drm/i915/display: Fix PHY_C20_VDR_HDMI_RATE programming Mika Kahola
@ 2025-10-15 12:20 ` Luca Coelho
0 siblings, 0 replies; 16+ messages in thread
From: Luca Coelho @ 2025-10-15 12:20 UTC (permalink / raw)
To: Mika Kahola, intel-gfx, intel-xe; +Cc: Imre Deak
On Mon, 2025-10-13 at 12:50 +0300, Mika Kahola wrote:
> From: Imre Deak <imre.deak@intel.com>
>
> The PHY_C20_VDR_HDMI_RATE registers 7:2 bits are reserved and they are
> not specified as a must-be-zero field. Accordingly this reserved field
> shouldn't be zeroed; to ensure that use an RMW to update the
> PHY_C20_HDMI_RATE field (which is bits 1:0 of the register).
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 7 ++++---
> drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h | 2 ++
> 2 files changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 6e49659d2f17..f8c1338f9053 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2714,9 +2714,10 @@ static void intel_c20_pll_program(struct intel_display *display,
> MB_WRITE_COMMITTED);
>
> if (!is_dp)
> - intel_cx0_write(encoder, INTEL_CX0_BOTH_LANES, PHY_C20_VDR_HDMI_RATE,
> - intel_c20_get_hdmi_rate(port_clock),
> - MB_WRITE_COMMITTED);
> + intel_cx0_rmw(encoder, INTEL_CX0_BOTH_LANES, PHY_C20_VDR_HDMI_RATE,
> + PHY_C20_HDMI_RATE_MASK,
> + intel_c20_get_hdmi_rate(port_clock),
> + MB_WRITE_COMMITTED);
>
> /*
> * 7. Write Vendor specific registers to toggle context setting to load
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> index 0743a3e2d15f..86e2e1c7babf 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> @@ -304,6 +304,8 @@
> #define PHY_C20_DP_RATE(val) REG_FIELD_PREP8(PHY_C20_DP_RATE_MASK, val)
> #define PHY_C20_CONTEXT_TOGGLE REG_BIT8(0)
> #define PHY_C20_VDR_HDMI_RATE 0xD01
> +#define PHY_C20_HDMI_RATE_MASK REG_GENMASK8(1, 0)
> +#define PHY_C20_HDMI_RATE(val) REG_FIELD_PREP8(PHY_C20_HDMI_RATE_MASK, val)
> #define PHY_C20_VDR_CUSTOM_WIDTH 0xD02
> #define PHY_C20_CUSTOM_WIDTH_MASK REG_GENMASK(1, 0)
> #define PHY_C20_CUSTOM_WIDTH(val) REG_FIELD_PREP8(PHY_C20_CUSTOM_WIDTH_MASK, val)
Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
--
Cheers,
Luca.
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 7/7] drm/i915/display: Add missing clock to C10 PHY state compute/HW readout
2025-10-13 9:50 [PATCH 0/7] drm/i915/display: Fix C20 PHY PLL DP/HDMI mode programming Mika Kahola
` (5 preceding siblings ...)
2025-10-13 9:50 ` [PATCH 6/7] drm/i915/display: Fix PHY_C20_VDR_HDMI_RATE programming Mika Kahola
@ 2025-10-13 9:50 ` Mika Kahola
2025-10-15 12:32 ` Luca Coelho
2025-10-16 10:55 ` [PATCH 0/7] drm/i915/display: Fix C20 PHY PLL DP/HDMI mode programming Kahola, Mika
7 siblings, 1 reply; 16+ messages in thread
From: Mika Kahola @ 2025-10-13 9:50 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: Imre Deak, Mika Kahola
From: Imre Deak <imre.deak@intel.com>
Clock value is missing from C10 hw readout stage. Let's fix this.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 5 +++++
drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c | 2 ++
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index f8c1338f9053..a74c1be225ac 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2103,6 +2103,9 @@ static int intel_c10pll_calc_state(struct intel_crtc_state *crtc_state,
return 0;
}
+static int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,
+ const struct intel_c10pll_state *pll_state);
+
static void intel_c10pll_readout_hw_state(struct intel_encoder *encoder,
struct intel_c10pll_state *pll_state)
{
@@ -2127,6 +2130,8 @@ static void intel_c10pll_readout_hw_state(struct intel_encoder *encoder,
pll_state->tx = intel_cx0_read(encoder, lane, PHY_C10_VDR_TX(0));
intel_cx0_phy_transaction_end(encoder, wakeref);
+
+ pll_state->clock = intel_c10pll_calc_port_clock(encoder, pll_state);
}
static void intel_c10_pll_program(struct intel_display *display,
diff --git a/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c b/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c
index 7fe6b4a18213..a201edceee10 100644
--- a/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c
+++ b/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c
@@ -332,6 +332,8 @@ void intel_snps_hdmi_pll_compute_c10pll(struct intel_c10pll_state *pll_state, u6
c10_curve_1, c10_curve_2, prescaler_divider,
&pll_params);
+ pll_state->clock = pixel_clock;
+
pll_state->tx = 0x10;
pll_state->cmn = 0x1;
pll_state->pll[0] = REG_FIELD_PREP(C10_PLL0_DIV5CLK_EN, pll_params.mpll_div5_en) |
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH 7/7] drm/i915/display: Add missing clock to C10 PHY state compute/HW readout
2025-10-13 9:50 ` [PATCH 7/7] drm/i915/display: Add missing clock to C10 PHY state compute/HW readout Mika Kahola
@ 2025-10-15 12:32 ` Luca Coelho
0 siblings, 0 replies; 16+ messages in thread
From: Luca Coelho @ 2025-10-15 12:32 UTC (permalink / raw)
To: Mika Kahola, intel-gfx, intel-xe; +Cc: Imre Deak
On Mon, 2025-10-13 at 12:50 +0300, Mika Kahola wrote:
> From: Imre Deak <imre.deak@intel.com>
>
> Clock value is missing from C10 hw readout stage. Let's fix this.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 5 +++++
> drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c | 2 ++
> 2 files changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index f8c1338f9053..a74c1be225ac 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2103,6 +2103,9 @@ static int intel_c10pll_calc_state(struct intel_crtc_state *crtc_state,
> return 0;
> }
>
> +static int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,
> + const struct intel_c10pll_state *pll_state);
> +
> static void intel_c10pll_readout_hw_state(struct intel_encoder *encoder,
> struct intel_c10pll_state *pll_state)
> {
> @@ -2127,6 +2130,8 @@ static void intel_c10pll_readout_hw_state(struct intel_encoder *encoder,
> pll_state->tx = intel_cx0_read(encoder, lane, PHY_C10_VDR_TX(0));
>
> intel_cx0_phy_transaction_end(encoder, wakeref);
> +
> + pll_state->clock = intel_c10pll_calc_port_clock(encoder, pll_state);
> }
>
> static void intel_c10_pll_program(struct intel_display *display,
> diff --git a/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c b/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c
> index 7fe6b4a18213..a201edceee10 100644
> --- a/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c
> +++ b/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c
> @@ -332,6 +332,8 @@ void intel_snps_hdmi_pll_compute_c10pll(struct intel_c10pll_state *pll_state, u6
> c10_curve_1, c10_curve_2, prescaler_divider,
> &pll_params);
>
> + pll_state->clock = pixel_clock;
> +
> pll_state->tx = 0x10;
> pll_state->cmn = 0x1;
> pll_state->pll[0] = REG_FIELD_PREP(C10_PLL0_DIV5CLK_EN, pll_params.mpll_div5_en) |
Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
--
Cheers,
Luca.
^ permalink raw reply [flat|nested] 16+ messages in thread
* RE: [PATCH 0/7] drm/i915/display: Fix C20 PHY PLL DP/HDMI mode programming
2025-10-13 9:50 [PATCH 0/7] drm/i915/display: Fix C20 PHY PLL DP/HDMI mode programming Mika Kahola
` (6 preceding siblings ...)
2025-10-13 9:50 ` [PATCH 7/7] drm/i915/display: Add missing clock to C10 PHY state compute/HW readout Mika Kahola
@ 2025-10-16 10:55 ` Kahola, Mika
7 siblings, 0 replies; 16+ messages in thread
From: Kahola, Mika @ 2025-10-16 10:55 UTC (permalink / raw)
To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Cc: Coelho, Luciano
> -----Original Message-----
> From: Kahola, Mika <mika.kahola@intel.com>
> Sent: Monday, 13 October 2025 12.51
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Kahola, Mika <mika.kahola@intel.com>
> Subject: [PATCH 0/7] drm/i915/display: Fix C20 PHY PLL DP/HDMI mode programming
>
> This patchset fixes the DP/HDMI mode programming for C20 PHY PLLs. While at it, it also adds the missing port clock HW readout
> for C10 PHY PLLs.
>
>
> These patches were originally part of the RFC PLL rework patch series [1], now resent separately since they include a fix, which as
> such should be tested/merged separately.
>
> [1] https://lore.kernel.org/all/20251001082839.2585559-1-mika.kahola@intel.com
>
Thanks, Luca, for reviewing the series. Series is now merged upstream.
-Mika-
> Imre Deak (7):
> drm/i915/display: Sanitize PHY_C20_VDR_CUSTOM_SERDES_RATE/DP_RATE
> field macros
> drm/i915/display: Sanitize PHY_C20_VDR_CUSTOM_SERDES_RATE/IS_DP flag
> macro
> drm/i915/display: Sanitize
> PHY_C20_VDR_CUSTOM_SERDES_RATE/CONTEXT_TOGGLE flag macro
> drm/i915/display: Sanitize PHY_C20_VDR_CUSTOM_SERDES_RATE/IS_HDMI_FRL
> flag macro
> drm/i915/display: Fix PHY_C20_VDR_CUSTOM_SERDES_RATE programming
> drm/i915/display: Fix PHY_C20_VDR_HDMI_RATE programming
> drm/i915/display: Add missing clock to C10 PHY state compute/HW
> readout
>
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 43 ++++++++++++------- .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 10
> +++--
> .../drm/i915/display/intel_snps_hdmi_pll.c | 2 +
> 3 files changed, 36 insertions(+), 19 deletions(-)
>
> --
> 2.34.1
^ permalink raw reply [flat|nested] 16+ messages in thread