From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Cc: ville.syrjala@linux.intel.com, jouni.hogander@intel.com,
animesh.manna@intel.com,
Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Subject: [PATCH 8/8] drm/i915/display: Add vblank_start adjustment logic for always-on VRR TG
Date: Mon, 13 Oct 2025 18:05:59 +0530 [thread overview]
Message-ID: <20251013123559.1055429-9-ankit.k.nautiyal@intel.com> (raw)
In-Reply-To: <20251013123559.1055429-1-ankit.k.nautiyal@intel.com>
As we move towards using a shorter, optimized guardband, we need to adjust
how the delayed vblank start is computed.
Adjust the crtc_vblank_start using Vtotal - guardband only when
intel_vrr_always_use_vrr_tg() is true.
Also update allow_vblank_delay_fastset() to permit vblank delay adjustments
while switching to lower refresh rate mode (LRR), when VRR TG is always
active. This avoids full modeset due to change in vblank start, while
maintaining consistent guardband.
These changes pave the way for future guardband optimization, by handling
the movement of the crtc_vblank_start for platforms that have VRR TG always
active.
v2: Drop the helper and add the adjustment directly to
intel_vrr_compute_guardband(). (Ville)
v3: Use adjusted_mode.crtc_vtotal instead of vmin and include the readout
logic to keep the compute and readout paths in sync. (Ville)
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 10 ++++++++--
drivers/gpu/drm/i915/display/intel_vrr.c | 6 +++++-
2 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index ceee5ae99c2c..65a7da694ef6 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4958,9 +4958,15 @@ static bool allow_vblank_delay_fastset(const struct intel_crtc_state *old_crtc_s
* Allow fastboot to fix up vblank delay (handled via LRR
* codepaths), a bit dodgy as the registers aren't
* double buffered but seems to be working more or less...
+ *
+ * Also allow this when the VRR timing generator is always on,
+ * and optimized guardband is used. In such cases,
+ * vblank delay may vary even without inherited state, but it's
+ * still safe as VRR guardband is still same.
*/
- return HAS_LRR(display) && old_crtc_state->inherited &&
- !intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI);
+ return HAS_LRR(display) &&
+ (old_crtc_state->inherited || intel_vrr_always_use_vrr_tg(display)) &&
+ !intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI);
}
bool
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 221b25832e56..a4b416da53f4 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -436,7 +436,7 @@ intel_vrr_max_guardband(struct intel_crtc_state *crtc_state)
void intel_vrr_compute_guardband(struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
- const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+ struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
if (!intel_vrr_possible(crtc_state))
return;
@@ -444,6 +444,10 @@ void intel_vrr_compute_guardband(struct intel_crtc_state *crtc_state)
crtc_state->vrr.guardband = min(crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay,
intel_vrr_max_guardband(crtc_state));
+ if (intel_vrr_always_use_vrr_tg(display))
+ adjusted_mode->crtc_vblank_start =
+ adjusted_mode->crtc_vtotal - crtc_state->vrr.guardband;
+
if (DISPLAY_VER(display) < 13)
crtc_state->vrr.pipeline_full =
intel_vrr_guardband_to_pipeline_full(crtc_state,
--
2.45.2
next prev parent reply other threads:[~2025-10-13 12:49 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-13 12:35 [PATCH 0/8] Preparatory patches for guardband optimization Ankit Nautiyal
2025-10-13 12:35 ` [PATCH 1/8] drm/i915/vrr: Use crtc_vsync_start/end for computing vrr.vsync_start/end Ankit Nautiyal
2025-10-13 12:35 ` [PATCH 2/8] drm/i915/display: Move intel_dpll_crtc_compute_clock early Ankit Nautiyal
2025-10-13 14:03 ` Ville Syrjälä
2025-10-13 12:35 ` [PATCH 3/8] drm/i915/vrr: s/intel_vrr_compute_config_late/intel_vrr_compute_guardband Ankit Nautiyal
2025-10-13 14:16 ` Ville Syrjälä
2025-10-13 12:35 ` [PATCH 4/8] drm/i915/vblank: Add helper to get correct vblank length Ankit Nautiyal
2025-10-13 12:35 ` [PATCH 5/8] drm/i915/psr: Consider SCL lines when validating vblank for wake latency Ankit Nautiyal
2025-10-13 12:35 ` [PATCH 6/8] drm/i915/display: Check if final vblank is sufficient for PSR features Ankit Nautiyal
2025-10-13 12:35 ` [PATCH 7/8] drm/i915/vrr: Recompute vblank_start for platforms with always-on VRR TG Ankit Nautiyal
2025-10-13 14:27 ` Ville Syrjälä
2025-10-13 12:35 ` Ankit Nautiyal [this message]
2025-10-13 13:00 ` ✓ CI.KUnit: success for Preparatory patches for guardband optimization (rev3) Patchwork
2025-10-13 13:15 ` ✗ CI.checksparse: warning " Patchwork
2025-10-13 13:37 ` ✓ Xe.CI.BAT: success " Patchwork
2025-10-13 14:59 ` ✗ Xe.CI.Full: failure " Patchwork
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