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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org,
	jouni.hogander@intel.com, animesh.manna@intel.com
Subject: Re: [PATCH 7/8] drm/i915/vrr: Recompute vblank_start for platforms with always-on VRR TG
Date: Mon, 13 Oct 2025 17:27:53 +0300	[thread overview]
Message-ID: <aO0MaW2Q-o6QXGo_@intel.com> (raw)
In-Reply-To: <20251013123559.1055429-8-ankit.k.nautiyal@intel.com>

On Mon, Oct 13, 2025 at 06:05:58PM +0530, Ankit Nautiyal wrote:
> Currently, crtc_vblank_start is read from either the VBLANK_START register
> (on pre-ADL platforms) or computed as vdisplay + set_context_latency in
> intel_get_transcoder_timings().
> 
> This works when the entire vblank region after vdisplay is treated as
> guardband, i.e.:
> delayed vblank start = vdisplay + SCL = vtotal - guardband.
> 
> However, with optimized guardband, the guardband becomes shorter, and the
> delayed vblank_start moves further away from vdisplay.
> 
> For platforms where intel_vrr_always_use_vrr_tg == false, the delayed
> vblank start is only relevant in VRR mode. We retain the original
> crtc_vblank_start and apply adjustments in VRR-specific paths. Evasion
> logic, push clear already use vtotal - guardband directly for VRR case.
> 
> On platforms where intel_vrr_always_use_vrr_tg == true, the delayed
> vblank_start is used in both fixed and VRR modes. So we need to change the
> crtc_vblank_start so that fixed rr case works properly.
> 
> Therefore for the readout, we need to overwrite crtc_vblank_start
> with vtotal - guardband to ensure correct behavior across both modes.
> 
> This change prepares the pipeline for optimized guardband usage by ensuring
> crtc_vblank_start reflects the correct timing on platforms with always-on
> VRR TG.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_vrr.c | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 8d71d7dc9d12..221b25832e56 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -821,6 +821,20 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
>  	 */
>  	if (crtc_state->vrr.enable)
>  		crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
> +
> +	/*
> +	 * For platforms that always use the VRR timing generator, we overwrite
> +	 * crtc_vblank_start with vtotal - guardband to reflect the delayed
> +	 * vblank start. This works for both default and optimized guardband values.
> +	 * On other platforms, we keep the original value from
> +	 * intel_get_transcoder_timings() and apply adjustments only in VRR-specific
> +	 * paths as needed.
> +	 */
> +	if (intel_vrr_always_use_vrr_tg(display))
> +		crtc_state->hw.adjusted_mode.crtc_vblank_start =
> +			crtc_state->hw.adjusted_mode.crtc_vtotal -
> +			crtc_state->vrr.guardband;

You still lost the compute counterpart somewhere.

And as mentioned, the new order of compute_pipe_mode()->compute_guardband()
will require that we fix up pipe_mode well (in the compute path). Could
just do it as 'pipe_mode.crtc_vblank_start = adjusted_mode.crtc_vblank_start'
after adjusted_mode has been tweaked.

It's a bit annoying that we need that one special pipe_mode handling in
the compute path, but there is no counterpart in the readout path.
But I suppose the only way to fix that would be to manually account for
joiner in the guardband calculations, which might be annoying as well...

-- 
Ville Syrjälä
Intel

  reply	other threads:[~2025-10-13 14:28 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-13 12:35 [PATCH 0/8] Preparatory patches for guardband optimization Ankit Nautiyal
2025-10-13 12:35 ` [PATCH 1/8] drm/i915/vrr: Use crtc_vsync_start/end for computing vrr.vsync_start/end Ankit Nautiyal
2025-10-13 12:35 ` [PATCH 2/8] drm/i915/display: Move intel_dpll_crtc_compute_clock early Ankit Nautiyal
2025-10-13 14:03   ` Ville Syrjälä
2025-10-13 12:35 ` [PATCH 3/8] drm/i915/vrr: s/intel_vrr_compute_config_late/intel_vrr_compute_guardband Ankit Nautiyal
2025-10-13 14:16   ` Ville Syrjälä
2025-10-13 12:35 ` [PATCH 4/8] drm/i915/vblank: Add helper to get correct vblank length Ankit Nautiyal
2025-10-13 12:35 ` [PATCH 5/8] drm/i915/psr: Consider SCL lines when validating vblank for wake latency Ankit Nautiyal
2025-10-13 12:35 ` [PATCH 6/8] drm/i915/display: Check if final vblank is sufficient for PSR features Ankit Nautiyal
2025-10-13 12:35 ` [PATCH 7/8] drm/i915/vrr: Recompute vblank_start for platforms with always-on VRR TG Ankit Nautiyal
2025-10-13 14:27   ` Ville Syrjälä [this message]
2025-10-13 12:35 ` [PATCH 8/8] drm/i915/display: Add vblank_start adjustment logic for " Ankit Nautiyal
2025-10-13 13:00 ` ✓ CI.KUnit: success for Preparatory patches for guardband optimization (rev3) Patchwork
2025-10-13 13:15 ` ✗ CI.checksparse: warning " Patchwork
2025-10-13 13:37 ` ✓ Xe.CI.BAT: success " Patchwork
2025-10-13 14:59 ` ✗ Xe.CI.Full: failure " Patchwork

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