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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org
Subject: [PATCH 6/9] drm/i915: s/min_cdck[]/plane_min_cdclk[]/
Date: Mon, 13 Oct 2025 23:12:33 +0300	[thread overview]
Message-ID: <20251013201236.30084-7-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20251013201236.30084-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Rename crtc_state->min_cdclk[] into crtc_state->plane_min_cdclk[]
to better reflect what it represents.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c         | 2 +-
 drivers/gpu/drm/i915/display/intel_display_types.h | 2 +-
 drivers/gpu/drm/i915/display/intel_modeset_setup.c | 6 +++---
 drivers/gpu/drm/i915/display/intel_plane.c         | 4 ++--
 4 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index d55b3dc23356..ed64fac7897d 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2824,7 +2824,7 @@ static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state)
 	int min_cdclk = 0;
 
 	for_each_intel_plane_on_crtc(display->drm, crtc, plane)
-		min_cdclk = max(min_cdclk, crtc_state->min_cdclk[plane->id]);
+		min_cdclk = max(min_cdclk, crtc_state->plane_min_cdclk[plane->id]);
 
 	return min_cdclk;
 }
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 87b7cec35320..f77d120733fd 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1192,7 +1192,7 @@ struct intel_crtc_state {
 
 	struct intel_crtc_wm_state wm;
 
-	int min_cdclk[I915_MAX_PLANES];
+	int plane_min_cdclk[I915_MAX_PLANES];
 
 	/* for packed/planar CbCr */
 	u32 data_rate[I915_MAX_PLANES];
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index deb877b2aebd..d5c432b613ce 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -853,16 +853,16 @@ static void intel_modeset_readout_hw_state(struct intel_display *display)
 			 */
 			if (plane_state->uapi.visible && plane->min_cdclk) {
 				if (crtc_state->double_wide || DISPLAY_VER(display) >= 10)
-					crtc_state->min_cdclk[plane->id] =
+					crtc_state->plane_min_cdclk[plane->id] =
 						DIV_ROUND_UP(crtc_state->pixel_rate, 2);
 				else
-					crtc_state->min_cdclk[plane->id] =
+					crtc_state->plane_min_cdclk[plane->id] =
 						crtc_state->pixel_rate;
 			}
 			drm_dbg_kms(display->drm,
 				    "[PLANE:%d:%s] min_cdclk %d kHz\n",
 				    plane->base.base.id, plane->base.name,
-				    crtc_state->min_cdclk[plane->id]);
+				    crtc_state->plane_min_cdclk[plane->id]);
 		}
 
 		intel_pmdemand_update_port_clock(display, pmdemand_state, pipe,
diff --git a/drivers/gpu/drm/i915/display/intel_plane.c b/drivers/gpu/drm/i915/display/intel_plane.c
index 074de9275951..78329deb395a 100644
--- a/drivers/gpu/drm/i915/display/intel_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_plane.c
@@ -304,7 +304,7 @@ static void intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
 
 	new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
 
-	new_crtc_state->min_cdclk[plane->id] =
+	new_crtc_state->plane_min_cdclk[plane->id] =
 		plane->min_cdclk(new_crtc_state, plane_state);
 }
 
@@ -391,7 +391,7 @@ void intel_plane_set_invisible(struct intel_crtc_state *crtc_state,
 	crtc_state->data_rate_y[plane->id] = 0;
 	crtc_state->rel_data_rate[plane->id] = 0;
 	crtc_state->rel_data_rate_y[plane->id] = 0;
-	crtc_state->min_cdclk[plane->id] = 0;
+	crtc_state->plane_min_cdclk[plane->id] = 0;
 
 	plane_state->uapi.visible = false;
 }
-- 
2.49.1


  parent reply	other threads:[~2025-10-13 20:13 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-13 20:12 [PATCH 0/9] drm/i915: Reorder cdclk stuff for vblank/guardband length checks Ville Syrjala
2025-10-13 20:12 ` [PATCH 1/9] drm/i915/bw: Untangle dbuf bw from the sagv/mem bw stuff Ville Syrjala
2025-10-16 10:39   ` Kahola, Mika
2025-10-13 20:12 ` [PATCH 2/9] drm/i915: s/"not not"/"not"/ Ville Syrjala
2025-10-16 10:41   ` Kahola, Mika
2025-10-13 20:12 ` [PATCH 3/9] drm/i915/bw: Relocate intel_bw_crtc_min_cdclk() Ville Syrjala
2025-10-16 10:43   ` Kahola, Mika
2025-10-13 20:12 ` [PATCH 4/9] drm/i915/ips: Eliminate the cdclk_state stuff from hsw_ips_compute_config() Ville Syrjala
2025-10-16 10:57   ` Kahola, Mika
2025-10-13 20:12 ` [PATCH 5/9] drm/i915/fbc: Decouple FBC from intel_cdclk_atomic_check() Ville Syrjala
2025-10-16 11:40   ` Kahola, Mika
2025-10-13 20:12 ` Ville Syrjala [this message]
2025-10-16 11:44   ` [PATCH 6/9] drm/i915: s/min_cdck[]/plane_min_cdclk[]/ Kahola, Mika
2025-10-13 20:12 ` [PATCH 7/9] drm/i915: Compute per-crtc min_cdclk earlier Ville Syrjala
2025-10-16 11:56   ` Kahola, Mika
2025-10-13 20:12 ` [PATCH 8/9] drm/i915: Include the per-crtc minimum cdclk in the crtc state dump Ville Syrjala
2025-10-16 11:56   ` Kahola, Mika
2025-10-13 20:12 ` [PATCH 9/9] drm/i915: Neuter cdclk_prefill_adjustment() Ville Syrjala
2025-10-16 11:59   ` Kahola, Mika
2025-10-14  0:16 ` ✗ CI.checkpatch: warning for drm/i915: Reorder cdclk stuff for vblank/guardband length checks Patchwork
2025-10-14  0:17 ` ✓ CI.KUnit: success " Patchwork
2025-10-14  0:32 ` ✗ CI.checksparse: warning " Patchwork
2025-10-14  0:58 ` ✓ Xe.CI.BAT: success " Patchwork
2025-10-14  8:53 ` ✗ Xe.CI.Full: failure " Patchwork

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