* [PATCH v3 1/7] drm/xe: Stub out new pagefault layer
2025-10-28 3:58 [PATCH v3 0/7] Pagefault refactor Matthew Brost
@ 2025-10-28 3:58 ` Matthew Brost
2025-10-31 13:33 ` Francois Dugast
2025-10-28 3:58 ` [PATCH v3 2/7] drm/xe: Implement xe_pagefault_init Matthew Brost
` (9 subsequent siblings)
10 siblings, 1 reply; 16+ messages in thread
From: Matthew Brost @ 2025-10-28 3:58 UTC (permalink / raw)
To: intel-xe; +Cc: stuart.summers, francois.dugast
Stub out the new page fault layer and add kernel documentation. This is
intended as a replacement for the GT page fault layer, enabling multiple
producers to hook into a shared page fault consumer interface.
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
drivers/gpu/drm/xe/Makefile | 1 +
drivers/gpu/drm/xe/xe_pagefault.c | 65 +++++++++++
drivers/gpu/drm/xe/xe_pagefault.h | 19 ++++
drivers/gpu/drm/xe/xe_pagefault_types.h | 136 ++++++++++++++++++++++++
4 files changed, 221 insertions(+)
create mode 100644 drivers/gpu/drm/xe/xe_pagefault.c
create mode 100644 drivers/gpu/drm/xe/xe_pagefault.h
create mode 100644 drivers/gpu/drm/xe/xe_pagefault_types.h
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 82c6b3d29676..b35021e5b9eb 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -94,6 +94,7 @@ xe-y += xe_bb.o \
xe_nvm.o \
xe_oa.o \
xe_observation.o \
+ xe_pagefault.o \
xe_pat.o \
xe_pci.o \
xe_pcode.o \
diff --git a/drivers/gpu/drm/xe/xe_pagefault.c b/drivers/gpu/drm/xe/xe_pagefault.c
new file mode 100644
index 000000000000..d509a80cb1f3
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_pagefault.c
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#include "xe_pagefault.h"
+#include "xe_pagefault_types.h"
+
+/**
+ * DOC: Xe page faults
+ *
+ * Xe page faults are handled in two layers. The producer layer interacts with
+ * hardware or firmware to receive and parse faults into struct xe_pagefault,
+ * then forwards them to the consumer. The consumer layer services the faults
+ * (e.g., memory migration, page table updates) and acknowledges the result back
+ * to the producer, which then forwards the results to the hardware or firmware.
+ * The consumer uses a page fault queue sized to absorb all potential faults and
+ * a multi-threaded worker to process them. Multiple producers are supported,
+ * with a single shared consumer.
+ *
+ * xe_pagefault.c implements the consumer layer.
+ */
+
+/**
+ * xe_pagefault_init() - Page fault init
+ * @xe: xe device instance
+ *
+ * Initialize Xe page fault state. Must be done after reading fuses.
+ *
+ * Return: 0 on Success, errno on failure
+ */
+int xe_pagefault_init(struct xe_device *xe)
+{
+ /* TODO - implement */
+ return 0;
+}
+
+/**
+ * xe_pagefault_reset() - Page fault reset for a GT
+ * @xe: xe device instance
+ * @gt: GT being reset
+ *
+ * Reset the Xe page fault state for a GT; that is, squash any pending faults on
+ * the GT.
+ */
+void xe_pagefault_reset(struct xe_device *xe, struct xe_gt *gt)
+{
+ /* TODO - implement */
+}
+
+/**
+ * xe_pagefault_handler() - Page fault handler
+ * @xe: xe device instance
+ * @pf: Page fault
+ *
+ * Sink the page fault to a queue (i.e., a memory buffer) and queue a worker to
+ * service it. Safe to be called from IRQ or process context. Reclaim safe.
+ *
+ * Return: 0 on success, errno on failure
+ */
+int xe_pagefault_handler(struct xe_device *xe, struct xe_pagefault *pf)
+{
+ /* TODO - implement */
+ return 0;
+}
diff --git a/drivers/gpu/drm/xe/xe_pagefault.h b/drivers/gpu/drm/xe/xe_pagefault.h
new file mode 100644
index 000000000000..bd0cdf9ed37f
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_pagefault.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef _XE_PAGEFAULT_H_
+#define _XE_PAGEFAULT_H_
+
+struct xe_device;
+struct xe_gt;
+struct xe_pagefault;
+
+int xe_pagefault_init(struct xe_device *xe);
+
+void xe_pagefault_reset(struct xe_device *xe, struct xe_gt *gt);
+
+int xe_pagefault_handler(struct xe_device *xe, struct xe_pagefault *pf);
+
+#endif
diff --git a/drivers/gpu/drm/xe/xe_pagefault_types.h b/drivers/gpu/drm/xe/xe_pagefault_types.h
new file mode 100644
index 000000000000..d3b516407d60
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_pagefault_types.h
@@ -0,0 +1,136 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef _XE_PAGEFAULT_TYPES_H_
+#define _XE_PAGEFAULT_TYPES_H_
+
+#include <linux/workqueue.h>
+
+struct xe_gt;
+struct xe_pagefault;
+
+/** enum xe_pagefault_access_type - Xe page fault access type */
+enum xe_pagefault_access_type {
+ /** @XE_PAGEFAULT_ACCESS_TYPE_READ: Read access type */
+ XE_PAGEFAULT_ACCESS_TYPE_READ = 0,
+ /** @XE_PAGEFAULT_ACCESS_TYPE_WRITE: Write access type */
+ XE_PAGEFAULT_ACCESS_TYPE_WRITE = 1,
+ /** @XE_PAGEFAULT_ACCESS_TYPE_ATOMIC: Atomic access type */
+ XE_PAGEFAULT_ACCESS_TYPE_ATOMIC = 2,
+};
+
+/** enum xe_pagefault_type - Xe page fault type */
+enum xe_pagefault_type {
+ /** @XE_PAGEFAULT_TYPE_NOT_PRESENT: Not present */
+ XE_PAGEFAULT_TYPE_NOT_PRESENT = 0,
+ /** @XE_PAGEFAULT_TYPE_WRITE_ACCESS_VIOLATION: Write access violation */
+ XE_PAGEFAULT_TYPE_WRITE_ACCESS_VIOLATION = 1,
+ /** @XE_PAGEFAULT_TYPE_ATOMIC_ACCESS_VIOLATION: Atomic access violation */
+ XE_PAGEFAULT_TYPE_ATOMIC_ACCESS_VIOLATION = 2,
+};
+
+/** struct xe_pagefault_ops - Xe pagefault ops (producer) */
+struct xe_pagefault_ops {
+ /**
+ * @ack_fault: Ack fault
+ * @pf: Page fault
+ * @err: Error state of fault
+ *
+ * Page fault producer receives acknowledgment from the consumer and
+ * sends the result to the HW/FW interface.
+ */
+ void (*ack_fault)(struct xe_pagefault *pf, int err);
+};
+
+/**
+ * struct xe_pagefault - Xe page fault
+ *
+ * Generic page fault structure for communication between producer and consumer.
+ * Carefully sized to be 64 bytes. Upon a device page fault, the producer
+ * populates this structure, and the consumer copies it into the page-fault
+ * queue for deferred handling.
+ */
+struct xe_pagefault {
+ /**
+ * @gt: GT of fault
+ */
+ struct xe_gt *gt;
+ /**
+ * @consumer: State for the software handling the fault. Populated by
+ * the producer and may be modified by the consumer to communicate
+ * information back to the producer upon fault acknowledgment.
+ */
+ struct {
+ /** @consumer.page_addr: address of page fault */
+ u64 page_addr;
+ /** @consumer.asid: address space ID */
+ u32 asid;
+ /**
+ * @consumer.access_type: access type, u8 rather than enum to
+ * keep size compact
+ */
+ u8 access_type;
+ /**
+ * @consumer.fault_type: fault type, u8 rather than enum to
+ * keep size compact
+ */
+ u8 fault_type;
+#define XE_PAGEFAULT_LEVEL_NACK 0xff /* Producer indicates nack fault */
+ /** @consumer.fault_level: fault level */
+ u8 fault_level;
+ /** @consumer.engine_class: engine class */
+ u8 engine_class;
+ /** @consumer.engine_instance: engine instance */
+ u8 engine_instance;
+ /** consumer.reserved: reserved bits for future expansion */
+ u8 reserved[7];
+ } consumer;
+ /**
+ * @producer: State for the producer (i.e., HW/FW interface). Populated
+ * by the producer and should not be modified—or even inspected—by the
+ * consumer, except for calling operations.
+ */
+ struct {
+ /** @producer.private: private pointer */
+ void *private;
+ /** @producer.ops: operations */
+ const struct xe_pagefault_ops *ops;
+#define XE_PAGEFAULT_PRODUCER_MSG_LEN_DW 4
+ /**
+ * @producer.msg: page fault message, used by producer in fault
+ * acknowledgment to formulate response to HW/FW interface.
+ * Included in the page-fault message because the producer
+ * typically receives the fault in a context where memory cannot
+ * be allocated (e.g., atomic context or the reclaim path).
+ */
+ u32 msg[XE_PAGEFAULT_PRODUCER_MSG_LEN_DW];
+ } producer;
+};
+
+/**
+ * struct xe_pagefault_queue: Xe pagefault queue (consumer)
+ *
+ * Used to capture all device page faults for deferred processing. Size this
+ * queue to absorb the device’s worst-case number of outstanding faults.
+ */
+struct xe_pagefault_queue {
+ /**
+ * @data: Data in queue containing struct xe_pagefault, protected by
+ * @lock
+ */
+ void *data;
+ /** @size: Size of queue in bytes */
+ u32 size;
+ /** @head: Head pointer in bytes, moved by producer, protected by @lock */
+ u32 head;
+ /** @tail: Tail pointer in bytes, moved by consumer, protected by @lock */
+ u32 tail;
+ /** @lock: protects page fault queue */
+ spinlock_t lock;
+ /** @worker: to process page faults */
+ struct work_struct worker;
+};
+
+#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH v3 1/7] drm/xe: Stub out new pagefault layer
2025-10-28 3:58 ` [PATCH v3 1/7] drm/xe: Stub out new pagefault layer Matthew Brost
@ 2025-10-31 13:33 ` Francois Dugast
2025-10-31 16:41 ` Matthew Brost
0 siblings, 1 reply; 16+ messages in thread
From: Francois Dugast @ 2025-10-31 13:33 UTC (permalink / raw)
To: Matthew Brost; +Cc: intel-xe, stuart.summers
On Mon, Oct 27, 2025 at 08:58:37PM -0700, Matthew Brost wrote:
> Stub out the new page fault layer and add kernel documentation. This is
> intended as a replacement for the GT page fault layer, enabling multiple
> producers to hook into a shared page fault consumer interface.
Nit: this patch and others in the series have been modified since the
previous version, for future revisions please include a brief changelog
in the commit message to help review, thanks.
Francois
>
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> ---
> drivers/gpu/drm/xe/Makefile | 1 +
> drivers/gpu/drm/xe/xe_pagefault.c | 65 +++++++++++
> drivers/gpu/drm/xe/xe_pagefault.h | 19 ++++
> drivers/gpu/drm/xe/xe_pagefault_types.h | 136 ++++++++++++++++++++++++
> 4 files changed, 221 insertions(+)
> create mode 100644 drivers/gpu/drm/xe/xe_pagefault.c
> create mode 100644 drivers/gpu/drm/xe/xe_pagefault.h
> create mode 100644 drivers/gpu/drm/xe/xe_pagefault_types.h
>
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> index 82c6b3d29676..b35021e5b9eb 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -94,6 +94,7 @@ xe-y += xe_bb.o \
> xe_nvm.o \
> xe_oa.o \
> xe_observation.o \
> + xe_pagefault.o \
> xe_pat.o \
> xe_pci.o \
> xe_pcode.o \
> diff --git a/drivers/gpu/drm/xe/xe_pagefault.c b/drivers/gpu/drm/xe/xe_pagefault.c
> new file mode 100644
> index 000000000000..d509a80cb1f3
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_pagefault.c
> @@ -0,0 +1,65 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#include "xe_pagefault.h"
> +#include "xe_pagefault_types.h"
> +
> +/**
> + * DOC: Xe page faults
> + *
> + * Xe page faults are handled in two layers. The producer layer interacts with
> + * hardware or firmware to receive and parse faults into struct xe_pagefault,
> + * then forwards them to the consumer. The consumer layer services the faults
> + * (e.g., memory migration, page table updates) and acknowledges the result back
> + * to the producer, which then forwards the results to the hardware or firmware.
> + * The consumer uses a page fault queue sized to absorb all potential faults and
> + * a multi-threaded worker to process them. Multiple producers are supported,
> + * with a single shared consumer.
> + *
> + * xe_pagefault.c implements the consumer layer.
> + */
> +
> +/**
> + * xe_pagefault_init() - Page fault init
> + * @xe: xe device instance
> + *
> + * Initialize Xe page fault state. Must be done after reading fuses.
> + *
> + * Return: 0 on Success, errno on failure
> + */
> +int xe_pagefault_init(struct xe_device *xe)
> +{
> + /* TODO - implement */
> + return 0;
> +}
> +
> +/**
> + * xe_pagefault_reset() - Page fault reset for a GT
> + * @xe: xe device instance
> + * @gt: GT being reset
> + *
> + * Reset the Xe page fault state for a GT; that is, squash any pending faults on
> + * the GT.
> + */
> +void xe_pagefault_reset(struct xe_device *xe, struct xe_gt *gt)
> +{
> + /* TODO - implement */
> +}
> +
> +/**
> + * xe_pagefault_handler() - Page fault handler
> + * @xe: xe device instance
> + * @pf: Page fault
> + *
> + * Sink the page fault to a queue (i.e., a memory buffer) and queue a worker to
> + * service it. Safe to be called from IRQ or process context. Reclaim safe.
> + *
> + * Return: 0 on success, errno on failure
> + */
> +int xe_pagefault_handler(struct xe_device *xe, struct xe_pagefault *pf)
> +{
> + /* TODO - implement */
> + return 0;
> +}
> diff --git a/drivers/gpu/drm/xe/xe_pagefault.h b/drivers/gpu/drm/xe/xe_pagefault.h
> new file mode 100644
> index 000000000000..bd0cdf9ed37f
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_pagefault.h
> @@ -0,0 +1,19 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#ifndef _XE_PAGEFAULT_H_
> +#define _XE_PAGEFAULT_H_
> +
> +struct xe_device;
> +struct xe_gt;
> +struct xe_pagefault;
> +
> +int xe_pagefault_init(struct xe_device *xe);
> +
> +void xe_pagefault_reset(struct xe_device *xe, struct xe_gt *gt);
> +
> +int xe_pagefault_handler(struct xe_device *xe, struct xe_pagefault *pf);
> +
> +#endif
> diff --git a/drivers/gpu/drm/xe/xe_pagefault_types.h b/drivers/gpu/drm/xe/xe_pagefault_types.h
> new file mode 100644
> index 000000000000..d3b516407d60
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_pagefault_types.h
> @@ -0,0 +1,136 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#ifndef _XE_PAGEFAULT_TYPES_H_
> +#define _XE_PAGEFAULT_TYPES_H_
> +
> +#include <linux/workqueue.h>
> +
> +struct xe_gt;
> +struct xe_pagefault;
> +
> +/** enum xe_pagefault_access_type - Xe page fault access type */
> +enum xe_pagefault_access_type {
> + /** @XE_PAGEFAULT_ACCESS_TYPE_READ: Read access type */
> + XE_PAGEFAULT_ACCESS_TYPE_READ = 0,
> + /** @XE_PAGEFAULT_ACCESS_TYPE_WRITE: Write access type */
> + XE_PAGEFAULT_ACCESS_TYPE_WRITE = 1,
> + /** @XE_PAGEFAULT_ACCESS_TYPE_ATOMIC: Atomic access type */
> + XE_PAGEFAULT_ACCESS_TYPE_ATOMIC = 2,
> +};
> +
> +/** enum xe_pagefault_type - Xe page fault type */
> +enum xe_pagefault_type {
> + /** @XE_PAGEFAULT_TYPE_NOT_PRESENT: Not present */
> + XE_PAGEFAULT_TYPE_NOT_PRESENT = 0,
> + /** @XE_PAGEFAULT_TYPE_WRITE_ACCESS_VIOLATION: Write access violation */
> + XE_PAGEFAULT_TYPE_WRITE_ACCESS_VIOLATION = 1,
> + /** @XE_PAGEFAULT_TYPE_ATOMIC_ACCESS_VIOLATION: Atomic access violation */
> + XE_PAGEFAULT_TYPE_ATOMIC_ACCESS_VIOLATION = 2,
> +};
> +
> +/** struct xe_pagefault_ops - Xe pagefault ops (producer) */
> +struct xe_pagefault_ops {
> + /**
> + * @ack_fault: Ack fault
> + * @pf: Page fault
> + * @err: Error state of fault
> + *
> + * Page fault producer receives acknowledgment from the consumer and
> + * sends the result to the HW/FW interface.
> + */
> + void (*ack_fault)(struct xe_pagefault *pf, int err);
> +};
> +
> +/**
> + * struct xe_pagefault - Xe page fault
> + *
> + * Generic page fault structure for communication between producer and consumer.
> + * Carefully sized to be 64 bytes. Upon a device page fault, the producer
> + * populates this structure, and the consumer copies it into the page-fault
> + * queue for deferred handling.
> + */
> +struct xe_pagefault {
> + /**
> + * @gt: GT of fault
> + */
> + struct xe_gt *gt;
> + /**
> + * @consumer: State for the software handling the fault. Populated by
> + * the producer and may be modified by the consumer to communicate
> + * information back to the producer upon fault acknowledgment.
> + */
> + struct {
> + /** @consumer.page_addr: address of page fault */
> + u64 page_addr;
> + /** @consumer.asid: address space ID */
> + u32 asid;
> + /**
> + * @consumer.access_type: access type, u8 rather than enum to
> + * keep size compact
> + */
> + u8 access_type;
> + /**
> + * @consumer.fault_type: fault type, u8 rather than enum to
> + * keep size compact
> + */
> + u8 fault_type;
> +#define XE_PAGEFAULT_LEVEL_NACK 0xff /* Producer indicates nack fault */
> + /** @consumer.fault_level: fault level */
> + u8 fault_level;
> + /** @consumer.engine_class: engine class */
> + u8 engine_class;
> + /** @consumer.engine_instance: engine instance */
> + u8 engine_instance;
> + /** consumer.reserved: reserved bits for future expansion */
> + u8 reserved[7];
> + } consumer;
> + /**
> + * @producer: State for the producer (i.e., HW/FW interface). Populated
> + * by the producer and should not be modified—or even inspected—by the
> + * consumer, except for calling operations.
> + */
> + struct {
> + /** @producer.private: private pointer */
> + void *private;
> + /** @producer.ops: operations */
> + const struct xe_pagefault_ops *ops;
> +#define XE_PAGEFAULT_PRODUCER_MSG_LEN_DW 4
> + /**
> + * @producer.msg: page fault message, used by producer in fault
> + * acknowledgment to formulate response to HW/FW interface.
> + * Included in the page-fault message because the producer
> + * typically receives the fault in a context where memory cannot
> + * be allocated (e.g., atomic context or the reclaim path).
> + */
> + u32 msg[XE_PAGEFAULT_PRODUCER_MSG_LEN_DW];
> + } producer;
> +};
> +
> +/**
> + * struct xe_pagefault_queue: Xe pagefault queue (consumer)
> + *
> + * Used to capture all device page faults for deferred processing. Size this
> + * queue to absorb the device’s worst-case number of outstanding faults.
> + */
> +struct xe_pagefault_queue {
> + /**
> + * @data: Data in queue containing struct xe_pagefault, protected by
> + * @lock
> + */
> + void *data;
> + /** @size: Size of queue in bytes */
> + u32 size;
> + /** @head: Head pointer in bytes, moved by producer, protected by @lock */
> + u32 head;
> + /** @tail: Tail pointer in bytes, moved by consumer, protected by @lock */
> + u32 tail;
> + /** @lock: protects page fault queue */
> + spinlock_t lock;
> + /** @worker: to process page faults */
> + struct work_struct worker;
> +};
> +
> +#endif
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH v3 1/7] drm/xe: Stub out new pagefault layer
2025-10-31 13:33 ` Francois Dugast
@ 2025-10-31 16:41 ` Matthew Brost
0 siblings, 0 replies; 16+ messages in thread
From: Matthew Brost @ 2025-10-31 16:41 UTC (permalink / raw)
To: Francois Dugast; +Cc: intel-xe, stuart.summers
On Fri, Oct 31, 2025 at 02:33:02PM +0100, Francois Dugast wrote:
> On Mon, Oct 27, 2025 at 08:58:37PM -0700, Matthew Brost wrote:
> > Stub out the new page fault layer and add kernel documentation. This is
> > intended as a replacement for the GT page fault layer, enabling multiple
> > producers to hook into a shared page fault consumer interface.
>
> Nit: this patch and others in the series have been modified since the
> previous version, for future revisions please include a brief changelog
> in the commit message to help review, thanks.
>
Yea, I had change logs but somehow lost them...
Will try to bring them back in v4.
Matt
> Francois
>
> >
> > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > ---
> > drivers/gpu/drm/xe/Makefile | 1 +
> > drivers/gpu/drm/xe/xe_pagefault.c | 65 +++++++++++
> > drivers/gpu/drm/xe/xe_pagefault.h | 19 ++++
> > drivers/gpu/drm/xe/xe_pagefault_types.h | 136 ++++++++++++++++++++++++
> > 4 files changed, 221 insertions(+)
> > create mode 100644 drivers/gpu/drm/xe/xe_pagefault.c
> > create mode 100644 drivers/gpu/drm/xe/xe_pagefault.h
> > create mode 100644 drivers/gpu/drm/xe/xe_pagefault_types.h
> >
> > diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> > index 82c6b3d29676..b35021e5b9eb 100644
> > --- a/drivers/gpu/drm/xe/Makefile
> > +++ b/drivers/gpu/drm/xe/Makefile
> > @@ -94,6 +94,7 @@ xe-y += xe_bb.o \
> > xe_nvm.o \
> > xe_oa.o \
> > xe_observation.o \
> > + xe_pagefault.o \
> > xe_pat.o \
> > xe_pci.o \
> > xe_pcode.o \
> > diff --git a/drivers/gpu/drm/xe/xe_pagefault.c b/drivers/gpu/drm/xe/xe_pagefault.c
> > new file mode 100644
> > index 000000000000..d509a80cb1f3
> > --- /dev/null
> > +++ b/drivers/gpu/drm/xe/xe_pagefault.c
> > @@ -0,0 +1,65 @@
> > +// SPDX-License-Identifier: MIT
> > +/*
> > + * Copyright © 2025 Intel Corporation
> > + */
> > +
> > +#include "xe_pagefault.h"
> > +#include "xe_pagefault_types.h"
> > +
> > +/**
> > + * DOC: Xe page faults
> > + *
> > + * Xe page faults are handled in two layers. The producer layer interacts with
> > + * hardware or firmware to receive and parse faults into struct xe_pagefault,
> > + * then forwards them to the consumer. The consumer layer services the faults
> > + * (e.g., memory migration, page table updates) and acknowledges the result back
> > + * to the producer, which then forwards the results to the hardware or firmware.
> > + * The consumer uses a page fault queue sized to absorb all potential faults and
> > + * a multi-threaded worker to process them. Multiple producers are supported,
> > + * with a single shared consumer.
> > + *
> > + * xe_pagefault.c implements the consumer layer.
> > + */
> > +
> > +/**
> > + * xe_pagefault_init() - Page fault init
> > + * @xe: xe device instance
> > + *
> > + * Initialize Xe page fault state. Must be done after reading fuses.
> > + *
> > + * Return: 0 on Success, errno on failure
> > + */
> > +int xe_pagefault_init(struct xe_device *xe)
> > +{
> > + /* TODO - implement */
> > + return 0;
> > +}
> > +
> > +/**
> > + * xe_pagefault_reset() - Page fault reset for a GT
> > + * @xe: xe device instance
> > + * @gt: GT being reset
> > + *
> > + * Reset the Xe page fault state for a GT; that is, squash any pending faults on
> > + * the GT.
> > + */
> > +void xe_pagefault_reset(struct xe_device *xe, struct xe_gt *gt)
> > +{
> > + /* TODO - implement */
> > +}
> > +
> > +/**
> > + * xe_pagefault_handler() - Page fault handler
> > + * @xe: xe device instance
> > + * @pf: Page fault
> > + *
> > + * Sink the page fault to a queue (i.e., a memory buffer) and queue a worker to
> > + * service it. Safe to be called from IRQ or process context. Reclaim safe.
> > + *
> > + * Return: 0 on success, errno on failure
> > + */
> > +int xe_pagefault_handler(struct xe_device *xe, struct xe_pagefault *pf)
> > +{
> > + /* TODO - implement */
> > + return 0;
> > +}
> > diff --git a/drivers/gpu/drm/xe/xe_pagefault.h b/drivers/gpu/drm/xe/xe_pagefault.h
> > new file mode 100644
> > index 000000000000..bd0cdf9ed37f
> > --- /dev/null
> > +++ b/drivers/gpu/drm/xe/xe_pagefault.h
> > @@ -0,0 +1,19 @@
> > +/* SPDX-License-Identifier: MIT */
> > +/*
> > + * Copyright © 2025 Intel Corporation
> > + */
> > +
> > +#ifndef _XE_PAGEFAULT_H_
> > +#define _XE_PAGEFAULT_H_
> > +
> > +struct xe_device;
> > +struct xe_gt;
> > +struct xe_pagefault;
> > +
> > +int xe_pagefault_init(struct xe_device *xe);
> > +
> > +void xe_pagefault_reset(struct xe_device *xe, struct xe_gt *gt);
> > +
> > +int xe_pagefault_handler(struct xe_device *xe, struct xe_pagefault *pf);
> > +
> > +#endif
> > diff --git a/drivers/gpu/drm/xe/xe_pagefault_types.h b/drivers/gpu/drm/xe/xe_pagefault_types.h
> > new file mode 100644
> > index 000000000000..d3b516407d60
> > --- /dev/null
> > +++ b/drivers/gpu/drm/xe/xe_pagefault_types.h
> > @@ -0,0 +1,136 @@
> > +/* SPDX-License-Identifier: MIT */
> > +/*
> > + * Copyright © 2025 Intel Corporation
> > + */
> > +
> > +#ifndef _XE_PAGEFAULT_TYPES_H_
> > +#define _XE_PAGEFAULT_TYPES_H_
> > +
> > +#include <linux/workqueue.h>
> > +
> > +struct xe_gt;
> > +struct xe_pagefault;
> > +
> > +/** enum xe_pagefault_access_type - Xe page fault access type */
> > +enum xe_pagefault_access_type {
> > + /** @XE_PAGEFAULT_ACCESS_TYPE_READ: Read access type */
> > + XE_PAGEFAULT_ACCESS_TYPE_READ = 0,
> > + /** @XE_PAGEFAULT_ACCESS_TYPE_WRITE: Write access type */
> > + XE_PAGEFAULT_ACCESS_TYPE_WRITE = 1,
> > + /** @XE_PAGEFAULT_ACCESS_TYPE_ATOMIC: Atomic access type */
> > + XE_PAGEFAULT_ACCESS_TYPE_ATOMIC = 2,
> > +};
> > +
> > +/** enum xe_pagefault_type - Xe page fault type */
> > +enum xe_pagefault_type {
> > + /** @XE_PAGEFAULT_TYPE_NOT_PRESENT: Not present */
> > + XE_PAGEFAULT_TYPE_NOT_PRESENT = 0,
> > + /** @XE_PAGEFAULT_TYPE_WRITE_ACCESS_VIOLATION: Write access violation */
> > + XE_PAGEFAULT_TYPE_WRITE_ACCESS_VIOLATION = 1,
> > + /** @XE_PAGEFAULT_TYPE_ATOMIC_ACCESS_VIOLATION: Atomic access violation */
> > + XE_PAGEFAULT_TYPE_ATOMIC_ACCESS_VIOLATION = 2,
> > +};
> > +
> > +/** struct xe_pagefault_ops - Xe pagefault ops (producer) */
> > +struct xe_pagefault_ops {
> > + /**
> > + * @ack_fault: Ack fault
> > + * @pf: Page fault
> > + * @err: Error state of fault
> > + *
> > + * Page fault producer receives acknowledgment from the consumer and
> > + * sends the result to the HW/FW interface.
> > + */
> > + void (*ack_fault)(struct xe_pagefault *pf, int err);
> > +};
> > +
> > +/**
> > + * struct xe_pagefault - Xe page fault
> > + *
> > + * Generic page fault structure for communication between producer and consumer.
> > + * Carefully sized to be 64 bytes. Upon a device page fault, the producer
> > + * populates this structure, and the consumer copies it into the page-fault
> > + * queue for deferred handling.
> > + */
> > +struct xe_pagefault {
> > + /**
> > + * @gt: GT of fault
> > + */
> > + struct xe_gt *gt;
> > + /**
> > + * @consumer: State for the software handling the fault. Populated by
> > + * the producer and may be modified by the consumer to communicate
> > + * information back to the producer upon fault acknowledgment.
> > + */
> > + struct {
> > + /** @consumer.page_addr: address of page fault */
> > + u64 page_addr;
> > + /** @consumer.asid: address space ID */
> > + u32 asid;
> > + /**
> > + * @consumer.access_type: access type, u8 rather than enum to
> > + * keep size compact
> > + */
> > + u8 access_type;
> > + /**
> > + * @consumer.fault_type: fault type, u8 rather than enum to
> > + * keep size compact
> > + */
> > + u8 fault_type;
> > +#define XE_PAGEFAULT_LEVEL_NACK 0xff /* Producer indicates nack fault */
> > + /** @consumer.fault_level: fault level */
> > + u8 fault_level;
> > + /** @consumer.engine_class: engine class */
> > + u8 engine_class;
> > + /** @consumer.engine_instance: engine instance */
> > + u8 engine_instance;
> > + /** consumer.reserved: reserved bits for future expansion */
> > + u8 reserved[7];
> > + } consumer;
> > + /**
> > + * @producer: State for the producer (i.e., HW/FW interface). Populated
> > + * by the producer and should not be modified—or even inspected—by the
> > + * consumer, except for calling operations.
> > + */
> > + struct {
> > + /** @producer.private: private pointer */
> > + void *private;
> > + /** @producer.ops: operations */
> > + const struct xe_pagefault_ops *ops;
> > +#define XE_PAGEFAULT_PRODUCER_MSG_LEN_DW 4
> > + /**
> > + * @producer.msg: page fault message, used by producer in fault
> > + * acknowledgment to formulate response to HW/FW interface.
> > + * Included in the page-fault message because the producer
> > + * typically receives the fault in a context where memory cannot
> > + * be allocated (e.g., atomic context or the reclaim path).
> > + */
> > + u32 msg[XE_PAGEFAULT_PRODUCER_MSG_LEN_DW];
> > + } producer;
> > +};
> > +
> > +/**
> > + * struct xe_pagefault_queue: Xe pagefault queue (consumer)
> > + *
> > + * Used to capture all device page faults for deferred processing. Size this
> > + * queue to absorb the device’s worst-case number of outstanding faults.
> > + */
> > +struct xe_pagefault_queue {
> > + /**
> > + * @data: Data in queue containing struct xe_pagefault, protected by
> > + * @lock
> > + */
> > + void *data;
> > + /** @size: Size of queue in bytes */
> > + u32 size;
> > + /** @head: Head pointer in bytes, moved by producer, protected by @lock */
> > + u32 head;
> > + /** @tail: Tail pointer in bytes, moved by consumer, protected by @lock */
> > + u32 tail;
> > + /** @lock: protects page fault queue */
> > + spinlock_t lock;
> > + /** @worker: to process page faults */
> > + struct work_struct worker;
> > +};
> > +
> > +#endif
> > --
> > 2.34.1
> >
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 2/7] drm/xe: Implement xe_pagefault_init
2025-10-28 3:58 [PATCH v3 0/7] Pagefault refactor Matthew Brost
2025-10-28 3:58 ` [PATCH v3 1/7] drm/xe: Stub out new pagefault layer Matthew Brost
@ 2025-10-28 3:58 ` Matthew Brost
2025-10-31 13:40 ` Francois Dugast
2025-10-28 3:58 ` [PATCH v3 3/7] drm/xe: Implement xe_pagefault_reset Matthew Brost
` (8 subsequent siblings)
10 siblings, 1 reply; 16+ messages in thread
From: Matthew Brost @ 2025-10-28 3:58 UTC (permalink / raw)
To: intel-xe; +Cc: stuart.summers, francois.dugast
Create pagefault queues and initialize them.
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
drivers/gpu/drm/xe/xe_device.c | 5 ++
drivers/gpu/drm/xe/xe_device_types.h | 11 ++++
drivers/gpu/drm/xe/xe_pagefault.c | 93 +++++++++++++++++++++++++++-
3 files changed, 107 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index 47f5391ad8e9..c17813c469fd 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -52,6 +52,7 @@
#include "xe_nvm.h"
#include "xe_oa.h"
#include "xe_observation.h"
+#include "xe_pagefault.h"
#include "xe_pat.h"
#include "xe_pcode.h"
#include "xe_pm.h"
@@ -890,6 +891,10 @@ int xe_device_probe(struct xe_device *xe)
if (err)
return err;
+ err = xe_pagefault_init(xe);
+ if (err)
+ return err;
+
for_each_gt(gt, xe, id) {
err = xe_gt_init(gt);
if (err)
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index af0ce275b032..7baf15f51575 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -18,6 +18,7 @@
#include "xe_lmtt_types.h"
#include "xe_memirq_types.h"
#include "xe_oa_types.h"
+#include "xe_pagefault_types.h"
#include "xe_platform_types.h"
#include "xe_pmu_types.h"
#include "xe_pt_types.h"
@@ -418,6 +419,16 @@ struct xe_device {
u32 next_asid;
/** @usm.lock: protects UM state */
struct rw_semaphore lock;
+ /** @usm.pf_wq: page fault work queue, unbound, high priority */
+ struct workqueue_struct *pf_wq;
+ /*
+ * We pick 4 here because, in the current implementation, it
+ * yields the best bandwidth utilization of the kernel paging
+ * engine.
+ */
+#define XE_PAGEFAULT_QUEUE_COUNT 4
+ /** @usm.pf_queue: Page fault queues */
+ struct xe_pagefault_queue pf_queue[XE_PAGEFAULT_QUEUE_COUNT];
} usm;
/** @pinned: pinned BO state */
diff --git a/drivers/gpu/drm/xe/xe_pagefault.c b/drivers/gpu/drm/xe/xe_pagefault.c
index d509a80cb1f3..43b26e7d090a 100644
--- a/drivers/gpu/drm/xe/xe_pagefault.c
+++ b/drivers/gpu/drm/xe/xe_pagefault.c
@@ -3,6 +3,10 @@
* Copyright © 2025 Intel Corporation
*/
+#include <drm/drm_managed.h>
+
+#include "xe_device.h"
+#include "xe_gt_types.h"
#include "xe_pagefault.h"
#include "xe_pagefault_types.h"
@@ -21,6 +25,71 @@
* xe_pagefault.c implements the consumer layer.
*/
+static int xe_pagefault_entry_size(void)
+{
+ return roundup_pow_of_two(sizeof(struct xe_pagefault));
+}
+
+static void xe_pagefault_queue_work(struct work_struct *w)
+{
+ /* TODO: Implement */
+}
+
+static int xe_pagefault_queue_init(struct xe_device *xe,
+ struct xe_pagefault_queue *pf_queue)
+{
+ struct xe_gt *gt;
+ int total_num_eus = 0;
+ u8 id;
+
+ for_each_gt(gt, xe, id) {
+ xe_dss_mask_t all_dss;
+ int num_dss, num_eus;
+
+ bitmap_or(all_dss, gt->fuse_topo.g_dss_mask,
+ gt->fuse_topo.c_dss_mask, XE_MAX_DSS_FUSE_BITS);
+
+ num_dss = bitmap_weight(all_dss, XE_MAX_DSS_FUSE_BITS);
+ num_eus = bitmap_weight(gt->fuse_topo.eu_mask_per_dss,
+ XE_MAX_EU_FUSE_BITS) * num_dss;
+
+ total_num_eus += num_eus;
+ }
+
+ xe_assert(xe, total_num_eus);
+
+ /*
+ * user can issue separate page faults per EU and per CS
+ *
+ * XXX: Multiplier required as compute UMD are getting PF queue errors
+ * without it. Follow on why this multiplier is required.
+ */
+#define PF_MULTIPLIER 8
+ pf_queue->size = (total_num_eus + XE_NUM_HW_ENGINES) *
+ xe_pagefault_entry_size() * PF_MULTIPLIER;
+ pf_queue->size = roundup_pow_of_two(pf_queue->size);
+#undef PF_MULTIPLIER
+
+ drm_dbg(&xe->drm, "xe_pagefault_entry_size=%d, total_num_eus=%d, pf_queue->size=%u",
+ xe_pagefault_entry_size(), total_num_eus, pf_queue->size);
+
+ spin_lock_init(&pf_queue->lock);
+ INIT_WORK(&pf_queue->worker, xe_pagefault_queue_work);
+
+ pf_queue->data = drmm_kzalloc(&xe->drm, pf_queue->size, GFP_KERNEL);
+ if (!pf_queue->data)
+ return -ENOMEM;
+
+ return 0;
+}
+
+static void xe_pagefault_fini(void *arg)
+{
+ struct xe_device *xe = arg;
+
+ destroy_workqueue(xe->usm.pf_wq);
+}
+
/**
* xe_pagefault_init() - Page fault init
* @xe: xe device instance
@@ -31,8 +100,28 @@
*/
int xe_pagefault_init(struct xe_device *xe)
{
- /* TODO - implement */
- return 0;
+ int err, i;
+
+ if (!xe->info.has_usm)
+ return 0;
+
+ xe->usm.pf_wq = alloc_workqueue("xe_page_fault_work_queue",
+ WQ_UNBOUND | WQ_HIGHPRI,
+ XE_PAGEFAULT_QUEUE_COUNT);
+ if (!xe->usm.pf_wq)
+ return -ENOMEM;
+
+ for (i = 0; i < XE_PAGEFAULT_QUEUE_COUNT; ++i) {
+ err = xe_pagefault_queue_init(xe, xe->usm.pf_queue + i);
+ if (err)
+ goto err_out;
+ }
+
+ return devm_add_action_or_reset(xe->drm.dev, xe_pagefault_fini, xe);
+
+err_out:
+ destroy_workqueue(xe->usm.pf_wq);
+ return err;
}
/**
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH v3 2/7] drm/xe: Implement xe_pagefault_init
2025-10-28 3:58 ` [PATCH v3 2/7] drm/xe: Implement xe_pagefault_init Matthew Brost
@ 2025-10-31 13:40 ` Francois Dugast
2025-10-31 16:40 ` Matthew Brost
0 siblings, 1 reply; 16+ messages in thread
From: Francois Dugast @ 2025-10-31 13:40 UTC (permalink / raw)
To: Matthew Brost; +Cc: intel-xe, stuart.summers
On Mon, Oct 27, 2025 at 08:58:38PM -0700, Matthew Brost wrote:
> Create pagefault queues and initialize them.
>
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> ---
> drivers/gpu/drm/xe/xe_device.c | 5 ++
> drivers/gpu/drm/xe/xe_device_types.h | 11 ++++
> drivers/gpu/drm/xe/xe_pagefault.c | 93 +++++++++++++++++++++++++++-
> 3 files changed, 107 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
> index 47f5391ad8e9..c17813c469fd 100644
> --- a/drivers/gpu/drm/xe/xe_device.c
> +++ b/drivers/gpu/drm/xe/xe_device.c
> @@ -52,6 +52,7 @@
> #include "xe_nvm.h"
> #include "xe_oa.h"
> #include "xe_observation.h"
> +#include "xe_pagefault.h"
> #include "xe_pat.h"
> #include "xe_pcode.h"
> #include "xe_pm.h"
> @@ -890,6 +891,10 @@ int xe_device_probe(struct xe_device *xe)
> if (err)
> return err;
>
> + err = xe_pagefault_init(xe);
> + if (err)
> + return err;
> +
It seems these lines ^...
> for_each_gt(gt, xe, id) {
> err = xe_gt_init(gt);
> if (err)
... should come after those ^ otherwise the number of EUs in
xe_pagefault_queue_init is incorrect.
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index af0ce275b032..7baf15f51575 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -18,6 +18,7 @@
> #include "xe_lmtt_types.h"
> #include "xe_memirq_types.h"
> #include "xe_oa_types.h"
> +#include "xe_pagefault_types.h"
> #include "xe_platform_types.h"
> #include "xe_pmu_types.h"
> #include "xe_pt_types.h"
> @@ -418,6 +419,16 @@ struct xe_device {
> u32 next_asid;
> /** @usm.lock: protects UM state */
> struct rw_semaphore lock;
> + /** @usm.pf_wq: page fault work queue, unbound, high priority */
> + struct workqueue_struct *pf_wq;
> + /*
> + * We pick 4 here because, in the current implementation, it
> + * yields the best bandwidth utilization of the kernel paging
> + * engine.
> + */
> +#define XE_PAGEFAULT_QUEUE_COUNT 4
> + /** @usm.pf_queue: Page fault queues */
> + struct xe_pagefault_queue pf_queue[XE_PAGEFAULT_QUEUE_COUNT];
> } usm;
>
> /** @pinned: pinned BO state */
> diff --git a/drivers/gpu/drm/xe/xe_pagefault.c b/drivers/gpu/drm/xe/xe_pagefault.c
> index d509a80cb1f3..43b26e7d090a 100644
> --- a/drivers/gpu/drm/xe/xe_pagefault.c
> +++ b/drivers/gpu/drm/xe/xe_pagefault.c
> @@ -3,6 +3,10 @@
> * Copyright © 2025 Intel Corporation
> */
>
> +#include <drm/drm_managed.h>
> +
> +#include "xe_device.h"
> +#include "xe_gt_types.h"
> #include "xe_pagefault.h"
> #include "xe_pagefault_types.h"
>
> @@ -21,6 +25,71 @@
> * xe_pagefault.c implements the consumer layer.
> */
>
> +static int xe_pagefault_entry_size(void)
> +{
> + return roundup_pow_of_two(sizeof(struct xe_pagefault));
> +}
> +
> +static void xe_pagefault_queue_work(struct work_struct *w)
> +{
> + /* TODO: Implement */
> +}
> +
> +static int xe_pagefault_queue_init(struct xe_device *xe,
> + struct xe_pagefault_queue *pf_queue)
> +{
> + struct xe_gt *gt;
> + int total_num_eus = 0;
> + u8 id;
> +
> + for_each_gt(gt, xe, id) {
> + xe_dss_mask_t all_dss;
> + int num_dss, num_eus;
> +
> + bitmap_or(all_dss, gt->fuse_topo.g_dss_mask,
> + gt->fuse_topo.c_dss_mask, XE_MAX_DSS_FUSE_BITS);
> +
> + num_dss = bitmap_weight(all_dss, XE_MAX_DSS_FUSE_BITS);
> + num_eus = bitmap_weight(gt->fuse_topo.eu_mask_per_dss,
> + XE_MAX_EU_FUSE_BITS) * num_dss;
> +
> + total_num_eus += num_eus;
> + }
> +
> + xe_assert(xe, total_num_eus);
> +
> + /*
> + * user can issue separate page faults per EU and per CS
> + *
> + * XXX: Multiplier required as compute UMD are getting PF queue errors
> + * without it. Follow on why this multiplier is required.
> + */
> +#define PF_MULTIPLIER 8
> + pf_queue->size = (total_num_eus + XE_NUM_HW_ENGINES) *
> + xe_pagefault_entry_size() * PF_MULTIPLIER;
> + pf_queue->size = roundup_pow_of_two(pf_queue->size);
> +#undef PF_MULTIPLIER
> +
> + drm_dbg(&xe->drm, "xe_pagefault_entry_size=%d, total_num_eus=%d, pf_queue->size=%u",
> + xe_pagefault_entry_size(), total_num_eus, pf_queue->size);
> +
> + spin_lock_init(&pf_queue->lock);
> + INIT_WORK(&pf_queue->worker, xe_pagefault_queue_work);
These 2 lines ^...
> +
> + pf_queue->data = drmm_kzalloc(&xe->drm, pf_queue->size, GFP_KERNEL);
> + if (!pf_queue->data)
> + return -ENOMEM;
... and those 3 lines were swapped since last revision. It is probably
too early for pf_queue to be used here anyway but was there a reason for
changing the order?
Francois
> +
> + return 0;
> +}
> +
> +static void xe_pagefault_fini(void *arg)
> +{
> + struct xe_device *xe = arg;
> +
> + destroy_workqueue(xe->usm.pf_wq);
> +}
> +
> /**
> * xe_pagefault_init() - Page fault init
> * @xe: xe device instance
> @@ -31,8 +100,28 @@
> */
> int xe_pagefault_init(struct xe_device *xe)
> {
> - /* TODO - implement */
> - return 0;
> + int err, i;
> +
> + if (!xe->info.has_usm)
> + return 0;
> +
> + xe->usm.pf_wq = alloc_workqueue("xe_page_fault_work_queue",
> + WQ_UNBOUND | WQ_HIGHPRI,
> + XE_PAGEFAULT_QUEUE_COUNT);
> + if (!xe->usm.pf_wq)
> + return -ENOMEM;
> +
> + for (i = 0; i < XE_PAGEFAULT_QUEUE_COUNT; ++i) {
> + err = xe_pagefault_queue_init(xe, xe->usm.pf_queue + i);
> + if (err)
> + goto err_out;
> + }
> +
> + return devm_add_action_or_reset(xe->drm.dev, xe_pagefault_fini, xe);
> +
> +err_out:
> + destroy_workqueue(xe->usm.pf_wq);
> + return err;
> }
>
> /**
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH v3 2/7] drm/xe: Implement xe_pagefault_init
2025-10-31 13:40 ` Francois Dugast
@ 2025-10-31 16:40 ` Matthew Brost
0 siblings, 0 replies; 16+ messages in thread
From: Matthew Brost @ 2025-10-31 16:40 UTC (permalink / raw)
To: Francois Dugast; +Cc: intel-xe, stuart.summers
On Fri, Oct 31, 2025 at 02:40:21PM +0100, Francois Dugast wrote:
> On Mon, Oct 27, 2025 at 08:58:38PM -0700, Matthew Brost wrote:
> > Create pagefault queues and initialize them.
> >
> > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > ---
> > drivers/gpu/drm/xe/xe_device.c | 5 ++
> > drivers/gpu/drm/xe/xe_device_types.h | 11 ++++
> > drivers/gpu/drm/xe/xe_pagefault.c | 93 +++++++++++++++++++++++++++-
> > 3 files changed, 107 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
> > index 47f5391ad8e9..c17813c469fd 100644
> > --- a/drivers/gpu/drm/xe/xe_device.c
> > +++ b/drivers/gpu/drm/xe/xe_device.c
> > @@ -52,6 +52,7 @@
> > #include "xe_nvm.h"
> > #include "xe_oa.h"
> > #include "xe_observation.h"
> > +#include "xe_pagefault.h"
> > #include "xe_pat.h"
> > #include "xe_pcode.h"
> > #include "xe_pm.h"
> > @@ -890,6 +891,10 @@ int xe_device_probe(struct xe_device *xe)
> > if (err)
> > return err;
> >
> > + err = xe_pagefault_init(xe);
> > + if (err)
> > + return err;
> > +
>
> It seems these lines ^...
>
> > for_each_gt(gt, xe, id) {
> > err = xe_gt_init(gt);
> > if (err)
>
>
> ... should come after those ^ otherwise the number of EUs in
> xe_pagefault_queue_init is incorrect.
>
Yea, this version is busted.
> > diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> > index af0ce275b032..7baf15f51575 100644
> > --- a/drivers/gpu/drm/xe/xe_device_types.h
> > +++ b/drivers/gpu/drm/xe/xe_device_types.h
> > @@ -18,6 +18,7 @@
> > #include "xe_lmtt_types.h"
> > #include "xe_memirq_types.h"
> > #include "xe_oa_types.h"
> > +#include "xe_pagefault_types.h"
> > #include "xe_platform_types.h"
> > #include "xe_pmu_types.h"
> > #include "xe_pt_types.h"
> > @@ -418,6 +419,16 @@ struct xe_device {
> > u32 next_asid;
> > /** @usm.lock: protects UM state */
> > struct rw_semaphore lock;
> > + /** @usm.pf_wq: page fault work queue, unbound, high priority */
> > + struct workqueue_struct *pf_wq;
> > + /*
> > + * We pick 4 here because, in the current implementation, it
> > + * yields the best bandwidth utilization of the kernel paging
> > + * engine.
> > + */
> > +#define XE_PAGEFAULT_QUEUE_COUNT 4
> > + /** @usm.pf_queue: Page fault queues */
> > + struct xe_pagefault_queue pf_queue[XE_PAGEFAULT_QUEUE_COUNT];
> > } usm;
> >
> > /** @pinned: pinned BO state */
> > diff --git a/drivers/gpu/drm/xe/xe_pagefault.c b/drivers/gpu/drm/xe/xe_pagefault.c
> > index d509a80cb1f3..43b26e7d090a 100644
> > --- a/drivers/gpu/drm/xe/xe_pagefault.c
> > +++ b/drivers/gpu/drm/xe/xe_pagefault.c
> > @@ -3,6 +3,10 @@
> > * Copyright © 2025 Intel Corporation
> > */
> >
> > +#include <drm/drm_managed.h>
> > +
> > +#include "xe_device.h"
> > +#include "xe_gt_types.h"
> > #include "xe_pagefault.h"
> > #include "xe_pagefault_types.h"
> >
> > @@ -21,6 +25,71 @@
> > * xe_pagefault.c implements the consumer layer.
> > */
> >
> > +static int xe_pagefault_entry_size(void)
> > +{
> > + return roundup_pow_of_two(sizeof(struct xe_pagefault));
> > +}
> > +
> > +static void xe_pagefault_queue_work(struct work_struct *w)
> > +{
> > + /* TODO: Implement */
> > +}
> > +
> > +static int xe_pagefault_queue_init(struct xe_device *xe,
> > + struct xe_pagefault_queue *pf_queue)
> > +{
> > + struct xe_gt *gt;
> > + int total_num_eus = 0;
> > + u8 id;
> > +
> > + for_each_gt(gt, xe, id) {
> > + xe_dss_mask_t all_dss;
> > + int num_dss, num_eus;
> > +
> > + bitmap_or(all_dss, gt->fuse_topo.g_dss_mask,
> > + gt->fuse_topo.c_dss_mask, XE_MAX_DSS_FUSE_BITS);
> > +
> > + num_dss = bitmap_weight(all_dss, XE_MAX_DSS_FUSE_BITS);
> > + num_eus = bitmap_weight(gt->fuse_topo.eu_mask_per_dss,
> > + XE_MAX_EU_FUSE_BITS) * num_dss;
> > +
> > + total_num_eus += num_eus;
> > + }
> > +
> > + xe_assert(xe, total_num_eus);
> > +
> > + /*
> > + * user can issue separate page faults per EU and per CS
> > + *
> > + * XXX: Multiplier required as compute UMD are getting PF queue errors
> > + * without it. Follow on why this multiplier is required.
> > + */
> > +#define PF_MULTIPLIER 8
> > + pf_queue->size = (total_num_eus + XE_NUM_HW_ENGINES) *
> > + xe_pagefault_entry_size() * PF_MULTIPLIER;
> > + pf_queue->size = roundup_pow_of_two(pf_queue->size);
> > +#undef PF_MULTIPLIER
> > +
> > + drm_dbg(&xe->drm, "xe_pagefault_entry_size=%d, total_num_eus=%d, pf_queue->size=%u",
> > + xe_pagefault_entry_size(), total_num_eus, pf_queue->size);
> > +
> > + spin_lock_init(&pf_queue->lock);
> > + INIT_WORK(&pf_queue->worker, xe_pagefault_queue_work);
>
> These 2 lines ^...
>
> > +
> > + pf_queue->data = drmm_kzalloc(&xe->drm, pf_queue->size, GFP_KERNEL);
> > + if (!pf_queue->data)
> > + return -ENOMEM;
>
> ... and those 3 lines were swapped since last revision. It is probably
> too early for pf_queue to be used here anyway but was there a reason for
> changing the order?
>
I was fighting CI and lost. Have a proper version which should work now locally.
Matt
> Francois
>
> > +
> > + return 0;
> > +}
> > +
> > +static void xe_pagefault_fini(void *arg)
> > +{
> > + struct xe_device *xe = arg;
> > +
> > + destroy_workqueue(xe->usm.pf_wq);
> > +}
> > +
> > /**
> > * xe_pagefault_init() - Page fault init
> > * @xe: xe device instance
> > @@ -31,8 +100,28 @@
> > */
> > int xe_pagefault_init(struct xe_device *xe)
> > {
> > - /* TODO - implement */
> > - return 0;
> > + int err, i;
> > +
> > + if (!xe->info.has_usm)
> > + return 0;
> > +
> > + xe->usm.pf_wq = alloc_workqueue("xe_page_fault_work_queue",
> > + WQ_UNBOUND | WQ_HIGHPRI,
> > + XE_PAGEFAULT_QUEUE_COUNT);
> > + if (!xe->usm.pf_wq)
> > + return -ENOMEM;
> > +
> > + for (i = 0; i < XE_PAGEFAULT_QUEUE_COUNT; ++i) {
> > + err = xe_pagefault_queue_init(xe, xe->usm.pf_queue + i);
> > + if (err)
> > + goto err_out;
> > + }
> > +
> > + return devm_add_action_or_reset(xe->drm.dev, xe_pagefault_fini, xe);
> > +
> > +err_out:
> > + destroy_workqueue(xe->usm.pf_wq);
> > + return err;
> > }
> >
> > /**
> > --
> > 2.34.1
> >
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 3/7] drm/xe: Implement xe_pagefault_reset
2025-10-28 3:58 [PATCH v3 0/7] Pagefault refactor Matthew Brost
2025-10-28 3:58 ` [PATCH v3 1/7] drm/xe: Stub out new pagefault layer Matthew Brost
2025-10-28 3:58 ` [PATCH v3 2/7] drm/xe: Implement xe_pagefault_init Matthew Brost
@ 2025-10-28 3:58 ` Matthew Brost
2025-10-28 3:58 ` [PATCH v3 4/7] drm/xe: Implement xe_pagefault_handler Matthew Brost
` (7 subsequent siblings)
10 siblings, 0 replies; 16+ messages in thread
From: Matthew Brost @ 2025-10-28 3:58 UTC (permalink / raw)
To: intel-xe; +Cc: stuart.summers, francois.dugast
Squash any pending faults on the GT being reset by setting the GT field
in struct xe_pagefault to NULL.
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
drivers/gpu/drm/xe/xe_gt.c | 2 ++
drivers/gpu/drm/xe/xe_pagefault.c | 23 ++++++++++++++++++++++-
2 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
index 89808b33d0a8..e4852c4c90cd 100644
--- a/drivers/gpu/drm/xe/xe_gt.c
+++ b/drivers/gpu/drm/xe/xe_gt.c
@@ -49,6 +49,7 @@
#include "xe_map.h"
#include "xe_migrate.h"
#include "xe_mmio.h"
+#include "xe_pagefault.h"
#include "xe_pat.h"
#include "xe_pm.h"
#include "xe_mocs.h"
@@ -849,6 +850,7 @@ static int gt_reset(struct xe_gt *gt)
xe_uc_gucrc_disable(>->uc);
xe_uc_stop_prepare(>->uc);
+ xe_pagefault_reset(gt_to_xe(gt), gt);
xe_gt_pagefault_reset(gt);
xe_uc_stop(>->uc);
diff --git a/drivers/gpu/drm/xe/xe_pagefault.c b/drivers/gpu/drm/xe/xe_pagefault.c
index 43b26e7d090a..f86c1eff0f4d 100644
--- a/drivers/gpu/drm/xe/xe_pagefault.c
+++ b/drivers/gpu/drm/xe/xe_pagefault.c
@@ -124,6 +124,24 @@ int xe_pagefault_init(struct xe_device *xe)
return err;
}
+static void xe_pagefault_queue_reset(struct xe_device *xe, struct xe_gt *gt,
+ struct xe_pagefault_queue *pf_queue)
+{
+ u32 i;
+
+ /* Squash all pending faults on the GT */
+
+ spin_lock_irq(&pf_queue->lock);
+ for (i = pf_queue->tail; i != pf_queue->head;
+ i = (i + xe_pagefault_entry_size()) % pf_queue->size) {
+ struct xe_pagefault *pf = pf_queue->data + i;
+
+ if (pf->gt == gt)
+ pf->gt = NULL;
+ }
+ spin_unlock_irq(&pf_queue->lock);
+}
+
/**
* xe_pagefault_reset() - Page fault reset for a GT
* @xe: xe device instance
@@ -134,7 +152,10 @@ int xe_pagefault_init(struct xe_device *xe)
*/
void xe_pagefault_reset(struct xe_device *xe, struct xe_gt *gt)
{
- /* TODO - implement */
+ int i;
+
+ for (i = 0; i < XE_PAGEFAULT_QUEUE_COUNT; ++i)
+ xe_pagefault_queue_reset(xe, gt, xe->usm.pf_queue + i);
}
/**
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v3 4/7] drm/xe: Implement xe_pagefault_handler
2025-10-28 3:58 [PATCH v3 0/7] Pagefault refactor Matthew Brost
` (2 preceding siblings ...)
2025-10-28 3:58 ` [PATCH v3 3/7] drm/xe: Implement xe_pagefault_reset Matthew Brost
@ 2025-10-28 3:58 ` Matthew Brost
2025-10-28 3:58 ` [PATCH v3 5/7] drm/xe: Implement xe_pagefault_queue_work Matthew Brost
` (6 subsequent siblings)
10 siblings, 0 replies; 16+ messages in thread
From: Matthew Brost @ 2025-10-28 3:58 UTC (permalink / raw)
To: intel-xe; +Cc: stuart.summers, francois.dugast
Enqueue (copy) the input struct xe_pagefault into a queue (i.e., into a
memory buffer) and schedule a worker to service it.
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Francois Dugast <francois.dugast@intel.com>
---
drivers/gpu/drm/xe/xe_pagefault.c | 32 +++++++++++++++++++++++++++++--
1 file changed, 30 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_pagefault.c b/drivers/gpu/drm/xe/xe_pagefault.c
index f86c1eff0f4d..6a4f34328d3c 100644
--- a/drivers/gpu/drm/xe/xe_pagefault.c
+++ b/drivers/gpu/drm/xe/xe_pagefault.c
@@ -3,6 +3,8 @@
* Copyright © 2025 Intel Corporation
*/
+#include <linux/circ_buf.h>
+
#include <drm/drm_managed.h>
#include "xe_device.h"
@@ -158,6 +160,14 @@ void xe_pagefault_reset(struct xe_device *xe, struct xe_gt *gt)
xe_pagefault_queue_reset(xe, gt, xe->usm.pf_queue + i);
}
+static bool xe_pagefault_queue_full(struct xe_pagefault_queue *pf_queue)
+{
+ lockdep_assert_held(&pf_queue->lock);
+
+ return CIRC_SPACE(pf_queue->head, pf_queue->tail, pf_queue->size) <=
+ xe_pagefault_entry_size();
+}
+
/**
* xe_pagefault_handler() - Page fault handler
* @xe: xe device instance
@@ -170,6 +180,24 @@ void xe_pagefault_reset(struct xe_device *xe, struct xe_gt *gt)
*/
int xe_pagefault_handler(struct xe_device *xe, struct xe_pagefault *pf)
{
- /* TODO - implement */
- return 0;
+ struct xe_pagefault_queue *pf_queue = xe->usm.pf_queue +
+ (pf->consumer.asid % XE_PAGEFAULT_QUEUE_COUNT);
+ unsigned long flags;
+ bool full;
+
+ spin_lock_irqsave(&pf_queue->lock, flags);
+ full = xe_pagefault_queue_full(pf_queue);
+ if (!full) {
+ memcpy(pf_queue->data + pf_queue->head, pf, sizeof(*pf));
+ pf_queue->head = (pf_queue->head + xe_pagefault_entry_size()) %
+ pf_queue->size;
+ queue_work(xe->usm.pf_wq, &pf_queue->worker);
+ } else {
+ drm_warn(&xe->drm,
+ "PageFault Queue (%d) full, shouldn't be possible\n",
+ pf->consumer.asid % XE_PAGEFAULT_QUEUE_COUNT);
+ }
+ spin_unlock_irqrestore(&pf_queue->lock, flags);
+
+ return full ? -ENOSPC : 0;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v3 5/7] drm/xe: Implement xe_pagefault_queue_work
2025-10-28 3:58 [PATCH v3 0/7] Pagefault refactor Matthew Brost
` (3 preceding siblings ...)
2025-10-28 3:58 ` [PATCH v3 4/7] drm/xe: Implement xe_pagefault_handler Matthew Brost
@ 2025-10-28 3:58 ` Matthew Brost
2025-10-28 3:58 ` [PATCH v3 6/7] drm/xe: Add xe_guc_pagefault layer Matthew Brost
` (5 subsequent siblings)
10 siblings, 0 replies; 16+ messages in thread
From: Matthew Brost @ 2025-10-28 3:58 UTC (permalink / raw)
To: intel-xe; +Cc: stuart.summers, francois.dugast
Implement a worker that services page faults, using the same
implementation as in xe_gt_pagefault.c.
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Stuart Summers <stuart.summers@intel.com>
---
drivers/gpu/drm/xe/xe_pagefault.c | 235 +++++++++++++++++++++++++++++-
1 file changed, 234 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xe/xe_pagefault.c b/drivers/gpu/drm/xe/xe_pagefault.c
index 6a4f34328d3c..e173544fa57a 100644
--- a/drivers/gpu/drm/xe/xe_pagefault.c
+++ b/drivers/gpu/drm/xe/xe_pagefault.c
@@ -5,12 +5,20 @@
#include <linux/circ_buf.h>
+#include <drm/drm_exec.h>
#include <drm/drm_managed.h>
+#include "xe_bo.h"
#include "xe_device.h"
+#include "xe_gt_printk.h"
#include "xe_gt_types.h"
+#include "xe_gt_stats.h"
+#include "xe_hw_engine.h"
#include "xe_pagefault.h"
#include "xe_pagefault_types.h"
+#include "xe_svm.h"
+#include "xe_trace_bo.h"
+#include "xe_vm.h"
/**
* DOC: Xe page faults
@@ -32,9 +40,234 @@ static int xe_pagefault_entry_size(void)
return roundup_pow_of_two(sizeof(struct xe_pagefault));
}
+static int xe_pagefault_begin(struct drm_exec *exec, struct xe_vma *vma,
+ struct xe_vram_region *vram, bool need_vram_move)
+{
+ struct xe_bo *bo = xe_vma_bo(vma);
+ struct xe_vm *vm = xe_vma_vm(vma);
+ int err;
+
+ err = xe_vm_lock_vma(exec, vma);
+ if (err)
+ return err;
+
+ if (!bo)
+ return 0;
+
+ return need_vram_move ? xe_bo_migrate(bo, vram->placement, NULL, exec) :
+ xe_bo_validate(bo, vm, true, exec);
+}
+
+static int xe_pagefault_handle_vma(struct xe_gt *gt, struct xe_vma *vma,
+ bool atomic)
+{
+ struct xe_vm *vm = xe_vma_vm(vma);
+ struct xe_tile *tile = gt_to_tile(gt);
+ struct xe_validation_ctx ctx;
+ struct drm_exec exec;
+ struct dma_fence *fence;
+ int err, needs_vram;
+
+ lockdep_assert_held_write(&vm->lock);
+
+ needs_vram = xe_vma_need_vram_for_atomic(vm->xe, vma, atomic);
+ if (needs_vram < 0 || (needs_vram && xe_vma_is_userptr(vma)))
+ return needs_vram < 0 ? needs_vram : -EACCES;
+
+ xe_gt_stats_incr(gt, XE_GT_STATS_ID_VMA_PAGEFAULT_COUNT, 1);
+ xe_gt_stats_incr(gt, XE_GT_STATS_ID_VMA_PAGEFAULT_KB,
+ xe_vma_size(vma) / SZ_1K);
+
+ trace_xe_vma_pagefault(vma);
+
+ /* Check if VMA is valid, opportunistic check only */
+ if (xe_vm_has_valid_gpu_mapping(tile, vma->tile_present,
+ vma->tile_invalidated) && !atomic)
+ return 0;
+
+retry_userptr:
+ if (xe_vma_is_userptr(vma) &&
+ xe_vma_userptr_check_repin(to_userptr_vma(vma))) {
+ struct xe_userptr_vma *uvma = to_userptr_vma(vma);
+
+ err = xe_vma_userptr_pin_pages(uvma);
+ if (err)
+ return err;
+ }
+
+ /* Lock VM and BOs dma-resv */
+ xe_validation_ctx_init(&ctx, &vm->xe->val, &exec, (struct xe_val_flags) {});
+ drm_exec_init(&exec, 0, 0);
+ drm_exec_until_all_locked(&exec) {
+ err = xe_pagefault_begin(&exec, vma, tile->mem.vram,
+ needs_vram == 1);
+ drm_exec_retry_on_contention(&exec);
+ xe_validation_retry_on_oom(&ctx, &err);
+ if (err)
+ goto unlock_dma_resv;
+
+ /* Bind VMA only to the GT that has faulted */
+ trace_xe_vma_pf_bind(vma);
+ xe_vm_set_validation_exec(vm, &exec);
+ fence = xe_vma_rebind(vm, vma, BIT(tile->id));
+ xe_vm_set_validation_exec(vm, NULL);
+ if (IS_ERR(fence)) {
+ err = PTR_ERR(fence);
+ xe_validation_retry_on_oom(&ctx, &err);
+ goto unlock_dma_resv;
+ }
+ }
+
+ dma_fence_wait(fence, false);
+ dma_fence_put(fence);
+
+unlock_dma_resv:
+ xe_validation_ctx_fini(&ctx);
+ if (err == -EAGAIN)
+ goto retry_userptr;
+
+ return err;
+}
+
+static bool
+xe_pagefault_access_is_atomic(enum xe_pagefault_access_type access_type)
+{
+ return access_type == XE_PAGEFAULT_ACCESS_TYPE_ATOMIC;
+}
+
+static struct xe_vm *xe_pagefault_asid_to_vm(struct xe_device *xe, u32 asid)
+{
+ struct xe_vm *vm;
+
+ down_read(&xe->usm.lock);
+ vm = xa_load(&xe->usm.asid_to_vm, asid);
+ if (vm && xe_vm_in_fault_mode(vm))
+ xe_vm_get(vm);
+ else
+ vm = ERR_PTR(-EINVAL);
+ up_read(&xe->usm.lock);
+
+ return vm;
+}
+
+static int xe_pagefault_service(struct xe_pagefault *pf)
+{
+ struct xe_gt *gt = pf->gt;
+ struct xe_device *xe = gt_to_xe(gt);
+ struct xe_vm *vm;
+ struct xe_vma *vma = NULL;
+ int err;
+ bool atomic;
+
+ /* Producer flagged this fault to be nacked */
+ if (pf->consumer.fault_level == XE_PAGEFAULT_LEVEL_NACK)
+ return -EFAULT;
+
+ vm = xe_pagefault_asid_to_vm(xe, pf->consumer.asid);
+ if (IS_ERR(vm))
+ return PTR_ERR(vm);
+
+ /*
+ * TODO: Change to read lock? Using write lock for simplicity.
+ */
+ down_write(&vm->lock);
+
+ if (xe_vm_is_closed(vm)) {
+ err = -ENOENT;
+ goto unlock_vm;
+ }
+
+ vma = xe_vm_find_vma_by_addr(vm, pf->consumer.page_addr);
+ if (!vma) {
+ err = -EINVAL;
+ goto unlock_vm;
+ }
+
+ atomic = xe_pagefault_access_is_atomic(pf->consumer.access_type);
+
+ if (xe_vma_is_cpu_addr_mirror(vma))
+ err = xe_svm_handle_pagefault(vm, vma, gt,
+ pf->consumer.page_addr, atomic);
+ else
+ err = xe_pagefault_handle_vma(gt, vma, atomic);
+
+unlock_vm:
+ if (!err)
+ vm->usm.last_fault_vma = vma;
+ up_write(&vm->lock);
+ xe_vm_put(vm);
+
+ return err;
+}
+
+static bool xe_pagefault_queue_pop(struct xe_pagefault_queue *pf_queue,
+ struct xe_pagefault *pf)
+{
+ bool found_fault = false;
+
+ spin_lock_irq(&pf_queue->lock);
+ if (pf_queue->tail != pf_queue->head) {
+ memcpy(pf, pf_queue->data + pf_queue->tail, sizeof(*pf));
+ pf_queue->tail = (pf_queue->tail + xe_pagefault_entry_size()) %
+ pf_queue->size;
+ found_fault = true;
+ }
+ spin_unlock_irq(&pf_queue->lock);
+
+ return found_fault;
+}
+
+static void xe_pagefault_print(struct xe_pagefault *pf)
+{
+ xe_gt_dbg(pf->gt, "\n\tASID: %d\n"
+ "\tFaulted Address: 0x%08x%08x\n"
+ "\tFaultType: %d\n"
+ "\tAccessType: %d\n"
+ "\tFaultLevel: %d\n"
+ "\tEngineClass: %d %s\n"
+ "\tEngineInstance: %d\n",
+ pf->consumer.asid,
+ upper_32_bits(pf->consumer.page_addr),
+ lower_32_bits(pf->consumer.page_addr),
+ pf->consumer.fault_type,
+ pf->consumer.access_type,
+ pf->consumer.fault_level,
+ pf->consumer.engine_class,
+ xe_hw_engine_class_to_str(pf->consumer.engine_class),
+ pf->consumer.engine_instance);
+}
+
static void xe_pagefault_queue_work(struct work_struct *w)
{
- /* TODO: Implement */
+ struct xe_pagefault_queue *pf_queue =
+ container_of(w, typeof(*pf_queue), worker);
+ struct xe_pagefault pf;
+ unsigned long threshold;
+
+#define USM_QUEUE_MAX_RUNTIME_MS 20
+ threshold = jiffies + msecs_to_jiffies(USM_QUEUE_MAX_RUNTIME_MS);
+
+ while (xe_pagefault_queue_pop(pf_queue, &pf)) {
+ int err;
+
+ if (!pf.gt) /* Fault squashed during reset */
+ continue;
+
+ err = xe_pagefault_service(&pf);
+ if (err) {
+ xe_pagefault_print(&pf);
+ xe_gt_dbg(pf.gt, "Fault response: Unsuccessful %pe\n",
+ ERR_PTR(err));
+ }
+
+ pf.producer.ops->ack_fault(&pf, err);
+
+ if (time_after(jiffies, threshold)) {
+ queue_work(gt_to_xe(pf.gt)->usm.pf_wq, w);
+ break;
+ }
+ }
+#undef USM_QUEUE_MAX_RUNTIME_MS
}
static int xe_pagefault_queue_init(struct xe_device *xe,
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v3 6/7] drm/xe: Add xe_guc_pagefault layer
2025-10-28 3:58 [PATCH v3 0/7] Pagefault refactor Matthew Brost
` (4 preceding siblings ...)
2025-10-28 3:58 ` [PATCH v3 5/7] drm/xe: Implement xe_pagefault_queue_work Matthew Brost
@ 2025-10-28 3:58 ` Matthew Brost
2025-10-28 3:58 ` [PATCH v3 7/7] drm/xe: Remove unused GT page fault code Matthew Brost
` (4 subsequent siblings)
10 siblings, 0 replies; 16+ messages in thread
From: Matthew Brost @ 2025-10-28 3:58 UTC (permalink / raw)
To: intel-xe; +Cc: stuart.summers, francois.dugast
Add xe_guc_pagefault layer (producer) which parses G2H fault messages
messages into struct xe_pagefault, forwards them to the page fault layer
(consumer) for servicing, and provides a vfunc to acknowledge faults to
the GuC upon completion. Replace the old (and incorrect) GT page fault
layer with this new layer throughout the driver.
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
drivers/gpu/drm/xe/Makefile | 2 +-
drivers/gpu/drm/xe/xe_gt.c | 6 --
drivers/gpu/drm/xe/xe_guc_ct.c | 6 +-
drivers/gpu/drm/xe/xe_guc_pagefault.c | 95 +++++++++++++++++++++++++++
drivers/gpu/drm/xe/xe_guc_pagefault.h | 15 +++++
drivers/gpu/drm/xe/xe_svm.c | 3 +-
drivers/gpu/drm/xe/xe_vm.c | 1 -
7 files changed, 113 insertions(+), 15 deletions(-)
create mode 100644 drivers/gpu/drm/xe/xe_guc_pagefault.c
create mode 100644 drivers/gpu/drm/xe/xe_guc_pagefault.h
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index b35021e5b9eb..319f208eb19a 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -58,7 +58,6 @@ xe-y += xe_bb.o \
xe_gt_freq.o \
xe_gt_idle.o \
xe_gt_mcr.o \
- xe_gt_pagefault.o \
xe_gt_sysfs.o \
xe_gt_throttle.o \
xe_gt_topology.o \
@@ -73,6 +72,7 @@ xe-y += xe_bb.o \
xe_guc_id_mgr.o \
xe_guc_klv_helpers.o \
xe_guc_log.o \
+ xe_guc_pagefault.o \
xe_guc_pc.o \
xe_guc_submit.o \
xe_guc_tlb_inval.o \
diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
index e4852c4c90cd..44ed3202dfd1 100644
--- a/drivers/gpu/drm/xe/xe_gt.c
+++ b/drivers/gpu/drm/xe/xe_gt.c
@@ -32,7 +32,6 @@
#include "xe_gt_freq.h"
#include "xe_gt_idle.h"
#include "xe_gt_mcr.h"
-#include "xe_gt_pagefault.h"
#include "xe_gt_printk.h"
#include "xe_gt_sriov_pf.h"
#include "xe_gt_sriov_vf.h"
@@ -638,10 +637,6 @@ int xe_gt_init(struct xe_gt *gt)
if (err)
return err;
- err = xe_gt_pagefault_init(gt);
- if (err)
- return err;
-
err = xe_gt_idle_init(>->gtidle);
if (err)
return err;
@@ -851,7 +846,6 @@ static int gt_reset(struct xe_gt *gt)
xe_uc_gucrc_disable(>->uc);
xe_uc_stop_prepare(>->uc);
xe_pagefault_reset(gt_to_xe(gt), gt);
- xe_gt_pagefault_reset(gt);
xe_uc_stop(>->uc);
diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c b/drivers/gpu/drm/xe/xe_guc_ct.c
index e68953ef3a00..529d2b3bec21 100644
--- a/drivers/gpu/drm/xe/xe_guc_ct.c
+++ b/drivers/gpu/drm/xe/xe_guc_ct.c
@@ -21,12 +21,12 @@
#include "xe_devcoredump.h"
#include "xe_device.h"
#include "xe_gt.h"
-#include "xe_gt_pagefault.h"
#include "xe_gt_printk.h"
#include "xe_gt_sriov_pf_control.h"
#include "xe_gt_sriov_pf_monitor.h"
#include "xe_guc.h"
#include "xe_guc_log.h"
+#include "xe_guc_pagefault.h"
#include "xe_guc_relay.h"
#include "xe_guc_submit.h"
#include "xe_guc_tlb_inval.h"
@@ -1545,10 +1545,6 @@ static int process_g2h_msg(struct xe_guc_ct *ct, u32 *msg, u32 len)
case XE_GUC_ACTION_TLB_INVALIDATION_DONE:
ret = xe_guc_tlb_inval_done_handler(guc, payload, adj_len);
break;
- case XE_GUC_ACTION_ACCESS_COUNTER_NOTIFY:
- ret = xe_guc_access_counter_notify_handler(guc, payload,
- adj_len);
- break;
case XE_GUC_ACTION_GUC2PF_RELAY_FROM_VF:
ret = xe_guc_relay_process_guc2pf(&guc->relay, hxg, hxg_len);
break;
diff --git a/drivers/gpu/drm/xe/xe_guc_pagefault.c b/drivers/gpu/drm/xe/xe_guc_pagefault.c
new file mode 100644
index 000000000000..719a18187a31
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_guc_pagefault.c
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#include "abi/guc_actions_abi.h"
+#include "xe_guc.h"
+#include "xe_guc_ct.h"
+#include "xe_guc_pagefault.h"
+#include "xe_pagefault.h"
+
+static void guc_ack_fault(struct xe_pagefault *pf, int err)
+{
+ u32 vfid = FIELD_GET(PFD_VFID, pf->producer.msg[2]);
+ u32 engine_instance = FIELD_GET(PFD_ENG_INSTANCE, pf->producer.msg[0]);
+ u32 engine_class = FIELD_GET(PFD_ENG_CLASS, pf->producer.msg[0]);
+ u32 pdata = FIELD_GET(PFD_PDATA_LO, pf->producer.msg[0]) |
+ (FIELD_GET(PFD_PDATA_HI, pf->producer.msg[1]) <<
+ PFD_PDATA_HI_SHIFT);
+ u32 action[] = {
+ XE_GUC_ACTION_PAGE_FAULT_RES_DESC,
+
+ FIELD_PREP(PFR_VALID, 1) |
+ FIELD_PREP(PFR_SUCCESS, !!err) |
+ FIELD_PREP(PFR_REPLY, PFR_ACCESS) |
+ FIELD_PREP(PFR_DESC_TYPE, FAULT_RESPONSE_DESC) |
+ FIELD_PREP(PFR_ASID, pf->consumer.asid),
+
+ FIELD_PREP(PFR_VFID, vfid) |
+ FIELD_PREP(PFR_ENG_INSTANCE, engine_instance) |
+ FIELD_PREP(PFR_ENG_CLASS, engine_class) |
+ FIELD_PREP(PFR_PDATA, pdata),
+ };
+ struct xe_guc *guc = pf->producer.private;
+
+ xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action), 0, 0);
+}
+
+static const struct xe_pagefault_ops guc_pagefault_ops = {
+ .ack_fault = guc_ack_fault,
+};
+
+/**
+ * xe_guc_pagefault_handler() - G2H page fault handler
+ * @guc: GuC object
+ * @msg: G2H message
+ * @len: Length of G2H message
+ *
+ * Parse GuC to host (G2H) message into a struct xe_pagefault and forward onto
+ * the Xe page fault layer.
+ *
+ * Return: 0 on success, errno on failure
+ */
+int xe_guc_pagefault_handler(struct xe_guc *guc, u32 *msg, u32 len)
+{
+ struct xe_pagefault pf;
+ int i;
+
+#define GUC_PF_MSG_LEN_DW \
+ (sizeof(struct xe_guc_pagefault_desc) / sizeof(u32))
+
+ BUILD_BUG_ON(GUC_PF_MSG_LEN_DW > XE_PAGEFAULT_PRODUCER_MSG_LEN_DW);
+
+ if (len != GUC_PF_MSG_LEN_DW)
+ return -EPROTO;
+
+ pf.gt = guc_to_gt(guc);
+
+ /*
+ * XXX: These values happen to match the enum in xe_pagefault_types.h.
+ * If that changes, we’ll need to remap them here.
+ */
+ pf.consumer.page_addr = ((u64)FIELD_GET(PFD_VIRTUAL_ADDR_HI, msg[3])
+ << PFD_VIRTUAL_ADDR_HI_SHIFT) |
+ (FIELD_GET(PFD_VIRTUAL_ADDR_LO, msg[2]) <<
+ PFD_VIRTUAL_ADDR_LO_SHIFT);
+ pf.consumer.asid = FIELD_GET(PFD_ASID, msg[1]);
+ pf.consumer.access_type = FIELD_GET(PFD_ACCESS_TYPE, msg[2]);
+ pf.consumer.fault_type = FIELD_GET(PFD_FAULT_TYPE, msg[2]);
+ if (FIELD_GET(XE2_PFD_TRVA_FAULT, msg[0]))
+ pf.consumer.fault_level = XE_PAGEFAULT_LEVEL_NACK;
+ else
+ pf.consumer.fault_level = FIELD_GET(PFD_FAULT_LEVEL, msg[0]);
+ pf.consumer.engine_class = FIELD_GET(PFD_ENG_CLASS, msg[0]);
+ pf.consumer.engine_instance = FIELD_GET(PFD_ENG_INSTANCE, msg[0]);
+
+ pf.producer.private = guc;
+ pf.producer.ops = &guc_pagefault_ops;
+ for (i = 0; i < GUC_PF_MSG_LEN_DW; ++i)
+ pf.producer.msg[i] = msg[i];
+
+#undef GUC_PF_MSG_LEN_DW
+
+ return xe_pagefault_handler(guc_to_xe(guc), &pf);
+}
diff --git a/drivers/gpu/drm/xe/xe_guc_pagefault.h b/drivers/gpu/drm/xe/xe_guc_pagefault.h
new file mode 100644
index 000000000000..3bd599e7207c
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_guc_pagefault.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef _XE_GUC_PAGEFAULT_H_
+#define _XE_GUC_PAGEFAULT_H_
+
+#include <linux/types.h>
+
+struct xe_guc;
+
+int xe_guc_pagefault_handler(struct xe_guc *guc, u32 *msg, u32 len);
+
+#endif
diff --git a/drivers/gpu/drm/xe/xe_svm.c b/drivers/gpu/drm/xe/xe_svm.c
index 13af589715a7..55c5a0eb82e1 100644
--- a/drivers/gpu/drm/xe/xe_svm.c
+++ b/drivers/gpu/drm/xe/xe_svm.c
@@ -104,8 +104,7 @@ xe_svm_garbage_collector_add_range(struct xe_vm *vm, struct xe_svm_range *range,
&vm->svm.garbage_collector.range_list);
spin_unlock(&vm->svm.garbage_collector.lock);
- queue_work(xe_device_get_root_tile(xe)->primary_gt->usm.pf_wq,
- &vm->svm.garbage_collector.work);
+ queue_work(xe->usm.pf_wq, &vm->svm.garbage_collector.work);
}
static void xe_svm_tlb_inval_count_stats_incr(struct xe_gt *gt)
diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
index 00f3520dec38..aef9d4ae9511 100644
--- a/drivers/gpu/drm/xe/xe_vm.c
+++ b/drivers/gpu/drm/xe/xe_vm.c
@@ -27,7 +27,6 @@
#include "xe_device.h"
#include "xe_drm_client.h"
#include "xe_exec_queue.h"
-#include "xe_gt_pagefault.h"
#include "xe_migrate.h"
#include "xe_pat.h"
#include "xe_pm.h"
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v3 7/7] drm/xe: Remove unused GT page fault code
2025-10-28 3:58 [PATCH v3 0/7] Pagefault refactor Matthew Brost
` (5 preceding siblings ...)
2025-10-28 3:58 ` [PATCH v3 6/7] drm/xe: Add xe_guc_pagefault layer Matthew Brost
@ 2025-10-28 3:58 ` Matthew Brost
2025-10-28 4:05 ` ✗ CI.checkpatch: warning for Pagefault refactor (rev2) Patchwork
` (3 subsequent siblings)
10 siblings, 0 replies; 16+ messages in thread
From: Matthew Brost @ 2025-10-28 3:58 UTC (permalink / raw)
To: intel-xe; +Cc: stuart.summers, francois.dugast
With the Xe page fault layer and GuC page layer in place, this is now
dead code and can be removed. ACC code is also removed, but this was
dead code.
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
drivers/gpu/drm/xe/xe_gt_pagefault.c | 679 ---------------------------
drivers/gpu/drm/xe/xe_gt_pagefault.h | 19 -
drivers/gpu/drm/xe/xe_gt_types.h | 65 ---
3 files changed, 763 deletions(-)
delete mode 100644 drivers/gpu/drm/xe/xe_gt_pagefault.c
delete mode 100644 drivers/gpu/drm/xe/xe_gt_pagefault.h
diff --git a/drivers/gpu/drm/xe/xe_gt_pagefault.c b/drivers/gpu/drm/xe/xe_gt_pagefault.c
deleted file mode 100644
index a054d6010ae0..000000000000
--- a/drivers/gpu/drm/xe/xe_gt_pagefault.c
+++ /dev/null
@@ -1,679 +0,0 @@
-// SPDX-License-Identifier: MIT
-/*
- * Copyright © 2022 Intel Corporation
- */
-
-#include "xe_gt_pagefault.h"
-
-#include <linux/bitfield.h>
-#include <linux/circ_buf.h>
-
-#include <drm/drm_exec.h>
-#include <drm/drm_managed.h>
-
-#include "abi/guc_actions_abi.h"
-#include "xe_bo.h"
-#include "xe_gt.h"
-#include "xe_gt_printk.h"
-#include "xe_gt_stats.h"
-#include "xe_guc.h"
-#include "xe_guc_ct.h"
-#include "xe_migrate.h"
-#include "xe_svm.h"
-#include "xe_trace_bo.h"
-#include "xe_vm.h"
-#include "xe_vram_types.h"
-
-struct pagefault {
- u64 page_addr;
- u32 asid;
- u16 pdata;
- u8 vfid;
- u8 access_type;
- u8 fault_type;
- u8 fault_level;
- u8 engine_class;
- u8 engine_instance;
- u8 fault_unsuccessful;
- bool trva_fault;
-};
-
-enum access_type {
- ACCESS_TYPE_READ = 0,
- ACCESS_TYPE_WRITE = 1,
- ACCESS_TYPE_ATOMIC = 2,
- ACCESS_TYPE_RESERVED = 3,
-};
-
-enum fault_type {
- NOT_PRESENT = 0,
- WRITE_ACCESS_VIOLATION = 1,
- ATOMIC_ACCESS_VIOLATION = 2,
-};
-
-struct acc {
- u64 va_range_base;
- u32 asid;
- u32 sub_granularity;
- u8 granularity;
- u8 vfid;
- u8 access_type;
- u8 engine_class;
- u8 engine_instance;
-};
-
-static bool access_is_atomic(enum access_type access_type)
-{
- return access_type == ACCESS_TYPE_ATOMIC;
-}
-
-static bool vma_is_valid(struct xe_tile *tile, struct xe_vma *vma)
-{
- return xe_vm_has_valid_gpu_mapping(tile, vma->tile_present,
- vma->tile_invalidated);
-}
-
-static int xe_pf_begin(struct drm_exec *exec, struct xe_vma *vma,
- bool need_vram_move, struct xe_vram_region *vram)
-{
- struct xe_bo *bo = xe_vma_bo(vma);
- struct xe_vm *vm = xe_vma_vm(vma);
- int err;
-
- err = xe_vm_lock_vma(exec, vma);
- if (err)
- return err;
-
- if (!bo)
- return 0;
-
- return need_vram_move ? xe_bo_migrate(bo, vram->placement, NULL, exec) :
- xe_bo_validate(bo, vm, true, exec);
-}
-
-static int handle_vma_pagefault(struct xe_gt *gt, struct xe_vma *vma,
- bool atomic)
-{
- struct xe_vm *vm = xe_vma_vm(vma);
- struct xe_tile *tile = gt_to_tile(gt);
- struct xe_validation_ctx ctx;
- struct drm_exec exec;
- struct dma_fence *fence;
- int err, needs_vram;
-
- lockdep_assert_held_write(&vm->lock);
-
- needs_vram = xe_vma_need_vram_for_atomic(vm->xe, vma, atomic);
- if (needs_vram < 0 || (needs_vram && xe_vma_is_userptr(vma)))
- return needs_vram < 0 ? needs_vram : -EACCES;
-
- xe_gt_stats_incr(gt, XE_GT_STATS_ID_VMA_PAGEFAULT_COUNT, 1);
- xe_gt_stats_incr(gt, XE_GT_STATS_ID_VMA_PAGEFAULT_KB, xe_vma_size(vma) / 1024);
-
- trace_xe_vma_pagefault(vma);
-
- /* Check if VMA is valid, opportunistic check only */
- if (vma_is_valid(tile, vma) && !atomic)
- return 0;
-
-retry_userptr:
- if (xe_vma_is_userptr(vma) &&
- xe_vma_userptr_check_repin(to_userptr_vma(vma))) {
- struct xe_userptr_vma *uvma = to_userptr_vma(vma);
-
- err = xe_vma_userptr_pin_pages(uvma);
- if (err)
- return err;
- }
-
- /* Lock VM and BOs dma-resv */
- xe_validation_ctx_init(&ctx, &vm->xe->val, &exec, (struct xe_val_flags) {});
- drm_exec_until_all_locked(&exec) {
- err = xe_pf_begin(&exec, vma, needs_vram == 1, tile->mem.vram);
- drm_exec_retry_on_contention(&exec);
- xe_validation_retry_on_oom(&ctx, &err);
- if (err)
- goto unlock_dma_resv;
-
- /* Bind VMA only to the GT that has faulted */
- trace_xe_vma_pf_bind(vma);
- xe_vm_set_validation_exec(vm, &exec);
- fence = xe_vma_rebind(vm, vma, BIT(tile->id));
- xe_vm_set_validation_exec(vm, NULL);
- if (IS_ERR(fence)) {
- err = PTR_ERR(fence);
- xe_validation_retry_on_oom(&ctx, &err);
- goto unlock_dma_resv;
- }
- }
-
- dma_fence_wait(fence, false);
- dma_fence_put(fence);
-
-unlock_dma_resv:
- xe_validation_ctx_fini(&ctx);
- if (err == -EAGAIN)
- goto retry_userptr;
-
- return err;
-}
-
-static struct xe_vm *asid_to_vm(struct xe_device *xe, u32 asid)
-{
- struct xe_vm *vm;
-
- down_read(&xe->usm.lock);
- vm = xa_load(&xe->usm.asid_to_vm, asid);
- if (vm && xe_vm_in_fault_mode(vm))
- xe_vm_get(vm);
- else
- vm = ERR_PTR(-EINVAL);
- up_read(&xe->usm.lock);
-
- return vm;
-}
-
-static int handle_pagefault(struct xe_gt *gt, struct pagefault *pf)
-{
- struct xe_device *xe = gt_to_xe(gt);
- struct xe_vm *vm;
- struct xe_vma *vma = NULL;
- int err;
- bool atomic;
-
- /* SW isn't expected to handle TRTT faults */
- if (pf->trva_fault)
- return -EFAULT;
-
- vm = asid_to_vm(xe, pf->asid);
- if (IS_ERR(vm))
- return PTR_ERR(vm);
-
- /*
- * TODO: Change to read lock? Using write lock for simplicity.
- */
- down_write(&vm->lock);
-
- if (xe_vm_is_closed(vm)) {
- err = -ENOENT;
- goto unlock_vm;
- }
-
- vma = xe_vm_find_vma_by_addr(vm, pf->page_addr);
- if (!vma) {
- err = -EINVAL;
- goto unlock_vm;
- }
-
- atomic = access_is_atomic(pf->access_type);
-
- if (xe_vma_is_cpu_addr_mirror(vma))
- err = xe_svm_handle_pagefault(vm, vma, gt,
- pf->page_addr, atomic);
- else
- err = handle_vma_pagefault(gt, vma, atomic);
-
-unlock_vm:
- if (!err)
- vm->usm.last_fault_vma = vma;
- up_write(&vm->lock);
- xe_vm_put(vm);
-
- return err;
-}
-
-static int send_pagefault_reply(struct xe_guc *guc,
- struct xe_guc_pagefault_reply *reply)
-{
- u32 action[] = {
- XE_GUC_ACTION_PAGE_FAULT_RES_DESC,
- reply->dw0,
- reply->dw1,
- };
-
- return xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action), 0, 0);
-}
-
-static void print_pagefault(struct xe_gt *gt, struct pagefault *pf)
-{
- xe_gt_dbg(gt, "\n\tASID: %d\n"
- "\tVFID: %d\n"
- "\tPDATA: 0x%04x\n"
- "\tFaulted Address: 0x%08x%08x\n"
- "\tFaultType: %d\n"
- "\tAccessType: %d\n"
- "\tFaultLevel: %d\n"
- "\tEngineClass: %d %s\n"
- "\tEngineInstance: %d\n",
- pf->asid, pf->vfid, pf->pdata, upper_32_bits(pf->page_addr),
- lower_32_bits(pf->page_addr),
- pf->fault_type, pf->access_type, pf->fault_level,
- pf->engine_class, xe_hw_engine_class_to_str(pf->engine_class),
- pf->engine_instance);
-}
-
-#define PF_MSG_LEN_DW 4
-
-static bool get_pagefault(struct pf_queue *pf_queue, struct pagefault *pf)
-{
- const struct xe_guc_pagefault_desc *desc;
- bool ret = false;
-
- spin_lock_irq(&pf_queue->lock);
- if (pf_queue->tail != pf_queue->head) {
- desc = (const struct xe_guc_pagefault_desc *)
- (pf_queue->data + pf_queue->tail);
-
- pf->fault_level = FIELD_GET(PFD_FAULT_LEVEL, desc->dw0);
- pf->trva_fault = FIELD_GET(XE2_PFD_TRVA_FAULT, desc->dw0);
- pf->engine_class = FIELD_GET(PFD_ENG_CLASS, desc->dw0);
- pf->engine_instance = FIELD_GET(PFD_ENG_INSTANCE, desc->dw0);
- pf->pdata = FIELD_GET(PFD_PDATA_HI, desc->dw1) <<
- PFD_PDATA_HI_SHIFT;
- pf->pdata |= FIELD_GET(PFD_PDATA_LO, desc->dw0);
- pf->asid = FIELD_GET(PFD_ASID, desc->dw1);
- pf->vfid = FIELD_GET(PFD_VFID, desc->dw2);
- pf->access_type = FIELD_GET(PFD_ACCESS_TYPE, desc->dw2);
- pf->fault_type = FIELD_GET(PFD_FAULT_TYPE, desc->dw2);
- pf->page_addr = (u64)(FIELD_GET(PFD_VIRTUAL_ADDR_HI, desc->dw3)) <<
- PFD_VIRTUAL_ADDR_HI_SHIFT;
- pf->page_addr |= FIELD_GET(PFD_VIRTUAL_ADDR_LO, desc->dw2) <<
- PFD_VIRTUAL_ADDR_LO_SHIFT;
-
- pf_queue->tail = (pf_queue->tail + PF_MSG_LEN_DW) %
- pf_queue->num_dw;
- ret = true;
- }
- spin_unlock_irq(&pf_queue->lock);
-
- return ret;
-}
-
-static bool pf_queue_full(struct pf_queue *pf_queue)
-{
- lockdep_assert_held(&pf_queue->lock);
-
- return CIRC_SPACE(pf_queue->head, pf_queue->tail,
- pf_queue->num_dw) <=
- PF_MSG_LEN_DW;
-}
-
-int xe_guc_pagefault_handler(struct xe_guc *guc, u32 *msg, u32 len)
-{
- struct xe_gt *gt = guc_to_gt(guc);
- struct pf_queue *pf_queue;
- unsigned long flags;
- u32 asid;
- bool full;
-
- if (unlikely(len != PF_MSG_LEN_DW))
- return -EPROTO;
-
- asid = FIELD_GET(PFD_ASID, msg[1]);
- pf_queue = gt->usm.pf_queue + (asid % NUM_PF_QUEUE);
-
- /*
- * The below logic doesn't work unless PF_QUEUE_NUM_DW % PF_MSG_LEN_DW == 0
- */
- xe_gt_assert(gt, !(pf_queue->num_dw % PF_MSG_LEN_DW));
-
- spin_lock_irqsave(&pf_queue->lock, flags);
- full = pf_queue_full(pf_queue);
- if (!full) {
- memcpy(pf_queue->data + pf_queue->head, msg, len * sizeof(u32));
- pf_queue->head = (pf_queue->head + len) %
- pf_queue->num_dw;
- queue_work(gt->usm.pf_wq, &pf_queue->worker);
- } else {
- xe_gt_warn(gt, "PageFault Queue full, shouldn't be possible\n");
- }
- spin_unlock_irqrestore(&pf_queue->lock, flags);
-
- return full ? -ENOSPC : 0;
-}
-
-#define USM_QUEUE_MAX_RUNTIME_MS 20
-
-static void pf_queue_work_func(struct work_struct *w)
-{
- struct pf_queue *pf_queue = container_of(w, struct pf_queue, worker);
- struct xe_gt *gt = pf_queue->gt;
- struct xe_guc_pagefault_reply reply = {};
- struct pagefault pf = {};
- unsigned long threshold;
- int ret;
-
- threshold = jiffies + msecs_to_jiffies(USM_QUEUE_MAX_RUNTIME_MS);
-
- while (get_pagefault(pf_queue, &pf)) {
- ret = handle_pagefault(gt, &pf);
- if (unlikely(ret)) {
- print_pagefault(gt, &pf);
- pf.fault_unsuccessful = 1;
- xe_gt_dbg(gt, "Fault response: Unsuccessful %pe\n", ERR_PTR(ret));
- }
-
- reply.dw0 = FIELD_PREP(PFR_VALID, 1) |
- FIELD_PREP(PFR_SUCCESS, pf.fault_unsuccessful) |
- FIELD_PREP(PFR_REPLY, PFR_ACCESS) |
- FIELD_PREP(PFR_DESC_TYPE, FAULT_RESPONSE_DESC) |
- FIELD_PREP(PFR_ASID, pf.asid);
-
- reply.dw1 = FIELD_PREP(PFR_VFID, pf.vfid) |
- FIELD_PREP(PFR_ENG_INSTANCE, pf.engine_instance) |
- FIELD_PREP(PFR_ENG_CLASS, pf.engine_class) |
- FIELD_PREP(PFR_PDATA, pf.pdata);
-
- send_pagefault_reply(>->uc.guc, &reply);
-
- if (time_after(jiffies, threshold) &&
- pf_queue->tail != pf_queue->head) {
- queue_work(gt->usm.pf_wq, w);
- break;
- }
- }
-}
-
-static void acc_queue_work_func(struct work_struct *w);
-
-static void pagefault_fini(void *arg)
-{
- struct xe_gt *gt = arg;
- struct xe_device *xe = gt_to_xe(gt);
-
- if (!xe->info.has_usm)
- return;
-
- destroy_workqueue(gt->usm.acc_wq);
- destroy_workqueue(gt->usm.pf_wq);
-}
-
-static int xe_alloc_pf_queue(struct xe_gt *gt, struct pf_queue *pf_queue)
-{
- struct xe_device *xe = gt_to_xe(gt);
- xe_dss_mask_t all_dss;
- int num_dss, num_eus;
-
- bitmap_or(all_dss, gt->fuse_topo.g_dss_mask, gt->fuse_topo.c_dss_mask,
- XE_MAX_DSS_FUSE_BITS);
-
- num_dss = bitmap_weight(all_dss, XE_MAX_DSS_FUSE_BITS);
- num_eus = bitmap_weight(gt->fuse_topo.eu_mask_per_dss,
- XE_MAX_EU_FUSE_BITS) * num_dss;
-
- /*
- * user can issue separate page faults per EU and per CS
- *
- * XXX: Multiplier required as compute UMD are getting PF queue errors
- * without it. Follow on why this multiplier is required.
- */
-#define PF_MULTIPLIER 8
- pf_queue->num_dw =
- (num_eus + XE_NUM_HW_ENGINES) * PF_MSG_LEN_DW * PF_MULTIPLIER;
- pf_queue->num_dw = roundup_pow_of_two(pf_queue->num_dw);
-#undef PF_MULTIPLIER
-
- pf_queue->gt = gt;
- pf_queue->data = devm_kcalloc(xe->drm.dev, pf_queue->num_dw,
- sizeof(u32), GFP_KERNEL);
- if (!pf_queue->data)
- return -ENOMEM;
-
- spin_lock_init(&pf_queue->lock);
- INIT_WORK(&pf_queue->worker, pf_queue_work_func);
-
- return 0;
-}
-
-int xe_gt_pagefault_init(struct xe_gt *gt)
-{
- struct xe_device *xe = gt_to_xe(gt);
- int i, ret = 0;
-
- if (!xe->info.has_usm)
- return 0;
-
- for (i = 0; i < NUM_PF_QUEUE; ++i) {
- ret = xe_alloc_pf_queue(gt, >->usm.pf_queue[i]);
- if (ret)
- return ret;
- }
- for (i = 0; i < NUM_ACC_QUEUE; ++i) {
- gt->usm.acc_queue[i].gt = gt;
- spin_lock_init(>->usm.acc_queue[i].lock);
- INIT_WORK(>->usm.acc_queue[i].worker, acc_queue_work_func);
- }
-
- gt->usm.pf_wq = alloc_workqueue("xe_gt_page_fault_work_queue",
- WQ_UNBOUND | WQ_HIGHPRI, NUM_PF_QUEUE);
- if (!gt->usm.pf_wq)
- return -ENOMEM;
-
- gt->usm.acc_wq = alloc_workqueue("xe_gt_access_counter_work_queue",
- WQ_UNBOUND | WQ_HIGHPRI,
- NUM_ACC_QUEUE);
- if (!gt->usm.acc_wq) {
- destroy_workqueue(gt->usm.pf_wq);
- return -ENOMEM;
- }
-
- return devm_add_action_or_reset(xe->drm.dev, pagefault_fini, gt);
-}
-
-void xe_gt_pagefault_reset(struct xe_gt *gt)
-{
- struct xe_device *xe = gt_to_xe(gt);
- int i;
-
- if (!xe->info.has_usm)
- return;
-
- for (i = 0; i < NUM_PF_QUEUE; ++i) {
- spin_lock_irq(>->usm.pf_queue[i].lock);
- gt->usm.pf_queue[i].head = 0;
- gt->usm.pf_queue[i].tail = 0;
- spin_unlock_irq(>->usm.pf_queue[i].lock);
- }
-
- for (i = 0; i < NUM_ACC_QUEUE; ++i) {
- spin_lock(>->usm.acc_queue[i].lock);
- gt->usm.acc_queue[i].head = 0;
- gt->usm.acc_queue[i].tail = 0;
- spin_unlock(>->usm.acc_queue[i].lock);
- }
-}
-
-static int granularity_in_byte(int val)
-{
- switch (val) {
- case 0:
- return SZ_128K;
- case 1:
- return SZ_2M;
- case 2:
- return SZ_16M;
- case 3:
- return SZ_64M;
- default:
- return 0;
- }
-}
-
-static int sub_granularity_in_byte(int val)
-{
- return (granularity_in_byte(val) / 32);
-}
-
-static void print_acc(struct xe_gt *gt, struct acc *acc)
-{
- xe_gt_warn(gt, "Access counter request:\n"
- "\tType: %s\n"
- "\tASID: %d\n"
- "\tVFID: %d\n"
- "\tEngine: %d:%d\n"
- "\tGranularity: 0x%x KB Region/ %d KB sub-granularity\n"
- "\tSub_Granularity Vector: 0x%08x\n"
- "\tVA Range base: 0x%016llx\n",
- acc->access_type ? "AC_NTFY_VAL" : "AC_TRIG_VAL",
- acc->asid, acc->vfid, acc->engine_class, acc->engine_instance,
- granularity_in_byte(acc->granularity) / SZ_1K,
- sub_granularity_in_byte(acc->granularity) / SZ_1K,
- acc->sub_granularity, acc->va_range_base);
-}
-
-static struct xe_vma *get_acc_vma(struct xe_vm *vm, struct acc *acc)
-{
- u64 page_va = acc->va_range_base + (ffs(acc->sub_granularity) - 1) *
- sub_granularity_in_byte(acc->granularity);
-
- return xe_vm_find_overlapping_vma(vm, page_va, SZ_4K);
-}
-
-static int handle_acc(struct xe_gt *gt, struct acc *acc)
-{
- struct xe_device *xe = gt_to_xe(gt);
- struct xe_tile *tile = gt_to_tile(gt);
- struct xe_validation_ctx ctx;
- struct drm_exec exec;
- struct xe_vm *vm;
- struct xe_vma *vma;
- int ret = 0;
-
- /* We only support ACC_TRIGGER at the moment */
- if (acc->access_type != ACC_TRIGGER)
- return -EINVAL;
-
- vm = asid_to_vm(xe, acc->asid);
- if (IS_ERR(vm))
- return PTR_ERR(vm);
-
- down_read(&vm->lock);
-
- /* Lookup VMA */
- vma = get_acc_vma(vm, acc);
- if (!vma) {
- ret = -EINVAL;
- goto unlock_vm;
- }
-
- trace_xe_vma_acc(vma);
-
- /* Userptr or null can't be migrated, nothing to do */
- if (xe_vma_has_no_bo(vma))
- goto unlock_vm;
-
- /* Lock VM and BOs dma-resv */
- xe_validation_ctx_init(&ctx, &vm->xe->val, &exec, (struct xe_val_flags) {});
- drm_exec_until_all_locked(&exec) {
- ret = xe_pf_begin(&exec, vma, IS_DGFX(vm->xe), tile->mem.vram);
- drm_exec_retry_on_contention(&exec);
- xe_validation_retry_on_oom(&ctx, &ret);
- }
-
- xe_validation_ctx_fini(&ctx);
-unlock_vm:
- up_read(&vm->lock);
- xe_vm_put(vm);
-
- return ret;
-}
-
-#define make_u64(hi__, low__) ((u64)(hi__) << 32 | (u64)(low__))
-
-#define ACC_MSG_LEN_DW 4
-
-static bool get_acc(struct acc_queue *acc_queue, struct acc *acc)
-{
- const struct xe_guc_acc_desc *desc;
- bool ret = false;
-
- spin_lock(&acc_queue->lock);
- if (acc_queue->tail != acc_queue->head) {
- desc = (const struct xe_guc_acc_desc *)
- (acc_queue->data + acc_queue->tail);
-
- acc->granularity = FIELD_GET(ACC_GRANULARITY, desc->dw2);
- acc->sub_granularity = FIELD_GET(ACC_SUBG_HI, desc->dw1) << 31 |
- FIELD_GET(ACC_SUBG_LO, desc->dw0);
- acc->engine_class = FIELD_GET(ACC_ENG_CLASS, desc->dw1);
- acc->engine_instance = FIELD_GET(ACC_ENG_INSTANCE, desc->dw1);
- acc->asid = FIELD_GET(ACC_ASID, desc->dw1);
- acc->vfid = FIELD_GET(ACC_VFID, desc->dw2);
- acc->access_type = FIELD_GET(ACC_TYPE, desc->dw0);
- acc->va_range_base = make_u64(desc->dw3 & ACC_VIRTUAL_ADDR_RANGE_HI,
- desc->dw2 & ACC_VIRTUAL_ADDR_RANGE_LO);
-
- acc_queue->tail = (acc_queue->tail + ACC_MSG_LEN_DW) %
- ACC_QUEUE_NUM_DW;
- ret = true;
- }
- spin_unlock(&acc_queue->lock);
-
- return ret;
-}
-
-static void acc_queue_work_func(struct work_struct *w)
-{
- struct acc_queue *acc_queue = container_of(w, struct acc_queue, worker);
- struct xe_gt *gt = acc_queue->gt;
- struct acc acc = {};
- unsigned long threshold;
- int ret;
-
- threshold = jiffies + msecs_to_jiffies(USM_QUEUE_MAX_RUNTIME_MS);
-
- while (get_acc(acc_queue, &acc)) {
- ret = handle_acc(gt, &acc);
- if (unlikely(ret)) {
- print_acc(gt, &acc);
- xe_gt_warn(gt, "ACC: Unsuccessful %pe\n", ERR_PTR(ret));
- }
-
- if (time_after(jiffies, threshold) &&
- acc_queue->tail != acc_queue->head) {
- queue_work(gt->usm.acc_wq, w);
- break;
- }
- }
-}
-
-static bool acc_queue_full(struct acc_queue *acc_queue)
-{
- lockdep_assert_held(&acc_queue->lock);
-
- return CIRC_SPACE(acc_queue->head, acc_queue->tail, ACC_QUEUE_NUM_DW) <=
- ACC_MSG_LEN_DW;
-}
-
-int xe_guc_access_counter_notify_handler(struct xe_guc *guc, u32 *msg, u32 len)
-{
- struct xe_gt *gt = guc_to_gt(guc);
- struct acc_queue *acc_queue;
- u32 asid;
- bool full;
-
- /*
- * The below logic doesn't work unless ACC_QUEUE_NUM_DW % ACC_MSG_LEN_DW == 0
- */
- BUILD_BUG_ON(ACC_QUEUE_NUM_DW % ACC_MSG_LEN_DW);
-
- if (unlikely(len != ACC_MSG_LEN_DW))
- return -EPROTO;
-
- asid = FIELD_GET(ACC_ASID, msg[1]);
- acc_queue = >->usm.acc_queue[asid % NUM_ACC_QUEUE];
-
- spin_lock(&acc_queue->lock);
- full = acc_queue_full(acc_queue);
- if (!full) {
- memcpy(acc_queue->data + acc_queue->head, msg,
- len * sizeof(u32));
- acc_queue->head = (acc_queue->head + len) % ACC_QUEUE_NUM_DW;
- queue_work(gt->usm.acc_wq, &acc_queue->worker);
- } else {
- xe_gt_warn(gt, "ACC Queue full, dropping ACC\n");
- }
- spin_unlock(&acc_queue->lock);
-
- return full ? -ENOSPC : 0;
-}
diff --git a/drivers/gpu/drm/xe/xe_gt_pagefault.h b/drivers/gpu/drm/xe/xe_gt_pagefault.h
deleted file mode 100644
index 839c065a5e4c..000000000000
--- a/drivers/gpu/drm/xe/xe_gt_pagefault.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* SPDX-License-Identifier: MIT */
-/*
- * Copyright © 2022 Intel Corporation
- */
-
-#ifndef _XE_GT_PAGEFAULT_H_
-#define _XE_GT_PAGEFAULT_H_
-
-#include <linux/types.h>
-
-struct xe_gt;
-struct xe_guc;
-
-int xe_gt_pagefault_init(struct xe_gt *gt);
-void xe_gt_pagefault_reset(struct xe_gt *gt);
-int xe_guc_pagefault_handler(struct xe_guc *guc, u32 *msg, u32 len);
-int xe_guc_access_counter_notify_handler(struct xe_guc *guc, u32 *msg, u32 len);
-
-#endif /* _XE_GT_PAGEFAULT_ */
diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h
index 0b525643a048..0a728180b6fe 100644
--- a/drivers/gpu/drm/xe/xe_gt_types.h
+++ b/drivers/gpu/drm/xe/xe_gt_types.h
@@ -220,71 +220,6 @@ struct xe_gt {
* operations (e.g. migrations, fixing page tables)
*/
u16 reserved_bcs_instance;
- /** @usm.pf_wq: page fault work queue, unbound, high priority */
- struct workqueue_struct *pf_wq;
- /** @usm.acc_wq: access counter work queue, unbound, high priority */
- struct workqueue_struct *acc_wq;
- /**
- * @usm.pf_queue: Page fault queue used to sync faults so faults can
- * be processed not under the GuC CT lock. The queue is sized so
- * it can sync all possible faults (1 per physical engine).
- * Multiple queues exist for page faults from different VMs to be
- * processed in parallel.
- */
- struct pf_queue {
- /** @usm.pf_queue.gt: back pointer to GT */
- struct xe_gt *gt;
- /** @usm.pf_queue.data: data in the page fault queue */
- u32 *data;
- /**
- * @usm.pf_queue.num_dw: number of DWORDS in the page
- * fault queue. Dynamically calculated based on the number
- * of compute resources available.
- */
- u32 num_dw;
- /**
- * @usm.pf_queue.tail: tail pointer in DWs for page fault queue,
- * moved by worker which processes faults (consumer).
- */
- u16 tail;
- /**
- * @usm.pf_queue.head: head pointer in DWs for page fault queue,
- * moved by G2H handler (producer).
- */
- u16 head;
- /** @usm.pf_queue.lock: protects page fault queue */
- spinlock_t lock;
- /** @usm.pf_queue.worker: to process page faults */
- struct work_struct worker;
-#define NUM_PF_QUEUE 4
- } pf_queue[NUM_PF_QUEUE];
- /**
- * @usm.acc_queue: Same as page fault queue, cannot process access
- * counters under CT lock.
- */
- struct acc_queue {
- /** @usm.acc_queue.gt: back pointer to GT */
- struct xe_gt *gt;
-#define ACC_QUEUE_NUM_DW 128
- /** @usm.acc_queue.data: data in the page fault queue */
- u32 data[ACC_QUEUE_NUM_DW];
- /**
- * @usm.acc_queue.tail: tail pointer in DWs for access counter queue,
- * moved by worker which processes counters
- * (consumer).
- */
- u16 tail;
- /**
- * @usm.acc_queue.head: head pointer in DWs for access counter queue,
- * moved by G2H handler (producer).
- */
- u16 head;
- /** @usm.acc_queue.lock: protects page fault queue */
- spinlock_t lock;
- /** @usm.acc_queue.worker: to process access counters */
- struct work_struct worker;
-#define NUM_ACC_QUEUE 4
- } acc_queue[NUM_ACC_QUEUE];
} usm;
/** @ordered_wq: used to serialize GT resets and TDRs */
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* ✗ CI.checkpatch: warning for Pagefault refactor (rev2)
2025-10-28 3:58 [PATCH v3 0/7] Pagefault refactor Matthew Brost
` (6 preceding siblings ...)
2025-10-28 3:58 ` [PATCH v3 7/7] drm/xe: Remove unused GT page fault code Matthew Brost
@ 2025-10-28 4:05 ` Patchwork
2025-10-28 4:06 ` ✓ CI.KUnit: success " Patchwork
` (2 subsequent siblings)
10 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2025-10-28 4:05 UTC (permalink / raw)
To: Matthew Brost; +Cc: intel-xe
== Series Details ==
Series: Pagefault refactor (rev2)
URL : https://patchwork.freedesktop.org/series/156508/
State : warning
== Summary ==
+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
f867e605613af1770f90c4b0afd4a8f06424d1f0
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 05f4c3a906e5be22b70775d7bda7c25688acf82a
Author: Matthew Brost <matthew.brost@intel.com>
Date: Mon Oct 27 20:58:43 2025 -0700
drm/xe: Remove unused GT page fault code
With the Xe page fault layer and GuC page layer in place, this is now
dead code and can be removed. ACC code is also removed, but this was
dead code.
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
+ /mt/dim checkpatch de43fe70c436c359e7478a5532d873f87357cb4e drm-intel
b391b45c2bdd drm/xe: Stub out new pagefault layer
-:25: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#25:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 227 lines checked
9f86bd033fc8 drm/xe: Implement xe_pagefault_init
093838c44b47 drm/xe: Implement xe_pagefault_reset
383e3fe70f66 drm/xe: Implement xe_pagefault_handler
cd7fd0d75ca2 drm/xe: Implement xe_pagefault_queue_work
065089569dea drm/xe: Add xe_guc_pagefault layer
-:95: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#95:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 187 lines checked
05f4c3a906e5 drm/xe: Remove unused GT page fault code
-:13: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#13:
deleted file mode 100644
total: 0 errors, 1 warnings, 0 checks, 71 lines checked
^ permalink raw reply [flat|nested] 16+ messages in thread* ✓ CI.KUnit: success for Pagefault refactor (rev2)
2025-10-28 3:58 [PATCH v3 0/7] Pagefault refactor Matthew Brost
` (7 preceding siblings ...)
2025-10-28 4:05 ` ✗ CI.checkpatch: warning for Pagefault refactor (rev2) Patchwork
@ 2025-10-28 4:06 ` Patchwork
2025-10-28 4:46 ` ✗ Xe.CI.BAT: failure " Patchwork
2025-10-28 9:30 ` ✗ Xe.CI.Full: " Patchwork
10 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2025-10-28 4:06 UTC (permalink / raw)
To: Matthew Brost; +Cc: intel-xe
== Series Details ==
Series: Pagefault refactor (rev2)
URL : https://patchwork.freedesktop.org/series/156508/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[04:05:33] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[04:05:37] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[04:06:08] Starting KUnit Kernel (1/1)...
[04:06:08] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[04:06:08] ================== guc_buf (11 subtests) ===================
[04:06:08] [PASSED] test_smallest
[04:06:08] [PASSED] test_largest
[04:06:08] [PASSED] test_granular
[04:06:08] [PASSED] test_unique
[04:06:08] [PASSED] test_overlap
[04:06:08] [PASSED] test_reusable
[04:06:08] [PASSED] test_too_big
[04:06:08] [PASSED] test_flush
[04:06:08] [PASSED] test_lookup
[04:06:08] [PASSED] test_data
[04:06:08] [PASSED] test_class
[04:06:08] ===================== [PASSED] guc_buf =====================
[04:06:08] =================== guc_dbm (7 subtests) ===================
[04:06:08] [PASSED] test_empty
[04:06:08] [PASSED] test_default
[04:06:08] ======================== test_size ========================
[04:06:08] [PASSED] 4
[04:06:08] [PASSED] 8
[04:06:08] [PASSED] 32
[04:06:08] [PASSED] 256
[04:06:08] ==================== [PASSED] test_size ====================
[04:06:08] ======================= test_reuse ========================
[04:06:08] [PASSED] 4
[04:06:08] [PASSED] 8
[04:06:08] [PASSED] 32
[04:06:08] [PASSED] 256
[04:06:08] =================== [PASSED] test_reuse ====================
[04:06:08] =================== test_range_overlap ====================
[04:06:08] [PASSED] 4
[04:06:08] [PASSED] 8
[04:06:08] [PASSED] 32
[04:06:08] [PASSED] 256
[04:06:08] =============== [PASSED] test_range_overlap ================
[04:06:08] =================== test_range_compact ====================
[04:06:08] [PASSED] 4
[04:06:08] [PASSED] 8
[04:06:08] [PASSED] 32
[04:06:08] [PASSED] 256
[04:06:08] =============== [PASSED] test_range_compact ================
[04:06:08] ==================== test_range_spare =====================
[04:06:08] [PASSED] 4
[04:06:08] [PASSED] 8
[04:06:08] [PASSED] 32
[04:06:08] [PASSED] 256
[04:06:08] ================ [PASSED] test_range_spare =================
[04:06:08] ===================== [PASSED] guc_dbm =====================
[04:06:08] =================== guc_idm (6 subtests) ===================
[04:06:08] [PASSED] bad_init
[04:06:08] [PASSED] no_init
[04:06:08] [PASSED] init_fini
[04:06:08] [PASSED] check_used
[04:06:08] [PASSED] check_quota
[04:06:08] [PASSED] check_all
[04:06:08] ===================== [PASSED] guc_idm =====================
[04:06:08] ================== no_relay (3 subtests) ===================
[04:06:08] [PASSED] xe_drops_guc2pf_if_not_ready
[04:06:08] [PASSED] xe_drops_guc2vf_if_not_ready
[04:06:08] [PASSED] xe_rejects_send_if_not_ready
[04:06:08] ==================== [PASSED] no_relay =====================
[04:06:08] ================== pf_relay (14 subtests) ==================
[04:06:08] [PASSED] pf_rejects_guc2pf_too_short
[04:06:08] [PASSED] pf_rejects_guc2pf_too_long
[04:06:08] [PASSED] pf_rejects_guc2pf_no_payload
[04:06:08] [PASSED] pf_fails_no_payload
[04:06:08] [PASSED] pf_fails_bad_origin
[04:06:08] [PASSED] pf_fails_bad_type
[04:06:08] [PASSED] pf_txn_reports_error
[04:06:08] [PASSED] pf_txn_sends_pf2guc
[04:06:08] [PASSED] pf_sends_pf2guc
[04:06:08] [SKIPPED] pf_loopback_nop
[04:06:08] [SKIPPED] pf_loopback_echo
[04:06:08] [SKIPPED] pf_loopback_fail
[04:06:08] [SKIPPED] pf_loopback_busy
[04:06:08] [SKIPPED] pf_loopback_retry
[04:06:08] ==================== [PASSED] pf_relay =====================
[04:06:08] ================== vf_relay (3 subtests) ===================
[04:06:08] [PASSED] vf_rejects_guc2vf_too_short
[04:06:08] [PASSED] vf_rejects_guc2vf_too_long
[04:06:08] [PASSED] vf_rejects_guc2vf_no_payload
[04:06:08] ==================== [PASSED] vf_relay =====================
[04:06:08] ===================== lmtt (1 subtest) =====================
[04:06:08] ======================== test_ops =========================
[04:06:08] [PASSED] 2-level
[04:06:08] [PASSED] multi-level
[04:06:08] ==================== [PASSED] test_ops =====================
[04:06:08] ====================== [PASSED] lmtt =======================
[04:06:08] ================= pf_service (11 subtests) =================
[04:06:08] [PASSED] pf_negotiate_any
[04:06:08] [PASSED] pf_negotiate_base_match
[04:06:08] [PASSED] pf_negotiate_base_newer
[04:06:08] [PASSED] pf_negotiate_base_next
[04:06:08] [SKIPPED] pf_negotiate_base_older
[04:06:08] [PASSED] pf_negotiate_base_prev
[04:06:08] [PASSED] pf_negotiate_latest_match
[04:06:08] [PASSED] pf_negotiate_latest_newer
[04:06:08] [PASSED] pf_negotiate_latest_next
[04:06:08] [SKIPPED] pf_negotiate_latest_older
[04:06:08] [SKIPPED] pf_negotiate_latest_prev
[04:06:08] =================== [PASSED] pf_service ====================
[04:06:08] ================= xe_guc_g2g (2 subtests) ==================
[04:06:08] ============== xe_live_guc_g2g_kunit_default ==============
[04:06:08] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[04:06:08] ============== xe_live_guc_g2g_kunit_allmem ===============
[04:06:08] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[04:06:08] =================== [SKIPPED] xe_guc_g2g ===================
[04:06:08] =================== xe_mocs (2 subtests) ===================
[04:06:08] ================ xe_live_mocs_kernel_kunit ================
[04:06:08] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[04:06:08] ================ xe_live_mocs_reset_kunit =================
[04:06:08] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[04:06:08] ==================== [SKIPPED] xe_mocs =====================
[04:06:08] ================= xe_migrate (2 subtests) ==================
[04:06:08] ================= xe_migrate_sanity_kunit =================
[04:06:08] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[04:06:08] ================== xe_validate_ccs_kunit ==================
[04:06:08] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[04:06:08] =================== [SKIPPED] xe_migrate ===================
[04:06:08] ================== xe_dma_buf (1 subtest) ==================
[04:06:08] ==================== xe_dma_buf_kunit =====================
[04:06:08] ================ [SKIPPED] xe_dma_buf_kunit ================
[04:06:08] =================== [SKIPPED] xe_dma_buf ===================
[04:06:08] ================= xe_bo_shrink (1 subtest) =================
[04:06:08] =================== xe_bo_shrink_kunit ====================
[04:06:08] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[04:06:08] ================== [SKIPPED] xe_bo_shrink ==================
[04:06:08] ==================== xe_bo (2 subtests) ====================
[04:06:08] ================== xe_ccs_migrate_kunit ===================
[04:06:08] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[04:06:08] ==================== xe_bo_evict_kunit ====================
[04:06:08] =============== [SKIPPED] xe_bo_evict_kunit ================
[04:06:08] ===================== [SKIPPED] xe_bo ======================
[04:06:08] ==================== args (11 subtests) ====================
[04:06:08] [PASSED] count_args_test
[04:06:08] [PASSED] call_args_example
[04:06:08] [PASSED] call_args_test
[04:06:08] [PASSED] drop_first_arg_example
[04:06:08] [PASSED] drop_first_arg_test
[04:06:08] [PASSED] first_arg_example
[04:06:08] [PASSED] first_arg_test
[04:06:08] [PASSED] last_arg_example
[04:06:08] [PASSED] last_arg_test
[04:06:08] [PASSED] pick_arg_example
[04:06:08] [PASSED] sep_comma_example
[04:06:08] ====================== [PASSED] args =======================
[04:06:08] =================== xe_pci (3 subtests) ====================
[04:06:08] ==================== check_graphics_ip ====================
[04:06:08] [PASSED] 12.00 Xe_LP
[04:06:08] [PASSED] 12.10 Xe_LP+
[04:06:08] [PASSED] 12.55 Xe_HPG
[04:06:08] [PASSED] 12.60 Xe_HPC
[04:06:08] [PASSED] 12.70 Xe_LPG
[04:06:08] [PASSED] 12.71 Xe_LPG
[04:06:08] [PASSED] 12.74 Xe_LPG+
[04:06:08] [PASSED] 20.01 Xe2_HPG
[04:06:08] [PASSED] 20.02 Xe2_HPG
[04:06:08] [PASSED] 20.04 Xe2_LPG
[04:06:08] [PASSED] 30.00 Xe3_LPG
[04:06:08] [PASSED] 30.01 Xe3_LPG
[04:06:08] [PASSED] 30.03 Xe3_LPG
[04:06:08] [PASSED] 30.04 Xe3_LPG
[04:06:08] [PASSED] 30.05 Xe3_LPG
[04:06:08] [PASSED] 35.11 Xe3p_XPC
[04:06:08] ================ [PASSED] check_graphics_ip ================
[04:06:08] ===================== check_media_ip ======================
[04:06:08] [PASSED] 12.00 Xe_M
[04:06:08] [PASSED] 12.55 Xe_HPM
[04:06:08] [PASSED] 13.00 Xe_LPM+
[04:06:08] [PASSED] 13.01 Xe2_HPM
[04:06:08] [PASSED] 20.00 Xe2_LPM
[04:06:08] [PASSED] 30.00 Xe3_LPM
[04:06:08] [PASSED] 30.02 Xe3_LPM
[04:06:08] [PASSED] 35.00 Xe3p_LPM
[04:06:08] [PASSED] 35.03 Xe3p_HPM
[04:06:08] ================= [PASSED] check_media_ip ==================
[04:06:08] =================== check_platform_desc ===================
[04:06:08] [PASSED] 0x9A60 (TIGERLAKE)
[04:06:08] [PASSED] 0x9A68 (TIGERLAKE)
[04:06:08] [PASSED] 0x9A70 (TIGERLAKE)
[04:06:08] [PASSED] 0x9A40 (TIGERLAKE)
[04:06:08] [PASSED] 0x9A49 (TIGERLAKE)
[04:06:08] [PASSED] 0x9A59 (TIGERLAKE)
[04:06:08] [PASSED] 0x9A78 (TIGERLAKE)
[04:06:08] [PASSED] 0x9AC0 (TIGERLAKE)
[04:06:08] [PASSED] 0x9AC9 (TIGERLAKE)
[04:06:08] [PASSED] 0x9AD9 (TIGERLAKE)
[04:06:08] [PASSED] 0x9AF8 (TIGERLAKE)
[04:06:08] [PASSED] 0x4C80 (ROCKETLAKE)
[04:06:08] [PASSED] 0x4C8A (ROCKETLAKE)
[04:06:08] [PASSED] 0x4C8B (ROCKETLAKE)
[04:06:08] [PASSED] 0x4C8C (ROCKETLAKE)
[04:06:08] [PASSED] 0x4C90 (ROCKETLAKE)
[04:06:08] [PASSED] 0x4C9A (ROCKETLAKE)
[04:06:08] [PASSED] 0x4680 (ALDERLAKE_S)
[04:06:08] [PASSED] 0x4682 (ALDERLAKE_S)
[04:06:08] [PASSED] 0x4688 (ALDERLAKE_S)
[04:06:08] [PASSED] 0x468A (ALDERLAKE_S)
[04:06:08] [PASSED] 0x468B (ALDERLAKE_S)
[04:06:08] [PASSED] 0x4690 (ALDERLAKE_S)
[04:06:08] [PASSED] 0x4692 (ALDERLAKE_S)
[04:06:08] [PASSED] 0x4693 (ALDERLAKE_S)
[04:06:08] [PASSED] 0x46A0 (ALDERLAKE_P)
[04:06:08] [PASSED] 0x46A1 (ALDERLAKE_P)
[04:06:08] [PASSED] 0x46A2 (ALDERLAKE_P)
[04:06:08] [PASSED] 0x46A3 (ALDERLAKE_P)
[04:06:08] [PASSED] 0x46A6 (ALDERLAKE_P)
[04:06:08] [PASSED] 0x46A8 (ALDERLAKE_P)
[04:06:08] [PASSED] 0x46AA (ALDERLAKE_P)
[04:06:08] [PASSED] 0x462A (ALDERLAKE_P)
[04:06:08] [PASSED] 0x4626 (ALDERLAKE_P)
[04:06:08] [PASSED] 0x4628 (ALDERLAKE_P)
[04:06:08] [PASSED] 0x46B0 (ALDERLAKE_P)
[04:06:08] [PASSED] 0x46B1 (ALDERLAKE_P)
[04:06:08] [PASSED] 0x46B2 (ALDERLAKE_P)
[04:06:08] [PASSED] 0x46B3 (ALDERLAKE_P)
[04:06:08] [PASSED] 0x46C0 (ALDERLAKE_P)
[04:06:08] [PASSED] 0x46C1 (ALDERLAKE_P)
[04:06:08] [PASSED] 0x46C2 (ALDERLAKE_P)
[04:06:08] [PASSED] 0x46C3 (ALDERLAKE_P)
[04:06:08] [PASSED] 0x46D0 (ALDERLAKE_N)
[04:06:08] [PASSED] 0x46D1 (ALDERLAKE_N)
[04:06:08] [PASSED] 0x46D2 (ALDERLAKE_N)
[04:06:08] [PASSED] 0x46D3 (ALDERLAKE_N)
[04:06:08] [PASSED] 0x46D4 (ALDERLAKE_N)
[04:06:08] [PASSED] 0xA721 (ALDERLAKE_P)
[04:06:08] [PASSED] 0xA7A1 (ALDERLAKE_P)
[04:06:08] [PASSED] 0xA7A9 (ALDERLAKE_P)
[04:06:08] [PASSED] 0xA7AC (ALDERLAKE_P)
[04:06:08] [PASSED] 0xA7AD (ALDERLAKE_P)
[04:06:08] [PASSED] 0xA720 (ALDERLAKE_P)
[04:06:08] [PASSED] 0xA7A0 (ALDERLAKE_P)
[04:06:08] [PASSED] 0xA7A8 (ALDERLAKE_P)
[04:06:08] [PASSED] 0xA7AA (ALDERLAKE_P)
[04:06:08] [PASSED] 0xA7AB (ALDERLAKE_P)
[04:06:08] [PASSED] 0xA780 (ALDERLAKE_S)
[04:06:08] [PASSED] 0xA781 (ALDERLAKE_S)
[04:06:08] [PASSED] 0xA782 (ALDERLAKE_S)
[04:06:08] [PASSED] 0xA783 (ALDERLAKE_S)
[04:06:08] [PASSED] 0xA788 (ALDERLAKE_S)
[04:06:08] [PASSED] 0xA789 (ALDERLAKE_S)
[04:06:08] [PASSED] 0xA78A (ALDERLAKE_S)
[04:06:08] [PASSED] 0xA78B (ALDERLAKE_S)
[04:06:08] [PASSED] 0x4905 (DG1)
[04:06:08] [PASSED] 0x4906 (DG1)
[04:06:08] [PASSED] 0x4907 (DG1)
[04:06:08] [PASSED] 0x4908 (DG1)
[04:06:08] [PASSED] 0x4909 (DG1)
[04:06:08] [PASSED] 0x56C0 (DG2)
[04:06:08] [PASSED] 0x56C2 (DG2)
[04:06:08] [PASSED] 0x56C1 (DG2)
[04:06:08] [PASSED] 0x7D51 (METEORLAKE)
[04:06:08] [PASSED] 0x7DD1 (METEORLAKE)
[04:06:08] [PASSED] 0x7D41 (METEORLAKE)
[04:06:08] [PASSED] 0x7D67 (METEORLAKE)
[04:06:08] [PASSED] 0xB640 (METEORLAKE)
[04:06:08] [PASSED] 0x56A0 (DG2)
[04:06:08] [PASSED] 0x56A1 (DG2)
[04:06:08] [PASSED] 0x56A2 (DG2)
[04:06:08] [PASSED] 0x56BE (DG2)
[04:06:08] [PASSED] 0x56BF (DG2)
[04:06:08] [PASSED] 0x5690 (DG2)
[04:06:08] [PASSED] 0x5691 (DG2)
[04:06:08] [PASSED] 0x5692 (DG2)
[04:06:08] [PASSED] 0x56A5 (DG2)
[04:06:08] [PASSED] 0x56A6 (DG2)
[04:06:08] [PASSED] 0x56B0 (DG2)
[04:06:08] [PASSED] 0x56B1 (DG2)
[04:06:08] [PASSED] 0x56BA (DG2)
[04:06:08] [PASSED] 0x56BB (DG2)
[04:06:08] [PASSED] 0x56BC (DG2)
[04:06:08] [PASSED] 0x56BD (DG2)
[04:06:08] [PASSED] 0x5693 (DG2)
[04:06:08] [PASSED] 0x5694 (DG2)
[04:06:08] [PASSED] 0x5695 (DG2)
[04:06:08] [PASSED] 0x56A3 (DG2)
[04:06:08] [PASSED] 0x56A4 (DG2)
[04:06:08] [PASSED] 0x56B2 (DG2)
[04:06:08] [PASSED] 0x56B3 (DG2)
[04:06:08] [PASSED] 0x5696 (DG2)
[04:06:08] [PASSED] 0x5697 (DG2)
[04:06:08] [PASSED] 0xB69 (PVC)
[04:06:08] [PASSED] 0xB6E (PVC)
[04:06:08] [PASSED] 0xBD4 (PVC)
[04:06:08] [PASSED] 0xBD5 (PVC)
[04:06:08] [PASSED] 0xBD6 (PVC)
[04:06:08] [PASSED] 0xBD7 (PVC)
[04:06:08] [PASSED] 0xBD8 (PVC)
[04:06:08] [PASSED] 0xBD9 (PVC)
[04:06:08] [PASSED] 0xBDA (PVC)
[04:06:08] [PASSED] 0xBDB (PVC)
[04:06:08] [PASSED] 0xBE0 (PVC)
[04:06:08] [PASSED] 0xBE1 (PVC)
[04:06:08] [PASSED] 0xBE5 (PVC)
[04:06:08] [PASSED] 0x7D40 (METEORLAKE)
[04:06:08] [PASSED] 0x7D45 (METEORLAKE)
[04:06:08] [PASSED] 0x7D55 (METEORLAKE)
[04:06:08] [PASSED] 0x7D60 (METEORLAKE)
[04:06:08] [PASSED] 0x7DD5 (METEORLAKE)
[04:06:08] [PASSED] 0x6420 (LUNARLAKE)
[04:06:08] [PASSED] 0x64A0 (LUNARLAKE)
[04:06:08] [PASSED] 0x64B0 (LUNARLAKE)
[04:06:08] [PASSED] 0xE202 (BATTLEMAGE)
[04:06:08] [PASSED] 0xE209 (BATTLEMAGE)
[04:06:08] [PASSED] 0xE20B (BATTLEMAGE)
[04:06:08] [PASSED] 0xE20C (BATTLEMAGE)
[04:06:08] [PASSED] 0xE20D (BATTLEMAGE)
[04:06:08] [PASSED] 0xE210 (BATTLEMAGE)
[04:06:08] [PASSED] 0xE211 (BATTLEMAGE)
[04:06:08] [PASSED] 0xE212 (BATTLEMAGE)
[04:06:08] [PASSED] 0xE216 (BATTLEMAGE)
[04:06:08] [PASSED] 0xE220 (BATTLEMAGE)
[04:06:08] [PASSED] 0xE221 (BATTLEMAGE)
[04:06:08] [PASSED] 0xE222 (BATTLEMAGE)
[04:06:08] [PASSED] 0xE223 (BATTLEMAGE)
[04:06:08] [PASSED] 0xB080 (PANTHERLAKE)
[04:06:08] [PASSED] 0xB081 (PANTHERLAKE)
[04:06:08] [PASSED] 0xB082 (PANTHERLAKE)
[04:06:08] [PASSED] 0xB083 (PANTHERLAKE)
[04:06:08] [PASSED] 0xB084 (PANTHERLAKE)
[04:06:08] [PASSED] 0xB085 (PANTHERLAKE)
[04:06:08] [PASSED] 0xB086 (PANTHERLAKE)
[04:06:08] [PASSED] 0xB087 (PANTHERLAKE)
[04:06:08] [PASSED] 0xB08F (PANTHERLAKE)
[04:06:08] [PASSED] 0xB090 (PANTHERLAKE)
[04:06:08] [PASSED] 0xB0A0 (PANTHERLAKE)
[04:06:08] [PASSED] 0xB0B0 (PANTHERLAKE)
[04:06:08] [PASSED] 0xFD80 (PANTHERLAKE)
[04:06:08] [PASSED] 0xFD81 (PANTHERLAKE)
[04:06:08] [PASSED] 0xD740 (NOVALAKE_S)
[04:06:08] [PASSED] 0xD741 (NOVALAKE_S)
[04:06:08] [PASSED] 0xD742 (NOVALAKE_S)
[04:06:08] [PASSED] 0xD743 (NOVALAKE_S)
[04:06:08] [PASSED] 0xD744 (NOVALAKE_S)
[04:06:08] [PASSED] 0xD745 (NOVALAKE_S)
[04:06:08] [PASSED] 0x674C (CRESCENTISLAND)
[04:06:08] =============== [PASSED] check_platform_desc ===============
[04:06:08] ===================== [PASSED] xe_pci ======================
[04:06:08] =================== xe_rtp (2 subtests) ====================
[04:06:08] =============== xe_rtp_process_to_sr_tests ================
[04:06:08] [PASSED] coalesce-same-reg
[04:06:08] [PASSED] no-match-no-add
[04:06:08] [PASSED] match-or
[04:06:08] [PASSED] match-or-xfail
[04:06:08] [PASSED] no-match-no-add-multiple-rules
[04:06:08] [PASSED] two-regs-two-entries
[04:06:08] [PASSED] clr-one-set-other
[04:06:08] [PASSED] set-field
[04:06:08] [PASSED] conflict-duplicate
[04:06:08] [PASSED] conflict-not-disjoint
[04:06:08] [PASSED] conflict-reg-type
[04:06:08] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[04:06:08] ================== xe_rtp_process_tests ===================
[04:06:08] [PASSED] active1
[04:06:08] [PASSED] active2
[04:06:08] [PASSED] active-inactive
[04:06:08] [PASSED] inactive-active
[04:06:08] [PASSED] inactive-1st_or_active-inactive
[04:06:08] [PASSED] inactive-2nd_or_active-inactive
[04:06:08] [PASSED] inactive-last_or_active-inactive
stty: 'standard input': Inappropriate ioctl for device
[04:06:08] [PASSED] inactive-no_or_active-inactive
[04:06:08] ============== [PASSED] xe_rtp_process_tests ===============
[04:06:08] ===================== [PASSED] xe_rtp ======================
[04:06:08] ==================== xe_wa (1 subtest) =====================
[04:06:08] ======================== xe_wa_gt =========================
[04:06:08] [PASSED] TIGERLAKE B0
[04:06:08] [PASSED] DG1 A0
[04:06:08] [PASSED] DG1 B0
[04:06:08] [PASSED] ALDERLAKE_S A0
[04:06:08] [PASSED] ALDERLAKE_S B0
[04:06:08] [PASSED] ALDERLAKE_S C0
[04:06:08] [PASSED] ALDERLAKE_S D0
[04:06:08] [PASSED] ALDERLAKE_P A0
[04:06:08] [PASSED] ALDERLAKE_P B0
[04:06:08] [PASSED] ALDERLAKE_P C0
[04:06:08] [PASSED] ALDERLAKE_S RPLS D0
[04:06:08] [PASSED] ALDERLAKE_P RPLU E0
[04:06:08] [PASSED] DG2 G10 C0
[04:06:08] [PASSED] DG2 G11 B1
[04:06:08] [PASSED] DG2 G12 A1
[04:06:08] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[04:06:08] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[04:06:08] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[04:06:08] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[04:06:08] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[04:06:08] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[04:06:08] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[04:06:08] ==================== [PASSED] xe_wa_gt =====================
[04:06:08] ====================== [PASSED] xe_wa ======================
[04:06:08] ============================================================
[04:06:08] Testing complete. Ran 318 tests: passed: 300, skipped: 18
[04:06:08] Elapsed time: 35.526s total, 4.250s configuring, 30.910s building, 0.320s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[04:06:08] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[04:06:10] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[04:06:35] Starting KUnit Kernel (1/1)...
[04:06:35] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[04:06:35] ============ drm_test_pick_cmdline (2 subtests) ============
[04:06:35] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[04:06:35] =============== drm_test_pick_cmdline_named ===============
[04:06:35] [PASSED] NTSC
[04:06:35] [PASSED] NTSC-J
[04:06:35] [PASSED] PAL
[04:06:35] [PASSED] PAL-M
[04:06:35] =========== [PASSED] drm_test_pick_cmdline_named ===========
[04:06:35] ============== [PASSED] drm_test_pick_cmdline ==============
[04:06:35] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[04:06:35] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[04:06:35] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[04:06:35] =========== drm_validate_clone_mode (2 subtests) ===========
[04:06:35] ============== drm_test_check_in_clone_mode ===============
[04:06:35] [PASSED] in_clone_mode
[04:06:35] [PASSED] not_in_clone_mode
[04:06:35] ========== [PASSED] drm_test_check_in_clone_mode ===========
[04:06:35] =============== drm_test_check_valid_clones ===============
[04:06:35] [PASSED] not_in_clone_mode
[04:06:35] [PASSED] valid_clone
[04:06:35] [PASSED] invalid_clone
[04:06:35] =========== [PASSED] drm_test_check_valid_clones ===========
[04:06:35] ============= [PASSED] drm_validate_clone_mode =============
[04:06:35] ============= drm_validate_modeset (1 subtest) =============
[04:06:35] [PASSED] drm_test_check_connector_changed_modeset
[04:06:35] ============== [PASSED] drm_validate_modeset ===============
[04:06:35] ====== drm_test_bridge_get_current_state (2 subtests) ======
[04:06:35] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[04:06:35] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[04:06:35] ======== [PASSED] drm_test_bridge_get_current_state ========
[04:06:35] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[04:06:35] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[04:06:35] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[04:06:35] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[04:06:35] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[04:06:35] ============== drm_bridge_alloc (2 subtests) ===============
[04:06:35] [PASSED] drm_test_drm_bridge_alloc_basic
[04:06:35] [PASSED] drm_test_drm_bridge_alloc_get_put
[04:06:35] ================ [PASSED] drm_bridge_alloc =================
[04:06:35] ================== drm_buddy (8 subtests) ==================
[04:06:35] [PASSED] drm_test_buddy_alloc_limit
[04:06:35] [PASSED] drm_test_buddy_alloc_optimistic
[04:06:35] [PASSED] drm_test_buddy_alloc_pessimistic
[04:06:35] [PASSED] drm_test_buddy_alloc_pathological
[04:06:35] [PASSED] drm_test_buddy_alloc_contiguous
[04:06:35] [PASSED] drm_test_buddy_alloc_clear
[04:06:35] [PASSED] drm_test_buddy_alloc_range_bias
[04:06:35] [PASSED] drm_test_buddy_fragmentation_performance
[04:06:35] ==================== [PASSED] drm_buddy ====================
[04:06:35] ============= drm_cmdline_parser (40 subtests) =============
[04:06:35] [PASSED] drm_test_cmdline_force_d_only
[04:06:35] [PASSED] drm_test_cmdline_force_D_only_dvi
[04:06:35] [PASSED] drm_test_cmdline_force_D_only_hdmi
[04:06:35] [PASSED] drm_test_cmdline_force_D_only_not_digital
[04:06:35] [PASSED] drm_test_cmdline_force_e_only
[04:06:35] [PASSED] drm_test_cmdline_res
[04:06:35] [PASSED] drm_test_cmdline_res_vesa
[04:06:35] [PASSED] drm_test_cmdline_res_vesa_rblank
[04:06:35] [PASSED] drm_test_cmdline_res_rblank
[04:06:35] [PASSED] drm_test_cmdline_res_bpp
[04:06:35] [PASSED] drm_test_cmdline_res_refresh
[04:06:35] [PASSED] drm_test_cmdline_res_bpp_refresh
[04:06:35] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[04:06:35] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[04:06:35] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[04:06:35] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[04:06:35] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[04:06:35] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[04:06:35] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[04:06:35] [PASSED] drm_test_cmdline_res_margins_force_on
[04:06:35] [PASSED] drm_test_cmdline_res_vesa_margins
[04:06:35] [PASSED] drm_test_cmdline_name
[04:06:35] [PASSED] drm_test_cmdline_name_bpp
[04:06:35] [PASSED] drm_test_cmdline_name_option
[04:06:35] [PASSED] drm_test_cmdline_name_bpp_option
[04:06:35] [PASSED] drm_test_cmdline_rotate_0
[04:06:35] [PASSED] drm_test_cmdline_rotate_90
[04:06:35] [PASSED] drm_test_cmdline_rotate_180
[04:06:35] [PASSED] drm_test_cmdline_rotate_270
[04:06:35] [PASSED] drm_test_cmdline_hmirror
[04:06:35] [PASSED] drm_test_cmdline_vmirror
[04:06:35] [PASSED] drm_test_cmdline_margin_options
[04:06:35] [PASSED] drm_test_cmdline_multiple_options
[04:06:35] [PASSED] drm_test_cmdline_bpp_extra_and_option
[04:06:35] [PASSED] drm_test_cmdline_extra_and_option
[04:06:35] [PASSED] drm_test_cmdline_freestanding_options
[04:06:35] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[04:06:35] [PASSED] drm_test_cmdline_panel_orientation
[04:06:35] ================ drm_test_cmdline_invalid =================
[04:06:35] [PASSED] margin_only
[04:06:35] [PASSED] interlace_only
[04:06:35] [PASSED] res_missing_x
[04:06:35] [PASSED] res_missing_y
[04:06:35] [PASSED] res_bad_y
[04:06:35] [PASSED] res_missing_y_bpp
[04:06:35] [PASSED] res_bad_bpp
[04:06:35] [PASSED] res_bad_refresh
[04:06:35] [PASSED] res_bpp_refresh_force_on_off
[04:06:35] [PASSED] res_invalid_mode
[04:06:35] [PASSED] res_bpp_wrong_place_mode
[04:06:35] [PASSED] name_bpp_refresh
[04:06:35] [PASSED] name_refresh
[04:06:35] [PASSED] name_refresh_wrong_mode
[04:06:35] [PASSED] name_refresh_invalid_mode
[04:06:35] [PASSED] rotate_multiple
[04:06:35] [PASSED] rotate_invalid_val
[04:06:35] [PASSED] rotate_truncated
[04:06:35] [PASSED] invalid_option
[04:06:35] [PASSED] invalid_tv_option
[04:06:35] [PASSED] truncated_tv_option
[04:06:35] ============ [PASSED] drm_test_cmdline_invalid =============
[04:06:35] =============== drm_test_cmdline_tv_options ===============
[04:06:35] [PASSED] NTSC
[04:06:35] [PASSED] NTSC_443
[04:06:35] [PASSED] NTSC_J
[04:06:35] [PASSED] PAL
[04:06:35] [PASSED] PAL_M
[04:06:35] [PASSED] PAL_N
[04:06:35] [PASSED] SECAM
[04:06:35] [PASSED] MONO_525
[04:06:35] [PASSED] MONO_625
[04:06:35] =========== [PASSED] drm_test_cmdline_tv_options ===========
[04:06:35] =============== [PASSED] drm_cmdline_parser ================
[04:06:35] ========== drmm_connector_hdmi_init (20 subtests) ==========
[04:06:35] [PASSED] drm_test_connector_hdmi_init_valid
[04:06:35] [PASSED] drm_test_connector_hdmi_init_bpc_8
[04:06:35] [PASSED] drm_test_connector_hdmi_init_bpc_10
[04:06:35] [PASSED] drm_test_connector_hdmi_init_bpc_12
[04:06:35] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[04:06:35] [PASSED] drm_test_connector_hdmi_init_bpc_null
[04:06:35] [PASSED] drm_test_connector_hdmi_init_formats_empty
[04:06:35] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[04:06:35] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[04:06:35] [PASSED] supported_formats=0x9 yuv420_allowed=1
[04:06:35] [PASSED] supported_formats=0x9 yuv420_allowed=0
[04:06:35] [PASSED] supported_formats=0x3 yuv420_allowed=1
[04:06:35] [PASSED] supported_formats=0x3 yuv420_allowed=0
[04:06:35] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[04:06:35] [PASSED] drm_test_connector_hdmi_init_null_ddc
[04:06:35] [PASSED] drm_test_connector_hdmi_init_null_product
[04:06:35] [PASSED] drm_test_connector_hdmi_init_null_vendor
[04:06:35] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[04:06:35] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[04:06:35] [PASSED] drm_test_connector_hdmi_init_product_valid
[04:06:35] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[04:06:35] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[04:06:35] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[04:06:35] ========= drm_test_connector_hdmi_init_type_valid =========
[04:06:35] [PASSED] HDMI-A
[04:06:35] [PASSED] HDMI-B
[04:06:35] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[04:06:35] ======== drm_test_connector_hdmi_init_type_invalid ========
[04:06:35] [PASSED] Unknown
[04:06:35] [PASSED] VGA
[04:06:35] [PASSED] DVI-I
[04:06:35] [PASSED] DVI-D
[04:06:35] [PASSED] DVI-A
[04:06:35] [PASSED] Composite
[04:06:35] [PASSED] SVIDEO
[04:06:35] [PASSED] LVDS
[04:06:35] [PASSED] Component
[04:06:35] [PASSED] DIN
[04:06:35] [PASSED] DP
[04:06:35] [PASSED] TV
[04:06:35] [PASSED] eDP
[04:06:35] [PASSED] Virtual
[04:06:35] [PASSED] DSI
[04:06:35] [PASSED] DPI
[04:06:35] [PASSED] Writeback
[04:06:35] [PASSED] SPI
[04:06:35] [PASSED] USB
[04:06:35] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[04:06:35] ============ [PASSED] drmm_connector_hdmi_init =============
[04:06:35] ============= drmm_connector_init (3 subtests) =============
[04:06:35] [PASSED] drm_test_drmm_connector_init
[04:06:35] [PASSED] drm_test_drmm_connector_init_null_ddc
[04:06:35] ========= drm_test_drmm_connector_init_type_valid =========
[04:06:35] [PASSED] Unknown
[04:06:35] [PASSED] VGA
[04:06:35] [PASSED] DVI-I
[04:06:35] [PASSED] DVI-D
[04:06:35] [PASSED] DVI-A
[04:06:35] [PASSED] Composite
[04:06:35] [PASSED] SVIDEO
[04:06:35] [PASSED] LVDS
[04:06:35] [PASSED] Component
[04:06:35] [PASSED] DIN
[04:06:35] [PASSED] DP
[04:06:35] [PASSED] HDMI-A
[04:06:35] [PASSED] HDMI-B
[04:06:35] [PASSED] TV
[04:06:35] [PASSED] eDP
[04:06:35] [PASSED] Virtual
[04:06:35] [PASSED] DSI
[04:06:35] [PASSED] DPI
[04:06:35] [PASSED] Writeback
[04:06:35] [PASSED] SPI
[04:06:35] [PASSED] USB
[04:06:35] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[04:06:35] =============== [PASSED] drmm_connector_init ===============
[04:06:35] ========= drm_connector_dynamic_init (6 subtests) ==========
[04:06:35] [PASSED] drm_test_drm_connector_dynamic_init
[04:06:35] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[04:06:35] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[04:06:35] [PASSED] drm_test_drm_connector_dynamic_init_properties
[04:06:35] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[04:06:35] [PASSED] Unknown
[04:06:35] [PASSED] VGA
[04:06:35] [PASSED] DVI-I
[04:06:35] [PASSED] DVI-D
[04:06:35] [PASSED] DVI-A
[04:06:35] [PASSED] Composite
[04:06:35] [PASSED] SVIDEO
[04:06:35] [PASSED] LVDS
[04:06:35] [PASSED] Component
[04:06:35] [PASSED] DIN
[04:06:35] [PASSED] DP
[04:06:35] [PASSED] HDMI-A
[04:06:35] [PASSED] HDMI-B
[04:06:35] [PASSED] TV
[04:06:35] [PASSED] eDP
[04:06:35] [PASSED] Virtual
[04:06:35] [PASSED] DSI
[04:06:35] [PASSED] DPI
[04:06:35] [PASSED] Writeback
[04:06:35] [PASSED] SPI
[04:06:35] [PASSED] USB
[04:06:35] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[04:06:35] ======== drm_test_drm_connector_dynamic_init_name =========
[04:06:35] [PASSED] Unknown
[04:06:35] [PASSED] VGA
[04:06:35] [PASSED] DVI-I
[04:06:35] [PASSED] DVI-D
[04:06:35] [PASSED] DVI-A
[04:06:35] [PASSED] Composite
[04:06:35] [PASSED] SVIDEO
[04:06:35] [PASSED] LVDS
[04:06:35] [PASSED] Component
[04:06:35] [PASSED] DIN
[04:06:35] [PASSED] DP
[04:06:35] [PASSED] HDMI-A
[04:06:35] [PASSED] HDMI-B
[04:06:35] [PASSED] TV
[04:06:35] [PASSED] eDP
[04:06:35] [PASSED] Virtual
[04:06:35] [PASSED] DSI
[04:06:35] [PASSED] DPI
[04:06:35] [PASSED] Writeback
[04:06:35] [PASSED] SPI
[04:06:35] [PASSED] USB
[04:06:35] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[04:06:35] =========== [PASSED] drm_connector_dynamic_init ============
[04:06:35] ==== drm_connector_dynamic_register_early (4 subtests) =====
[04:06:35] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[04:06:35] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[04:06:35] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[04:06:35] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[04:06:35] ====== [PASSED] drm_connector_dynamic_register_early =======
[04:06:35] ======= drm_connector_dynamic_register (7 subtests) ========
[04:06:35] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[04:06:35] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[04:06:35] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[04:06:35] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[04:06:35] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[04:06:35] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[04:06:35] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[04:06:35] ========= [PASSED] drm_connector_dynamic_register ==========
[04:06:35] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[04:06:35] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[04:06:35] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[04:06:35] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[04:06:35] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[04:06:35] ========== drm_test_get_tv_mode_from_name_valid ===========
[04:06:35] [PASSED] NTSC
[04:06:35] [PASSED] NTSC-443
[04:06:35] [PASSED] NTSC-J
[04:06:35] [PASSED] PAL
[04:06:35] [PASSED] PAL-M
[04:06:35] [PASSED] PAL-N
[04:06:35] [PASSED] SECAM
[04:06:35] [PASSED] Mono
[04:06:35] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[04:06:35] [PASSED] drm_test_get_tv_mode_from_name_truncated
[04:06:35] ============ [PASSED] drm_get_tv_mode_from_name ============
[04:06:35] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[04:06:35] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[04:06:35] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[04:06:35] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[04:06:35] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[04:06:35] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[04:06:35] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[04:06:35] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[04:06:35] [PASSED] VIC 96
[04:06:35] [PASSED] VIC 97
[04:06:35] [PASSED] VIC 101
[04:06:35] [PASSED] VIC 102
[04:06:35] [PASSED] VIC 106
[04:06:35] [PASSED] VIC 107
[04:06:35] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[04:06:35] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[04:06:35] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[04:06:35] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[04:06:35] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[04:06:35] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[04:06:35] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[04:06:35] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[04:06:35] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[04:06:35] [PASSED] Automatic
[04:06:35] [PASSED] Full
[04:06:35] [PASSED] Limited 16:235
[04:06:35] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[04:06:35] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[04:06:35] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[04:06:35] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[04:06:35] === drm_test_drm_hdmi_connector_get_output_format_name ====
[04:06:35] [PASSED] RGB
[04:06:35] [PASSED] YUV 4:2:0
[04:06:35] [PASSED] YUV 4:2:2
[04:06:35] [PASSED] YUV 4:4:4
[04:06:35] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[04:06:35] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[04:06:35] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[04:06:35] ============= drm_damage_helper (21 subtests) ==============
[04:06:35] [PASSED] drm_test_damage_iter_no_damage
[04:06:35] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[04:06:35] [PASSED] drm_test_damage_iter_no_damage_src_moved
[04:06:35] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[04:06:35] [PASSED] drm_test_damage_iter_no_damage_not_visible
[04:06:35] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[04:06:35] [PASSED] drm_test_damage_iter_no_damage_no_fb
[04:06:35] [PASSED] drm_test_damage_iter_simple_damage
[04:06:35] [PASSED] drm_test_damage_iter_single_damage
[04:06:35] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[04:06:35] [PASSED] drm_test_damage_iter_single_damage_outside_src
[04:06:35] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[04:06:35] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[04:06:35] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[04:06:35] [PASSED] drm_test_damage_iter_single_damage_src_moved
[04:06:35] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[04:06:35] [PASSED] drm_test_damage_iter_damage
[04:06:35] [PASSED] drm_test_damage_iter_damage_one_intersect
[04:06:35] [PASSED] drm_test_damage_iter_damage_one_outside
[04:06:35] [PASSED] drm_test_damage_iter_damage_src_moved
[04:06:35] [PASSED] drm_test_damage_iter_damage_not_visible
[04:06:35] ================ [PASSED] drm_damage_helper ================
[04:06:35] ============== drm_dp_mst_helper (3 subtests) ==============
[04:06:35] ============== drm_test_dp_mst_calc_pbn_mode ==============
[04:06:35] [PASSED] Clock 154000 BPP 30 DSC disabled
[04:06:35] [PASSED] Clock 234000 BPP 30 DSC disabled
[04:06:35] [PASSED] Clock 297000 BPP 24 DSC disabled
[04:06:35] [PASSED] Clock 332880 BPP 24 DSC enabled
[04:06:35] [PASSED] Clock 324540 BPP 24 DSC enabled
[04:06:35] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[04:06:35] ============== drm_test_dp_mst_calc_pbn_div ===============
[04:06:35] [PASSED] Link rate 2000000 lane count 4
[04:06:35] [PASSED] Link rate 2000000 lane count 2
[04:06:35] [PASSED] Link rate 2000000 lane count 1
[04:06:35] [PASSED] Link rate 1350000 lane count 4
[04:06:35] [PASSED] Link rate 1350000 lane count 2
[04:06:35] [PASSED] Link rate 1350000 lane count 1
[04:06:35] [PASSED] Link rate 1000000 lane count 4
[04:06:35] [PASSED] Link rate 1000000 lane count 2
[04:06:35] [PASSED] Link rate 1000000 lane count 1
[04:06:35] [PASSED] Link rate 810000 lane count 4
[04:06:35] [PASSED] Link rate 810000 lane count 2
[04:06:35] [PASSED] Link rate 810000 lane count 1
[04:06:35] [PASSED] Link rate 540000 lane count 4
[04:06:35] [PASSED] Link rate 540000 lane count 2
[04:06:35] [PASSED] Link rate 540000 lane count 1
[04:06:35] [PASSED] Link rate 270000 lane count 4
[04:06:35] [PASSED] Link rate 270000 lane count 2
[04:06:35] [PASSED] Link rate 270000 lane count 1
[04:06:35] [PASSED] Link rate 162000 lane count 4
[04:06:35] [PASSED] Link rate 162000 lane count 2
[04:06:35] [PASSED] Link rate 162000 lane count 1
[04:06:35] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[04:06:35] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[04:06:35] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[04:06:35] [PASSED] DP_POWER_UP_PHY with port number
[04:06:35] [PASSED] DP_POWER_DOWN_PHY with port number
[04:06:35] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[04:06:35] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[04:06:35] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[04:06:35] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[04:06:35] [PASSED] DP_QUERY_PAYLOAD with port number
[04:06:35] [PASSED] DP_QUERY_PAYLOAD with VCPI
[04:06:35] [PASSED] DP_REMOTE_DPCD_READ with port number
[04:06:35] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[04:06:35] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[04:06:35] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[04:06:35] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[04:06:35] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[04:06:35] [PASSED] DP_REMOTE_I2C_READ with port number
[04:06:35] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[04:06:35] [PASSED] DP_REMOTE_I2C_READ with transactions array
[04:06:35] [PASSED] DP_REMOTE_I2C_WRITE with port number
[04:06:35] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[04:06:35] [PASSED] DP_REMOTE_I2C_WRITE with data array
[04:06:35] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[04:06:35] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[04:06:35] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[04:06:35] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[04:06:35] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[04:06:35] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[04:06:35] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[04:06:35] ================ [PASSED] drm_dp_mst_helper ================
[04:06:35] ================== drm_exec (7 subtests) ===================
[04:06:35] [PASSED] sanitycheck
[04:06:35] [PASSED] test_lock
[04:06:35] [PASSED] test_lock_unlock
[04:06:35] [PASSED] test_duplicates
[04:06:35] [PASSED] test_prepare
[04:06:35] [PASSED] test_prepare_array
[04:06:35] [PASSED] test_multiple_loops
[04:06:35] ==================== [PASSED] drm_exec =====================
[04:06:35] =========== drm_format_helper_test (17 subtests) ===========
[04:06:35] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[04:06:35] [PASSED] single_pixel_source_buffer
[04:06:35] [PASSED] single_pixel_clip_rectangle
[04:06:35] [PASSED] well_known_colors
[04:06:35] [PASSED] destination_pitch
[04:06:35] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[04:06:35] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[04:06:35] [PASSED] single_pixel_source_buffer
[04:06:35] [PASSED] single_pixel_clip_rectangle
[04:06:35] [PASSED] well_known_colors
[04:06:35] [PASSED] destination_pitch
[04:06:35] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[04:06:35] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[04:06:35] [PASSED] single_pixel_source_buffer
[04:06:35] [PASSED] single_pixel_clip_rectangle
[04:06:35] [PASSED] well_known_colors
[04:06:35] [PASSED] destination_pitch
[04:06:35] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[04:06:35] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[04:06:35] [PASSED] single_pixel_source_buffer
[04:06:35] [PASSED] single_pixel_clip_rectangle
[04:06:35] [PASSED] well_known_colors
[04:06:35] [PASSED] destination_pitch
[04:06:35] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[04:06:35] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[04:06:35] [PASSED] single_pixel_source_buffer
[04:06:35] [PASSED] single_pixel_clip_rectangle
[04:06:35] [PASSED] well_known_colors
[04:06:35] [PASSED] destination_pitch
[04:06:35] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[04:06:35] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[04:06:35] [PASSED] single_pixel_source_buffer
[04:06:35] [PASSED] single_pixel_clip_rectangle
[04:06:35] [PASSED] well_known_colors
[04:06:35] [PASSED] destination_pitch
[04:06:35] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[04:06:35] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[04:06:35] [PASSED] single_pixel_source_buffer
[04:06:35] [PASSED] single_pixel_clip_rectangle
[04:06:35] [PASSED] well_known_colors
[04:06:35] [PASSED] destination_pitch
[04:06:35] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[04:06:35] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[04:06:35] [PASSED] single_pixel_source_buffer
[04:06:35] [PASSED] single_pixel_clip_rectangle
[04:06:35] [PASSED] well_known_colors
[04:06:35] [PASSED] destination_pitch
[04:06:35] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[04:06:35] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[04:06:35] [PASSED] single_pixel_source_buffer
[04:06:35] [PASSED] single_pixel_clip_rectangle
[04:06:35] [PASSED] well_known_colors
[04:06:35] [PASSED] destination_pitch
[04:06:35] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[04:06:35] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[04:06:35] [PASSED] single_pixel_source_buffer
[04:06:35] [PASSED] single_pixel_clip_rectangle
[04:06:35] [PASSED] well_known_colors
[04:06:35] [PASSED] destination_pitch
[04:06:35] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[04:06:35] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[04:06:35] [PASSED] single_pixel_source_buffer
[04:06:35] [PASSED] single_pixel_clip_rectangle
[04:06:35] [PASSED] well_known_colors
[04:06:35] [PASSED] destination_pitch
[04:06:35] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[04:06:35] ============== drm_test_fb_xrgb8888_to_mono ===============
[04:06:35] [PASSED] single_pixel_source_buffer
[04:06:35] [PASSED] single_pixel_clip_rectangle
[04:06:35] [PASSED] well_known_colors
[04:06:35] [PASSED] destination_pitch
[04:06:35] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[04:06:35] ==================== drm_test_fb_swab =====================
[04:06:35] [PASSED] single_pixel_source_buffer
[04:06:35] [PASSED] single_pixel_clip_rectangle
[04:06:35] [PASSED] well_known_colors
[04:06:35] [PASSED] destination_pitch
[04:06:35] ================ [PASSED] drm_test_fb_swab =================
[04:06:35] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[04:06:35] [PASSED] single_pixel_source_buffer
[04:06:35] [PASSED] single_pixel_clip_rectangle
[04:06:35] [PASSED] well_known_colors
[04:06:35] [PASSED] destination_pitch
[04:06:35] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[04:06:35] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[04:06:35] [PASSED] single_pixel_source_buffer
[04:06:35] [PASSED] single_pixel_clip_rectangle
[04:06:35] [PASSED] well_known_colors
[04:06:35] [PASSED] destination_pitch
[04:06:35] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[04:06:35] ================= drm_test_fb_clip_offset =================
[04:06:35] [PASSED] pass through
[04:06:35] [PASSED] horizontal offset
[04:06:35] [PASSED] vertical offset
[04:06:35] [PASSED] horizontal and vertical offset
[04:06:35] [PASSED] horizontal offset (custom pitch)
[04:06:35] [PASSED] vertical offset (custom pitch)
[04:06:35] [PASSED] horizontal and vertical offset (custom pitch)
[04:06:35] ============= [PASSED] drm_test_fb_clip_offset =============
[04:06:35] =================== drm_test_fb_memcpy ====================
[04:06:35] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[04:06:35] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[04:06:35] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[04:06:35] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[04:06:35] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[04:06:35] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[04:06:35] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[04:06:35] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[04:06:35] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[04:06:35] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[04:06:35] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[04:06:35] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[04:06:35] =============== [PASSED] drm_test_fb_memcpy ================
[04:06:35] ============= [PASSED] drm_format_helper_test ==============
[04:06:35] ================= drm_format (18 subtests) =================
[04:06:35] [PASSED] drm_test_format_block_width_invalid
[04:06:35] [PASSED] drm_test_format_block_width_one_plane
[04:06:35] [PASSED] drm_test_format_block_width_two_plane
[04:06:35] [PASSED] drm_test_format_block_width_three_plane
[04:06:35] [PASSED] drm_test_format_block_width_tiled
[04:06:35] [PASSED] drm_test_format_block_height_invalid
[04:06:35] [PASSED] drm_test_format_block_height_one_plane
[04:06:35] [PASSED] drm_test_format_block_height_two_plane
[04:06:35] [PASSED] drm_test_format_block_height_three_plane
[04:06:35] [PASSED] drm_test_format_block_height_tiled
[04:06:35] [PASSED] drm_test_format_min_pitch_invalid
[04:06:35] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[04:06:35] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[04:06:35] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[04:06:35] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[04:06:35] [PASSED] drm_test_format_min_pitch_two_plane
[04:06:35] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[04:06:35] [PASSED] drm_test_format_min_pitch_tiled
[04:06:35] =================== [PASSED] drm_format ====================
[04:06:35] ============== drm_framebuffer (10 subtests) ===============
[04:06:35] ========== drm_test_framebuffer_check_src_coords ==========
[04:06:35] [PASSED] Success: source fits into fb
[04:06:35] [PASSED] Fail: overflowing fb with x-axis coordinate
[04:06:35] [PASSED] Fail: overflowing fb with y-axis coordinate
[04:06:35] [PASSED] Fail: overflowing fb with source width
[04:06:35] [PASSED] Fail: overflowing fb with source height
[04:06:35] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[04:06:35] [PASSED] drm_test_framebuffer_cleanup
[04:06:35] =============== drm_test_framebuffer_create ===============
[04:06:35] [PASSED] ABGR8888 normal sizes
[04:06:35] [PASSED] ABGR8888 max sizes
[04:06:35] [PASSED] ABGR8888 pitch greater than min required
[04:06:35] [PASSED] ABGR8888 pitch less than min required
[04:06:35] [PASSED] ABGR8888 Invalid width
[04:06:35] [PASSED] ABGR8888 Invalid buffer handle
[04:06:35] [PASSED] No pixel format
[04:06:35] [PASSED] ABGR8888 Width 0
[04:06:35] [PASSED] ABGR8888 Height 0
[04:06:35] [PASSED] ABGR8888 Out of bound height * pitch combination
[04:06:35] [PASSED] ABGR8888 Large buffer offset
[04:06:35] [PASSED] ABGR8888 Buffer offset for inexistent plane
[04:06:35] [PASSED] ABGR8888 Invalid flag
[04:06:35] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[04:06:35] [PASSED] ABGR8888 Valid buffer modifier
[04:06:35] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[04:06:35] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[04:06:35] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[04:06:35] [PASSED] NV12 Normal sizes
[04:06:35] [PASSED] NV12 Max sizes
[04:06:35] [PASSED] NV12 Invalid pitch
[04:06:35] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[04:06:35] [PASSED] NV12 different modifier per-plane
[04:06:35] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[04:06:35] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[04:06:35] [PASSED] NV12 Modifier for inexistent plane
[04:06:35] [PASSED] NV12 Handle for inexistent plane
[04:06:35] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[04:06:35] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[04:06:35] [PASSED] YVU420 Normal sizes
[04:06:35] [PASSED] YVU420 Max sizes
[04:06:35] [PASSED] YVU420 Invalid pitch
[04:06:35] [PASSED] YVU420 Different pitches
[04:06:35] [PASSED] YVU420 Different buffer offsets/pitches
[04:06:35] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[04:06:35] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[04:06:35] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[04:06:35] [PASSED] YVU420 Valid modifier
[04:06:35] [PASSED] YVU420 Different modifiers per plane
[04:06:35] [PASSED] YVU420 Modifier for inexistent plane
[04:06:35] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[04:06:35] [PASSED] X0L2 Normal sizes
[04:06:35] [PASSED] X0L2 Max sizes
[04:06:35] [PASSED] X0L2 Invalid pitch
[04:06:35] [PASSED] X0L2 Pitch greater than minimum required
[04:06:35] [PASSED] X0L2 Handle for inexistent plane
[04:06:35] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[04:06:35] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[04:06:35] [PASSED] X0L2 Valid modifier
[04:06:35] [PASSED] X0L2 Modifier for inexistent plane
[04:06:35] =========== [PASSED] drm_test_framebuffer_create ===========
[04:06:35] [PASSED] drm_test_framebuffer_free
[04:06:35] [PASSED] drm_test_framebuffer_init
[04:06:35] [PASSED] drm_test_framebuffer_init_bad_format
[04:06:35] [PASSED] drm_test_framebuffer_init_dev_mismatch
[04:06:35] [PASSED] drm_test_framebuffer_lookup
[04:06:35] [PASSED] drm_test_framebuffer_lookup_inexistent
[04:06:35] [PASSED] drm_test_framebuffer_modifiers_not_supported
[04:06:35] ================= [PASSED] drm_framebuffer =================
[04:06:35] ================ drm_gem_shmem (8 subtests) ================
[04:06:35] [PASSED] drm_gem_shmem_test_obj_create
[04:06:35] [PASSED] drm_gem_shmem_test_obj_create_private
[04:06:35] [PASSED] drm_gem_shmem_test_pin_pages
[04:06:35] [PASSED] drm_gem_shmem_test_vmap
[04:06:35] [PASSED] drm_gem_shmem_test_get_pages_sgt
[04:06:35] [PASSED] drm_gem_shmem_test_get_sg_table
[04:06:35] [PASSED] drm_gem_shmem_test_madvise
[04:06:35] [PASSED] drm_gem_shmem_test_purge
[04:06:35] ================== [PASSED] drm_gem_shmem ==================
[04:06:35] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[04:06:35] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[04:06:35] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[04:06:35] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[04:06:35] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[04:06:35] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[04:06:35] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[04:06:35] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[04:06:35] [PASSED] Automatic
[04:06:35] [PASSED] Full
[04:06:35] [PASSED] Limited 16:235
[04:06:35] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[04:06:35] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[04:06:35] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[04:06:35] [PASSED] drm_test_check_disable_connector
[04:06:35] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[04:06:35] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[04:06:35] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[04:06:35] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[04:06:35] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[04:06:35] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[04:06:35] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[04:06:35] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[04:06:35] [PASSED] drm_test_check_output_bpc_dvi
[04:06:35] [PASSED] drm_test_check_output_bpc_format_vic_1
[04:06:35] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[04:06:35] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[04:06:35] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[04:06:35] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[04:06:35] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[04:06:35] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[04:06:35] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[04:06:35] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[04:06:35] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[04:06:35] [PASSED] drm_test_check_broadcast_rgb_value
[04:06:35] [PASSED] drm_test_check_bpc_8_value
[04:06:35] [PASSED] drm_test_check_bpc_10_value
[04:06:35] [PASSED] drm_test_check_bpc_12_value
[04:06:35] [PASSED] drm_test_check_format_value
[04:06:35] [PASSED] drm_test_check_tmds_char_value
[04:06:35] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[04:06:35] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[04:06:35] [PASSED] drm_test_check_mode_valid
[04:06:35] [PASSED] drm_test_check_mode_valid_reject
[04:06:35] [PASSED] drm_test_check_mode_valid_reject_rate
[04:06:35] [PASSED] drm_test_check_mode_valid_reject_max_clock
[04:06:35] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[04:06:35] ================= drm_managed (2 subtests) =================
[04:06:35] [PASSED] drm_test_managed_release_action
[04:06:35] [PASSED] drm_test_managed_run_action
[04:06:35] =================== [PASSED] drm_managed ===================
[04:06:35] =================== drm_mm (6 subtests) ====================
[04:06:35] [PASSED] drm_test_mm_init
[04:06:35] [PASSED] drm_test_mm_debug
[04:06:35] [PASSED] drm_test_mm_align32
[04:06:35] [PASSED] drm_test_mm_align64
[04:06:35] [PASSED] drm_test_mm_lowest
[04:06:35] [PASSED] drm_test_mm_highest
[04:06:35] ===================== [PASSED] drm_mm ======================
[04:06:35] ============= drm_modes_analog_tv (5 subtests) =============
[04:06:35] [PASSED] drm_test_modes_analog_tv_mono_576i
[04:06:35] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[04:06:35] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[04:06:35] [PASSED] drm_test_modes_analog_tv_pal_576i
[04:06:35] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[04:06:35] =============== [PASSED] drm_modes_analog_tv ===============
[04:06:35] ============== drm_plane_helper (2 subtests) ===============
[04:06:35] =============== drm_test_check_plane_state ================
[04:06:35] [PASSED] clipping_simple
[04:06:35] [PASSED] clipping_rotate_reflect
[04:06:35] [PASSED] positioning_simple
[04:06:35] [PASSED] upscaling
[04:06:35] [PASSED] downscaling
[04:06:35] [PASSED] rounding1
[04:06:35] [PASSED] rounding2
[04:06:35] [PASSED] rounding3
[04:06:35] [PASSED] rounding4
[04:06:35] =========== [PASSED] drm_test_check_plane_state ============
[04:06:35] =========== drm_test_check_invalid_plane_state ============
[04:06:35] [PASSED] positioning_invalid
[04:06:35] [PASSED] upscaling_invalid
[04:06:35] [PASSED] downscaling_invalid
[04:06:35] ======= [PASSED] drm_test_check_invalid_plane_state ========
[04:06:35] ================ [PASSED] drm_plane_helper =================
[04:06:35] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[04:06:35] ====== drm_test_connector_helper_tv_get_modes_check =======
[04:06:35] [PASSED] None
[04:06:35] [PASSED] PAL
[04:06:35] [PASSED] NTSC
[04:06:35] [PASSED] Both, NTSC Default
[04:06:35] [PASSED] Both, PAL Default
[04:06:35] [PASSED] Both, NTSC Default, with PAL on command-line
[04:06:35] [PASSED] Both, PAL Default, with NTSC on command-line
[04:06:35] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[04:06:35] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[04:06:35] ================== drm_rect (9 subtests) ===================
[04:06:35] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[04:06:35] [PASSED] drm_test_rect_clip_scaled_not_clipped
[04:06:35] [PASSED] drm_test_rect_clip_scaled_clipped
[04:06:35] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[04:06:35] ================= drm_test_rect_intersect =================
[04:06:35] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[04:06:35] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[04:06:35] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[04:06:35] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[04:06:35] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[04:06:35] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[04:06:35] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[04:06:35] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[04:06:35] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[04:06:35] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[04:06:35] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[04:06:35] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[04:06:35] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[04:06:35] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[04:06:35] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[04:06:35] ============= [PASSED] drm_test_rect_intersect =============
[04:06:35] ================ drm_test_rect_calc_hscale ================
[04:06:35] [PASSED] normal use
[04:06:35] [PASSED] out of max range
[04:06:35] [PASSED] out of min range
[04:06:35] [PASSED] zero dst
[04:06:35] [PASSED] negative src
[04:06:35] [PASSED] negative dst
[04:06:35] ============ [PASSED] drm_test_rect_calc_hscale ============
[04:06:35] ================ drm_test_rect_calc_vscale ================
[04:06:35] [PASSED] normal use
stty: 'standard input': Inappropriate ioctl for device
[04:06:35] [PASSED] out of max range
[04:06:35] [PASSED] out of min range
[04:06:35] [PASSED] zero dst
[04:06:35] [PASSED] negative src
[04:06:35] [PASSED] negative dst
[04:06:35] ============ [PASSED] drm_test_rect_calc_vscale ============
[04:06:35] ================== drm_test_rect_rotate ===================
[04:06:35] [PASSED] reflect-x
[04:06:35] [PASSED] reflect-y
[04:06:35] [PASSED] rotate-0
[04:06:35] [PASSED] rotate-90
[04:06:35] [PASSED] rotate-180
[04:06:35] [PASSED] rotate-270
[04:06:35] ============== [PASSED] drm_test_rect_rotate ===============
[04:06:35] ================ drm_test_rect_rotate_inv =================
[04:06:35] [PASSED] reflect-x
[04:06:35] [PASSED] reflect-y
[04:06:35] [PASSED] rotate-0
[04:06:35] [PASSED] rotate-90
[04:06:35] [PASSED] rotate-180
[04:06:35] [PASSED] rotate-270
[04:06:35] ============ [PASSED] drm_test_rect_rotate_inv =============
[04:06:35] ==================== [PASSED] drm_rect =====================
[04:06:35] ============ drm_sysfb_modeset_test (1 subtest) ============
[04:06:35] ============ drm_test_sysfb_build_fourcc_list =============
[04:06:35] [PASSED] no native formats
[04:06:35] [PASSED] XRGB8888 as native format
[04:06:35] [PASSED] remove duplicates
[04:06:35] [PASSED] convert alpha formats
[04:06:35] [PASSED] random formats
[04:06:35] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[04:06:35] ============= [PASSED] drm_sysfb_modeset_test ==============
[04:06:35] ============================================================
[04:06:35] Testing complete. Ran 622 tests: passed: 622
[04:06:35] Elapsed time: 26.965s total, 1.639s configuring, 24.810s building, 0.458s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[04:06:35] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[04:06:37] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[04:06:46] Starting KUnit Kernel (1/1)...
[04:06:46] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[04:06:46] ================= ttm_device (5 subtests) ==================
[04:06:46] [PASSED] ttm_device_init_basic
[04:06:46] [PASSED] ttm_device_init_multiple
[04:06:46] [PASSED] ttm_device_fini_basic
[04:06:46] [PASSED] ttm_device_init_no_vma_man
[04:06:46] ================== ttm_device_init_pools ==================
[04:06:46] [PASSED] No DMA allocations, no DMA32 required
[04:06:46] [PASSED] DMA allocations, DMA32 required
[04:06:46] [PASSED] No DMA allocations, DMA32 required
[04:06:46] [PASSED] DMA allocations, no DMA32 required
[04:06:46] ============== [PASSED] ttm_device_init_pools ==============
[04:06:46] =================== [PASSED] ttm_device ====================
[04:06:46] ================== ttm_pool (8 subtests) ===================
[04:06:46] ================== ttm_pool_alloc_basic ===================
[04:06:46] [PASSED] One page
[04:06:46] [PASSED] More than one page
[04:06:46] [PASSED] Above the allocation limit
[04:06:46] [PASSED] One page, with coherent DMA mappings enabled
[04:06:46] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[04:06:46] ============== [PASSED] ttm_pool_alloc_basic ===============
[04:06:46] ============== ttm_pool_alloc_basic_dma_addr ==============
[04:06:46] [PASSED] One page
[04:06:46] [PASSED] More than one page
[04:06:46] [PASSED] Above the allocation limit
[04:06:46] [PASSED] One page, with coherent DMA mappings enabled
[04:06:46] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[04:06:46] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[04:06:46] [PASSED] ttm_pool_alloc_order_caching_match
[04:06:46] [PASSED] ttm_pool_alloc_caching_mismatch
[04:06:46] [PASSED] ttm_pool_alloc_order_mismatch
[04:06:46] [PASSED] ttm_pool_free_dma_alloc
[04:06:46] [PASSED] ttm_pool_free_no_dma_alloc
[04:06:46] [PASSED] ttm_pool_fini_basic
[04:06:46] ==================== [PASSED] ttm_pool =====================
[04:06:46] ================ ttm_resource (8 subtests) =================
[04:06:46] ================= ttm_resource_init_basic =================
[04:06:46] [PASSED] Init resource in TTM_PL_SYSTEM
[04:06:46] [PASSED] Init resource in TTM_PL_VRAM
[04:06:46] [PASSED] Init resource in a private placement
[04:06:46] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[04:06:46] ============= [PASSED] ttm_resource_init_basic =============
[04:06:46] [PASSED] ttm_resource_init_pinned
[04:06:46] [PASSED] ttm_resource_fini_basic
[04:06:46] [PASSED] ttm_resource_manager_init_basic
[04:06:46] [PASSED] ttm_resource_manager_usage_basic
[04:06:46] [PASSED] ttm_resource_manager_set_used_basic
[04:06:46] [PASSED] ttm_sys_man_alloc_basic
[04:06:46] [PASSED] ttm_sys_man_free_basic
[04:06:46] ================== [PASSED] ttm_resource ===================
[04:06:46] =================== ttm_tt (15 subtests) ===================
[04:06:46] ==================== ttm_tt_init_basic ====================
[04:06:46] [PASSED] Page-aligned size
[04:06:46] [PASSED] Extra pages requested
[04:06:46] ================ [PASSED] ttm_tt_init_basic ================
[04:06:46] [PASSED] ttm_tt_init_misaligned
[04:06:46] [PASSED] ttm_tt_fini_basic
[04:06:46] [PASSED] ttm_tt_fini_sg
[04:06:46] [PASSED] ttm_tt_fini_shmem
[04:06:46] [PASSED] ttm_tt_create_basic
[04:06:46] [PASSED] ttm_tt_create_invalid_bo_type
[04:06:46] [PASSED] ttm_tt_create_ttm_exists
[04:06:46] [PASSED] ttm_tt_create_failed
[04:06:46] [PASSED] ttm_tt_destroy_basic
[04:06:46] [PASSED] ttm_tt_populate_null_ttm
[04:06:46] [PASSED] ttm_tt_populate_populated_ttm
[04:06:46] [PASSED] ttm_tt_unpopulate_basic
[04:06:46] [PASSED] ttm_tt_unpopulate_empty_ttm
[04:06:46] [PASSED] ttm_tt_swapin_basic
[04:06:46] ===================== [PASSED] ttm_tt ======================
[04:06:46] =================== ttm_bo (14 subtests) ===================
[04:06:46] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[04:06:46] [PASSED] Cannot be interrupted and sleeps
[04:06:46] [PASSED] Cannot be interrupted, locks straight away
[04:06:46] [PASSED] Can be interrupted, sleeps
[04:06:46] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[04:06:46] [PASSED] ttm_bo_reserve_locked_no_sleep
[04:06:46] [PASSED] ttm_bo_reserve_no_wait_ticket
[04:06:46] [PASSED] ttm_bo_reserve_double_resv
[04:06:46] [PASSED] ttm_bo_reserve_interrupted
[04:06:46] [PASSED] ttm_bo_reserve_deadlock
[04:06:46] [PASSED] ttm_bo_unreserve_basic
[04:06:46] [PASSED] ttm_bo_unreserve_pinned
[04:06:46] [PASSED] ttm_bo_unreserve_bulk
[04:06:46] [PASSED] ttm_bo_fini_basic
[04:06:46] [PASSED] ttm_bo_fini_shared_resv
[04:06:46] [PASSED] ttm_bo_pin_basic
[04:06:46] [PASSED] ttm_bo_pin_unpin_resource
[04:06:46] [PASSED] ttm_bo_multiple_pin_one_unpin
[04:06:46] ===================== [PASSED] ttm_bo ======================
[04:06:46] ============== ttm_bo_validate (21 subtests) ===============
[04:06:46] ============== ttm_bo_init_reserved_sys_man ===============
[04:06:46] [PASSED] Buffer object for userspace
[04:06:46] [PASSED] Kernel buffer object
[04:06:46] [PASSED] Shared buffer object
[04:06:46] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[04:06:46] ============== ttm_bo_init_reserved_mock_man ==============
[04:06:46] [PASSED] Buffer object for userspace
[04:06:46] [PASSED] Kernel buffer object
[04:06:46] [PASSED] Shared buffer object
[04:06:46] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[04:06:46] [PASSED] ttm_bo_init_reserved_resv
[04:06:46] ================== ttm_bo_validate_basic ==================
[04:06:46] [PASSED] Buffer object for userspace
[04:06:46] [PASSED] Kernel buffer object
[04:06:46] [PASSED] Shared buffer object
[04:06:46] ============== [PASSED] ttm_bo_validate_basic ==============
[04:06:46] [PASSED] ttm_bo_validate_invalid_placement
[04:06:46] ============= ttm_bo_validate_same_placement ==============
[04:06:46] [PASSED] System manager
[04:06:46] [PASSED] VRAM manager
[04:06:46] ========= [PASSED] ttm_bo_validate_same_placement ==========
[04:06:46] [PASSED] ttm_bo_validate_failed_alloc
[04:06:46] [PASSED] ttm_bo_validate_pinned
[04:06:46] [PASSED] ttm_bo_validate_busy_placement
[04:06:46] ================ ttm_bo_validate_multihop =================
[04:06:46] [PASSED] Buffer object for userspace
[04:06:46] [PASSED] Kernel buffer object
[04:06:46] [PASSED] Shared buffer object
[04:06:46] ============ [PASSED] ttm_bo_validate_multihop =============
[04:06:46] ========== ttm_bo_validate_no_placement_signaled ==========
[04:06:46] [PASSED] Buffer object in system domain, no page vector
[04:06:46] [PASSED] Buffer object in system domain with an existing page vector
[04:06:46] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[04:06:46] ======== ttm_bo_validate_no_placement_not_signaled ========
[04:06:46] [PASSED] Buffer object for userspace
[04:06:46] [PASSED] Kernel buffer object
[04:06:46] [PASSED] Shared buffer object
[04:06:46] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[04:06:46] [PASSED] ttm_bo_validate_move_fence_signaled
[04:06:46] ========= ttm_bo_validate_move_fence_not_signaled =========
[04:06:46] [PASSED] Waits for GPU
[04:06:46] [PASSED] Tries to lock straight away
[04:06:46] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[04:06:46] [PASSED] ttm_bo_validate_happy_evict
[04:06:46] [PASSED] ttm_bo_validate_all_pinned_evict
[04:06:46] [PASSED] ttm_bo_validate_allowed_only_evict
[04:06:46] [PASSED] ttm_bo_validate_deleted_evict
[04:06:46] [PASSED] ttm_bo_validate_busy_domain_evict
[04:06:46] [PASSED] ttm_bo_validate_evict_gutting
[04:06:46] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[04:06:46] ================= [PASSED] ttm_bo_validate =================
[04:06:46] ============================================================
[04:06:46] Testing complete. Ran 101 tests: passed: 101
[04:06:47] Elapsed time: 11.258s total, 1.721s configuring, 9.271s building, 0.233s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 16+ messages in thread* ✗ Xe.CI.BAT: failure for Pagefault refactor (rev2)
2025-10-28 3:58 [PATCH v3 0/7] Pagefault refactor Matthew Brost
` (8 preceding siblings ...)
2025-10-28 4:06 ` ✓ CI.KUnit: success " Patchwork
@ 2025-10-28 4:46 ` Patchwork
2025-10-28 9:30 ` ✗ Xe.CI.Full: " Patchwork
10 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2025-10-28 4:46 UTC (permalink / raw)
To: Matthew Brost; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 5927 bytes --]
== Series Details ==
Series: Pagefault refactor (rev2)
URL : https://patchwork.freedesktop.org/series/156508/
State : failure
== Summary ==
CI Bug Log - changes from xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e_BAT -> xe-pw-156508v2_BAT
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with xe-pw-156508v2_BAT absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-156508v2_BAT, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (13 -> 13)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in xe-pw-156508v2_BAT:
### IGT changes ###
#### Possible regressions ####
* igt@kms_pipe_crc_basic@hang-read-crc:
- bat-dg2-oem2: [PASS][1] -> [ABORT][2] +1 other test abort
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/bat-dg2-oem2/igt@kms_pipe_crc_basic@hang-read-crc.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/bat-dg2-oem2/igt@kms_pipe_crc_basic@hang-read-crc.html
* igt@kms_pipe_crc_basic@hang-read-crc@pipe-a-edp-1:
- bat-adlp-7: [PASS][3] -> [ABORT][4] +1 other test abort
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/bat-adlp-7/igt@kms_pipe_crc_basic@hang-read-crc@pipe-a-edp-1.html
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/bat-adlp-7/igt@kms_pipe_crc_basic@hang-read-crc@pipe-a-edp-1.html
* igt@xe_live_ktest@xe_bo@xe_bo_evict_kunit:
- bat-atsm-2: [PASS][5] -> [ABORT][6] +1 other test abort
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/bat-atsm-2/igt@xe_live_ktest@xe_bo@xe_bo_evict_kunit.html
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/bat-atsm-2/igt@xe_live_ktest@xe_bo@xe_bo_evict_kunit.html
* igt@xe_module_load@load:
- bat-ptl-2: [PASS][7] -> [ABORT][8]
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/bat-ptl-2/igt@xe_module_load@load.html
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/bat-ptl-2/igt@xe_module_load@load.html
- bat-ptl-1: [PASS][9] -> [ABORT][10]
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/bat-ptl-1/igt@xe_module_load@load.html
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/bat-ptl-1/igt@xe_module_load@load.html
- bat-ptl-vm: [PASS][11] -> [ABORT][12]
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/bat-ptl-vm/igt@xe_module_load@load.html
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/bat-ptl-vm/igt@xe_module_load@load.html
- bat-lnl-1: [PASS][13] -> [ABORT][14]
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/bat-lnl-1/igt@xe_module_load@load.html
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/bat-lnl-1/igt@xe_module_load@load.html
- bat-pvc-2: [PASS][15] -> [ABORT][16]
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/bat-pvc-2/igt@xe_module_load@load.html
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/bat-pvc-2/igt@xe_module_load@load.html
- bat-bmg-2: [PASS][17] -> [ABORT][18]
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/bat-bmg-2/igt@xe_module_load@load.html
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/bat-bmg-2/igt@xe_module_load@load.html
- bat-bmg-3: [PASS][19] -> [ABORT][20]
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/bat-bmg-3/igt@xe_module_load@load.html
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/bat-bmg-3/igt@xe_module_load@load.html
- bat-bmg-1: [PASS][21] -> [ABORT][22]
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/bat-bmg-1/igt@xe_module_load@load.html
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/bat-bmg-1/igt@xe_module_load@load.html
- bat-lnl-2: [PASS][23] -> [ABORT][24]
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/bat-lnl-2/igt@xe_module_load@load.html
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/bat-lnl-2/igt@xe_module_load@load.html
Known issues
------------
Here are the changes found in xe-pw-156508v2_BAT that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_flip@basic-plain-flip@d-edp1:
- bat-adlp-7: [PASS][25] -> [DMESG-WARN][26] ([Intel XE#4543]) +1 other test dmesg-warn
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/bat-adlp-7/igt@kms_flip@basic-plain-flip@d-edp1.html
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/bat-adlp-7/igt@kms_flip@basic-plain-flip@d-edp1.html
[Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
Build changes
-------------
* IGT: IGT_8597 -> IGT_8598
* Linux: xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e -> xe-pw-156508v2
IGT_8597: 8597
IGT_8598: 8598
xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e: de43fe70c436c359e7478a5532d873f87357cb4e
xe-pw-156508v2: 156508v2
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/index.html
[-- Attachment #2: Type: text/html, Size: 6682 bytes --]
^ permalink raw reply [flat|nested] 16+ messages in thread* ✗ Xe.CI.Full: failure for Pagefault refactor (rev2)
2025-10-28 3:58 [PATCH v3 0/7] Pagefault refactor Matthew Brost
` (9 preceding siblings ...)
2025-10-28 4:46 ` ✗ Xe.CI.BAT: failure " Patchwork
@ 2025-10-28 9:30 ` Patchwork
10 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2025-10-28 9:30 UTC (permalink / raw)
To: Matthew Brost; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 49876 bytes --]
== Series Details ==
Series: Pagefault refactor (rev2)
URL : https://patchwork.freedesktop.org/series/156508/
State : failure
== Summary ==
CI Bug Log - changes from xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e_FULL -> xe-pw-156508v2_FULL
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with xe-pw-156508v2_FULL absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-156508v2_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (4 -> 4)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in xe-pw-156508v2_FULL:
### IGT changes ###
#### Possible regressions ####
* igt@kms_pipe_crc_basic@hang-read-crc@pipe-a-hdmi-a-1:
- shard-adlp: [PASS][1] -> [ABORT][2] +9 other tests abort
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-adlp-3/igt@kms_pipe_crc_basic@hang-read-crc@pipe-a-hdmi-a-1.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-adlp-6/igt@kms_pipe_crc_basic@hang-read-crc@pipe-a-hdmi-a-1.html
* igt@xe_exec_reset@parallel-gt-reset:
- shard-adlp: NOTRUN -> [ABORT][3]
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-adlp-6/igt@xe_exec_reset@parallel-gt-reset.html
- shard-dg2-set2: NOTRUN -> [ABORT][4]
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-dg2-433/igt@xe_exec_reset@parallel-gt-reset.html
* igt@xe_gt_freq@freq_reset_multiple:
- shard-dg2-set2: [PASS][5] -> [ABORT][6] +5 other tests abort
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-dg2-464/igt@xe_gt_freq@freq_reset_multiple.html
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-dg2-464/igt@xe_gt_freq@freq_reset_multiple.html
#### Warnings ####
* igt@xe_exec_reset@cm-cat-error:
- shard-adlp: [DMESG-WARN][7] ([Intel XE#3868]) -> [ABORT][8] +1 other test abort
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-adlp-2/igt@xe_exec_reset@cm-cat-error.html
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-adlp-1/igt@xe_exec_reset@cm-cat-error.html
* igt@xe_live_ktest@xe_bo:
- shard-dg2-set2: [FAIL][9] ([Intel XE#3099]) -> [ABORT][10] +1 other test abort
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-dg2-436/igt@xe_live_ktest@xe_bo.html
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-dg2-432/igt@xe_live_ktest@xe_bo.html
* igt@xe_module_load@load:
- shard-lnl: ([PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [DMESG-WARN][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34]) ([Intel XE#6295]) -> ([DMESG-WARN][35], [DMESG-WARN][36], [DMESG-WARN][37], [DMESG-WARN][38], [DMESG-WARN][39], [DMESG-WARN][40], [DMESG-WARN][41], [DMESG-WARN][42], [DMESG-WARN][43], [DMESG-WARN][44], [DMESG-WARN][45], [DMESG-WARN][46], [DMESG-WARN][47], [DMESG-WARN][48], [DMESG-WARN][49], [DMESG-WARN][50], [DMESG-WARN][51], [DMESG-WARN][52], [DMESG-WARN][53], [DMESG-WARN][54], [DMESG-WARN][55], [DMESG-WARN][56], [DMESG-WARN][57], [DMESG-WARN][58], [DMESG-WARN][59])
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-lnl-5/igt@xe_module_load@load.html
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-lnl-5/igt@xe_module_load@load.html
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-lnl-5/igt@xe_module_load@load.html
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-lnl-4/igt@xe_module_load@load.html
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-lnl-3/igt@xe_module_load@load.html
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-lnl-4/igt@xe_module_load@load.html
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-lnl-1/igt@xe_module_load@load.html
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-lnl-4/igt@xe_module_load@load.html
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-lnl-4/igt@xe_module_load@load.html
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-lnl-1/igt@xe_module_load@load.html
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-lnl-3/igt@xe_module_load@load.html
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-lnl-3/igt@xe_module_load@load.html
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-lnl-8/igt@xe_module_load@load.html
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-lnl-8/igt@xe_module_load@load.html
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-lnl-7/igt@xe_module_load@load.html
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-lnl-8/igt@xe_module_load@load.html
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-lnl-2/igt@xe_module_load@load.html
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-lnl-2/igt@xe_module_load@load.html
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-lnl-2/igt@xe_module_load@load.html
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-lnl-1/igt@xe_module_load@load.html
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-lnl-7/igt@xe_module_load@load.html
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-lnl-7/igt@xe_module_load@load.html
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-lnl-7/igt@xe_module_load@load.html
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-lnl-1/igt@xe_module_load@load.html
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-lnl-2/igt@xe_module_load@load.html
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-lnl-4/igt@xe_module_load@load.html
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-lnl-4/igt@xe_module_load@load.html
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-lnl-4/igt@xe_module_load@load.html
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-lnl-4/igt@xe_module_load@load.html
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-lnl-8/igt@xe_module_load@load.html
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-lnl-2/igt@xe_module_load@load.html
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-lnl-8/igt@xe_module_load@load.html
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-lnl-8/igt@xe_module_load@load.html
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-lnl-5/igt@xe_module_load@load.html
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-lnl-5/igt@xe_module_load@load.html
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-lnl-5/igt@xe_module_load@load.html
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-lnl-5/igt@xe_module_load@load.html
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-lnl-7/igt@xe_module_load@load.html
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-lnl-7/igt@xe_module_load@load.html
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-lnl-7/igt@xe_module_load@load.html
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-lnl-7/igt@xe_module_load@load.html
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-lnl-1/igt@xe_module_load@load.html
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-lnl-1/igt@xe_module_load@load.html
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-lnl-1/igt@xe_module_load@load.html
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-lnl-1/igt@xe_module_load@load.html
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-lnl-3/igt@xe_module_load@load.html
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-lnl-3/igt@xe_module_load@load.html
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-lnl-3/igt@xe_module_load@load.html
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-lnl-2/igt@xe_module_load@load.html
- shard-bmg: ([SKIP][60], [PASS][61], [PASS][62], [PASS][63], [PASS][64], [PASS][65], [PASS][66], [PASS][67], [PASS][68], [PASS][69], [PASS][70], [PASS][71], [PASS][72], [PASS][73], [PASS][74], [PASS][75], [PASS][76], [PASS][77], [PASS][78], [PASS][79], [PASS][80], [PASS][81], [PASS][82], [PASS][83], [PASS][84], [PASS][85]) ([Intel XE#2457]) -> ([DMESG-WARN][86], [DMESG-WARN][87], [DMESG-WARN][88], [DMESG-WARN][89], [DMESG-WARN][90], [DMESG-WARN][91], [DMESG-WARN][92], [DMESG-WARN][93], [DMESG-WARN][94], [DMESG-WARN][95], [DMESG-WARN][96], [DMESG-WARN][97], [DMESG-WARN][98], [DMESG-WARN][99], [DMESG-WARN][100], [DMESG-WARN][101], [DMESG-WARN][102], [DMESG-WARN][103], [DMESG-WARN][104], [DMESG-WARN][105], [DMESG-WARN][106], [DMESG-WARN][107], [DMESG-WARN][108], [DMESG-WARN][109], [DMESG-WARN][110])
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-bmg-6/igt@xe_module_load@load.html
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-bmg-7/igt@xe_module_load@load.html
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-bmg-7/igt@xe_module_load@load.html
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-bmg-3/igt@xe_module_load@load.html
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-bmg-6/igt@xe_module_load@load.html
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-bmg-6/igt@xe_module_load@load.html
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-bmg-2/igt@xe_module_load@load.html
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-bmg-2/igt@xe_module_load@load.html
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-bmg-3/igt@xe_module_load@load.html
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-bmg-8/igt@xe_module_load@load.html
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-bmg-8/igt@xe_module_load@load.html
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-bmg-8/igt@xe_module_load@load.html
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-bmg-7/igt@xe_module_load@load.html
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-bmg-5/igt@xe_module_load@load.html
[74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-bmg-2/igt@xe_module_load@load.html
[75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-bmg-2/igt@xe_module_load@load.html
[76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-bmg-1/igt@xe_module_load@load.html
[77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-bmg-5/igt@xe_module_load@load.html
[78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-bmg-8/igt@xe_module_load@load.html
[79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-bmg-4/igt@xe_module_load@load.html
[80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-bmg-4/igt@xe_module_load@load.html
[81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-bmg-4/igt@xe_module_load@load.html
[82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-bmg-6/igt@xe_module_load@load.html
[83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-bmg-6/igt@xe_module_load@load.html
[84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-bmg-1/igt@xe_module_load@load.html
[85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-bmg-1/igt@xe_module_load@load.html
[86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-bmg-2/igt@xe_module_load@load.html
[87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-bmg-2/igt@xe_module_load@load.html
[88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-bmg-2/igt@xe_module_load@load.html
[89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-bmg-5/igt@xe_module_load@load.html
[90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-bmg-5/igt@xe_module_load@load.html
[91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-bmg-5/igt@xe_module_load@load.html
[92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-bmg-4/igt@xe_module_load@load.html
[93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-bmg-4/igt@xe_module_load@load.html
[94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-bmg-7/igt@xe_module_load@load.html
[95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-bmg-7/igt@xe_module_load@load.html
[96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-bmg-7/igt@xe_module_load@load.html
[97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-bmg-7/igt@xe_module_load@load.html
[98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-bmg-6/igt@xe_module_load@load.html
[99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-bmg-6/igt@xe_module_load@load.html
[100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-bmg-6/igt@xe_module_load@load.html
[101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-bmg-3/igt@xe_module_load@load.html
[102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-bmg-3/igt@xe_module_load@load.html
[103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-bmg-3/igt@xe_module_load@load.html
[104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-bmg-3/igt@xe_module_load@load.html
[105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-bmg-8/igt@xe_module_load@load.html
[106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-bmg-8/igt@xe_module_load@load.html
[107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-bmg-8/igt@xe_module_load@load.html
[108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-bmg-1/igt@xe_module_load@load.html
[109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-bmg-1/igt@xe_module_load@load.html
[110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-bmg-1/igt@xe_module_load@load.html
* igt@xe_sriov_scheduling@equal-throughput:
- shard-adlp: [DMESG-FAIL][111] ([Intel XE#3868] / [Intel XE#5213]) -> [ABORT][112] +1 other test abort
[111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-adlp-4/igt@xe_sriov_scheduling@equal-throughput.html
[112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-adlp-2/igt@xe_sriov_scheduling@equal-throughput.html
Known issues
------------
Here are the changes found in xe-pw-156508v2_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_async_flips@crc-atomic@pipe-d-hdmi-a-1:
- shard-adlp: [PASS][113] -> [FAIL][114] ([Intel XE#3884]) +1 other test fail
[113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-adlp-8/igt@kms_async_flips@crc-atomic@pipe-d-hdmi-a-1.html
[114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-adlp-2/igt@kms_async_flips@crc-atomic@pipe-d-hdmi-a-1.html
* igt@kms_big_fb@4-tiled-32bpp-rotate-270:
- shard-dg2-set2: NOTRUN -> [SKIP][115] ([Intel XE#316])
[115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-dg2-435/igt@kms_big_fb@4-tiled-32bpp-rotate-270.html
* igt@kms_big_fb@4-tiled-addfb-size-offset-overflow:
- shard-adlp: NOTRUN -> [SKIP][116] ([Intel XE#607])
[116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-adlp-3/igt@kms_big_fb@4-tiled-addfb-size-offset-overflow.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-180:
- shard-adlp: NOTRUN -> [DMESG-FAIL][117] ([Intel XE#4543])
[117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-adlp-3/igt@kms_big_fb@y-tiled-8bpp-rotate-180.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- shard-adlp: [PASS][118] -> [DMESG-FAIL][119] ([Intel XE#4543]) +11 other tests dmesg-fail
[118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-adlp-6/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
[119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-adlp-3/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_big_fb@yf-tiled-32bpp-rotate-0:
- shard-dg2-set2: NOTRUN -> [SKIP][120] ([Intel XE#1124]) +4 other tests skip
[120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-dg2-435/igt@kms_big_fb@yf-tiled-32bpp-rotate-0.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- shard-adlp: NOTRUN -> [SKIP][121] ([Intel XE#1124]) +1 other test skip
[121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-adlp-4/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_bw@connected-linear-tiling-4-displays-1920x1080p:
- shard-dg2-set2: NOTRUN -> [SKIP][122] ([Intel XE#2191])
[122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-dg2-464/igt@kms_bw@connected-linear-tiling-4-displays-1920x1080p.html
- shard-adlp: NOTRUN -> [SKIP][123] ([Intel XE#2191])
[123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-adlp-2/igt@kms_bw@connected-linear-tiling-4-displays-1920x1080p.html
* igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs-cc@pipe-b-hdmi-a-1:
- shard-adlp: NOTRUN -> [SKIP][124] ([Intel XE#787]) +5 other tests skip
[124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-adlp-8/igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs-cc@pipe-b-hdmi-a-1.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-mc-ccs@pipe-d-hdmi-a-1:
- shard-adlp: NOTRUN -> [SKIP][125] ([Intel XE#455] / [Intel XE#787]) +3 other tests skip
[125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-adlp-1/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-mc-ccs@pipe-d-hdmi-a-1.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs:
- shard-adlp: NOTRUN -> [SKIP][126] ([Intel XE#2907])
[126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-adlp-2/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs.html
- shard-dg2-set2: NOTRUN -> [SKIP][127] ([Intel XE#2907])
[127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-dg2-464/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs.html
* igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-rc-ccs@pipe-c-hdmi-a-6:
- shard-dg2-set2: NOTRUN -> [SKIP][128] ([Intel XE#787]) +27 other tests skip
[128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-dg2-464/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-rc-ccs@pipe-c-hdmi-a-6.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-d-hdmi-a-6:
- shard-dg2-set2: [PASS][129] -> [INCOMPLETE][130] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#6168])
[129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-d-hdmi-a-6.html
[130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-d-hdmi-a-6.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-d-hdmi-a-6:
- shard-dg2-set2: NOTRUN -> [INCOMPLETE][131] ([Intel XE#2705] / [Intel XE#4212] / [Intel XE#4522])
[131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-d-hdmi-a-6.html
* igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs-cc:
- shard-dg2-set2: NOTRUN -> [SKIP][132] ([Intel XE#455] / [Intel XE#787]) +7 other tests skip
[132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs-cc.html
* igt@kms_chamelium_edid@hdmi-edid-read:
- shard-dg2-set2: NOTRUN -> [SKIP][133] ([Intel XE#373]) +1 other test skip
[133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-dg2-435/igt@kms_chamelium_edid@hdmi-edid-read.html
* igt@kms_chamelium_hpd@dp-hpd-for-each-pipe:
- shard-adlp: NOTRUN -> [SKIP][134] ([Intel XE#373]) +1 other test skip
[134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-adlp-1/igt@kms_chamelium_hpd@dp-hpd-for-each-pipe.html
* igt@kms_content_protection@dp-mst-type-0:
- shard-adlp: NOTRUN -> [SKIP][135] ([Intel XE#307])
[135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-adlp-9/igt@kms_content_protection@dp-mst-type-0.html
- shard-dg2-set2: NOTRUN -> [SKIP][136] ([Intel XE#307])
[136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-dg2-466/igt@kms_content_protection@dp-mst-type-0.html
* igt@kms_dsc@dsc-with-output-formats-with-bpc:
- shard-dg2-set2: NOTRUN -> [SKIP][137] ([Intel XE#455]) +6 other tests skip
[137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-dg2-463/igt@kms_dsc@dsc-with-output-formats-with-bpc.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-adlp: [PASS][138] -> [DMESG-WARN][139] ([Intel XE#4543]) +7 other tests dmesg-warn
[138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-adlp-9/igt@kms_flip@flip-vs-suspend-interruptible.html
[139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-adlp-9/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling:
- shard-adlp: NOTRUN -> [SKIP][140] ([Intel XE#455]) +5 other tests skip
[140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-adlp-4/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling.html
* igt@kms_frontbuffer_tracking@drrs-1p-offscreen-pri-indfb-draw-render:
- shard-adlp: NOTRUN -> [SKIP][141] ([Intel XE#6312])
[141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-adlp-6/igt@kms_frontbuffer_tracking@drrs-1p-offscreen-pri-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@drrs-2p-primscrn-indfb-pgflip-blt:
- shard-adlp: NOTRUN -> [SKIP][142] ([Intel XE#656]) +6 other tests skip
[142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-adlp-6/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-indfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@drrs-indfb-scaledprimary:
- shard-dg2-set2: NOTRUN -> [SKIP][143] ([Intel XE#651]) +5 other tests skip
[143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-dg2-433/igt@kms_frontbuffer_tracking@drrs-indfb-scaledprimary.html
* igt@kms_frontbuffer_tracking@fbcdrrs-1p-offscreen-pri-indfb-draw-render:
- shard-dg2-set2: NOTRUN -> [SKIP][144] ([Intel XE#6312]) +1 other test skip
[144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-dg2-464/igt@kms_frontbuffer_tracking@fbcdrrs-1p-offscreen-pri-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-render:
- shard-adlp: NOTRUN -> [SKIP][145] ([Intel XE#653]) +2 other tests skip
[145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-adlp-2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-slowdraw:
- shard-dg2-set2: NOTRUN -> [SKIP][146] ([Intel XE#653]) +8 other tests skip
[146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-dg2-463/igt@kms_frontbuffer_tracking@fbcpsr-slowdraw.html
* igt@kms_pm_rpm@dpms-non-lpsp:
- shard-adlp: NOTRUN -> [SKIP][147] ([Intel XE#836])
[147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-adlp-4/igt@kms_pm_rpm@dpms-non-lpsp.html
* igt@kms_psr2_sf@fbc-pr-overlay-plane-update-continuous-sf:
- shard-adlp: NOTRUN -> [SKIP][148] ([Intel XE#1406] / [Intel XE#1489]) +2 other tests skip
[148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-adlp-9/igt@kms_psr2_sf@fbc-pr-overlay-plane-update-continuous-sf.html
- shard-dg2-set2: NOTRUN -> [SKIP][149] ([Intel XE#1406] / [Intel XE#1489]) +2 other tests skip
[149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-dg2-466/igt@kms_psr2_sf@fbc-pr-overlay-plane-update-continuous-sf.html
* igt@kms_psr2_su@page_flip-nv12:
- shard-dg2-set2: NOTRUN -> [SKIP][150] ([Intel XE#1122] / [Intel XE#1406]) +1 other test skip
[150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-dg2-435/igt@kms_psr2_su@page_flip-nv12.html
* igt@kms_psr@fbc-psr-sprite-render:
- shard-dg2-set2: NOTRUN -> [SKIP][151] ([Intel XE#1406] / [Intel XE#2850] / [Intel XE#929]) +6 other tests skip
[151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-dg2-436/igt@kms_psr@fbc-psr-sprite-render.html
* igt@kms_psr@pr-sprite-render:
- shard-adlp: NOTRUN -> [SKIP][152] ([Intel XE#1406] / [Intel XE#2850] / [Intel XE#929]) +2 other tests skip
[152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-adlp-2/igt@kms_psr@pr-sprite-render.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-0:
- shard-dg2-set2: NOTRUN -> [SKIP][153] ([Intel XE#1127])
[153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-dg2-436/igt@kms_rotation_crc@primary-y-tiled-reflect-x-0.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-90:
- shard-dg2-set2: NOTRUN -> [SKIP][154] ([Intel XE#3414]) +1 other test skip
[154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-dg2-463/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html
- shard-adlp: NOTRUN -> [SKIP][155] ([Intel XE#3414])
[155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-adlp-9/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html
* igt@kms_vrr@lobf:
- shard-adlp: NOTRUN -> [SKIP][156] ([Intel XE#2168])
[156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-adlp-4/igt@kms_vrr@lobf.html
- shard-dg2-set2: NOTRUN -> [SKIP][157] ([Intel XE#2168])
[157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-dg2-432/igt@kms_vrr@lobf.html
* igt@xe_configfs@survivability-mode:
- shard-dg2-set2: NOTRUN -> [SKIP][158] ([Intel XE#6010])
[158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-dg2-463/igt@xe_configfs@survivability-mode.html
* igt@xe_copy_basic@mem-copy-linear-0xfd:
- shard-dg2-set2: NOTRUN -> [SKIP][159] ([Intel XE#1123])
[159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-dg2-466/igt@xe_copy_basic@mem-copy-linear-0xfd.html
* igt@xe_eudebug_online@resume-one:
- shard-adlp: NOTRUN -> [SKIP][160] ([Intel XE#4837] / [Intel XE#5565]) +2 other tests skip
[160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-adlp-1/igt@xe_eudebug_online@resume-one.html
* igt@xe_evict@evict-beng-large-external-cm:
- shard-adlp: NOTRUN -> [SKIP][161] ([Intel XE#261] / [Intel XE#5564])
[161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-adlp-1/igt@xe_evict@evict-beng-large-external-cm.html
* igt@xe_evict@evict-small-cm:
- shard-adlp: NOTRUN -> [SKIP][162] ([Intel XE#261] / [Intel XE#5564] / [Intel XE#688])
[162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-adlp-1/igt@xe_evict@evict-small-cm.html
* igt@xe_exec_fault_mode@invalid-va-scratch-nopagefault:
- shard-adlp: NOTRUN -> [SKIP][163] ([Intel XE#288] / [Intel XE#5561]) +3 other tests skip
[163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-adlp-4/igt@xe_exec_fault_mode@invalid-va-scratch-nopagefault.html
* igt@xe_exec_fault_mode@once-rebind-prefetch:
- shard-dg2-set2: NOTRUN -> [SKIP][164] ([Intel XE#288]) +6 other tests skip
[164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-dg2-436/igt@xe_exec_fault_mode@once-rebind-prefetch.html
* igt@xe_exec_mix_modes@exec-spinner-interrupted-dma-fence:
- shard-adlp: NOTRUN -> [SKIP][165] ([Intel XE#2360])
[165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-adlp-2/igt@xe_exec_mix_modes@exec-spinner-interrupted-dma-fence.html
* igt@xe_exec_sip_eudebug@wait-writesip-nodebug:
- shard-dg2-set2: NOTRUN -> [SKIP][166] ([Intel XE#4837]) +6 other tests skip
[166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-dg2-432/igt@xe_exec_sip_eudebug@wait-writesip-nodebug.html
* igt@xe_exec_system_allocator@once-mmap-remap-ro-dontunmap:
- shard-adlp: NOTRUN -> [SKIP][167] ([Intel XE#4915]) +56 other tests skip
[167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-adlp-8/igt@xe_exec_system_allocator@once-mmap-remap-ro-dontunmap.html
* igt@xe_exec_system_allocator@threads-many-large-mmap-mlock:
- shard-dg2-set2: NOTRUN -> [SKIP][168] ([Intel XE#4915]) +118 other tests skip
[168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-dg2-432/igt@xe_exec_system_allocator@threads-many-large-mmap-mlock.html
* igt@xe_fault_injection@probe-fail-guc-xe_guc_mmio_send_recv:
- shard-dg2-set2: [PASS][169] -> [DMESG-WARN][170] ([Intel XE#5893]) +1 other test dmesg-warn
[169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-dg2-463/igt@xe_fault_injection@probe-fail-guc-xe_guc_mmio_send_recv.html
[170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-dg2-435/igt@xe_fault_injection@probe-fail-guc-xe_guc_mmio_send_recv.html
* igt@xe_live_ktest@xe_eudebug:
- shard-adlp: NOTRUN -> [SKIP][171] ([Intel XE#455] / [Intel XE#5712])
[171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-adlp-8/igt@xe_live_ktest@xe_eudebug.html
* igt@xe_oa@mmio-triggered-reports-read:
- shard-adlp: NOTRUN -> [SKIP][172] ([Intel XE#6032])
[172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-adlp-3/igt@xe_oa@mmio-triggered-reports-read.html
* igt@xe_oa@non-privileged-map-oa-buffer:
- shard-dg2-set2: NOTRUN -> [SKIP][173] ([Intel XE#3573]) +1 other test skip
[173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-dg2-466/igt@xe_oa@non-privileged-map-oa-buffer.html
- shard-adlp: NOTRUN -> [SKIP][174] ([Intel XE#3573])
[174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-adlp-9/igt@xe_oa@non-privileged-map-oa-buffer.html
* igt@xe_peer2peer@write:
- shard-adlp: NOTRUN -> [SKIP][175] ([Intel XE#1061] / [Intel XE#5568])
[175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-adlp-3/igt@xe_peer2peer@write.html
* igt@xe_peer2peer@write@write-gpua-vram01-gpub-system-p2p:
- shard-dg2-set2: NOTRUN -> [FAIL][176] ([Intel XE#1173]) +1 other test fail
[176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-dg2-435/igt@xe_peer2peer@write@write-gpua-vram01-gpub-system-p2p.html
* igt@xe_pm@s2idle-vm-bind-unbind-all:
- shard-dg2-set2: [PASS][177] -> [TIMEOUT][178] ([Intel XE#6227])
[177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-dg2-434/igt@xe_pm@s2idle-vm-bind-unbind-all.html
[178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-dg2-435/igt@xe_pm@s2idle-vm-bind-unbind-all.html
* igt@xe_pm@s4-mocs:
- shard-adlp: NOTRUN -> [FAIL][179] ([Intel XE#6406])
[179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-adlp-1/igt@xe_pm@s4-mocs.html
* igt@xe_pxp@pxp-stale-queue-post-suspend:
- shard-dg2-set2: NOTRUN -> [SKIP][180] ([Intel XE#4733])
[180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-dg2-436/igt@xe_pxp@pxp-stale-queue-post-suspend.html
* igt@xe_query@multigpu-query-uc-fw-version-huc:
- shard-adlp: NOTRUN -> [SKIP][181] ([Intel XE#944])
[181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-adlp-1/igt@xe_query@multigpu-query-uc-fw-version-huc.html
- shard-dg2-set2: NOTRUN -> [SKIP][182] ([Intel XE#944])
[182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-dg2-434/igt@xe_query@multigpu-query-uc-fw-version-huc.html
* igt@xe_sriov_vram@vf-access-after-resize-up:
- shard-dg2-set2: NOTRUN -> [SKIP][183] ([Intel XE#6318])
[183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-dg2-436/igt@xe_sriov_vram@vf-access-after-resize-up.html
- shard-adlp: NOTRUN -> [SKIP][184] ([Intel XE#6376])
[184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-adlp-8/igt@xe_sriov_vram@vf-access-after-resize-up.html
#### Possible fixes ####
* igt@kms_async_flips@test-time-stamp-atomic:
- shard-adlp: [DMESG-WARN][185] ([Intel XE#4917]) -> [PASS][186]
[185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-adlp-4/igt@kms_async_flips@test-time-stamp-atomic.html
[186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-adlp-4/igt@kms_async_flips@test-time-stamp-atomic.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- shard-adlp: [DMESG-FAIL][187] ([Intel XE#4543]) -> [PASS][188] +11 other tests pass
[187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-adlp-9/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
[188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-adlp-3/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-dp-4:
- shard-dg2-set2: [INCOMPLETE][189] ([Intel XE#1727] / [Intel XE#3113]) -> [PASS][190]
[189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-dg2-432/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-dp-4.html
[190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-dp-4.html
* igt@kms_flip@flip-vs-panning-interruptible:
- shard-adlp: [DMESG-WARN][191] ([Intel XE#4543] / [Intel XE#5208]) -> [PASS][192]
[191]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-adlp-1/igt@kms_flip@flip-vs-panning-interruptible.html
[192]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-adlp-1/igt@kms_flip@flip-vs-panning-interruptible.html
* igt@kms_flip@flip-vs-panning-interruptible@b-hdmi-a1:
- shard-adlp: [DMESG-WARN][193] ([Intel XE#4543]) -> [PASS][194] +10 other tests pass
[193]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-adlp-1/igt@kms_flip@flip-vs-panning-interruptible@b-hdmi-a1.html
[194]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-adlp-1/igt@kms_flip@flip-vs-panning-interruptible@b-hdmi-a1.html
* igt@kms_flip@flip-vs-panning-vs-hang@d-hdmi-a1:
- shard-adlp: [TIMEOUT][195] ([Intel XE#4543]) -> [PASS][196] +1 other test pass
[195]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-adlp-1/igt@kms_flip@flip-vs-panning-vs-hang@d-hdmi-a1.html
[196]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-adlp-2/igt@kms_flip@flip-vs-panning-vs-hang@d-hdmi-a1.html
* igt@kms_flip@flip-vs-suspend@b-hdmi-a1:
- shard-adlp: [DMESG-WARN][197] ([Intel XE#2953] / [Intel XE#4173]) -> [PASS][198] +8 other tests pass
[197]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-adlp-6/igt@kms_flip@flip-vs-suspend@b-hdmi-a1.html
[198]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-adlp-9/igt@kms_flip@flip-vs-suspend@b-hdmi-a1.html
* igt@kms_flip@flip-vs-suspend@d-dp4:
- shard-dg2-set2: [INCOMPLETE][199] ([Intel XE#2049] / [Intel XE#2597]) -> [PASS][200] +1 other test pass
[199]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-dg2-434/igt@kms_flip@flip-vs-suspend@d-dp4.html
[200]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-dg2-464/igt@kms_flip@flip-vs-suspend@d-dp4.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling@pipe-a-valid-mode:
- shard-adlp: [DMESG-FAIL][201] ([Intel XE#4543] / [Intel XE#4921]) -> [PASS][202] +1 other test pass
[201]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-adlp-1/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling@pipe-a-valid-mode.html
[202]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-adlp-6/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling@pipe-a-valid-mode.html
* igt@xe_configfs@engines-allowed-invalid:
- shard-adlp: [ABORT][203] ([Intel XE#5466]) -> [PASS][204]
[203]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-adlp-4/igt@xe_configfs@engines-allowed-invalid.html
[204]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-adlp-3/igt@xe_configfs@engines-allowed-invalid.html
* igt@xe_gt_freq@freq_fixed_idle:
- shard-dg2-set2: [FAIL][205] ([Intel XE#6407]) -> [PASS][206]
[205]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-dg2-432/igt@xe_gt_freq@freq_fixed_idle.html
[206]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-dg2-434/igt@xe_gt_freq@freq_fixed_idle.html
* igt@xe_pm@s2idle-basic:
- shard-adlp: [DMESG-WARN][207] ([Intel XE#2953] / [Intel XE#4173] / [Intel XE#4504]) -> [PASS][208]
[207]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-adlp-8/igt@xe_pm@s2idle-basic.html
[208]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-adlp-6/igt@xe_pm@s2idle-basic.html
#### Warnings ####
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs:
- shard-dg2-set2: [INCOMPLETE][209] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4345] / [Intel XE#4522]) -> [INCOMPLETE][210] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4345] / [Intel XE#6168])
[209]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html
[210]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs:
- shard-dg2-set2: [INCOMPLETE][211] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4345]) -> [INCOMPLETE][212] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#4212] / [Intel XE#4345] / [Intel XE#4522])
[211]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-dg2-432/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
[212]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
* igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling@pipe-a-valid-mode:
- shard-adlp: [DMESG-WARN][213] ([Intel XE#2953] / [Intel XE#4173]) -> [DMESG-FAIL][214] ([Intel XE#4543] / [Intel XE#4921]) +1 other test dmesg-fail
[213]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-adlp-8/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling@pipe-a-valid-mode.html
[214]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-adlp-2/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling@pipe-a-valid-mode.html
* igt@xe_exec_basic@multigpu-no-exec-null-rebind:
- shard-adlp: [DMESG-WARN][215] ([Intel XE#4917]) -> [SKIP][216] ([Intel XE#1392] / [Intel XE#5575])
[215]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-adlp-4/igt@xe_exec_basic@multigpu-no-exec-null-rebind.html
[216]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-adlp-2/igt@xe_exec_basic@multigpu-no-exec-null-rebind.html
* igt@xe_live_ktest@xe_dma_buf:
- shard-dg2-set2: [FAIL][217] ([Intel XE#3099]) -> [INCOMPLETE][218] ([Intel XE#4842]) +1 other test incomplete
[217]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e/shard-dg2-464/igt@xe_live_ktest@xe_dma_buf.html
[218]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/shard-dg2-436/igt@xe_live_ktest@xe_dma_buf.html
[Intel XE#1061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1061
[Intel XE#1122]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1122
[Intel XE#1123]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1123
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127
[Intel XE#1173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1173
[Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
[Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
[Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
[Intel XE#2168]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2168
[Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
[Intel XE#2360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2360
[Intel XE#2457]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2457
[Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597
[Intel XE#261]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/261
[Intel XE#2705]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2705
[Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
[Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
[Intel XE#2907]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2907
[Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
[Intel XE#307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/307
[Intel XE#3099]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3099
[Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
[Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
[Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
[Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
[Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
[Intel XE#3868]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3868
[Intel XE#3884]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3884
[Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
[Intel XE#4212]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4212
[Intel XE#4345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4345
[Intel XE#4504]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4504
[Intel XE#4522]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4522
[Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
[Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
[Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
[Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
[Intel XE#4842]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4842
[Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
[Intel XE#4917]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4917
[Intel XE#4921]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4921
[Intel XE#5208]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5208
[Intel XE#5213]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5213
[Intel XE#5466]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5466
[Intel XE#5561]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5561
[Intel XE#5564]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5564
[Intel XE#5565]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5565
[Intel XE#5568]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5568
[Intel XE#5575]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5575
[Intel XE#5712]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5712
[Intel XE#5893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5893
[Intel XE#6010]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6010
[Intel XE#6032]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6032
[Intel XE#607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/607
[Intel XE#6168]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6168
[Intel XE#6227]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6227
[Intel XE#6295]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6295
[Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
[Intel XE#6318]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6318
[Intel XE#6376]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6376
[Intel XE#6406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6406
[Intel XE#6407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6407
[Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
[Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
[Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
[Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
[Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
[Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
[Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
[Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
Build changes
-------------
* IGT: IGT_8597 -> IGT_8598
* Linux: xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e -> xe-pw-156508v2
IGT_8597: 8597
IGT_8598: 8598
xe-3994-de43fe70c436c359e7478a5532d873f87357cb4e: de43fe70c436c359e7478a5532d873f87357cb4e
xe-pw-156508v2: 156508v2
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156508v2/index.html
[-- Attachment #2: Type: text/html, Size: 57072 bytes --]
^ permalink raw reply [flat|nested] 16+ messages in thread