From: Mika Kahola <mika.kahola@intel.com>
To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Cc: Mika Kahola <mika.kahola@intel.com>
Subject: [CI 01/32] drm/i915/display: Rename TBT functions to be ICL specific
Date: Fri, 31 Oct 2025 12:35:18 +0200 [thread overview]
Message-ID: <20251031103549.173208-2-mika.kahola@intel.com> (raw)
In-Reply-To: <20251031103549.173208-1-mika.kahola@intel.com>
Rename pll functions to include ICL platform as these are
used from ICL onwards.
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 30 +++++++++----------
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 8ea96cc524a1..303f03b420ae 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3754,9 +3754,9 @@ static bool combo_pll_get_hw_state(struct intel_display *display,
return icl_pll_get_hw_state(display, pll, dpll_hw_state, enable_reg);
}
-static bool tbt_pll_get_hw_state(struct intel_display *display,
- struct intel_dpll *pll,
- struct intel_dpll_hw_state *dpll_hw_state)
+static bool icl_tbt_pll_get_hw_state(struct intel_display *display,
+ struct intel_dpll *pll,
+ struct intel_dpll_hw_state *dpll_hw_state)
{
return icl_pll_get_hw_state(display, pll, dpll_hw_state, TBT_PLL_ENABLE);
}
@@ -3985,9 +3985,9 @@ static void combo_pll_enable(struct intel_display *display,
/* DVFS post sequence would be here. See the comment above. */
}
-static void tbt_pll_enable(struct intel_display *display,
- struct intel_dpll *pll,
- const struct intel_dpll_hw_state *dpll_hw_state)
+static void icl_tbt_pll_enable(struct intel_display *display,
+ struct intel_dpll *pll,
+ const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
@@ -4070,8 +4070,8 @@ static void combo_pll_disable(struct intel_display *display,
icl_pll_disable(display, pll, enable_reg);
}
-static void tbt_pll_disable(struct intel_display *display,
- struct intel_dpll *pll)
+static void icl_tbt_pll_disable(struct intel_display *display,
+ struct intel_dpll *pll)
{
icl_pll_disable(display, pll, TBT_PLL_ENABLE);
}
@@ -4143,10 +4143,10 @@ static const struct intel_dpll_funcs combo_pll_funcs = {
.get_freq = icl_ddi_combo_pll_get_freq,
};
-static const struct intel_dpll_funcs tbt_pll_funcs = {
- .enable = tbt_pll_enable,
- .disable = tbt_pll_disable,
- .get_hw_state = tbt_pll_get_hw_state,
+static const struct intel_dpll_funcs icl_tbt_pll_funcs = {
+ .enable = icl_tbt_pll_enable,
+ .disable = icl_tbt_pll_disable,
+ .get_hw_state = icl_tbt_pll_get_hw_state,
.get_freq = icl_ddi_tbt_pll_get_freq,
};
@@ -4160,7 +4160,7 @@ static const struct intel_dpll_funcs mg_pll_funcs = {
static const struct dpll_info icl_plls[] = {
{ .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
{ .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
- { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
+ { .name = "TBT PLL", .funcs = &icl_tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
.is_alt_port_dpll = true, },
{ .name = "MG PLL 1", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
{ .name = "MG PLL 2", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
@@ -4208,7 +4208,7 @@ static const struct intel_dpll_funcs dkl_pll_funcs = {
static const struct dpll_info tgl_plls[] = {
{ .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
{ .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
- { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
+ { .name = "TBT PLL", .funcs = &icl_tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
.is_alt_port_dpll = true, },
{ .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
{ .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
@@ -4286,7 +4286,7 @@ static const struct intel_dpll_mgr adls_pll_mgr = {
static const struct dpll_info adlp_plls[] = {
{ .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
{ .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
- { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
+ { .name = "TBT PLL", .funcs = &icl_tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
.is_alt_port_dpll = true, },
{ .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
{ .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
--
2.34.1
next prev parent reply other threads:[~2025-10-31 10:47 UTC|newest]
Thread overview: 77+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-31 10:35 [CI 00/32] [PATCH 00/32] drm/i915/display: Add MTL+ platforms to support dpll framework Mika Kahola
2025-10-31 10:35 ` Mika Kahola [this message]
2025-11-11 5:21 ` [CI 01/32] drm/i915/display: Rename TBT functions to be ICL specific Kandpal, Suraj
2025-10-31 10:35 ` [CI 02/32] drm/i915/display: Factor out C10 msgbus access start/end helpers Mika Kahola
2025-11-11 5:26 ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 03/32] drm/i915/display: Sanitize setting the Cx0 PLL use_c10 flag Mika Kahola
2025-11-11 5:29 ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 04/32] drm/i915/display: Sanitize calculating C20 PLL state from tables Mika Kahola
2025-11-11 5:36 ` Kandpal, Suraj
2025-11-11 10:02 ` Imre Deak
2025-11-12 4:10 ` Kandpal, Suraj
2025-11-12 12:58 ` Imre Deak
2025-10-31 10:35 ` [CI 05/32] drm/i915/display: Track the C20 PHY VDR state in the PLL state Mika Kahola
2025-11-11 5:43 ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 06/32] drm/i915/display: Move definition of Cx0 PHY functions earlier Mika Kahola
2025-11-11 5:45 ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 07/32] drm/i915/display: Add macro to get DDI port width from a register value Mika Kahola
2025-11-11 5:47 ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 08/32] drm/i915/display: Track the Cx0 PHY enabled lane count in the PLL state Mika Kahola
2025-11-11 5:55 ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 09/32] drm/i915/display: Sanitize C10 PHY PLL SSC register setup Mika Kahola
2025-11-11 5:56 ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 10/32] drm/i915/display: Read out the Cx0 PHY SSC enabled state Mika Kahola
2025-11-12 4:13 ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 11/32] drm/i915/display: Determine Cx0 PLL DP mode from PLL state Mika Kahola
2025-11-11 6:08 ` Kandpal, Suraj
2025-11-11 10:11 ` Imre Deak
2025-11-12 4:15 ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 12/32] drm/i915/display: Determine Cx0 PLL port clock " Mika Kahola
2025-11-11 6:11 ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 13/32] drm/i915/display: Zero Cx0 PLL state before compute and HW readout Mika Kahola
2025-11-11 6:13 ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 14/32] drm/i915/display: Print additional Cx0 PLL HW state Mika Kahola
2025-11-11 6:17 ` Kandpal, Suraj
2025-11-11 11:14 ` Jani Nikula
2025-11-11 11:16 ` Jani Nikula
2025-11-11 12:34 ` Imre Deak
2025-10-31 10:35 ` [CI 15/32] drm/i915/display: Remove state verification Mika Kahola
2025-11-11 6:20 ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 16/32] drm/i915/display: PLL information for MTL+ Mika Kahola
2025-11-12 4:19 ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 17/32] drm/i915/display: Update C10/C20 state calculation Mika Kahola
2025-11-12 4:28 ` Kandpal, Suraj
2025-11-12 13:52 ` Kahola, Mika
2025-10-31 10:35 ` [CI 18/32] drm/i915/display: Compute plls for MTL+ platform Mika Kahola
2025-11-12 4:41 ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 19/32] drm/i915/display: MTL+ .get_dplls Mika Kahola
2025-11-12 4:47 ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 20/32] drm/i915/display: MTL+ .put_dplls Mika Kahola
2025-11-12 4:49 ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 21/32] drm/i915/display: Add .update_active_dpll Mika Kahola
2025-11-12 4:50 ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 22/32] drm/i915/display: Add .update_dpll_ref_clks Mika Kahola
2025-11-12 4:51 ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 23/32] drm/i915/display: Add .dump_hw_state Mika Kahola
2025-11-12 5:07 ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 24/32] drm/i915/display: Add .compare_hw_state Mika Kahola
2025-11-12 5:10 ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 25/32] drm/i915/display: Add .get_hw_state to MTL+ platforms Mika Kahola
2025-11-12 5:14 ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 26/32] drm/i915/display: Add .get_freq " Mika Kahola
2025-11-12 5:19 ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 27/32] drm/i915/display: Add .crtc_get_dpll hook Mika Kahola
2025-11-12 5:20 ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 28/32] drm/i915/display: PLL verify debug state print Mika Kahola
2025-11-12 5:27 ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 29/32] drm/i915/display: Add .enable_clock on DDI for MTL+ platforms Mika Kahola
2025-11-12 5:32 ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 30/32] drm/i915/display: Get configuration for C10 and C20 Mika Kahola
2025-10-31 10:35 ` [CI 31/32] drm/i915/display: Add Thunderbolt support Mika Kahola
2025-10-31 10:35 ` [CI 32/32] drm/i915/display: Enable dpll framework for MTL+ Mika Kahola
2025-11-12 5:39 ` Kandpal, Suraj
2025-10-31 12:48 ` ✗ CI.checkpatch: warning for drm/i915/display: Add MTL+ platforms to support dpll framework (rev2) Patchwork
2025-10-31 12:49 ` ✓ CI.KUnit: success " Patchwork
2025-10-31 13:04 ` ✗ CI.checksparse: warning " Patchwork
2025-10-31 13:54 ` ✓ Xe.CI.BAT: success " Patchwork
2025-11-01 0:15 ` ✗ Xe.CI.Full: failure " Patchwork
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