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From: Imre Deak <imre.deak@intel.com>
To: Suraj Kandpal <suraj.kandpal@intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>,
	"intel-xe@lists.freedesktop.org" <intel-xe@lists.freedesktop.org>
Subject: Re: [CI 11/32] drm/i915/display: Determine Cx0 PLL DP mode from PLL state
Date: Tue, 11 Nov 2025 12:11:31 +0200	[thread overview]
Message-ID: <aRML00uJoXeoHj8J@ideak-desk> (raw)
In-Reply-To: <IA3PR11MB893752DEB841A09898BEB562E3CFA@IA3PR11MB8937.namprd11.prod.outlook.com>

On Tue, Nov 11, 2025 at 08:08:34AM +0200, Suraj Kandpal wrote:
> [...]
> > @@ -2929,10 +2958,11 @@ static void intel_c20_pll_program(struct
> > intel_display *display,
> > 
> >  static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
> >  					 const struct intel_cx0pll_state *pll_state,
> > -					 bool is_dp, int port_clock,
> > +					 int port_clock,
> >  					 bool lane_reversal)
> >  {
> >  	struct intel_display *display = to_intel_display(encoder);
> > +	bool is_dp = cx0pll_state_is_dp(pll_state);
> 
> Wouldn't a simple check of drm_encoder's type tell us if it is dp or not ?

For a DDI encoder drm_encoder::encoder_type is DRM_MODE_ENCODER_TMDS,
from which you can't determine if the encoder is used for a DP or HDMI
output. This also applies to intel_encoder_is_dp(), which will return
true if for instance a DDI encoder wired to a DP++ connector is used for
an HDMI output.

> Regards,
> Suraj Kandpal

  reply	other threads:[~2025-11-11 10:11 UTC|newest]

Thread overview: 77+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-31 10:35 [CI 00/32] [PATCH 00/32] drm/i915/display: Add MTL+ platforms to support dpll framework Mika Kahola
2025-10-31 10:35 ` [CI 01/32] drm/i915/display: Rename TBT functions to be ICL specific Mika Kahola
2025-11-11  5:21   ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 02/32] drm/i915/display: Factor out C10 msgbus access start/end helpers Mika Kahola
2025-11-11  5:26   ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 03/32] drm/i915/display: Sanitize setting the Cx0 PLL use_c10 flag Mika Kahola
2025-11-11  5:29   ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 04/32] drm/i915/display: Sanitize calculating C20 PLL state from tables Mika Kahola
2025-11-11  5:36   ` Kandpal, Suraj
2025-11-11 10:02     ` Imre Deak
2025-11-12  4:10       ` Kandpal, Suraj
2025-11-12 12:58         ` Imre Deak
2025-10-31 10:35 ` [CI 05/32] drm/i915/display: Track the C20 PHY VDR state in the PLL state Mika Kahola
2025-11-11  5:43   ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 06/32] drm/i915/display: Move definition of Cx0 PHY functions earlier Mika Kahola
2025-11-11  5:45   ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 07/32] drm/i915/display: Add macro to get DDI port width from a register value Mika Kahola
2025-11-11  5:47   ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 08/32] drm/i915/display: Track the Cx0 PHY enabled lane count in the PLL state Mika Kahola
2025-11-11  5:55   ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 09/32] drm/i915/display: Sanitize C10 PHY PLL SSC register setup Mika Kahola
2025-11-11  5:56   ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 10/32] drm/i915/display: Read out the Cx0 PHY SSC enabled state Mika Kahola
2025-11-12  4:13   ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 11/32] drm/i915/display: Determine Cx0 PLL DP mode from PLL state Mika Kahola
2025-11-11  6:08   ` Kandpal, Suraj
2025-11-11 10:11     ` Imre Deak [this message]
2025-11-12  4:15       ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 12/32] drm/i915/display: Determine Cx0 PLL port clock " Mika Kahola
2025-11-11  6:11   ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 13/32] drm/i915/display: Zero Cx0 PLL state before compute and HW readout Mika Kahola
2025-11-11  6:13   ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 14/32] drm/i915/display: Print additional Cx0 PLL HW state Mika Kahola
2025-11-11  6:17   ` Kandpal, Suraj
2025-11-11 11:14   ` Jani Nikula
2025-11-11 11:16     ` Jani Nikula
2025-11-11 12:34       ` Imre Deak
2025-10-31 10:35 ` [CI 15/32] drm/i915/display: Remove state verification Mika Kahola
2025-11-11  6:20   ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 16/32] drm/i915/display: PLL information for MTL+ Mika Kahola
2025-11-12  4:19   ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 17/32] drm/i915/display: Update C10/C20 state calculation Mika Kahola
2025-11-12  4:28   ` Kandpal, Suraj
2025-11-12 13:52     ` Kahola, Mika
2025-10-31 10:35 ` [CI 18/32] drm/i915/display: Compute plls for MTL+ platform Mika Kahola
2025-11-12  4:41   ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 19/32] drm/i915/display: MTL+ .get_dplls Mika Kahola
2025-11-12  4:47   ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 20/32] drm/i915/display: MTL+ .put_dplls Mika Kahola
2025-11-12  4:49   ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 21/32] drm/i915/display: Add .update_active_dpll Mika Kahola
2025-11-12  4:50   ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 22/32] drm/i915/display: Add .update_dpll_ref_clks Mika Kahola
2025-11-12  4:51   ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 23/32] drm/i915/display: Add .dump_hw_state Mika Kahola
2025-11-12  5:07   ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 24/32] drm/i915/display: Add .compare_hw_state Mika Kahola
2025-11-12  5:10   ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 25/32] drm/i915/display: Add .get_hw_state to MTL+ platforms Mika Kahola
2025-11-12  5:14   ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 26/32] drm/i915/display: Add .get_freq " Mika Kahola
2025-11-12  5:19   ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 27/32] drm/i915/display: Add .crtc_get_dpll hook Mika Kahola
2025-11-12  5:20   ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 28/32] drm/i915/display: PLL verify debug state print Mika Kahola
2025-11-12  5:27   ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 29/32] drm/i915/display: Add .enable_clock on DDI for MTL+ platforms Mika Kahola
2025-11-12  5:32   ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 30/32] drm/i915/display: Get configuration for C10 and C20 Mika Kahola
2025-10-31 10:35 ` [CI 31/32] drm/i915/display: Add Thunderbolt support Mika Kahola
2025-10-31 10:35 ` [CI 32/32] drm/i915/display: Enable dpll framework for MTL+ Mika Kahola
2025-11-12  5:39   ` Kandpal, Suraj
2025-10-31 12:48 ` ✗ CI.checkpatch: warning for drm/i915/display: Add MTL+ platforms to support dpll framework (rev2) Patchwork
2025-10-31 12:49 ` ✓ CI.KUnit: success " Patchwork
2025-10-31 13:04 ` ✗ CI.checksparse: warning " Patchwork
2025-10-31 13:54 ` ✓ Xe.CI.BAT: success " Patchwork
2025-11-01  0:15 ` ✗ Xe.CI.Full: failure " Patchwork

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