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From: Mika Kahola <mika.kahola@intel.com>
To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Cc: Mika Kahola <mika.kahola@intel.com>,
	Suraj Kandpal <suraj.kandpal@intel.com>
Subject: [PATCH v2 01/32] drm/i915/cx0: Rename TBT functions to be ICL specific
Date: Mon, 17 Nov 2025 12:45:31 +0200	[thread overview]
Message-ID: <20251117104602.2363671-2-mika.kahola@intel.com> (raw)
In-Reply-To: <20251117104602.2363671-1-mika.kahola@intel.com>

Rename pll functions to include ICL platform as these are
used from ICL onwards.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 30 +++++++++----------
 1 file changed, 15 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 9c7cf03cf022..8c345e1bdd94 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3753,9 +3753,9 @@ static bool combo_pll_get_hw_state(struct intel_display *display,
 	return icl_pll_get_hw_state(display, pll, dpll_hw_state, enable_reg);
 }
 
-static bool tbt_pll_get_hw_state(struct intel_display *display,
-				 struct intel_dpll *pll,
-				 struct intel_dpll_hw_state *dpll_hw_state)
+static bool icl_tbt_pll_get_hw_state(struct intel_display *display,
+				     struct intel_dpll *pll,
+				     struct intel_dpll_hw_state *dpll_hw_state)
 {
 	return icl_pll_get_hw_state(display, pll, dpll_hw_state, TBT_PLL_ENABLE);
 }
@@ -3984,9 +3984,9 @@ static void combo_pll_enable(struct intel_display *display,
 	/* DVFS post sequence would be here. See the comment above. */
 }
 
-static void tbt_pll_enable(struct intel_display *display,
-			   struct intel_dpll *pll,
-			   const struct intel_dpll_hw_state *dpll_hw_state)
+static void icl_tbt_pll_enable(struct intel_display *display,
+			       struct intel_dpll *pll,
+			       const struct intel_dpll_hw_state *dpll_hw_state)
 {
 	const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
 
@@ -4069,8 +4069,8 @@ static void combo_pll_disable(struct intel_display *display,
 	icl_pll_disable(display, pll, enable_reg);
 }
 
-static void tbt_pll_disable(struct intel_display *display,
-			    struct intel_dpll *pll)
+static void icl_tbt_pll_disable(struct intel_display *display,
+				struct intel_dpll *pll)
 {
 	icl_pll_disable(display, pll, TBT_PLL_ENABLE);
 }
@@ -4142,10 +4142,10 @@ static const struct intel_dpll_funcs combo_pll_funcs = {
 	.get_freq = icl_ddi_combo_pll_get_freq,
 };
 
-static const struct intel_dpll_funcs tbt_pll_funcs = {
-	.enable = tbt_pll_enable,
-	.disable = tbt_pll_disable,
-	.get_hw_state = tbt_pll_get_hw_state,
+static const struct intel_dpll_funcs icl_tbt_pll_funcs = {
+	.enable = icl_tbt_pll_enable,
+	.disable = icl_tbt_pll_disable,
+	.get_hw_state = icl_tbt_pll_get_hw_state,
 	.get_freq = icl_ddi_tbt_pll_get_freq,
 };
 
@@ -4159,7 +4159,7 @@ static const struct intel_dpll_funcs mg_pll_funcs = {
 static const struct dpll_info icl_plls[] = {
 	{ .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
 	{ .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
-	{ .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
+	{ .name = "TBT PLL", .funcs = &icl_tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
 	  .is_alt_port_dpll = true, },
 	{ .name = "MG PLL 1", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
 	{ .name = "MG PLL 2", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
@@ -4207,7 +4207,7 @@ static const struct intel_dpll_funcs dkl_pll_funcs = {
 static const struct dpll_info tgl_plls[] = {
 	{ .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
 	{ .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
-	{ .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
+	{ .name = "TBT PLL", .funcs = &icl_tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
 	  .is_alt_port_dpll = true, },
 	{ .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
 	{ .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
@@ -4285,7 +4285,7 @@ static const struct intel_dpll_mgr adls_pll_mgr = {
 static const struct dpll_info adlp_plls[] = {
 	{ .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
 	{ .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
-	{ .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
+	{ .name = "TBT PLL", .funcs = &icl_tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
 	  .is_alt_port_dpll = true, },
 	{ .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
 	{ .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
-- 
2.34.1


  reply	other threads:[~2025-11-17 10:59 UTC|newest]

Thread overview: 69+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-17 10:45 [PATCH v2 00/32] drm/i915/cx0: Add MTL+ platforms to support dpll framework Mika Kahola
2025-11-17 10:45 ` Mika Kahola [this message]
2025-11-17 10:45 ` [PATCH v2 02/32] drm/i915/cx0: Factor out C10 msgbus access start/end helpers Mika Kahola
2025-11-17 10:45 ` [PATCH v2 03/32] drm/i915/cx0: Sanitize setting the Cx0 PLL use_c10 flag Mika Kahola
2025-11-17 10:45 ` [PATCH v2 04/32] drm/i915/cx0: Sanitize calculating C20 PLL state from tables Mika Kahola
2025-11-17 10:45 ` [PATCH v2 05/32] drm/i915/cx0: Track the C20 PHY VDR state in the PLL state Mika Kahola
2025-11-18  3:43   ` Kandpal, Suraj
2025-11-17 10:45 ` [PATCH v2 06/32] drm/i915/cx0: Move definition of Cx0 PHY functions earlier Mika Kahola
2025-11-17 10:45 ` [PATCH v2 07/32] drm/i915/cx0: Add macro to get DDI port width from a register value Mika Kahola
2025-11-17 10:45 ` [PATCH v2 08/32] drm/i915/cx0: Track the Cx0 PHY enabled lane count in the PLL state Mika Kahola
2025-11-17 10:45 ` [PATCH v2 09/32] drm/i915/cx0: Sanitize C10 PHY PLL SSC register setup Mika Kahola
2025-11-17 10:45 ` [PATCH v2 10/32] drm/i915/cx0: Read out the Cx0 PHY SSC enabled state Mika Kahola
2025-11-17 10:45 ` [PATCH v2 11/32] drm/i915/cx0: Determine Cx0 PLL DP mode from PLL state Mika Kahola
2025-11-17 10:45 ` [PATCH v2 12/32] drm/i915/cx0: Determine Cx0 PLL port clock " Mika Kahola
2025-11-17 10:45 ` [PATCH v2 13/32] drm/i915/cx0: Zero Cx0 PLL state before compute and HW readout Mika Kahola
2025-11-17 10:45 ` [PATCH v2 14/32] drm/i915/cx0: Print additional Cx0 PLL HW state Mika Kahola
2025-11-18  3:49   ` Kandpal, Suraj
2025-11-17 10:45 ` [PATCH v2 15/32] drm/i915/cx0: Remove state verification Mika Kahola
2025-11-17 10:45 ` [PATCH v2 16/32] drm/i915/cx0: Add PLL information for MTL+ Mika Kahola
2025-11-18  3:56   ` Kandpal, Suraj
2025-11-17 10:45 ` [PATCH v2 17/32] drm/i915/cx0: Update C10/C20 state calculation Mika Kahola
2025-11-18  4:00   ` Kandpal, Suraj
2025-11-17 10:45 ` [PATCH v2 18/32] drm/i915/cx0: Compute plls for MTL+ platform Mika Kahola
2025-11-18  4:03   ` Kandpal, Suraj
2025-11-18  9:14     ` Kahola, Mika
2025-11-17 10:45 ` [PATCH v2 19/32] drm/i915/cx0: Add MTL+ .get_dplls hook Mika Kahola
2025-11-18  4:04   ` Kandpal, Suraj
2025-11-17 10:45 ` [PATCH v2 20/32] drm/i915/cx0: Add MTL+ .put_dplls hook Mika Kahola
2025-11-17 10:45 ` [PATCH v2 21/32] drm/i915/cx0: Add MTL+ .update_active_dpll hook Mika Kahola
2025-11-18  4:21   ` Kandpal, Suraj
2025-11-18  9:46     ` Kahola, Mika
2025-11-18 11:28     ` Kahola, Mika
2025-11-18 13:28   ` [PATCH v3 " Mika Kahola
2025-11-19  5:29     ` Kandpal, Suraj
2025-11-17 10:45 ` [PATCH v2 22/32] drm/i915/cx0: Add MTL+ .update_dpll_ref_clks hook Mika Kahola
2025-11-17 10:45 ` [PATCH v2 23/32] drm/i915/cx0: Add MTL+ .dump_hw_state hook Mika Kahola
2025-11-17 10:45 ` [PATCH v2 24/32] drm/i915/cx0: Add .compare_hw_state hook Mika Kahola
2025-11-17 10:45 ` [PATCH v2 25/32] drm/i915/cx0: Add MTL+ .get_hw_state hook Mika Kahola
2026-04-20 23:19   ` Gustavo Sousa
2026-04-21  7:27     ` Kahola, Mika
2025-11-17 10:45 ` [PATCH v2 26/32] drm/i915/cx0: Add MTL+ .get_freq hook Mika Kahola
2025-11-17 10:45 ` [PATCH v2 27/32] drm/i915/cx0: Add MTL+ .crtc_get_dpll hook Mika Kahola
2025-11-17 10:45 ` [PATCH v2 28/32] drm/i915/cx0: PLL verify debug state print Mika Kahola
2025-11-17 10:45 ` [PATCH v2 29/32] drm/i915/cx0: Add MTL+ .enable_clock/.disable clock hooks on DDI Mika Kahola
2025-11-17 10:46 ` [PATCH v2 30/32] drm/i915/cx0: Get encoder configuration for C10 and C20 PHY PLLs Mika Kahola
2025-11-18  4:33   ` Kandpal, Suraj
2025-11-18 12:02     ` Kahola, Mika
2025-11-19  5:25       ` Kandpal, Suraj
2025-11-17 10:46 ` [PATCH v2 31/32] drm/i915/cx0: Add MTL+ Thunderbolt PLL hooks Mika Kahola
2025-11-18  4:38   ` Kandpal, Suraj
2025-11-18 10:50     ` Imre Deak
2025-11-19  6:03       ` Kandpal, Suraj
2025-11-17 10:46 ` [PATCH v2 32/32] drm/i915/cx0: Enable dpll framework for MTL+ Mika Kahola
2025-11-18  4:14   ` Kandpal, Suraj
2025-11-18  9:20     ` Kahola, Mika
2025-11-18 13:28   ` [PATCH v3 " Mika Kahola
2025-11-19  5:26     ` Kandpal, Suraj
2025-11-17 11:06 ` ✗ CI.checkpatch: warning for drm/i915/cx0: Add MTL+ platforms to support dpll framework Patchwork
2025-11-17 11:07 ` ✓ CI.KUnit: success " Patchwork
2025-11-17 11:22 ` ✗ CI.checksparse: warning " Patchwork
2025-11-17 12:09 ` ✓ Xe.CI.BAT: success " Patchwork
2025-11-17 13:29 ` ✗ Xe.CI.Full: failure " Patchwork
2025-11-18 17:17 ` ✗ CI.checkpatch: warning for drm/i915/cx0: Add MTL+ platforms to support dpll framework (rev3) Patchwork
2025-11-18 17:18 ` ✓ CI.KUnit: success " Patchwork
2025-11-18 17:33 ` ✗ CI.checksparse: warning " Patchwork
2025-11-18 17:58 ` ✓ Xe.CI.BAT: success " Patchwork
2025-11-19 11:59 ` [PATCH v2 00/32] drm/i915/cx0: Add MTL+ platforms to support dpll framework Kahola, Mika
2025-11-19 18:12   ` Matt Roper
2025-11-20 12:41     ` Kahola, Mika

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