* ✗ CI.checkpatch: warning for Plane Color Pipeline support for Intel platforms (rev7)
2025-12-03 8:51 [v8 00/15] Plane Color Pipeline support for Intel platforms Uma Shankar
@ 2025-12-03 8:47 ` Patchwork
2025-12-03 8:48 ` ✓ CI.KUnit: success " Patchwork
` (16 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: Patchwork @ 2025-12-03 8:47 UTC (permalink / raw)
To: Uma Shankar; +Cc: intel-xe
== Series Details ==
Series: Plane Color Pipeline support for Intel platforms (rev7)
URL : https://patchwork.freedesktop.org/series/141788/
State : warning
== Summary ==
+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
2de9a3901bc28757c7906b454717b64e2a214021
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 4517659f8a22a104a59fea48b387ccbb7728f747
Author: Uma Shankar <uma.shankar@intel.com>
Date: Wed Dec 3 14:22:11 2025 +0530
drm/i915/color: Enable Plane Color Pipelines
Expose color pipeline and add ability to program it.
v2: Set bit to enable multisegmented lut
v3: s/drm_color_lut_32/drm_color_lut32 (Simon)
v4: - Fix dsb programming
- Remove multi-segment LUT, they will be added in later patches
- Add pipeline only to TGL+
- Code Refactor
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
+ /mt/dim checkpatch 6a00c52137a5a8eb36cb762d4649abe16cc0ca33 drm-intel
02a328eb8dea drm/i915/display: Add identifiers for driver specific blocks
a03bffefe7ef drm/i915: Add intel_color_op
-:31: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 48 lines checked
07493f2083e2 drm/i915/color: Add helper to create intel colorop
24bbf2706833 drm/i915/color: Create a transfer function color pipeline
-:45: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#45:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 107 lines checked
f7c16851a9e8 drm/i915/color: Add framework to program CSC
ad401335ee52 drm/i915/color: Preserve sign bit when int_bits is Zero
72445df0785e drm/i915/color: Add plane CTM callback for D12 and beyond
6e419b73912c drm/i915: Add register definitions for Plane Degamma
-:41: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#41: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:300:
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_A, \
-:43: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#43: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:302:
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_2(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_A, \
-:45: WARNING:LONG_LINE: line length of 123 exceeds 100 columns
#45: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:304:
+#define PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_INDEX_ENH_1(pipe), \
-:45: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#45: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:304:
+#define PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_INDEX_ENH_1(pipe), \
+ _PLANE_PRE_CSC_GAMC_INDEX_ENH_2(pipe))
-:46: WARNING:LONG_LINE: line length of 111 exceeds 100 columns
#46: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:305:
+ _PLANE_PRE_CSC_GAMC_INDEX_ENH_2(pipe))
-:53: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#53: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:312:
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_1(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_DATA_ENH_1_A, \
-:55: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#55: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:314:
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_2(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_DATA_ENH_2_A, \
-:57: WARNING:LONG_LINE: line length of 122 exceeds 100 columns
#57: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:316:
+#define PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_DATA_ENH_1(pipe), \
-:57: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#57: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:316:
+#define PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_DATA_ENH_1(pipe), \
+ _PLANE_PRE_CSC_GAMC_DATA_ENH_2(pipe))
-:58: WARNING:LONG_LINE: line length of 110 exceeds 100 columns
#58: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:317:
+ _PLANE_PRE_CSC_GAMC_DATA_ENH_2(pipe))
-:68: WARNING:LONG_LINE: line length of 119 exceeds 100 columns
#68: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:327:
+#define PLANE_PRE_CSC_GAMC_INDEX(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_INDEX_1(pipe), \
-:68: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#68: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:327:
+#define PLANE_PRE_CSC_GAMC_INDEX(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_INDEX_1(pipe), \
+ _PLANE_PRE_CSC_GAMC_INDEX_2(pipe))
-:69: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#69: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:328:
+ _PLANE_PRE_CSC_GAMC_INDEX_2(pipe))
-:79: WARNING:LONG_LINE: line length of 118 exceeds 100 columns
#79: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:338:
+#define PLANE_PRE_CSC_GAMC_DATA(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_DATA_1(pipe), \
-:79: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#79: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:338:
+#define PLANE_PRE_CSC_GAMC_DATA(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_DATA_1(pipe), \
+ _PLANE_PRE_CSC_GAMC_DATA_2(pipe))
-:80: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#80: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:339:
+ _PLANE_PRE_CSC_GAMC_DATA_2(pipe))
total: 0 errors, 12 warnings, 4 checks, 60 lines checked
f2ea0dd78975 drm/i915: Add register definitions for Plane Post CSC
-:39: WARNING:LONG_LINE: line length of 118 exceeds 100 columns
#39: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:301:
+#define _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1_A, \
-:40: WARNING:LONG_LINE: line length of 110 exceeds 100 columns
#40: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:302:
+ _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1_B)
-:41: WARNING:LONG_LINE: line length of 118 exceeds 100 columns
#41: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:303:
+#define _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2_A, \
-:42: WARNING:LONG_LINE: line length of 110 exceeds 100 columns
#42: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:304:
+ _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2_B)
-:43: WARNING:LONG_LINE: line length of 137 exceeds 100 columns
#43: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:305:
+#define PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1(pipe), \
-:43: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#43: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:305:
+#define PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1(pipe), \
+ _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2(pipe))
-:44: WARNING:LONG_LINE: line length of 125 exceeds 100 columns
#44: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:306:
+ _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2(pipe))
-:50: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#50: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:312:
+#define _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1_A, \
-:51: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#51: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:313:
+ _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1_B)
-:52: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#52: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:314:
+#define _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2_A, \
-:53: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#53: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:315:
+ _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2_B)
-:54: WARNING:LONG_LINE: line length of 136 exceeds 100 columns
#54: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:316:
+#define PLANE_POST_CSC_GAMC_SEG0_DATA_ENH(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1(pipe), \
-:54: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#54: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:316:
+#define PLANE_POST_CSC_GAMC_SEG0_DATA_ENH(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1(pipe), \
+ _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2(pipe))
-:55: WARNING:LONG_LINE: line length of 124 exceeds 100 columns
#55: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:317:
+ _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2(pipe))
-:61: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#61: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:323:
+#define _PLANE_POST_CSC_GAMC_INDEX_ENH_1(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_INDEX_ENH_1_A, \
-:63: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#63: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:325:
+#define _PLANE_POST_CSC_GAMC_INDEX_ENH_2(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_INDEX_ENH_2_A, \
-:65: WARNING:LONG_LINE: line length of 124 exceeds 100 columns
#65: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:327:
+#define PLANE_POST_CSC_GAMC_INDEX_ENH(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_INDEX_ENH_1(pipe), \
-:65: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#65: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:327:
+#define PLANE_POST_CSC_GAMC_INDEX_ENH(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_INDEX_ENH_1(pipe), \
+ _PLANE_POST_CSC_GAMC_INDEX_ENH_2(pipe))
-:66: WARNING:LONG_LINE: line length of 112 exceeds 100 columns
#66: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:328:
+ _PLANE_POST_CSC_GAMC_INDEX_ENH_2(pipe))
-:72: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#72: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:334:
+#define _PLANE_POST_CSC_GAMC_DATA_ENH_1(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_DATA_ENH_1_A, \
-:74: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#74: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:336:
+#define _PLANE_POST_CSC_GAMC_DATA_ENH_2(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_DATA_ENH_2_A, \
-:76: WARNING:LONG_LINE: line length of 123 exceeds 100 columns
#76: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:338:
+#define PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_DATA_ENH_1(pipe), \
-:76: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#76: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:338:
+#define PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_DATA_ENH_1(pipe), \
+ _PLANE_POST_CSC_GAMC_DATA_ENH_2(pipe))
-:77: WARNING:LONG_LINE: line length of 111 exceeds 100 columns
#77: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:339:
+ _PLANE_POST_CSC_GAMC_DATA_ENH_2(pipe))
-:83: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#83: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:345:
+#define _PLANE_POST_CSC_GAMC_INDEX_1(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_INDEX_1_A, \
-:85: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#85: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:347:
+#define _PLANE_POST_CSC_GAMC_INDEX_2(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_INDEX_2_A, \
-:87: WARNING:LONG_LINE: line length of 120 exceeds 100 columns
#87: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:349:
+#define PLANE_POST_CSC_GAMC_INDEX(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_INDEX_1(pipe), \
-:87: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#87: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:349:
+#define PLANE_POST_CSC_GAMC_INDEX(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_INDEX_1(pipe), \
+ _PLANE_POST_CSC_GAMC_INDEX_2(pipe))
-:88: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#88: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:350:
+ _PLANE_POST_CSC_GAMC_INDEX_2(pipe))
-:98: WARNING:LONG_LINE: line length of 119 exceeds 100 columns
#98: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:360:
+#define PLANE_POST_CSC_GAMC_DATA(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_DATA_1(pipe), \
-:98: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#98: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:360:
+#define PLANE_POST_CSC_GAMC_DATA(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_DATA_1(pipe), \
+ _PLANE_POST_CSC_GAMC_DATA_2(pipe))
-:99: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#99: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:361:
+ _PLANE_POST_CSC_GAMC_DATA_2(pipe))
total: 0 errors, 26 warnings, 6 checks, 79 lines checked
13222154fb85 drm/i915/color: Add framework to program PRE/POST CSC LUT
79127e0c2f32 drm/i915/color: Program Pre-CSC registers
65fb856bff86 drm/i915/color: Program Plane Post CSC Registers
93a5f3c5bf47 drm/i915/color: Add registers for 3D LUT
4472fd22b525 drm/i915/color: Add 3D LUT to color pipeline
4517659f8a22 drm/i915/color: Enable Plane Color Pipelines
^ permalink raw reply [flat|nested] 29+ messages in thread
* ✓ CI.KUnit: success for Plane Color Pipeline support for Intel platforms (rev7)
2025-12-03 8:51 [v8 00/15] Plane Color Pipeline support for Intel platforms Uma Shankar
2025-12-03 8:47 ` ✗ CI.checkpatch: warning for Plane Color Pipeline support for Intel platforms (rev7) Patchwork
@ 2025-12-03 8:48 ` Patchwork
2025-12-03 8:51 ` [v8 01/15] drm/i915/display: Add identifiers for driver specific blocks Uma Shankar
` (15 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: Patchwork @ 2025-12-03 8:48 UTC (permalink / raw)
To: Uma Shankar; +Cc: intel-xe
== Series Details ==
Series: Plane Color Pipeline support for Intel platforms (rev7)
URL : https://patchwork.freedesktop.org/series/141788/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[08:47:14] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[08:47:18] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[08:47:48] Starting KUnit Kernel (1/1)...
[08:47:48] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[08:47:49] ================== guc_buf (11 subtests) ===================
[08:47:49] [PASSED] test_smallest
[08:47:49] [PASSED] test_largest
[08:47:49] [PASSED] test_granular
[08:47:49] [PASSED] test_unique
[08:47:49] [PASSED] test_overlap
[08:47:49] [PASSED] test_reusable
[08:47:49] [PASSED] test_too_big
[08:47:49] [PASSED] test_flush
[08:47:49] [PASSED] test_lookup
[08:47:49] [PASSED] test_data
[08:47:49] [PASSED] test_class
[08:47:49] ===================== [PASSED] guc_buf =====================
[08:47:49] =================== guc_dbm (7 subtests) ===================
[08:47:49] [PASSED] test_empty
[08:47:49] [PASSED] test_default
[08:47:49] ======================== test_size ========================
[08:47:49] [PASSED] 4
[08:47:49] [PASSED] 8
[08:47:49] [PASSED] 32
[08:47:49] [PASSED] 256
[08:47:49] ==================== [PASSED] test_size ====================
[08:47:49] ======================= test_reuse ========================
[08:47:49] [PASSED] 4
[08:47:49] [PASSED] 8
[08:47:49] [PASSED] 32
[08:47:49] [PASSED] 256
[08:47:49] =================== [PASSED] test_reuse ====================
[08:47:49] =================== test_range_overlap ====================
[08:47:49] [PASSED] 4
[08:47:49] [PASSED] 8
[08:47:49] [PASSED] 32
[08:47:49] [PASSED] 256
[08:47:49] =============== [PASSED] test_range_overlap ================
[08:47:49] =================== test_range_compact ====================
[08:47:49] [PASSED] 4
[08:47:49] [PASSED] 8
[08:47:49] [PASSED] 32
[08:47:49] [PASSED] 256
[08:47:49] =============== [PASSED] test_range_compact ================
[08:47:49] ==================== test_range_spare =====================
[08:47:49] [PASSED] 4
[08:47:49] [PASSED] 8
[08:47:49] [PASSED] 32
[08:47:49] [PASSED] 256
[08:47:49] ================ [PASSED] test_range_spare =================
[08:47:49] ===================== [PASSED] guc_dbm =====================
[08:47:49] =================== guc_idm (6 subtests) ===================
[08:47:49] [PASSED] bad_init
[08:47:49] [PASSED] no_init
[08:47:49] [PASSED] init_fini
[08:47:49] [PASSED] check_used
[08:47:49] [PASSED] check_quota
[08:47:49] [PASSED] check_all
[08:47:49] ===================== [PASSED] guc_idm =====================
[08:47:49] ================== no_relay (3 subtests) ===================
[08:47:49] [PASSED] xe_drops_guc2pf_if_not_ready
[08:47:49] [PASSED] xe_drops_guc2vf_if_not_ready
[08:47:49] [PASSED] xe_rejects_send_if_not_ready
[08:47:49] ==================== [PASSED] no_relay =====================
[08:47:49] ================== pf_relay (14 subtests) ==================
[08:47:49] [PASSED] pf_rejects_guc2pf_too_short
[08:47:49] [PASSED] pf_rejects_guc2pf_too_long
[08:47:49] [PASSED] pf_rejects_guc2pf_no_payload
[08:47:49] [PASSED] pf_fails_no_payload
[08:47:49] [PASSED] pf_fails_bad_origin
[08:47:49] [PASSED] pf_fails_bad_type
[08:47:49] [PASSED] pf_txn_reports_error
[08:47:49] [PASSED] pf_txn_sends_pf2guc
[08:47:49] [PASSED] pf_sends_pf2guc
[08:47:49] [SKIPPED] pf_loopback_nop
[08:47:49] [SKIPPED] pf_loopback_echo
[08:47:49] [SKIPPED] pf_loopback_fail
[08:47:49] [SKIPPED] pf_loopback_busy
[08:47:49] [SKIPPED] pf_loopback_retry
[08:47:49] ==================== [PASSED] pf_relay =====================
[08:47:49] ================== vf_relay (3 subtests) ===================
[08:47:49] [PASSED] vf_rejects_guc2vf_too_short
[08:47:49] [PASSED] vf_rejects_guc2vf_too_long
[08:47:49] [PASSED] vf_rejects_guc2vf_no_payload
[08:47:49] ==================== [PASSED] vf_relay =====================
[08:47:49] ================ pf_gt_config (6 subtests) =================
[08:47:49] [PASSED] fair_contexts_1vf
[08:47:49] [PASSED] fair_doorbells_1vf
[08:47:49] [PASSED] fair_ggtt_1vf
[08:47:49] ====================== fair_contexts ======================
[08:47:49] [PASSED] 1 VF
[08:47:49] [PASSED] 2 VFs
[08:47:49] [PASSED] 3 VFs
[08:47:49] [PASSED] 4 VFs
[08:47:49] [PASSED] 5 VFs
[08:47:49] [PASSED] 6 VFs
[08:47:49] [PASSED] 7 VFs
[08:47:49] [PASSED] 8 VFs
[08:47:49] [PASSED] 9 VFs
[08:47:49] [PASSED] 10 VFs
[08:47:49] [PASSED] 11 VFs
[08:47:49] [PASSED] 12 VFs
[08:47:49] [PASSED] 13 VFs
[08:47:49] [PASSED] 14 VFs
[08:47:49] [PASSED] 15 VFs
[08:47:49] [PASSED] 16 VFs
[08:47:49] [PASSED] 17 VFs
[08:47:49] [PASSED] 18 VFs
[08:47:49] [PASSED] 19 VFs
[08:47:49] [PASSED] 20 VFs
[08:47:49] [PASSED] 21 VFs
[08:47:49] [PASSED] 22 VFs
[08:47:49] [PASSED] 23 VFs
[08:47:49] [PASSED] 24 VFs
[08:47:49] [PASSED] 25 VFs
[08:47:49] [PASSED] 26 VFs
[08:47:49] [PASSED] 27 VFs
[08:47:49] [PASSED] 28 VFs
[08:47:49] [PASSED] 29 VFs
[08:47:49] [PASSED] 30 VFs
[08:47:49] [PASSED] 31 VFs
[08:47:49] [PASSED] 32 VFs
[08:47:49] [PASSED] 33 VFs
[08:47:49] [PASSED] 34 VFs
[08:47:49] [PASSED] 35 VFs
[08:47:49] [PASSED] 36 VFs
[08:47:49] [PASSED] 37 VFs
[08:47:49] [PASSED] 38 VFs
[08:47:49] [PASSED] 39 VFs
[08:47:49] [PASSED] 40 VFs
[08:47:49] [PASSED] 41 VFs
[08:47:49] [PASSED] 42 VFs
[08:47:49] [PASSED] 43 VFs
[08:47:49] [PASSED] 44 VFs
[08:47:49] [PASSED] 45 VFs
[08:47:49] [PASSED] 46 VFs
[08:47:49] [PASSED] 47 VFs
[08:47:49] [PASSED] 48 VFs
[08:47:49] [PASSED] 49 VFs
[08:47:49] [PASSED] 50 VFs
[08:47:49] [PASSED] 51 VFs
[08:47:49] [PASSED] 52 VFs
[08:47:49] [PASSED] 53 VFs
[08:47:49] [PASSED] 54 VFs
[08:47:49] [PASSED] 55 VFs
[08:47:49] [PASSED] 56 VFs
[08:47:49] [PASSED] 57 VFs
[08:47:49] [PASSED] 58 VFs
[08:47:49] [PASSED] 59 VFs
[08:47:49] [PASSED] 60 VFs
[08:47:49] [PASSED] 61 VFs
[08:47:49] [PASSED] 62 VFs
[08:47:49] [PASSED] 63 VFs
[08:47:49] ================== [PASSED] fair_contexts ==================
[08:47:49] ===================== fair_doorbells ======================
[08:47:49] [PASSED] 1 VF
[08:47:49] [PASSED] 2 VFs
[08:47:49] [PASSED] 3 VFs
[08:47:49] [PASSED] 4 VFs
[08:47:49] [PASSED] 5 VFs
[08:47:49] [PASSED] 6 VFs
[08:47:49] [PASSED] 7 VFs
[08:47:49] [PASSED] 8 VFs
[08:47:49] [PASSED] 9 VFs
[08:47:49] [PASSED] 10 VFs
[08:47:49] [PASSED] 11 VFs
[08:47:49] [PASSED] 12 VFs
[08:47:49] [PASSED] 13 VFs
[08:47:49] [PASSED] 14 VFs
[08:47:49] [PASSED] 15 VFs
[08:47:49] [PASSED] 16 VFs
[08:47:49] [PASSED] 17 VFs
[08:47:49] [PASSED] 18 VFs
[08:47:49] [PASSED] 19 VFs
[08:47:49] [PASSED] 20 VFs
[08:47:49] [PASSED] 21 VFs
[08:47:49] [PASSED] 22 VFs
[08:47:49] [PASSED] 23 VFs
[08:47:49] [PASSED] 24 VFs
[08:47:49] [PASSED] 25 VFs
[08:47:49] [PASSED] 26 VFs
[08:47:49] [PASSED] 27 VFs
[08:47:49] [PASSED] 28 VFs
[08:47:49] [PASSED] 29 VFs
[08:47:49] [PASSED] 30 VFs
[08:47:49] [PASSED] 31 VFs
[08:47:49] [PASSED] 32 VFs
[08:47:49] [PASSED] 33 VFs
[08:47:49] [PASSED] 34 VFs
[08:47:49] [PASSED] 35 VFs
[08:47:49] [PASSED] 36 VFs
[08:47:49] [PASSED] 37 VFs
[08:47:49] [PASSED] 38 VFs
[08:47:49] [PASSED] 39 VFs
[08:47:49] [PASSED] 40 VFs
[08:47:49] [PASSED] 41 VFs
[08:47:49] [PASSED] 42 VFs
[08:47:49] [PASSED] 43 VFs
[08:47:49] [PASSED] 44 VFs
[08:47:49] [PASSED] 45 VFs
[08:47:49] [PASSED] 46 VFs
[08:47:49] [PASSED] 47 VFs
[08:47:49] [PASSED] 48 VFs
[08:47:49] [PASSED] 49 VFs
[08:47:49] [PASSED] 50 VFs
[08:47:49] [PASSED] 51 VFs
[08:47:49] [PASSED] 52 VFs
[08:47:49] [PASSED] 53 VFs
[08:47:49] [PASSED] 54 VFs
[08:47:49] [PASSED] 55 VFs
[08:47:49] [PASSED] 56 VFs
[08:47:49] [PASSED] 57 VFs
[08:47:49] [PASSED] 58 VFs
[08:47:49] [PASSED] 59 VFs
[08:47:49] [PASSED] 60 VFs
[08:47:49] [PASSED] 61 VFs
[08:47:49] [PASSED] 62 VFs
[08:47:49] [PASSED] 63 VFs
[08:47:49] ================= [PASSED] fair_doorbells ==================
[08:47:49] ======================== fair_ggtt ========================
[08:47:49] [PASSED] 1 VF
[08:47:49] [PASSED] 2 VFs
[08:47:49] [PASSED] 3 VFs
[08:47:49] [PASSED] 4 VFs
[08:47:49] [PASSED] 5 VFs
[08:47:49] [PASSED] 6 VFs
[08:47:49] [PASSED] 7 VFs
[08:47:49] [PASSED] 8 VFs
[08:47:49] [PASSED] 9 VFs
[08:47:49] [PASSED] 10 VFs
[08:47:49] [PASSED] 11 VFs
[08:47:49] [PASSED] 12 VFs
[08:47:49] [PASSED] 13 VFs
[08:47:49] [PASSED] 14 VFs
[08:47:49] [PASSED] 15 VFs
[08:47:49] [PASSED] 16 VFs
[08:47:49] [PASSED] 17 VFs
[08:47:49] [PASSED] 18 VFs
[08:47:49] [PASSED] 19 VFs
[08:47:49] [PASSED] 20 VFs
[08:47:49] [PASSED] 21 VFs
[08:47:49] [PASSED] 22 VFs
[08:47:49] [PASSED] 23 VFs
[08:47:49] [PASSED] 24 VFs
[08:47:49] [PASSED] 25 VFs
[08:47:49] [PASSED] 26 VFs
[08:47:49] [PASSED] 27 VFs
[08:47:49] [PASSED] 28 VFs
[08:47:49] [PASSED] 29 VFs
[08:47:49] [PASSED] 30 VFs
[08:47:49] [PASSED] 31 VFs
[08:47:49] [PASSED] 32 VFs
[08:47:49] [PASSED] 33 VFs
[08:47:49] [PASSED] 34 VFs
[08:47:49] [PASSED] 35 VFs
[08:47:49] [PASSED] 36 VFs
[08:47:49] [PASSED] 37 VFs
[08:47:49] [PASSED] 38 VFs
[08:47:49] [PASSED] 39 VFs
[08:47:49] [PASSED] 40 VFs
[08:47:49] [PASSED] 41 VFs
[08:47:49] [PASSED] 42 VFs
[08:47:49] [PASSED] 43 VFs
[08:47:49] [PASSED] 44 VFs
[08:47:49] [PASSED] 45 VFs
[08:47:49] [PASSED] 46 VFs
[08:47:49] [PASSED] 47 VFs
[08:47:49] [PASSED] 48 VFs
[08:47:49] [PASSED] 49 VFs
[08:47:49] [PASSED] 50 VFs
[08:47:49] [PASSED] 51 VFs
[08:47:49] [PASSED] 52 VFs
[08:47:49] [PASSED] 53 VFs
[08:47:49] [PASSED] 54 VFs
[08:47:49] [PASSED] 55 VFs
[08:47:49] [PASSED] 56 VFs
[08:47:49] [PASSED] 57 VFs
[08:47:49] [PASSED] 58 VFs
[08:47:49] [PASSED] 59 VFs
[08:47:49] [PASSED] 60 VFs
[08:47:49] [PASSED] 61 VFs
[08:47:49] [PASSED] 62 VFs
[08:47:49] [PASSED] 63 VFs
[08:47:49] ==================== [PASSED] fair_ggtt ====================
[08:47:49] ================== [PASSED] pf_gt_config ===================
[08:47:49] ===================== lmtt (1 subtest) =====================
[08:47:49] ======================== test_ops =========================
[08:47:49] [PASSED] 2-level
[08:47:49] [PASSED] multi-level
[08:47:49] ==================== [PASSED] test_ops =====================
[08:47:49] ====================== [PASSED] lmtt =======================
[08:47:49] ================= pf_service (11 subtests) =================
[08:47:49] [PASSED] pf_negotiate_any
[08:47:49] [PASSED] pf_negotiate_base_match
[08:47:49] [PASSED] pf_negotiate_base_newer
[08:47:49] [PASSED] pf_negotiate_base_next
[08:47:49] [SKIPPED] pf_negotiate_base_older
[08:47:49] [PASSED] pf_negotiate_base_prev
[08:47:49] [PASSED] pf_negotiate_latest_match
[08:47:49] [PASSED] pf_negotiate_latest_newer
[08:47:49] [PASSED] pf_negotiate_latest_next
[08:47:49] [SKIPPED] pf_negotiate_latest_older
[08:47:49] [SKIPPED] pf_negotiate_latest_prev
[08:47:49] =================== [PASSED] pf_service ====================
[08:47:49] ================= xe_guc_g2g (2 subtests) ==================
[08:47:49] ============== xe_live_guc_g2g_kunit_default ==============
[08:47:49] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[08:47:49] ============== xe_live_guc_g2g_kunit_allmem ===============
[08:47:49] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[08:47:49] =================== [SKIPPED] xe_guc_g2g ===================
[08:47:49] =================== xe_mocs (2 subtests) ===================
[08:47:49] ================ xe_live_mocs_kernel_kunit ================
[08:47:49] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[08:47:49] ================ xe_live_mocs_reset_kunit =================
[08:47:49] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[08:47:49] ==================== [SKIPPED] xe_mocs =====================
[08:47:49] ================= xe_migrate (2 subtests) ==================
[08:47:49] ================= xe_migrate_sanity_kunit =================
[08:47:49] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[08:47:49] ================== xe_validate_ccs_kunit ==================
[08:47:49] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[08:47:49] =================== [SKIPPED] xe_migrate ===================
[08:47:49] ================== xe_dma_buf (1 subtest) ==================
[08:47:49] ==================== xe_dma_buf_kunit =====================
[08:47:49] ================ [SKIPPED] xe_dma_buf_kunit ================
[08:47:49] =================== [SKIPPED] xe_dma_buf ===================
[08:47:49] ================= xe_bo_shrink (1 subtest) =================
[08:47:49] =================== xe_bo_shrink_kunit ====================
[08:47:49] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[08:47:49] ================== [SKIPPED] xe_bo_shrink ==================
[08:47:49] ==================== xe_bo (2 subtests) ====================
[08:47:49] ================== xe_ccs_migrate_kunit ===================
[08:47:49] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[08:47:49] ==================== xe_bo_evict_kunit ====================
[08:47:49] =============== [SKIPPED] xe_bo_evict_kunit ================
[08:47:49] ===================== [SKIPPED] xe_bo ======================
[08:47:49] ==================== args (11 subtests) ====================
[08:47:49] [PASSED] count_args_test
[08:47:49] [PASSED] call_args_example
[08:47:49] [PASSED] call_args_test
[08:47:49] [PASSED] drop_first_arg_example
[08:47:49] [PASSED] drop_first_arg_test
[08:47:49] [PASSED] first_arg_example
[08:47:49] [PASSED] first_arg_test
[08:47:49] [PASSED] last_arg_example
[08:47:49] [PASSED] last_arg_test
[08:47:49] [PASSED] pick_arg_example
[08:47:49] [PASSED] sep_comma_example
[08:47:49] ====================== [PASSED] args =======================
[08:47:49] =================== xe_pci (3 subtests) ====================
[08:47:49] ==================== check_graphics_ip ====================
[08:47:49] [PASSED] 12.00 Xe_LP
[08:47:49] [PASSED] 12.10 Xe_LP+
[08:47:49] [PASSED] 12.55 Xe_HPG
[08:47:49] [PASSED] 12.60 Xe_HPC
[08:47:49] [PASSED] 12.70 Xe_LPG
[08:47:49] [PASSED] 12.71 Xe_LPG
[08:47:49] [PASSED] 12.74 Xe_LPG+
[08:47:49] [PASSED] 20.01 Xe2_HPG
[08:47:49] [PASSED] 20.02 Xe2_HPG
[08:47:49] [PASSED] 20.04 Xe2_LPG
[08:47:49] [PASSED] 30.00 Xe3_LPG
[08:47:49] [PASSED] 30.01 Xe3_LPG
[08:47:49] [PASSED] 30.03 Xe3_LPG
[08:47:49] [PASSED] 30.04 Xe3_LPG
[08:47:49] [PASSED] 30.05 Xe3_LPG
[08:47:49] [PASSED] 35.11 Xe3p_XPC
[08:47:49] ================ [PASSED] check_graphics_ip ================
[08:47:49] ===================== check_media_ip ======================
[08:47:49] [PASSED] 12.00 Xe_M
[08:47:49] [PASSED] 12.55 Xe_HPM
[08:47:49] [PASSED] 13.00 Xe_LPM+
[08:47:49] [PASSED] 13.01 Xe2_HPM
[08:47:49] [PASSED] 20.00 Xe2_LPM
[08:47:49] [PASSED] 30.00 Xe3_LPM
[08:47:49] [PASSED] 30.02 Xe3_LPM
[08:47:49] [PASSED] 35.00 Xe3p_LPM
[08:47:49] [PASSED] 35.03 Xe3p_HPM
[08:47:49] ================= [PASSED] check_media_ip ==================
[08:47:49] =================== check_platform_desc ===================
[08:47:49] [PASSED] 0x9A60 (TIGERLAKE)
[08:47:49] [PASSED] 0x9A68 (TIGERLAKE)
[08:47:49] [PASSED] 0x9A70 (TIGERLAKE)
[08:47:49] [PASSED] 0x9A40 (TIGERLAKE)
[08:47:49] [PASSED] 0x9A49 (TIGERLAKE)
[08:47:49] [PASSED] 0x9A59 (TIGERLAKE)
[08:47:49] [PASSED] 0x9A78 (TIGERLAKE)
[08:47:49] [PASSED] 0x9AC0 (TIGERLAKE)
[08:47:49] [PASSED] 0x9AC9 (TIGERLAKE)
[08:47:49] [PASSED] 0x9AD9 (TIGERLAKE)
[08:47:49] [PASSED] 0x9AF8 (TIGERLAKE)
[08:47:49] [PASSED] 0x4C80 (ROCKETLAKE)
[08:47:49] [PASSED] 0x4C8A (ROCKETLAKE)
[08:47:49] [PASSED] 0x4C8B (ROCKETLAKE)
[08:47:49] [PASSED] 0x4C8C (ROCKETLAKE)
[08:47:49] [PASSED] 0x4C90 (ROCKETLAKE)
[08:47:49] [PASSED] 0x4C9A (ROCKETLAKE)
[08:47:49] [PASSED] 0x4680 (ALDERLAKE_S)
[08:47:49] [PASSED] 0x4682 (ALDERLAKE_S)
[08:47:49] [PASSED] 0x4688 (ALDERLAKE_S)
[08:47:49] [PASSED] 0x468A (ALDERLAKE_S)
[08:47:49] [PASSED] 0x468B (ALDERLAKE_S)
[08:47:49] [PASSED] 0x4690 (ALDERLAKE_S)
[08:47:49] [PASSED] 0x4692 (ALDERLAKE_S)
[08:47:49] [PASSED] 0x4693 (ALDERLAKE_S)
[08:47:49] [PASSED] 0x46A0 (ALDERLAKE_P)
[08:47:49] [PASSED] 0x46A1 (ALDERLAKE_P)
[08:47:49] [PASSED] 0x46A2 (ALDERLAKE_P)
[08:47:49] [PASSED] 0x46A3 (ALDERLAKE_P)
[08:47:49] [PASSED] 0x46A6 (ALDERLAKE_P)
[08:47:49] [PASSED] 0x46A8 (ALDERLAKE_P)
[08:47:49] [PASSED] 0x46AA (ALDERLAKE_P)
[08:47:49] [PASSED] 0x462A (ALDERLAKE_P)
[08:47:49] [PASSED] 0x4626 (ALDERLAKE_P)
[08:47:49] [PASSED] 0x4628 (ALDERLAKE_P)
[08:47:49] [PASSED] 0x46B0 (ALDERLAKE_P)
stty: 'standard input': Inappropriate ioctl for device
[08:47:49] [PASSED] 0x46B1 (ALDERLAKE_P)
[08:47:49] [PASSED] 0x46B2 (ALDERLAKE_P)
[08:47:49] [PASSED] 0x46B3 (ALDERLAKE_P)
[08:47:49] [PASSED] 0x46C0 (ALDERLAKE_P)
[08:47:49] [PASSED] 0x46C1 (ALDERLAKE_P)
[08:47:49] [PASSED] 0x46C2 (ALDERLAKE_P)
[08:47:49] [PASSED] 0x46C3 (ALDERLAKE_P)
[08:47:49] [PASSED] 0x46D0 (ALDERLAKE_N)
[08:47:49] [PASSED] 0x46D1 (ALDERLAKE_N)
[08:47:49] [PASSED] 0x46D2 (ALDERLAKE_N)
[08:47:49] [PASSED] 0x46D3 (ALDERLAKE_N)
[08:47:49] [PASSED] 0x46D4 (ALDERLAKE_N)
[08:47:49] [PASSED] 0xA721 (ALDERLAKE_P)
[08:47:49] [PASSED] 0xA7A1 (ALDERLAKE_P)
[08:47:49] [PASSED] 0xA7A9 (ALDERLAKE_P)
[08:47:49] [PASSED] 0xA7AC (ALDERLAKE_P)
[08:47:49] [PASSED] 0xA7AD (ALDERLAKE_P)
[08:47:49] [PASSED] 0xA720 (ALDERLAKE_P)
[08:47:49] [PASSED] 0xA7A0 (ALDERLAKE_P)
[08:47:49] [PASSED] 0xA7A8 (ALDERLAKE_P)
[08:47:49] [PASSED] 0xA7AA (ALDERLAKE_P)
[08:47:49] [PASSED] 0xA7AB (ALDERLAKE_P)
[08:47:49] [PASSED] 0xA780 (ALDERLAKE_S)
[08:47:49] [PASSED] 0xA781 (ALDERLAKE_S)
[08:47:49] [PASSED] 0xA782 (ALDERLAKE_S)
[08:47:49] [PASSED] 0xA783 (ALDERLAKE_S)
[08:47:49] [PASSED] 0xA788 (ALDERLAKE_S)
[08:47:49] [PASSED] 0xA789 (ALDERLAKE_S)
[08:47:49] [PASSED] 0xA78A (ALDERLAKE_S)
[08:47:49] [PASSED] 0xA78B (ALDERLAKE_S)
[08:47:49] [PASSED] 0x4905 (DG1)
[08:47:49] [PASSED] 0x4906 (DG1)
[08:47:49] [PASSED] 0x4907 (DG1)
[08:47:49] [PASSED] 0x4908 (DG1)
[08:47:49] [PASSED] 0x4909 (DG1)
[08:47:49] [PASSED] 0x56C0 (DG2)
[08:47:49] [PASSED] 0x56C2 (DG2)
[08:47:49] [PASSED] 0x56C1 (DG2)
[08:47:49] [PASSED] 0x7D51 (METEORLAKE)
[08:47:49] [PASSED] 0x7DD1 (METEORLAKE)
[08:47:49] [PASSED] 0x7D41 (METEORLAKE)
[08:47:49] [PASSED] 0x7D67 (METEORLAKE)
[08:47:49] [PASSED] 0xB640 (METEORLAKE)
[08:47:49] [PASSED] 0x56A0 (DG2)
[08:47:49] [PASSED] 0x56A1 (DG2)
[08:47:49] [PASSED] 0x56A2 (DG2)
[08:47:49] [PASSED] 0x56BE (DG2)
[08:47:49] [PASSED] 0x56BF (DG2)
[08:47:49] [PASSED] 0x5690 (DG2)
[08:47:49] [PASSED] 0x5691 (DG2)
[08:47:49] [PASSED] 0x5692 (DG2)
[08:47:49] [PASSED] 0x56A5 (DG2)
[08:47:49] [PASSED] 0x56A6 (DG2)
[08:47:49] [PASSED] 0x56B0 (DG2)
[08:47:49] [PASSED] 0x56B1 (DG2)
[08:47:49] [PASSED] 0x56BA (DG2)
[08:47:49] [PASSED] 0x56BB (DG2)
[08:47:49] [PASSED] 0x56BC (DG2)
[08:47:49] [PASSED] 0x56BD (DG2)
[08:47:49] [PASSED] 0x5693 (DG2)
[08:47:49] [PASSED] 0x5694 (DG2)
[08:47:49] [PASSED] 0x5695 (DG2)
[08:47:49] [PASSED] 0x56A3 (DG2)
[08:47:49] [PASSED] 0x56A4 (DG2)
[08:47:49] [PASSED] 0x56B2 (DG2)
[08:47:49] [PASSED] 0x56B3 (DG2)
[08:47:49] [PASSED] 0x5696 (DG2)
[08:47:49] [PASSED] 0x5697 (DG2)
[08:47:49] [PASSED] 0xB69 (PVC)
[08:47:49] [PASSED] 0xB6E (PVC)
[08:47:49] [PASSED] 0xBD4 (PVC)
[08:47:49] [PASSED] 0xBD5 (PVC)
[08:47:49] [PASSED] 0xBD6 (PVC)
[08:47:49] [PASSED] 0xBD7 (PVC)
[08:47:49] [PASSED] 0xBD8 (PVC)
[08:47:49] [PASSED] 0xBD9 (PVC)
[08:47:49] [PASSED] 0xBDA (PVC)
[08:47:49] [PASSED] 0xBDB (PVC)
[08:47:49] [PASSED] 0xBE0 (PVC)
[08:47:49] [PASSED] 0xBE1 (PVC)
[08:47:49] [PASSED] 0xBE5 (PVC)
[08:47:49] [PASSED] 0x7D40 (METEORLAKE)
[08:47:49] [PASSED] 0x7D45 (METEORLAKE)
[08:47:49] [PASSED] 0x7D55 (METEORLAKE)
[08:47:49] [PASSED] 0x7D60 (METEORLAKE)
[08:47:49] [PASSED] 0x7DD5 (METEORLAKE)
[08:47:49] [PASSED] 0x6420 (LUNARLAKE)
[08:47:49] [PASSED] 0x64A0 (LUNARLAKE)
[08:47:49] [PASSED] 0x64B0 (LUNARLAKE)
[08:47:49] [PASSED] 0xE202 (BATTLEMAGE)
[08:47:49] [PASSED] 0xE209 (BATTLEMAGE)
[08:47:49] [PASSED] 0xE20B (BATTLEMAGE)
[08:47:49] [PASSED] 0xE20C (BATTLEMAGE)
[08:47:49] [PASSED] 0xE20D (BATTLEMAGE)
[08:47:49] [PASSED] 0xE210 (BATTLEMAGE)
[08:47:49] [PASSED] 0xE211 (BATTLEMAGE)
[08:47:49] [PASSED] 0xE212 (BATTLEMAGE)
[08:47:49] [PASSED] 0xE216 (BATTLEMAGE)
[08:47:49] [PASSED] 0xE220 (BATTLEMAGE)
[08:47:49] [PASSED] 0xE221 (BATTLEMAGE)
[08:47:49] [PASSED] 0xE222 (BATTLEMAGE)
[08:47:49] [PASSED] 0xE223 (BATTLEMAGE)
[08:47:49] [PASSED] 0xB080 (PANTHERLAKE)
[08:47:49] [PASSED] 0xB081 (PANTHERLAKE)
[08:47:49] [PASSED] 0xB082 (PANTHERLAKE)
[08:47:49] [PASSED] 0xB083 (PANTHERLAKE)
[08:47:49] [PASSED] 0xB084 (PANTHERLAKE)
[08:47:49] [PASSED] 0xB085 (PANTHERLAKE)
[08:47:49] [PASSED] 0xB086 (PANTHERLAKE)
[08:47:49] [PASSED] 0xB087 (PANTHERLAKE)
[08:47:49] [PASSED] 0xB08F (PANTHERLAKE)
[08:47:49] [PASSED] 0xB090 (PANTHERLAKE)
[08:47:49] [PASSED] 0xB0A0 (PANTHERLAKE)
[08:47:49] [PASSED] 0xB0B0 (PANTHERLAKE)
[08:47:49] [PASSED] 0xD740 (NOVALAKE_S)
[08:47:49] [PASSED] 0xD741 (NOVALAKE_S)
[08:47:49] [PASSED] 0xD742 (NOVALAKE_S)
[08:47:49] [PASSED] 0xD743 (NOVALAKE_S)
[08:47:49] [PASSED] 0xD744 (NOVALAKE_S)
[08:47:49] [PASSED] 0xD745 (NOVALAKE_S)
[08:47:49] [PASSED] 0x674C (CRESCENTISLAND)
[08:47:49] [PASSED] 0xFD80 (PANTHERLAKE)
[08:47:49] [PASSED] 0xFD81 (PANTHERLAKE)
[08:47:49] =============== [PASSED] check_platform_desc ===============
[08:47:49] ===================== [PASSED] xe_pci ======================
[08:47:49] =================== xe_rtp (2 subtests) ====================
[08:47:49] =============== xe_rtp_process_to_sr_tests ================
[08:47:49] [PASSED] coalesce-same-reg
[08:47:49] [PASSED] no-match-no-add
[08:47:49] [PASSED] match-or
[08:47:49] [PASSED] match-or-xfail
[08:47:49] [PASSED] no-match-no-add-multiple-rules
[08:47:49] [PASSED] two-regs-two-entries
[08:47:49] [PASSED] clr-one-set-other
[08:47:49] [PASSED] set-field
[08:47:49] [PASSED] conflict-duplicate
[08:47:49] [PASSED] conflict-not-disjoint
[08:47:49] [PASSED] conflict-reg-type
[08:47:49] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[08:47:49] ================== xe_rtp_process_tests ===================
[08:47:49] [PASSED] active1
[08:47:49] [PASSED] active2
[08:47:49] [PASSED] active-inactive
[08:47:49] [PASSED] inactive-active
[08:47:49] [PASSED] inactive-1st_or_active-inactive
[08:47:49] [PASSED] inactive-2nd_or_active-inactive
[08:47:49] [PASSED] inactive-last_or_active-inactive
[08:47:49] [PASSED] inactive-no_or_active-inactive
[08:47:49] ============== [PASSED] xe_rtp_process_tests ===============
[08:47:49] ===================== [PASSED] xe_rtp ======================
[08:47:49] ==================== xe_wa (1 subtest) =====================
[08:47:49] ======================== xe_wa_gt =========================
[08:47:49] [PASSED] TIGERLAKE B0
[08:47:49] [PASSED] DG1 A0
[08:47:49] [PASSED] DG1 B0
[08:47:49] [PASSED] ALDERLAKE_S A0
[08:47:49] [PASSED] ALDERLAKE_S B0
[08:47:49] [PASSED] ALDERLAKE_S C0
[08:47:49] [PASSED] ALDERLAKE_S D0
[08:47:49] [PASSED] ALDERLAKE_P A0
[08:47:49] [PASSED] ALDERLAKE_P B0
[08:47:49] [PASSED] ALDERLAKE_P C0
[08:47:49] [PASSED] ALDERLAKE_S RPLS D0
[08:47:49] [PASSED] ALDERLAKE_P RPLU E0
[08:47:49] [PASSED] DG2 G10 C0
[08:47:49] [PASSED] DG2 G11 B1
[08:47:49] [PASSED] DG2 G12 A1
[08:47:49] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[08:47:49] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[08:47:49] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[08:47:49] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[08:47:49] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[08:47:49] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[08:47:49] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[08:47:49] ==================== [PASSED] xe_wa_gt =====================
[08:47:49] ====================== [PASSED] xe_wa ======================
[08:47:49] ============================================================
[08:47:49] Testing complete. Ran 510 tests: passed: 492, skipped: 18
[08:47:49] Elapsed time: 35.021s total, 4.141s configuring, 30.415s building, 0.457s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[08:47:49] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[08:47:51] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[08:48:15] Starting KUnit Kernel (1/1)...
[08:48:15] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[08:48:15] ============ drm_test_pick_cmdline (2 subtests) ============
[08:48:15] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[08:48:15] =============== drm_test_pick_cmdline_named ===============
[08:48:15] [PASSED] NTSC
[08:48:15] [PASSED] NTSC-J
[08:48:15] [PASSED] PAL
[08:48:15] [PASSED] PAL-M
[08:48:15] =========== [PASSED] drm_test_pick_cmdline_named ===========
[08:48:15] ============== [PASSED] drm_test_pick_cmdline ==============
[08:48:15] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[08:48:15] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[08:48:15] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[08:48:15] =========== drm_validate_clone_mode (2 subtests) ===========
[08:48:15] ============== drm_test_check_in_clone_mode ===============
[08:48:15] [PASSED] in_clone_mode
[08:48:15] [PASSED] not_in_clone_mode
[08:48:15] ========== [PASSED] drm_test_check_in_clone_mode ===========
[08:48:15] =============== drm_test_check_valid_clones ===============
[08:48:15] [PASSED] not_in_clone_mode
[08:48:15] [PASSED] valid_clone
[08:48:15] [PASSED] invalid_clone
[08:48:15] =========== [PASSED] drm_test_check_valid_clones ===========
[08:48:15] ============= [PASSED] drm_validate_clone_mode =============
[08:48:15] ============= drm_validate_modeset (1 subtest) =============
[08:48:15] [PASSED] drm_test_check_connector_changed_modeset
[08:48:15] ============== [PASSED] drm_validate_modeset ===============
[08:48:15] ====== drm_test_bridge_get_current_state (2 subtests) ======
[08:48:15] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[08:48:15] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[08:48:15] ======== [PASSED] drm_test_bridge_get_current_state ========
[08:48:15] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[08:48:15] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[08:48:15] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[08:48:15] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[08:48:15] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[08:48:15] ============== drm_bridge_alloc (2 subtests) ===============
[08:48:15] [PASSED] drm_test_drm_bridge_alloc_basic
[08:48:15] [PASSED] drm_test_drm_bridge_alloc_get_put
[08:48:15] ================ [PASSED] drm_bridge_alloc =================
[08:48:15] ================== drm_buddy (8 subtests) ==================
[08:48:15] [PASSED] drm_test_buddy_alloc_limit
[08:48:15] [PASSED] drm_test_buddy_alloc_optimistic
[08:48:15] [PASSED] drm_test_buddy_alloc_pessimistic
[08:48:15] [PASSED] drm_test_buddy_alloc_pathological
[08:48:15] [PASSED] drm_test_buddy_alloc_contiguous
[08:48:15] [PASSED] drm_test_buddy_alloc_clear
[08:48:16] [PASSED] drm_test_buddy_alloc_range_bias
[08:48:16] [PASSED] drm_test_buddy_fragmentation_performance
[08:48:16] ==================== [PASSED] drm_buddy ====================
[08:48:16] ============= drm_cmdline_parser (40 subtests) =============
[08:48:16] [PASSED] drm_test_cmdline_force_d_only
[08:48:16] [PASSED] drm_test_cmdline_force_D_only_dvi
[08:48:16] [PASSED] drm_test_cmdline_force_D_only_hdmi
[08:48:16] [PASSED] drm_test_cmdline_force_D_only_not_digital
[08:48:16] [PASSED] drm_test_cmdline_force_e_only
[08:48:16] [PASSED] drm_test_cmdline_res
[08:48:16] [PASSED] drm_test_cmdline_res_vesa
[08:48:16] [PASSED] drm_test_cmdline_res_vesa_rblank
[08:48:16] [PASSED] drm_test_cmdline_res_rblank
[08:48:16] [PASSED] drm_test_cmdline_res_bpp
[08:48:16] [PASSED] drm_test_cmdline_res_refresh
[08:48:16] [PASSED] drm_test_cmdline_res_bpp_refresh
[08:48:16] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[08:48:16] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[08:48:16] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[08:48:16] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[08:48:16] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[08:48:16] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[08:48:16] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[08:48:16] [PASSED] drm_test_cmdline_res_margins_force_on
[08:48:16] [PASSED] drm_test_cmdline_res_vesa_margins
[08:48:16] [PASSED] drm_test_cmdline_name
[08:48:16] [PASSED] drm_test_cmdline_name_bpp
[08:48:16] [PASSED] drm_test_cmdline_name_option
[08:48:16] [PASSED] drm_test_cmdline_name_bpp_option
[08:48:16] [PASSED] drm_test_cmdline_rotate_0
[08:48:16] [PASSED] drm_test_cmdline_rotate_90
[08:48:16] [PASSED] drm_test_cmdline_rotate_180
[08:48:16] [PASSED] drm_test_cmdline_rotate_270
[08:48:16] [PASSED] drm_test_cmdline_hmirror
[08:48:16] [PASSED] drm_test_cmdline_vmirror
[08:48:16] [PASSED] drm_test_cmdline_margin_options
[08:48:16] [PASSED] drm_test_cmdline_multiple_options
[08:48:16] [PASSED] drm_test_cmdline_bpp_extra_and_option
[08:48:16] [PASSED] drm_test_cmdline_extra_and_option
[08:48:16] [PASSED] drm_test_cmdline_freestanding_options
[08:48:16] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[08:48:16] [PASSED] drm_test_cmdline_panel_orientation
[08:48:16] ================ drm_test_cmdline_invalid =================
[08:48:16] [PASSED] margin_only
[08:48:16] [PASSED] interlace_only
[08:48:16] [PASSED] res_missing_x
[08:48:16] [PASSED] res_missing_y
[08:48:16] [PASSED] res_bad_y
[08:48:16] [PASSED] res_missing_y_bpp
[08:48:16] [PASSED] res_bad_bpp
[08:48:16] [PASSED] res_bad_refresh
[08:48:16] [PASSED] res_bpp_refresh_force_on_off
[08:48:16] [PASSED] res_invalid_mode
[08:48:16] [PASSED] res_bpp_wrong_place_mode
[08:48:16] [PASSED] name_bpp_refresh
[08:48:16] [PASSED] name_refresh
[08:48:16] [PASSED] name_refresh_wrong_mode
[08:48:16] [PASSED] name_refresh_invalid_mode
[08:48:16] [PASSED] rotate_multiple
[08:48:16] [PASSED] rotate_invalid_val
[08:48:16] [PASSED] rotate_truncated
[08:48:16] [PASSED] invalid_option
[08:48:16] [PASSED] invalid_tv_option
[08:48:16] [PASSED] truncated_tv_option
[08:48:16] ============ [PASSED] drm_test_cmdline_invalid =============
[08:48:16] =============== drm_test_cmdline_tv_options ===============
[08:48:16] [PASSED] NTSC
[08:48:16] [PASSED] NTSC_443
[08:48:16] [PASSED] NTSC_J
[08:48:16] [PASSED] PAL
[08:48:16] [PASSED] PAL_M
[08:48:16] [PASSED] PAL_N
[08:48:16] [PASSED] SECAM
[08:48:16] [PASSED] MONO_525
[08:48:16] [PASSED] MONO_625
[08:48:16] =========== [PASSED] drm_test_cmdline_tv_options ===========
[08:48:16] =============== [PASSED] drm_cmdline_parser ================
[08:48:16] ========== drmm_connector_hdmi_init (20 subtests) ==========
[08:48:16] [PASSED] drm_test_connector_hdmi_init_valid
[08:48:16] [PASSED] drm_test_connector_hdmi_init_bpc_8
[08:48:16] [PASSED] drm_test_connector_hdmi_init_bpc_10
[08:48:16] [PASSED] drm_test_connector_hdmi_init_bpc_12
[08:48:16] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[08:48:16] [PASSED] drm_test_connector_hdmi_init_bpc_null
[08:48:16] [PASSED] drm_test_connector_hdmi_init_formats_empty
[08:48:16] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[08:48:16] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[08:48:16] [PASSED] supported_formats=0x9 yuv420_allowed=1
[08:48:16] [PASSED] supported_formats=0x9 yuv420_allowed=0
[08:48:16] [PASSED] supported_formats=0x3 yuv420_allowed=1
[08:48:16] [PASSED] supported_formats=0x3 yuv420_allowed=0
[08:48:16] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[08:48:16] [PASSED] drm_test_connector_hdmi_init_null_ddc
[08:48:16] [PASSED] drm_test_connector_hdmi_init_null_product
[08:48:16] [PASSED] drm_test_connector_hdmi_init_null_vendor
[08:48:16] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[08:48:16] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[08:48:16] [PASSED] drm_test_connector_hdmi_init_product_valid
[08:48:16] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[08:48:16] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[08:48:16] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[08:48:16] ========= drm_test_connector_hdmi_init_type_valid =========
[08:48:16] [PASSED] HDMI-A
[08:48:16] [PASSED] HDMI-B
[08:48:16] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[08:48:16] ======== drm_test_connector_hdmi_init_type_invalid ========
[08:48:16] [PASSED] Unknown
[08:48:16] [PASSED] VGA
[08:48:16] [PASSED] DVI-I
[08:48:16] [PASSED] DVI-D
[08:48:16] [PASSED] DVI-A
[08:48:16] [PASSED] Composite
[08:48:16] [PASSED] SVIDEO
[08:48:16] [PASSED] LVDS
[08:48:16] [PASSED] Component
[08:48:16] [PASSED] DIN
[08:48:16] [PASSED] DP
[08:48:16] [PASSED] TV
[08:48:16] [PASSED] eDP
[08:48:16] [PASSED] Virtual
[08:48:16] [PASSED] DSI
[08:48:16] [PASSED] DPI
[08:48:16] [PASSED] Writeback
[08:48:16] [PASSED] SPI
[08:48:16] [PASSED] USB
[08:48:16] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[08:48:16] ============ [PASSED] drmm_connector_hdmi_init =============
[08:48:16] ============= drmm_connector_init (3 subtests) =============
[08:48:16] [PASSED] drm_test_drmm_connector_init
[08:48:16] [PASSED] drm_test_drmm_connector_init_null_ddc
[08:48:16] ========= drm_test_drmm_connector_init_type_valid =========
[08:48:16] [PASSED] Unknown
[08:48:16] [PASSED] VGA
[08:48:16] [PASSED] DVI-I
[08:48:16] [PASSED] DVI-D
[08:48:16] [PASSED] DVI-A
[08:48:16] [PASSED] Composite
[08:48:16] [PASSED] SVIDEO
[08:48:16] [PASSED] LVDS
[08:48:16] [PASSED] Component
[08:48:16] [PASSED] DIN
[08:48:16] [PASSED] DP
[08:48:16] [PASSED] HDMI-A
[08:48:16] [PASSED] HDMI-B
[08:48:16] [PASSED] TV
[08:48:16] [PASSED] eDP
[08:48:16] [PASSED] Virtual
[08:48:16] [PASSED] DSI
[08:48:16] [PASSED] DPI
[08:48:16] [PASSED] Writeback
[08:48:16] [PASSED] SPI
[08:48:16] [PASSED] USB
[08:48:16] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[08:48:16] =============== [PASSED] drmm_connector_init ===============
[08:48:16] ========= drm_connector_dynamic_init (6 subtests) ==========
[08:48:16] [PASSED] drm_test_drm_connector_dynamic_init
[08:48:16] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[08:48:16] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[08:48:16] [PASSED] drm_test_drm_connector_dynamic_init_properties
[08:48:16] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[08:48:16] [PASSED] Unknown
[08:48:16] [PASSED] VGA
[08:48:16] [PASSED] DVI-I
[08:48:16] [PASSED] DVI-D
[08:48:16] [PASSED] DVI-A
[08:48:16] [PASSED] Composite
[08:48:16] [PASSED] SVIDEO
[08:48:16] [PASSED] LVDS
[08:48:16] [PASSED] Component
[08:48:16] [PASSED] DIN
[08:48:16] [PASSED] DP
[08:48:16] [PASSED] HDMI-A
[08:48:16] [PASSED] HDMI-B
[08:48:16] [PASSED] TV
[08:48:16] [PASSED] eDP
[08:48:16] [PASSED] Virtual
[08:48:16] [PASSED] DSI
[08:48:16] [PASSED] DPI
[08:48:16] [PASSED] Writeback
[08:48:16] [PASSED] SPI
[08:48:16] [PASSED] USB
[08:48:16] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[08:48:16] ======== drm_test_drm_connector_dynamic_init_name =========
[08:48:16] [PASSED] Unknown
[08:48:16] [PASSED] VGA
[08:48:16] [PASSED] DVI-I
[08:48:16] [PASSED] DVI-D
[08:48:16] [PASSED] DVI-A
[08:48:16] [PASSED] Composite
[08:48:16] [PASSED] SVIDEO
[08:48:16] [PASSED] LVDS
[08:48:16] [PASSED] Component
[08:48:16] [PASSED] DIN
[08:48:16] [PASSED] DP
[08:48:16] [PASSED] HDMI-A
[08:48:16] [PASSED] HDMI-B
[08:48:16] [PASSED] TV
[08:48:16] [PASSED] eDP
[08:48:16] [PASSED] Virtual
[08:48:16] [PASSED] DSI
[08:48:16] [PASSED] DPI
[08:48:16] [PASSED] Writeback
[08:48:16] [PASSED] SPI
[08:48:16] [PASSED] USB
[08:48:16] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[08:48:16] =========== [PASSED] drm_connector_dynamic_init ============
[08:48:16] ==== drm_connector_dynamic_register_early (4 subtests) =====
[08:48:16] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[08:48:16] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[08:48:16] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[08:48:16] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[08:48:16] ====== [PASSED] drm_connector_dynamic_register_early =======
[08:48:16] ======= drm_connector_dynamic_register (7 subtests) ========
[08:48:16] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[08:48:16] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[08:48:16] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[08:48:16] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[08:48:16] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[08:48:16] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[08:48:16] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[08:48:16] ========= [PASSED] drm_connector_dynamic_register ==========
[08:48:16] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[08:48:16] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[08:48:16] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[08:48:16] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[08:48:16] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[08:48:16] ========== drm_test_get_tv_mode_from_name_valid ===========
[08:48:16] [PASSED] NTSC
[08:48:16] [PASSED] NTSC-443
[08:48:16] [PASSED] NTSC-J
[08:48:16] [PASSED] PAL
[08:48:16] [PASSED] PAL-M
[08:48:16] [PASSED] PAL-N
[08:48:16] [PASSED] SECAM
[08:48:16] [PASSED] Mono
[08:48:16] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[08:48:16] [PASSED] drm_test_get_tv_mode_from_name_truncated
[08:48:16] ============ [PASSED] drm_get_tv_mode_from_name ============
[08:48:16] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[08:48:16] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[08:48:16] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[08:48:16] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[08:48:16] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[08:48:16] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[08:48:16] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[08:48:16] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[08:48:16] [PASSED] VIC 96
[08:48:16] [PASSED] VIC 97
[08:48:16] [PASSED] VIC 101
[08:48:16] [PASSED] VIC 102
[08:48:16] [PASSED] VIC 106
[08:48:16] [PASSED] VIC 107
[08:48:16] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[08:48:16] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[08:48:16] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[08:48:16] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[08:48:16] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[08:48:16] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[08:48:16] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[08:48:16] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[08:48:16] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[08:48:16] [PASSED] Automatic
[08:48:16] [PASSED] Full
[08:48:16] [PASSED] Limited 16:235
[08:48:16] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[08:48:16] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[08:48:16] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[08:48:16] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[08:48:16] === drm_test_drm_hdmi_connector_get_output_format_name ====
[08:48:16] [PASSED] RGB
[08:48:16] [PASSED] YUV 4:2:0
[08:48:16] [PASSED] YUV 4:2:2
[08:48:16] [PASSED] YUV 4:4:4
[08:48:16] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[08:48:16] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[08:48:16] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[08:48:16] ============= drm_damage_helper (21 subtests) ==============
[08:48:16] [PASSED] drm_test_damage_iter_no_damage
[08:48:16] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[08:48:16] [PASSED] drm_test_damage_iter_no_damage_src_moved
[08:48:16] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[08:48:16] [PASSED] drm_test_damage_iter_no_damage_not_visible
[08:48:16] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[08:48:16] [PASSED] drm_test_damage_iter_no_damage_no_fb
[08:48:16] [PASSED] drm_test_damage_iter_simple_damage
[08:48:16] [PASSED] drm_test_damage_iter_single_damage
[08:48:16] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[08:48:16] [PASSED] drm_test_damage_iter_single_damage_outside_src
[08:48:16] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[08:48:16] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[08:48:16] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[08:48:16] [PASSED] drm_test_damage_iter_single_damage_src_moved
[08:48:16] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[08:48:16] [PASSED] drm_test_damage_iter_damage
[08:48:16] [PASSED] drm_test_damage_iter_damage_one_intersect
[08:48:16] [PASSED] drm_test_damage_iter_damage_one_outside
[08:48:16] [PASSED] drm_test_damage_iter_damage_src_moved
[08:48:16] [PASSED] drm_test_damage_iter_damage_not_visible
[08:48:16] ================ [PASSED] drm_damage_helper ================
[08:48:16] ============== drm_dp_mst_helper (3 subtests) ==============
[08:48:16] ============== drm_test_dp_mst_calc_pbn_mode ==============
[08:48:16] [PASSED] Clock 154000 BPP 30 DSC disabled
[08:48:16] [PASSED] Clock 234000 BPP 30 DSC disabled
[08:48:16] [PASSED] Clock 297000 BPP 24 DSC disabled
[08:48:16] [PASSED] Clock 332880 BPP 24 DSC enabled
[08:48:16] [PASSED] Clock 324540 BPP 24 DSC enabled
[08:48:16] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[08:48:16] ============== drm_test_dp_mst_calc_pbn_div ===============
[08:48:16] [PASSED] Link rate 2000000 lane count 4
[08:48:16] [PASSED] Link rate 2000000 lane count 2
[08:48:16] [PASSED] Link rate 2000000 lane count 1
[08:48:16] [PASSED] Link rate 1350000 lane count 4
[08:48:16] [PASSED] Link rate 1350000 lane count 2
[08:48:16] [PASSED] Link rate 1350000 lane count 1
[08:48:16] [PASSED] Link rate 1000000 lane count 4
[08:48:16] [PASSED] Link rate 1000000 lane count 2
[08:48:16] [PASSED] Link rate 1000000 lane count 1
[08:48:16] [PASSED] Link rate 810000 lane count 4
[08:48:16] [PASSED] Link rate 810000 lane count 2
[08:48:16] [PASSED] Link rate 810000 lane count 1
[08:48:16] [PASSED] Link rate 540000 lane count 4
[08:48:16] [PASSED] Link rate 540000 lane count 2
[08:48:16] [PASSED] Link rate 540000 lane count 1
[08:48:16] [PASSED] Link rate 270000 lane count 4
[08:48:16] [PASSED] Link rate 270000 lane count 2
[08:48:16] [PASSED] Link rate 270000 lane count 1
[08:48:16] [PASSED] Link rate 162000 lane count 4
[08:48:16] [PASSED] Link rate 162000 lane count 2
[08:48:16] [PASSED] Link rate 162000 lane count 1
[08:48:16] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[08:48:16] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[08:48:16] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[08:48:16] [PASSED] DP_POWER_UP_PHY with port number
[08:48:16] [PASSED] DP_POWER_DOWN_PHY with port number
[08:48:16] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[08:48:16] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[08:48:16] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[08:48:16] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[08:48:16] [PASSED] DP_QUERY_PAYLOAD with port number
[08:48:16] [PASSED] DP_QUERY_PAYLOAD with VCPI
[08:48:16] [PASSED] DP_REMOTE_DPCD_READ with port number
[08:48:16] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[08:48:16] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[08:48:16] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[08:48:16] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[08:48:16] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[08:48:16] [PASSED] DP_REMOTE_I2C_READ with port number
[08:48:16] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[08:48:16] [PASSED] DP_REMOTE_I2C_READ with transactions array
[08:48:16] [PASSED] DP_REMOTE_I2C_WRITE with port number
[08:48:16] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[08:48:16] [PASSED] DP_REMOTE_I2C_WRITE with data array
[08:48:16] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[08:48:16] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[08:48:16] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[08:48:16] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[08:48:16] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[08:48:16] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[08:48:16] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[08:48:16] ================ [PASSED] drm_dp_mst_helper ================
[08:48:16] ================== drm_exec (7 subtests) ===================
[08:48:16] [PASSED] sanitycheck
[08:48:16] [PASSED] test_lock
[08:48:16] [PASSED] test_lock_unlock
[08:48:16] [PASSED] test_duplicates
[08:48:16] [PASSED] test_prepare
[08:48:16] [PASSED] test_prepare_array
[08:48:16] [PASSED] test_multiple_loops
[08:48:16] ==================== [PASSED] drm_exec =====================
[08:48:16] =========== drm_format_helper_test (17 subtests) ===========
[08:48:16] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[08:48:16] [PASSED] single_pixel_source_buffer
[08:48:16] [PASSED] single_pixel_clip_rectangle
[08:48:16] [PASSED] well_known_colors
[08:48:16] [PASSED] destination_pitch
[08:48:16] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[08:48:16] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[08:48:16] [PASSED] single_pixel_source_buffer
[08:48:16] [PASSED] single_pixel_clip_rectangle
[08:48:16] [PASSED] well_known_colors
[08:48:16] [PASSED] destination_pitch
[08:48:16] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[08:48:16] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[08:48:16] [PASSED] single_pixel_source_buffer
[08:48:16] [PASSED] single_pixel_clip_rectangle
[08:48:16] [PASSED] well_known_colors
[08:48:16] [PASSED] destination_pitch
[08:48:16] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[08:48:16] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[08:48:16] [PASSED] single_pixel_source_buffer
[08:48:16] [PASSED] single_pixel_clip_rectangle
[08:48:16] [PASSED] well_known_colors
[08:48:16] [PASSED] destination_pitch
[08:48:16] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[08:48:16] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[08:48:16] [PASSED] single_pixel_source_buffer
[08:48:16] [PASSED] single_pixel_clip_rectangle
[08:48:16] [PASSED] well_known_colors
[08:48:16] [PASSED] destination_pitch
[08:48:16] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[08:48:16] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[08:48:16] [PASSED] single_pixel_source_buffer
[08:48:16] [PASSED] single_pixel_clip_rectangle
[08:48:16] [PASSED] well_known_colors
[08:48:16] [PASSED] destination_pitch
[08:48:16] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[08:48:16] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[08:48:16] [PASSED] single_pixel_source_buffer
[08:48:16] [PASSED] single_pixel_clip_rectangle
[08:48:16] [PASSED] well_known_colors
[08:48:16] [PASSED] destination_pitch
[08:48:16] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[08:48:16] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[08:48:16] [PASSED] single_pixel_source_buffer
[08:48:16] [PASSED] single_pixel_clip_rectangle
[08:48:16] [PASSED] well_known_colors
[08:48:16] [PASSED] destination_pitch
[08:48:16] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[08:48:16] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[08:48:16] [PASSED] single_pixel_source_buffer
[08:48:16] [PASSED] single_pixel_clip_rectangle
[08:48:16] [PASSED] well_known_colors
[08:48:16] [PASSED] destination_pitch
[08:48:16] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[08:48:16] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[08:48:16] [PASSED] single_pixel_source_buffer
[08:48:16] [PASSED] single_pixel_clip_rectangle
[08:48:16] [PASSED] well_known_colors
[08:48:16] [PASSED] destination_pitch
[08:48:16] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[08:48:16] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[08:48:16] [PASSED] single_pixel_source_buffer
[08:48:16] [PASSED] single_pixel_clip_rectangle
[08:48:16] [PASSED] well_known_colors
[08:48:16] [PASSED] destination_pitch
[08:48:16] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[08:48:16] ============== drm_test_fb_xrgb8888_to_mono ===============
[08:48:16] [PASSED] single_pixel_source_buffer
[08:48:16] [PASSED] single_pixel_clip_rectangle
[08:48:16] [PASSED] well_known_colors
[08:48:16] [PASSED] destination_pitch
[08:48:16] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[08:48:16] ==================== drm_test_fb_swab =====================
[08:48:16] [PASSED] single_pixel_source_buffer
[08:48:16] [PASSED] single_pixel_clip_rectangle
[08:48:16] [PASSED] well_known_colors
[08:48:16] [PASSED] destination_pitch
[08:48:16] ================ [PASSED] drm_test_fb_swab =================
[08:48:16] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[08:48:16] [PASSED] single_pixel_source_buffer
[08:48:16] [PASSED] single_pixel_clip_rectangle
[08:48:16] [PASSED] well_known_colors
[08:48:16] [PASSED] destination_pitch
[08:48:16] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[08:48:16] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[08:48:16] [PASSED] single_pixel_source_buffer
[08:48:16] [PASSED] single_pixel_clip_rectangle
[08:48:16] [PASSED] well_known_colors
[08:48:16] [PASSED] destination_pitch
[08:48:16] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[08:48:16] ================= drm_test_fb_clip_offset =================
[08:48:16] [PASSED] pass through
[08:48:16] [PASSED] horizontal offset
[08:48:16] [PASSED] vertical offset
[08:48:16] [PASSED] horizontal and vertical offset
[08:48:16] [PASSED] horizontal offset (custom pitch)
[08:48:16] [PASSED] vertical offset (custom pitch)
[08:48:16] [PASSED] horizontal and vertical offset (custom pitch)
[08:48:16] ============= [PASSED] drm_test_fb_clip_offset =============
[08:48:16] =================== drm_test_fb_memcpy ====================
[08:48:16] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[08:48:16] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[08:48:16] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[08:48:16] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[08:48:16] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[08:48:16] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[08:48:16] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[08:48:16] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[08:48:16] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[08:48:16] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[08:48:16] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[08:48:16] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[08:48:16] =============== [PASSED] drm_test_fb_memcpy ================
[08:48:16] ============= [PASSED] drm_format_helper_test ==============
[08:48:16] ================= drm_format (18 subtests) =================
[08:48:16] [PASSED] drm_test_format_block_width_invalid
[08:48:16] [PASSED] drm_test_format_block_width_one_plane
[08:48:16] [PASSED] drm_test_format_block_width_two_plane
[08:48:16] [PASSED] drm_test_format_block_width_three_plane
[08:48:16] [PASSED] drm_test_format_block_width_tiled
[08:48:16] [PASSED] drm_test_format_block_height_invalid
[08:48:16] [PASSED] drm_test_format_block_height_one_plane
[08:48:16] [PASSED] drm_test_format_block_height_two_plane
[08:48:16] [PASSED] drm_test_format_block_height_three_plane
[08:48:16] [PASSED] drm_test_format_block_height_tiled
[08:48:16] [PASSED] drm_test_format_min_pitch_invalid
[08:48:16] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[08:48:16] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[08:48:16] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[08:48:16] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[08:48:16] [PASSED] drm_test_format_min_pitch_two_plane
[08:48:16] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[08:48:16] [PASSED] drm_test_format_min_pitch_tiled
[08:48:16] =================== [PASSED] drm_format ====================
[08:48:16] ============== drm_framebuffer (10 subtests) ===============
[08:48:16] ========== drm_test_framebuffer_check_src_coords ==========
[08:48:16] [PASSED] Success: source fits into fb
[08:48:16] [PASSED] Fail: overflowing fb with x-axis coordinate
[08:48:16] [PASSED] Fail: overflowing fb with y-axis coordinate
[08:48:16] [PASSED] Fail: overflowing fb with source width
[08:48:16] [PASSED] Fail: overflowing fb with source height
[08:48:16] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[08:48:16] [PASSED] drm_test_framebuffer_cleanup
[08:48:16] =============== drm_test_framebuffer_create ===============
[08:48:16] [PASSED] ABGR8888 normal sizes
[08:48:16] [PASSED] ABGR8888 max sizes
[08:48:16] [PASSED] ABGR8888 pitch greater than min required
[08:48:16] [PASSED] ABGR8888 pitch less than min required
[08:48:16] [PASSED] ABGR8888 Invalid width
[08:48:16] [PASSED] ABGR8888 Invalid buffer handle
[08:48:16] [PASSED] No pixel format
[08:48:16] [PASSED] ABGR8888 Width 0
[08:48:16] [PASSED] ABGR8888 Height 0
[08:48:16] [PASSED] ABGR8888 Out of bound height * pitch combination
[08:48:16] [PASSED] ABGR8888 Large buffer offset
[08:48:16] [PASSED] ABGR8888 Buffer offset for inexistent plane
[08:48:16] [PASSED] ABGR8888 Invalid flag
[08:48:16] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[08:48:16] [PASSED] ABGR8888 Valid buffer modifier
[08:48:16] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[08:48:16] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[08:48:16] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[08:48:16] [PASSED] NV12 Normal sizes
[08:48:16] [PASSED] NV12 Max sizes
[08:48:16] [PASSED] NV12 Invalid pitch
[08:48:16] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[08:48:16] [PASSED] NV12 different modifier per-plane
[08:48:16] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[08:48:16] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[08:48:16] [PASSED] NV12 Modifier for inexistent plane
[08:48:16] [PASSED] NV12 Handle for inexistent plane
[08:48:16] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[08:48:16] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[08:48:16] [PASSED] YVU420 Normal sizes
[08:48:16] [PASSED] YVU420 Max sizes
[08:48:16] [PASSED] YVU420 Invalid pitch
[08:48:16] [PASSED] YVU420 Different pitches
[08:48:16] [PASSED] YVU420 Different buffer offsets/pitches
[08:48:16] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[08:48:16] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[08:48:16] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[08:48:16] [PASSED] YVU420 Valid modifier
[08:48:16] [PASSED] YVU420 Different modifiers per plane
[08:48:16] [PASSED] YVU420 Modifier for inexistent plane
[08:48:16] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[08:48:16] [PASSED] X0L2 Normal sizes
[08:48:16] [PASSED] X0L2 Max sizes
[08:48:16] [PASSED] X0L2 Invalid pitch
[08:48:16] [PASSED] X0L2 Pitch greater than minimum required
[08:48:16] [PASSED] X0L2 Handle for inexistent plane
[08:48:16] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[08:48:16] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[08:48:16] [PASSED] X0L2 Valid modifier
[08:48:16] [PASSED] X0L2 Modifier for inexistent plane
[08:48:16] =========== [PASSED] drm_test_framebuffer_create ===========
[08:48:16] [PASSED] drm_test_framebuffer_free
[08:48:16] [PASSED] drm_test_framebuffer_init
[08:48:16] [PASSED] drm_test_framebuffer_init_bad_format
[08:48:16] [PASSED] drm_test_framebuffer_init_dev_mismatch
[08:48:16] [PASSED] drm_test_framebuffer_lookup
[08:48:16] [PASSED] drm_test_framebuffer_lookup_inexistent
[08:48:16] [PASSED] drm_test_framebuffer_modifiers_not_supported
[08:48:16] ================= [PASSED] drm_framebuffer =================
[08:48:16] ================ drm_gem_shmem (8 subtests) ================
[08:48:16] [PASSED] drm_gem_shmem_test_obj_create
[08:48:16] [PASSED] drm_gem_shmem_test_obj_create_private
[08:48:16] [PASSED] drm_gem_shmem_test_pin_pages
[08:48:16] [PASSED] drm_gem_shmem_test_vmap
[08:48:16] [PASSED] drm_gem_shmem_test_get_pages_sgt
[08:48:16] [PASSED] drm_gem_shmem_test_get_sg_table
[08:48:16] [PASSED] drm_gem_shmem_test_madvise
[08:48:16] [PASSED] drm_gem_shmem_test_purge
[08:48:16] ================== [PASSED] drm_gem_shmem ==================
[08:48:16] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[08:48:16] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[08:48:16] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[08:48:16] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[08:48:16] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[08:48:16] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[08:48:16] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[08:48:16] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[08:48:16] [PASSED] Automatic
[08:48:16] [PASSED] Full
[08:48:16] [PASSED] Limited 16:235
[08:48:16] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[08:48:16] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[08:48:16] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[08:48:16] [PASSED] drm_test_check_disable_connector
[08:48:16] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[08:48:16] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[08:48:16] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[08:48:16] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[08:48:16] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[08:48:16] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[08:48:16] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[08:48:16] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[08:48:16] [PASSED] drm_test_check_output_bpc_dvi
[08:48:16] [PASSED] drm_test_check_output_bpc_format_vic_1
[08:48:16] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[08:48:16] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[08:48:16] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[08:48:16] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[08:48:16] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[08:48:16] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[08:48:16] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[08:48:16] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[08:48:16] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[08:48:16] [PASSED] drm_test_check_broadcast_rgb_value
[08:48:16] [PASSED] drm_test_check_bpc_8_value
[08:48:16] [PASSED] drm_test_check_bpc_10_value
[08:48:16] [PASSED] drm_test_check_bpc_12_value
[08:48:16] [PASSED] drm_test_check_format_value
[08:48:16] [PASSED] drm_test_check_tmds_char_value
[08:48:16] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[08:48:16] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[08:48:16] [PASSED] drm_test_check_mode_valid
[08:48:16] [PASSED] drm_test_check_mode_valid_reject
[08:48:16] [PASSED] drm_test_check_mode_valid_reject_rate
[08:48:16] [PASSED] drm_test_check_mode_valid_reject_max_clock
[08:48:16] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[08:48:16] ================= drm_managed (2 subtests) =================
[08:48:16] [PASSED] drm_test_managed_release_action
[08:48:16] [PASSED] drm_test_managed_run_action
[08:48:16] =================== [PASSED] drm_managed ===================
[08:48:16] =================== drm_mm (6 subtests) ====================
[08:48:16] [PASSED] drm_test_mm_init
[08:48:16] [PASSED] drm_test_mm_debug
[08:48:16] [PASSED] drm_test_mm_align32
[08:48:16] [PASSED] drm_test_mm_align64
[08:48:16] [PASSED] drm_test_mm_lowest
[08:48:16] [PASSED] drm_test_mm_highest
[08:48:16] ===================== [PASSED] drm_mm ======================
[08:48:16] ============= drm_modes_analog_tv (5 subtests) =============
[08:48:16] [PASSED] drm_test_modes_analog_tv_mono_576i
[08:48:16] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[08:48:16] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[08:48:16] [PASSED] drm_test_modes_analog_tv_pal_576i
[08:48:16] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[08:48:16] =============== [PASSED] drm_modes_analog_tv ===============
[08:48:16] ============== drm_plane_helper (2 subtests) ===============
[08:48:16] =============== drm_test_check_plane_state ================
[08:48:16] [PASSED] clipping_simple
[08:48:16] [PASSED] clipping_rotate_reflect
[08:48:16] [PASSED] positioning_simple
[08:48:16] [PASSED] upscaling
[08:48:16] [PASSED] downscaling
[08:48:16] [PASSED] rounding1
[08:48:16] [PASSED] rounding2
[08:48:16] [PASSED] rounding3
[08:48:16] [PASSED] rounding4
[08:48:16] =========== [PASSED] drm_test_check_plane_state ============
[08:48:16] =========== drm_test_check_invalid_plane_state ============
[08:48:16] [PASSED] positioning_invalid
[08:48:16] [PASSED] upscaling_invalid
[08:48:16] [PASSED] downscaling_invalid
[08:48:16] ======= [PASSED] drm_test_check_invalid_plane_state ========
[08:48:16] ================ [PASSED] drm_plane_helper =================
[08:48:16] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[08:48:16] ====== drm_test_connector_helper_tv_get_modes_check =======
[08:48:16] [PASSED] None
[08:48:16] [PASSED] PAL
[08:48:16] [PASSED] NTSC
[08:48:16] [PASSED] Both, NTSC Default
[08:48:16] [PASSED] Both, PAL Default
[08:48:16] [PASSED] Both, NTSC Default, with PAL on command-line
[08:48:16] [PASSED] Both, PAL Default, with NTSC on command-line
[08:48:16] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[08:48:16] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[08:48:16] ================== drm_rect (9 subtests) ===================
[08:48:16] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[08:48:16] [PASSED] drm_test_rect_clip_scaled_not_clipped
[08:48:16] [PASSED] drm_test_rect_clip_scaled_clipped
[08:48:16] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[08:48:16] ================= drm_test_rect_intersect =================
[08:48:16] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[08:48:16] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[08:48:16] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[08:48:16] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[08:48:16] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[08:48:16] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[08:48:16] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[08:48:16] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[08:48:16] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[08:48:16] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[08:48:16] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[08:48:16] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[08:48:16] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[08:48:16] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[08:48:16] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[08:48:16] ============= [PASSED] drm_test_rect_intersect =============
[08:48:16] ================ drm_test_rect_calc_hscale ================
[08:48:16] [PASSED] normal use
[08:48:16] [PASSED] out of max range
[08:48:16] [PASSED] out of min range
[08:48:16] [PASSED] zero dst
[08:48:16] [PASSED] negative src
[08:48:16] [PASSED] negative dst
[08:48:16] ============ [PASSED] drm_test_rect_calc_hscale ============
[08:48:16] ================ drm_test_rect_calc_vscale ================
[08:48:16] [PASSED] normal use
stty: 'standard input': Inappropriate ioctl for device
[08:48:16] [PASSED] out of max range
[08:48:16] [PASSED] out of min range
[08:48:16] [PASSED] zero dst
[08:48:16] [PASSED] negative src
[08:48:16] [PASSED] negative dst
[08:48:16] ============ [PASSED] drm_test_rect_calc_vscale ============
[08:48:16] ================== drm_test_rect_rotate ===================
[08:48:16] [PASSED] reflect-x
[08:48:16] [PASSED] reflect-y
[08:48:16] [PASSED] rotate-0
[08:48:16] [PASSED] rotate-90
[08:48:16] [PASSED] rotate-180
[08:48:16] [PASSED] rotate-270
[08:48:16] ============== [PASSED] drm_test_rect_rotate ===============
[08:48:16] ================ drm_test_rect_rotate_inv =================
[08:48:16] [PASSED] reflect-x
[08:48:16] [PASSED] reflect-y
[08:48:16] [PASSED] rotate-0
[08:48:16] [PASSED] rotate-90
[08:48:16] [PASSED] rotate-180
[08:48:16] [PASSED] rotate-270
[08:48:16] ============ [PASSED] drm_test_rect_rotate_inv =============
[08:48:16] ==================== [PASSED] drm_rect =====================
[08:48:16] ============ drm_sysfb_modeset_test (1 subtest) ============
[08:48:16] ============ drm_test_sysfb_build_fourcc_list =============
[08:48:16] [PASSED] no native formats
[08:48:16] [PASSED] XRGB8888 as native format
[08:48:16] [PASSED] remove duplicates
[08:48:16] [PASSED] convert alpha formats
[08:48:16] [PASSED] random formats
[08:48:16] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[08:48:16] ============= [PASSED] drm_sysfb_modeset_test ==============
[08:48:16] ================== drm_fixp (2 subtests) ===================
[08:48:16] [PASSED] drm_test_int2fixp
[08:48:16] [PASSED] drm_test_sm2fixp
[08:48:16] ==================== [PASSED] drm_fixp =====================
[08:48:16] ============================================================
[08:48:16] Testing complete. Ran 624 tests: passed: 624
[08:48:16] Elapsed time: 26.752s total, 1.668s configuring, 24.611s building, 0.442s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[08:48:16] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[08:48:18] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[08:48:27] Starting KUnit Kernel (1/1)...
[08:48:27] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[08:48:27] ================= ttm_device (5 subtests) ==================
[08:48:27] [PASSED] ttm_device_init_basic
[08:48:27] [PASSED] ttm_device_init_multiple
[08:48:27] [PASSED] ttm_device_fini_basic
[08:48:27] [PASSED] ttm_device_init_no_vma_man
[08:48:27] ================== ttm_device_init_pools ==================
[08:48:27] [PASSED] No DMA allocations, no DMA32 required
[08:48:27] [PASSED] DMA allocations, DMA32 required
[08:48:27] [PASSED] No DMA allocations, DMA32 required
[08:48:27] [PASSED] DMA allocations, no DMA32 required
[08:48:27] ============== [PASSED] ttm_device_init_pools ==============
[08:48:27] =================== [PASSED] ttm_device ====================
[08:48:27] ================== ttm_pool (8 subtests) ===================
[08:48:27] ================== ttm_pool_alloc_basic ===================
[08:48:27] [PASSED] One page
[08:48:27] [PASSED] More than one page
[08:48:27] [PASSED] Above the allocation limit
[08:48:27] [PASSED] One page, with coherent DMA mappings enabled
[08:48:27] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[08:48:27] ============== [PASSED] ttm_pool_alloc_basic ===============
[08:48:27] ============== ttm_pool_alloc_basic_dma_addr ==============
[08:48:27] [PASSED] One page
[08:48:27] [PASSED] More than one page
[08:48:27] [PASSED] Above the allocation limit
[08:48:27] [PASSED] One page, with coherent DMA mappings enabled
[08:48:27] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[08:48:27] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[08:48:27] [PASSED] ttm_pool_alloc_order_caching_match
[08:48:27] [PASSED] ttm_pool_alloc_caching_mismatch
[08:48:27] [PASSED] ttm_pool_alloc_order_mismatch
[08:48:27] [PASSED] ttm_pool_free_dma_alloc
[08:48:27] [PASSED] ttm_pool_free_no_dma_alloc
[08:48:27] [PASSED] ttm_pool_fini_basic
[08:48:27] ==================== [PASSED] ttm_pool =====================
[08:48:27] ================ ttm_resource (8 subtests) =================
[08:48:27] ================= ttm_resource_init_basic =================
[08:48:27] [PASSED] Init resource in TTM_PL_SYSTEM
[08:48:27] [PASSED] Init resource in TTM_PL_VRAM
[08:48:27] [PASSED] Init resource in a private placement
[08:48:27] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[08:48:27] ============= [PASSED] ttm_resource_init_basic =============
[08:48:27] [PASSED] ttm_resource_init_pinned
[08:48:27] [PASSED] ttm_resource_fini_basic
[08:48:27] [PASSED] ttm_resource_manager_init_basic
[08:48:27] [PASSED] ttm_resource_manager_usage_basic
[08:48:27] [PASSED] ttm_resource_manager_set_used_basic
[08:48:27] [PASSED] ttm_sys_man_alloc_basic
[08:48:27] [PASSED] ttm_sys_man_free_basic
[08:48:27] ================== [PASSED] ttm_resource ===================
[08:48:27] =================== ttm_tt (15 subtests) ===================
[08:48:27] ==================== ttm_tt_init_basic ====================
[08:48:27] [PASSED] Page-aligned size
[08:48:27] [PASSED] Extra pages requested
[08:48:27] ================ [PASSED] ttm_tt_init_basic ================
[08:48:27] [PASSED] ttm_tt_init_misaligned
[08:48:27] [PASSED] ttm_tt_fini_basic
[08:48:27] [PASSED] ttm_tt_fini_sg
[08:48:27] [PASSED] ttm_tt_fini_shmem
[08:48:27] [PASSED] ttm_tt_create_basic
[08:48:27] [PASSED] ttm_tt_create_invalid_bo_type
[08:48:27] [PASSED] ttm_tt_create_ttm_exists
[08:48:27] [PASSED] ttm_tt_create_failed
[08:48:27] [PASSED] ttm_tt_destroy_basic
[08:48:27] [PASSED] ttm_tt_populate_null_ttm
[08:48:27] [PASSED] ttm_tt_populate_populated_ttm
[08:48:27] [PASSED] ttm_tt_unpopulate_basic
[08:48:27] [PASSED] ttm_tt_unpopulate_empty_ttm
[08:48:27] [PASSED] ttm_tt_swapin_basic
[08:48:27] ===================== [PASSED] ttm_tt ======================
[08:48:27] =================== ttm_bo (14 subtests) ===================
[08:48:27] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[08:48:27] [PASSED] Cannot be interrupted and sleeps
[08:48:27] [PASSED] Cannot be interrupted, locks straight away
[08:48:27] [PASSED] Can be interrupted, sleeps
[08:48:27] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[08:48:27] [PASSED] ttm_bo_reserve_locked_no_sleep
[08:48:27] [PASSED] ttm_bo_reserve_no_wait_ticket
[08:48:27] [PASSED] ttm_bo_reserve_double_resv
[08:48:27] [PASSED] ttm_bo_reserve_interrupted
[08:48:27] [PASSED] ttm_bo_reserve_deadlock
[08:48:27] [PASSED] ttm_bo_unreserve_basic
[08:48:27] [PASSED] ttm_bo_unreserve_pinned
[08:48:27] [PASSED] ttm_bo_unreserve_bulk
[08:48:27] [PASSED] ttm_bo_fini_basic
[08:48:27] [PASSED] ttm_bo_fini_shared_resv
[08:48:27] [PASSED] ttm_bo_pin_basic
[08:48:27] [PASSED] ttm_bo_pin_unpin_resource
[08:48:27] [PASSED] ttm_bo_multiple_pin_one_unpin
[08:48:27] ===================== [PASSED] ttm_bo ======================
[08:48:27] ============== ttm_bo_validate (21 subtests) ===============
[08:48:27] ============== ttm_bo_init_reserved_sys_man ===============
[08:48:27] [PASSED] Buffer object for userspace
[08:48:27] [PASSED] Kernel buffer object
[08:48:27] [PASSED] Shared buffer object
[08:48:27] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[08:48:27] ============== ttm_bo_init_reserved_mock_man ==============
[08:48:27] [PASSED] Buffer object for userspace
[08:48:27] [PASSED] Kernel buffer object
[08:48:27] [PASSED] Shared buffer object
[08:48:27] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[08:48:27] [PASSED] ttm_bo_init_reserved_resv
[08:48:27] ================== ttm_bo_validate_basic ==================
[08:48:27] [PASSED] Buffer object for userspace
[08:48:27] [PASSED] Kernel buffer object
[08:48:27] [PASSED] Shared buffer object
[08:48:27] ============== [PASSED] ttm_bo_validate_basic ==============
[08:48:27] [PASSED] ttm_bo_validate_invalid_placement
[08:48:27] ============= ttm_bo_validate_same_placement ==============
[08:48:27] [PASSED] System manager
[08:48:27] [PASSED] VRAM manager
[08:48:27] ========= [PASSED] ttm_bo_validate_same_placement ==========
[08:48:27] [PASSED] ttm_bo_validate_failed_alloc
[08:48:27] [PASSED] ttm_bo_validate_pinned
[08:48:27] [PASSED] ttm_bo_validate_busy_placement
[08:48:27] ================ ttm_bo_validate_multihop =================
[08:48:27] [PASSED] Buffer object for userspace
[08:48:27] [PASSED] Kernel buffer object
[08:48:27] [PASSED] Shared buffer object
[08:48:27] ============ [PASSED] ttm_bo_validate_multihop =============
[08:48:27] ========== ttm_bo_validate_no_placement_signaled ==========
[08:48:27] [PASSED] Buffer object in system domain, no page vector
[08:48:27] [PASSED] Buffer object in system domain with an existing page vector
[08:48:27] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[08:48:27] ======== ttm_bo_validate_no_placement_not_signaled ========
[08:48:27] [PASSED] Buffer object for userspace
[08:48:27] [PASSED] Kernel buffer object
[08:48:27] [PASSED] Shared buffer object
[08:48:27] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[08:48:27] [PASSED] ttm_bo_validate_move_fence_signaled
[08:48:27] ========= ttm_bo_validate_move_fence_not_signaled =========
[08:48:27] [PASSED] Waits for GPU
[08:48:27] [PASSED] Tries to lock straight away
[08:48:27] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[08:48:27] [PASSED] ttm_bo_validate_happy_evict
[08:48:27] [PASSED] ttm_bo_validate_all_pinned_evict
[08:48:27] [PASSED] ttm_bo_validate_allowed_only_evict
[08:48:27] [PASSED] ttm_bo_validate_deleted_evict
[08:48:27] [PASSED] ttm_bo_validate_busy_domain_evict
[08:48:27] [PASSED] ttm_bo_validate_evict_gutting
[08:48:27] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[08:48:27] ================= [PASSED] ttm_bo_validate =================
[08:48:27] ============================================================
[08:48:27] Testing complete. Ran 101 tests: passed: 101
[08:48:27] Elapsed time: 11.183s total, 1.701s configuring, 9.216s building, 0.219s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 29+ messages in thread
* [v8 00/15] Plane Color Pipeline support for Intel platforms
@ 2025-12-03 8:51 Uma Shankar
2025-12-03 8:47 ` ✗ CI.checkpatch: warning for Plane Color Pipeline support for Intel platforms (rev7) Patchwork
` (17 more replies)
0 siblings, 18 replies; 29+ messages in thread
From: Uma Shankar @ 2025-12-03 8:51 UTC (permalink / raw)
To: intel-gfx, intel-xe, dri-devel
Cc: chaitanya.kumar.borah, ville.syrjala, pekka.paalanen, contact,
harry.wentland, mwen, jadahl, sebastian.wick, swati2.sharma,
alex.hung, jani.nikula, suraj.kandpal, Uma Shankar, Joshua Ashton,
Michel Dänzer, Xaver Hugl, Victoria Brekenfeld, Sima,
Liviu Dudau
This series intends to add support for Plane Color Management for
Intel platforms. This is based on the design which has been agreed
upon by the community. Series implementing the design for generic
DRM core has been sent out by Alex Hung and Harry Wentland and is
merged to upstream tree:
https://patchwork.freedesktop.org/series/152970/
IGT Changes to validate the same have been implemented and can be found
below:
https://patchwork.freedesktop.org/series/150455/
Follow On work:
Changes for Multi Segmented/PWL LUT's will be taken up in a separate
series to align with implementation of basic color pipeline first in
upstream. This is as per agreement and alignment in Hackfest discussion.
Changes in v8:
- Review comments addressed (Arun, Suraj)
Changes in v7:
- Review comments addressed (Jani, Suraj)
- Rebased on AMD series for core API's
- Some fixes
Changes in v6:
- Remove Multi Segmented LUT implementations. This will be taken up
as a separate series.
- Code Refactoring and review comments addressed (Jani, Suraj, Simon)
- Propogate Plane Color changes to crtc state
- Fix DSB programming for Luts
- Add 3D Lut support
- Plane color callbacks updated to TGL+
- Rebase on AMD's Color series v12 version
Changes in v5:
- Exposing CTM as 3x4 instead of 3x3 using post offsets.
- Exposing single segmented 1D LUT color op along with multi
segmented lut in 2 different color pipelines
- Add helper to extract LUT data from 32 bit samples
- Enable uapi to hardware state copy in driver
- Add DSB support to program color Luts
- Fix some miscellaneous issues
Changes in v4:
- Rebase
Changes in v3:
- Rebase on latest plane color pipeline series (v7) from AMD
- Update documentation for 3x3 CTM colorop (Dmitry)
- Fix documentation for multi segmented 1D lut (Dmitry)
- Squash changes for 1d LUT helpers (Dmitry)
Changes in v2:
- Add documentation for hardware capability detection for segmented luts
- Add documentation for lut computation in userspace based on
hardware caps
- Update drm_color_lut_range data structure and handling
- Enhance the structure to avoid ambiguity and cater to varying
hardware implementations of 1D Lut blocks
- Replace drm_color_lut_ext with drm_color_lut32
- Change namespace for drm_color_lut_range flags (Sebastien)
- Program super fine post csc gamma lut segment for Intel hardware
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Pekka Paalanen <pekka.paalanen@collabora.com>
Cc: Simon Ser <contact@emersion.fr>
Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Melissa Wen <mwen@igalia.com>
Cc: Jonas Ådahl <jadahl@redhat.com>
Cc: Sebastian Wick <sebastian.wick@redhat.com>
Cc: Joshua Ashton <joshua@froggi.es>
Cc: Michel Dänzer <mdaenzer@redhat.com>
Cc: Xaver Hugl <xaver.hugl@gmail.com>
Cc: Victoria Brekenfeld <victoria@system76.com>
Cc: Sima <daniel@ffwll.ch>
Cc: Liviu Dudau <Liviu.Dudau@arm.com>
Cc: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Cc: Swati Sharma <swati2.sharma@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Suraj Kandpal <suraj.kandpal@intel.com>
Chaitanya Kumar Borah (8):
drm/i915/display: Add identifiers for driver specific blocks
drm/i915: Add intel_color_op
drm/i915/color: Add helper to create intel colorop
drm/i915/color: Create a transfer function color pipeline
drm/i915/color: Add framework to program CSC
drm/i915/color: Preserve sign bit when int_bits is Zero
drm/i915/color: Add registers for 3D LUT
drm/i915/color: Add 3D LUT to color pipeline
Uma Shankar (7):
drm/i915/color: Add plane CTM callback for D12 and beyond
drm/i915: Add register definitions for Plane Degamma
drm/i915: Add register definitions for Plane Post CSC
drm/i915/color: Add framework to program PRE/POST CSC LUT
drm/i915/color: Program Pre-CSC registers
drm/i915/color: Program Plane Post CSC Registers
drm/i915/color: Enable Plane Color Pipelines
drivers/gpu/drm/i915/Makefile | 2 +
drivers/gpu/drm/i915/display/intel_color.c | 335 ++++++++++++++++++
drivers/gpu/drm/i915/display/intel_color.h | 8 +-
.../drm/i915/display/intel_color_pipeline.c | 99 ++++++
.../drm/i915/display/intel_color_pipeline.h | 14 +
.../gpu/drm/i915/display/intel_color_regs.h | 29 ++
drivers/gpu/drm/i915/display/intel_colorop.c | 35 ++
drivers/gpu/drm/i915/display/intel_colorop.h | 15 +
drivers/gpu/drm/i915/display/intel_display.c | 5 +-
.../drm/i915/display/intel_display_limits.h | 9 +
.../drm/i915/display/intel_display_types.h | 9 +
drivers/gpu/drm/i915/display/intel_plane.c | 55 +++
.../drm/i915/display/skl_universal_plane.c | 21 ++
.../i915/display/skl_universal_plane_regs.h | 115 ++++++
drivers/gpu/drm/xe/Makefile | 2 +
15 files changed, 751 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_color_pipeline.c
create mode 100644 drivers/gpu/drm/i915/display/intel_color_pipeline.h
create mode 100644 drivers/gpu/drm/i915/display/intel_colorop.c
create mode 100644 drivers/gpu/drm/i915/display/intel_colorop.h
--
2.50.1
^ permalink raw reply [flat|nested] 29+ messages in thread
* [v8 01/15] drm/i915/display: Add identifiers for driver specific blocks
2025-12-03 8:51 [v8 00/15] Plane Color Pipeline support for Intel platforms Uma Shankar
2025-12-03 8:47 ` ✗ CI.checkpatch: warning for Plane Color Pipeline support for Intel platforms (rev7) Patchwork
2025-12-03 8:48 ` ✓ CI.KUnit: success " Patchwork
@ 2025-12-03 8:51 ` Uma Shankar
2025-12-03 8:51 ` [v8 02/15] drm/i915: Add intel_color_op Uma Shankar
` (14 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: Uma Shankar @ 2025-12-03 8:51 UTC (permalink / raw)
To: intel-gfx, intel-xe, dri-devel
Cc: chaitanya.kumar.borah, ville.syrjala, pekka.paalanen, contact,
harry.wentland, mwen, jadahl, sebastian.wick, swati2.sharma,
alex.hung, jani.nikula, suraj.kandpal, Uma Shankar
From: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Add macros to identify intel specific color blocks. It will help
in mapping drm_color_ops to intel color HW blocks
v2:- Prefix enums with INTEL_* (Jani, Suraj)
- Remove unnecessary comments (Jani)
- Commit message improvements (Suraj)
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_limits.h | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_limits.h b/drivers/gpu/drm/i915/display/intel_display_limits.h
index f0fa27e365ab..55fd574ba313 100644
--- a/drivers/gpu/drm/i915/display/intel_display_limits.h
+++ b/drivers/gpu/drm/i915/display/intel_display_limits.h
@@ -138,4 +138,12 @@ enum hpd_pin {
HPD_NUM_PINS
};
+enum intel_color_block {
+ INTEL_PLANE_CB_PRE_CSC_LUT,
+ INTEL_PLANE_CB_CSC,
+ INTEL_PLANE_CB_POST_CSC_LUT,
+
+ INTEL_CB_MAX
+};
+
#endif /* __INTEL_DISPLAY_LIMITS_H__ */
--
2.50.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [v8 02/15] drm/i915: Add intel_color_op
2025-12-03 8:51 [v8 00/15] Plane Color Pipeline support for Intel platforms Uma Shankar
` (2 preceding siblings ...)
2025-12-03 8:51 ` [v8 01/15] drm/i915/display: Add identifiers for driver specific blocks Uma Shankar
@ 2025-12-03 8:51 ` Uma Shankar
2025-12-03 8:51 ` [v8 03/15] drm/i915/color: Add helper to create intel colorop Uma Shankar
` (13 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: Uma Shankar @ 2025-12-03 8:51 UTC (permalink / raw)
To: intel-gfx, intel-xe, dri-devel
Cc: chaitanya.kumar.borah, ville.syrjala, pekka.paalanen, contact,
harry.wentland, mwen, jadahl, sebastian.wick, swati2.sharma,
alex.hung, jani.nikula, suraj.kandpal, Uma Shankar
From: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Add data structure to store intel specific details of colorop
v2:
- Remove dead code
- Convert macro to function (Jani)
- Remove colorop state as it is not being used
- Refactor to separate file
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_colorop.c | 10 ++++++++++
drivers/gpu/drm/i915/display/intel_colorop.h | 13 +++++++++++++
drivers/gpu/drm/i915/display/intel_display_types.h | 5 +++++
drivers/gpu/drm/xe/Makefile | 1 +
5 files changed, 30 insertions(+)
create mode 100644 drivers/gpu/drm/i915/display/intel_colorop.c
create mode 100644 drivers/gpu/drm/i915/display/intel_colorop.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index b2250432ae98..7c19d5345d88 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -240,6 +240,7 @@ i915-y += \
display/intel_cdclk.o \
display/intel_cmtg.o \
display/intel_color.o \
+ display/intel_colorop.o \
display/intel_combo_phy.o \
display/intel_connector.o \
display/intel_crtc.o \
diff --git a/drivers/gpu/drm/i915/display/intel_colorop.c b/drivers/gpu/drm/i915/display/intel_colorop.c
new file mode 100644
index 000000000000..eaab50d2d126
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_colorop.c
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+#include "intel_colorop.h"
+
+struct intel_colorop *to_intel_colorop(struct drm_colorop *colorop)
+{
+ return container_of(colorop, struct intel_colorop, base);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_colorop.h b/drivers/gpu/drm/i915/display/intel_colorop.h
new file mode 100644
index 000000000000..23a29a565949
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_colorop.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef __INTEL_COLOROP_H__
+#define __INTEL_COLOROP_H__
+
+#include "intel_display_types.h"
+
+struct intel_colorop *to_intel_colorop(struct drm_colorop *colorop);
+
+#endif /* __INTEL_COLOROP_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index f8f7bc956214..764053a59270 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1986,6 +1986,11 @@ struct intel_dp_mst_encoder {
struct intel_connector *connector;
};
+struct intel_colorop {
+ struct drm_colorop base;
+ enum intel_color_block id;
+};
+
static inline struct intel_encoder *
intel_attached_encoder(struct intel_connector *connector)
{
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index a7e13a676f7d..3420725c4ba8 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -234,6 +234,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
i915-display/intel_cdclk.o \
i915-display/intel_cmtg.o \
i915-display/intel_color.o \
+ i915-display/intel_colorop.o \
i915-display/intel_combo_phy.o \
i915-display/intel_connector.o \
i915-display/intel_crtc.o \
--
2.50.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [v8 03/15] drm/i915/color: Add helper to create intel colorop
2025-12-03 8:51 [v8 00/15] Plane Color Pipeline support for Intel platforms Uma Shankar
` (3 preceding siblings ...)
2025-12-03 8:51 ` [v8 02/15] drm/i915: Add intel_color_op Uma Shankar
@ 2025-12-03 8:51 ` Uma Shankar
2025-12-03 8:52 ` [v8 04/15] drm/i915/color: Create a transfer function color pipeline Uma Shankar
` (12 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: Uma Shankar @ 2025-12-03 8:51 UTC (permalink / raw)
To: intel-gfx, intel-xe, dri-devel
Cc: chaitanya.kumar.borah, ville.syrjala, pekka.paalanen, contact,
harry.wentland, mwen, jadahl, sebastian.wick, swati2.sharma,
alex.hung, jani.nikula, suraj.kandpal, Uma Shankar
From: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Add intel colorop create helper
v2:
- Make function names consistent (Jani)
- Remove redundant code related to colorop state
- Refactor code to separate files
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_colorop.c | 25 ++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_colorop.h | 2 ++
2 files changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_colorop.c b/drivers/gpu/drm/i915/display/intel_colorop.c
index eaab50d2d126..f2fc0d8780ce 100644
--- a/drivers/gpu/drm/i915/display/intel_colorop.c
+++ b/drivers/gpu/drm/i915/display/intel_colorop.c
@@ -8,3 +8,28 @@ struct intel_colorop *to_intel_colorop(struct drm_colorop *colorop)
{
return container_of(colorop, struct intel_colorop, base);
}
+
+struct intel_colorop *intel_colorop_alloc(void)
+{
+ struct intel_colorop *colorop;
+
+ colorop = kzalloc(sizeof(*colorop), GFP_KERNEL);
+ if (!colorop)
+ return ERR_PTR(-ENOMEM);
+
+ return colorop;
+}
+
+struct intel_colorop *intel_colorop_create(enum intel_color_block id)
+{
+ struct intel_colorop *colorop;
+
+ colorop = intel_colorop_alloc();
+
+ if (IS_ERR(colorop))
+ return colorop;
+
+ colorop->id = id;
+
+ return colorop;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_colorop.h b/drivers/gpu/drm/i915/display/intel_colorop.h
index 23a29a565949..21d58eb9f3d0 100644
--- a/drivers/gpu/drm/i915/display/intel_colorop.h
+++ b/drivers/gpu/drm/i915/display/intel_colorop.h
@@ -9,5 +9,7 @@
#include "intel_display_types.h"
struct intel_colorop *to_intel_colorop(struct drm_colorop *colorop);
+struct intel_colorop *intel_colorop_alloc(void);
+struct intel_colorop *intel_colorop_create(enum intel_color_block id);
#endif /* __INTEL_COLOROP_H__ */
--
2.50.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [v8 04/15] drm/i915/color: Create a transfer function color pipeline
2025-12-03 8:51 [v8 00/15] Plane Color Pipeline support for Intel platforms Uma Shankar
` (4 preceding siblings ...)
2025-12-03 8:51 ` [v8 03/15] drm/i915/color: Add helper to create intel colorop Uma Shankar
@ 2025-12-03 8:52 ` Uma Shankar
2025-12-03 8:52 ` [v8 05/15] drm/i915/color: Add framework to program CSC Uma Shankar
` (11 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: Uma Shankar @ 2025-12-03 8:52 UTC (permalink / raw)
To: intel-gfx, intel-xe, dri-devel
Cc: chaitanya.kumar.borah, ville.syrjala, pekka.paalanen, contact,
harry.wentland, mwen, jadahl, sebastian.wick, swati2.sharma,
alex.hung, jani.nikula, suraj.kandpal, Uma Shankar
From: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Add a color pipeline with three colorops in the sequence
1D LUT - 3x4 CTM - 1D LUT
This pipeline can be used to do any color space conversion or HDR
tone mapping
v2: Change namespace to drm_plane_colorop*
v3: Use simpler/pre-existing colorops for first iteration
v4:
- s/*_tf_*/*_color_* (Jani)
- Refactor to separate files (Jani)
- Add missing space in comment (Suraj)
- Consolidate patch that adds/attaches pipeline property
v5:
- Limit MAX_COLOR_PIPELINES to 2.(Suraj)
Increase it as and when we add more pipelines.
- Remove redundant initialization code (Suraj)
v6:
- Use drm_plane_create_color_pipeline_property() (Arun)
Now MAX_COLOR_PIPELINES is 1
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
.../drm/i915/display/intel_color_pipeline.c | 80 +++++++++++++++++++
.../drm/i915/display/intel_color_pipeline.h | 13 +++
drivers/gpu/drm/xe/Makefile | 1 +
4 files changed, 95 insertions(+)
create mode 100644 drivers/gpu/drm/i915/display/intel_color_pipeline.c
create mode 100644 drivers/gpu/drm/i915/display/intel_color_pipeline.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 7c19d5345d88..ca5c69d1cb08 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -241,6 +241,7 @@ i915-y += \
display/intel_cmtg.o \
display/intel_color.o \
display/intel_colorop.o \
+ display/intel_color_pipeline.o \
display/intel_combo_phy.o \
display/intel_connector.o \
display/intel_crtc.o \
diff --git a/drivers/gpu/drm/i915/display/intel_color_pipeline.c b/drivers/gpu/drm/i915/display/intel_color_pipeline.c
new file mode 100644
index 000000000000..489d470cd011
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_color_pipeline.c
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+#include "intel_colorop.h"
+#include "intel_color_pipeline.h"
+#include "intel_de.h"
+#include "intel_display_types.h"
+#include "skl_universal_plane.h"
+
+#define MAX_COLOR_PIPELINES 1
+#define PLANE_DEGAMMA_SIZE 128
+#define PLANE_GAMMA_SIZE 32
+
+static
+int _intel_color_pipeline_plane_init(struct drm_plane *plane, struct drm_prop_enum_list *list)
+{
+ struct intel_colorop *colorop;
+ struct drm_device *dev = plane->dev;
+ int ret;
+ struct drm_colorop *prev_op;
+
+ colorop = intel_colorop_create(INTEL_PLANE_CB_PRE_CSC_LUT);
+
+ ret = drm_plane_colorop_curve_1d_lut_init(dev, &colorop->base, plane,
+ PLANE_DEGAMMA_SIZE,
+ DRM_COLOROP_LUT1D_INTERPOLATION_LINEAR,
+ DRM_COLOROP_FLAG_ALLOW_BYPASS);
+
+ if (ret)
+ return ret;
+
+ list->type = colorop->base.base.id;
+ list->name = kasprintf(GFP_KERNEL, "Color Pipeline %d", colorop->base.base.id);
+
+ /* TODO: handle failures and clean up */
+ prev_op = &colorop->base;
+
+ colorop = intel_colorop_create(INTEL_PLANE_CB_CSC);
+ ret = drm_plane_colorop_ctm_3x4_init(dev, &colorop->base, plane,
+ DRM_COLOROP_FLAG_ALLOW_BYPASS);
+ if (ret)
+ return ret;
+
+ drm_colorop_set_next_property(prev_op, &colorop->base);
+ prev_op = &colorop->base;
+
+ colorop = intel_colorop_create(INTEL_PLANE_CB_POST_CSC_LUT);
+ ret = drm_plane_colorop_curve_1d_lut_init(dev, &colorop->base, plane,
+ PLANE_GAMMA_SIZE,
+ DRM_COLOROP_LUT1D_INTERPOLATION_LINEAR,
+ DRM_COLOROP_FLAG_ALLOW_BYPASS);
+ if (ret)
+ return ret;
+
+ drm_colorop_set_next_property(prev_op, &colorop->base);
+
+ return 0;
+}
+
+int intel_color_pipeline_plane_init(struct drm_plane *plane)
+{
+ struct drm_device *dev = plane->dev;
+ struct intel_display *display = to_intel_display(dev);
+ struct drm_prop_enum_list pipelines[MAX_COLOR_PIPELINES];
+ int len = 0;
+ int ret;
+
+ /* Currently expose pipeline only for HDR planes */
+ if (!icl_is_hdr_plane(display, to_intel_plane(plane)->id))
+ return 0;
+
+ /* Add pipeline consisting of transfer functions */
+ ret = _intel_color_pipeline_plane_init(plane, &pipelines[len]);
+ if (ret)
+ return ret;
+ len++;
+
+ return drm_plane_create_color_pipeline_property(plane, pipelines, len);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_color_pipeline.h b/drivers/gpu/drm/i915/display/intel_color_pipeline.h
new file mode 100644
index 000000000000..7f1d32bc9202
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_color_pipeline.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef __INTEL_COLOR_PIPELINE_H__
+#define __INTEL_COLOR_PIPELINE_H__
+
+struct drm_plane;
+
+int intel_color_pipeline_plane_init(struct drm_plane *plane);
+
+#endif /* __INTEL_COLOR_PIPELINE_H__ */
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 3420725c4ba8..89f922d745ba 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -235,6 +235,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
i915-display/intel_cmtg.o \
i915-display/intel_color.o \
i915-display/intel_colorop.o \
+ i915-display/intel_color_pipeline.o \
i915-display/intel_combo_phy.o \
i915-display/intel_connector.o \
i915-display/intel_crtc.o \
--
2.50.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [v8 05/15] drm/i915/color: Add framework to program CSC
2025-12-03 8:51 [v8 00/15] Plane Color Pipeline support for Intel platforms Uma Shankar
` (5 preceding siblings ...)
2025-12-03 8:52 ` [v8 04/15] drm/i915/color: Create a transfer function color pipeline Uma Shankar
@ 2025-12-03 8:52 ` Uma Shankar
2025-12-03 8:52 ` [v8 06/15] drm/i915/color: Preserve sign bit when int_bits is Zero Uma Shankar
` (10 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: Uma Shankar @ 2025-12-03 8:52 UTC (permalink / raw)
To: intel-gfx, intel-xe, dri-devel
Cc: chaitanya.kumar.borah, ville.syrjala, pekka.paalanen, contact,
harry.wentland, mwen, jadahl, sebastian.wick, swati2.sharma,
alex.hung, jani.nikula, suraj.kandpal, Uma Shankar
From: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Add framework to program CSC. It enables copying of matrix from UAPI
to intel plane state. Also add helper functions which will eventually
program values to hardware.
Add a crtc state variable to track plane color change.
v2:
- Add crtc_state->plane_color_changed
- Improve comments (Suraj)
- s/intel_plane_*_color/intel_plane_color_* (Suraj)
v3:
- align parameters with open braces (Suraj)
- Improve commit message (Suraj)
v4:
- Re-arrange variable declaration (Suraj)
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 21 ++++++++
drivers/gpu/drm/i915/display/intel_color.h | 4 +-
.../drm/i915/display/intel_display_types.h | 4 ++
drivers/gpu/drm/i915/display/intel_plane.c | 49 +++++++++++++++++++
4 files changed, 77 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index a217a67ceb43..33fe5c9b4663 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -87,6 +87,10 @@ struct intel_color_funcs {
* Read config other than LUTs and CSCs, before them. Optional.
*/
void (*get_config)(struct intel_crtc_state *crtc_state);
+
+ /* Plane CSC*/
+ void (*load_plane_csc_matrix)(struct intel_dsb *dsb,
+ const struct intel_plane_state *plane_state);
};
#define CTM_COEFF_SIGN (1ULL << 63)
@@ -3963,6 +3967,23 @@ static const struct intel_color_funcs ilk_color_funcs = {
.get_config = ilk_get_config,
};
+static void
+intel_color_load_plane_csc_matrix(struct intel_dsb *dsb,
+ const struct intel_plane_state *plane_state)
+{
+ struct intel_display *display = to_intel_display(plane_state);
+
+ if (display->funcs.color->load_plane_csc_matrix)
+ display->funcs.color->load_plane_csc_matrix(dsb, plane_state);
+}
+
+void intel_color_plane_program_pipeline(struct intel_dsb *dsb,
+ const struct intel_plane_state *plane_state)
+{
+ if (plane_state->hw.ctm)
+ intel_color_load_plane_csc_matrix(dsb, plane_state);
+}
+
void intel_color_crtc_init(struct intel_crtc *crtc)
{
struct intel_display *display = to_intel_display(crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_color.h b/drivers/gpu/drm/i915/display/intel_color.h
index bf7a12ce9df0..8051c827a1d8 100644
--- a/drivers/gpu/drm/i915/display/intel_color.h
+++ b/drivers/gpu/drm/i915/display/intel_color.h
@@ -13,6 +13,7 @@ struct intel_crtc_state;
struct intel_crtc;
struct intel_display;
struct intel_dsb;
+struct intel_plane_state;
struct drm_property_blob;
void intel_color_init_hooks(struct intel_display *display);
@@ -40,5 +41,6 @@ bool intel_color_lut_equal(const struct intel_crtc_state *crtc_state,
const struct drm_property_blob *blob2,
bool is_pre_csc_lut);
void intel_color_assert_luts(const struct intel_crtc_state *crtc_state);
-
+void intel_color_plane_program_pipeline(struct intel_dsb *dsb,
+ const struct intel_plane_state *plane_state);
#endif /* __INTEL_COLOR_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 764053a59270..0f70240970c7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -646,6 +646,7 @@ struct intel_plane_state {
enum drm_color_encoding color_encoding;
enum drm_color_range color_range;
enum drm_scaling_filter scaling_filter;
+ struct drm_property_blob *ctm;
} hw;
struct i915_vma *ggtt_vma;
@@ -1391,6 +1392,9 @@ struct intel_crtc_state {
u8 silence_period_sym_clocks;
u8 lfps_half_cycle_num_of_syms;
} alpm_state;
+
+ /* to track changes in plane color blocks */
+ bool plane_color_changed;
};
enum intel_pipe_crc_source {
diff --git a/drivers/gpu/drm/i915/display/intel_plane.c b/drivers/gpu/drm/i915/display/intel_plane.c
index 7b7619d59251..01fd6ccc2aae 100644
--- a/drivers/gpu/drm/i915/display/intel_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_plane.c
@@ -48,6 +48,7 @@
#include "i9xx_plane_regs.h"
#include "intel_cdclk.h"
#include "intel_cursor.h"
+#include "intel_colorop.h"
#include "intel_display_rps.h"
#include "intel_display_trace.h"
#include "intel_display_types.h"
@@ -340,6 +341,52 @@ intel_plane_copy_uapi_plane_damage(struct intel_plane_state *new_plane_state,
*damage = drm_plane_state_src(&new_uapi_plane_state->uapi);
}
+static bool
+intel_plane_colorop_replace_blob(struct intel_plane_state *plane_state,
+ struct intel_colorop *intel_colorop,
+ struct drm_property_blob *blob)
+{
+ if (intel_colorop->id == INTEL_PLANE_CB_CSC)
+ return drm_property_replace_blob(&plane_state->hw.ctm, blob);
+
+ return false;
+}
+
+static void
+intel_plane_color_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
+ const struct intel_plane_state *from_plane_state,
+ struct intel_crtc *crtc)
+{
+ struct drm_colorop *iter_colorop, *colorop;
+ struct drm_colorop_state *new_colorop_state;
+ struct drm_atomic_state *state = plane_state->uapi.state;
+ struct intel_colorop *intel_colorop;
+ struct drm_property_blob *blob;
+ struct intel_atomic_state *intel_atomic_state = to_intel_atomic_state(state);
+ struct intel_crtc_state *new_crtc_state = intel_atomic_state ?
+ intel_atomic_get_new_crtc_state(intel_atomic_state, crtc) : NULL;
+ bool changed = false;
+ int i = 0;
+
+ iter_colorop = plane_state->uapi.color_pipeline;
+
+ while (iter_colorop) {
+ for_each_new_colorop_in_state(state, colorop, new_colorop_state, i) {
+ if (new_colorop_state->colorop == iter_colorop) {
+ blob = new_colorop_state->bypass ? NULL : new_colorop_state->data;
+ intel_colorop = to_intel_colorop(colorop);
+ changed |= intel_plane_colorop_replace_blob(plane_state,
+ intel_colorop,
+ blob);
+ }
+ }
+ iter_colorop = iter_colorop->next;
+ }
+
+ if (new_crtc_state && changed)
+ new_crtc_state->plane_color_changed = true;
+}
+
void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
const struct intel_plane_state *from_plane_state,
struct intel_crtc *crtc)
@@ -368,6 +415,8 @@ void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
plane_state->uapi.src = drm_plane_state_src(&from_plane_state->uapi);
plane_state->uapi.dst = drm_plane_state_dest(&from_plane_state->uapi);
+
+ intel_plane_color_copy_uapi_to_hw_state(plane_state, from_plane_state, crtc);
}
void intel_plane_copy_hw_state(struct intel_plane_state *plane_state,
--
2.50.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [v8 06/15] drm/i915/color: Preserve sign bit when int_bits is Zero
2025-12-03 8:51 [v8 00/15] Plane Color Pipeline support for Intel platforms Uma Shankar
` (6 preceding siblings ...)
2025-12-03 8:52 ` [v8 05/15] drm/i915/color: Add framework to program CSC Uma Shankar
@ 2025-12-03 8:52 ` Uma Shankar
2025-12-03 8:52 ` [v8 07/15] drm/i915/color: Add plane CTM callback for D12 and beyond Uma Shankar
` (9 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: Uma Shankar @ 2025-12-03 8:52 UTC (permalink / raw)
To: intel-gfx, intel-xe, dri-devel
Cc: chaitanya.kumar.borah, ville.syrjala, pekka.paalanen, contact,
harry.wentland, mwen, jadahl, sebastian.wick, swati2.sharma,
alex.hung, jani.nikula, suraj.kandpal, Uma Shankar
From: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
When int_bits == 0, we lose the sign bit when we do the range check
and apply the mask.
Fix this by ensuring a minimum of one integer bit, which guarantees space
for the sign bit in fully fractional representations (e.g. S0.12)
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 33fe5c9b4663..81b87fed8878 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -613,6 +613,8 @@ static u16 ctm_to_twos_complement(u64 coeff, int int_bits, int frac_bits)
if (CTM_COEFF_NEGATIVE(coeff))
c = -c;
+ int_bits = max(int_bits, 1);
+
c = clamp(c, -(s64)BIT(int_bits + frac_bits - 1),
(s64)(BIT(int_bits + frac_bits - 1) - 1));
--
2.50.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [v8 07/15] drm/i915/color: Add plane CTM callback for D12 and beyond
2025-12-03 8:51 [v8 00/15] Plane Color Pipeline support for Intel platforms Uma Shankar
` (7 preceding siblings ...)
2025-12-03 8:52 ` [v8 06/15] drm/i915/color: Preserve sign bit when int_bits is Zero Uma Shankar
@ 2025-12-03 8:52 ` Uma Shankar
2025-12-03 8:52 ` [v8 08/15] drm/i915: Add register definitions for Plane Degamma Uma Shankar
` (8 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: Uma Shankar @ 2025-12-03 8:52 UTC (permalink / raw)
To: intel-gfx, intel-xe, dri-devel
Cc: chaitanya.kumar.borah, ville.syrjala, pekka.paalanen, contact,
harry.wentland, mwen, jadahl, sebastian.wick, swati2.sharma,
alex.hung, jani.nikula, suraj.kandpal, Uma Shankar
Add callback for setting CTM block in platforms D12 and beyond
v2:
- Add dsb support
- Pass plane_state as we are now doing a uapi to hw state copy
- Add support for 3x4 matrix
v3:
- Add relevant header file
- Fix typo (Suraj)
- Add callback to TGL+ (Suraj)
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 98 ++++++++++++++++++++++
1 file changed, 98 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 81b87fed8878..2f8e985d51e5 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -32,6 +32,8 @@
#include "intel_display_utils.h"
#include "intel_dsb.h"
#include "intel_vrr.h"
+#include "skl_universal_plane.h"
+#include "skl_universal_plane_regs.h"
struct intel_color_funcs {
int (*color_check)(struct intel_atomic_state *state,
@@ -3842,6 +3844,101 @@ static void icl_read_luts(struct intel_crtc_state *crtc_state)
}
}
+static void
+xelpd_load_plane_csc_matrix(struct intel_dsb *dsb,
+ const struct intel_plane_state *plane_state)
+{
+ struct intel_display *display = to_intel_display(plane_state);
+ const struct drm_plane_state *state = &plane_state->uapi;
+ enum pipe pipe = to_intel_plane(state->plane)->pipe;
+ enum plane_id plane = to_intel_plane(state->plane)->id;
+ const struct drm_property_blob *blob = plane_state->hw.ctm;
+ struct drm_color_ctm_3x4 *ctm;
+ const u64 *input;
+ u16 coeffs[9] = {};
+ int i, j;
+
+ if (!icl_is_hdr_plane(display, plane) || !blob)
+ return;
+
+ ctm = blob->data;
+ input = ctm->matrix;
+
+ /*
+ * Convert fixed point S31.32 input to format supported by the
+ * hardware.
+ */
+ for (i = 0, j = 0; i < ARRAY_SIZE(coeffs); i++) {
+ u64 abs_coeff = ((1ULL << 63) - 1) & input[j];
+
+ /*
+ * Clamp input value to min/max supported by
+ * hardware.
+ */
+ abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_4_0 - 1);
+
+ /* sign bit */
+ if (CTM_COEFF_NEGATIVE(input[j]))
+ coeffs[i] |= 1 << 15;
+
+ if (abs_coeff < CTM_COEFF_0_125)
+ coeffs[i] |= (3 << 12) |
+ ILK_CSC_COEFF_FP(abs_coeff, 12);
+ else if (abs_coeff < CTM_COEFF_0_25)
+ coeffs[i] |= (2 << 12) |
+ ILK_CSC_COEFF_FP(abs_coeff, 11);
+ else if (abs_coeff < CTM_COEFF_0_5)
+ coeffs[i] |= (1 << 12) |
+ ILK_CSC_COEFF_FP(abs_coeff, 10);
+ else if (abs_coeff < CTM_COEFF_1_0)
+ coeffs[i] |= ILK_CSC_COEFF_FP(abs_coeff, 9);
+ else if (abs_coeff < CTM_COEFF_2_0)
+ coeffs[i] |= (7 << 12) |
+ ILK_CSC_COEFF_FP(abs_coeff, 8);
+ else
+ coeffs[i] |= (6 << 12) |
+ ILK_CSC_COEFF_FP(abs_coeff, 7);
+
+ /* Skip postoffs */
+ if (!((j + 2) % 4))
+ j += 2;
+ else
+ j++;
+ }
+
+ intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane, 0),
+ coeffs[0] << 16 | coeffs[1]);
+ intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane, 1),
+ coeffs[2] << 16);
+
+ intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane, 2),
+ coeffs[3] << 16 | coeffs[4]);
+ intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane, 3),
+ coeffs[5] << 16);
+
+ intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane, 4),
+ coeffs[6] << 16 | coeffs[7]);
+ intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane, 5),
+ coeffs[8] << 16);
+
+ intel_de_write_dsb(display, dsb, PLANE_CSC_PREOFF(pipe, plane, 0), 0);
+ intel_de_write_dsb(display, dsb, PLANE_CSC_PREOFF(pipe, plane, 1), 0);
+ intel_de_write_dsb(display, dsb, PLANE_CSC_PREOFF(pipe, plane, 2), 0);
+
+ /*
+ * Conversion from S31.32 to S0.12. BIT[12] is the signed bit
+ */
+ intel_de_write_dsb(display, dsb,
+ PLANE_CSC_POSTOFF(pipe, plane, 0),
+ ctm_to_twos_complement(input[3], 0, 12));
+ intel_de_write_dsb(display, dsb,
+ PLANE_CSC_POSTOFF(pipe, plane, 1),
+ ctm_to_twos_complement(input[7], 0, 12));
+ intel_de_write_dsb(display, dsb,
+ PLANE_CSC_POSTOFF(pipe, plane, 2),
+ ctm_to_twos_complement(input[11], 0, 12));
+}
+
static const struct intel_color_funcs chv_color_funcs = {
.color_check = chv_color_check,
.color_commit_arm = i9xx_color_commit_arm,
@@ -3889,6 +3986,7 @@ static const struct intel_color_funcs tgl_color_funcs = {
.lut_equal = icl_lut_equal,
.read_csc = icl_read_csc,
.get_config = skl_get_config,
+ .load_plane_csc_matrix = xelpd_load_plane_csc_matrix,
};
static const struct intel_color_funcs icl_color_funcs = {
--
2.50.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [v8 08/15] drm/i915: Add register definitions for Plane Degamma
2025-12-03 8:51 [v8 00/15] Plane Color Pipeline support for Intel platforms Uma Shankar
` (8 preceding siblings ...)
2025-12-03 8:52 ` [v8 07/15] drm/i915/color: Add plane CTM callback for D12 and beyond Uma Shankar
@ 2025-12-03 8:52 ` Uma Shankar
2025-12-03 8:52 ` [v8 09/15] drm/i915: Add register definitions for Plane Post CSC Uma Shankar
` (7 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: Uma Shankar @ 2025-12-03 8:52 UTC (permalink / raw)
To: intel-gfx, intel-xe, dri-devel
Cc: chaitanya.kumar.borah, ville.syrjala, pekka.paalanen, contact,
harry.wentland, mwen, jadahl, sebastian.wick, swati2.sharma,
alex.hung, jani.nikula, suraj.kandpal, Uma Shankar
Add macros to define Plane Degamma registers
v2:
- Add BSpec links (Suraj)
v3:
- Add Bspec links in trailer (Suraj)
- Fix checkpatch issues (Suraj)
BSpec: 50411, 50412, 50413, 50414
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
---
.../i915/display/skl_universal_plane_regs.h | 48 +++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
index 6f815b231340..1e5d7ef37f1c 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
@@ -254,6 +254,7 @@
#define PLANE_COLOR_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-ICL */
#define PLANE_COLOR_PLANE_CSC_ENABLE REG_BIT(21) /* ICL+ */
#define PLANE_COLOR_INPUT_CSC_ENABLE REG_BIT(20) /* ICL+ */
+#define PLANE_COLOR_PRE_CSC_GAMMA_ENABLE REG_BIT(14)
#define PLANE_COLOR_CSC_MODE_MASK REG_GENMASK(19, 17)
#define PLANE_COLOR_CSC_MODE_BYPASS REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 0)
#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 1)
@@ -290,6 +291,53 @@
_PLANE_INPUT_CSC_POSTOFF_HI_1_A, _PLANE_INPUT_CSC_POSTOFF_HI_1_B, \
_PLANE_INPUT_CSC_POSTOFF_HI_2_A, _PLANE_INPUT_CSC_POSTOFF_HI_2_B)
+#define _MMIO_PLANE_GAMC(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) * 4)
+
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_A 0x701d0
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_B 0x711d0
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_A 0x702d0
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_B 0x712d0
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_A, \
+ _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_B)
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_2(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_A, \
+ _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_B)
+#define PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_INDEX_ENH_1(pipe), \
+ _PLANE_PRE_CSC_GAMC_INDEX_ENH_2(pipe))
+#define PLANE_PAL_PREC_AUTO_INCREMENT REG_BIT(10)
+
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_1_A 0x701d4
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_1_B 0x711d4
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_2_A 0x702d4
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_2_B 0x712d4
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_1(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_DATA_ENH_1_A, \
+ _PLANE_PRE_CSC_GAMC_DATA_ENH_1_B)
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_2(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_DATA_ENH_2_A, \
+ _PLANE_PRE_CSC_GAMC_DATA_ENH_2_B)
+#define PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_DATA_ENH_1(pipe), \
+ _PLANE_PRE_CSC_GAMC_DATA_ENH_2(pipe))
+
+#define _PLANE_PRE_CSC_GAMC_INDEX_1_A 0x704d0
+#define _PLANE_PRE_CSC_GAMC_INDEX_1_B 0x714d0
+#define _PLANE_PRE_CSC_GAMC_INDEX_2_A 0x705d0
+#define _PLANE_PRE_CSC_GAMC_INDEX_2_B 0x715d0
+#define _PLANE_PRE_CSC_GAMC_INDEX_1(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_INDEX_1_A, \
+ _PLANE_PRE_CSC_GAMC_INDEX_1_B)
+#define _PLANE_PRE_CSC_GAMC_INDEX_2(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_INDEX_2_A, \
+ _PLANE_PRE_CSC_GAMC_INDEX_2_B)
+#define PLANE_PRE_CSC_GAMC_INDEX(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_INDEX_1(pipe), \
+ _PLANE_PRE_CSC_GAMC_INDEX_2(pipe))
+
+#define _PLANE_PRE_CSC_GAMC_DATA_1_A 0x704d4
+#define _PLANE_PRE_CSC_GAMC_DATA_1_B 0x714d4
+#define _PLANE_PRE_CSC_GAMC_DATA_2_A 0x705d4
+#define _PLANE_PRE_CSC_GAMC_DATA_2_B 0x715d4
+#define _PLANE_PRE_CSC_GAMC_DATA_1(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_DATA_1_A, \
+ _PLANE_PRE_CSC_GAMC_DATA_1_B)
+#define _PLANE_PRE_CSC_GAMC_DATA_2(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_DATA_2_A, \
+ _PLANE_PRE_CSC_GAMC_DATA_2_B)
+#define PLANE_PRE_CSC_GAMC_DATA(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_DATA_1(pipe), \
+ _PLANE_PRE_CSC_GAMC_DATA_2(pipe))
+
#define _PLANE_CSC_RY_GY_1_A 0x70210
#define _PLANE_CSC_RY_GY_2_A 0x70310
#define _PLANE_CSC_RY_GY_1_B 0x71210
--
2.50.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [v8 09/15] drm/i915: Add register definitions for Plane Post CSC
2025-12-03 8:51 [v8 00/15] Plane Color Pipeline support for Intel platforms Uma Shankar
` (9 preceding siblings ...)
2025-12-03 8:52 ` [v8 08/15] drm/i915: Add register definitions for Plane Degamma Uma Shankar
@ 2025-12-03 8:52 ` Uma Shankar
2025-12-03 8:52 ` [v8 10/15] drm/i915/color: Add framework to program PRE/POST CSC LUT Uma Shankar
` (6 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: Uma Shankar @ 2025-12-03 8:52 UTC (permalink / raw)
To: intel-gfx, intel-xe, dri-devel
Cc: chaitanya.kumar.borah, ville.syrjala, pekka.paalanen, contact,
harry.wentland, mwen, jadahl, sebastian.wick, swati2.sharma,
alex.hung, jani.nikula, suraj.kandpal, Uma Shankar
Add macros to define Plane Post CSC registers
v2:
- Add Plane Post CSC Gamma Multi Segment Enable bit
- Add BSpec entries (Suraj)
v3:
- Fix checkpatch issues (Suraj)
BSpec: 50403, 50404, 50405, 50406, 50409, 50410,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
---
.../i915/display/skl_universal_plane_regs.h | 67 +++++++++++++++++++
1 file changed, 67 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
index 1e5d7ef37f1c..6fd4da9f63cf 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
@@ -254,6 +254,7 @@
#define PLANE_COLOR_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-ICL */
#define PLANE_COLOR_PLANE_CSC_ENABLE REG_BIT(21) /* ICL+ */
#define PLANE_COLOR_INPUT_CSC_ENABLE REG_BIT(20) /* ICL+ */
+#define PLANE_COLOR_POST_CSC_GAMMA_MULTSEG_ENABLE REG_BIT(15) /* TGL+ */
#define PLANE_COLOR_PRE_CSC_GAMMA_ENABLE REG_BIT(14)
#define PLANE_COLOR_CSC_MODE_MASK REG_GENMASK(19, 17)
#define PLANE_COLOR_CSC_MODE_BYPASS REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 0)
@@ -293,6 +294,72 @@
#define _MMIO_PLANE_GAMC(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) * 4)
+#define _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1_A 0x70160
+#define _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1_B 0x71160
+#define _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2_A 0x70260
+#define _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2_B 0x71260
+#define _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1_A, \
+ _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1_B)
+#define _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2_A, \
+ _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2_B)
+#define PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1(pipe), \
+ _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2(pipe))
+
+#define _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1_A 0x70164
+#define _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1_B 0x71164
+#define _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2_A 0x70264
+#define _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2_B 0x71264
+#define _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1_A, \
+ _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1_B)
+#define _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2_A, \
+ _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2_B)
+#define PLANE_POST_CSC_GAMC_SEG0_DATA_ENH(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1(pipe), \
+ _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2(pipe))
+
+#define _PLANE_POST_CSC_GAMC_INDEX_ENH_1_A 0x701d8
+#define _PLANE_POST_CSC_GAMC_INDEX_ENH_1_B 0x711d8
+#define _PLANE_POST_CSC_GAMC_INDEX_ENH_2_A 0x702d8
+#define _PLANE_POST_CSC_GAMC_INDEX_ENH_2_B 0x712d8
+#define _PLANE_POST_CSC_GAMC_INDEX_ENH_1(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_INDEX_ENH_1_A, \
+ _PLANE_POST_CSC_GAMC_INDEX_ENH_1_B)
+#define _PLANE_POST_CSC_GAMC_INDEX_ENH_2(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_INDEX_ENH_2_A, \
+ _PLANE_POST_CSC_GAMC_INDEX_ENH_2_B)
+#define PLANE_POST_CSC_GAMC_INDEX_ENH(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_INDEX_ENH_1(pipe), \
+ _PLANE_POST_CSC_GAMC_INDEX_ENH_2(pipe))
+
+#define _PLANE_POST_CSC_GAMC_DATA_ENH_1_A 0x701dc
+#define _PLANE_POST_CSC_GAMC_DATA_ENH_1_B 0x711dc
+#define _PLANE_POST_CSC_GAMC_DATA_ENH_2_A 0x702dc
+#define _PLANE_POST_CSC_GAMC_DATA_ENH_2_B 0x712dc
+#define _PLANE_POST_CSC_GAMC_DATA_ENH_1(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_DATA_ENH_1_A, \
+ _PLANE_POST_CSC_GAMC_DATA_ENH_1_B)
+#define _PLANE_POST_CSC_GAMC_DATA_ENH_2(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_DATA_ENH_2_A, \
+ _PLANE_POST_CSC_GAMC_DATA_ENH_2_B)
+#define PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_DATA_ENH_1(pipe), \
+ _PLANE_POST_CSC_GAMC_DATA_ENH_2(pipe))
+
+#define _PLANE_POST_CSC_GAMC_INDEX_1_A 0x704d8
+#define _PLANE_POST_CSC_GAMC_INDEX_1_B 0x714d8
+#define _PLANE_POST_CSC_GAMC_INDEX_2_A 0x705d8
+#define _PLANE_POST_CSC_GAMC_INDEX_2_B 0x715d8
+#define _PLANE_POST_CSC_GAMC_INDEX_1(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_INDEX_1_A, \
+ _PLANE_POST_CSC_GAMC_INDEX_1_B)
+#define _PLANE_POST_CSC_GAMC_INDEX_2(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_INDEX_2_A, \
+ _PLANE_POST_CSC_GAMC_INDEX_2_B)
+#define PLANE_POST_CSC_GAMC_INDEX(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_INDEX_1(pipe), \
+ _PLANE_POST_CSC_GAMC_INDEX_2(pipe))
+
+#define _PLANE_POST_CSC_GAMC_DATA_1_A 0x704dc
+#define _PLANE_POST_CSC_GAMC_DATA_1_B 0x714dc
+#define _PLANE_POST_CSC_GAMC_DATA_2_A 0x705dc
+#define _PLANE_POST_CSC_GAMC_DATA_2_B 0x715dc
+#define _PLANE_POST_CSC_GAMC_DATA_1(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_DATA_1_A, \
+ _PLANE_POST_CSC_GAMC_DATA_1_B)
+#define _PLANE_POST_CSC_GAMC_DATA_2(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_DATA_2_A, \
+ _PLANE_POST_CSC_GAMC_DATA_2_B)
+#define PLANE_POST_CSC_GAMC_DATA(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_DATA_1(pipe), \
+ _PLANE_POST_CSC_GAMC_DATA_2(pipe))
+
#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_A 0x701d0
#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_B 0x711d0
#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_A 0x702d0
--
2.50.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [v8 10/15] drm/i915/color: Add framework to program PRE/POST CSC LUT
2025-12-03 8:51 [v8 00/15] Plane Color Pipeline support for Intel platforms Uma Shankar
` (10 preceding siblings ...)
2025-12-03 8:52 ` [v8 09/15] drm/i915: Add register definitions for Plane Post CSC Uma Shankar
@ 2025-12-03 8:52 ` Uma Shankar
2025-12-03 8:52 ` [v8 11/15] drm/i915/color: Program Pre-CSC registers Uma Shankar
` (5 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: Uma Shankar @ 2025-12-03 8:52 UTC (permalink / raw)
To: intel-gfx, intel-xe, dri-devel
Cc: chaitanya.kumar.borah, ville.syrjala, pekka.paalanen, contact,
harry.wentland, mwen, jadahl, sebastian.wick, swati2.sharma,
alex.hung, jani.nikula, suraj.kandpal, Uma Shankar
Add framework that will help in loading LUT to Pre/Post CSC color
blocks.
v2: Add dsb support
v3: Align enum names
v4: Propagate change in lut data to crtc_state
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 16 ++++++++++++++++
.../gpu/drm/i915/display/intel_display_types.h | 2 +-
drivers/gpu/drm/i915/display/intel_plane.c | 4 ++++
3 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 2f8e985d51e5..4ca359d68730 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -93,6 +93,10 @@ struct intel_color_funcs {
/* Plane CSC*/
void (*load_plane_csc_matrix)(struct intel_dsb *dsb,
const struct intel_plane_state *plane_state);
+
+ /* Plane Pre/Post CSC */
+ void (*load_plane_luts)(struct intel_dsb *dsb,
+ const struct intel_plane_state *plane_state);
};
#define CTM_COEFF_SIGN (1ULL << 63)
@@ -4077,11 +4081,23 @@ intel_color_load_plane_csc_matrix(struct intel_dsb *dsb,
display->funcs.color->load_plane_csc_matrix(dsb, plane_state);
}
+static void
+intel_color_load_plane_luts(struct intel_dsb *dsb,
+ const struct intel_plane_state *plane_state)
+{
+ struct intel_display *display = to_intel_display(plane_state);
+
+ if (display->funcs.color->load_plane_luts)
+ display->funcs.color->load_plane_luts(dsb, plane_state);
+}
+
void intel_color_plane_program_pipeline(struct intel_dsb *dsb,
const struct intel_plane_state *plane_state)
{
if (plane_state->hw.ctm)
intel_color_load_plane_csc_matrix(dsb, plane_state);
+ if (plane_state->hw.degamma_lut || plane_state->hw.gamma_lut)
+ intel_color_load_plane_luts(dsb, plane_state);
}
void intel_color_crtc_init(struct intel_crtc *crtc)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 0f70240970c7..499ed3685e21 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -646,7 +646,7 @@ struct intel_plane_state {
enum drm_color_encoding color_encoding;
enum drm_color_range color_range;
enum drm_scaling_filter scaling_filter;
- struct drm_property_blob *ctm;
+ struct drm_property_blob *ctm, *degamma_lut, *gamma_lut;
} hw;
struct i915_vma *ggtt_vma;
diff --git a/drivers/gpu/drm/i915/display/intel_plane.c b/drivers/gpu/drm/i915/display/intel_plane.c
index 01fd6ccc2aae..a73ce9ce3214 100644
--- a/drivers/gpu/drm/i915/display/intel_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_plane.c
@@ -348,6 +348,10 @@ intel_plane_colorop_replace_blob(struct intel_plane_state *plane_state,
{
if (intel_colorop->id == INTEL_PLANE_CB_CSC)
return drm_property_replace_blob(&plane_state->hw.ctm, blob);
+ else if (intel_colorop->id == INTEL_PLANE_CB_PRE_CSC_LUT)
+ return drm_property_replace_blob(&plane_state->hw.degamma_lut, blob);
+ else if (intel_colorop->id == INTEL_PLANE_CB_POST_CSC_LUT)
+ return drm_property_replace_blob(&plane_state->hw.gamma_lut, blob);
return false;
}
--
2.50.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [v8 11/15] drm/i915/color: Program Pre-CSC registers
2025-12-03 8:51 [v8 00/15] Plane Color Pipeline support for Intel platforms Uma Shankar
` (11 preceding siblings ...)
2025-12-03 8:52 ` [v8 10/15] drm/i915/color: Add framework to program PRE/POST CSC LUT Uma Shankar
@ 2025-12-03 8:52 ` Uma Shankar
2025-12-03 8:52 ` [v8 12/15] drm/i915/color: Program Plane Post CSC Registers Uma Shankar
` (4 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: Uma Shankar @ 2025-12-03 8:52 UTC (permalink / raw)
To: intel-gfx, intel-xe, dri-devel
Cc: chaitanya.kumar.borah, ville.syrjala, pekka.paalanen, contact,
harry.wentland, mwen, jadahl, sebastian.wick, swati2.sharma,
alex.hung, jani.nikula, suraj.kandpal, Uma Shankar
Add callback to program Pre-CSC LUT for TGL and beyond
v2: Add DSB support
v3: Add support for single segment 1D LUT color op
v4:
- s/drm_color_lut_32/drm_color_lut32/ (Simon)
- Change commit message (Suraj)
- Improve comments (Suraj)
- Remove multisegmented programming, to be added later
- Remove dead code for SDR planes, add when needed
BSpec: 50411, 50412, 50413, 50414
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 61 ++++++++++++++++++++++
1 file changed, 61 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 4ca359d68730..2a114d2964fa 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -3943,6 +3943,66 @@ xelpd_load_plane_csc_matrix(struct intel_dsb *dsb,
ctm_to_twos_complement(input[11], 0, 12));
}
+static void
+xelpd_program_plane_pre_csc_lut(struct intel_dsb *dsb,
+ const struct intel_plane_state *plane_state)
+{
+ struct intel_display *display = to_intel_display(plane_state);
+ const struct drm_plane_state *state = &plane_state->uapi;
+ enum pipe pipe = to_intel_plane(state->plane)->pipe;
+ enum plane_id plane = to_intel_plane(state->plane)->id;
+ const struct drm_color_lut32 *pre_csc_lut = plane_state->hw.degamma_lut->data;
+ u32 i, lut_size;
+
+ if (icl_is_hdr_plane(display, plane)) {
+ lut_size = 128;
+
+ intel_de_write_dsb(display, dsb,
+ PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe, plane, 0),
+ PLANE_PAL_PREC_AUTO_INCREMENT);
+
+ if (pre_csc_lut) {
+ for (i = 0; i < lut_size; i++) {
+ u32 lut_val = drm_color_lut32_extract(pre_csc_lut[i].green, 24);
+
+ intel_de_write_dsb(display, dsb,
+ PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0),
+ lut_val);
+ }
+
+ /* Program the max register to clamp values > 1.0. */
+ /* TODO: Restrict to 0x7ffffff */
+ do {
+ intel_de_write_dsb(display, dsb,
+ PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0),
+ (1 << 24));
+ } while (i++ > 130);
+ } else {
+ for (i = 0; i < lut_size; i++) {
+ u32 v = (i * ((1 << 24) - 1)) / (lut_size - 1);
+
+ intel_de_write_dsb(display, dsb,
+ PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0), v);
+ }
+
+ do {
+ intel_de_write_dsb(display, dsb,
+ PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0),
+ 1 << 24);
+ } while (i++ < 130);
+ }
+
+ intel_de_write_dsb(display, dsb, PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe, plane, 0), 0);
+ }
+}
+
+static void
+xelpd_plane_load_luts(struct intel_dsb *dsb, const struct intel_plane_state *plane_state)
+{
+ if (plane_state->hw.degamma_lut)
+ xelpd_program_plane_pre_csc_lut(dsb, plane_state);
+}
+
static const struct intel_color_funcs chv_color_funcs = {
.color_check = chv_color_check,
.color_commit_arm = i9xx_color_commit_arm,
@@ -3991,6 +4051,7 @@ static const struct intel_color_funcs tgl_color_funcs = {
.read_csc = icl_read_csc,
.get_config = skl_get_config,
.load_plane_csc_matrix = xelpd_load_plane_csc_matrix,
+ .load_plane_luts = xelpd_plane_load_luts,
};
static const struct intel_color_funcs icl_color_funcs = {
--
2.50.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [v8 12/15] drm/i915/color: Program Plane Post CSC Registers
2025-12-03 8:51 [v8 00/15] Plane Color Pipeline support for Intel platforms Uma Shankar
` (12 preceding siblings ...)
2025-12-03 8:52 ` [v8 11/15] drm/i915/color: Program Pre-CSC registers Uma Shankar
@ 2025-12-03 8:52 ` Uma Shankar
2025-12-03 8:52 ` [v8 13/15] drm/i915/color: Add registers for 3D LUT Uma Shankar
` (3 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: Uma Shankar @ 2025-12-03 8:52 UTC (permalink / raw)
To: intel-gfx, intel-xe, dri-devel
Cc: chaitanya.kumar.borah, ville.syrjala, pekka.paalanen, contact,
harry.wentland, mwen, jadahl, sebastian.wick, swati2.sharma,
alex.hung, jani.nikula, suraj.kandpal, Uma Shankar
Extract the LUT and program plane post csc registers.
v2: Add DSB support
v3: Add support for single segment 1D LUT
v4:
- s/drm_color_lut_32/drm_color_lut32 (Simon)
- Move declaration to beginning of the function (Suraj)
- Remove multisegmented code, add it later
- Remove dead code for SDR planes, add it later
v5:
- Fix iterator issues
v6: Removed redundant variable (Suraj)
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 59 ++++++++++++++++++++++
1 file changed, 59 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 2a114d2964fa..08f3b5b47b8e 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -3996,11 +3996,70 @@ xelpd_program_plane_pre_csc_lut(struct intel_dsb *dsb,
}
}
+static void
+xelpd_program_plane_post_csc_lut(struct intel_dsb *dsb,
+ const struct intel_plane_state *plane_state)
+{
+ struct intel_display *display = to_intel_display(plane_state);
+ const struct drm_plane_state *state = &plane_state->uapi;
+ enum pipe pipe = to_intel_plane(state->plane)->pipe;
+ enum plane_id plane = to_intel_plane(state->plane)->id;
+ const struct drm_color_lut32 *post_csc_lut = plane_state->hw.gamma_lut->data;
+ u32 i, lut_size, lut_val;
+
+ if (icl_is_hdr_plane(display, plane)) {
+ intel_de_write_dsb(display, dsb, PLANE_POST_CSC_GAMC_INDEX_ENH(pipe, plane, 0),
+ PLANE_PAL_PREC_AUTO_INCREMENT);
+ /* TODO: Add macro */
+ intel_de_write_dsb(display, dsb, PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH(pipe, plane, 0),
+ PLANE_PAL_PREC_AUTO_INCREMENT);
+ if (post_csc_lut) {
+ lut_size = 32;
+ for (i = 0; i < lut_size; i++) {
+ lut_val = drm_color_lut32_extract(post_csc_lut[i].green, 24);
+
+ intel_de_write_dsb(display, dsb,
+ PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, 0),
+ lut_val);
+ }
+
+ /* Segment 2 */
+ do {
+ intel_de_write_dsb(display, dsb,
+ PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, 0),
+ (1 << 24));
+ } while (i++ < 34);
+ } else {
+ /*TODO: Add for segment 0 */
+ lut_size = 32;
+ for (i = 0; i < lut_size; i++) {
+ u32 v = (i * ((1 << 24) - 1)) / (lut_size - 1);
+
+ intel_de_write_dsb(display, dsb,
+ PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, 0), v);
+ }
+
+ do {
+ intel_de_write_dsb(display, dsb,
+ PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, 0),
+ 1 << 24);
+ } while (i++ < 34);
+ }
+
+ intel_de_write_dsb(display, dsb, PLANE_POST_CSC_GAMC_INDEX_ENH(pipe, plane, 0), 0);
+ intel_de_write_dsb(display, dsb,
+ PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH(pipe, plane, 0), 0);
+ }
+}
+
static void
xelpd_plane_load_luts(struct intel_dsb *dsb, const struct intel_plane_state *plane_state)
{
if (plane_state->hw.degamma_lut)
xelpd_program_plane_pre_csc_lut(dsb, plane_state);
+
+ if (plane_state->hw.gamma_lut)
+ xelpd_program_plane_post_csc_lut(dsb, plane_state);
}
static const struct intel_color_funcs chv_color_funcs = {
--
2.50.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [v8 13/15] drm/i915/color: Add registers for 3D LUT
2025-12-03 8:51 [v8 00/15] Plane Color Pipeline support for Intel platforms Uma Shankar
` (13 preceding siblings ...)
2025-12-03 8:52 ` [v8 12/15] drm/i915/color: Program Plane Post CSC Registers Uma Shankar
@ 2025-12-03 8:52 ` Uma Shankar
2025-12-03 8:52 ` [v8 14/15] drm/i915/color: Add 3D LUT to color pipeline Uma Shankar
` (2 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: Uma Shankar @ 2025-12-03 8:52 UTC (permalink / raw)
To: intel-gfx, intel-xe, dri-devel
Cc: chaitanya.kumar.borah, ville.syrjala, pekka.paalanen, contact,
harry.wentland, mwen, jadahl, sebastian.wick, swati2.sharma,
alex.hung, jani.nikula, suraj.kandpal, Uma Shankar
From: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Add registers needed to program 3D LUT
v2:
- Follow convention documented in i915_reg.h (Jani)
- Removing space in trailer (Suraj)
- Move registers to intel_color_regs.h
BSpec: 69378, 69379, 69380
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
.../gpu/drm/i915/display/intel_color_regs.h | 29 +++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_color_regs.h b/drivers/gpu/drm/i915/display/intel_color_regs.h
index 8eb643cfead7..c370b6029369 100644
--- a/drivers/gpu/drm/i915/display/intel_color_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_color_regs.h
@@ -316,4 +316,33 @@
#define SKL_BOTTOM_COLOR_CSC_ENABLE REG_BIT(30)
#define SKL_BOTTOM_COLOR(pipe) _MMIO_PIPE(pipe, _SKL_BOTTOM_COLOR_A, _SKL_BOTTOM_COLOR_B)
+/* 3D LUT */
+#define _LUT_3D_CTL_A 0x490A4
+#define _LUT_3D_CTL_B 0x491A4
+#define LUT_3D_CTL(pipe) _MMIO_PIPE(pipe, _LUT_3D_CTL_A, _LUT_3D_CTL_B)
+#define LUT_3D_ENABLE REG_BIT(31)
+#define LUT_3D_READY REG_BIT(30)
+#define LUT_3D_BINDING_MASK REG_GENMASK(23, 22)
+#define LUT_3D_BIND_PIPE REG_FIELD_PREP(LUT_3D_BINDING_MASK, 0)
+#define LUT_3D_BIND_PLANE_1 REG_FIELD_PREP(LUT_3D_BINDING_MASK, 1)
+#define LUT_3D_BIND_PLANE_2 REG_FIELD_PREP(LUT_3D_BINDING_MASK, 2)
+#define LUT_3D_BIND_PLANE_3 REG_FIELD_PREP(LUT_3D_BINDING_MASK, 3)
+
+#define _LUT_3D_INDEX_A 0x490A8
+#define _LUT_3D_INDEX_B 0x491A8
+#define LUT_3D_INDEX(pipe) _MMIO_PIPE(pipe, _LUT_3D_INDEX_A, _LUT_3D_INDEX_B)
+#define LUT_3D_AUTO_INCREMENT REG_BIT(13)
+#define LUT_3D_INDEX_VALUE_MASK REG_GENMASK(12, 0)
+#define LUT_3D_INDEX_VALUE(x) REG_FIELD_PREP(LUT_3D_INDEX_VALUE_MASK, (x))
+
+#define _LUT_3D_DATA_A 0x490AC
+#define _LUT_3D_DATA_B 0x491AC
+#define LUT_3D_DATA(pipe) _MMIO_PIPE(pipe, _LUT_3D_DATA_A, _LUT_3D_DATA_B)
+#define LUT_3D_DATA_RED_MASK REG_GENMASK(29, 20)
+#define LUT_3D_DATA_GREEN_MASK REG_GENMASK(19, 10)
+#define LUT_3D_DATA_BLUE_MASK REG_GENMASK(9, 0)
+#define LUT_3D_DATA_RED(x) REG_FIELD_PREP(LUT_3D_DATA_RED_MASK, (x))
+#define LUT_3D_DATA_GREEN(x) REG_FIELD_PREP(LUT_3D_DATA_GREEN_MASK, (x))
+#define LUT_3D_DATA_BLUE(x) REG_FIELD_PREP(LUT_3D_DATA_BLUE_MASK, (x))
+
#endif /* __INTEL_COLOR_REGS_H__ */
--
2.50.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [v8 14/15] drm/i915/color: Add 3D LUT to color pipeline
2025-12-03 8:51 [v8 00/15] Plane Color Pipeline support for Intel platforms Uma Shankar
` (14 preceding siblings ...)
2025-12-03 8:52 ` [v8 13/15] drm/i915/color: Add registers for 3D LUT Uma Shankar
@ 2025-12-03 8:52 ` Uma Shankar
2025-12-12 15:08 ` Ville Syrjälä
2025-12-03 8:52 ` [v8 15/15] drm/i915/color: Enable Plane Color Pipelines Uma Shankar
2025-12-04 18:44 ` [v8 00/15] Plane Color Pipeline support for Intel platforms Jani Nikula
17 siblings, 1 reply; 29+ messages in thread
From: Uma Shankar @ 2025-12-03 8:52 UTC (permalink / raw)
To: intel-gfx, intel-xe, dri-devel
Cc: chaitanya.kumar.borah, ville.syrjala, pekka.paalanen, contact,
harry.wentland, mwen, jadahl, sebastian.wick, swati2.sharma,
alex.hung, jani.nikula, suraj.kandpal, Uma Shankar
From: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Add helpers to program the 3D LUT registers and arm them.
LUT_3D_READY in LUT_3D_CLT is cleared off by the HW once
the LUT buffer is loaded into it's internal working RAM.
So by the time we try to load/commit new values, we expect
it to be cleared off. If not, log an error and return
without writing new values. Do it only when writing with MMIO.
There is no way to read register within DSB execution.
v2:
- Add information regarding LUT_3D_READY to commit message (Jani)
- Log error instead of a drm_warn and return without committing changes
if 3DLUT HW is not ready to accept new values.
- Refactor intel_color_crtc_has_3dlut()
Also remove Gen10 check (Suraj)
v3:
- Addressed review comments (Suraj)
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 78 +++++++++++++++++++
drivers/gpu/drm/i915/display/intel_color.h | 4 +
.../drm/i915/display/intel_color_pipeline.c | 29 +++++--
.../drm/i915/display/intel_color_pipeline.h | 3 +-
.../drm/i915/display/intel_display_limits.h | 1 +
.../drm/i915/display/intel_display_types.h | 2 +-
drivers/gpu/drm/i915/display/intel_plane.c | 2 +
7 files changed, 112 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 08f3b5b47b8e..e7950655434b 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -4062,6 +4062,52 @@ xelpd_plane_load_luts(struct intel_dsb *dsb, const struct intel_plane_state *pla
xelpd_program_plane_post_csc_lut(dsb, plane_state);
}
+static u32 glk_3dlut_10(const struct drm_color_lut32 *color)
+{
+ return REG_FIELD_PREP(LUT_3D_DATA_RED_MASK, drm_color_lut32_extract(color->red, 10)) |
+ REG_FIELD_PREP(LUT_3D_DATA_GREEN_MASK, drm_color_lut32_extract(color->green, 10)) |
+ REG_FIELD_PREP(LUT_3D_DATA_BLUE_MASK, drm_color_lut32_extract(color->blue, 10));
+}
+
+static void glk_load_lut_3d(struct intel_dsb *dsb,
+ struct intel_crtc *crtc,
+ const struct drm_property_blob *blob)
+{
+ struct intel_display *display = to_intel_display(crtc->base.dev);
+ const struct drm_color_lut32 *lut = blob->data;
+ int i, lut_size = drm_color_lut32_size(blob);
+ enum pipe pipe = crtc->pipe;
+
+ if (!dsb && intel_de_read(display, LUT_3D_CTL(pipe)) & LUT_3D_READY) {
+ drm_err(display->drm, "[CRTC:%d:%s] 3D LUT not ready, not loading LUTs\n",
+ crtc->base.base.id, crtc->base.name);
+ return;
+ }
+
+ intel_de_write_dsb(display, dsb, LUT_3D_INDEX(pipe), LUT_3D_AUTO_INCREMENT);
+ for (i = 0; i < lut_size; i++)
+ intel_de_write_dsb(display, dsb, LUT_3D_DATA(pipe), glk_3dlut_10(&lut[i]));
+ intel_de_write_dsb(display, dsb, LUT_3D_INDEX(pipe), 0);
+}
+
+static void glk_lut_3d_commit(struct intel_dsb *dsb, struct intel_crtc *crtc, bool enable)
+{
+ struct intel_display *display = to_intel_display(crtc);
+ enum pipe pipe = crtc->pipe;
+ u32 val = 0;
+
+ if (!dsb && intel_de_read(display, LUT_3D_CTL(pipe)) & LUT_3D_READY) {
+ drm_err(display->drm, "[CRTC:%d:%s] 3D LUT not ready, not committing change\n",
+ crtc->base.base.id, crtc->base.name);
+ return;
+ }
+
+ if (enable)
+ val = LUT_3D_ENABLE | LUT_3D_READY | LUT_3D_BIND_PLANE_1;
+
+ intel_de_write_dsb(display, dsb, LUT_3D_CTL(pipe), val);
+}
+
static const struct intel_color_funcs chv_color_funcs = {
.color_check = chv_color_check,
.color_commit_arm = i9xx_color_commit_arm,
@@ -4191,6 +4237,16 @@ static const struct intel_color_funcs ilk_color_funcs = {
.get_config = ilk_get_config,
};
+void intel_color_plane_commit_arm(struct intel_dsb *dsb,
+ const struct intel_plane_state *plane_state)
+{
+ struct intel_display *display = to_intel_display(plane_state);
+ struct intel_crtc *crtc = to_intel_crtc(plane_state->uapi.crtc);
+
+ if (crtc && intel_color_crtc_has_3dlut(display, crtc->pipe))
+ glk_lut_3d_commit(dsb, crtc, !!plane_state->hw.lut_3d);
+}
+
static void
intel_color_load_plane_csc_matrix(struct intel_dsb *dsb,
const struct intel_plane_state *plane_state)
@@ -4211,6 +4267,26 @@ intel_color_load_plane_luts(struct intel_dsb *dsb,
display->funcs.color->load_plane_luts(dsb, plane_state);
}
+bool
+intel_color_crtc_has_3dlut(struct intel_display *display, enum pipe pipe)
+{
+ if (DISPLAY_VER(display) >= 12)
+ return pipe == PIPE_A || pipe == PIPE_B;
+ else
+ return false;
+}
+
+static void
+intel_color_load_3dlut(struct intel_dsb *dsb,
+ const struct intel_plane_state *plane_state)
+{
+ struct intel_display *display = to_intel_display(plane_state);
+ struct intel_crtc *crtc = to_intel_crtc(plane_state->uapi.crtc);
+
+ if (crtc && intel_color_crtc_has_3dlut(display, crtc->pipe))
+ glk_load_lut_3d(dsb, crtc, plane_state->hw.lut_3d);
+}
+
void intel_color_plane_program_pipeline(struct intel_dsb *dsb,
const struct intel_plane_state *plane_state)
{
@@ -4218,6 +4294,8 @@ void intel_color_plane_program_pipeline(struct intel_dsb *dsb,
intel_color_load_plane_csc_matrix(dsb, plane_state);
if (plane_state->hw.degamma_lut || plane_state->hw.gamma_lut)
intel_color_load_plane_luts(dsb, plane_state);
+ if (plane_state->hw.lut_3d)
+ intel_color_load_3dlut(dsb, plane_state);
}
void intel_color_crtc_init(struct intel_crtc *crtc)
diff --git a/drivers/gpu/drm/i915/display/intel_color.h b/drivers/gpu/drm/i915/display/intel_color.h
index 8051c827a1d8..c21b9bdf7bb8 100644
--- a/drivers/gpu/drm/i915/display/intel_color.h
+++ b/drivers/gpu/drm/i915/display/intel_color.h
@@ -15,6 +15,7 @@ struct intel_display;
struct intel_dsb;
struct intel_plane_state;
struct drm_property_blob;
+enum pipe;
void intel_color_init_hooks(struct intel_display *display);
int intel_color_init(struct intel_display *display);
@@ -43,4 +44,7 @@ bool intel_color_lut_equal(const struct intel_crtc_state *crtc_state,
void intel_color_assert_luts(const struct intel_crtc_state *crtc_state);
void intel_color_plane_program_pipeline(struct intel_dsb *dsb,
const struct intel_plane_state *plane_state);
+void intel_color_plane_commit_arm(struct intel_dsb *dsb,
+ const struct intel_plane_state *plane_state);
+bool intel_color_crtc_has_3dlut(struct intel_display *display, enum pipe pipe);
#endif /* __INTEL_COLOR_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_color_pipeline.c b/drivers/gpu/drm/i915/display/intel_color_pipeline.c
index 489d470cd011..942d9b9c93ce 100644
--- a/drivers/gpu/drm/i915/display/intel_color_pipeline.c
+++ b/drivers/gpu/drm/i915/display/intel_color_pipeline.c
@@ -2,6 +2,7 @@
/*
* Copyright © 2025 Intel Corporation
*/
+#include "intel_color.h"
#include "intel_colorop.h"
#include "intel_color_pipeline.h"
#include "intel_de.h"
@@ -13,12 +14,14 @@
#define PLANE_GAMMA_SIZE 32
static
-int _intel_color_pipeline_plane_init(struct drm_plane *plane, struct drm_prop_enum_list *list)
+int _intel_color_pipeline_plane_init(struct drm_plane *plane, struct drm_prop_enum_list *list,
+ enum pipe pipe)
{
- struct intel_colorop *colorop;
struct drm_device *dev = plane->dev;
- int ret;
+ struct intel_display *display = to_intel_display(dev);
struct drm_colorop *prev_op;
+ struct intel_colorop *colorop;
+ int ret;
colorop = intel_colorop_create(INTEL_PLANE_CB_PRE_CSC_LUT);
@@ -36,6 +39,22 @@ int _intel_color_pipeline_plane_init(struct drm_plane *plane, struct drm_prop_en
/* TODO: handle failures and clean up */
prev_op = &colorop->base;
+ if (DISPLAY_VER(display) >= 35 &&
+ intel_color_crtc_has_3dlut(display, pipe) &&
+ plane->type == DRM_PLANE_TYPE_PRIMARY) {
+ colorop = intel_colorop_create(INTEL_PLANE_CB_3DLUT);
+
+ ret = drm_plane_colorop_3dlut_init(dev, &colorop->base, plane, 17,
+ DRM_COLOROP_LUT3D_INTERPOLATION_TETRAHEDRAL,
+ true);
+ if (ret)
+ return ret;
+
+ drm_colorop_set_next_property(prev_op, &colorop->base);
+
+ prev_op = &colorop->base;
+ }
+
colorop = intel_colorop_create(INTEL_PLANE_CB_CSC);
ret = drm_plane_colorop_ctm_3x4_init(dev, &colorop->base, plane,
DRM_COLOROP_FLAG_ALLOW_BYPASS);
@@ -58,7 +77,7 @@ int _intel_color_pipeline_plane_init(struct drm_plane *plane, struct drm_prop_en
return 0;
}
-int intel_color_pipeline_plane_init(struct drm_plane *plane)
+int intel_color_pipeline_plane_init(struct drm_plane *plane, enum pipe pipe)
{
struct drm_device *dev = plane->dev;
struct intel_display *display = to_intel_display(dev);
@@ -71,7 +90,7 @@ int intel_color_pipeline_plane_init(struct drm_plane *plane)
return 0;
/* Add pipeline consisting of transfer functions */
- ret = _intel_color_pipeline_plane_init(plane, &pipelines[len]);
+ ret = _intel_color_pipeline_plane_init(plane, &pipelines[len], pipe);
if (ret)
return ret;
len++;
diff --git a/drivers/gpu/drm/i915/display/intel_color_pipeline.h b/drivers/gpu/drm/i915/display/intel_color_pipeline.h
index 7f1d32bc9202..a457d306da7f 100644
--- a/drivers/gpu/drm/i915/display/intel_color_pipeline.h
+++ b/drivers/gpu/drm/i915/display/intel_color_pipeline.h
@@ -7,7 +7,8 @@
#define __INTEL_COLOR_PIPELINE_H__
struct drm_plane;
+enum pipe;
-int intel_color_pipeline_plane_init(struct drm_plane *plane);
+int intel_color_pipeline_plane_init(struct drm_plane *plane, enum pipe pipe);
#endif /* __INTEL_COLOR_PIPELINE_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_limits.h b/drivers/gpu/drm/i915/display/intel_display_limits.h
index 55fd574ba313..cb3c9c665c44 100644
--- a/drivers/gpu/drm/i915/display/intel_display_limits.h
+++ b/drivers/gpu/drm/i915/display/intel_display_limits.h
@@ -142,6 +142,7 @@ enum intel_color_block {
INTEL_PLANE_CB_PRE_CSC_LUT,
INTEL_PLANE_CB_CSC,
INTEL_PLANE_CB_POST_CSC_LUT,
+ INTEL_PLANE_CB_3DLUT,
INTEL_CB_MAX
};
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 499ed3685e21..3c08ef5bb611 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -646,7 +646,7 @@ struct intel_plane_state {
enum drm_color_encoding color_encoding;
enum drm_color_range color_range;
enum drm_scaling_filter scaling_filter;
- struct drm_property_blob *ctm, *degamma_lut, *gamma_lut;
+ struct drm_property_blob *ctm, *degamma_lut, *gamma_lut, *lut_3d;
} hw;
struct i915_vma *ggtt_vma;
diff --git a/drivers/gpu/drm/i915/display/intel_plane.c b/drivers/gpu/drm/i915/display/intel_plane.c
index a73ce9ce3214..36849cd56c02 100644
--- a/drivers/gpu/drm/i915/display/intel_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_plane.c
@@ -352,6 +352,8 @@ intel_plane_colorop_replace_blob(struct intel_plane_state *plane_state,
return drm_property_replace_blob(&plane_state->hw.degamma_lut, blob);
else if (intel_colorop->id == INTEL_PLANE_CB_POST_CSC_LUT)
return drm_property_replace_blob(&plane_state->hw.gamma_lut, blob);
+ else if (intel_colorop->id == INTEL_PLANE_CB_3DLUT)
+ return drm_property_replace_blob(&plane_state->hw.lut_3d, blob);
return false;
}
--
2.50.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [v8 15/15] drm/i915/color: Enable Plane Color Pipelines
2025-12-03 8:51 [v8 00/15] Plane Color Pipeline support for Intel platforms Uma Shankar
` (15 preceding siblings ...)
2025-12-03 8:52 ` [v8 14/15] drm/i915/color: Add 3D LUT to color pipeline Uma Shankar
@ 2025-12-03 8:52 ` Uma Shankar
2025-12-04 18:44 ` [v8 00/15] Plane Color Pipeline support for Intel platforms Jani Nikula
17 siblings, 0 replies; 29+ messages in thread
From: Uma Shankar @ 2025-12-03 8:52 UTC (permalink / raw)
To: intel-gfx, intel-xe, dri-devel
Cc: chaitanya.kumar.borah, ville.syrjala, pekka.paalanen, contact,
harry.wentland, mwen, jadahl, sebastian.wick, swati2.sharma,
alex.hung, jani.nikula, suraj.kandpal, Uma Shankar
Expose color pipeline and add ability to program it.
v2: Set bit to enable multisegmented lut
v3: s/drm_color_lut_32/drm_color_lut32 (Simon)
v4: - Fix dsb programming
- Remove multi-segment LUT, they will be added in later patches
- Add pipeline only to TGL+
- Code Refactor
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 5 ++++-
.../drm/i915/display/skl_universal_plane.c | 21 +++++++++++++++++++
2 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index de8ae14e06cd..9c6d3ecdb589 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7298,6 +7298,7 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
struct intel_display *display = to_intel_display(state);
struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
+ unsigned int size = new_crtc_state->plane_color_changed ? 8192 : 1024;
if (!new_crtc_state->use_flipq &&
!new_crtc_state->use_dsb &&
@@ -7308,10 +7309,12 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
* Rough estimate:
* ~64 registers per each plane * 8 planes = 512
* Double that for pipe stuff and other overhead.
+ * ~4913 registers for 3DLUT
+ * ~200 color registers * 3 HDR planes
*/
new_crtc_state->dsb_commit = intel_dsb_prepare(state, crtc, INTEL_DSB_0,
new_crtc_state->use_dsb ||
- new_crtc_state->use_flipq ? 1024 : 16);
+ new_crtc_state->use_flipq ? size : 16);
if (!new_crtc_state->dsb_commit) {
new_crtc_state->use_flipq = false;
new_crtc_state->use_dsb = false;
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index d38582af6b39..4db350203999 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -10,6 +10,8 @@
#include <drm/drm_print.h>
#include "intel_bo.h"
+#include "intel_color.h"
+#include "intel_color_pipeline.h"
#include "intel_de.h"
#include "intel_display_irq.h"
#include "intel_display_regs.h"
@@ -1274,6 +1276,18 @@ static u32 glk_plane_color_ctl(const struct intel_plane_state *plane_state)
if (plane_state->force_black)
plane_color_ctl |= PLANE_COLOR_PLANE_CSC_ENABLE;
+ if (plane_state->hw.degamma_lut)
+ plane_color_ctl |= PLANE_COLOR_PRE_CSC_GAMMA_ENABLE;
+
+ if (plane_state->hw.ctm)
+ plane_color_ctl |= PLANE_COLOR_PLANE_CSC_ENABLE;
+
+ if (plane_state->hw.gamma_lut) {
+ plane_color_ctl &= ~PLANE_COLOR_PLANE_GAMMA_DISABLE;
+ if (drm_color_lut32_size(plane_state->hw.gamma_lut) != 32)
+ plane_color_ctl |= PLANE_COLOR_POST_CSC_GAMMA_MULTSEG_ENABLE;
+ }
+
return plane_color_ctl;
}
@@ -1555,6 +1569,8 @@ icl_plane_update_noarm(struct intel_dsb *dsb,
plane_color_ctl = plane_state->color_ctl |
glk_plane_color_ctl_crtc(crtc_state);
+ intel_color_plane_program_pipeline(dsb, plane_state);
+
/* The scaler will handle the output position */
if (plane_state->scaler_id >= 0) {
crtc_x = 0;
@@ -1656,6 +1672,8 @@ icl_plane_update_arm(struct intel_dsb *dsb,
icl_plane_update_sel_fetch_arm(dsb, plane, crtc_state, plane_state);
+ intel_color_plane_commit_arm(dsb, plane_state);
+
/*
* In order to have FBC for fp16 formats pixel normalizer block must be
* active. Check if pixel normalizer block need to be enabled for FBC.
@@ -3000,6 +3018,9 @@ skl_universal_plane_create(struct intel_display *display,
DRM_COLOR_YCBCR_BT709,
DRM_COLOR_YCBCR_LIMITED_RANGE);
+ if (DISPLAY_VER(display) >= 12)
+ intel_color_pipeline_plane_init(&plane->base, pipe);
+
drm_plane_create_alpha_property(&plane->base);
drm_plane_create_blend_mode_property(&plane->base,
BIT(DRM_MODE_BLEND_PIXEL_NONE) |
--
2.50.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* Re: [v8 00/15] Plane Color Pipeline support for Intel platforms
2025-12-03 8:51 [v8 00/15] Plane Color Pipeline support for Intel platforms Uma Shankar
` (16 preceding siblings ...)
2025-12-03 8:52 ` [v8 15/15] drm/i915/color: Enable Plane Color Pipelines Uma Shankar
@ 2025-12-04 18:44 ` Jani Nikula
2025-12-11 0:08 ` Matt Roper
17 siblings, 1 reply; 29+ messages in thread
From: Jani Nikula @ 2025-12-04 18:44 UTC (permalink / raw)
To: Uma Shankar, intel-gfx, intel-xe, dri-devel
Cc: chaitanya.kumar.borah, ville.syrjala, pekka.paalanen, contact,
harry.wentland, mwen, jadahl, sebastian.wick, swati2.sharma,
alex.hung, suraj.kandpal, Uma Shankar, Joshua Ashton,
Michel Dänzer, Xaver Hugl, Victoria Brekenfeld, Sima,
Liviu Dudau
On Wed, 03 Dec 2025, Uma Shankar <uma.shankar@intel.com> wrote:
> This series intends to add support for Plane Color Management for
> Intel platforms. This is based on the design which has been agreed
> upon by the community. Series implementing the design for generic
> DRM core has been sent out by Alex Hung and Harry Wentland and is
> merged to upstream tree:
> https://patchwork.freedesktop.org/series/152970/
Thanks for the patches, pushed to topic/drm-intel-plane-color-pipeline,
and sent out the pull request [1].
BR,
Jani.
[1] https://lore.kernel.org/all/e7129c6afd6208719d2f5124da86e810505e7a7b@intel.com
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [v8 00/15] Plane Color Pipeline support for Intel platforms
2025-12-04 18:44 ` [v8 00/15] Plane Color Pipeline support for Intel platforms Jani Nikula
@ 2025-12-11 0:08 ` Matt Roper
2025-12-11 14:01 ` Borah, Chaitanya Kumar
0 siblings, 1 reply; 29+ messages in thread
From: Matt Roper @ 2025-12-11 0:08 UTC (permalink / raw)
To: Jani Nikula
Cc: Uma Shankar, intel-gfx, intel-xe, dri-devel,
chaitanya.kumar.borah, ville.syrjala, pekka.paalanen, contact,
harry.wentland, mwen, jadahl, sebastian.wick, swati2.sharma,
alex.hung, suraj.kandpal, Joshua Ashton, Michel Dänzer,
Xaver Hugl, Victoria Brekenfeld, Sima, Liviu Dudau
On Thu, Dec 04, 2025 at 08:44:57PM +0200, Jani Nikula wrote:
> On Wed, 03 Dec 2025, Uma Shankar <uma.shankar@intel.com> wrote:
> > This series intends to add support for Plane Color Management for
> > Intel platforms. This is based on the design which has been agreed
> > upon by the community. Series implementing the design for generic
> > DRM core has been sent out by Alex Hung and Harry Wentland and is
> > merged to upstream tree:
> > https://patchwork.freedesktop.org/series/152970/
>
> Thanks for the patches, pushed to topic/drm-intel-plane-color-pipeline,
> and sent out the pull request [1].
Drive-by comment, but does this series have some memory leaks? Maybe
I'm missing something, but I see various allocations that don't seem to
have corresponding free's anywhere. E.g., the colorop from
intel_colorop_alloc() doesn't seem to be freed anywhere. And
drm_colorop_pipeline_destroy() / drm_colorop_cleanup() don't seem to be
called from anywhere yet, so I think the state allocated by
drm_colorop_reset() might also be leaking in the intel_display code?
Maybe I'm just overlooking something obvious; I haven't reviewed the
series in depth.
Matt
>
> BR,
> Jani.
>
>
> [1] https://lore.kernel.org/all/e7129c6afd6208719d2f5124da86e810505e7a7b@intel.com
>
>
> --
> Jani Nikula, Intel
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [v8 00/15] Plane Color Pipeline support for Intel platforms
2025-12-11 0:08 ` Matt Roper
@ 2025-12-11 14:01 ` Borah, Chaitanya Kumar
0 siblings, 0 replies; 29+ messages in thread
From: Borah, Chaitanya Kumar @ 2025-12-11 14:01 UTC (permalink / raw)
To: Matt Roper, Jani Nikula
Cc: Uma Shankar, intel-gfx, intel-xe, dri-devel, ville.syrjala,
pekka.paalanen, contact, harry.wentland, mwen, jadahl,
sebastian.wick, swati2.sharma, alex.hung, suraj.kandpal,
Joshua Ashton, Michel Dänzer, Xaver Hugl,
Victoria Brekenfeld, Sima, Liviu Dudau
On 12/11/2025 5:38 AM, Matt Roper wrote:
> On Thu, Dec 04, 2025 at 08:44:57PM +0200, Jani Nikula wrote:
>> On Wed, 03 Dec 2025, Uma Shankar <uma.shankar@intel.com> wrote:
>>> This series intends to add support for Plane Color Management for
>>> Intel platforms. This is based on the design which has been agreed
>>> upon by the community. Series implementing the design for generic
>>> DRM core has been sent out by Alex Hung and Harry Wentland and is
>>> merged to upstream tree:
>>> https://patchwork.freedesktop.org/series/152970/
>>
>> Thanks for the patches, pushed to topic/drm-intel-plane-color-pipeline,
>> and sent out the pull request [1].
>
> Drive-by comment, but does this series have some memory leaks? Maybe
> I'm missing something, but I see various allocations that don't seem to
> have corresponding free's anywhere. E.g., the colorop from
> intel_colorop_alloc() doesn't seem to be freed anywhere. And
> drm_colorop_pipeline_destroy() / drm_colorop_cleanup() don't seem to be
> called from anywhere yet, so I think the state allocated by
> drm_colorop_reset() might also be leaking in the intel_display code?
>
> Maybe I'm just overlooking something obvious; I haven't reviewed the
> series in depth.
>
Thank you for the comment Matt. You are probably right, we seemed to
have missed it.
Kmemleak does not seem to care about intel_colorop_alloc(). Probably
because the lifetime of these objects is tied to the driver itself?
It does complain about the kasprintfs used in
_intel_color_pipeline_plane_init().
This is used in amdgpu and vkms too. So they might be missing this too.
Also, I see amd calling drm_colorop_pipeline_destroy() only in the init
failure path. vkms seems to get this right, It calls it from
vkms_destroy(). I can ofcourse be wrong.
Anyway, let me investigate a bit further and hopefully come up with some
fixes.
==
Chaitanya
>
> Matt
>
>>
>> BR,
>> Jani.
>>
>>
>> [1] https://lore.kernel.org/all/e7129c6afd6208719d2f5124da86e810505e7a7b@intel.com
>>
>>
>> --
>> Jani Nikula, Intel
>
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [v8 14/15] drm/i915/color: Add 3D LUT to color pipeline
2025-12-03 8:52 ` [v8 14/15] drm/i915/color: Add 3D LUT to color pipeline Uma Shankar
@ 2025-12-12 15:08 ` Ville Syrjälä
2025-12-12 17:46 ` Borah, Chaitanya Kumar
0 siblings, 1 reply; 29+ messages in thread
From: Ville Syrjälä @ 2025-12-12 15:08 UTC (permalink / raw)
To: Uma Shankar
Cc: intel-gfx, intel-xe, dri-devel, chaitanya.kumar.borah,
pekka.paalanen, contact, harry.wentland, mwen, jadahl,
sebastian.wick, swati2.sharma, alex.hung, jani.nikula,
suraj.kandpal
On Wed, Dec 03, 2025 at 02:22:10PM +0530, Uma Shankar wrote:
> From: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
>
> Add helpers to program the 3D LUT registers and arm them.
>
> LUT_3D_READY in LUT_3D_CLT is cleared off by the HW once
> the LUT buffer is loaded into it's internal working RAM.
> So by the time we try to load/commit new values, we expect
> it to be cleared off. If not, log an error and return
> without writing new values. Do it only when writing with MMIO.
> There is no way to read register within DSB execution.
>
> v2:
> - Add information regarding LUT_3D_READY to commit message (Jani)
> - Log error instead of a drm_warn and return without committing changes
> if 3DLUT HW is not ready to accept new values.
> - Refactor intel_color_crtc_has_3dlut()
> Also remove Gen10 check (Suraj)
> v3:
> - Addressed review comments (Suraj)
>
> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 78 +++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_color.h | 4 +
> .../drm/i915/display/intel_color_pipeline.c | 29 +++++--
> .../drm/i915/display/intel_color_pipeline.h | 3 +-
> .../drm/i915/display/intel_display_limits.h | 1 +
> .../drm/i915/display/intel_display_types.h | 2 +-
> drivers/gpu/drm/i915/display/intel_plane.c | 2 +
> 7 files changed, 112 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index 08f3b5b47b8e..e7950655434b 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -4062,6 +4062,52 @@ xelpd_plane_load_luts(struct intel_dsb *dsb, const struct intel_plane_state *pla
> xelpd_program_plane_post_csc_lut(dsb, plane_state);
> }
>
> +static u32 glk_3dlut_10(const struct drm_color_lut32 *color)
> +{
> + return REG_FIELD_PREP(LUT_3D_DATA_RED_MASK, drm_color_lut32_extract(color->red, 10)) |
> + REG_FIELD_PREP(LUT_3D_DATA_GREEN_MASK, drm_color_lut32_extract(color->green, 10)) |
> + REG_FIELD_PREP(LUT_3D_DATA_BLUE_MASK, drm_color_lut32_extract(color->blue, 10));
> +}
> +
> +static void glk_load_lut_3d(struct intel_dsb *dsb,
> + struct intel_crtc *crtc,
> + const struct drm_property_blob *blob)
> +{
> + struct intel_display *display = to_intel_display(crtc->base.dev);
> + const struct drm_color_lut32 *lut = blob->data;
> + int i, lut_size = drm_color_lut32_size(blob);
> + enum pipe pipe = crtc->pipe;
> +
> + if (!dsb && intel_de_read(display, LUT_3D_CTL(pipe)) & LUT_3D_READY) {
> + drm_err(display->drm, "[CRTC:%d:%s] 3D LUT not ready, not loading LUTs\n",
> + crtc->base.base.id, crtc->base.name);
> + return;
Just ran into this while perusing the code...
This check could be implemented exactly like intel_vrr_check_push_sent()
so that it works for both the DSB and non-DSB paths. The 'return' should
just get nuked IMO.
> +void intel_color_plane_commit_arm(struct intel_dsb *dsb,
> + const struct intel_plane_state *plane_state)
> +{
> + struct intel_display *display = to_intel_display(plane_state);
> + struct intel_crtc *crtc = to_intel_crtc(plane_state->uapi.crtc);
> +
> + if (crtc && intel_color_crtc_has_3dlut(display, crtc->pipe))
> + glk_lut_3d_commit(dsb, crtc, !!plane_state->hw.lut_3d);
^^^^^^^^^^^^
And this looks like a pretty major fail. Why is the 3D LUT stored in
the *plane* state when it's a pipe level thing?
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [v8 14/15] drm/i915/color: Add 3D LUT to color pipeline
2025-12-12 15:08 ` Ville Syrjälä
@ 2025-12-12 17:46 ` Borah, Chaitanya Kumar
2025-12-12 18:25 ` Simon Ser
2025-12-12 18:45 ` Ville Syrjälä
0 siblings, 2 replies; 29+ messages in thread
From: Borah, Chaitanya Kumar @ 2025-12-12 17:46 UTC (permalink / raw)
To: Ville Syrjälä, Uma Shankar
Cc: intel-gfx, intel-xe, dri-devel, pekka.paalanen, contact,
harry.wentland, mwen, jadahl, sebastian.wick, swati2.sharma,
alex.hung, jani.nikula, suraj.kandpal
On 12/12/2025 8:38 PM, Ville Syrjälä wrote:
> On Wed, Dec 03, 2025 at 02:22:10PM +0530, Uma Shankar wrote:
>> From: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
>>
>> Add helpers to program the 3D LUT registers and arm them.
>>
>> LUT_3D_READY in LUT_3D_CLT is cleared off by the HW once
>> the LUT buffer is loaded into it's internal working RAM.
>> So by the time we try to load/commit new values, we expect
>> it to be cleared off. If not, log an error and return
>> without writing new values. Do it only when writing with MMIO.
>> There is no way to read register within DSB execution.
>>
>> v2:
>> - Add information regarding LUT_3D_READY to commit message (Jani)
>> - Log error instead of a drm_warn and return without committing changes
>> if 3DLUT HW is not ready to accept new values.
>> - Refactor intel_color_crtc_has_3dlut()
>> Also remove Gen10 check (Suraj)
>> v3:
>> - Addressed review comments (Suraj)
>>
>> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
>> Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
>> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_color.c | 78 +++++++++++++++++++
>> drivers/gpu/drm/i915/display/intel_color.h | 4 +
>> .../drm/i915/display/intel_color_pipeline.c | 29 +++++--
>> .../drm/i915/display/intel_color_pipeline.h | 3 +-
>> .../drm/i915/display/intel_display_limits.h | 1 +
>> .../drm/i915/display/intel_display_types.h | 2 +-
>> drivers/gpu/drm/i915/display/intel_plane.c | 2 +
>> 7 files changed, 112 insertions(+), 7 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
>> index 08f3b5b47b8e..e7950655434b 100644
>> --- a/drivers/gpu/drm/i915/display/intel_color.c
>> +++ b/drivers/gpu/drm/i915/display/intel_color.c
>> @@ -4062,6 +4062,52 @@ xelpd_plane_load_luts(struct intel_dsb *dsb, const struct intel_plane_state *pla
>> xelpd_program_plane_post_csc_lut(dsb, plane_state);
>> }
>>
>> +static u32 glk_3dlut_10(const struct drm_color_lut32 *color)
>> +{
>> + return REG_FIELD_PREP(LUT_3D_DATA_RED_MASK, drm_color_lut32_extract(color->red, 10)) |
>> + REG_FIELD_PREP(LUT_3D_DATA_GREEN_MASK, drm_color_lut32_extract(color->green, 10)) |
>> + REG_FIELD_PREP(LUT_3D_DATA_BLUE_MASK, drm_color_lut32_extract(color->blue, 10));
>> +}
>> +
>> +static void glk_load_lut_3d(struct intel_dsb *dsb,
>> + struct intel_crtc *crtc,
>> + const struct drm_property_blob *blob)
>> +{
>> + struct intel_display *display = to_intel_display(crtc->base.dev);
>> + const struct drm_color_lut32 *lut = blob->data;
>> + int i, lut_size = drm_color_lut32_size(blob);
>> + enum pipe pipe = crtc->pipe;
>> +
>> + if (!dsb && intel_de_read(display, LUT_3D_CTL(pipe)) & LUT_3D_READY) {
>> + drm_err(display->drm, "[CRTC:%d:%s] 3D LUT not ready, not loading LUTs\n",
>> + crtc->base.base.id, crtc->base.name);
>> + return;
>
> Just ran into this while perusing the code...
>
> This check could be implemented exactly like intel_vrr_check_push_sent()
> so that it works for both the DSB and non-DSB paths.
We did discuss this briefly[1], but went on with this as a first step.
My main concern was if it is a good idea to poll for a bit in the middle
of a commit. I understand that this is done for TRANS_PUSH_SEND but that
is the last thing we do for a commit.
>The 'return' should
> just get nuked IMO.
>
So just move ahead and program irrespective?
>> +void intel_color_plane_commit_arm(struct intel_dsb *dsb,
>> + const struct intel_plane_state *plane_state)
>> +{
>> + struct intel_display *display = to_intel_display(plane_state);
>> + struct intel_crtc *crtc = to_intel_crtc(plane_state->uapi.crtc);
>> +
>> + if (crtc && intel_color_crtc_has_3dlut(display, crtc->pipe))
>> + glk_lut_3d_commit(dsb, crtc, !!plane_state->hw.lut_3d);
> ^^^^^^^^^^^^
>
> And this looks like a pretty major fail. Why is the 3D LUT stored in
> the *plane* state when it's a pipe level thing?
>
With DISPLAY_VER(display) >= 35, 3DLUT can be attached to a plane.
(Bits[23:22] in 3DLUT_CTL). This is the only way we are exposing the HW
to the userspace right now (through the new plane color pipeline uapi).
Therefore, it lies in the plane state.
However, there are (soonish)plans to adopt the color pipeline for crtcs
too. Once that happens, it needs to be handled a bit more carefully. A
potential approach is to allow userspace to program the block with a
first come first served semantics and fail the commit if it tries to set
3DLUT both on plane and crtc in the same commit.
[1]
https://lore.kernel.org/intel-gfx/b01cade8-ba63-472a-a95f-bba9af57afbb@intel.com/
==
Chaitanya
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [v8 14/15] drm/i915/color: Add 3D LUT to color pipeline
2025-12-12 17:46 ` Borah, Chaitanya Kumar
@ 2025-12-12 18:25 ` Simon Ser
2025-12-15 8:43 ` Borah, Chaitanya Kumar
2025-12-12 18:45 ` Ville Syrjälä
1 sibling, 1 reply; 29+ messages in thread
From: Simon Ser @ 2025-12-12 18:25 UTC (permalink / raw)
To: Borah, Chaitanya Kumar
Cc: Ville Syrjälä, Uma Shankar, intel-gfx, intel-xe,
dri-devel, pekka.paalanen, harry.wentland, mwen, jadahl,
sebastian.wick, swati2.sharma, alex.hung, jani.nikula,
suraj.kandpal
On Friday, December 12th, 2025 at 18:47, Borah, Chaitanya Kumar <chaitanya.kumar.borah@intel.com> wrote:
> > > +void intel_color_plane_commit_arm(struct intel_dsb *dsb,
> > > + const struct intel_plane_state *plane_state)
> > > +{
> > > + struct intel_display *display = to_intel_display(plane_state);
> > > + struct intel_crtc *crtc = to_intel_crtc(plane_state->uapi.crtc);
> > > +
> > > + if (crtc && intel_color_crtc_has_3dlut(display, crtc->pipe))
> > > + glk_lut_3d_commit(dsb, crtc, !!plane_state->hw.lut_3d);
> > > ^^^^^^^^^^^^
> >
> > And this looks like a pretty major fail. Why is the 3D LUT stored in
> > the plane state when it's a pipe level thing?
>
> With DISPLAY_VER(display) >= 35, 3DLUT can be attached to a plane.
>
> (Bits[23:22] in 3DLUT_CTL). This is the only way we are exposing the HW
> to the userspace right now (through the new plane color pipeline uapi).
> Therefore, it lies in the plane state.
>
> However, there are (soonish)plans to adopt the color pipeline for crtcs
> too. Once that happens, it needs to be handled a bit more carefully. A
> potential approach is to allow userspace to program the block with a
> first come first served semantics and fail the commit if it tries to set
> 3DLUT both on plane and crtc in the same commit.
The plane 3D LUT must only be used before blending. Any pipe-level
post-blending 3D LUT hardware block is not suitable to implement plane
colorops.
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [v8 14/15] drm/i915/color: Add 3D LUT to color pipeline
2025-12-12 17:46 ` Borah, Chaitanya Kumar
2025-12-12 18:25 ` Simon Ser
@ 2025-12-12 18:45 ` Ville Syrjälä
2025-12-15 8:26 ` Borah, Chaitanya Kumar
1 sibling, 1 reply; 29+ messages in thread
From: Ville Syrjälä @ 2025-12-12 18:45 UTC (permalink / raw)
To: Borah, Chaitanya Kumar
Cc: Uma Shankar, intel-gfx, intel-xe, dri-devel, pekka.paalanen,
contact, harry.wentland, mwen, jadahl, sebastian.wick,
swati2.sharma, alex.hung, jani.nikula, suraj.kandpal
On Fri, Dec 12, 2025 at 11:16:56PM +0530, Borah, Chaitanya Kumar wrote:
>
>
> On 12/12/2025 8:38 PM, Ville Syrjälä wrote:
> > On Wed, Dec 03, 2025 at 02:22:10PM +0530, Uma Shankar wrote:
> >> From: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
> >>
> >> Add helpers to program the 3D LUT registers and arm them.
> >>
> >> LUT_3D_READY in LUT_3D_CLT is cleared off by the HW once
> >> the LUT buffer is loaded into it's internal working RAM.
> >> So by the time we try to load/commit new values, we expect
> >> it to be cleared off. If not, log an error and return
> >> without writing new values. Do it only when writing with MMIO.
> >> There is no way to read register within DSB execution.
> >>
> >> v2:
> >> - Add information regarding LUT_3D_READY to commit message (Jani)
> >> - Log error instead of a drm_warn and return without committing changes
> >> if 3DLUT HW is not ready to accept new values.
> >> - Refactor intel_color_crtc_has_3dlut()
> >> Also remove Gen10 check (Suraj)
> >> v3:
> >> - Addressed review comments (Suraj)
> >>
> >> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> >> Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
> >> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> >> ---
> >> drivers/gpu/drm/i915/display/intel_color.c | 78 +++++++++++++++++++
> >> drivers/gpu/drm/i915/display/intel_color.h | 4 +
> >> .../drm/i915/display/intel_color_pipeline.c | 29 +++++--
> >> .../drm/i915/display/intel_color_pipeline.h | 3 +-
> >> .../drm/i915/display/intel_display_limits.h | 1 +
> >> .../drm/i915/display/intel_display_types.h | 2 +-
> >> drivers/gpu/drm/i915/display/intel_plane.c | 2 +
> >> 7 files changed, 112 insertions(+), 7 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> >> index 08f3b5b47b8e..e7950655434b 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_color.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> >> @@ -4062,6 +4062,52 @@ xelpd_plane_load_luts(struct intel_dsb *dsb, const struct intel_plane_state *pla
> >> xelpd_program_plane_post_csc_lut(dsb, plane_state);
> >> }
> >>
> >> +static u32 glk_3dlut_10(const struct drm_color_lut32 *color)
> >> +{
> >> + return REG_FIELD_PREP(LUT_3D_DATA_RED_MASK, drm_color_lut32_extract(color->red, 10)) |
> >> + REG_FIELD_PREP(LUT_3D_DATA_GREEN_MASK, drm_color_lut32_extract(color->green, 10)) |
> >> + REG_FIELD_PREP(LUT_3D_DATA_BLUE_MASK, drm_color_lut32_extract(color->blue, 10));
> >> +}
> >> +
> >> +static void glk_load_lut_3d(struct intel_dsb *dsb,
> >> + struct intel_crtc *crtc,
> >> + const struct drm_property_blob *blob)
> >> +{
> >> + struct intel_display *display = to_intel_display(crtc->base.dev);
> >> + const struct drm_color_lut32 *lut = blob->data;
> >> + int i, lut_size = drm_color_lut32_size(blob);
> >> + enum pipe pipe = crtc->pipe;
> >> +
> >> + if (!dsb && intel_de_read(display, LUT_3D_CTL(pipe)) & LUT_3D_READY) {
> >> + drm_err(display->drm, "[CRTC:%d:%s] 3D LUT not ready, not loading LUTs\n",
> >> + crtc->base.base.id, crtc->base.name);
> >> + return;
> >
> > Just ran into this while perusing the code...
> >
> > This check could be implemented exactly like intel_vrr_check_push_sent()
> > so that it works for both the DSB and non-DSB paths.
>
> We did discuss this briefly[1], but went on with this as a first step.
>
> My main concern was if it is a good idea to poll for a bit in the middle
> of a commit. I understand that this is done for TRANS_PUSH_SEND but that
> is the last thing we do for a commit.
It's a single register read so not a big deal perhaps. But if that's a
concern then the entire check could be moved to the start of the commit.
Hmm, or perhaps we should move this check to the end of the commit as
well... Not sure.
>
> >The 'return' should
> > just get nuked IMO.
> >
>
> So just move ahead and program irrespective?
Having dead codepaths is not a great idea since they're never tested.
Also we should try to keep the DSB and MMIO codepaths as similar as
possible to avoid weird heisenbugs.
>
> >> +void intel_color_plane_commit_arm(struct intel_dsb *dsb,
> >> + const struct intel_plane_state *plane_state)
> >> +{
> >> + struct intel_display *display = to_intel_display(plane_state);
> >> + struct intel_crtc *crtc = to_intel_crtc(plane_state->uapi.crtc);
> >> +
> >> + if (crtc && intel_color_crtc_has_3dlut(display, crtc->pipe))
> >> + glk_lut_3d_commit(dsb, crtc, !!plane_state->hw.lut_3d);
> > ^^^^^^^^^^^^
> >
> > And this looks like a pretty major fail. Why is the 3D LUT stored in
> > the *plane* state when it's a pipe level thing?
> >
>
> With DISPLAY_VER(display) >= 35, 3DLUT can be attached to a plane.
> (Bits[23:22] in 3DLUT_CTL). This is the only way we are exposing the HW
> to the userspace right now (through the new plane color pipeline uapi).
> Therefore, it lies in the plane state.
And something makes sure it's only used by one plane at a time?
> However, there are (soonish)plans to adopt the color pipeline for crtcs
> too. Once that happens, it needs to be handled a bit more carefully. A
> potential approach is to allow userspace to program the block with a
> first come first served semantics and fail the commit if it tries to set
> 3DLUT both on plane and crtc in the same commit.
>
> [1]
> https://lore.kernel.org/intel-gfx/b01cade8-ba63-472a-a95f-bba9af57afbb@intel.com/
>
> ==
> Chaitanya
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [v8 14/15] drm/i915/color: Add 3D LUT to color pipeline
2025-12-12 18:45 ` Ville Syrjälä
@ 2025-12-15 8:26 ` Borah, Chaitanya Kumar
0 siblings, 0 replies; 29+ messages in thread
From: Borah, Chaitanya Kumar @ 2025-12-15 8:26 UTC (permalink / raw)
To: Ville Syrjälä
Cc: Uma Shankar, intel-gfx, intel-xe, dri-devel, pekka.paalanen,
contact, harry.wentland, mwen, jadahl, sebastian.wick,
swati2.sharma, alex.hung, jani.nikula, suraj.kandpal
On 12/13/2025 12:15 AM, Ville Syrjälä wrote:
> On Fri, Dec 12, 2025 at 11:16:56PM +0530, Borah, Chaitanya Kumar wrote:
>>
>>
>> On 12/12/2025 8:38 PM, Ville Syrjälä wrote:
>>> On Wed, Dec 03, 2025 at 02:22:10PM +0530, Uma Shankar wrote:
>>>> From: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
>>>>
>>>> Add helpers to program the 3D LUT registers and arm them.
>>>>
>>>> LUT_3D_READY in LUT_3D_CLT is cleared off by the HW once
>>>> the LUT buffer is loaded into it's internal working RAM.
>>>> So by the time we try to load/commit new values, we expect
>>>> it to be cleared off. If not, log an error and return
>>>> without writing new values. Do it only when writing with MMIO.
>>>> There is no way to read register within DSB execution.
>>>>
>>>> v2:
>>>> - Add information regarding LUT_3D_READY to commit message (Jani)
>>>> - Log error instead of a drm_warn and return without committing changes
>>>> if 3DLUT HW is not ready to accept new values.
>>>> - Refactor intel_color_crtc_has_3dlut()
>>>> Also remove Gen10 check (Suraj)
>>>> v3:
>>>> - Addressed review comments (Suraj)
>>>>
>>>> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
>>>> Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
>>>> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
>>>> ---
>>>> drivers/gpu/drm/i915/display/intel_color.c | 78 +++++++++++++++++++
>>>> drivers/gpu/drm/i915/display/intel_color.h | 4 +
>>>> .../drm/i915/display/intel_color_pipeline.c | 29 +++++--
>>>> .../drm/i915/display/intel_color_pipeline.h | 3 +-
>>>> .../drm/i915/display/intel_display_limits.h | 1 +
>>>> .../drm/i915/display/intel_display_types.h | 2 +-
>>>> drivers/gpu/drm/i915/display/intel_plane.c | 2 +
>>>> 7 files changed, 112 insertions(+), 7 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
>>>> index 08f3b5b47b8e..e7950655434b 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_color.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_color.c
>>>> @@ -4062,6 +4062,52 @@ xelpd_plane_load_luts(struct intel_dsb *dsb, const struct intel_plane_state *pla
>>>> xelpd_program_plane_post_csc_lut(dsb, plane_state);
>>>> }
>>>>
>>>> +static u32 glk_3dlut_10(const struct drm_color_lut32 *color)
>>>> +{
>>>> + return REG_FIELD_PREP(LUT_3D_DATA_RED_MASK, drm_color_lut32_extract(color->red, 10)) |
>>>> + REG_FIELD_PREP(LUT_3D_DATA_GREEN_MASK, drm_color_lut32_extract(color->green, 10)) |
>>>> + REG_FIELD_PREP(LUT_3D_DATA_BLUE_MASK, drm_color_lut32_extract(color->blue, 10));
>>>> +}
>>>> +
>>>> +static void glk_load_lut_3d(struct intel_dsb *dsb,
>>>> + struct intel_crtc *crtc,
>>>> + const struct drm_property_blob *blob)
>>>> +{
>>>> + struct intel_display *display = to_intel_display(crtc->base.dev);
>>>> + const struct drm_color_lut32 *lut = blob->data;
>>>> + int i, lut_size = drm_color_lut32_size(blob);
>>>> + enum pipe pipe = crtc->pipe;
>>>> +
>>>> + if (!dsb && intel_de_read(display, LUT_3D_CTL(pipe)) & LUT_3D_READY) {
>>>> + drm_err(display->drm, "[CRTC:%d:%s] 3D LUT not ready, not loading LUTs\n",
>>>> + crtc->base.base.id, crtc->base.name);
>>>> + return;
>>>
>>> Just ran into this while perusing the code...
>>>
>>> This check could be implemented exactly like intel_vrr_check_push_sent()
>>> so that it works for both the DSB and non-DSB paths.
>>
>> We did discuss this briefly[1], but went on with this as a first step.
>>
>> My main concern was if it is a good idea to poll for a bit in the middle
>> of a commit. I understand that this is done for TRANS_PUSH_SEND but that
>> is the last thing we do for a commit.
>
> It's a single register read so not a big deal perhaps. But if that's a
> concern then the entire check could be moved to the start of the commit.
> Hmm, or perhaps we should move this check to the end of the commit as
> well... Not sure.
>
Having a dsb poll with timeout equivalent to a MMIO read might be a way
to go. I have to check if it actually can be done.
Another way would be to implement all this in the state checker at the
end of each commit.
>>
>>> The 'return' should
>>> just get nuked IMO.
>>>
>>
>> So just move ahead and program irrespective?
>
> Having dead codepaths is not a great idea since they're never tested.
> Also we should try to keep the DSB and MMIO codepaths as similar as
> possible to avoid weird heisenbugs.
>
Yes that's a good point. From that perspective it would make sense to
remove the return from the MMIO path as well.
>>
>>>> +void intel_color_plane_commit_arm(struct intel_dsb *dsb,
>>>> + const struct intel_plane_state *plane_state)
>>>> +{
>>>> + struct intel_display *display = to_intel_display(plane_state);
>>>> + struct intel_crtc *crtc = to_intel_crtc(plane_state->uapi.crtc);
>>>> +
>>>> + if (crtc && intel_color_crtc_has_3dlut(display, crtc->pipe))
>>>> + glk_lut_3d_commit(dsb, crtc, !!plane_state->hw.lut_3d);
>>> ^^^^^^^^^^^^
>>>
>>> And this looks like a pretty major fail. Why is the 3D LUT stored in
>>> the *plane* state when it's a pipe level thing?
>>>
>>
>> With DISPLAY_VER(display) >= 35, 3DLUT can be attached to a plane.
>> (Bits[23:22] in 3DLUT_CTL). This is the only way we are exposing the HW
>> to the userspace right now (through the new plane color pipeline uapi).
>> Therefore, it lies in the plane state.
>
> And something makes sure it's only used by one plane at a time?
>
Unfortunately, even with the latest color pipeline UAPI, there is no
good way to represent a HW block which can be shared/attached at
different stages of the pipeline. So right now, we expose 3DLUT only
attached with the primary plane.
That way we don't confuse the userspace with opaque commit failures on
trying to enable it on multiple planes which would otherwise make the
pipeline totally unusable.
If we do find a way to expose 3DLUT on all the supported planes, then we
have to start worrying about it.
==
Chaitanya
>> However, there are (soonish)plans to adopt the color pipeline for crtcs
>> too. Once that happens, it needs to be handled a bit more carefully. A
>> potential approach is to allow userspace to program the block with a
>> first come first served semantics and fail the commit if it tries to set
>> 3DLUT both on plane and crtc in the same commit.
>>
>> [1]
>> https://lore.kernel.org/intel-gfx/b01cade8-ba63-472a-a95f-bba9af57afbb@intel.com/
>>
>> ==
>> Chaitanya
>
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [v8 14/15] drm/i915/color: Add 3D LUT to color pipeline
2025-12-12 18:25 ` Simon Ser
@ 2025-12-15 8:43 ` Borah, Chaitanya Kumar
2025-12-18 16:15 ` Simon Ser
0 siblings, 1 reply; 29+ messages in thread
From: Borah, Chaitanya Kumar @ 2025-12-15 8:43 UTC (permalink / raw)
To: Simon Ser
Cc: Ville Syrjälä, Uma Shankar, intel-gfx, intel-xe,
dri-devel, pekka.paalanen, harry.wentland, mwen, jadahl,
sebastian.wick, swati2.sharma, alex.hung, jani.nikula,
suraj.kandpal
On 12/12/2025 11:55 PM, Simon Ser wrote:
> On Friday, December 12th, 2025 at 18:47, Borah, Chaitanya Kumar <chaitanya.kumar.borah@intel.com> wrote:
>
>>>> +void intel_color_plane_commit_arm(struct intel_dsb *dsb,
>>>> + const struct intel_plane_state *plane_state)
>>>> +{
>>>> + struct intel_display *display = to_intel_display(plane_state);
>>>> + struct intel_crtc *crtc = to_intel_crtc(plane_state->uapi.crtc);
>>>> +
>>>> + if (crtc && intel_color_crtc_has_3dlut(display, crtc->pipe))
>>>> + glk_lut_3d_commit(dsb, crtc, !!plane_state->hw.lut_3d);
>>>> ^^^^^^^^^^^^
>>>
>>> And this looks like a pretty major fail. Why is the 3D LUT stored in
>>> the plane state when it's a pipe level thing?
>>
>> With DISPLAY_VER(display) >= 35, 3DLUT can be attached to a plane.
>>
>> (Bits[23:22] in 3DLUT_CTL). This is the only way we are exposing the HW
>> to the userspace right now (through the new plane color pipeline uapi).
>> Therefore, it lies in the plane state.
>>
>> However, there are (soonish)plans to adopt the color pipeline for crtcs
>> too. Once that happens, it needs to be handled a bit more carefully. A
>> potential approach is to allow userspace to program the block with a
>> first come first served semantics and fail the commit if it tries to set
>> 3DLUT both on plane and crtc in the same commit.
>
> The plane 3D LUT must only be used before blending. Any pipe-level
> post-blending 3D LUT hardware block is not suitable to implement plane
> colorops.
Same 3D LUT block is shared across pipe and planes. When we do end up
implementing the pipe color pipeline we would like the 3DLUT exposed at
the pipe stage too.
However, there is no good way to do it in the current color pipeline
UAPI (atleast that I know of). One suggestion from Harry (discussed in
the hackfest) was to list the pipelines in order of preference of the
driver.
Considering we prefer the pre-blend 3DLUT over a post blend one, it
would mean that we *don't* expose the 3DLUT on the first pipeline on the
crtc but do it in the second one. (I am not sure how well it scales though)
I have considered other solutions like introducing a new property say
"muxed" which could be used with Bypass to indicate if the current color
block is being used in another part of the pipeline.
Suggestions are welcome.
==
Chaitanya
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [v8 14/15] drm/i915/color: Add 3D LUT to color pipeline
2025-12-15 8:43 ` Borah, Chaitanya Kumar
@ 2025-12-18 16:15 ` Simon Ser
2025-12-19 13:24 ` Borah, Chaitanya Kumar
0 siblings, 1 reply; 29+ messages in thread
From: Simon Ser @ 2025-12-18 16:15 UTC (permalink / raw)
To: Borah, Chaitanya Kumar
Cc: Ville Syrjälä, Uma Shankar, intel-gfx, intel-xe,
dri-devel, pekka.paalanen, harry.wentland, mwen, jadahl,
sebastian.wick, swati2.sharma, alex.hung, jani.nikula,
suraj.kandpal
On Monday, December 15th, 2025 at 09:43, Borah, Chaitanya Kumar <chaitanya.kumar.borah@intel.com> wrote:
> On 12/12/2025 11:55 PM, Simon Ser wrote:
>
> > On Friday, December 12th, 2025 at 18:47, Borah, Chaitanya Kumar chaitanya.kumar.borah@intel.com wrote:
> >
> > > > > +void intel_color_plane_commit_arm(struct intel_dsb *dsb,
> > > > > + const struct intel_plane_state *plane_state)
> > > > > +{
> > > > > + struct intel_display *display = to_intel_display(plane_state);
> > > > > + struct intel_crtc *crtc = to_intel_crtc(plane_state->uapi.crtc);
> > > > > +
> > > > > + if (crtc && intel_color_crtc_has_3dlut(display, crtc->pipe))
> > > > > + glk_lut_3d_commit(dsb, crtc, !!plane_state->hw.lut_3d);
> > > > > ^^^^^^^^^^^^
> > > >
> > > > And this looks like a pretty major fail. Why is the 3D LUT stored in
> > > > the plane state when it's a pipe level thing?
> > >
> > > With DISPLAY_VER(display) >= 35, 3DLUT can be attached to a plane.
> > >
> > > (Bits[23:22] in 3DLUT_CTL). This is the only way we are exposing the HW
> > > to the userspace right now (through the new plane color pipeline uapi).
> > > Therefore, it lies in the plane state.
> > >
> > > However, there are (soonish)plans to adopt the color pipeline for crtcs
> > > too. Once that happens, it needs to be handled a bit more carefully. A
> > > potential approach is to allow userspace to program the block with a
> > > first come first served semantics and fail the commit if it tries to set
> > > 3DLUT both on plane and crtc in the same commit.
> >
> > The plane 3D LUT must only be used before blending. Any pipe-level
> > post-blending 3D LUT hardware block is not suitable to implement plane
> > colorops.
>
> Same 3D LUT block is shared across pipe and planes. When we do end up
> implementing the pipe color pipeline we would like the 3DLUT exposed at
> the pipe stage too.
Ah, I see! And there is a switch in the hw to configure whether it's
applied pre- or post-blending?
> However, there is no good way to do it in the current color pipeline
> UAPI (atleast that I know of). One suggestion from Harry (discussed in
> the hackfest) was to list the pipelines in order of preference of the
> driver.
>
> Considering we prefer the pre-blend 3DLUT over a post blend one, it
> would mean that we don't expose the 3DLUT on the first pipeline on the
> crtc but do it in the second one. (I am not sure how well it scales though)
>
> I have considered other solutions like introducing a new property say
> "muxed" which could be used with Bypass to indicate if the current color
> block is being used in another part of the pipeline.
I think two pipelines + making commits fail when they use conflicting
colorops is the way to go.
If it turns out to be a generalized issue with more hardware and the
above solution isn't enough for user-space, we can think of introducing
a way to describe the limitation.
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [v8 14/15] drm/i915/color: Add 3D LUT to color pipeline
2025-12-18 16:15 ` Simon Ser
@ 2025-12-19 13:24 ` Borah, Chaitanya Kumar
0 siblings, 0 replies; 29+ messages in thread
From: Borah, Chaitanya Kumar @ 2025-12-19 13:24 UTC (permalink / raw)
To: Simon Ser
Cc: Ville Syrjälä, Uma Shankar, intel-gfx, intel-xe,
dri-devel, pekka.paalanen, harry.wentland, mwen, jadahl,
sebastian.wick, swati2.sharma, alex.hung, jani.nikula,
suraj.kandpal
On 12/18/2025 9:45 PM, Simon Ser wrote:
> On Monday, December 15th, 2025 at 09:43, Borah, Chaitanya Kumar <chaitanya.kumar.borah@intel.com> wrote:
>
>> On 12/12/2025 11:55 PM, Simon Ser wrote:
>>
>>> On Friday, December 12th, 2025 at 18:47, Borah, Chaitanya Kumar chaitanya.kumar.borah@intel.com wrote:
>>>
>>>>>> +void intel_color_plane_commit_arm(struct intel_dsb *dsb,
>>>>>> + const struct intel_plane_state *plane_state)
>>>>>> +{
>>>>>> + struct intel_display *display = to_intel_display(plane_state);
>>>>>> + struct intel_crtc *crtc = to_intel_crtc(plane_state->uapi.crtc);
>>>>>> +
>>>>>> + if (crtc && intel_color_crtc_has_3dlut(display, crtc->pipe))
>>>>>> + glk_lut_3d_commit(dsb, crtc, !!plane_state->hw.lut_3d);
>>>>>> ^^^^^^^^^^^^
>>>>>
>>>>> And this looks like a pretty major fail. Why is the 3D LUT stored in
>>>>> the plane state when it's a pipe level thing?
>>>>
>>>> With DISPLAY_VER(display) >= 35, 3DLUT can be attached to a plane.
>>>>
>>>> (Bits[23:22] in 3DLUT_CTL). This is the only way we are exposing the HW
>>>> to the userspace right now (through the new plane color pipeline uapi).
>>>> Therefore, it lies in the plane state.
>>>>
>>>> However, there are (soonish)plans to adopt the color pipeline for crtcs
>>>> too. Once that happens, it needs to be handled a bit more carefully. A
>>>> potential approach is to allow userspace to program the block with a
>>>> first come first served semantics and fail the commit if it tries to set
>>>> 3DLUT both on plane and crtc in the same commit.
>>>
>>> The plane 3D LUT must only be used before blending. Any pipe-level
>>> post-blending 3D LUT hardware block is not suitable to implement plane
>>> colorops.
>>
>> Same 3D LUT block is shared across pipe and planes. When we do end up
>> implementing the pipe color pipeline we would like the 3DLUT exposed at
>> the pipe stage too.
>
> Ah, I see! And there is a switch in the hw to configure whether it's
> applied pre- or post-blending?
>
Yes, that's correct.
>> However, there is no good way to do it in the current color pipeline
>> UAPI (atleast that I know of). One suggestion from Harry (discussed in
>> the hackfest) was to list the pipelines in order of preference of the
>> driver.
>>
>> Considering we prefer the pre-blend 3DLUT over a post blend one, it
>> would mean that we don't expose the 3DLUT on the first pipeline on the
>> crtc but do it in the second one. (I am not sure how well it scales though)
>>
>> I have considered other solutions like introducing a new property say
>> "muxed" which could be used with Bypass to indicate if the current color
>> block is being used in another part of the pipeline.
>
> I think two pipelines + making commits fail when they use conflicting
> colorops is the way to go.
>
> If it turns out to be a generalized issue with more hardware and the
> above solution isn't enough for user-space, we can think of introducing
> a way to describe the limitation.
IIRC, AMD also had similar HW semantics with some block. But a problem
for another day, I guess.
==
Chaitanya
^ permalink raw reply [flat|nested] 29+ messages in thread
end of thread, other threads:[~2025-12-19 16:15 UTC | newest]
Thread overview: 29+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-12-03 8:51 [v8 00/15] Plane Color Pipeline support for Intel platforms Uma Shankar
2025-12-03 8:47 ` ✗ CI.checkpatch: warning for Plane Color Pipeline support for Intel platforms (rev7) Patchwork
2025-12-03 8:48 ` ✓ CI.KUnit: success " Patchwork
2025-12-03 8:51 ` [v8 01/15] drm/i915/display: Add identifiers for driver specific blocks Uma Shankar
2025-12-03 8:51 ` [v8 02/15] drm/i915: Add intel_color_op Uma Shankar
2025-12-03 8:51 ` [v8 03/15] drm/i915/color: Add helper to create intel colorop Uma Shankar
2025-12-03 8:52 ` [v8 04/15] drm/i915/color: Create a transfer function color pipeline Uma Shankar
2025-12-03 8:52 ` [v8 05/15] drm/i915/color: Add framework to program CSC Uma Shankar
2025-12-03 8:52 ` [v8 06/15] drm/i915/color: Preserve sign bit when int_bits is Zero Uma Shankar
2025-12-03 8:52 ` [v8 07/15] drm/i915/color: Add plane CTM callback for D12 and beyond Uma Shankar
2025-12-03 8:52 ` [v8 08/15] drm/i915: Add register definitions for Plane Degamma Uma Shankar
2025-12-03 8:52 ` [v8 09/15] drm/i915: Add register definitions for Plane Post CSC Uma Shankar
2025-12-03 8:52 ` [v8 10/15] drm/i915/color: Add framework to program PRE/POST CSC LUT Uma Shankar
2025-12-03 8:52 ` [v8 11/15] drm/i915/color: Program Pre-CSC registers Uma Shankar
2025-12-03 8:52 ` [v8 12/15] drm/i915/color: Program Plane Post CSC Registers Uma Shankar
2025-12-03 8:52 ` [v8 13/15] drm/i915/color: Add registers for 3D LUT Uma Shankar
2025-12-03 8:52 ` [v8 14/15] drm/i915/color: Add 3D LUT to color pipeline Uma Shankar
2025-12-12 15:08 ` Ville Syrjälä
2025-12-12 17:46 ` Borah, Chaitanya Kumar
2025-12-12 18:25 ` Simon Ser
2025-12-15 8:43 ` Borah, Chaitanya Kumar
2025-12-18 16:15 ` Simon Ser
2025-12-19 13:24 ` Borah, Chaitanya Kumar
2025-12-12 18:45 ` Ville Syrjälä
2025-12-15 8:26 ` Borah, Chaitanya Kumar
2025-12-03 8:52 ` [v8 15/15] drm/i915/color: Enable Plane Color Pipelines Uma Shankar
2025-12-04 18:44 ` [v8 00/15] Plane Color Pipeline support for Intel platforms Jani Nikula
2025-12-11 0:08 ` Matt Roper
2025-12-11 14:01 ` Borah, Chaitanya Kumar
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