[PATCH v2 0/8] Move PSR/Panel Replay sink data into intel_connector

[PATCH v2 0/8] Move PSR/Panel Replay sink data into intel_connector

[Jouni Högander]

This is a preparation patch set for MST Panel Replay.

In case of MST Panel Replay we may have several CRTCs on single
pipe. There CRTCs representing virtual devices within e.g. docking
station. All these virtual devices has their own DPCD registers
containing their Panel Replay capability information. These needs to
be taken into account when computing used Panel Replay state. Due to
this we can't continue having only sink capabilities stored in struct
intel_dp.

This patch set is moving Panel Replay capabilities into struct
intel_connector to make them available for Panel Replay CRTC state
computation.

v2:
  - use __le16 for two byte values in dpcd
  - use sizeof instead of hardcoded size in reading dpcd
  - drop unnecessarily passing intel_dp pointer
  - inline simple helpers 
  - use intel_dp_attached_dp instead of passing as a parameter
  - move pr/psr_dpcd into *_caps substruct
  - add FIXME
  - extra w/s removed

Jouni Högander (8):
  drm/i915/psr: Add panel granularity information into intel_connector
  drm/i915/psr: Use SU granularity information available in
    intel_connector
  drm/i915/psr: Compute Panel Replay/Adaptive Sync coexistence behavior
  drm/i915/psr: Move pr_dpcd and psr_dpcd to intel_connector
  drm/i915/psr: Clear pr_dpcd as well on disconnect
  drm/i915/psr: Move Panel Replay DSC sink support data to
    intel_connector
  drm/i915/psr: Move sink PSR and Panel Replay booleans to
    intel_connector
  drm/i915/psr: Move sink_sync_latency to intel_connector

 drivers/gpu/drm/i915/display/intel_alpm.c     |   6 +-
 .../drm/i915/display/intel_display_types.h    |  45 ++-
 drivers/gpu/drm/i915/display/intel_dp.c       |  17 +-
 drivers/gpu/drm/i915/display/intel_psr.c      | 298 +++++++++---------
 drivers/gpu/drm/i915/display/intel_psr.h      |   2 +-
 5 files changed, 205 insertions(+), 163 deletions(-)

-- 
2.43.0

[PATCH v2 1/8] drm/i915/psr: Add panel granularity information into intel_connector

[Jouni Högander]

As a preparation for MST Panel Replay implementation add psr_caps and
panel_replay_caps structures into intel_connector. These are supposed to
contain all sink information related to PSR and Panel Replay.

As a first step in moving Panel Replay and PSR sink data add panel
granularity information into these newly added caps structures.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_types.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index f8f7bc956214b..82f1aac22d50d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -561,6 +561,16 @@ struct intel_connector {
 			} overall_throughput;
 			int max_line_width;
 		} dsc_branch_caps;
+
+		struct {
+			u16 su_w_granularity;
+			u16 su_y_granularity;
+		} panel_replay_caps;
+
+		struct {
+			u16 su_w_granularity;
+			u16 su_y_granularity;
+		} psr_caps;
 	} dp;
 
 	struct {
-- 
2.43.0

[PATCH v2 2/8] drm/i915/psr: Use SU granularity information available in intel_connector

[Jouni Högander]

Currently we are storing only one set of granularity information for panels
supporting both PSR and Panel Replay. As panel is informing own
granularities for PSR and Panel Replay they could be different. Let's use
own granularities for PSR and Panel Replay instead of having only one set
for both. This is done by having intel_connector::psr_caps and
panel_replay_caps both containing granularity information.

Also remove complexity of sharing granularity read between PSR and Panel
Replay.

v2:
  - use __le16 for two byte values in dpcd
  - use sizeof instead of hardcoded size in reading dpcd
  - drop unnecessarily passing intel_dp pointer

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c  |   4 +-
 drivers/gpu/drm/i915/display/intel_psr.c | 147 +++++++++++------------
 drivers/gpu/drm/i915/display/intel_psr.h |   2 +-
 3 files changed, 72 insertions(+), 81 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 7df0e5e13688d..dcceb0ae2a56d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4562,7 +4562,7 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector
 	 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
 	 * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
 	 */
-	intel_psr_init_dpcd(intel_dp);
+	intel_psr_init_dpcd(intel_dp, connector);
 
 	intel_edp_set_sink_rates(intel_dp);
 	intel_dp_set_max_sink_lane_count(intel_dp);
@@ -6074,7 +6074,7 @@ intel_dp_detect(struct drm_connector *_connector,
 		connector->base.epoch_counter++;
 
 	if (!intel_dp_is_edp(intel_dp))
-		intel_psr_init_dpcd(intel_dp);
+		intel_psr_init_dpcd(intel_dp, connector);
 
 	intel_dp_detect_dsc_caps(intel_dp, connector);
 
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 15ef3b6caad6e..5f8df67f9993e 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -494,82 +494,37 @@ static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp)
 	return val;
 }
 
-static u8 intel_dp_get_su_capability(struct intel_dp *intel_dp)
-{
-	u8 su_capability = 0;
-
-	if (intel_dp->psr.sink_panel_replay_su_support) {
-		if (drm_dp_dpcd_read_byte(&intel_dp->aux,
-					  DP_PANEL_REPLAY_CAP_CAPABILITY,
-					  &su_capability) < 0)
-			return 0;
-	} else {
-		su_capability = intel_dp->psr_dpcd[1];
-	}
-
-	return su_capability;
-}
-
-static unsigned int
-intel_dp_get_su_x_granularity_offset(struct intel_dp *intel_dp)
-{
-	return intel_dp->psr.sink_panel_replay_su_support ?
-		DP_PANEL_REPLAY_CAP_X_GRANULARITY :
-		DP_PSR2_SU_X_GRANULARITY;
-}
-
-static unsigned int
-intel_dp_get_su_y_granularity_offset(struct intel_dp *intel_dp)
-{
-	return intel_dp->psr.sink_panel_replay_su_support ?
-		DP_PANEL_REPLAY_CAP_Y_GRANULARITY :
-		DP_PSR2_SU_Y_GRANULARITY;
-}
-
-/*
- * Note: Bits related to granularity are same in panel replay and psr
- * registers. Rely on PSR definitions on these "common" bits.
- */
-static void intel_dp_get_su_granularity(struct intel_dp *intel_dp)
+static void _psr_compute_su_granularity(struct intel_dp *intel_dp,
+					struct intel_connector *connector)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
 	ssize_t r;
-	u16 w;
+	__le16 w;
 	u8 y;
 
-	/*
-	 * TODO: Do we need to take into account panel supporting both PSR and
-	 * Panel replay?
-	 */
-
 	/*
 	 * If sink don't have specific granularity requirements set legacy
 	 * ones.
 	 */
-	if (!(intel_dp_get_su_capability(intel_dp) &
-	      DP_PSR2_SU_GRANULARITY_REQUIRED)) {
+	if (!(intel_dp->psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) {
 		/* As PSR2 HW sends full lines, we do not care about x granularity */
 		w = 4;
 		y = 4;
 		goto exit;
 	}
 
-	r = drm_dp_dpcd_read(&intel_dp->aux,
-			     intel_dp_get_su_x_granularity_offset(intel_dp),
-			     &w, 2);
-	if (r != 2)
+	r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &w, sizeof(w));
+	if (r != sizeof(w))
 		drm_dbg_kms(display->drm,
 			    "Unable to read selective update x granularity\n");
 	/*
 	 * Spec says that if the value read is 0 the default granularity should
 	 * be used instead.
 	 */
-	if (r != 2 || w == 0)
+	if (r != sizeof(w) || w == 0)
 		w = 4;
 
-	r = drm_dp_dpcd_read(&intel_dp->aux,
-			     intel_dp_get_su_y_granularity_offset(intel_dp),
-			     &y, 1);
+	r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_Y_GRANULARITY, &y, 1);
 	if (r != 1) {
 		drm_dbg_kms(display->drm,
 			    "Unable to read selective update y granularity\n");
@@ -579,8 +534,8 @@ static void intel_dp_get_su_granularity(struct intel_dp *intel_dp)
 		y = 1;
 
 exit:
-	intel_dp->psr.su_w_granularity = w;
-	intel_dp->psr.su_y_granularity = y;
+	connector->dp.psr_caps.su_w_granularity = le16_to_cpu(w);
+	connector->dp.psr_caps.su_y_granularity = y;
 }
 
 static enum intel_panel_replay_dsc_support
@@ -621,7 +576,32 @@ static const char *panel_replay_dsc_support_str(enum intel_panel_replay_dsc_supp
 	};
 }
 
-static void _panel_replay_init_dpcd(struct intel_dp *intel_dp)
+static void _panel_replay_compute_su_granularity(struct intel_dp *intel_dp,
+						 struct intel_connector *connector)
+{
+	u16 w;
+	u8 y;
+
+	if (!(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
+	       DP_PANEL_REPLAY_SU_GRANULARITY_REQUIRED)) {
+		w = 4;
+		y = 4;
+		goto exit;
+	}
+
+	/*
+	 * Spec says that if the value read is 0 the default granularity should
+	 * be used instead.
+	 */
+	w = le16_to_cpu(*(__le16 *)&intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_X_GRANULARITY)]) ? : 4;
+	y = intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_Y_GRANULARITY)] ? : 1;
+
+exit:
+	connector->dp.panel_replay_caps.su_w_granularity = w;
+	connector->dp.panel_replay_caps.su_y_granularity = y;
+}
+
+static void _panel_replay_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
 	int ret;
@@ -657,9 +637,12 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp)
 	intel_dp->psr.sink_panel_replay_support = true;
 
 	if (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
-	    DP_PANEL_REPLAY_SU_SUPPORT)
+	    DP_PANEL_REPLAY_SU_SUPPORT) {
 		intel_dp->psr.sink_panel_replay_su_support = true;
 
+		_panel_replay_compute_su_granularity(intel_dp, connector);
+	}
+
 	intel_dp->psr.sink_panel_replay_dsc_support = compute_pr_dsc_support(intel_dp);
 
 	drm_dbg_kms(display->drm,
@@ -669,7 +652,7 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp)
 		    panel_replay_dsc_support_str(intel_dp->psr.sink_panel_replay_dsc_support));
 }
 
-static void _psr_init_dpcd(struct intel_dp *intel_dp)
+static void _psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
 	int ret;
@@ -722,17 +705,16 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp)
 		drm_dbg_kms(display->drm, "PSR2 %ssupported\n",
 			    intel_dp->psr.sink_psr2_support ? "" : "not ");
 	}
+
+	if (intel_dp->psr.sink_psr2_support)
+		_psr_compute_su_granularity(intel_dp, connector);
 }
 
-void intel_psr_init_dpcd(struct intel_dp *intel_dp)
+void intel_psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
 {
-	_psr_init_dpcd(intel_dp);
-
-	_panel_replay_init_dpcd(intel_dp);
+	_psr_init_dpcd(intel_dp, connector);
 
-	if (intel_dp->psr.sink_psr2_support ||
-	    intel_dp->psr.sink_panel_replay_su_support)
-		intel_dp_get_su_granularity(intel_dp);
+	_panel_replay_init_dpcd(intel_dp, connector);
 }
 
 static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
@@ -1304,25 +1286,32 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
 	return crtc_state->enable_psr2_sel_fetch = true;
 }
 
-static bool psr2_granularity_check(struct intel_dp *intel_dp,
-				   struct intel_crtc_state *crtc_state)
+static bool psr2_granularity_check(struct intel_crtc_state *crtc_state,
+				   struct intel_connector *connector)
 {
+	struct intel_dp *intel_dp = intel_attached_dp(connector);
 	struct intel_display *display = to_intel_display(intel_dp);
 	const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
 	const int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
 	const int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
 	u16 y_granularity = 0;
+	u16 sink_y_granularity = crtc_state->has_panel_replay ?
+		connector->dp.panel_replay_caps.su_y_granularity :
+		connector->dp.psr_caps.su_y_granularity;
+	u16 sink_w_granularity =  crtc_state->has_panel_replay ?
+		connector->dp.panel_replay_caps.su_w_granularity :
+		connector->dp.psr_caps.su_w_granularity;
 
 	/* PSR2 HW only send full lines so we only need to validate the width */
-	if (crtc_hdisplay % intel_dp->psr.su_w_granularity)
+	if (crtc_hdisplay % sink_w_granularity)
 		return false;
 
-	if (crtc_vdisplay % intel_dp->psr.su_y_granularity)
+	if (crtc_vdisplay % sink_y_granularity)
 		return false;
 
 	/* HW tracking is only aligned to 4 lines */
 	if (!crtc_state->enable_psr2_sel_fetch)
-		return intel_dp->psr.su_y_granularity == 4;
+		return sink_y_granularity == 4;
 
 	/*
 	 * adl_p and mtl platforms have 1 line granularity.
@@ -1330,11 +1319,11 @@ static bool psr2_granularity_check(struct intel_dp *intel_dp,
 	 * to match sink requirement if multiple of 4.
 	 */
 	if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14)
-		y_granularity = intel_dp->psr.su_y_granularity;
-	else if (intel_dp->psr.su_y_granularity <= 2)
+		y_granularity = sink_y_granularity;
+	else if (sink_y_granularity <= 2)
 		y_granularity = 4;
-	else if ((intel_dp->psr.su_y_granularity % 4) == 0)
-		y_granularity = intel_dp->psr.su_y_granularity;
+	else if ((sink_y_granularity % 4) == 0)
+		y_granularity = sink_y_granularity;
 
 	if (y_granularity == 0 || crtc_vdisplay % y_granularity)
 		return false;
@@ -1621,9 +1610,11 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 	return true;
 }
 
-static bool intel_sel_update_config_valid(struct intel_dp *intel_dp,
-					  struct intel_crtc_state *crtc_state)
+static bool intel_sel_update_config_valid(struct intel_crtc_state *crtc_state,
+					  struct drm_connector_state *conn_state)
 {
+	struct intel_connector *connector = to_intel_connector(conn_state->connector);
+	struct intel_dp *intel_dp = intel_attached_dp(connector);
 	struct intel_display *display = to_intel_display(intel_dp);
 
 	if (HAS_PSR2_SEL_FETCH(display) &&
@@ -1671,7 +1662,7 @@ static bool intel_sel_update_config_valid(struct intel_dp *intel_dp,
 		goto unsupported;
 	}
 
-	if (!psr2_granularity_check(intel_dp, crtc_state)) {
+	if (!psr2_granularity_check(crtc_state, connector)) {
 		drm_dbg_kms(display->drm,
 			    "Selective update not enabled, SU granularity not compatible\n");
 		goto unsupported;
@@ -1866,7 +1857,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
 	if (!crtc_state->has_psr)
 		return;
 
-	crtc_state->has_sel_update = intel_sel_update_config_valid(intel_dp, crtc_state);
+	crtc_state->has_sel_update = intel_sel_update_config_valid(crtc_state, conn_state);
 }
 
 void intel_psr_get_config(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index 024ee4c309852..b41dc4d44ff29 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -28,7 +28,7 @@ struct intel_plane_state;
 bool intel_encoder_can_psr(struct intel_encoder *encoder);
 bool intel_psr_needs_aux_io_power(struct intel_encoder *encoder,
 				  const struct intel_crtc_state *crtc_state);
-void intel_psr_init_dpcd(struct intel_dp *intel_dp);
+void intel_psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector);
 void intel_psr_panel_replay_enable_sink(struct intel_dp *intel_dp);
 void intel_psr_pre_plane_update(struct intel_atomic_state *state,
 				struct intel_crtc *crtc);
-- 
2.43.0

Re: [PATCH v2 2/8] drm/i915/psr: Use SU granularity information available in intel_connector

[Imre Deak]

On Wed, Dec 03, 2025 at 12:31:28PM +0200, Jouni Högander wrote:
> Currently we are storing only one set of granularity information for panels
> supporting both PSR and Panel Replay. As panel is informing own
> granularities for PSR and Panel Replay they could be different. Let's use
> own granularities for PSR and Panel Replay instead of having only one set
> for both. This is done by having intel_connector::psr_caps and
> panel_replay_caps both containing granularity information.
> 
> Also remove complexity of sharing granularity read between PSR and Panel
> Replay.
> 
> v2:
>   - use __le16 for two byte values in dpcd
>   - use sizeof instead of hardcoded size in reading dpcd
>   - drop unnecessarily passing intel_dp pointer
> 
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> Reviewed-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c  |   4 +-
>  drivers/gpu/drm/i915/display/intel_psr.c | 147 +++++++++++------------
>  drivers/gpu/drm/i915/display/intel_psr.h |   2 +-
>  3 files changed, 72 insertions(+), 81 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 7df0e5e13688d..dcceb0ae2a56d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4562,7 +4562,7 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector
>  	 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
>  	 * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
>  	 */
> -	intel_psr_init_dpcd(intel_dp);
> +	intel_psr_init_dpcd(intel_dp, connector);
>  
>  	intel_edp_set_sink_rates(intel_dp);
>  	intel_dp_set_max_sink_lane_count(intel_dp);
> @@ -6074,7 +6074,7 @@ intel_dp_detect(struct drm_connector *_connector,
>  		connector->base.epoch_counter++;
>  
>  	if (!intel_dp_is_edp(intel_dp))
> -		intel_psr_init_dpcd(intel_dp);
> +		intel_psr_init_dpcd(intel_dp, connector);
>  
>  	intel_dp_detect_dsc_caps(intel_dp, connector);
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 15ef3b6caad6e..5f8df67f9993e 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -494,82 +494,37 @@ static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp)
>  	return val;
>  }
>  
> -static u8 intel_dp_get_su_capability(struct intel_dp *intel_dp)
> -{
> -	u8 su_capability = 0;
> -
> -	if (intel_dp->psr.sink_panel_replay_su_support) {
> -		if (drm_dp_dpcd_read_byte(&intel_dp->aux,
> -					  DP_PANEL_REPLAY_CAP_CAPABILITY,
> -					  &su_capability) < 0)
> -			return 0;
> -	} else {
> -		su_capability = intel_dp->psr_dpcd[1];
> -	}
> -
> -	return su_capability;
> -}
> -
> -static unsigned int
> -intel_dp_get_su_x_granularity_offset(struct intel_dp *intel_dp)
> -{
> -	return intel_dp->psr.sink_panel_replay_su_support ?
> -		DP_PANEL_REPLAY_CAP_X_GRANULARITY :
> -		DP_PSR2_SU_X_GRANULARITY;
> -}
> -
> -static unsigned int
> -intel_dp_get_su_y_granularity_offset(struct intel_dp *intel_dp)
> -{
> -	return intel_dp->psr.sink_panel_replay_su_support ?
> -		DP_PANEL_REPLAY_CAP_Y_GRANULARITY :
> -		DP_PSR2_SU_Y_GRANULARITY;
> -}
> -
> -/*
> - * Note: Bits related to granularity are same in panel replay and psr
> - * registers. Rely on PSR definitions on these "common" bits.
> - */
> -static void intel_dp_get_su_granularity(struct intel_dp *intel_dp)
> +static void _psr_compute_su_granularity(struct intel_dp *intel_dp,
> +					struct intel_connector *connector)
>  {
>  	struct intel_display *display = to_intel_display(intel_dp);
>  	ssize_t r;
> -	u16 w;
> +	__le16 w;
>  	u8 y;
>  
> -	/*
> -	 * TODO: Do we need to take into account panel supporting both PSR and
> -	 * Panel replay?
> -	 */
> -
>  	/*
>  	 * If sink don't have specific granularity requirements set legacy
>  	 * ones.
>  	 */
> -	if (!(intel_dp_get_su_capability(intel_dp) &
> -	      DP_PSR2_SU_GRANULARITY_REQUIRED)) {
> +	if (!(intel_dp->psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) {
>  		/* As PSR2 HW sends full lines, we do not care about x granularity */
>  		w = 4;

This needs now a cpu_to_le16() or a separate variable.

>  		y = 4;
>  		goto exit;
>  	}
>  
> -	r = drm_dp_dpcd_read(&intel_dp->aux,
> -			     intel_dp_get_su_x_granularity_offset(intel_dp),
> -			     &w, 2);
> -	if (r != 2)
> +	r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &w, sizeof(w));
> +	if (r != sizeof(w))
>  		drm_dbg_kms(display->drm,
>  			    "Unable to read selective update x granularity\n");
>  	/*
>  	 * Spec says that if the value read is 0 the default granularity should
>  	 * be used instead.
>  	 */
> -	if (r != 2 || w == 0)
> +	if (r != sizeof(w) || w == 0)
>  		w = 4;

This also needs a conversion/separate variable as above.

The patch otherwise looks ok to me.

>  
> -	r = drm_dp_dpcd_read(&intel_dp->aux,
> -			     intel_dp_get_su_y_granularity_offset(intel_dp),
> -			     &y, 1);
> +	r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_Y_GRANULARITY, &y, 1);
>  	if (r != 1) {
>  		drm_dbg_kms(display->drm,
>  			    "Unable to read selective update y granularity\n");
> @@ -579,8 +534,8 @@ static void intel_dp_get_su_granularity(struct intel_dp *intel_dp)
>  		y = 1;
>  
>  exit:
> -	intel_dp->psr.su_w_granularity = w;
> -	intel_dp->psr.su_y_granularity = y;
> +	connector->dp.psr_caps.su_w_granularity = le16_to_cpu(w);
> +	connector->dp.psr_caps.su_y_granularity = y;
>  }
>  
>  static enum intel_panel_replay_dsc_support
> @@ -621,7 +576,32 @@ static const char *panel_replay_dsc_support_str(enum intel_panel_replay_dsc_supp
>  	};
>  }
>  
> -static void _panel_replay_init_dpcd(struct intel_dp *intel_dp)
> +static void _panel_replay_compute_su_granularity(struct intel_dp *intel_dp,
> +						 struct intel_connector *connector)
> +{
> +	u16 w;
> +	u8 y;
> +
> +	if (!(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
> +	       DP_PANEL_REPLAY_SU_GRANULARITY_REQUIRED)) {
> +		w = 4;
> +		y = 4;
> +		goto exit;
> +	}
> +
> +	/*
> +	 * Spec says that if the value read is 0 the default granularity should
> +	 * be used instead.
> +	 */
> +	w = le16_to_cpu(*(__le16 *)&intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_X_GRANULARITY)]) ? : 4;
> +	y = intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_Y_GRANULARITY)] ? : 1;
> +
> +exit:
> +	connector->dp.panel_replay_caps.su_w_granularity = w;
> +	connector->dp.panel_replay_caps.su_y_granularity = y;
> +}
> +
> +static void _panel_replay_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
>  {
>  	struct intel_display *display = to_intel_display(intel_dp);
>  	int ret;
> @@ -657,9 +637,12 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp)
>  	intel_dp->psr.sink_panel_replay_support = true;
>  
>  	if (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
> -	    DP_PANEL_REPLAY_SU_SUPPORT)
> +	    DP_PANEL_REPLAY_SU_SUPPORT) {
>  		intel_dp->psr.sink_panel_replay_su_support = true;
>  
> +		_panel_replay_compute_su_granularity(intel_dp, connector);
> +	}
> +
>  	intel_dp->psr.sink_panel_replay_dsc_support = compute_pr_dsc_support(intel_dp);
>  
>  	drm_dbg_kms(display->drm,
> @@ -669,7 +652,7 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp)
>  		    panel_replay_dsc_support_str(intel_dp->psr.sink_panel_replay_dsc_support));
>  }
>  
> -static void _psr_init_dpcd(struct intel_dp *intel_dp)
> +static void _psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
>  {
>  	struct intel_display *display = to_intel_display(intel_dp);
>  	int ret;
> @@ -722,17 +705,16 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp)
>  		drm_dbg_kms(display->drm, "PSR2 %ssupported\n",
>  			    intel_dp->psr.sink_psr2_support ? "" : "not ");
>  	}
> +
> +	if (intel_dp->psr.sink_psr2_support)
> +		_psr_compute_su_granularity(intel_dp, connector);
>  }
>  
> -void intel_psr_init_dpcd(struct intel_dp *intel_dp)
> +void intel_psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
>  {
> -	_psr_init_dpcd(intel_dp);
> -
> -	_panel_replay_init_dpcd(intel_dp);
> +	_psr_init_dpcd(intel_dp, connector);
>  
> -	if (intel_dp->psr.sink_psr2_support ||
> -	    intel_dp->psr.sink_panel_replay_su_support)
> -		intel_dp_get_su_granularity(intel_dp);
> +	_panel_replay_init_dpcd(intel_dp, connector);
>  }
>  
>  static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
> @@ -1304,25 +1286,32 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
>  	return crtc_state->enable_psr2_sel_fetch = true;
>  }
>  
> -static bool psr2_granularity_check(struct intel_dp *intel_dp,
> -				   struct intel_crtc_state *crtc_state)
> +static bool psr2_granularity_check(struct intel_crtc_state *crtc_state,
> +				   struct intel_connector *connector)
>  {
> +	struct intel_dp *intel_dp = intel_attached_dp(connector);
>  	struct intel_display *display = to_intel_display(intel_dp);
>  	const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
>  	const int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
>  	const int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
>  	u16 y_granularity = 0;
> +	u16 sink_y_granularity = crtc_state->has_panel_replay ?
> +		connector->dp.panel_replay_caps.su_y_granularity :
> +		connector->dp.psr_caps.su_y_granularity;
> +	u16 sink_w_granularity =  crtc_state->has_panel_replay ?
> +		connector->dp.panel_replay_caps.su_w_granularity :
> +		connector->dp.psr_caps.su_w_granularity;
>  
>  	/* PSR2 HW only send full lines so we only need to validate the width */
> -	if (crtc_hdisplay % intel_dp->psr.su_w_granularity)
> +	if (crtc_hdisplay % sink_w_granularity)
>  		return false;
>  
> -	if (crtc_vdisplay % intel_dp->psr.su_y_granularity)
> +	if (crtc_vdisplay % sink_y_granularity)
>  		return false;
>  
>  	/* HW tracking is only aligned to 4 lines */
>  	if (!crtc_state->enable_psr2_sel_fetch)
> -		return intel_dp->psr.su_y_granularity == 4;
> +		return sink_y_granularity == 4;
>  
>  	/*
>  	 * adl_p and mtl platforms have 1 line granularity.
> @@ -1330,11 +1319,11 @@ static bool psr2_granularity_check(struct intel_dp *intel_dp,
>  	 * to match sink requirement if multiple of 4.
>  	 */
>  	if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14)
> -		y_granularity = intel_dp->psr.su_y_granularity;
> -	else if (intel_dp->psr.su_y_granularity <= 2)
> +		y_granularity = sink_y_granularity;
> +	else if (sink_y_granularity <= 2)
>  		y_granularity = 4;
> -	else if ((intel_dp->psr.su_y_granularity % 4) == 0)
> -		y_granularity = intel_dp->psr.su_y_granularity;
> +	else if ((sink_y_granularity % 4) == 0)
> +		y_granularity = sink_y_granularity;
>  
>  	if (y_granularity == 0 || crtc_vdisplay % y_granularity)
>  		return false;
> @@ -1621,9 +1610,11 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
>  	return true;
>  }
>  
> -static bool intel_sel_update_config_valid(struct intel_dp *intel_dp,
> -					  struct intel_crtc_state *crtc_state)
> +static bool intel_sel_update_config_valid(struct intel_crtc_state *crtc_state,
> +					  struct drm_connector_state *conn_state)
>  {
> +	struct intel_connector *connector = to_intel_connector(conn_state->connector);
> +	struct intel_dp *intel_dp = intel_attached_dp(connector);
>  	struct intel_display *display = to_intel_display(intel_dp);
>  
>  	if (HAS_PSR2_SEL_FETCH(display) &&
> @@ -1671,7 +1662,7 @@ static bool intel_sel_update_config_valid(struct intel_dp *intel_dp,
>  		goto unsupported;
>  	}
>  
> -	if (!psr2_granularity_check(intel_dp, crtc_state)) {
> +	if (!psr2_granularity_check(crtc_state, connector)) {
>  		drm_dbg_kms(display->drm,
>  			    "Selective update not enabled, SU granularity not compatible\n");
>  		goto unsupported;
> @@ -1866,7 +1857,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
>  	if (!crtc_state->has_psr)
>  		return;
>  
> -	crtc_state->has_sel_update = intel_sel_update_config_valid(intel_dp, crtc_state);
> +	crtc_state->has_sel_update = intel_sel_update_config_valid(crtc_state, conn_state);
>  }
>  
>  void intel_psr_get_config(struct intel_encoder *encoder,
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
> index 024ee4c309852..b41dc4d44ff29 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -28,7 +28,7 @@ struct intel_plane_state;
>  bool intel_encoder_can_psr(struct intel_encoder *encoder);
>  bool intel_psr_needs_aux_io_power(struct intel_encoder *encoder,
>  				  const struct intel_crtc_state *crtc_state);
> -void intel_psr_init_dpcd(struct intel_dp *intel_dp);
> +void intel_psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector);
>  void intel_psr_panel_replay_enable_sink(struct intel_dp *intel_dp);
>  void intel_psr_pre_plane_update(struct intel_atomic_state *state,
>  				struct intel_crtc *crtc);
> -- 
> 2.43.0
> 

[PATCH v3] drm/i915/psr: Use SU granularity information available in intel_connector

[Jouni Högander]

Currently we are storing only one set of granularity information for panels
supporting both PSR and Panel Replay. As panel is informing own
granularities for PSR and Panel Replay they could be different. Let's use
own granularities for PSR and Panel Replay instead of having only one set
for both. This is done by having intel_connector::psr_caps and
panel_replay_caps both containing granularity information.

Also remove complexity of sharing granularity read between PSR and Panel
Replay.

v3:
  - use cpu_to_le16 for default value
v2:
  - use __le16 for two byte values in dpcd
  - use sizeof instead of hardcoded size in reading dpcd
  - drop unnecessarily passing intel_dp pointer

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c  |   4 +-
 drivers/gpu/drm/i915/display/intel_psr.c | 151 +++++++++++------------
 drivers/gpu/drm/i915/display/intel_psr.h |   2 +-
 3 files changed, 74 insertions(+), 83 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 7df0e5e13688d..dcceb0ae2a56d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4562,7 +4562,7 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector
 	 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
 	 * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
 	 */
-	intel_psr_init_dpcd(intel_dp);
+	intel_psr_init_dpcd(intel_dp, connector);
 
 	intel_edp_set_sink_rates(intel_dp);
 	intel_dp_set_max_sink_lane_count(intel_dp);
@@ -6074,7 +6074,7 @@ intel_dp_detect(struct drm_connector *_connector,
 		connector->base.epoch_counter++;
 
 	if (!intel_dp_is_edp(intel_dp))
-		intel_psr_init_dpcd(intel_dp);
+		intel_psr_init_dpcd(intel_dp, connector);
 
 	intel_dp_detect_dsc_caps(intel_dp, connector);
 
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 15ef3b6caad6e..417a6cd2fca9d 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -494,82 +494,37 @@ static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp)
 	return val;
 }
 
-static u8 intel_dp_get_su_capability(struct intel_dp *intel_dp)
-{
-	u8 su_capability = 0;
-
-	if (intel_dp->psr.sink_panel_replay_su_support) {
-		if (drm_dp_dpcd_read_byte(&intel_dp->aux,
-					  DP_PANEL_REPLAY_CAP_CAPABILITY,
-					  &su_capability) < 0)
-			return 0;
-	} else {
-		su_capability = intel_dp->psr_dpcd[1];
-	}
-
-	return su_capability;
-}
-
-static unsigned int
-intel_dp_get_su_x_granularity_offset(struct intel_dp *intel_dp)
-{
-	return intel_dp->psr.sink_panel_replay_su_support ?
-		DP_PANEL_REPLAY_CAP_X_GRANULARITY :
-		DP_PSR2_SU_X_GRANULARITY;
-}
-
-static unsigned int
-intel_dp_get_su_y_granularity_offset(struct intel_dp *intel_dp)
-{
-	return intel_dp->psr.sink_panel_replay_su_support ?
-		DP_PANEL_REPLAY_CAP_Y_GRANULARITY :
-		DP_PSR2_SU_Y_GRANULARITY;
-}
-
-/*
- * Note: Bits related to granularity are same in panel replay and psr
- * registers. Rely on PSR definitions on these "common" bits.
- */
-static void intel_dp_get_su_granularity(struct intel_dp *intel_dp)
+static void _psr_compute_su_granularity(struct intel_dp *intel_dp,
+					struct intel_connector *connector)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
 	ssize_t r;
-	u16 w;
+	__le16 w;
 	u8 y;
 
-	/*
-	 * TODO: Do we need to take into account panel supporting both PSR and
-	 * Panel replay?
-	 */
-
 	/*
 	 * If sink don't have specific granularity requirements set legacy
 	 * ones.
 	 */
-	if (!(intel_dp_get_su_capability(intel_dp) &
-	      DP_PSR2_SU_GRANULARITY_REQUIRED)) {
+	if (!(intel_dp->psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) {
 		/* As PSR2 HW sends full lines, we do not care about x granularity */
-		w = 4;
+		w = cpu_to_le16(4);
 		y = 4;
 		goto exit;
 	}
 
-	r = drm_dp_dpcd_read(&intel_dp->aux,
-			     intel_dp_get_su_x_granularity_offset(intel_dp),
-			     &w, 2);
-	if (r != 2)
+	r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &w, sizeof(w));
+	if (r != sizeof(w))
 		drm_dbg_kms(display->drm,
 			    "Unable to read selective update x granularity\n");
 	/*
 	 * Spec says that if the value read is 0 the default granularity should
 	 * be used instead.
 	 */
-	if (r != 2 || w == 0)
-		w = 4;
+	if (r != sizeof(w) || w == 0)
+		w = cpu_to_le16(4);
 
-	r = drm_dp_dpcd_read(&intel_dp->aux,
-			     intel_dp_get_su_y_granularity_offset(intel_dp),
-			     &y, 1);
+	r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_Y_GRANULARITY, &y, 1);
 	if (r != 1) {
 		drm_dbg_kms(display->drm,
 			    "Unable to read selective update y granularity\n");
@@ -579,8 +534,8 @@ static void intel_dp_get_su_granularity(struct intel_dp *intel_dp)
 		y = 1;
 
 exit:
-	intel_dp->psr.su_w_granularity = w;
-	intel_dp->psr.su_y_granularity = y;
+	connector->dp.psr_caps.su_w_granularity = le16_to_cpu(w);
+	connector->dp.psr_caps.su_y_granularity = y;
 }
 
 static enum intel_panel_replay_dsc_support
@@ -621,7 +576,32 @@ static const char *panel_replay_dsc_support_str(enum intel_panel_replay_dsc_supp
 	};
 }
 
-static void _panel_replay_init_dpcd(struct intel_dp *intel_dp)
+static void _panel_replay_compute_su_granularity(struct intel_dp *intel_dp,
+						 struct intel_connector *connector)
+{
+	u16 w;
+	u8 y;
+
+	if (!(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
+	       DP_PANEL_REPLAY_SU_GRANULARITY_REQUIRED)) {
+		w = 4;
+		y = 4;
+		goto exit;
+	}
+
+	/*
+	 * Spec says that if the value read is 0 the default granularity should
+	 * be used instead.
+	 */
+	w = le16_to_cpu(*(__le16 *)&intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_X_GRANULARITY)]) ? : 4;
+	y = intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_Y_GRANULARITY)] ? : 1;
+
+exit:
+	connector->dp.panel_replay_caps.su_w_granularity = w;
+	connector->dp.panel_replay_caps.su_y_granularity = y;
+}
+
+static void _panel_replay_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
 	int ret;
@@ -657,9 +637,12 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp)
 	intel_dp->psr.sink_panel_replay_support = true;
 
 	if (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
-	    DP_PANEL_REPLAY_SU_SUPPORT)
+	    DP_PANEL_REPLAY_SU_SUPPORT) {
 		intel_dp->psr.sink_panel_replay_su_support = true;
 
+		_panel_replay_compute_su_granularity(intel_dp, connector);
+	}
+
 	intel_dp->psr.sink_panel_replay_dsc_support = compute_pr_dsc_support(intel_dp);
 
 	drm_dbg_kms(display->drm,
@@ -669,7 +652,7 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp)
 		    panel_replay_dsc_support_str(intel_dp->psr.sink_panel_replay_dsc_support));
 }
 
-static void _psr_init_dpcd(struct intel_dp *intel_dp)
+static void _psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
 	int ret;
@@ -722,17 +705,16 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp)
 		drm_dbg_kms(display->drm, "PSR2 %ssupported\n",
 			    intel_dp->psr.sink_psr2_support ? "" : "not ");
 	}
+
+	if (intel_dp->psr.sink_psr2_support)
+		_psr_compute_su_granularity(intel_dp, connector);
 }
 
-void intel_psr_init_dpcd(struct intel_dp *intel_dp)
+void intel_psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
 {
-	_psr_init_dpcd(intel_dp);
-
-	_panel_replay_init_dpcd(intel_dp);
+	_psr_init_dpcd(intel_dp, connector);
 
-	if (intel_dp->psr.sink_psr2_support ||
-	    intel_dp->psr.sink_panel_replay_su_support)
-		intel_dp_get_su_granularity(intel_dp);
+	_panel_replay_init_dpcd(intel_dp, connector);
 }
 
 static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
@@ -1304,25 +1286,32 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
 	return crtc_state->enable_psr2_sel_fetch = true;
 }
 
-static bool psr2_granularity_check(struct intel_dp *intel_dp,
-				   struct intel_crtc_state *crtc_state)
+static bool psr2_granularity_check(struct intel_crtc_state *crtc_state,
+				   struct intel_connector *connector)
 {
+	struct intel_dp *intel_dp = intel_attached_dp(connector);
 	struct intel_display *display = to_intel_display(intel_dp);
 	const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
 	const int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
 	const int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
 	u16 y_granularity = 0;
+	u16 sink_y_granularity = crtc_state->has_panel_replay ?
+		connector->dp.panel_replay_caps.su_y_granularity :
+		connector->dp.psr_caps.su_y_granularity;
+	u16 sink_w_granularity =  crtc_state->has_panel_replay ?
+		connector->dp.panel_replay_caps.su_w_granularity :
+		connector->dp.psr_caps.su_w_granularity;
 
 	/* PSR2 HW only send full lines so we only need to validate the width */
-	if (crtc_hdisplay % intel_dp->psr.su_w_granularity)
+	if (crtc_hdisplay % sink_w_granularity)
 		return false;
 
-	if (crtc_vdisplay % intel_dp->psr.su_y_granularity)
+	if (crtc_vdisplay % sink_y_granularity)
 		return false;
 
 	/* HW tracking is only aligned to 4 lines */
 	if (!crtc_state->enable_psr2_sel_fetch)
-		return intel_dp->psr.su_y_granularity == 4;
+		return sink_y_granularity == 4;
 
 	/*
 	 * adl_p and mtl platforms have 1 line granularity.
@@ -1330,11 +1319,11 @@ static bool psr2_granularity_check(struct intel_dp *intel_dp,
 	 * to match sink requirement if multiple of 4.
 	 */
 	if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14)
-		y_granularity = intel_dp->psr.su_y_granularity;
-	else if (intel_dp->psr.su_y_granularity <= 2)
+		y_granularity = sink_y_granularity;
+	else if (sink_y_granularity <= 2)
 		y_granularity = 4;
-	else if ((intel_dp->psr.su_y_granularity % 4) == 0)
-		y_granularity = intel_dp->psr.su_y_granularity;
+	else if ((sink_y_granularity % 4) == 0)
+		y_granularity = sink_y_granularity;
 
 	if (y_granularity == 0 || crtc_vdisplay % y_granularity)
 		return false;
@@ -1621,9 +1610,11 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 	return true;
 }
 
-static bool intel_sel_update_config_valid(struct intel_dp *intel_dp,
-					  struct intel_crtc_state *crtc_state)
+static bool intel_sel_update_config_valid(struct intel_crtc_state *crtc_state,
+					  struct drm_connector_state *conn_state)
 {
+	struct intel_connector *connector = to_intel_connector(conn_state->connector);
+	struct intel_dp *intel_dp = intel_attached_dp(connector);
 	struct intel_display *display = to_intel_display(intel_dp);
 
 	if (HAS_PSR2_SEL_FETCH(display) &&
@@ -1671,7 +1662,7 @@ static bool intel_sel_update_config_valid(struct intel_dp *intel_dp,
 		goto unsupported;
 	}
 
-	if (!psr2_granularity_check(intel_dp, crtc_state)) {
+	if (!psr2_granularity_check(crtc_state, connector)) {
 		drm_dbg_kms(display->drm,
 			    "Selective update not enabled, SU granularity not compatible\n");
 		goto unsupported;
@@ -1866,7 +1857,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
 	if (!crtc_state->has_psr)
 		return;
 
-	crtc_state->has_sel_update = intel_sel_update_config_valid(intel_dp, crtc_state);
+	crtc_state->has_sel_update = intel_sel_update_config_valid(crtc_state, conn_state);
 }
 
 void intel_psr_get_config(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index 024ee4c309852..b41dc4d44ff29 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -28,7 +28,7 @@ struct intel_plane_state;
 bool intel_encoder_can_psr(struct intel_encoder *encoder);
 bool intel_psr_needs_aux_io_power(struct intel_encoder *encoder,
 				  const struct intel_crtc_state *crtc_state);
-void intel_psr_init_dpcd(struct intel_dp *intel_dp);
+void intel_psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector);
 void intel_psr_panel_replay_enable_sink(struct intel_dp *intel_dp);
 void intel_psr_pre_plane_update(struct intel_atomic_state *state,
 				struct intel_crtc *crtc);
-- 
2.43.0

[PATCH v2 3/8] drm/i915/psr: Compute Panel Replay/Adaptive Sync coexistence behavior

[Jouni Högander]

Currently we are checking Panel Replay capability DPCD register in
intel_alpm.c and writing PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU
and PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE in PR_ALPM_CTL
register base on the informaion. Instead of directly accessing
intel_dp->pr_dpcd compute the behavior during psr_compute_config and store
it in intel_crtc_state.

v2:
  - inline added helpers
  - use intel_dp_attached_dp instead of passing as a parameter

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c     |  6 ++---
 .../drm/i915/display/intel_display_types.h    |  2 ++
 drivers/gpu/drm/i915/display/intel_psr.c      | 27 ++++++++++++++-----
 3 files changed, 24 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index 6372f533f65b5..7ce8c674bb030 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -326,11 +326,9 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
 		if (intel_dp->as_sdp_supported) {
 			u32 pr_alpm_ctl = PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1;
 
-			if (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
-			    DP_PANEL_REPLAY_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPTIVE_SYNC_SDP)
+			if (crtc_state->link_off_after_as_sdp_when_pr_active)
 				pr_alpm_ctl |= PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU;
-			if (!(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
-						DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR))
+			if (crtc_state->disable_as_sdp_when_pr_active)
 				pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE;
 
 			intel_de_write(display, PR_ALPM_CTL(display, cpu_transcoder),
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 82f1aac22d50d..715161ad9e926 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1161,6 +1161,8 @@ struct intel_crtc_state {
 	bool enable_psr2_su_region_et;
 	bool req_psr2_sdp_prior_scanline;
 	bool has_panel_replay;
+	bool link_off_after_as_sdp_when_pr_active;
+	bool disable_as_sdp_when_pr_active;
 	bool wm_level_disabled;
 	bool pkg_c_latency_used;
 	/* Only used for state verification. */
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 5f8df67f9993e..d2d9ad969d9b5 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1708,14 +1708,25 @@ static bool _psr_compute_config(struct intel_dp *intel_dp,
 	return true;
 }
 
-static bool
-_panel_replay_compute_config(struct intel_dp *intel_dp,
-			     struct intel_crtc_state *crtc_state,
-			     const struct drm_connector_state *conn_state)
+static inline bool compute_link_off_after_as_sdp_when_pr_active(struct intel_dp *intel_dp)
+{
+	return (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
+		DP_PANEL_REPLAY_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPTIVE_SYNC_SDP);
+}
+
+static inline bool compute_disable_as_sdp_when_pr_active(struct intel_dp *intel_dp)
+{
+	return !(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
+		 DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR);
+}
+
+static bool _panel_replay_compute_config(struct intel_crtc_state *crtc_state,
+					 const struct drm_connector_state *conn_state)
 {
-	struct intel_display *display = to_intel_display(intel_dp);
 	struct intel_connector *connector =
 		to_intel_connector(conn_state->connector);
+	struct intel_dp *intel_dp = intel_attached_dp(connector);
+	struct intel_display *display = to_intel_display(intel_dp);
 	struct intel_hdcp *hdcp = &connector->hdcp;
 
 	if (!CAN_PANEL_REPLAY(intel_dp))
@@ -1740,6 +1751,9 @@ _panel_replay_compute_config(struct intel_dp *intel_dp,
 		return false;
 	}
 
+	crtc_state->link_off_after_as_sdp_when_pr_active = compute_link_off_after_as_sdp_when_pr_active(intel_dp);
+	crtc_state->disable_as_sdp_when_pr_active = compute_disable_as_sdp_when_pr_active(intel_dp);
+
 	if (!intel_dp_is_edp(intel_dp))
 		return true;
 
@@ -1847,8 +1861,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
 
 	/* Only used for state verification. */
 	crtc_state->panel_replay_dsc_support = intel_dp->psr.sink_panel_replay_dsc_support;
-	crtc_state->has_panel_replay = _panel_replay_compute_config(intel_dp,
-								    crtc_state,
+	crtc_state->has_panel_replay = _panel_replay_compute_config(crtc_state,
 								    conn_state);
 
 	crtc_state->has_psr = crtc_state->has_panel_replay ? true :
-- 
2.43.0

[PATCH v2 4/8] drm/i915/psr: Move pr_dpcd and psr_dpcd to intel_connector

[Jouni Högander]

As a preparation for MST Panel Replay we need to move Panel Replay sink
related data into intel_connector. Move pr_dpcd as well into
intel_connector. Generally this is more correct place for this data so move
psr_dpcd as well.

v2:
  - move pr/psr_dpcd into *_caps substruct
  - drop intel_dp from psr2_su_region_et_valid and
    _panel_replay_compute_su_granularity parameters

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
---
 .../drm/i915/display/intel_display_types.h    |  8 +-
 drivers/gpu/drm/i915/display/intel_psr.c      | 92 ++++++++++---------
 2 files changed, 54 insertions(+), 46 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 715161ad9e926..659bd62f0ad18 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -563,11 +563,16 @@ struct intel_connector {
 		} dsc_branch_caps;
 
 		struct {
+			u8 dpcd[DP_PANEL_REPLAY_CAP_SIZE];
+#define INTEL_PR_DPCD_INDEX(pr_dpcd_register)	((pr_dpcd_register) - DP_PANEL_REPLAY_CAP_SUPPORT)
+
 			u16 su_w_granularity;
 			u16 su_y_granularity;
 		} panel_replay_caps;
 
 		struct {
+			u8 dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
+
 			u16 su_w_granularity;
 			u16 su_y_granularity;
 		} psr_caps;
@@ -1768,9 +1773,6 @@ struct intel_dp {
 	bool needs_modeset_retry;
 	bool use_max_params;
 	u8 dpcd[DP_RECEIVER_CAP_SIZE];
-	u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
-	u8 pr_dpcd[DP_PANEL_REPLAY_CAP_SIZE];
-#define INTEL_PR_DPCD_INDEX(pr_dpcd_register)	((pr_dpcd_register) - DP_PANEL_REPLAY_CAP_SUPPORT)
 
 	u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 	u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index d2d9ad969d9b5..5fc2279cb8b7f 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -506,7 +506,7 @@ static void _psr_compute_su_granularity(struct intel_dp *intel_dp,
 	 * If sink don't have specific granularity requirements set legacy
 	 * ones.
 	 */
-	if (!(intel_dp->psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) {
+	if (!(connector->dp.psr_caps.dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) {
 		/* As PSR2 HW sends full lines, we do not care about x granularity */
 		w = 4;
 		y = 4;
@@ -539,12 +539,12 @@ static void _psr_compute_su_granularity(struct intel_dp *intel_dp,
 }
 
 static enum intel_panel_replay_dsc_support
-compute_pr_dsc_support(struct intel_dp *intel_dp)
+compute_pr_dsc_support(struct intel_connector *connector)
 {
 	u8 pr_dsc_mode;
 	u8 val;
 
-	val = intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)];
+	val = connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)];
 	pr_dsc_mode = REG_FIELD_GET8(DP_PANEL_REPLAY_DSC_DECODE_CAPABILITY_IN_PR_MASK, val);
 
 	switch (pr_dsc_mode) {
@@ -576,13 +576,12 @@ static const char *panel_replay_dsc_support_str(enum intel_panel_replay_dsc_supp
 	};
 }
 
-static void _panel_replay_compute_su_granularity(struct intel_dp *intel_dp,
-						 struct intel_connector *connector)
+static void _panel_replay_compute_su_granularity(struct intel_connector *connector)
 {
 	u16 w;
 	u8 y;
 
-	if (!(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
+	if (!(connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
 	       DP_PANEL_REPLAY_SU_GRANULARITY_REQUIRED)) {
 		w = 4;
 		y = 4;
@@ -593,8 +592,8 @@ static void _panel_replay_compute_su_granularity(struct intel_dp *intel_dp,
 	 * Spec says that if the value read is 0 the default granularity should
 	 * be used instead.
 	 */
-	w = le16_to_cpu(*(__le16 *)&intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_X_GRANULARITY)]) ? : 4;
-	y = intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_Y_GRANULARITY)] ? : 1;
+	w = le16_to_cpu(*(__le16 *)&connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_X_GRANULARITY)]) ? : 4;
+	y = connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_Y_GRANULARITY)] ? : 1;
 
 exit:
 	connector->dp.panel_replay_caps.su_w_granularity = w;
@@ -611,11 +610,12 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp, struct intel_conn
 		return;
 
 	ret = drm_dp_dpcd_read_data(&intel_dp->aux, DP_PANEL_REPLAY_CAP_SUPPORT,
-				    &intel_dp->pr_dpcd, sizeof(intel_dp->pr_dpcd));
+				    &connector->dp.panel_replay_caps.dpcd,
+				    sizeof(connector->dp.panel_replay_caps.dpcd));
 	if (ret < 0)
 		return;
 
-	if (!(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
+	if (!(connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
 	      DP_PANEL_REPLAY_SUPPORT))
 		return;
 
@@ -626,7 +626,7 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp, struct intel_conn
 			return;
 		}
 
-		if (!(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
+		if (!(connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
 		      DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT)) {
 			drm_dbg_kms(display->drm,
 				    "Panel doesn't support early transport, eDP Panel Replay not possible\n");
@@ -636,14 +636,14 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp, struct intel_conn
 
 	intel_dp->psr.sink_panel_replay_support = true;
 
-	if (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
+	if (connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
 	    DP_PANEL_REPLAY_SU_SUPPORT) {
 		intel_dp->psr.sink_panel_replay_su_support = true;
 
-		_panel_replay_compute_su_granularity(intel_dp, connector);
+		_panel_replay_compute_su_granularity(connector);
 	}
 
-	intel_dp->psr.sink_panel_replay_dsc_support = compute_pr_dsc_support(intel_dp);
+	intel_dp->psr.sink_panel_replay_dsc_support = compute_pr_dsc_support(connector);
 
 	drm_dbg_kms(display->drm,
 		    "Panel replay %sis supported by panel (in DSC mode: %s)\n",
@@ -657,16 +657,16 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *co
 	struct intel_display *display = to_intel_display(intel_dp);
 	int ret;
 
-	ret = drm_dp_dpcd_read_data(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
-				    sizeof(intel_dp->psr_dpcd));
+	ret = drm_dp_dpcd_read_data(&intel_dp->aux, DP_PSR_SUPPORT, connector->dp.psr_caps.dpcd,
+				    sizeof(connector->dp.psr_caps.dpcd));
 	if (ret < 0)
 		return;
 
-	if (!intel_dp->psr_dpcd[0])
+	if (!connector->dp.psr_caps.dpcd[0])
 		return;
 
 	drm_dbg_kms(display->drm, "eDP panel supports PSR version %x\n",
-		    intel_dp->psr_dpcd[0]);
+		    connector->dp.psr_caps.dpcd[0]);
 
 	if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) {
 		drm_dbg_kms(display->drm,
@@ -685,8 +685,8 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *co
 		intel_dp_get_sink_sync_latency(intel_dp);
 
 	if (DISPLAY_VER(display) >= 9 &&
-	    intel_dp->psr_dpcd[0] >= DP_PSR2_WITH_Y_COORD_IS_SUPPORTED) {
-		bool y_req = intel_dp->psr_dpcd[1] &
+	    connector->dp.psr_caps.dpcd[0] >= DP_PSR2_WITH_Y_COORD_IS_SUPPORTED) {
+		bool y_req = connector->dp.psr_caps.dpcd[1] &
 			     DP_PSR2_SU_Y_COORDINATE_REQUIRED;
 
 		/*
@@ -754,8 +754,9 @@ static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
 		       aux_ctl);
 }
 
-static bool psr2_su_region_et_valid(struct intel_dp *intel_dp, bool panel_replay)
+static bool psr2_su_region_et_valid(struct intel_connector *connector, bool panel_replay)
 {
+	struct intel_dp *intel_dp = intel_attached_dp(connector);
 	struct intel_display *display = to_intel_display(intel_dp);
 
 	if (DISPLAY_VER(display) < 20 || !intel_dp_is_edp(intel_dp) ||
@@ -763,9 +764,9 @@ static bool psr2_su_region_et_valid(struct intel_dp *intel_dp, bool panel_replay
 		return false;
 
 	return panel_replay ?
-		intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
+		connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
 		DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT :
-		intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED;
+		connector->dp.psr_caps.dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED;
 }
 
 static void _panel_replay_enable_sink(struct intel_dp *intel_dp,
@@ -1361,16 +1362,18 @@ static bool _compute_psr2_sdp_prior_scanline_indication(struct intel_dp *intel_d
 }
 
 static int intel_psr_entry_setup_frames(struct intel_dp *intel_dp,
+					struct drm_connector_state *conn_state,
 					const struct drm_display_mode *adjusted_mode)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
-	int psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
+	struct intel_connector *connector = to_intel_connector(conn_state->connector);
+	int psr_setup_time = drm_dp_psr_setup_time(connector->dp.psr_caps.dpcd);
 	int entry_setup_frames = 0;
 
 	if (psr_setup_time < 0) {
 		drm_dbg_kms(display->drm,
 			    "PSR condition failed: Invalid PSR setup time (0x%02x)\n",
-			    intel_dp->psr_dpcd[1]);
+			    connector->dp.psr_caps.dpcd[1]);
 		return -ETIME;
 	}
 
@@ -1668,8 +1671,8 @@ static bool intel_sel_update_config_valid(struct intel_crtc_state *crtc_state,
 		goto unsupported;
 	}
 
-	crtc_state->enable_psr2_su_region_et =
-		psr2_su_region_et_valid(intel_dp, crtc_state->has_panel_replay);
+	crtc_state->enable_psr2_su_region_et = psr2_su_region_et_valid(connector,
+								       crtc_state->has_panel_replay);
 
 	return true;
 
@@ -1679,7 +1682,8 @@ static bool intel_sel_update_config_valid(struct intel_crtc_state *crtc_state,
 }
 
 static bool _psr_compute_config(struct intel_dp *intel_dp,
-				struct intel_crtc_state *crtc_state)
+				struct intel_crtc_state *crtc_state,
+				struct drm_connector_state *conn_state)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
@@ -1694,7 +1698,7 @@ static bool _psr_compute_config(struct intel_dp *intel_dp,
 	if (crtc_state->vrr.enable)
 		return false;
 
-	entry_setup_frames = intel_psr_entry_setup_frames(intel_dp, adjusted_mode);
+	entry_setup_frames = intel_psr_entry_setup_frames(intel_dp, conn_state, adjusted_mode);
 
 	if (entry_setup_frames >= 0) {
 		intel_dp->psr.entry_setup_frames = entry_setup_frames;
@@ -1708,15 +1712,15 @@ static bool _psr_compute_config(struct intel_dp *intel_dp,
 	return true;
 }
 
-static inline bool compute_link_off_after_as_sdp_when_pr_active(struct intel_dp *intel_dp)
+static inline bool compute_link_off_after_as_sdp_when_pr_active(struct intel_connector *connector)
 {
-	return (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
+	return (connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
 		DP_PANEL_REPLAY_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPTIVE_SYNC_SDP);
 }
 
-static inline bool compute_disable_as_sdp_when_pr_active(struct intel_dp *intel_dp)
+static inline bool compute_disable_as_sdp_when_pr_active(struct intel_connector *connector)
 {
-	return !(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
+	return !(connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
 		 DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR);
 }
 
@@ -1751,8 +1755,8 @@ static bool _panel_replay_compute_config(struct intel_crtc_state *crtc_state,
 		return false;
 	}
 
-	crtc_state->link_off_after_as_sdp_when_pr_active = compute_link_off_after_as_sdp_when_pr_active(intel_dp);
-	crtc_state->disable_as_sdp_when_pr_active = compute_disable_as_sdp_when_pr_active(intel_dp);
+	crtc_state->link_off_after_as_sdp_when_pr_active = compute_link_off_after_as_sdp_when_pr_active(connector);
+	crtc_state->disable_as_sdp_when_pr_active = compute_disable_as_sdp_when_pr_active(connector);
 
 	if (!intel_dp_is_edp(intel_dp))
 		return true;
@@ -1865,7 +1869,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
 								    conn_state);
 
 	crtc_state->has_psr = crtc_state->has_panel_replay ? true :
-		_psr_compute_config(intel_dp, crtc_state);
+		_psr_compute_config(intel_dp, crtc_state, conn_state);
 
 	if (!crtc_state->has_psr)
 		return;
@@ -4114,6 +4118,7 @@ psr_source_status(struct intel_dp *intel_dp, struct seq_file *m)
 }
 
 static void intel_psr_sink_capability(struct intel_dp *intel_dp,
+				      struct intel_connector *connector,
 				      struct seq_file *m)
 {
 	struct intel_psr *psr = &intel_dp->psr;
@@ -4122,15 +4127,15 @@ static void intel_psr_sink_capability(struct intel_dp *intel_dp,
 		   str_yes_no(psr->sink_support));
 
 	if (psr->sink_support)
-		seq_printf(m, " [0x%02x]", intel_dp->psr_dpcd[0]);
-	if (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED)
+		seq_printf(m, " [0x%02x]", connector->dp.psr_caps.dpcd[0]);
+	if (connector->dp.psr_caps.dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED)
 		seq_printf(m, " (Early Transport)");
 	seq_printf(m, ", Panel Replay = %s", str_yes_no(psr->sink_panel_replay_support));
 	seq_printf(m, ", Panel Replay Selective Update = %s",
 		   str_yes_no(psr->sink_panel_replay_su_support));
 	seq_printf(m, ", Panel Replay DSC support = %s",
 		   panel_replay_dsc_support_str(psr->sink_panel_replay_dsc_support));
-	if (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
+	if (connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
 	    DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT)
 		seq_printf(m, " (Early Transport)");
 	seq_printf(m, "\n");
@@ -4168,7 +4173,8 @@ static void intel_psr_print_mode(struct intel_dp *intel_dp,
 		seq_printf(m, "  %s\n", psr->no_psr_reason);
 }
 
-static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp)
+static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp,
+			    struct intel_connector *connector)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
 	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
@@ -4177,7 +4183,7 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp)
 	bool enabled;
 	u32 val, psr2_ctl;
 
-	intel_psr_sink_capability(intel_dp, m);
+	intel_psr_sink_capability(intel_dp, connector, m);
 
 	if (!(psr->sink_support || psr->sink_panel_replay_support))
 		return 0;
@@ -4293,7 +4299,7 @@ static int i915_edp_psr_status_show(struct seq_file *m, void *data)
 	if (!intel_dp)
 		return -ENODEV;
 
-	return intel_psr_status(m, intel_dp);
+	return intel_psr_status(m, intel_dp, intel_dp->attached_connector);
 }
 DEFINE_SHOW_ATTRIBUTE(i915_edp_psr_status);
 
@@ -4427,7 +4433,7 @@ static int i915_psr_status_show(struct seq_file *m, void *data)
 	struct intel_connector *connector = m->private;
 	struct intel_dp *intel_dp = intel_attached_dp(connector);
 
-	return intel_psr_status(m, intel_dp);
+	return intel_psr_status(m, intel_dp, connector);
 }
 DEFINE_SHOW_ATTRIBUTE(i915_psr_status);
 
-- 
2.43.0

[PATCH v2 5/8] drm/i915/psr: Clear pr_dpcd as well on disconnect

[Jouni Högander]

Currently we are leaving pr_dpcd containing Panel Replay capability DPCD
registers as it is on disconnect. Clear it as well on disconnect.

v2: add FIXME

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index dcceb0ae2a56d..3838835e7e7eb 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6048,7 +6048,15 @@ intel_dp_detect(struct drm_connector *_connector,
 
 	if (status == connector_status_disconnected) {
 		intel_dp_test_reset(intel_dp);
+		/*
+		 * FIXME: Resetting these caps here cause
+		 * state computation fail if the connector need to be
+		 * modeset after sink disconnect. Move resetting them
+		 * to where new sink is connected.
+		 */
 		memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd));
+		memset(connector->dp.panel_replay_caps.dpcd, 0,
+		       sizeof(connector->dp.panel_replay_caps.dpcd));
 		intel_dp->psr.sink_panel_replay_support = false;
 		intel_dp->psr.sink_panel_replay_su_support = false;
 		intel_dp->psr.sink_panel_replay_dsc_support =
-- 
2.43.0

Re: [PATCH v2 5/8] drm/i915/psr: Clear pr_dpcd as well on disconnect

[Imre Deak]

On Wed, Dec 03, 2025 at 12:31:31PM +0200, Jouni Högander wrote:
> Currently we are leaving pr_dpcd containing Panel Replay capability DPCD
> registers as it is on disconnect. Clear it as well on disconnect.
> 
> v2: add FIXME
> 
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index dcceb0ae2a56d..3838835e7e7eb 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -6048,7 +6048,15 @@ intel_dp_detect(struct drm_connector *_connector,
>  
>  	if (status == connector_status_disconnected) {
>  		intel_dp_test_reset(intel_dp);
> +		/*
> +		 * FIXME: Resetting these caps here cause
> +		 * state computation fail if the connector need to be
> +		 * modeset after sink disconnect. Move resetting them
> +		 * to where new sink is connected.
> +		 */
>  		memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd));
> +		memset(connector->dp.panel_replay_caps.dpcd, 0,
> +		       sizeof(connector->dp.panel_replay_caps.dpcd));
>  		intel_dp->psr.sink_panel_replay_support = false;
>  		intel_dp->psr.sink_panel_replay_su_support = false;
>  		intel_dp->psr.sink_panel_replay_dsc_support =
> -- 
> 2.43.0
> 

[PATCH v2 6/8] drm/i915/psr: Move Panel Replay DSC sink support data to intel_connector

[Jouni Högander]

As a preparation for MST Panel Replay we need to move Panel Replay sink
related data into intel_connector. Move Panel Replay DSC sink support data
as well into intel_connector.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
---
 .../gpu/drm/i915/display/intel_display_types.h   | 15 ++++++++-------
 drivers/gpu/drm/i915/display/intel_dp.c          |  2 +-
 drivers/gpu/drm/i915/display/intel_psr.c         | 16 ++++++++--------
 3 files changed, 17 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 659bd62f0ad18..b5641698db695 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -509,6 +509,12 @@ struct intel_hdcp {
 	bool force_hdcp14;
 };
 
+enum intel_panel_replay_dsc_support {
+	INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED,
+	INTEL_DP_PANEL_REPLAY_DSC_FULL_FRAME_ONLY,
+	INTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE,
+};
+
 struct intel_connector {
 	struct drm_connector base;
 	/*
@@ -566,6 +572,8 @@ struct intel_connector {
 			u8 dpcd[DP_PANEL_REPLAY_CAP_SIZE];
 #define INTEL_PR_DPCD_INDEX(pr_dpcd_register)	((pr_dpcd_register) - DP_PANEL_REPLAY_CAP_SUPPORT)
 
+			enum intel_panel_replay_dsc_support dsc_support;
+
 			u16 su_w_granularity;
 			u16 su_y_granularity;
 		} panel_replay_caps;
@@ -969,12 +977,6 @@ struct intel_csc_matrix {
 	u16 postoff[3];
 };
 
-enum intel_panel_replay_dsc_support {
-	INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED,
-	INTEL_DP_PANEL_REPLAY_DSC_FULL_FRAME_ONLY,
-	INTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE,
-};
-
 struct scaler_filter_coeff {
 	u16 sign;
 	u16 exp;
@@ -1746,7 +1748,6 @@ struct intel_psr {
 	bool source_panel_replay_support;
 	bool sink_panel_replay_support;
 	bool sink_panel_replay_su_support;
-	enum intel_panel_replay_dsc_support sink_panel_replay_dsc_support;
 	bool panel_replay_enabled;
 	u32 dc3co_exitline;
 	u32 dc3co_exit_delay;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 3838835e7e7eb..8c5ddf0b09d25 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6059,7 +6059,7 @@ intel_dp_detect(struct drm_connector *_connector,
 		       sizeof(connector->dp.panel_replay_caps.dpcd));
 		intel_dp->psr.sink_panel_replay_support = false;
 		intel_dp->psr.sink_panel_replay_su_support = false;
-		intel_dp->psr.sink_panel_replay_dsc_support =
+		connector->dp.panel_replay_caps.dsc_support =
 			INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED;
 
 		intel_dp_mst_disconnect(intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 5fc2279cb8b7f..1d3864405c850 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -643,13 +643,13 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp, struct intel_conn
 		_panel_replay_compute_su_granularity(connector);
 	}
 
-	intel_dp->psr.sink_panel_replay_dsc_support = compute_pr_dsc_support(connector);
+	connector->dp.panel_replay_caps.dsc_support = compute_pr_dsc_support(connector);
 
 	drm_dbg_kms(display->drm,
 		    "Panel replay %sis supported by panel (in DSC mode: %s)\n",
 		    intel_dp->psr.sink_panel_replay_su_support ?
 		    "selective_update " : "",
-		    panel_replay_dsc_support_str(intel_dp->psr.sink_panel_replay_dsc_support));
+		    panel_replay_dsc_support_str(connector->dp.panel_replay_caps.dsc_support));
 }
 
 static void _psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
@@ -1651,7 +1651,7 @@ static bool intel_sel_update_config_valid(struct intel_crtc_state *crtc_state,
 			goto unsupported;
 
 		if (intel_dsc_enabled_on_link(crtc_state) &&
-		    intel_dp->psr.sink_panel_replay_dsc_support !=
+		    connector->dp.panel_replay_caps.dsc_support !=
 		    INTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE) {
 			drm_dbg_kms(display->drm,
 				    "Selective update with Panel Replay not enabled because it's not supported with DSC\n");
@@ -1748,7 +1748,7 @@ static bool _panel_replay_compute_config(struct intel_crtc_state *crtc_state,
 	}
 
 	if (intel_dsc_enabled_on_link(crtc_state) &&
-	    intel_dp->psr.sink_panel_replay_dsc_support ==
+	    connector->dp.panel_replay_caps.dsc_support ==
 	    INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED) {
 		drm_dbg_kms(display->drm,
 			    "Panel Replay not enabled because it's not supported with DSC\n");
@@ -1833,6 +1833,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
 			      struct drm_connector_state *conn_state)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
+	struct intel_connector *connector = to_intel_connector(conn_state->connector);
 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
 
 	if (!psr_global_enabled(intel_dp)) {
@@ -1864,9 +1865,8 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
 	}
 
 	/* Only used for state verification. */
-	crtc_state->panel_replay_dsc_support = intel_dp->psr.sink_panel_replay_dsc_support;
-	crtc_state->has_panel_replay = _panel_replay_compute_config(crtc_state,
-								    conn_state);
+	crtc_state->panel_replay_dsc_support = connector->dp.panel_replay_caps.dsc_support;
+	crtc_state->has_panel_replay = _panel_replay_compute_config(crtc_state, conn_state);
 
 	crtc_state->has_psr = crtc_state->has_panel_replay ? true :
 		_psr_compute_config(intel_dp, crtc_state, conn_state);
@@ -4134,7 +4134,7 @@ static void intel_psr_sink_capability(struct intel_dp *intel_dp,
 	seq_printf(m, ", Panel Replay Selective Update = %s",
 		   str_yes_no(psr->sink_panel_replay_su_support));
 	seq_printf(m, ", Panel Replay DSC support = %s",
-		   panel_replay_dsc_support_str(psr->sink_panel_replay_dsc_support));
+		   panel_replay_dsc_support_str(connector->dp.panel_replay_caps.dsc_support));
 	if (connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
 	    DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT)
 		seq_printf(m, " (Early Transport)");
-- 
2.43.0

[PATCH v2 7/8] drm/i915/psr: Move sink PSR and Panel Replay booleans to intel_connector

[Jouni Högander]

As a preparation for MST Panel Replay we need to move Panel Replay sink
related data into intel_connector. Move sink support booleans as well
into intel_connector. Generally this is more correct place for this data so
move PSR versions as well.

Still sink_support and sink_panel_replay_support are kept to keep CAN_PSR
and CAN_PANEL_REPLAY macros. Plan is to keep them that way as they are
widely used from patch where connector is not available.

Later we might want to clear intel_dp->psr.sink_panel_replay_support if any
of the devices in branch is not supporting Panel Replay (mst).

v2:
  - commit message updated
  - Extra w/s removed

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 .../drm/i915/display/intel_display_types.h    |  7 ++-
 drivers/gpu/drm/i915/display/intel_dp.c       |  3 +-
 drivers/gpu/drm/i915/display/intel_psr.c      | 44 +++++++++++--------
 3 files changed, 32 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index b5641698db695..fb1c8b2d3979f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -572,6 +572,8 @@ struct intel_connector {
 			u8 dpcd[DP_PANEL_REPLAY_CAP_SIZE];
 #define INTEL_PR_DPCD_INDEX(pr_dpcd_register)	((pr_dpcd_register) - DP_PANEL_REPLAY_CAP_SUPPORT)
 
+			bool support;
+			bool su_support;
 			enum intel_panel_replay_dsc_support dsc_support;
 
 			u16 su_w_granularity;
@@ -581,6 +583,9 @@ struct intel_connector {
 		struct {
 			u8 dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 
+			bool support;
+			bool su_support;
+
 			u16 su_w_granularity;
 			u16 su_y_granularity;
 		} psr_caps;
@@ -1731,7 +1736,6 @@ struct intel_psr {
 	bool active;
 	struct work_struct work;
 	unsigned int busy_frontbuffer_bits;
-	bool sink_psr2_support;
 	bool link_standby;
 	bool sel_update_enabled;
 	bool psr2_sel_fetch_enabled;
@@ -1747,7 +1751,6 @@ struct intel_psr {
 	u16 su_y_granularity;
 	bool source_panel_replay_support;
 	bool sink_panel_replay_support;
-	bool sink_panel_replay_su_support;
 	bool panel_replay_enabled;
 	u32 dc3co_exitline;
 	u32 dc3co_exit_delay;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 8c5ddf0b09d25..4419954867455 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6058,7 +6058,8 @@ intel_dp_detect(struct drm_connector *_connector,
 		memset(connector->dp.panel_replay_caps.dpcd, 0,
 		       sizeof(connector->dp.panel_replay_caps.dpcd));
 		intel_dp->psr.sink_panel_replay_support = false;
-		intel_dp->psr.sink_panel_replay_su_support = false;
+		connector->dp.panel_replay_caps.support = false;
+		connector->dp.panel_replay_caps.su_support = false;
 		connector->dp.panel_replay_caps.dsc_support =
 			INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED;
 
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 1d3864405c850..c01e06f9cf643 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -634,11 +634,12 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp, struct intel_conn
 		}
 	}
 
+	connector->dp.panel_replay_caps.support = true;
 	intel_dp->psr.sink_panel_replay_support = true;
 
 	if (connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
 	    DP_PANEL_REPLAY_SU_SUPPORT) {
-		intel_dp->psr.sink_panel_replay_su_support = true;
+		connector->dp.panel_replay_caps.su_support = true;
 
 		_panel_replay_compute_su_granularity(connector);
 	}
@@ -647,7 +648,7 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp, struct intel_conn
 
 	drm_dbg_kms(display->drm,
 		    "Panel replay %sis supported by panel (in DSC mode: %s)\n",
-		    intel_dp->psr.sink_panel_replay_su_support ?
+		    connector->dp.panel_replay_caps.su_support ?
 		    "selective_update " : "",
 		    panel_replay_dsc_support_str(connector->dp.panel_replay_caps.dsc_support));
 }
@@ -680,7 +681,9 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *co
 		return;
 	}
 
+	connector->dp.psr_caps.support = true;
 	intel_dp->psr.sink_support = true;
+
 	intel_dp->psr.sink_sync_latency =
 		intel_dp_get_sink_sync_latency(intel_dp);
 
@@ -700,13 +703,13 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *co
 		 * Y-coordinate requirement panels we would need to enable
 		 * GTC first.
 		 */
-		intel_dp->psr.sink_psr2_support = y_req &&
+		connector->dp.psr_caps.su_support = y_req &&
 			intel_alpm_aux_wake_supported(intel_dp);
 		drm_dbg_kms(display->drm, "PSR2 %ssupported\n",
-			    intel_dp->psr.sink_psr2_support ? "" : "not ");
+			    connector->dp.psr_caps.su_support ? "" : "not ");
 	}
 
-	if (intel_dp->psr.sink_psr2_support)
+	if (connector->dp.psr_caps.su_support)
 		_psr_compute_su_granularity(intel_dp, connector);
 }
 
@@ -1514,14 +1517,16 @@ static bool alpm_config_valid(struct intel_dp *intel_dp,
 }
 
 static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
-				    struct intel_crtc_state *crtc_state)
+				    struct intel_crtc_state *crtc_state,
+				    struct drm_connector_state *conn_state)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
+	struct intel_connector *connector = to_intel_connector(conn_state->connector);
 	int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
 	int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
 	int psr_max_h = 0, psr_max_v = 0, max_bpp = 0;
 
-	if (!intel_dp->psr.sink_psr2_support || display->params.enable_psr == 1)
+	if (!connector->dp.psr_caps.su_support || display->params.enable_psr == 1)
 		return false;
 
 	/* JSL and EHL only supports eDP 1.3 */
@@ -1634,7 +1639,8 @@ static bool intel_sel_update_config_valid(struct intel_crtc_state *crtc_state,
 		goto unsupported;
 	}
 
-	if (!crtc_state->has_panel_replay && !intel_psr2_config_valid(intel_dp, crtc_state))
+	if (!crtc_state->has_panel_replay && !intel_psr2_config_valid(intel_dp, crtc_state,
+								      conn_state))
 		goto unsupported;
 
 	if (!_compute_psr2_sdp_prior_scanline_indication(intel_dp, crtc_state)) {
@@ -1647,7 +1653,7 @@ static bool intel_sel_update_config_valid(struct intel_crtc_state *crtc_state,
 		if (DISPLAY_VER(display) < 14)
 			goto unsupported;
 
-		if (!intel_dp->psr.sink_panel_replay_su_support)
+		if (!connector->dp.panel_replay_caps.su_support)
 			goto unsupported;
 
 		if (intel_dsc_enabled_on_link(crtc_state) &&
@@ -1736,6 +1742,9 @@ static bool _panel_replay_compute_config(struct intel_crtc_state *crtc_state,
 	if (!CAN_PANEL_REPLAY(intel_dp))
 		return false;
 
+	if (!connector->dp.panel_replay_caps.support)
+		return false;
+
 	if (!panel_replay_global_enabled(intel_dp)) {
 		drm_dbg_kms(display->drm, "Panel Replay disabled by flag\n");
 		return false;
@@ -4117,22 +4126,19 @@ psr_source_status(struct intel_dp *intel_dp, struct seq_file *m)
 	seq_printf(m, "Source PSR/PanelReplay status: %s [0x%08x]\n", status, val);
 }
 
-static void intel_psr_sink_capability(struct intel_dp *intel_dp,
-				      struct intel_connector *connector,
+static void intel_psr_sink_capability(struct intel_connector *connector,
 				      struct seq_file *m)
 {
-	struct intel_psr *psr = &intel_dp->psr;
-
 	seq_printf(m, "Sink support: PSR = %s",
-		   str_yes_no(psr->sink_support));
+		   str_yes_no(connector->dp.psr_caps.support));
 
-	if (psr->sink_support)
+	if (connector->dp.psr_caps.support)
 		seq_printf(m, " [0x%02x]", connector->dp.psr_caps.dpcd[0]);
 	if (connector->dp.psr_caps.dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED)
 		seq_printf(m, " (Early Transport)");
-	seq_printf(m, ", Panel Replay = %s", str_yes_no(psr->sink_panel_replay_support));
+	seq_printf(m, ", Panel Replay = %s", str_yes_no(connector->dp.panel_replay_caps.support));
 	seq_printf(m, ", Panel Replay Selective Update = %s",
-		   str_yes_no(psr->sink_panel_replay_su_support));
+		   str_yes_no(connector->dp.panel_replay_caps.su_support));
 	seq_printf(m, ", Panel Replay DSC support = %s",
 		   panel_replay_dsc_support_str(connector->dp.panel_replay_caps.dsc_support));
 	if (connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
@@ -4183,9 +4189,9 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp,
 	bool enabled;
 	u32 val, psr2_ctl;
 
-	intel_psr_sink_capability(intel_dp, connector, m);
+	intel_psr_sink_capability(connector, m);
 
-	if (!(psr->sink_support || psr->sink_panel_replay_support))
+	if (!(connector->dp.psr_caps.support || connector->dp.panel_replay_caps.support))
 		return 0;
 
 	wakeref = intel_display_rpm_get(display);
-- 
2.43.0

Re: [PATCH v2 7/8] drm/i915/psr: Move sink PSR and Panel Replay booleans to intel_connector

[Imre Deak]

On Wed, Dec 03, 2025 at 12:31:33PM +0200, Jouni Högander wrote:
> As a preparation for MST Panel Replay we need to move Panel Replay sink
> related data into intel_connector. Move sink support booleans as well
> into intel_connector. Generally this is more correct place for this data so
> move PSR versions as well.
> 
> Still sink_support and sink_panel_replay_support are kept to keep CAN_PSR
> and CAN_PANEL_REPLAY macros. Plan is to keep them that way as they are
> widely used from patch where connector is not available.
> 
> Later we might want to clear intel_dp->psr.sink_panel_replay_support if any
> of the devices in branch is not supporting Panel Replay (mst).
> 
> v2:
>   - commit message updated
>   - Extra w/s removed
> 
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  .../drm/i915/display/intel_display_types.h    |  7 ++-
>  drivers/gpu/drm/i915/display/intel_dp.c       |  3 +-
>  drivers/gpu/drm/i915/display/intel_psr.c      | 44 +++++++++++--------
>  3 files changed, 32 insertions(+), 22 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index b5641698db695..fb1c8b2d3979f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -572,6 +572,8 @@ struct intel_connector {
>  			u8 dpcd[DP_PANEL_REPLAY_CAP_SIZE];
>  #define INTEL_PR_DPCD_INDEX(pr_dpcd_register)	((pr_dpcd_register) - DP_PANEL_REPLAY_CAP_SUPPORT)
>  
> +			bool support;
> +			bool su_support;
>  			enum intel_panel_replay_dsc_support dsc_support;
>  
>  			u16 su_w_granularity;
> @@ -581,6 +583,9 @@ struct intel_connector {
>  		struct {
>  			u8 dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
>  
> +			bool support;
> +			bool su_support;
> +
>  			u16 su_w_granularity;
>  			u16 su_y_granularity;
>  		} psr_caps;
> @@ -1731,7 +1736,6 @@ struct intel_psr {
>  	bool active;
>  	struct work_struct work;
>  	unsigned int busy_frontbuffer_bits;
> -	bool sink_psr2_support;
>  	bool link_standby;
>  	bool sel_update_enabled;
>  	bool psr2_sel_fetch_enabled;
> @@ -1747,7 +1751,6 @@ struct intel_psr {
>  	u16 su_y_granularity;
>  	bool source_panel_replay_support;
>  	bool sink_panel_replay_support;
> -	bool sink_panel_replay_su_support;
>  	bool panel_replay_enabled;
>  	u32 dc3co_exitline;
>  	u32 dc3co_exit_delay;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 8c5ddf0b09d25..4419954867455 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -6058,7 +6058,8 @@ intel_dp_detect(struct drm_connector *_connector,
>  		memset(connector->dp.panel_replay_caps.dpcd, 0,
>  		       sizeof(connector->dp.panel_replay_caps.dpcd));
>  		intel_dp->psr.sink_panel_replay_support = false;
> -		intel_dp->psr.sink_panel_replay_su_support = false;
> +		connector->dp.panel_replay_caps.support = false;
> +		connector->dp.panel_replay_caps.su_support = false;
>  		connector->dp.panel_replay_caps.dsc_support =
>  			INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED;
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 1d3864405c850..c01e06f9cf643 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -634,11 +634,12 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp, struct intel_conn
>  		}
>  	}
>  
> +	connector->dp.panel_replay_caps.support = true;
>  	intel_dp->psr.sink_panel_replay_support = true;
>  
>  	if (connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
>  	    DP_PANEL_REPLAY_SU_SUPPORT) {
> -		intel_dp->psr.sink_panel_replay_su_support = true;
> +		connector->dp.panel_replay_caps.su_support = true;
>  
>  		_panel_replay_compute_su_granularity(connector);
>  	}
> @@ -647,7 +648,7 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp, struct intel_conn
>  
>  	drm_dbg_kms(display->drm,
>  		    "Panel replay %sis supported by panel (in DSC mode: %s)\n",
> -		    intel_dp->psr.sink_panel_replay_su_support ?
> +		    connector->dp.panel_replay_caps.su_support ?
>  		    "selective_update " : "",
>  		    panel_replay_dsc_support_str(connector->dp.panel_replay_caps.dsc_support));
>  }
> @@ -680,7 +681,9 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *co
>  		return;
>  	}
>  
> +	connector->dp.psr_caps.support = true;
>  	intel_dp->psr.sink_support = true;
> +
>  	intel_dp->psr.sink_sync_latency =
>  		intel_dp_get_sink_sync_latency(intel_dp);
>  
> @@ -700,13 +703,13 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *co
>  		 * Y-coordinate requirement panels we would need to enable
>  		 * GTC first.
>  		 */
> -		intel_dp->psr.sink_psr2_support = y_req &&
> +		connector->dp.psr_caps.su_support = y_req &&
>  			intel_alpm_aux_wake_supported(intel_dp);
>  		drm_dbg_kms(display->drm, "PSR2 %ssupported\n",
> -			    intel_dp->psr.sink_psr2_support ? "" : "not ");
> +			    connector->dp.psr_caps.su_support ? "" : "not ");
>  	}
>  
> -	if (intel_dp->psr.sink_psr2_support)
> +	if (connector->dp.psr_caps.su_support)
>  		_psr_compute_su_granularity(intel_dp, connector);
>  }
>  
> @@ -1514,14 +1517,16 @@ static bool alpm_config_valid(struct intel_dp *intel_dp,
>  }
>  
>  static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
> -				    struct intel_crtc_state *crtc_state)
> +				    struct intel_crtc_state *crtc_state,
> +				    struct drm_connector_state *conn_state)
>  {
>  	struct intel_display *display = to_intel_display(intel_dp);
> +	struct intel_connector *connector = to_intel_connector(conn_state->connector);
>  	int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
>  	int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
>  	int psr_max_h = 0, psr_max_v = 0, max_bpp = 0;
>  
> -	if (!intel_dp->psr.sink_psr2_support || display->params.enable_psr == 1)
> +	if (!connector->dp.psr_caps.su_support || display->params.enable_psr == 1)
>  		return false;
>  
>  	/* JSL and EHL only supports eDP 1.3 */
> @@ -1634,7 +1639,8 @@ static bool intel_sel_update_config_valid(struct intel_crtc_state *crtc_state,
>  		goto unsupported;
>  	}
>  
> -	if (!crtc_state->has_panel_replay && !intel_psr2_config_valid(intel_dp, crtc_state))
> +	if (!crtc_state->has_panel_replay && !intel_psr2_config_valid(intel_dp, crtc_state,
> +								      conn_state))
>  		goto unsupported;
>  
>  	if (!_compute_psr2_sdp_prior_scanline_indication(intel_dp, crtc_state)) {
> @@ -1647,7 +1653,7 @@ static bool intel_sel_update_config_valid(struct intel_crtc_state *crtc_state,
>  		if (DISPLAY_VER(display) < 14)
>  			goto unsupported;
>  
> -		if (!intel_dp->psr.sink_panel_replay_su_support)
> +		if (!connector->dp.panel_replay_caps.su_support)
>  			goto unsupported;
>  
>  		if (intel_dsc_enabled_on_link(crtc_state) &&
> @@ -1736,6 +1742,9 @@ static bool _panel_replay_compute_config(struct intel_crtc_state *crtc_state,
>  	if (!CAN_PANEL_REPLAY(intel_dp))
>  		return false;
>  
> +	if (!connector->dp.panel_replay_caps.support)
> +		return false;
> +
>  	if (!panel_replay_global_enabled(intel_dp)) {
>  		drm_dbg_kms(display->drm, "Panel Replay disabled by flag\n");
>  		return false;
> @@ -4117,22 +4126,19 @@ psr_source_status(struct intel_dp *intel_dp, struct seq_file *m)
>  	seq_printf(m, "Source PSR/PanelReplay status: %s [0x%08x]\n", status, val);
>  }
>  
> -static void intel_psr_sink_capability(struct intel_dp *intel_dp,
> -				      struct intel_connector *connector,
> +static void intel_psr_sink_capability(struct intel_connector *connector,
>  				      struct seq_file *m)
>  {
> -	struct intel_psr *psr = &intel_dp->psr;
> -
>  	seq_printf(m, "Sink support: PSR = %s",
> -		   str_yes_no(psr->sink_support));
> +		   str_yes_no(connector->dp.psr_caps.support));
>  
> -	if (psr->sink_support)
> +	if (connector->dp.psr_caps.support)
>  		seq_printf(m, " [0x%02x]", connector->dp.psr_caps.dpcd[0]);
>  	if (connector->dp.psr_caps.dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED)
>  		seq_printf(m, " (Early Transport)");
> -	seq_printf(m, ", Panel Replay = %s", str_yes_no(psr->sink_panel_replay_support));
> +	seq_printf(m, ", Panel Replay = %s", str_yes_no(connector->dp.panel_replay_caps.support));
>  	seq_printf(m, ", Panel Replay Selective Update = %s",
> -		   str_yes_no(psr->sink_panel_replay_su_support));
> +		   str_yes_no(connector->dp.panel_replay_caps.su_support));
>  	seq_printf(m, ", Panel Replay DSC support = %s",
>  		   panel_replay_dsc_support_str(connector->dp.panel_replay_caps.dsc_support));
>  	if (connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
> @@ -4183,9 +4189,9 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp,
>  	bool enabled;
>  	u32 val, psr2_ctl;
>  
> -	intel_psr_sink_capability(intel_dp, connector, m);
> +	intel_psr_sink_capability(connector, m);
>  
> -	if (!(psr->sink_support || psr->sink_panel_replay_support))
> +	if (!(connector->dp.psr_caps.support || connector->dp.panel_replay_caps.support))
>  		return 0;
>  
>  	wakeref = intel_display_rpm_get(display);
> -- 
> 2.43.0
> 

Re: [PATCH v2 7/8] drm/i915/psr: Move sink PSR and Panel Replay booleans to intel_connector

[Hogander, Jouni]

On Wed, 2025-12-03 at 16:58 +0200, Imre Deak wrote:
> On Wed, Dec 03, 2025 at 12:31:33PM +0200, Jouni Högander wrote:
> > As a preparation for MST Panel Replay we need to move Panel Replay
> > sink
> > related data into intel_connector. Move sink support booleans as
> > well
> > into intel_connector. Generally this is more correct place for this
> > data so
> > move PSR versions as well.
> > 
> > Still sink_support and sink_panel_replay_support are kept to keep
> > CAN_PSR
> > and CAN_PANEL_REPLAY macros. Plan is to keep them that way as they
> > are
> > widely used from patch where connector is not available.
> > 
> > Later we might want to clear intel_dp-
> > >psr.sink_panel_replay_support if any
> > of the devices in branch is not supporting Panel Replay (mst).
> > 
> > v2:
> >   - commit message updated
> >   - Extra w/s removed
> > 
> > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> 
> Reviewed-by: Imre Deak <imre.deak@intel.com>

Thank you Imre for your review. I will take care of those leftovers you
pointed out. All patches in this set now pushed to drm-intel-next.

BR,

Jouni Högander
> 
> > ---
> >  .../drm/i915/display/intel_display_types.h    |  7 ++-
> >  drivers/gpu/drm/i915/display/intel_dp.c       |  3 +-
> >  drivers/gpu/drm/i915/display/intel_psr.c      | 44 +++++++++++----
> > ----
> >  3 files changed, 32 insertions(+), 22 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index b5641698db695..fb1c8b2d3979f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -572,6 +572,8 @@ struct intel_connector {
> >  			u8 dpcd[DP_PANEL_REPLAY_CAP_SIZE];
> >  #define
> > INTEL_PR_DPCD_INDEX(pr_dpcd_register)	((pr_dpcd_register) - DP_PANEL_REPLAY_CAP_SUPPORT)
> >  
> > +			bool support;
> > +			bool su_support;
> >  			enum intel_panel_replay_dsc_support
> > dsc_support;
> >  
> >  			u16 su_w_granularity;
> > @@ -581,6 +583,9 @@ struct intel_connector {
> >  		struct {
> >  			u8 dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
> >  
> > +			bool support;
> > +			bool su_support;
> > +
> >  			u16 su_w_granularity;
> >  			u16 su_y_granularity;
> >  		} psr_caps;
> > @@ -1731,7 +1736,6 @@ struct intel_psr {
> >  	bool active;
> >  	struct work_struct work;
> >  	unsigned int busy_frontbuffer_bits;
> > -	bool sink_psr2_support;
> >  	bool link_standby;
> >  	bool sel_update_enabled;
> >  	bool psr2_sel_fetch_enabled;
> > @@ -1747,7 +1751,6 @@ struct intel_psr {
> >  	u16 su_y_granularity;
> >  	bool source_panel_replay_support;
> >  	bool sink_panel_replay_support;
> > -	bool sink_panel_replay_su_support;
> >  	bool panel_replay_enabled;
> >  	u32 dc3co_exitline;
> >  	u32 dc3co_exit_delay;
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 8c5ddf0b09d25..4419954867455 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -6058,7 +6058,8 @@ intel_dp_detect(struct drm_connector
> > *_connector,
> >  		memset(connector->dp.panel_replay_caps.dpcd, 0,
> >  		       sizeof(connector-
> > >dp.panel_replay_caps.dpcd));
> >  		intel_dp->psr.sink_panel_replay_support = false;
> > -		intel_dp->psr.sink_panel_replay_su_support =
> > false;
> > +		connector->dp.panel_replay_caps.support = false;
> > +		connector->dp.panel_replay_caps.su_support =
> > false;
> >  		connector->dp.panel_replay_caps.dsc_support =
> >  			INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED;
> >  
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 1d3864405c850..c01e06f9cf643 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -634,11 +634,12 @@ static void _panel_replay_init_dpcd(struct
> > intel_dp *intel_dp, struct intel_conn
> >  		}
> >  	}
> >  
> > +	connector->dp.panel_replay_caps.support = true;
> >  	intel_dp->psr.sink_panel_replay_support = true;
> >  
> >  	if (connector-
> > >dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_
> > SUPPORT)] &
> >  	    DP_PANEL_REPLAY_SU_SUPPORT) {
> > -		intel_dp->psr.sink_panel_replay_su_support = true;
> > +		connector->dp.panel_replay_caps.su_support = true;
> >  
> >  		_panel_replay_compute_su_granularity(connector);
> >  	}
> > @@ -647,7 +648,7 @@ static void _panel_replay_init_dpcd(struct
> > intel_dp *intel_dp, struct intel_conn
> >  
> >  	drm_dbg_kms(display->drm,
> >  		    "Panel replay %sis supported by panel (in DSC
> > mode: %s)\n",
> > -		    intel_dp->psr.sink_panel_replay_su_support ?
> > +		    connector->dp.panel_replay_caps.su_support ?
> >  		    "selective_update " : "",
> >  		    panel_replay_dsc_support_str(connector-
> > >dp.panel_replay_caps.dsc_support));
> >  }
> > @@ -680,7 +681,9 @@ static void _psr_init_dpcd(struct intel_dp
> > *intel_dp, struct intel_connector *co
> >  		return;
> >  	}
> >  
> > +	connector->dp.psr_caps.support = true;
> >  	intel_dp->psr.sink_support = true;
> > +
> >  	intel_dp->psr.sink_sync_latency =
> >  		intel_dp_get_sink_sync_latency(intel_dp);
> >  
> > @@ -700,13 +703,13 @@ static void _psr_init_dpcd(struct intel_dp
> > *intel_dp, struct intel_connector *co
> >  		 * Y-coordinate requirement panels we would need
> > to enable
> >  		 * GTC first.
> >  		 */
> > -		intel_dp->psr.sink_psr2_support = y_req &&
> > +		connector->dp.psr_caps.su_support = y_req &&
> >  			intel_alpm_aux_wake_supported(intel_dp);
> >  		drm_dbg_kms(display->drm, "PSR2 %ssupported\n",
> > -			    intel_dp->psr.sink_psr2_support ? "" :
> > "not ");
> > +			    connector->dp.psr_caps.su_support ? ""
> > : "not ");
> >  	}
> >  
> > -	if (intel_dp->psr.sink_psr2_support)
> > +	if (connector->dp.psr_caps.su_support)
> >  		_psr_compute_su_granularity(intel_dp, connector);
> >  }
> >  
> > @@ -1514,14 +1517,16 @@ static bool alpm_config_valid(struct
> > intel_dp *intel_dp,
> >  }
> >  
> >  static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
> > -				    struct intel_crtc_state
> > *crtc_state)
> > +				    struct intel_crtc_state
> > *crtc_state,
> > +				    struct drm_connector_state
> > *conn_state)
> >  {
> >  	struct intel_display *display =
> > to_intel_display(intel_dp);
> > +	struct intel_connector *connector =
> > to_intel_connector(conn_state->connector);
> >  	int crtc_hdisplay = crtc_state-
> > >hw.adjusted_mode.crtc_hdisplay;
> >  	int crtc_vdisplay = crtc_state-
> > >hw.adjusted_mode.crtc_vdisplay;
> >  	int psr_max_h = 0, psr_max_v = 0, max_bpp = 0;
> >  
> > -	if (!intel_dp->psr.sink_psr2_support || display-
> > >params.enable_psr == 1)
> > +	if (!connector->dp.psr_caps.su_support || display-
> > >params.enable_psr == 1)
> >  		return false;
> >  
> >  	/* JSL and EHL only supports eDP 1.3 */
> > @@ -1634,7 +1639,8 @@ static bool
> > intel_sel_update_config_valid(struct intel_crtc_state *crtc_state,
> >  		goto unsupported;
> >  	}
> >  
> > -	if (!crtc_state->has_panel_replay &&
> > !intel_psr2_config_valid(intel_dp, crtc_state))
> > +	if (!crtc_state->has_panel_replay &&
> > !intel_psr2_config_valid(intel_dp, crtc_state,
> > +								  
> >     conn_state))
> >  		goto unsupported;
> >  
> >  	if (!_compute_psr2_sdp_prior_scanline_indication(intel_dp,
> > crtc_state)) {
> > @@ -1647,7 +1653,7 @@ static bool
> > intel_sel_update_config_valid(struct intel_crtc_state *crtc_state,
> >  		if (DISPLAY_VER(display) < 14)
> >  			goto unsupported;
> >  
> > -		if (!intel_dp->psr.sink_panel_replay_su_support)
> > +		if (!connector->dp.panel_replay_caps.su_support)
> >  			goto unsupported;
> >  
> >  		if (intel_dsc_enabled_on_link(crtc_state) &&
> > @@ -1736,6 +1742,9 @@ static bool
> > _panel_replay_compute_config(struct intel_crtc_state *crtc_state,
> >  	if (!CAN_PANEL_REPLAY(intel_dp))
> >  		return false;
> >  
> > +	if (!connector->dp.panel_replay_caps.support)
> > +		return false;
> > +
> >  	if (!panel_replay_global_enabled(intel_dp)) {
> >  		drm_dbg_kms(display->drm, "Panel Replay disabled
> > by flag\n");
> >  		return false;
> > @@ -4117,22 +4126,19 @@ psr_source_status(struct intel_dp
> > *intel_dp, struct seq_file *m)
> >  	seq_printf(m, "Source PSR/PanelReplay status: %s
> > [0x%08x]\n", status, val);
> >  }
> >  
> > -static void intel_psr_sink_capability(struct intel_dp *intel_dp,
> > -				      struct intel_connector
> > *connector,
> > +static void intel_psr_sink_capability(struct intel_connector
> > *connector,
> >  				      struct seq_file *m)
> >  {
> > -	struct intel_psr *psr = &intel_dp->psr;
> > -
> >  	seq_printf(m, "Sink support: PSR = %s",
> > -		   str_yes_no(psr->sink_support));
> > +		   str_yes_no(connector->dp.psr_caps.support));
> >  
> > -	if (psr->sink_support)
> > +	if (connector->dp.psr_caps.support)
> >  		seq_printf(m, " [0x%02x]", connector-
> > >dp.psr_caps.dpcd[0]);
> >  	if (connector->dp.psr_caps.dpcd[0] ==
> > DP_PSR2_WITH_Y_COORD_ET_SUPPORTED)
> >  		seq_printf(m, " (Early Transport)");
> > -	seq_printf(m, ", Panel Replay = %s", str_yes_no(psr-
> > >sink_panel_replay_support));
> > +	seq_printf(m, ", Panel Replay = %s", str_yes_no(connector-
> > >dp.panel_replay_caps.support));
> >  	seq_printf(m, ", Panel Replay Selective Update = %s",
> > -		   str_yes_no(psr->sink_panel_replay_su_support));
> > +		   str_yes_no(connector-
> > >dp.panel_replay_caps.su_support));
> >  	seq_printf(m, ", Panel Replay DSC support = %s",
> >  		   panel_replay_dsc_support_str(connector-
> > >dp.panel_replay_caps.dsc_support));
> >  	if (connector-
> > >dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_
> > SUPPORT)] &
> > @@ -4183,9 +4189,9 @@ static int intel_psr_status(struct seq_file
> > *m, struct intel_dp *intel_dp,
> >  	bool enabled;
> >  	u32 val, psr2_ctl;
> >  
> > -	intel_psr_sink_capability(intel_dp, connector, m);
> > +	intel_psr_sink_capability(connector, m);
> >  
> > -	if (!(psr->sink_support || psr-
> > >sink_panel_replay_support))
> > +	if (!(connector->dp.psr_caps.support || connector-
> > >dp.panel_replay_caps.support))
> >  		return 0;
> >  
> >  	wakeref = intel_display_rpm_get(display);
> > -- 
> > 2.43.0
> > 

[PATCH v2 8/8] drm/i915/psr: Move sink_sync_latency to intel_connector

[Jouni Högander]

As everything else related to PSR and Panel Replay capabilities are moved
into intel_connector move sink_sync_latency as well.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_types.h | 3 ++-
 drivers/gpu/drm/i915/display/intel_psr.c           | 8 ++++----
 2 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index fb1c8b2d3979f..90821019eaa13 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -588,6 +588,8 @@ struct intel_connector {
 
 			u16 su_w_granularity;
 			u16 su_y_granularity;
+
+			u8 sync_latency;
 		} psr_caps;
 	} dp;
 
@@ -1742,7 +1744,6 @@ struct intel_psr {
 	bool psr2_sel_fetch_cff_enabled;
 	bool su_region_et_enabled;
 	bool req_psr2_sdp_prior_scanline;
-	u8 sink_sync_latency;
 	ktime_t last_entry_attempt;
 	ktime_t last_exit;
 	bool sink_not_reliable;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index c01e06f9cf643..b2dd4317c675f 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -684,8 +684,7 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *co
 	connector->dp.psr_caps.support = true;
 	intel_dp->psr.sink_support = true;
 
-	intel_dp->psr.sink_sync_latency =
-		intel_dp_get_sink_sync_latency(intel_dp);
+	connector->dp.psr_caps.sync_latency = intel_dp_get_sink_sync_latency(intel_dp);
 
 	if (DISPLAY_VER(display) >= 9 &&
 	    connector->dp.psr_caps.dpcd[0] >= DP_PSR2_WITH_Y_COORD_IS_SUPPORTED) {
@@ -910,7 +909,7 @@ static u8 psr_compute_idle_frames(struct intel_dp *intel_dp)
 	 * off-by-one issue that HW has in some cases.
 	 */
 	idle_frames = max(6, connector->panel.vbt.psr.idle_frames);
-	idle_frames = max(idle_frames, intel_dp->psr.sink_sync_latency + 1);
+	idle_frames = max(idle_frames, connector->dp.psr_caps.sync_latency + 1);
 
 	if (drm_WARN_ON(display->drm, idle_frames > 0xf))
 		idle_frames = 0xf;
@@ -1005,10 +1004,11 @@ static int psr2_block_count(struct intel_dp *intel_dp)
 
 static u8 frames_before_su_entry(struct intel_dp *intel_dp)
 {
+	struct intel_connector *connector = intel_dp->attached_connector;
 	u8 frames_before_su_entry;
 
 	frames_before_su_entry = max_t(u8,
-				       intel_dp->psr.sink_sync_latency + 1,
+				       connector->dp.psr_caps.sync_latency + 1,
 				       2);
 
 	/* Entry setup frames must be at least 1 less than frames before SU entry */
-- 
2.43.0

✗ CI.checkpatch: warning for Move PSR/Panel Replay sink data into intel_connector (rev2)

[Patchwork]

== Series Details ==

Series: Move PSR/Panel Replay sink data into intel_connector (rev2)
URL   : https://patchwork.freedesktop.org/series/157898/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
2de9a3901bc28757c7906b454717b64e2a214021
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit edef0904dbf249b06e50c6bbb7d7c7516a4c395e
Author: Jouni Högander <jouni.hogander@intel.com>
Date:   Wed Dec 3 12:31:34 2025 +0200

    drm/i915/psr: Move sink_sync_latency to intel_connector
    
    As everything else related to PSR and Panel Replay capabilities are moved
    into intel_connector move sink_sync_latency as well.
    
    Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
    Reviewed-by: Imre Deak <imre.deak@intel.com>
+ /mt/dim checkpatch 6bb7557236825dae297c2399e24e40b4d9cd1a88 drm-intel
a012ca4a7354 drm/i915/psr: Add panel granularity information into intel_connector
08a63b7832dc drm/i915/psr: Use SU granularity information available in intel_connector
-:178: WARNING:LONG_LINE: line length of 117 exceeds 100 columns
#178: FILE: drivers/gpu/drm/i915/display/intel_psr.c:596:
+	w = le16_to_cpu(*(__le16 *)&intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_X_GRANULARITY)]) ? : 4;

total: 0 errors, 1 warnings, 0 checks, 282 lines checked
9818ec8908e7 drm/i915/psr: Compute Panel Replay/Adaptive Sync coexistence behavior
-:94: WARNING:LONG_LINE: line length of 114 exceeds 100 columns
#94: FILE: drivers/gpu/drm/i915/display/intel_psr.c:1754:
+	crtc_state->link_off_after_as_sdp_when_pr_active = compute_link_off_after_as_sdp_when_pr_active(intel_dp);

total: 0 errors, 1 warnings, 0 checks, 69 lines checked
5d3f5f406c65 drm/i915/psr: Move pr_dpcd and psr_dpcd to intel_connector
-:77: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#77: FILE: drivers/gpu/drm/i915/display/intel_psr.c:547:
+	val = connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)];

-:93: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#93: FILE: drivers/gpu/drm/i915/display/intel_psr.c:584:
+	if (!(connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &

-:103: WARNING:LONG_LINE: line length of 136 exceeds 100 columns
#103: FILE: drivers/gpu/drm/i915/display/intel_psr.c:595:
+	w = le16_to_cpu(*(__le16 *)&connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_X_GRANULARITY)]) ? : 4;

-:104: WARNING:LONG_LINE: line length of 111 exceeds 100 columns
#104: FILE: drivers/gpu/drm/i915/display/intel_psr.c:596:
+	y = connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_Y_GRANULARITY)] ? : 1;

-:119: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#119: FILE: drivers/gpu/drm/i915/display/intel_psr.c:618:
+	if (!(connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &

-:128: WARNING:LONG_LINE: line length of 110 exceeds 100 columns
#128: FILE: drivers/gpu/drm/i915/display/intel_psr.c:629:
+		if (!(connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &

-:198: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#198: FILE: drivers/gpu/drm/i915/display/intel_psr.c:767:
+		connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &

-:233: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#233: FILE: drivers/gpu/drm/i915/display/intel_psr.c:1675:
+								       crtc_state->has_panel_replay);

-:264: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#264: FILE: drivers/gpu/drm/i915/display/intel_psr.c:1717:
+	return (connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &

-:272: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#272: FILE: drivers/gpu/drm/i915/display/intel_psr.c:1723:
+	return !(connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &

-:282: WARNING:LONG_LINE: line length of 115 exceeds 100 columns
#282: FILE: drivers/gpu/drm/i915/display/intel_psr.c:1758:
+	crtc_state->link_off_after_as_sdp_when_pr_active = compute_link_off_after_as_sdp_when_pr_active(connector);

-:283: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#283: FILE: drivers/gpu/drm/i915/display/intel_psr.c:1759:
+	crtc_state->disable_as_sdp_when_pr_active = compute_disable_as_sdp_when_pr_active(connector);

total: 0 errors, 12 warnings, 0 checks, 304 lines checked
1a2cb6b9aaa0 drm/i915/psr: Clear pr_dpcd as well on disconnect
ec694fccde2b drm/i915/psr: Move Panel Replay DSC sink support data to intel_connector
c335b421bbc5 drm/i915/psr: Move sink PSR and Panel Replay booleans to intel_connector
edef0904dbf2 drm/i915/psr: Move sink_sync_latency to intel_connector

✓ CI.KUnit: success for Move PSR/Panel Replay sink data into intel_connector (rev2)

[Patchwork]

== Series Details ==

Series: Move PSR/Panel Replay sink data into intel_connector (rev2)
URL   : https://patchwork.freedesktop.org/series/157898/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[10:38:20] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[10:38:24] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[10:38:55] Starting KUnit Kernel (1/1)...
[10:38:55] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[10:38:55] ================== guc_buf (11 subtests) ===================
[10:38:55] [PASSED] test_smallest
[10:38:55] [PASSED] test_largest
[10:38:55] [PASSED] test_granular
[10:38:55] [PASSED] test_unique
[10:38:55] [PASSED] test_overlap
[10:38:55] [PASSED] test_reusable
[10:38:55] [PASSED] test_too_big
[10:38:55] [PASSED] test_flush
[10:38:55] [PASSED] test_lookup
[10:38:55] [PASSED] test_data
[10:38:55] [PASSED] test_class
[10:38:55] ===================== [PASSED] guc_buf =====================
[10:38:55] =================== guc_dbm (7 subtests) ===================
[10:38:55] [PASSED] test_empty
[10:38:55] [PASSED] test_default
[10:38:55] ======================== test_size  ========================
[10:38:55] [PASSED] 4
[10:38:55] [PASSED] 8
[10:38:55] [PASSED] 32
[10:38:55] [PASSED] 256
[10:38:55] ==================== [PASSED] test_size ====================
[10:38:55] ======================= test_reuse  ========================
[10:38:55] [PASSED] 4
[10:38:55] [PASSED] 8
[10:38:55] [PASSED] 32
[10:38:55] [PASSED] 256
[10:38:55] =================== [PASSED] test_reuse ====================
[10:38:55] =================== test_range_overlap  ====================
[10:38:55] [PASSED] 4
[10:38:55] [PASSED] 8
[10:38:55] [PASSED] 32
[10:38:55] [PASSED] 256
[10:38:55] =============== [PASSED] test_range_overlap ================
[10:38:55] =================== test_range_compact  ====================
[10:38:55] [PASSED] 4
[10:38:55] [PASSED] 8
[10:38:55] [PASSED] 32
[10:38:55] [PASSED] 256
[10:38:55] =============== [PASSED] test_range_compact ================
[10:38:55] ==================== test_range_spare  =====================
[10:38:55] [PASSED] 4
[10:38:55] [PASSED] 8
[10:38:55] [PASSED] 32
[10:38:55] [PASSED] 256
[10:38:55] ================ [PASSED] test_range_spare =================
[10:38:55] ===================== [PASSED] guc_dbm =====================
[10:38:55] =================== guc_idm (6 subtests) ===================
[10:38:55] [PASSED] bad_init
[10:38:55] [PASSED] no_init
[10:38:55] [PASSED] init_fini
[10:38:55] [PASSED] check_used
[10:38:55] [PASSED] check_quota
[10:38:55] [PASSED] check_all
[10:38:55] ===================== [PASSED] guc_idm =====================
[10:38:55] ================== no_relay (3 subtests) ===================
[10:38:55] [PASSED] xe_drops_guc2pf_if_not_ready
[10:38:55] [PASSED] xe_drops_guc2vf_if_not_ready
[10:38:55] [PASSED] xe_rejects_send_if_not_ready
[10:38:55] ==================== [PASSED] no_relay =====================
[10:38:55] ================== pf_relay (14 subtests) ==================
[10:38:55] [PASSED] pf_rejects_guc2pf_too_short
[10:38:55] [PASSED] pf_rejects_guc2pf_too_long
[10:38:55] [PASSED] pf_rejects_guc2pf_no_payload
[10:38:55] [PASSED] pf_fails_no_payload
[10:38:55] [PASSED] pf_fails_bad_origin
[10:38:55] [PASSED] pf_fails_bad_type
[10:38:55] [PASSED] pf_txn_reports_error
[10:38:55] [PASSED] pf_txn_sends_pf2guc
[10:38:55] [PASSED] pf_sends_pf2guc
[10:38:55] [SKIPPED] pf_loopback_nop
[10:38:55] [SKIPPED] pf_loopback_echo
[10:38:55] [SKIPPED] pf_loopback_fail
[10:38:55] [SKIPPED] pf_loopback_busy
[10:38:55] [SKIPPED] pf_loopback_retry
[10:38:55] ==================== [PASSED] pf_relay =====================
[10:38:55] ================== vf_relay (3 subtests) ===================
[10:38:55] [PASSED] vf_rejects_guc2vf_too_short
[10:38:55] [PASSED] vf_rejects_guc2vf_too_long
[10:38:55] [PASSED] vf_rejects_guc2vf_no_payload
[10:38:55] ==================== [PASSED] vf_relay =====================
[10:38:55] ================ pf_gt_config (6 subtests) =================
[10:38:55] [PASSED] fair_contexts_1vf
[10:38:55] [PASSED] fair_doorbells_1vf
[10:38:55] [PASSED] fair_ggtt_1vf
[10:38:55] ====================== fair_contexts  ======================
[10:38:55] [PASSED] 1 VF
[10:38:55] [PASSED] 2 VFs
[10:38:55] [PASSED] 3 VFs
[10:38:55] [PASSED] 4 VFs
[10:38:55] [PASSED] 5 VFs
[10:38:55] [PASSED] 6 VFs
[10:38:55] [PASSED] 7 VFs
[10:38:55] [PASSED] 8 VFs
[10:38:55] [PASSED] 9 VFs
[10:38:55] [PASSED] 10 VFs
[10:38:55] [PASSED] 11 VFs
[10:38:55] [PASSED] 12 VFs
[10:38:55] [PASSED] 13 VFs
[10:38:55] [PASSED] 14 VFs
[10:38:55] [PASSED] 15 VFs
[10:38:55] [PASSED] 16 VFs
[10:38:55] [PASSED] 17 VFs
[10:38:55] [PASSED] 18 VFs
[10:38:55] [PASSED] 19 VFs
[10:38:55] [PASSED] 20 VFs
[10:38:55] [PASSED] 21 VFs
[10:38:55] [PASSED] 22 VFs
[10:38:55] [PASSED] 23 VFs
[10:38:55] [PASSED] 24 VFs
[10:38:55] [PASSED] 25 VFs
[10:38:55] [PASSED] 26 VFs
[10:38:55] [PASSED] 27 VFs
[10:38:55] [PASSED] 28 VFs
[10:38:55] [PASSED] 29 VFs
[10:38:55] [PASSED] 30 VFs
[10:38:55] [PASSED] 31 VFs
[10:38:55] [PASSED] 32 VFs
[10:38:55] [PASSED] 33 VFs
[10:38:55] [PASSED] 34 VFs
[10:38:55] [PASSED] 35 VFs
[10:38:55] [PASSED] 36 VFs
[10:38:55] [PASSED] 37 VFs
[10:38:55] [PASSED] 38 VFs
[10:38:55] [PASSED] 39 VFs
[10:38:55] [PASSED] 40 VFs
[10:38:55] [PASSED] 41 VFs
[10:38:55] [PASSED] 42 VFs
[10:38:55] [PASSED] 43 VFs
[10:38:55] [PASSED] 44 VFs
[10:38:55] [PASSED] 45 VFs
[10:38:55] [PASSED] 46 VFs
[10:38:55] [PASSED] 47 VFs
[10:38:55] [PASSED] 48 VFs
[10:38:55] [PASSED] 49 VFs
[10:38:55] [PASSED] 50 VFs
[10:38:55] [PASSED] 51 VFs
[10:38:55] [PASSED] 52 VFs
[10:38:55] [PASSED] 53 VFs
[10:38:55] [PASSED] 54 VFs
[10:38:55] [PASSED] 55 VFs
[10:38:55] [PASSED] 56 VFs
[10:38:55] [PASSED] 57 VFs
[10:38:55] [PASSED] 58 VFs
[10:38:55] [PASSED] 59 VFs
[10:38:55] [PASSED] 60 VFs
[10:38:55] [PASSED] 61 VFs
[10:38:55] [PASSED] 62 VFs
[10:38:55] [PASSED] 63 VFs
[10:38:55] ================== [PASSED] fair_contexts ==================
[10:38:55] ===================== fair_doorbells  ======================
[10:38:55] [PASSED] 1 VF
[10:38:55] [PASSED] 2 VFs
[10:38:55] [PASSED] 3 VFs
[10:38:55] [PASSED] 4 VFs
[10:38:55] [PASSED] 5 VFs
[10:38:55] [PASSED] 6 VFs
[10:38:55] [PASSED] 7 VFs
[10:38:55] [PASSED] 8 VFs
[10:38:55] [PASSED] 9 VFs
[10:38:55] [PASSED] 10 VFs
[10:38:55] [PASSED] 11 VFs
[10:38:55] [PASSED] 12 VFs
[10:38:55] [PASSED] 13 VFs
[10:38:55] [PASSED] 14 VFs
[10:38:55] [PASSED] 15 VFs
[10:38:55] [PASSED] 16 VFs
[10:38:55] [PASSED] 17 VFs
[10:38:55] [PASSED] 18 VFs
[10:38:55] [PASSED] 19 VFs
[10:38:55] [PASSED] 20 VFs
[10:38:55] [PASSED] 21 VFs
[10:38:55] [PASSED] 22 VFs
[10:38:55] [PASSED] 23 VFs
[10:38:55] [PASSED] 24 VFs
[10:38:55] [PASSED] 25 VFs
[10:38:55] [PASSED] 26 VFs
[10:38:55] [PASSED] 27 VFs
[10:38:55] [PASSED] 28 VFs
[10:38:55] [PASSED] 29 VFs
[10:38:55] [PASSED] 30 VFs
[10:38:55] [PASSED] 31 VFs
[10:38:55] [PASSED] 32 VFs
[10:38:55] [PASSED] 33 VFs
[10:38:55] [PASSED] 34 VFs
[10:38:55] [PASSED] 35 VFs
[10:38:55] [PASSED] 36 VFs
[10:38:55] [PASSED] 37 VFs
[10:38:55] [PASSED] 38 VFs
[10:38:55] [PASSED] 39 VFs
[10:38:55] [PASSED] 40 VFs
[10:38:55] [PASSED] 41 VFs
[10:38:55] [PASSED] 42 VFs
[10:38:55] [PASSED] 43 VFs
[10:38:55] [PASSED] 44 VFs
[10:38:55] [PASSED] 45 VFs
[10:38:55] [PASSED] 46 VFs
[10:38:55] [PASSED] 47 VFs
[10:38:55] [PASSED] 48 VFs
[10:38:55] [PASSED] 49 VFs
[10:38:55] [PASSED] 50 VFs
[10:38:55] [PASSED] 51 VFs
[10:38:55] [PASSED] 52 VFs
[10:38:55] [PASSED] 53 VFs
[10:38:55] [PASSED] 54 VFs
[10:38:55] [PASSED] 55 VFs
[10:38:55] [PASSED] 56 VFs
[10:38:55] [PASSED] 57 VFs
[10:38:55] [PASSED] 58 VFs
[10:38:55] [PASSED] 59 VFs
[10:38:55] [PASSED] 60 VFs
[10:38:55] [PASSED] 61 VFs
[10:38:55] [PASSED] 62 VFs
[10:38:55] [PASSED] 63 VFs
[10:38:55] ================= [PASSED] fair_doorbells ==================
[10:38:55] ======================== fair_ggtt  ========================
[10:38:55] [PASSED] 1 VF
[10:38:55] [PASSED] 2 VFs
[10:38:55] [PASSED] 3 VFs
[10:38:55] [PASSED] 4 VFs
[10:38:55] [PASSED] 5 VFs
[10:38:55] [PASSED] 6 VFs
[10:38:55] [PASSED] 7 VFs
[10:38:55] [PASSED] 8 VFs
[10:38:55] [PASSED] 9 VFs
[10:38:55] [PASSED] 10 VFs
[10:38:55] [PASSED] 11 VFs
[10:38:55] [PASSED] 12 VFs
[10:38:55] [PASSED] 13 VFs
[10:38:55] [PASSED] 14 VFs
[10:38:55] [PASSED] 15 VFs
[10:38:55] [PASSED] 16 VFs
[10:38:55] [PASSED] 17 VFs
[10:38:55] [PASSED] 18 VFs
[10:38:55] [PASSED] 19 VFs
[10:38:55] [PASSED] 20 VFs
[10:38:55] [PASSED] 21 VFs
[10:38:55] [PASSED] 22 VFs
[10:38:55] [PASSED] 23 VFs
[10:38:55] [PASSED] 24 VFs
[10:38:55] [PASSED] 25 VFs
[10:38:55] [PASSED] 26 VFs
[10:38:55] [PASSED] 27 VFs
[10:38:55] [PASSED] 28 VFs
[10:38:55] [PASSED] 29 VFs
[10:38:55] [PASSED] 30 VFs
[10:38:55] [PASSED] 31 VFs
[10:38:55] [PASSED] 32 VFs
[10:38:55] [PASSED] 33 VFs
[10:38:55] [PASSED] 34 VFs
[10:38:55] [PASSED] 35 VFs
[10:38:55] [PASSED] 36 VFs
[10:38:55] [PASSED] 37 VFs
[10:38:55] [PASSED] 38 VFs
[10:38:55] [PASSED] 39 VFs
[10:38:55] [PASSED] 40 VFs
[10:38:55] [PASSED] 41 VFs
[10:38:55] [PASSED] 42 VFs
[10:38:55] [PASSED] 43 VFs
[10:38:55] [PASSED] 44 VFs
[10:38:55] [PASSED] 45 VFs
[10:38:55] [PASSED] 46 VFs
[10:38:55] [PASSED] 47 VFs
[10:38:55] [PASSED] 48 VFs
[10:38:55] [PASSED] 49 VFs
[10:38:55] [PASSED] 50 VFs
[10:38:55] [PASSED] 51 VFs
[10:38:55] [PASSED] 52 VFs
[10:38:55] [PASSED] 53 VFs
[10:38:55] [PASSED] 54 VFs
[10:38:55] [PASSED] 55 VFs
[10:38:55] [PASSED] 56 VFs
[10:38:55] [PASSED] 57 VFs
[10:38:55] [PASSED] 58 VFs
[10:38:55] [PASSED] 59 VFs
[10:38:55] [PASSED] 60 VFs
[10:38:55] [PASSED] 61 VFs
[10:38:55] [PASSED] 62 VFs
[10:38:55] [PASSED] 63 VFs
[10:38:55] ==================== [PASSED] fair_ggtt ====================
[10:38:55] ================== [PASSED] pf_gt_config ===================
[10:38:55] ===================== lmtt (1 subtest) =====================
[10:38:55] ======================== test_ops  =========================
[10:38:55] [PASSED] 2-level
[10:38:55] [PASSED] multi-level
[10:38:55] ==================== [PASSED] test_ops =====================
[10:38:55] ====================== [PASSED] lmtt =======================
[10:38:55] ================= pf_service (11 subtests) =================
[10:38:55] [PASSED] pf_negotiate_any
[10:38:55] [PASSED] pf_negotiate_base_match
[10:38:55] [PASSED] pf_negotiate_base_newer
[10:38:55] [PASSED] pf_negotiate_base_next
[10:38:55] [SKIPPED] pf_negotiate_base_older
[10:38:55] [PASSED] pf_negotiate_base_prev
[10:38:55] [PASSED] pf_negotiate_latest_match
[10:38:55] [PASSED] pf_negotiate_latest_newer
[10:38:55] [PASSED] pf_negotiate_latest_next
[10:38:55] [SKIPPED] pf_negotiate_latest_older
[10:38:55] [SKIPPED] pf_negotiate_latest_prev
[10:38:55] =================== [PASSED] pf_service ====================
[10:38:55] ================= xe_guc_g2g (2 subtests) ==================
[10:38:55] ============== xe_live_guc_g2g_kunit_default  ==============
[10:38:55] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[10:38:55] ============== xe_live_guc_g2g_kunit_allmem  ===============
[10:38:55] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[10:38:55] =================== [SKIPPED] xe_guc_g2g ===================
[10:38:55] =================== xe_mocs (2 subtests) ===================
[10:38:55] ================ xe_live_mocs_kernel_kunit  ================
[10:38:55] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[10:38:55] ================ xe_live_mocs_reset_kunit  =================
[10:38:55] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[10:38:55] ==================== [SKIPPED] xe_mocs =====================
[10:38:55] ================= xe_migrate (2 subtests) ==================
[10:38:55] ================= xe_migrate_sanity_kunit  =================
[10:38:55] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[10:38:55] ================== xe_validate_ccs_kunit  ==================
[10:38:55] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[10:38:55] =================== [SKIPPED] xe_migrate ===================
[10:38:55] ================== xe_dma_buf (1 subtest) ==================
[10:38:55] ==================== xe_dma_buf_kunit  =====================
[10:38:55] ================ [SKIPPED] xe_dma_buf_kunit ================
[10:38:55] =================== [SKIPPED] xe_dma_buf ===================
[10:38:55] ================= xe_bo_shrink (1 subtest) =================
[10:38:55] =================== xe_bo_shrink_kunit  ====================
[10:38:55] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[10:38:55] ================== [SKIPPED] xe_bo_shrink ==================
[10:38:55] ==================== xe_bo (2 subtests) ====================
[10:38:55] ================== xe_ccs_migrate_kunit  ===================
[10:38:55] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[10:38:55] ==================== xe_bo_evict_kunit  ====================
[10:38:55] =============== [SKIPPED] xe_bo_evict_kunit ================
[10:38:55] ===================== [SKIPPED] xe_bo ======================
[10:38:55] ==================== args (11 subtests) ====================
[10:38:55] [PASSED] count_args_test
[10:38:55] [PASSED] call_args_example
[10:38:55] [PASSED] call_args_test
[10:38:55] [PASSED] drop_first_arg_example
[10:38:55] [PASSED] drop_first_arg_test
[10:38:55] [PASSED] first_arg_example
[10:38:55] [PASSED] first_arg_test
[10:38:55] [PASSED] last_arg_example
[10:38:55] [PASSED] last_arg_test
[10:38:55] [PASSED] pick_arg_example
[10:38:55] [PASSED] sep_comma_example
[10:38:55] ====================== [PASSED] args =======================
[10:38:55] =================== xe_pci (3 subtests) ====================
[10:38:55] ==================== check_graphics_ip  ====================
[10:38:55] [PASSED] 12.00 Xe_LP
[10:38:55] [PASSED] 12.10 Xe_LP+
[10:38:55] [PASSED] 12.55 Xe_HPG
[10:38:55] [PASSED] 12.60 Xe_HPC
[10:38:55] [PASSED] 12.70 Xe_LPG
[10:38:55] [PASSED] 12.71 Xe_LPG
[10:38:55] [PASSED] 12.74 Xe_LPG+
[10:38:55] [PASSED] 20.01 Xe2_HPG
[10:38:55] [PASSED] 20.02 Xe2_HPG
[10:38:55] [PASSED] 20.04 Xe2_LPG
[10:38:55] [PASSED] 30.00 Xe3_LPG
[10:38:55] [PASSED] 30.01 Xe3_LPG
[10:38:55] [PASSED] 30.03 Xe3_LPG
[10:38:55] [PASSED] 30.04 Xe3_LPG
[10:38:55] [PASSED] 30.05 Xe3_LPG
[10:38:55] [PASSED] 35.11 Xe3p_XPC
[10:38:55] ================ [PASSED] check_graphics_ip ================
[10:38:55] ===================== check_media_ip  ======================
[10:38:55] [PASSED] 12.00 Xe_M
[10:38:55] [PASSED] 12.55 Xe_HPM
[10:38:55] [PASSED] 13.00 Xe_LPM+
[10:38:55] [PASSED] 13.01 Xe2_HPM
[10:38:55] [PASSED] 20.00 Xe2_LPM
[10:38:55] [PASSED] 30.00 Xe3_LPM
[10:38:55] [PASSED] 30.02 Xe3_LPM
[10:38:55] [PASSED] 35.00 Xe3p_LPM
[10:38:55] [PASSED] 35.03 Xe3p_HPM
[10:38:55] ================= [PASSED] check_media_ip ==================
[10:38:55] =================== check_platform_desc  ===================
[10:38:55] [PASSED] 0x9A60 (TIGERLAKE)
[10:38:55] [PASSED] 0x9A68 (TIGERLAKE)
[10:38:55] [PASSED] 0x9A70 (TIGERLAKE)
[10:38:55] [PASSED] 0x9A40 (TIGERLAKE)
[10:38:55] [PASSED] 0x9A49 (TIGERLAKE)
[10:38:55] [PASSED] 0x9A59 (TIGERLAKE)
[10:38:55] [PASSED] 0x9A78 (TIGERLAKE)
[10:38:55] [PASSED] 0x9AC0 (TIGERLAKE)
[10:38:55] [PASSED] 0x9AC9 (TIGERLAKE)
[10:38:55] [PASSED] 0x9AD9 (TIGERLAKE)
[10:38:55] [PASSED] 0x9AF8 (TIGERLAKE)
[10:38:55] [PASSED] 0x4C80 (ROCKETLAKE)
[10:38:55] [PASSED] 0x4C8A (ROCKETLAKE)
[10:38:55] [PASSED] 0x4C8B (ROCKETLAKE)
[10:38:55] [PASSED] 0x4C8C (ROCKETLAKE)
[10:38:55] [PASSED] 0x4C90 (ROCKETLAKE)
[10:38:55] [PASSED] 0x4C9A (ROCKETLAKE)
[10:38:55] [PASSED] 0x4680 (ALDERLAKE_S)
[10:38:55] [PASSED] 0x4682 (ALDERLAKE_S)
[10:38:55] [PASSED] 0x4688 (ALDERLAKE_S)
[10:38:55] [PASSED] 0x468A (ALDERLAKE_S)
[10:38:55] [PASSED] 0x468B (ALDERLAKE_S)
[10:38:55] [PASSED] 0x4690 (ALDERLAKE_S)
[10:38:55] [PASSED] 0x4692 (ALDERLAKE_S)
[10:38:55] [PASSED] 0x4693 (ALDERLAKE_S)
[10:38:55] [PASSED] 0x46A0 (ALDERLAKE_P)
[10:38:55] [PASSED] 0x46A1 (ALDERLAKE_P)
[10:38:55] [PASSED] 0x46A2 (ALDERLAKE_P)
[10:38:55] [PASSED] 0x46A3 (ALDERLAKE_P)
[10:38:55] [PASSED] 0x46A6 (ALDERLAKE_P)
[10:38:55] [PASSED] 0x46A8 (ALDERLAKE_P)
[10:38:55] [PASSED] 0x46AA (ALDERLAKE_P)
[10:38:55] [PASSED] 0x462A (ALDERLAKE_P)
[10:38:55] [PASSED] 0x4626 (ALDERLAKE_P)
[10:38:55] [PASSED] 0x4628 (ALDERLAKE_P)
[10:38:55] [PASSED] 0x46B0 (ALDERLAKE_P)
stty: 'standard input': Inappropriate ioctl for device
[10:38:55] [PASSED] 0x46B1 (ALDERLAKE_P)
[10:38:55] [PASSED] 0x46B2 (ALDERLAKE_P)
[10:38:55] [PASSED] 0x46B3 (ALDERLAKE_P)
[10:38:55] [PASSED] 0x46C0 (ALDERLAKE_P)
[10:38:55] [PASSED] 0x46C1 (ALDERLAKE_P)
[10:38:55] [PASSED] 0x46C2 (ALDERLAKE_P)
[10:38:55] [PASSED] 0x46C3 (ALDERLAKE_P)
[10:38:55] [PASSED] 0x46D0 (ALDERLAKE_N)
[10:38:55] [PASSED] 0x46D1 (ALDERLAKE_N)
[10:38:55] [PASSED] 0x46D2 (ALDERLAKE_N)
[10:38:55] [PASSED] 0x46D3 (ALDERLAKE_N)
[10:38:55] [PASSED] 0x46D4 (ALDERLAKE_N)
[10:38:55] [PASSED] 0xA721 (ALDERLAKE_P)
[10:38:55] [PASSED] 0xA7A1 (ALDERLAKE_P)
[10:38:55] [PASSED] 0xA7A9 (ALDERLAKE_P)
[10:38:55] [PASSED] 0xA7AC (ALDERLAKE_P)
[10:38:55] [PASSED] 0xA7AD (ALDERLAKE_P)
[10:38:55] [PASSED] 0xA720 (ALDERLAKE_P)
[10:38:55] [PASSED] 0xA7A0 (ALDERLAKE_P)
[10:38:55] [PASSED] 0xA7A8 (ALDERLAKE_P)
[10:38:55] [PASSED] 0xA7AA (ALDERLAKE_P)
[10:38:55] [PASSED] 0xA7AB (ALDERLAKE_P)
[10:38:55] [PASSED] 0xA780 (ALDERLAKE_S)
[10:38:55] [PASSED] 0xA781 (ALDERLAKE_S)
[10:38:55] [PASSED] 0xA782 (ALDERLAKE_S)
[10:38:55] [PASSED] 0xA783 (ALDERLAKE_S)
[10:38:55] [PASSED] 0xA788 (ALDERLAKE_S)
[10:38:55] [PASSED] 0xA789 (ALDERLAKE_S)
[10:38:55] [PASSED] 0xA78A (ALDERLAKE_S)
[10:38:55] [PASSED] 0xA78B (ALDERLAKE_S)
[10:38:55] [PASSED] 0x4905 (DG1)
[10:38:55] [PASSED] 0x4906 (DG1)
[10:38:55] [PASSED] 0x4907 (DG1)
[10:38:55] [PASSED] 0x4908 (DG1)
[10:38:55] [PASSED] 0x4909 (DG1)
[10:38:55] [PASSED] 0x56C0 (DG2)
[10:38:55] [PASSED] 0x56C2 (DG2)
[10:38:55] [PASSED] 0x56C1 (DG2)
[10:38:55] [PASSED] 0x7D51 (METEORLAKE)
[10:38:55] [PASSED] 0x7DD1 (METEORLAKE)
[10:38:55] [PASSED] 0x7D41 (METEORLAKE)
[10:38:55] [PASSED] 0x7D67 (METEORLAKE)
[10:38:55] [PASSED] 0xB640 (METEORLAKE)
[10:38:55] [PASSED] 0x56A0 (DG2)
[10:38:55] [PASSED] 0x56A1 (DG2)
[10:38:55] [PASSED] 0x56A2 (DG2)
[10:38:55] [PASSED] 0x56BE (DG2)
[10:38:55] [PASSED] 0x56BF (DG2)
[10:38:55] [PASSED] 0x5690 (DG2)
[10:38:55] [PASSED] 0x5691 (DG2)
[10:38:55] [PASSED] 0x5692 (DG2)
[10:38:55] [PASSED] 0x56A5 (DG2)
[10:38:55] [PASSED] 0x56A6 (DG2)
[10:38:55] [PASSED] 0x56B0 (DG2)
[10:38:55] [PASSED] 0x56B1 (DG2)
[10:38:55] [PASSED] 0x56BA (DG2)
[10:38:55] [PASSED] 0x56BB (DG2)
[10:38:55] [PASSED] 0x56BC (DG2)
[10:38:55] [PASSED] 0x56BD (DG2)
[10:38:55] [PASSED] 0x5693 (DG2)
[10:38:55] [PASSED] 0x5694 (DG2)
[10:38:55] [PASSED] 0x5695 (DG2)
[10:38:55] [PASSED] 0x56A3 (DG2)
[10:38:55] [PASSED] 0x56A4 (DG2)
[10:38:55] [PASSED] 0x56B2 (DG2)
[10:38:55] [PASSED] 0x56B3 (DG2)
[10:38:55] [PASSED] 0x5696 (DG2)
[10:38:55] [PASSED] 0x5697 (DG2)
[10:38:55] [PASSED] 0xB69 (PVC)
[10:38:55] [PASSED] 0xB6E (PVC)
[10:38:55] [PASSED] 0xBD4 (PVC)
[10:38:55] [PASSED] 0xBD5 (PVC)
[10:38:55] [PASSED] 0xBD6 (PVC)
[10:38:55] [PASSED] 0xBD7 (PVC)
[10:38:55] [PASSED] 0xBD8 (PVC)
[10:38:55] [PASSED] 0xBD9 (PVC)
[10:38:55] [PASSED] 0xBDA (PVC)
[10:38:55] [PASSED] 0xBDB (PVC)
[10:38:55] [PASSED] 0xBE0 (PVC)
[10:38:55] [PASSED] 0xBE1 (PVC)
[10:38:55] [PASSED] 0xBE5 (PVC)
[10:38:55] [PASSED] 0x7D40 (METEORLAKE)
[10:38:55] [PASSED] 0x7D45 (METEORLAKE)
[10:38:55] [PASSED] 0x7D55 (METEORLAKE)
[10:38:55] [PASSED] 0x7D60 (METEORLAKE)
[10:38:55] [PASSED] 0x7DD5 (METEORLAKE)
[10:38:55] [PASSED] 0x6420 (LUNARLAKE)
[10:38:55] [PASSED] 0x64A0 (LUNARLAKE)
[10:38:55] [PASSED] 0x64B0 (LUNARLAKE)
[10:38:55] [PASSED] 0xE202 (BATTLEMAGE)
[10:38:55] [PASSED] 0xE209 (BATTLEMAGE)
[10:38:55] [PASSED] 0xE20B (BATTLEMAGE)
[10:38:55] [PASSED] 0xE20C (BATTLEMAGE)
[10:38:55] [PASSED] 0xE20D (BATTLEMAGE)
[10:38:55] [PASSED] 0xE210 (BATTLEMAGE)
[10:38:55] [PASSED] 0xE211 (BATTLEMAGE)
[10:38:55] [PASSED] 0xE212 (BATTLEMAGE)
[10:38:55] [PASSED] 0xE216 (BATTLEMAGE)
[10:38:55] [PASSED] 0xE220 (BATTLEMAGE)
[10:38:55] [PASSED] 0xE221 (BATTLEMAGE)
[10:38:55] [PASSED] 0xE222 (BATTLEMAGE)
[10:38:55] [PASSED] 0xE223 (BATTLEMAGE)
[10:38:55] [PASSED] 0xB080 (PANTHERLAKE)
[10:38:55] [PASSED] 0xB081 (PANTHERLAKE)
[10:38:55] [PASSED] 0xB082 (PANTHERLAKE)
[10:38:55] [PASSED] 0xB083 (PANTHERLAKE)
[10:38:55] [PASSED] 0xB084 (PANTHERLAKE)
[10:38:55] [PASSED] 0xB085 (PANTHERLAKE)
[10:38:55] [PASSED] 0xB086 (PANTHERLAKE)
[10:38:55] [PASSED] 0xB087 (PANTHERLAKE)
[10:38:55] [PASSED] 0xB08F (PANTHERLAKE)
[10:38:55] [PASSED] 0xB090 (PANTHERLAKE)
[10:38:55] [PASSED] 0xB0A0 (PANTHERLAKE)
[10:38:55] [PASSED] 0xB0B0 (PANTHERLAKE)
[10:38:55] [PASSED] 0xD740 (NOVALAKE_S)
[10:38:55] [PASSED] 0xD741 (NOVALAKE_S)
[10:38:55] [PASSED] 0xD742 (NOVALAKE_S)
[10:38:55] [PASSED] 0xD743 (NOVALAKE_S)
[10:38:55] [PASSED] 0xD744 (NOVALAKE_S)
[10:38:55] [PASSED] 0xD745 (NOVALAKE_S)
[10:38:55] [PASSED] 0x674C (CRESCENTISLAND)
[10:38:55] [PASSED] 0xFD80 (PANTHERLAKE)
[10:38:55] [PASSED] 0xFD81 (PANTHERLAKE)
[10:38:55] =============== [PASSED] check_platform_desc ===============
[10:38:55] ===================== [PASSED] xe_pci ======================
[10:38:55] =================== xe_rtp (2 subtests) ====================
[10:38:55] =============== xe_rtp_process_to_sr_tests  ================
[10:38:55] [PASSED] coalesce-same-reg
[10:38:55] [PASSED] no-match-no-add
[10:38:55] [PASSED] match-or
[10:38:55] [PASSED] match-or-xfail
[10:38:55] [PASSED] no-match-no-add-multiple-rules
[10:38:55] [PASSED] two-regs-two-entries
[10:38:55] [PASSED] clr-one-set-other
[10:38:55] [PASSED] set-field
[10:38:55] [PASSED] conflict-duplicate
[10:38:55] [PASSED] conflict-not-disjoint
[10:38:55] [PASSED] conflict-reg-type
[10:38:55] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[10:38:55] ================== xe_rtp_process_tests  ===================
[10:38:55] [PASSED] active1
[10:38:55] [PASSED] active2
[10:38:55] [PASSED] active-inactive
[10:38:55] [PASSED] inactive-active
[10:38:55] [PASSED] inactive-1st_or_active-inactive
[10:38:55] [PASSED] inactive-2nd_or_active-inactive
[10:38:55] [PASSED] inactive-last_or_active-inactive
[10:38:55] [PASSED] inactive-no_or_active-inactive
[10:38:55] ============== [PASSED] xe_rtp_process_tests ===============
[10:38:55] ===================== [PASSED] xe_rtp ======================
[10:38:55] ==================== xe_wa (1 subtest) =====================
[10:38:55] ======================== xe_wa_gt  =========================
[10:38:55] [PASSED] TIGERLAKE B0
[10:38:55] [PASSED] DG1 A0
[10:38:55] [PASSED] DG1 B0
[10:38:55] [PASSED] ALDERLAKE_S A0
[10:38:55] [PASSED] ALDERLAKE_S B0
[10:38:55] [PASSED] ALDERLAKE_S C0
[10:38:55] [PASSED] ALDERLAKE_S D0
[10:38:55] [PASSED] ALDERLAKE_P A0
[10:38:55] [PASSED] ALDERLAKE_P B0
[10:38:55] [PASSED] ALDERLAKE_P C0
[10:38:55] [PASSED] ALDERLAKE_S RPLS D0
[10:38:55] [PASSED] ALDERLAKE_P RPLU E0
[10:38:55] [PASSED] DG2 G10 C0
[10:38:55] [PASSED] DG2 G11 B1
[10:38:55] [PASSED] DG2 G12 A1
[10:38:55] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[10:38:55] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[10:38:55] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[10:38:55] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[10:38:55] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[10:38:55] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[10:38:55] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[10:38:55] ==================== [PASSED] xe_wa_gt =====================
[10:38:55] ====================== [PASSED] xe_wa ======================
[10:38:55] ============================================================
[10:38:55] Testing complete. Ran 510 tests: passed: 492, skipped: 18
[10:38:55] Elapsed time: 35.242s total, 4.223s configuring, 30.552s building, 0.459s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[10:38:55] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[10:38:57] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[10:39:22] Starting KUnit Kernel (1/1)...
[10:39:22] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[10:39:22] ============ drm_test_pick_cmdline (2 subtests) ============
[10:39:22] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[10:39:22] =============== drm_test_pick_cmdline_named  ===============
[10:39:22] [PASSED] NTSC
[10:39:22] [PASSED] NTSC-J
[10:39:22] [PASSED] PAL
[10:39:22] [PASSED] PAL-M
[10:39:22] =========== [PASSED] drm_test_pick_cmdline_named ===========
[10:39:22] ============== [PASSED] drm_test_pick_cmdline ==============
[10:39:22] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[10:39:22] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[10:39:22] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[10:39:22] =========== drm_validate_clone_mode (2 subtests) ===========
[10:39:22] ============== drm_test_check_in_clone_mode  ===============
[10:39:22] [PASSED] in_clone_mode
[10:39:22] [PASSED] not_in_clone_mode
[10:39:22] ========== [PASSED] drm_test_check_in_clone_mode ===========
[10:39:22] =============== drm_test_check_valid_clones  ===============
[10:39:22] [PASSED] not_in_clone_mode
[10:39:22] [PASSED] valid_clone
[10:39:22] [PASSED] invalid_clone
[10:39:22] =========== [PASSED] drm_test_check_valid_clones ===========
[10:39:22] ============= [PASSED] drm_validate_clone_mode =============
[10:39:22] ============= drm_validate_modeset (1 subtest) =============
[10:39:22] [PASSED] drm_test_check_connector_changed_modeset
[10:39:22] ============== [PASSED] drm_validate_modeset ===============
[10:39:22] ====== drm_test_bridge_get_current_state (2 subtests) ======
[10:39:22] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[10:39:22] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[10:39:22] ======== [PASSED] drm_test_bridge_get_current_state ========
[10:39:22] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[10:39:22] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[10:39:22] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[10:39:22] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[10:39:22] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[10:39:22] ============== drm_bridge_alloc (2 subtests) ===============
[10:39:22] [PASSED] drm_test_drm_bridge_alloc_basic
[10:39:22] [PASSED] drm_test_drm_bridge_alloc_get_put
[10:39:22] ================ [PASSED] drm_bridge_alloc =================
[10:39:22] ================== drm_buddy (8 subtests) ==================
[10:39:22] [PASSED] drm_test_buddy_alloc_limit
[10:39:22] [PASSED] drm_test_buddy_alloc_optimistic
[10:39:22] [PASSED] drm_test_buddy_alloc_pessimistic
[10:39:22] [PASSED] drm_test_buddy_alloc_pathological
[10:39:22] [PASSED] drm_test_buddy_alloc_contiguous
[10:39:22] [PASSED] drm_test_buddy_alloc_clear
[10:39:22] [PASSED] drm_test_buddy_alloc_range_bias
[10:39:22] [PASSED] drm_test_buddy_fragmentation_performance
[10:39:22] ==================== [PASSED] drm_buddy ====================
[10:39:22] ============= drm_cmdline_parser (40 subtests) =============
[10:39:22] [PASSED] drm_test_cmdline_force_d_only
[10:39:22] [PASSED] drm_test_cmdline_force_D_only_dvi
[10:39:22] [PASSED] drm_test_cmdline_force_D_only_hdmi
[10:39:22] [PASSED] drm_test_cmdline_force_D_only_not_digital
[10:39:22] [PASSED] drm_test_cmdline_force_e_only
[10:39:22] [PASSED] drm_test_cmdline_res
[10:39:22] [PASSED] drm_test_cmdline_res_vesa
[10:39:22] [PASSED] drm_test_cmdline_res_vesa_rblank
[10:39:22] [PASSED] drm_test_cmdline_res_rblank
[10:39:22] [PASSED] drm_test_cmdline_res_bpp
[10:39:22] [PASSED] drm_test_cmdline_res_refresh
[10:39:22] [PASSED] drm_test_cmdline_res_bpp_refresh
[10:39:22] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[10:39:22] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[10:39:22] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[10:39:22] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[10:39:22] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[10:39:22] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[10:39:22] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[10:39:22] [PASSED] drm_test_cmdline_res_margins_force_on
[10:39:22] [PASSED] drm_test_cmdline_res_vesa_margins
[10:39:22] [PASSED] drm_test_cmdline_name
[10:39:22] [PASSED] drm_test_cmdline_name_bpp
[10:39:22] [PASSED] drm_test_cmdline_name_option
[10:39:22] [PASSED] drm_test_cmdline_name_bpp_option
[10:39:22] [PASSED] drm_test_cmdline_rotate_0
[10:39:22] [PASSED] drm_test_cmdline_rotate_90
[10:39:22] [PASSED] drm_test_cmdline_rotate_180
[10:39:22] [PASSED] drm_test_cmdline_rotate_270
[10:39:22] [PASSED] drm_test_cmdline_hmirror
[10:39:22] [PASSED] drm_test_cmdline_vmirror
[10:39:22] [PASSED] drm_test_cmdline_margin_options
[10:39:22] [PASSED] drm_test_cmdline_multiple_options
[10:39:22] [PASSED] drm_test_cmdline_bpp_extra_and_option
[10:39:22] [PASSED] drm_test_cmdline_extra_and_option
[10:39:22] [PASSED] drm_test_cmdline_freestanding_options
[10:39:22] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[10:39:22] [PASSED] drm_test_cmdline_panel_orientation
[10:39:22] ================ drm_test_cmdline_invalid  =================
[10:39:22] [PASSED] margin_only
[10:39:22] [PASSED] interlace_only
[10:39:22] [PASSED] res_missing_x
[10:39:22] [PASSED] res_missing_y
[10:39:22] [PASSED] res_bad_y
[10:39:22] [PASSED] res_missing_y_bpp
[10:39:22] [PASSED] res_bad_bpp
[10:39:22] [PASSED] res_bad_refresh
[10:39:22] [PASSED] res_bpp_refresh_force_on_off
[10:39:22] [PASSED] res_invalid_mode
[10:39:22] [PASSED] res_bpp_wrong_place_mode
[10:39:22] [PASSED] name_bpp_refresh
[10:39:22] [PASSED] name_refresh
[10:39:22] [PASSED] name_refresh_wrong_mode
[10:39:22] [PASSED] name_refresh_invalid_mode
[10:39:22] [PASSED] rotate_multiple
[10:39:22] [PASSED] rotate_invalid_val
[10:39:22] [PASSED] rotate_truncated
[10:39:22] [PASSED] invalid_option
[10:39:22] [PASSED] invalid_tv_option
[10:39:22] [PASSED] truncated_tv_option
[10:39:22] ============ [PASSED] drm_test_cmdline_invalid =============
[10:39:22] =============== drm_test_cmdline_tv_options  ===============
[10:39:22] [PASSED] NTSC
[10:39:22] [PASSED] NTSC_443
[10:39:22] [PASSED] NTSC_J
[10:39:22] [PASSED] PAL
[10:39:22] [PASSED] PAL_M
[10:39:22] [PASSED] PAL_N
[10:39:22] [PASSED] SECAM
[10:39:22] [PASSED] MONO_525
[10:39:22] [PASSED] MONO_625
[10:39:22] =========== [PASSED] drm_test_cmdline_tv_options ===========
[10:39:22] =============== [PASSED] drm_cmdline_parser ================
[10:39:22] ========== drmm_connector_hdmi_init (20 subtests) ==========
[10:39:22] [PASSED] drm_test_connector_hdmi_init_valid
[10:39:22] [PASSED] drm_test_connector_hdmi_init_bpc_8
[10:39:22] [PASSED] drm_test_connector_hdmi_init_bpc_10
[10:39:22] [PASSED] drm_test_connector_hdmi_init_bpc_12
[10:39:22] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[10:39:22] [PASSED] drm_test_connector_hdmi_init_bpc_null
[10:39:22] [PASSED] drm_test_connector_hdmi_init_formats_empty
[10:39:22] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[10:39:22] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[10:39:22] [PASSED] supported_formats=0x9 yuv420_allowed=1
[10:39:22] [PASSED] supported_formats=0x9 yuv420_allowed=0
[10:39:22] [PASSED] supported_formats=0x3 yuv420_allowed=1
[10:39:22] [PASSED] supported_formats=0x3 yuv420_allowed=0
[10:39:22] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[10:39:22] [PASSED] drm_test_connector_hdmi_init_null_ddc
[10:39:22] [PASSED] drm_test_connector_hdmi_init_null_product
[10:39:22] [PASSED] drm_test_connector_hdmi_init_null_vendor
[10:39:22] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[10:39:22] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[10:39:22] [PASSED] drm_test_connector_hdmi_init_product_valid
[10:39:22] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[10:39:22] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[10:39:22] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[10:39:22] ========= drm_test_connector_hdmi_init_type_valid  =========
[10:39:22] [PASSED] HDMI-A
[10:39:22] [PASSED] HDMI-B
[10:39:22] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[10:39:22] ======== drm_test_connector_hdmi_init_type_invalid  ========
[10:39:22] [PASSED] Unknown
[10:39:22] [PASSED] VGA
[10:39:22] [PASSED] DVI-I
[10:39:22] [PASSED] DVI-D
[10:39:22] [PASSED] DVI-A
[10:39:22] [PASSED] Composite
[10:39:22] [PASSED] SVIDEO
[10:39:22] [PASSED] LVDS
[10:39:22] [PASSED] Component
[10:39:22] [PASSED] DIN
[10:39:22] [PASSED] DP
[10:39:22] [PASSED] TV
[10:39:22] [PASSED] eDP
[10:39:22] [PASSED] Virtual
[10:39:22] [PASSED] DSI
[10:39:22] [PASSED] DPI
[10:39:22] [PASSED] Writeback
[10:39:22] [PASSED] SPI
[10:39:22] [PASSED] USB
[10:39:22] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[10:39:22] ============ [PASSED] drmm_connector_hdmi_init =============
[10:39:22] ============= drmm_connector_init (3 subtests) =============
[10:39:22] [PASSED] drm_test_drmm_connector_init
[10:39:22] [PASSED] drm_test_drmm_connector_init_null_ddc
[10:39:22] ========= drm_test_drmm_connector_init_type_valid  =========
[10:39:22] [PASSED] Unknown
[10:39:22] [PASSED] VGA
[10:39:22] [PASSED] DVI-I
[10:39:22] [PASSED] DVI-D
[10:39:22] [PASSED] DVI-A
[10:39:22] [PASSED] Composite
[10:39:22] [PASSED] SVIDEO
[10:39:22] [PASSED] LVDS
[10:39:22] [PASSED] Component
[10:39:22] [PASSED] DIN
[10:39:22] [PASSED] DP
[10:39:22] [PASSED] HDMI-A
[10:39:22] [PASSED] HDMI-B
[10:39:22] [PASSED] TV
[10:39:22] [PASSED] eDP
[10:39:22] [PASSED] Virtual
[10:39:22] [PASSED] DSI
[10:39:22] [PASSED] DPI
[10:39:22] [PASSED] Writeback
[10:39:22] [PASSED] SPI
[10:39:22] [PASSED] USB
[10:39:22] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[10:39:22] =============== [PASSED] drmm_connector_init ===============
[10:39:22] ========= drm_connector_dynamic_init (6 subtests) ==========
[10:39:22] [PASSED] drm_test_drm_connector_dynamic_init
[10:39:22] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[10:39:22] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[10:39:22] [PASSED] drm_test_drm_connector_dynamic_init_properties
[10:39:22] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[10:39:22] [PASSED] Unknown
[10:39:22] [PASSED] VGA
[10:39:22] [PASSED] DVI-I
[10:39:22] [PASSED] DVI-D
[10:39:22] [PASSED] DVI-A
[10:39:22] [PASSED] Composite
[10:39:22] [PASSED] SVIDEO
[10:39:22] [PASSED] LVDS
[10:39:22] [PASSED] Component
[10:39:22] [PASSED] DIN
[10:39:22] [PASSED] DP
[10:39:22] [PASSED] HDMI-A
[10:39:22] [PASSED] HDMI-B
[10:39:22] [PASSED] TV
[10:39:22] [PASSED] eDP
[10:39:22] [PASSED] Virtual
[10:39:22] [PASSED] DSI
[10:39:22] [PASSED] DPI
[10:39:22] [PASSED] Writeback
[10:39:22] [PASSED] SPI
[10:39:22] [PASSED] USB
[10:39:22] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[10:39:22] ======== drm_test_drm_connector_dynamic_init_name  =========
[10:39:22] [PASSED] Unknown
[10:39:22] [PASSED] VGA
[10:39:22] [PASSED] DVI-I
[10:39:22] [PASSED] DVI-D
[10:39:22] [PASSED] DVI-A
[10:39:22] [PASSED] Composite
[10:39:22] [PASSED] SVIDEO
[10:39:22] [PASSED] LVDS
[10:39:22] [PASSED] Component
[10:39:22] [PASSED] DIN
[10:39:22] [PASSED] DP
[10:39:22] [PASSED] HDMI-A
[10:39:22] [PASSED] HDMI-B
[10:39:22] [PASSED] TV
[10:39:22] [PASSED] eDP
[10:39:22] [PASSED] Virtual
[10:39:22] [PASSED] DSI
[10:39:22] [PASSED] DPI
[10:39:22] [PASSED] Writeback
[10:39:22] [PASSED] SPI
[10:39:22] [PASSED] USB
[10:39:22] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[10:39:22] =========== [PASSED] drm_connector_dynamic_init ============
[10:39:22] ==== drm_connector_dynamic_register_early (4 subtests) =====
[10:39:22] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[10:39:22] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[10:39:22] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[10:39:22] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[10:39:22] ====== [PASSED] drm_connector_dynamic_register_early =======
[10:39:22] ======= drm_connector_dynamic_register (7 subtests) ========
[10:39:22] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[10:39:22] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[10:39:22] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[10:39:22] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[10:39:22] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[10:39:22] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[10:39:22] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[10:39:22] ========= [PASSED] drm_connector_dynamic_register ==========
[10:39:22] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[10:39:22] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[10:39:22] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[10:39:22] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[10:39:22] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[10:39:22] ========== drm_test_get_tv_mode_from_name_valid  ===========
[10:39:22] [PASSED] NTSC
[10:39:22] [PASSED] NTSC-443
[10:39:22] [PASSED] NTSC-J
[10:39:22] [PASSED] PAL
[10:39:22] [PASSED] PAL-M
[10:39:22] [PASSED] PAL-N
[10:39:22] [PASSED] SECAM
[10:39:22] [PASSED] Mono
[10:39:22] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[10:39:22] [PASSED] drm_test_get_tv_mode_from_name_truncated
[10:39:22] ============ [PASSED] drm_get_tv_mode_from_name ============
[10:39:22] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[10:39:22] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[10:39:22] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[10:39:22] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[10:39:22] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[10:39:22] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[10:39:22] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[10:39:22] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[10:39:22] [PASSED] VIC 96
[10:39:22] [PASSED] VIC 97
[10:39:22] [PASSED] VIC 101
[10:39:22] [PASSED] VIC 102
[10:39:22] [PASSED] VIC 106
[10:39:22] [PASSED] VIC 107
[10:39:22] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[10:39:22] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[10:39:22] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[10:39:22] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[10:39:22] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[10:39:22] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[10:39:22] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[10:39:22] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[10:39:22] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[10:39:22] [PASSED] Automatic
[10:39:22] [PASSED] Full
[10:39:22] [PASSED] Limited 16:235
[10:39:22] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[10:39:22] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[10:39:22] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[10:39:22] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[10:39:22] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[10:39:22] [PASSED] RGB
[10:39:22] [PASSED] YUV 4:2:0
[10:39:22] [PASSED] YUV 4:2:2
[10:39:22] [PASSED] YUV 4:4:4
[10:39:22] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[10:39:22] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[10:39:22] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[10:39:22] ============= drm_damage_helper (21 subtests) ==============
[10:39:22] [PASSED] drm_test_damage_iter_no_damage
[10:39:22] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[10:39:22] [PASSED] drm_test_damage_iter_no_damage_src_moved
[10:39:22] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[10:39:22] [PASSED] drm_test_damage_iter_no_damage_not_visible
[10:39:22] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[10:39:22] [PASSED] drm_test_damage_iter_no_damage_no_fb
[10:39:22] [PASSED] drm_test_damage_iter_simple_damage
[10:39:22] [PASSED] drm_test_damage_iter_single_damage
[10:39:22] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[10:39:22] [PASSED] drm_test_damage_iter_single_damage_outside_src
[10:39:22] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[10:39:22] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[10:39:22] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[10:39:22] [PASSED] drm_test_damage_iter_single_damage_src_moved
[10:39:22] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[10:39:22] [PASSED] drm_test_damage_iter_damage
[10:39:22] [PASSED] drm_test_damage_iter_damage_one_intersect
[10:39:22] [PASSED] drm_test_damage_iter_damage_one_outside
[10:39:22] [PASSED] drm_test_damage_iter_damage_src_moved
[10:39:22] [PASSED] drm_test_damage_iter_damage_not_visible
[10:39:22] ================ [PASSED] drm_damage_helper ================
[10:39:22] ============== drm_dp_mst_helper (3 subtests) ==============
[10:39:22] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[10:39:22] [PASSED] Clock 154000 BPP 30 DSC disabled
[10:39:22] [PASSED] Clock 234000 BPP 30 DSC disabled
[10:39:22] [PASSED] Clock 297000 BPP 24 DSC disabled
[10:39:22] [PASSED] Clock 332880 BPP 24 DSC enabled
[10:39:22] [PASSED] Clock 324540 BPP 24 DSC enabled
[10:39:22] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[10:39:22] ============== drm_test_dp_mst_calc_pbn_div  ===============
[10:39:22] [PASSED] Link rate 2000000 lane count 4
[10:39:22] [PASSED] Link rate 2000000 lane count 2
[10:39:22] [PASSED] Link rate 2000000 lane count 1
[10:39:22] [PASSED] Link rate 1350000 lane count 4
[10:39:22] [PASSED] Link rate 1350000 lane count 2
[10:39:22] [PASSED] Link rate 1350000 lane count 1
[10:39:22] [PASSED] Link rate 1000000 lane count 4
[10:39:22] [PASSED] Link rate 1000000 lane count 2
[10:39:22] [PASSED] Link rate 1000000 lane count 1
[10:39:22] [PASSED] Link rate 810000 lane count 4
[10:39:22] [PASSED] Link rate 810000 lane count 2
[10:39:22] [PASSED] Link rate 810000 lane count 1
[10:39:22] [PASSED] Link rate 540000 lane count 4
[10:39:22] [PASSED] Link rate 540000 lane count 2
[10:39:22] [PASSED] Link rate 540000 lane count 1
[10:39:22] [PASSED] Link rate 270000 lane count 4
[10:39:22] [PASSED] Link rate 270000 lane count 2
[10:39:22] [PASSED] Link rate 270000 lane count 1
[10:39:22] [PASSED] Link rate 162000 lane count 4
[10:39:22] [PASSED] Link rate 162000 lane count 2
[10:39:22] [PASSED] Link rate 162000 lane count 1
[10:39:22] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[10:39:22] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[10:39:22] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[10:39:22] [PASSED] DP_POWER_UP_PHY with port number
[10:39:22] [PASSED] DP_POWER_DOWN_PHY with port number
[10:39:22] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[10:39:22] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[10:39:22] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[10:39:22] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[10:39:22] [PASSED] DP_QUERY_PAYLOAD with port number
[10:39:22] [PASSED] DP_QUERY_PAYLOAD with VCPI
[10:39:22] [PASSED] DP_REMOTE_DPCD_READ with port number
[10:39:22] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[10:39:22] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[10:39:22] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[10:39:22] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[10:39:22] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[10:39:22] [PASSED] DP_REMOTE_I2C_READ with port number
[10:39:22] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[10:39:22] [PASSED] DP_REMOTE_I2C_READ with transactions array
[10:39:22] [PASSED] DP_REMOTE_I2C_WRITE with port number
[10:39:22] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[10:39:22] [PASSED] DP_REMOTE_I2C_WRITE with data array
[10:39:22] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[10:39:22] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[10:39:22] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[10:39:22] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[10:39:22] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[10:39:22] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[10:39:22] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[10:39:22] ================ [PASSED] drm_dp_mst_helper ================
[10:39:22] ================== drm_exec (7 subtests) ===================
[10:39:22] [PASSED] sanitycheck
[10:39:22] [PASSED] test_lock
[10:39:22] [PASSED] test_lock_unlock
[10:39:22] [PASSED] test_duplicates
[10:39:22] [PASSED] test_prepare
[10:39:22] [PASSED] test_prepare_array
[10:39:22] [PASSED] test_multiple_loops
[10:39:22] ==================== [PASSED] drm_exec =====================
[10:39:22] =========== drm_format_helper_test (17 subtests) ===========
[10:39:22] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[10:39:22] [PASSED] single_pixel_source_buffer
[10:39:22] [PASSED] single_pixel_clip_rectangle
[10:39:22] [PASSED] well_known_colors
[10:39:22] [PASSED] destination_pitch
[10:39:22] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[10:39:22] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[10:39:22] [PASSED] single_pixel_source_buffer
[10:39:22] [PASSED] single_pixel_clip_rectangle
[10:39:22] [PASSED] well_known_colors
[10:39:22] [PASSED] destination_pitch
[10:39:22] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[10:39:22] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[10:39:22] [PASSED] single_pixel_source_buffer
[10:39:22] [PASSED] single_pixel_clip_rectangle
[10:39:22] [PASSED] well_known_colors
[10:39:22] [PASSED] destination_pitch
[10:39:22] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[10:39:22] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[10:39:22] [PASSED] single_pixel_source_buffer
[10:39:22] [PASSED] single_pixel_clip_rectangle
[10:39:22] [PASSED] well_known_colors
[10:39:22] [PASSED] destination_pitch
[10:39:22] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[10:39:22] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[10:39:22] [PASSED] single_pixel_source_buffer
[10:39:22] [PASSED] single_pixel_clip_rectangle
[10:39:22] [PASSED] well_known_colors
[10:39:22] [PASSED] destination_pitch
[10:39:22] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[10:39:22] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[10:39:22] [PASSED] single_pixel_source_buffer
[10:39:22] [PASSED] single_pixel_clip_rectangle
[10:39:22] [PASSED] well_known_colors
[10:39:22] [PASSED] destination_pitch
[10:39:22] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[10:39:22] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[10:39:22] [PASSED] single_pixel_source_buffer
[10:39:22] [PASSED] single_pixel_clip_rectangle
[10:39:22] [PASSED] well_known_colors
[10:39:22] [PASSED] destination_pitch
[10:39:22] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[10:39:22] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[10:39:22] [PASSED] single_pixel_source_buffer
[10:39:22] [PASSED] single_pixel_clip_rectangle
[10:39:22] [PASSED] well_known_colors
[10:39:22] [PASSED] destination_pitch
[10:39:22] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[10:39:22] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[10:39:22] [PASSED] single_pixel_source_buffer
[10:39:22] [PASSED] single_pixel_clip_rectangle
[10:39:22] [PASSED] well_known_colors
[10:39:22] [PASSED] destination_pitch
[10:39:22] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[10:39:22] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[10:39:22] [PASSED] single_pixel_source_buffer
[10:39:22] [PASSED] single_pixel_clip_rectangle
[10:39:22] [PASSED] well_known_colors
[10:39:22] [PASSED] destination_pitch
[10:39:22] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[10:39:22] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[10:39:22] [PASSED] single_pixel_source_buffer
[10:39:22] [PASSED] single_pixel_clip_rectangle
[10:39:22] [PASSED] well_known_colors
[10:39:22] [PASSED] destination_pitch
[10:39:22] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[10:39:22] ============== drm_test_fb_xrgb8888_to_mono  ===============
[10:39:22] [PASSED] single_pixel_source_buffer
[10:39:22] [PASSED] single_pixel_clip_rectangle
[10:39:22] [PASSED] well_known_colors
[10:39:22] [PASSED] destination_pitch
[10:39:22] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[10:39:22] ==================== drm_test_fb_swab  =====================
[10:39:22] [PASSED] single_pixel_source_buffer
[10:39:22] [PASSED] single_pixel_clip_rectangle
[10:39:22] [PASSED] well_known_colors
[10:39:22] [PASSED] destination_pitch
[10:39:22] ================ [PASSED] drm_test_fb_swab =================
[10:39:22] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[10:39:22] [PASSED] single_pixel_source_buffer
[10:39:22] [PASSED] single_pixel_clip_rectangle
[10:39:22] [PASSED] well_known_colors
[10:39:22] [PASSED] destination_pitch
[10:39:22] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[10:39:22] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[10:39:22] [PASSED] single_pixel_source_buffer
[10:39:22] [PASSED] single_pixel_clip_rectangle
[10:39:22] [PASSED] well_known_colors
[10:39:22] [PASSED] destination_pitch
[10:39:22] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[10:39:22] ================= drm_test_fb_clip_offset  =================
[10:39:22] [PASSED] pass through
[10:39:22] [PASSED] horizontal offset
[10:39:22] [PASSED] vertical offset
[10:39:22] [PASSED] horizontal and vertical offset
[10:39:22] [PASSED] horizontal offset (custom pitch)
[10:39:22] [PASSED] vertical offset (custom pitch)
[10:39:22] [PASSED] horizontal and vertical offset (custom pitch)
[10:39:22] ============= [PASSED] drm_test_fb_clip_offset =============
[10:39:22] =================== drm_test_fb_memcpy  ====================
[10:39:22] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[10:39:22] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[10:39:22] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[10:39:22] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[10:39:22] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[10:39:22] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[10:39:22] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[10:39:22] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[10:39:22] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[10:39:22] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[10:39:22] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[10:39:22] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[10:39:22] =============== [PASSED] drm_test_fb_memcpy ================
[10:39:22] ============= [PASSED] drm_format_helper_test ==============
[10:39:22] ================= drm_format (18 subtests) =================
[10:39:22] [PASSED] drm_test_format_block_width_invalid
[10:39:22] [PASSED] drm_test_format_block_width_one_plane
[10:39:22] [PASSED] drm_test_format_block_width_two_plane
[10:39:22] [PASSED] drm_test_format_block_width_three_plane
[10:39:22] [PASSED] drm_test_format_block_width_tiled
[10:39:22] [PASSED] drm_test_format_block_height_invalid
[10:39:22] [PASSED] drm_test_format_block_height_one_plane
[10:39:22] [PASSED] drm_test_format_block_height_two_plane
[10:39:22] [PASSED] drm_test_format_block_height_three_plane
[10:39:22] [PASSED] drm_test_format_block_height_tiled
[10:39:22] [PASSED] drm_test_format_min_pitch_invalid
[10:39:22] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[10:39:22] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[10:39:22] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[10:39:22] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[10:39:22] [PASSED] drm_test_format_min_pitch_two_plane
[10:39:22] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[10:39:22] [PASSED] drm_test_format_min_pitch_tiled
[10:39:22] =================== [PASSED] drm_format ====================
[10:39:22] ============== drm_framebuffer (10 subtests) ===============
[10:39:22] ========== drm_test_framebuffer_check_src_coords  ==========
[10:39:22] [PASSED] Success: source fits into fb
[10:39:22] [PASSED] Fail: overflowing fb with x-axis coordinate
[10:39:22] [PASSED] Fail: overflowing fb with y-axis coordinate
[10:39:22] [PASSED] Fail: overflowing fb with source width
[10:39:22] [PASSED] Fail: overflowing fb with source height
[10:39:22] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[10:39:22] [PASSED] drm_test_framebuffer_cleanup
[10:39:22] =============== drm_test_framebuffer_create  ===============
[10:39:22] [PASSED] ABGR8888 normal sizes
[10:39:22] [PASSED] ABGR8888 max sizes
[10:39:22] [PASSED] ABGR8888 pitch greater than min required
[10:39:22] [PASSED] ABGR8888 pitch less than min required
[10:39:22] [PASSED] ABGR8888 Invalid width
[10:39:22] [PASSED] ABGR8888 Invalid buffer handle
[10:39:22] [PASSED] No pixel format
[10:39:22] [PASSED] ABGR8888 Width 0
[10:39:22] [PASSED] ABGR8888 Height 0
[10:39:22] [PASSED] ABGR8888 Out of bound height * pitch combination
[10:39:22] [PASSED] ABGR8888 Large buffer offset
[10:39:22] [PASSED] ABGR8888 Buffer offset for inexistent plane
[10:39:22] [PASSED] ABGR8888 Invalid flag
[10:39:22] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[10:39:22] [PASSED] ABGR8888 Valid buffer modifier
[10:39:22] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[10:39:22] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[10:39:22] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[10:39:22] [PASSED] NV12 Normal sizes
[10:39:22] [PASSED] NV12 Max sizes
[10:39:22] [PASSED] NV12 Invalid pitch
[10:39:22] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[10:39:22] [PASSED] NV12 different  modifier per-plane
[10:39:22] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[10:39:22] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[10:39:22] [PASSED] NV12 Modifier for inexistent plane
[10:39:22] [PASSED] NV12 Handle for inexistent plane
[10:39:22] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[10:39:22] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[10:39:22] [PASSED] YVU420 Normal sizes
[10:39:22] [PASSED] YVU420 Max sizes
[10:39:22] [PASSED] YVU420 Invalid pitch
[10:39:22] [PASSED] YVU420 Different pitches
[10:39:22] [PASSED] YVU420 Different buffer offsets/pitches
[10:39:22] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[10:39:22] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[10:39:22] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[10:39:22] [PASSED] YVU420 Valid modifier
[10:39:22] [PASSED] YVU420 Different modifiers per plane
[10:39:22] [PASSED] YVU420 Modifier for inexistent plane
[10:39:22] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[10:39:22] [PASSED] X0L2 Normal sizes
[10:39:22] [PASSED] X0L2 Max sizes
[10:39:22] [PASSED] X0L2 Invalid pitch
[10:39:22] [PASSED] X0L2 Pitch greater than minimum required
[10:39:22] [PASSED] X0L2 Handle for inexistent plane
[10:39:22] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[10:39:22] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[10:39:22] [PASSED] X0L2 Valid modifier
[10:39:22] [PASSED] X0L2 Modifier for inexistent plane
[10:39:22] =========== [PASSED] drm_test_framebuffer_create ===========
[10:39:22] [PASSED] drm_test_framebuffer_free
[10:39:22] [PASSED] drm_test_framebuffer_init
[10:39:22] [PASSED] drm_test_framebuffer_init_bad_format
[10:39:22] [PASSED] drm_test_framebuffer_init_dev_mismatch
[10:39:22] [PASSED] drm_test_framebuffer_lookup
[10:39:22] [PASSED] drm_test_framebuffer_lookup_inexistent
[10:39:22] [PASSED] drm_test_framebuffer_modifiers_not_supported
[10:39:22] ================= [PASSED] drm_framebuffer =================
[10:39:22] ================ drm_gem_shmem (8 subtests) ================
[10:39:22] [PASSED] drm_gem_shmem_test_obj_create
[10:39:22] [PASSED] drm_gem_shmem_test_obj_create_private
[10:39:22] [PASSED] drm_gem_shmem_test_pin_pages
[10:39:22] [PASSED] drm_gem_shmem_test_vmap
[10:39:22] [PASSED] drm_gem_shmem_test_get_pages_sgt
[10:39:22] [PASSED] drm_gem_shmem_test_get_sg_table
[10:39:22] [PASSED] drm_gem_shmem_test_madvise
[10:39:22] [PASSED] drm_gem_shmem_test_purge
[10:39:22] ================== [PASSED] drm_gem_shmem ==================
[10:39:22] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[10:39:22] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[10:39:22] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[10:39:22] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[10:39:22] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[10:39:22] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[10:39:22] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[10:39:22] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[10:39:22] [PASSED] Automatic
[10:39:22] [PASSED] Full
[10:39:22] [PASSED] Limited 16:235
[10:39:22] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[10:39:22] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[10:39:22] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[10:39:22] [PASSED] drm_test_check_disable_connector
[10:39:22] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[10:39:22] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[10:39:22] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[10:39:22] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[10:39:22] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[10:39:22] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[10:39:22] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[10:39:22] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[10:39:22] [PASSED] drm_test_check_output_bpc_dvi
[10:39:22] [PASSED] drm_test_check_output_bpc_format_vic_1
[10:39:22] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[10:39:22] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[10:39:22] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[10:39:22] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[10:39:22] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[10:39:22] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[10:39:22] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[10:39:22] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[10:39:22] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[10:39:22] [PASSED] drm_test_check_broadcast_rgb_value
[10:39:22] [PASSED] drm_test_check_bpc_8_value
[10:39:22] [PASSED] drm_test_check_bpc_10_value
[10:39:22] [PASSED] drm_test_check_bpc_12_value
[10:39:22] [PASSED] drm_test_check_format_value
[10:39:22] [PASSED] drm_test_check_tmds_char_value
[10:39:22] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[10:39:22] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[10:39:22] [PASSED] drm_test_check_mode_valid
[10:39:22] [PASSED] drm_test_check_mode_valid_reject
[10:39:22] [PASSED] drm_test_check_mode_valid_reject_rate
[10:39:22] [PASSED] drm_test_check_mode_valid_reject_max_clock
[10:39:22] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[10:39:22] ================= drm_managed (2 subtests) =================
[10:39:22] [PASSED] drm_test_managed_release_action
[10:39:22] [PASSED] drm_test_managed_run_action
[10:39:22] =================== [PASSED] drm_managed ===================
[10:39:22] =================== drm_mm (6 subtests) ====================
[10:39:22] [PASSED] drm_test_mm_init
[10:39:22] [PASSED] drm_test_mm_debug
[10:39:22] [PASSED] drm_test_mm_align32
[10:39:22] [PASSED] drm_test_mm_align64
[10:39:22] [PASSED] drm_test_mm_lowest
[10:39:22] [PASSED] drm_test_mm_highest
[10:39:22] ===================== [PASSED] drm_mm ======================
[10:39:22] ============= drm_modes_analog_tv (5 subtests) =============
[10:39:22] [PASSED] drm_test_modes_analog_tv_mono_576i
[10:39:22] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[10:39:22] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[10:39:22] [PASSED] drm_test_modes_analog_tv_pal_576i
[10:39:22] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[10:39:22] =============== [PASSED] drm_modes_analog_tv ===============
[10:39:22] ============== drm_plane_helper (2 subtests) ===============
[10:39:22] =============== drm_test_check_plane_state  ================
[10:39:22] [PASSED] clipping_simple
[10:39:22] [PASSED] clipping_rotate_reflect
[10:39:22] [PASSED] positioning_simple
[10:39:22] [PASSED] upscaling
[10:39:22] [PASSED] downscaling
[10:39:22] [PASSED] rounding1
[10:39:22] [PASSED] rounding2
[10:39:22] [PASSED] rounding3
[10:39:22] [PASSED] rounding4
[10:39:22] =========== [PASSED] drm_test_check_plane_state ============
[10:39:22] =========== drm_test_check_invalid_plane_state  ============
[10:39:22] [PASSED] positioning_invalid
[10:39:22] [PASSED] upscaling_invalid
[10:39:22] [PASSED] downscaling_invalid
[10:39:22] ======= [PASSED] drm_test_check_invalid_plane_state ========
[10:39:22] ================ [PASSED] drm_plane_helper =================
[10:39:22] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[10:39:22] ====== drm_test_connector_helper_tv_get_modes_check  =======
[10:39:22] [PASSED] None
[10:39:22] [PASSED] PAL
[10:39:22] [PASSED] NTSC
[10:39:22] [PASSED] Both, NTSC Default
[10:39:22] [PASSED] Both, PAL Default
[10:39:22] [PASSED] Both, NTSC Default, with PAL on command-line
[10:39:22] [PASSED] Both, PAL Default, with NTSC on command-line
[10:39:22] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[10:39:22] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[10:39:22] ================== drm_rect (9 subtests) ===================
[10:39:22] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[10:39:22] [PASSED] drm_test_rect_clip_scaled_not_clipped
[10:39:22] [PASSED] drm_test_rect_clip_scaled_clipped
[10:39:22] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[10:39:22] ================= drm_test_rect_intersect  =================
[10:39:22] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[10:39:22] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[10:39:22] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[10:39:22] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[10:39:22] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[10:39:22] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[10:39:22] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[10:39:22] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[10:39:22] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[10:39:22] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[10:39:22] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[10:39:22] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[10:39:22] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[10:39:22] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[10:39:22] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[10:39:22] ============= [PASSED] drm_test_rect_intersect =============
[10:39:22] ================ drm_test_rect_calc_hscale  ================
[10:39:22] [PASSED] normal use
[10:39:22] [PASSED] out of max range
[10:39:22] [PASSED] out of min range
[10:39:22] [PASSED] zero dst
[10:39:22] [PASSED] negative src
[10:39:22] [PASSED] negative dst
[10:39:22] ============ [PASSED] drm_test_rect_calc_hscale ============
[10:39:22] ================ drm_test_rect_calc_vscale  ================
[10:39:22] [PASSED] normal use
stty: 'standard input': Inappropriate ioctl for device
[10:39:22] [PASSED] out of max range
[10:39:22] [PASSED] out of min range
[10:39:22] [PASSED] zero dst
[10:39:22] [PASSED] negative src
[10:39:22] [PASSED] negative dst
[10:39:22] ============ [PASSED] drm_test_rect_calc_vscale ============
[10:39:22] ================== drm_test_rect_rotate  ===================
[10:39:22] [PASSED] reflect-x
[10:39:22] [PASSED] reflect-y
[10:39:22] [PASSED] rotate-0
[10:39:22] [PASSED] rotate-90
[10:39:22] [PASSED] rotate-180
[10:39:22] [PASSED] rotate-270
[10:39:22] ============== [PASSED] drm_test_rect_rotate ===============
[10:39:22] ================ drm_test_rect_rotate_inv  =================
[10:39:22] [PASSED] reflect-x
[10:39:22] [PASSED] reflect-y
[10:39:22] [PASSED] rotate-0
[10:39:22] [PASSED] rotate-90
[10:39:22] [PASSED] rotate-180
[10:39:22] [PASSED] rotate-270
[10:39:22] ============ [PASSED] drm_test_rect_rotate_inv =============
[10:39:22] ==================== [PASSED] drm_rect =====================
[10:39:22] ============ drm_sysfb_modeset_test (1 subtest) ============
[10:39:22] ============ drm_test_sysfb_build_fourcc_list  =============
[10:39:22] [PASSED] no native formats
[10:39:22] [PASSED] XRGB8888 as native format
[10:39:22] [PASSED] remove duplicates
[10:39:22] [PASSED] convert alpha formats
[10:39:22] [PASSED] random formats
[10:39:22] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[10:39:22] ============= [PASSED] drm_sysfb_modeset_test ==============
[10:39:22] ================== drm_fixp (2 subtests) ===================
[10:39:22] [PASSED] drm_test_int2fixp
[10:39:22] [PASSED] drm_test_sm2fixp
[10:39:22] ==================== [PASSED] drm_fixp =====================
[10:39:22] ============================================================
[10:39:22] Testing complete. Ran 624 tests: passed: 624
[10:39:22] Elapsed time: 26.984s total, 1.609s configuring, 24.904s building, 0.433s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[10:39:23] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[10:39:24] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[10:39:33] Starting KUnit Kernel (1/1)...
[10:39:33] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[10:39:34] ================= ttm_device (5 subtests) ==================
[10:39:34] [PASSED] ttm_device_init_basic
[10:39:34] [PASSED] ttm_device_init_multiple
[10:39:34] [PASSED] ttm_device_fini_basic
[10:39:34] [PASSED] ttm_device_init_no_vma_man
[10:39:34] ================== ttm_device_init_pools  ==================
[10:39:34] [PASSED] No DMA allocations, no DMA32 required
[10:39:34] [PASSED] DMA allocations, DMA32 required
[10:39:34] [PASSED] No DMA allocations, DMA32 required
[10:39:34] [PASSED] DMA allocations, no DMA32 required
[10:39:34] ============== [PASSED] ttm_device_init_pools ==============
[10:39:34] =================== [PASSED] ttm_device ====================
[10:39:34] ================== ttm_pool (8 subtests) ===================
[10:39:34] ================== ttm_pool_alloc_basic  ===================
[10:39:34] [PASSED] One page
[10:39:34] [PASSED] More than one page
[10:39:34] [PASSED] Above the allocation limit
[10:39:34] [PASSED] One page, with coherent DMA mappings enabled
[10:39:34] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[10:39:34] ============== [PASSED] ttm_pool_alloc_basic ===============
[10:39:34] ============== ttm_pool_alloc_basic_dma_addr  ==============
[10:39:34] [PASSED] One page
[10:39:34] [PASSED] More than one page
[10:39:34] [PASSED] Above the allocation limit
[10:39:34] [PASSED] One page, with coherent DMA mappings enabled
[10:39:34] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[10:39:34] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[10:39:34] [PASSED] ttm_pool_alloc_order_caching_match
[10:39:34] [PASSED] ttm_pool_alloc_caching_mismatch
[10:39:34] [PASSED] ttm_pool_alloc_order_mismatch
[10:39:34] [PASSED] ttm_pool_free_dma_alloc
[10:39:34] [PASSED] ttm_pool_free_no_dma_alloc
[10:39:34] [PASSED] ttm_pool_fini_basic
[10:39:34] ==================== [PASSED] ttm_pool =====================
[10:39:34] ================ ttm_resource (8 subtests) =================
[10:39:34] ================= ttm_resource_init_basic  =================
[10:39:34] [PASSED] Init resource in TTM_PL_SYSTEM
[10:39:34] [PASSED] Init resource in TTM_PL_VRAM
[10:39:34] [PASSED] Init resource in a private placement
[10:39:34] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[10:39:34] ============= [PASSED] ttm_resource_init_basic =============
[10:39:34] [PASSED] ttm_resource_init_pinned
[10:39:34] [PASSED] ttm_resource_fini_basic
[10:39:34] [PASSED] ttm_resource_manager_init_basic
[10:39:34] [PASSED] ttm_resource_manager_usage_basic
[10:39:34] [PASSED] ttm_resource_manager_set_used_basic
[10:39:34] [PASSED] ttm_sys_man_alloc_basic
[10:39:34] [PASSED] ttm_sys_man_free_basic
[10:39:34] ================== [PASSED] ttm_resource ===================
[10:39:34] =================== ttm_tt (15 subtests) ===================
[10:39:34] ==================== ttm_tt_init_basic  ====================
[10:39:34] [PASSED] Page-aligned size
[10:39:34] [PASSED] Extra pages requested
[10:39:34] ================ [PASSED] ttm_tt_init_basic ================
[10:39:34] [PASSED] ttm_tt_init_misaligned
[10:39:34] [PASSED] ttm_tt_fini_basic
[10:39:34] [PASSED] ttm_tt_fini_sg
[10:39:34] [PASSED] ttm_tt_fini_shmem
[10:39:34] [PASSED] ttm_tt_create_basic
[10:39:34] [PASSED] ttm_tt_create_invalid_bo_type
[10:39:34] [PASSED] ttm_tt_create_ttm_exists
[10:39:34] [PASSED] ttm_tt_create_failed
[10:39:34] [PASSED] ttm_tt_destroy_basic
[10:39:34] [PASSED] ttm_tt_populate_null_ttm
[10:39:34] [PASSED] ttm_tt_populate_populated_ttm
[10:39:34] [PASSED] ttm_tt_unpopulate_basic
[10:39:34] [PASSED] ttm_tt_unpopulate_empty_ttm
[10:39:34] [PASSED] ttm_tt_swapin_basic
[10:39:34] ===================== [PASSED] ttm_tt ======================
[10:39:34] =================== ttm_bo (14 subtests) ===================
[10:39:34] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[10:39:34] [PASSED] Cannot be interrupted and sleeps
[10:39:34] [PASSED] Cannot be interrupted, locks straight away
[10:39:34] [PASSED] Can be interrupted, sleeps
[10:39:34] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[10:39:34] [PASSED] ttm_bo_reserve_locked_no_sleep
[10:39:34] [PASSED] ttm_bo_reserve_no_wait_ticket
[10:39:34] [PASSED] ttm_bo_reserve_double_resv
[10:39:34] [PASSED] ttm_bo_reserve_interrupted
[10:39:34] [PASSED] ttm_bo_reserve_deadlock
[10:39:34] [PASSED] ttm_bo_unreserve_basic
[10:39:34] [PASSED] ttm_bo_unreserve_pinned
[10:39:34] [PASSED] ttm_bo_unreserve_bulk
[10:39:34] [PASSED] ttm_bo_fini_basic
[10:39:34] [PASSED] ttm_bo_fini_shared_resv
[10:39:34] [PASSED] ttm_bo_pin_basic
[10:39:34] [PASSED] ttm_bo_pin_unpin_resource
[10:39:34] [PASSED] ttm_bo_multiple_pin_one_unpin
[10:39:34] ===================== [PASSED] ttm_bo ======================
[10:39:34] ============== ttm_bo_validate (21 subtests) ===============
[10:39:34] ============== ttm_bo_init_reserved_sys_man  ===============
[10:39:34] [PASSED] Buffer object for userspace
[10:39:34] [PASSED] Kernel buffer object
[10:39:34] [PASSED] Shared buffer object
[10:39:34] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[10:39:34] ============== ttm_bo_init_reserved_mock_man  ==============
[10:39:34] [PASSED] Buffer object for userspace
[10:39:34] [PASSED] Kernel buffer object
[10:39:34] [PASSED] Shared buffer object
[10:39:34] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[10:39:34] [PASSED] ttm_bo_init_reserved_resv
[10:39:34] ================== ttm_bo_validate_basic  ==================
[10:39:34] [PASSED] Buffer object for userspace
[10:39:34] [PASSED] Kernel buffer object
[10:39:34] [PASSED] Shared buffer object
[10:39:34] ============== [PASSED] ttm_bo_validate_basic ==============
[10:39:34] [PASSED] ttm_bo_validate_invalid_placement
[10:39:34] ============= ttm_bo_validate_same_placement  ==============
[10:39:34] [PASSED] System manager
[10:39:34] [PASSED] VRAM manager
[10:39:34] ========= [PASSED] ttm_bo_validate_same_placement ==========
[10:39:34] [PASSED] ttm_bo_validate_failed_alloc
[10:39:34] [PASSED] ttm_bo_validate_pinned
[10:39:34] [PASSED] ttm_bo_validate_busy_placement
[10:39:34] ================ ttm_bo_validate_multihop  =================
[10:39:34] [PASSED] Buffer object for userspace
[10:39:34] [PASSED] Kernel buffer object
[10:39:34] [PASSED] Shared buffer object
[10:39:34] ============ [PASSED] ttm_bo_validate_multihop =============
[10:39:34] ========== ttm_bo_validate_no_placement_signaled  ==========
[10:39:34] [PASSED] Buffer object in system domain, no page vector
[10:39:34] [PASSED] Buffer object in system domain with an existing page vector
[10:39:34] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[10:39:34] ======== ttm_bo_validate_no_placement_not_signaled  ========
[10:39:34] [PASSED] Buffer object for userspace
[10:39:34] [PASSED] Kernel buffer object
[10:39:34] [PASSED] Shared buffer object
[10:39:34] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[10:39:34] [PASSED] ttm_bo_validate_move_fence_signaled
[10:39:34] ========= ttm_bo_validate_move_fence_not_signaled  =========
[10:39:34] [PASSED] Waits for GPU
[10:39:34] [PASSED] Tries to lock straight away
[10:39:34] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[10:39:34] [PASSED] ttm_bo_validate_happy_evict
[10:39:34] [PASSED] ttm_bo_validate_all_pinned_evict
[10:39:34] [PASSED] ttm_bo_validate_allowed_only_evict
[10:39:34] [PASSED] ttm_bo_validate_deleted_evict
[10:39:34] [PASSED] ttm_bo_validate_busy_domain_evict
[10:39:34] [PASSED] ttm_bo_validate_evict_gutting
[10:39:34] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[10:39:34] ================= [PASSED] ttm_bo_validate =================
[10:39:34] ============================================================
[10:39:34] Testing complete. Ran 101 tests: passed: 101
[10:39:34] Elapsed time: 11.158s total, 1.604s configuring, 9.287s building, 0.226s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel