From: Imre Deak <imre.deak@intel.com>
To: <intel-gfx@lists.freedesktop.org>, <intel-xe@lists.freedesktop.org>
Cc: Vinod Govindapillai <vinod.govindapillai@intel.com>
Subject: [PATCH 04/19] drm/i915/dp: Align min/max DSC input BPPs to sink caps
Date: Mon, 22 Dec 2025 17:35:32 +0200 [thread overview]
Message-ID: <20251222153547.713360-6-imre.deak@intel.com> (raw)
In-Reply-To: <20251222153547.713360-1-imre.deak@intel.com>
Align the minimum/maximum DSC input BPPs to the corresponding sink DSC
input BPP capability limits already when computing the BPP limits. This
alignment is also performed later during state computation, however
there is no reason to initialize the limits to an unaligned/incorrect
value.
Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 25 +++++++++++++++++++++++--
1 file changed, 23 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 9d7a1df179a4e..4807a98d396a2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1905,6 +1905,23 @@ int intel_dp_dsc_max_src_input_bpc(struct intel_display *display)
return intel_dp_dsc_min_src_input_bpc();
}
+static int align_min_sink_dsc_input_bpp(const struct intel_connector *connector,
+ int min_pipe_bpp)
+{
+ u8 dsc_bpc[3];
+ int num_bpc;
+ int i;
+
+ num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd,
+ dsc_bpc);
+ for (i = num_bpc - 1; i >= 0; i--) {
+ if (dsc_bpc[i] * 3 >= min_pipe_bpp)
+ return dsc_bpc[i] * 3;
+ }
+
+ return 0;
+}
+
static int align_max_sink_dsc_input_bpp(const struct intel_connector *connector,
int max_pipe_bpp)
{
@@ -2680,15 +2697,19 @@ intel_dp_dsc_compute_pipe_bpp_limits(struct intel_connector *connector,
int dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(display);
limits->pipe.min_bpp = max(limits->pipe.min_bpp, dsc_min_bpc * 3);
+ limits->pipe.min_bpp = align_min_sink_dsc_input_bpp(connector, limits->pipe.min_bpp);
+
limits->pipe.max_bpp = min(limits->pipe.max_bpp, dsc_max_bpc * 3);
+ limits->pipe.max_bpp = align_max_sink_dsc_input_bpp(connector, limits->pipe.max_bpp);
if (limits->pipe.min_bpp <= 0 ||
limits->pipe.min_bpp > limits->pipe.max_bpp) {
drm_dbg_kms(display->drm,
- "[CONNECTOR:%d:%s] Invalid DSC src/sink input BPP (src:%d-%d pipe:%d-%d)\n",
+ "[CONNECTOR:%d:%s] Invalid DSC src/sink input BPP (src:%d-%d pipe:%d-%d sink-align:%d-%d)\n",
connector->base.base.id, connector->base.name,
dsc_min_bpc * 3, dsc_max_bpc * 3,
- orig_limits.pipe.min_bpp, orig_limits.pipe.max_bpp);
+ orig_limits.pipe.min_bpp, orig_limits.pipe.max_bpp,
+ limits->pipe.min_bpp, limits->pipe.max_bpp);
return false;
}
--
2.49.1
next prev parent reply other threads:[~2025-12-22 15:36 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-22 15:35 [PATCH 00/19] rm/i915/dp: Clean up link BW/DSC slice config computation (link BW) Imre Deak
2025-12-22 15:35 ` [PATCH 01/19] drm/i915/dp: Drop unused timeslots param from dsc_compute_link_config() Imre Deak
2025-12-22 15:35 ` [PATCH] drm/i915/dp: Fail state computation for invalid DSC source input BPP values Imre Deak
2025-12-22 15:35 ` [PATCH 02/19] drm/i915/dp: Factor out align_max_sink_dsc_input_bpp() Imre Deak
2025-12-22 15:35 ` [PATCH 03/19] drm/i915/dp: Factor out align_max_vesa_compressed_bpp_x16() Imre Deak
2025-12-22 15:35 ` Imre Deak [this message]
2025-12-22 15:35 ` [PATCH 05/19] drm/i915/dp: Align min/max compressed BPPs when calculating BPP limits Imre Deak
2025-12-22 15:35 ` [PATCH 06/19] drm/i915/dp: Drop intel_dp parameter from intel_dp_compute_config_link_bpp_limits() Imre Deak
2025-12-22 15:35 ` [PATCH 07/19] drm/i915/dp: Pass intel_output_format to intel_dp_dsc_sink_{min_max}_compressed_bpp() Imre Deak
2025-12-22 15:35 ` [PATCH 08/19] drm/i915/dp: Pass mode clock to dsc_throughput_quirk_max_bpp_x16() Imre Deak
2025-12-22 15:35 ` [PATCH 09/19] drm/i915/dp: Factor out compute_min_compressed_bpp_x16() Imre Deak
2025-12-22 15:35 ` [PATCH 10/19] drm/i915/dp: Factor out compute_max_compressed_bpp_x16() Imre Deak
2025-12-22 15:35 ` [PATCH 11/19] drm/i915/dp: Add intel_dp_mode_valid_with_dsc() Imre Deak
2025-12-22 15:35 ` [PATCH 12/19] drm/i915/dp: Unify detect and compute time DSC mode BW validation Imre Deak
2025-12-22 15:35 ` [PATCH 13/19] drm/i915/dp: Use helpers to align min/max compressed BPPs Imre Deak
2025-12-22 15:35 ` [PATCH 14/19] drm/i915/dp: Simplify computing DSC BPPs for eDP Imre Deak
2025-12-22 15:35 ` [PATCH 15/19] drm/i915/dp: Simplify computing DSC BPPs for DP-SST Imre Deak
2025-12-22 15:35 ` [PATCH 16/19] drm/i915/dp: Simplify computing forced DSC BPP " Imre Deak
2025-12-22 15:35 ` [PATCH 17/19] drm/i915/dp: Unify computing compressed BPP for DP-SST and eDP Imre Deak
2025-12-22 15:35 ` [PATCH 18/19] drm/i915/dp: Simplify eDP vs. DP compressed BPP computation Imre Deak
2025-12-22 15:35 ` [PATCH 19/19] drm/i915/dp: Simplify computing the DSC compressed BPP for DP-MST Imre Deak
2025-12-22 22:21 ` ✓ CI.KUnit: success for drm/i915/dp: Fail state computation for invalid DSC source input BPP values Patchwork
2025-12-22 22:36 ` ✗ CI.checksparse: warning " Patchwork
2025-12-22 22:58 ` ✓ Xe.CI.BAT: success " Patchwork
2025-12-23 6:35 ` ✓ Xe.CI.Full: " Patchwork
[not found] ` <176654308984.114937.922653558011609259@a3b018990fe9>
2026-01-13 17:33 ` ✓ i915.CI.Full: success for drm/i915/dp: Fail state computation for invalid DSC source input BPP values (rev3) Imre Deak
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