Re: [PATCH 1/2] drm/xe: Coalesce pagefault error handling

[Matt Roper <matthew.d.roper@intel.com>]

On Mon, Jan 12, 2026 at 11:47:57AM +0530, Varun Gupta wrote:
> The page fault is only ever printed on when the fault handling fails.
> Use a single dbg with the fault response status and its details.

This commit message here seems to be a copy of the one from
https://lore.kernel.org/all/20251107-pagefault-prefetch-v1-1-93291d619126@intel.com/
but doesn't match the code changes below.  It looks like the change
below just renames the xe_pagefault_print() function and adds an
additional (currently unused) err parameter.

Maybe you intended some of the changes from patch #2 (incrementing the
stats counters) to be included in this patch?  Either way, the commit
message needs to be updated.


Matt

> 
> Originally-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Matthew Brost <matthew.brost@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Varun Gupta <varun.gupta@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_pagefault.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_pagefault.c b/drivers/gpu/drm/xe/xe_pagefault.c
> index 6bee53d6ffc3..34dac4280b9d 100644
> --- a/drivers/gpu/drm/xe/xe_pagefault.c
> +++ b/drivers/gpu/drm/xe/xe_pagefault.c
> @@ -221,7 +221,7 @@ static bool xe_pagefault_queue_pop(struct xe_pagefault_queue *pf_queue,
>  	return found_fault;
>  }
>  
> -static void xe_pagefault_print(struct xe_pagefault *pf)
> +static void xe_pagefault_error_account(struct xe_pagefault *pf, int err)
>  {
>  	xe_gt_info(pf->gt, "\n\tASID: %d\n"
>  		   "\tFaulted Address: 0x%08x%08x\n"
> @@ -259,7 +259,7 @@ static void xe_pagefault_queue_work(struct work_struct *w)
>  
>  		err = xe_pagefault_service(&pf);
>  		if (err) {
> -			xe_pagefault_print(&pf);
> +			xe_pagefault_error_account(&pf, err);
>  			xe_gt_info(pf.gt, "Fault response: Unsuccessful %pe\n",
>  				   ERR_PTR(err));
>  		}
> -- 
> 2.43.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation