[PATCH 0/2] GuC CT memory optimizations

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* [PATCH 0/2] GuC CT memory optimizations
@ 2026-02-13 20:50 Matthew Brost
  2026-02-13 20:50 ` [PATCH 1/2] drm/xe: Split H2G and G2H into separate buffer objects Matthew Brost
                   ` (4 more replies)
  0 siblings, 5 replies; 7+ messages in thread
From: Matthew Brost @ 2026-02-13 20:50 UTC (permalink / raw)
  To: intel-xe; +Cc: francois.dugast, daniele.ceraolospurio, michal.wajdeczko

Profiling has shown that reading from VRAM on BMG is very slow and
introduces significant latency in GuC CT operations. To address this,
CPU-side read buffers (G2H) are moved to system memory, and unnecessary
CPU reads of VRAM in hot paths are removed. This is marked as a fixes
change due to the dramatic improvement in G2H performance, which affects
hot paths such as TLB invalidation fences and fault-storm handling.

We likely have similar issues in hardware fence signaling paths that
currently read from VRAM. A follow-up will move the LRC fence seqno (and
possibly other CPU-side LRC reads) to system memory as well.

Matt

Matthew Brost (2):
  drm/xe: Split H2G and G2H into separate buffer objects
  drm/xe: Remove H2G reads in CT send path in non-debug builds

 drivers/gpu/drm/xe/xe_guc_ct.c       | 80 ++++++++++++++++++----------
 drivers/gpu/drm/xe/xe_guc_ct_types.h |  6 ++-
 2 files changed, 55 insertions(+), 31 deletions(-)

-- 
2.34.1

^ permalink raw reply	[flat|nested] 7+ messages in thread

* [PATCH 1/2] drm/xe: Split H2G and G2H into separate buffer objects
  2026-02-13 20:50 [PATCH 0/2] GuC CT memory optimizations Matthew Brost
@ 2026-02-13 20:50 ` Matthew Brost
  2026-02-13 21:17   ` Matthew Brost
  2026-02-13 20:50 ` [PATCH 2/2] drm/xe: Remove H2G reads in CT send path in non-debug builds Matthew Brost
                   ` (3 subsequent siblings)
  4 siblings, 1 reply; 7+ messages in thread
From: Matthew Brost @ 2026-02-13 20:50 UTC (permalink / raw)
  To: intel-xe; +Cc: francois.dugast, daniele.ceraolospurio, michal.wajdeczko

H2G and G2H buffers have different access patterns (H2G is CPU-write,
GuC-read, while G2H is GPU-write, CPU-read). On dGPU, these patterns
benefit from different memory placements: H2G in VRAM and G2H in system
memory. Split the CT buffer into two separate buffers—one for H2G and
one for G2H—and select the optimal placement for each.

This provides a significant performance improvement on the G2H read
path, reducing a single read from ~20 µs to under 1 µs on BMG.

Fixes: dd08ebf6c352 ("drm/xe: Introduce a new DRM driver for Intel GPUs")
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
 drivers/gpu/drm/xe/xe_guc_ct.c       | 66 ++++++++++++++++++----------
 drivers/gpu/drm/xe/xe_guc_ct_types.h |  6 ++-
 2 files changed, 48 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c b/drivers/gpu/drm/xe/xe_guc_ct.c
index 8a45573f8812..5d8d90a4f879 100644
--- a/drivers/gpu/drm/xe/xe_guc_ct.c
+++ b/drivers/gpu/drm/xe/xe_guc_ct.c
@@ -255,6 +255,7 @@ static bool g2h_fence_needs_alloc(struct g2h_fence *g2h_fence)
 
 #define CTB_DESC_SIZE		ALIGN(sizeof(struct guc_ct_buffer_desc), SZ_2K)
 #define CTB_H2G_BUFFER_OFFSET	(CTB_DESC_SIZE * 2)
+#define CTB_G2H_BUFFER_OFFSET	(CTB_DESC_SIZE * 2)
 #define CTB_H2G_BUFFER_SIZE	(SZ_4K)
 #define CTB_H2G_BUFFER_DWORDS	(CTB_H2G_BUFFER_SIZE / sizeof(u32))
 #define CTB_G2H_BUFFER_SIZE	(SZ_128K)
@@ -279,10 +280,14 @@ long xe_guc_ct_queue_proc_time_jiffies(struct xe_guc_ct *ct)
 	return (CTB_H2G_BUFFER_SIZE / SZ_4K) * HZ;
 }
 
-static size_t guc_ct_size(void)
+static size_t guc_h2g_size(void)
 {
-	return CTB_H2G_BUFFER_OFFSET + CTB_H2G_BUFFER_SIZE +
-		CTB_G2H_BUFFER_SIZE;
+	return CTB_H2G_BUFFER_OFFSET + CTB_H2G_BUFFER_SIZE;
+}
+
+static size_t guc_g2h_size(void)
+{
+	return CTB_G2H_BUFFER_OFFSET + CTB_G2H_BUFFER_SIZE;
 }
 
 static void guc_ct_fini(struct drm_device *drm, void *arg)
@@ -311,7 +316,8 @@ int xe_guc_ct_init_noalloc(struct xe_guc_ct *ct)
 	struct xe_gt *gt = ct_to_gt(ct);
 	int err;
 
-	xe_gt_assert(gt, !(guc_ct_size() % PAGE_SIZE));
+	xe_gt_assert(gt, !(guc_h2g_size() % PAGE_SIZE));
+	xe_gt_assert(gt, !(guc_g2h_size() % PAGE_SIZE));
 
 	err = drmm_mutex_init(&xe->drm, &ct->lock);
 	if (err)
@@ -356,7 +362,17 @@ int xe_guc_ct_init(struct xe_guc_ct *ct)
 	struct xe_tile *tile = gt_to_tile(gt);
 	struct xe_bo *bo;
 
-	bo = xe_managed_bo_create_pin_map(xe, tile, guc_ct_size(),
+	bo = xe_managed_bo_create_pin_map(xe, tile, guc_h2g_size(),
+					  XE_BO_FLAG_SYSTEM |
+					  XE_BO_FLAG_GGTT |
+					  XE_BO_FLAG_GGTT_INVALIDATE |
+					  XE_BO_FLAG_PINNED_NORESTORE);
+	if (IS_ERR(bo))
+		return PTR_ERR(bo);
+
+	ct->bo_h2g = bo;
+
+	bo = xe_managed_bo_create_pin_map(xe, tile, guc_g2h_size(),
 					  XE_BO_FLAG_SYSTEM |
 					  XE_BO_FLAG_GGTT |
 					  XE_BO_FLAG_GGTT_INVALIDATE |
@@ -364,7 +380,7 @@ int xe_guc_ct_init(struct xe_guc_ct *ct)
 	if (IS_ERR(bo))
 		return PTR_ERR(bo);
 
-	ct->bo = bo;
+	ct->bo_g2h = bo;
 
 	return devm_add_action_or_reset(xe->drm.dev, guc_action_disable_ct, ct);
 }
@@ -389,7 +405,7 @@ int xe_guc_ct_init_post_hwconfig(struct xe_guc_ct *ct)
 	xe_assert(xe, !xe_guc_ct_enabled(ct));
 
 	if (IS_DGFX(xe)) {
-		ret = xe_managed_bo_reinit_in_vram(xe, tile, &ct->bo);
+		ret = xe_managed_bo_reinit_in_vram(xe, tile, &ct->bo_h2g);
 		if (ret)
 			return ret;
 	}
@@ -439,8 +455,7 @@ static void guc_ct_ctb_g2h_init(struct xe_device *xe, struct guc_ctb *g2h,
 	g2h->desc = IOSYS_MAP_INIT_OFFSET(map, CTB_DESC_SIZE);
 	xe_map_memset(xe, &g2h->desc, 0, 0, sizeof(struct guc_ct_buffer_desc));
 
-	g2h->cmds = IOSYS_MAP_INIT_OFFSET(map, CTB_H2G_BUFFER_OFFSET +
-					    CTB_H2G_BUFFER_SIZE);
+	g2h->cmds = IOSYS_MAP_INIT_OFFSET(map, CTB_G2H_BUFFER_OFFSET);
 }
 
 static int guc_ct_ctb_h2g_register(struct xe_guc_ct *ct)
@@ -449,8 +464,8 @@ static int guc_ct_ctb_h2g_register(struct xe_guc_ct *ct)
 	u32 desc_addr, ctb_addr, size;
 	int err;
 
-	desc_addr = xe_bo_ggtt_addr(ct->bo);
-	ctb_addr = xe_bo_ggtt_addr(ct->bo) + CTB_H2G_BUFFER_OFFSET;
+	desc_addr = xe_bo_ggtt_addr(ct->bo_h2g);
+	ctb_addr = xe_bo_ggtt_addr(ct->bo_h2g) + CTB_H2G_BUFFER_OFFSET;
 	size = ct->ctbs.h2g.info.size * sizeof(u32);
 
 	err = xe_guc_self_cfg64(guc,
@@ -476,9 +491,8 @@ static int guc_ct_ctb_g2h_register(struct xe_guc_ct *ct)
 	u32 desc_addr, ctb_addr, size;
 	int err;
 
-	desc_addr = xe_bo_ggtt_addr(ct->bo) + CTB_DESC_SIZE;
-	ctb_addr = xe_bo_ggtt_addr(ct->bo) + CTB_H2G_BUFFER_OFFSET +
-		CTB_H2G_BUFFER_SIZE;
+	desc_addr = xe_bo_ggtt_addr(ct->bo_g2h) + CTB_DESC_SIZE;
+	ctb_addr = xe_bo_ggtt_addr(ct->bo_g2h) + CTB_G2H_BUFFER_OFFSET;
 	size = ct->ctbs.g2h.info.size * sizeof(u32);
 
 	err = xe_guc_self_cfg64(guc,
@@ -605,9 +619,12 @@ static int __xe_guc_ct_start(struct xe_guc_ct *ct, bool needs_register)
 	xe_gt_assert(gt, !xe_guc_ct_enabled(ct));
 
 	if (needs_register) {
-		xe_map_memset(xe, &ct->bo->vmap, 0, 0, xe_bo_size(ct->bo));
-		guc_ct_ctb_h2g_init(xe, &ct->ctbs.h2g, &ct->bo->vmap);
-		guc_ct_ctb_g2h_init(xe, &ct->ctbs.g2h, &ct->bo->vmap);
+		xe_map_memset(xe, &ct->bo_h2g->vmap, 0, 0,
+			      xe_bo_size(ct->bo_h2g));
+		xe_map_memset(xe, &ct->bo_g2h->vmap, 0, 0,
+			      xe_bo_size(ct->bo_g2h));
+		guc_ct_ctb_h2g_init(xe, &ct->ctbs.h2g, &ct->bo_h2g->vmap);
+		guc_ct_ctb_g2h_init(xe, &ct->ctbs.g2h, &ct->bo_g2h->vmap);
 
 		err = guc_ct_ctb_h2g_register(ct);
 		if (err)
@@ -624,7 +641,7 @@ static int __xe_guc_ct_start(struct xe_guc_ct *ct, bool needs_register)
 		ct->ctbs.h2g.info.broken = false;
 		ct->ctbs.g2h.info.broken = false;
 		/* Skip everything in H2G buffer */
-		xe_map_memset(xe, &ct->bo->vmap, CTB_H2G_BUFFER_OFFSET, 0,
+		xe_map_memset(xe, &ct->bo_h2g->vmap, CTB_H2G_BUFFER_OFFSET, 0,
 			      CTB_H2G_BUFFER_SIZE);
 	}
 
@@ -1963,8 +1980,9 @@ static struct xe_guc_ct_snapshot *guc_ct_snapshot_alloc(struct xe_guc_ct *ct, bo
 	if (!snapshot)
 		return NULL;
 
-	if (ct->bo && want_ctb) {
-		snapshot->ctb_size = xe_bo_size(ct->bo);
+	if (ct->bo_h2g && ct->bo_g2h && want_ctb) {
+		snapshot->ctb_size = xe_bo_size(ct->bo_h2g) +
+			xe_bo_size(ct->bo_g2h);
 		snapshot->ctb = kmalloc(snapshot->ctb_size, atomic ? GFP_ATOMIC : GFP_KERNEL);
 	}
 
@@ -2012,8 +2030,12 @@ static struct xe_guc_ct_snapshot *guc_ct_snapshot_capture(struct xe_guc_ct *ct,
 		guc_ctb_snapshot_capture(xe, &ct->ctbs.g2h, &snapshot->g2h);
 	}
 
-	if (ct->bo && snapshot->ctb)
-		xe_map_memcpy_from(xe, snapshot->ctb, &ct->bo->vmap, 0, snapshot->ctb_size);
+	if (ct->bo_h2g && ct->bo_g2h && snapshot->ctb) {
+		xe_map_memcpy_from(xe, snapshot->ctb, &ct->bo_h2g->vmap, 0,
+				   xe_bo_size(ct->bo_h2g));
+		xe_map_memcpy_from(xe, snapshot->ctb, &ct->bo_g2h->vmap,
+				   xe_bo_size(ct->bo_h2g), xe_bo_size(ct->bo_g2h));
+	}
 
 	return snapshot;
 }
diff --git a/drivers/gpu/drm/xe/xe_guc_ct_types.h b/drivers/gpu/drm/xe/xe_guc_ct_types.h
index 09d7ff1ef42a..385a607e4777 100644
--- a/drivers/gpu/drm/xe/xe_guc_ct_types.h
+++ b/drivers/gpu/drm/xe/xe_guc_ct_types.h
@@ -126,8 +126,10 @@ struct xe_fast_req_fence {
  * for the H2G and G2H requests sent and received through the buffers.
  */
 struct xe_guc_ct {
-	/** @bo: Xe BO for CT */
-	struct xe_bo *bo;
+	/** @bo_h2g: Xe BO for H2G */
+	struct xe_bo *bo_h2g;
+	/** @bo_g2h: Xe BO for G2H */
+	struct xe_bo *bo_g2h;
 	/** @lock: protects everything in CT layer */
 	struct mutex lock;
 	/** @fast_lock: protects G2H channel and credits */
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 7+ messages in thread

* Re: [PATCH 1/2] drm/xe: Split H2G and G2H into separate buffer objects
  2026-02-13 20:50 ` [PATCH 1/2] drm/xe: Split H2G and G2H into separate buffer objects Matthew Brost
@ 2026-02-13 21:17   ` Matthew Brost
  0 siblings, 0 replies; 7+ messages in thread
From: Matthew Brost @ 2026-02-13 21:17 UTC (permalink / raw)
  To: intel-xe; +Cc: francois.dugast, daniele.ceraolospurio, michal.wajdeczko

On Fri, Feb 13, 2026 at 12:50:42PM -0800, Matthew Brost wrote:
> H2G and G2H buffers have different access patterns (H2G is CPU-write,
> GuC-read, while G2H is GPU-write, CPU-read). On dGPU, these patterns
> benefit from different memory placements: H2G in VRAM and G2H in system
> memory. Split the CT buffer into two separate buffers—one for H2G and
> one for G2H—and select the optimal placement for each.
> 
> This provides a significant performance improvement on the G2H read
> path, reducing a single read from ~20 µs to under 1 µs on BMG.
> 
> Fixes: dd08ebf6c352 ("drm/xe: Introduce a new DRM driver for Intel GPUs")
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_guc_ct.c       | 66 ++++++++++++++++++----------
>  drivers/gpu/drm/xe/xe_guc_ct_types.h |  6 ++-
>  2 files changed, 48 insertions(+), 24 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c b/drivers/gpu/drm/xe/xe_guc_ct.c
> index 8a45573f8812..5d8d90a4f879 100644
> --- a/drivers/gpu/drm/xe/xe_guc_ct.c
> +++ b/drivers/gpu/drm/xe/xe_guc_ct.c
> @@ -255,6 +255,7 @@ static bool g2h_fence_needs_alloc(struct g2h_fence *g2h_fence)
>  
>  #define CTB_DESC_SIZE		ALIGN(sizeof(struct guc_ct_buffer_desc), SZ_2K)
>  #define CTB_H2G_BUFFER_OFFSET	(CTB_DESC_SIZE * 2)
> +#define CTB_G2H_BUFFER_OFFSET	(CTB_DESC_SIZE * 2)
>  #define CTB_H2G_BUFFER_SIZE	(SZ_4K)
>  #define CTB_H2G_BUFFER_DWORDS	(CTB_H2G_BUFFER_SIZE / sizeof(u32))
>  #define CTB_G2H_BUFFER_SIZE	(SZ_128K)
> @@ -279,10 +280,14 @@ long xe_guc_ct_queue_proc_time_jiffies(struct xe_guc_ct *ct)
>  	return (CTB_H2G_BUFFER_SIZE / SZ_4K) * HZ;
>  }
>  
> -static size_t guc_ct_size(void)
> +static size_t guc_h2g_size(void)
>  {
> -	return CTB_H2G_BUFFER_OFFSET + CTB_H2G_BUFFER_SIZE +
> -		CTB_G2H_BUFFER_SIZE;
> +	return CTB_H2G_BUFFER_OFFSET + CTB_H2G_BUFFER_SIZE;
> +}
> +
> +static size_t guc_g2h_size(void)
> +{
> +	return CTB_G2H_BUFFER_OFFSET + CTB_G2H_BUFFER_SIZE;
>  }
>  
>  static void guc_ct_fini(struct drm_device *drm, void *arg)
> @@ -311,7 +316,8 @@ int xe_guc_ct_init_noalloc(struct xe_guc_ct *ct)
>  	struct xe_gt *gt = ct_to_gt(ct);
>  	int err;
>  
> -	xe_gt_assert(gt, !(guc_ct_size() % PAGE_SIZE));
> +	xe_gt_assert(gt, !(guc_h2g_size() % PAGE_SIZE));
> +	xe_gt_assert(gt, !(guc_g2h_size() % PAGE_SIZE));
>  
>  	err = drmm_mutex_init(&xe->drm, &ct->lock);
>  	if (err)
> @@ -356,7 +362,17 @@ int xe_guc_ct_init(struct xe_guc_ct *ct)
>  	struct xe_tile *tile = gt_to_tile(gt);
>  	struct xe_bo *bo;
>  
> -	bo = xe_managed_bo_create_pin_map(xe, tile, guc_ct_size(),
> +	bo = xe_managed_bo_create_pin_map(xe, tile, guc_h2g_size(),
> +					  XE_BO_FLAG_SYSTEM |
> +					  XE_BO_FLAG_GGTT |
> +					  XE_BO_FLAG_GGTT_INVALIDATE |
> +					  XE_BO_FLAG_PINNED_NORESTORE);
> +	if (IS_ERR(bo))
> +		return PTR_ERR(bo);
> +
> +	ct->bo_h2g = bo;
> +
> +	bo = xe_managed_bo_create_pin_map(xe, tile, guc_g2h_size(),
>  					  XE_BO_FLAG_SYSTEM |
>  					  XE_BO_FLAG_GGTT |
>  					  XE_BO_FLAG_GGTT_INVALIDATE |
> @@ -364,7 +380,7 @@ int xe_guc_ct_init(struct xe_guc_ct *ct)
>  	if (IS_ERR(bo))
>  		return PTR_ERR(bo);
>  
> -	ct->bo = bo;
> +	ct->bo_g2h = bo;
>  
>  	return devm_add_action_or_reset(xe->drm.dev, guc_action_disable_ct, ct);
>  }
> @@ -389,7 +405,7 @@ int xe_guc_ct_init_post_hwconfig(struct xe_guc_ct *ct)
>  	xe_assert(xe, !xe_guc_ct_enabled(ct));
>  
>  	if (IS_DGFX(xe)) {
> -		ret = xe_managed_bo_reinit_in_vram(xe, tile, &ct->bo);
> +		ret = xe_managed_bo_reinit_in_vram(xe, tile, &ct->bo_h2g);
>  		if (ret)
>  			return ret;
>  	}
> @@ -439,8 +455,7 @@ static void guc_ct_ctb_g2h_init(struct xe_device *xe, struct guc_ctb *g2h,
>  	g2h->desc = IOSYS_MAP_INIT_OFFSET(map, CTB_DESC_SIZE);
>  	xe_map_memset(xe, &g2h->desc, 0, 0, sizeof(struct guc_ct_buffer_desc));
>  
> -	g2h->cmds = IOSYS_MAP_INIT_OFFSET(map, CTB_H2G_BUFFER_OFFSET +
> -					    CTB_H2G_BUFFER_SIZE);
> +	g2h->cmds = IOSYS_MAP_INIT_OFFSET(map, CTB_G2H_BUFFER_OFFSET);
>  }
>  
>  static int guc_ct_ctb_h2g_register(struct xe_guc_ct *ct)
> @@ -449,8 +464,8 @@ static int guc_ct_ctb_h2g_register(struct xe_guc_ct *ct)
>  	u32 desc_addr, ctb_addr, size;
>  	int err;
>  
> -	desc_addr = xe_bo_ggtt_addr(ct->bo);
> -	ctb_addr = xe_bo_ggtt_addr(ct->bo) + CTB_H2G_BUFFER_OFFSET;
> +	desc_addr = xe_bo_ggtt_addr(ct->bo_h2g);
> +	ctb_addr = xe_bo_ggtt_addr(ct->bo_h2g) + CTB_H2G_BUFFER_OFFSET;
>  	size = ct->ctbs.h2g.info.size * sizeof(u32);
>  
>  	err = xe_guc_self_cfg64(guc,
> @@ -476,9 +491,8 @@ static int guc_ct_ctb_g2h_register(struct xe_guc_ct *ct)
>  	u32 desc_addr, ctb_addr, size;
>  	int err;
>  
> -	desc_addr = xe_bo_ggtt_addr(ct->bo) + CTB_DESC_SIZE;
> -	ctb_addr = xe_bo_ggtt_addr(ct->bo) + CTB_H2G_BUFFER_OFFSET +
> -		CTB_H2G_BUFFER_SIZE;
> +	desc_addr = xe_bo_ggtt_addr(ct->bo_g2h) + CTB_DESC_SIZE;
> +	ctb_addr = xe_bo_ggtt_addr(ct->bo_g2h) + CTB_G2H_BUFFER_OFFSET;
>  	size = ct->ctbs.g2h.info.size * sizeof(u32);
>  
>  	err = xe_guc_self_cfg64(guc,
> @@ -605,9 +619,12 @@ static int __xe_guc_ct_start(struct xe_guc_ct *ct, bool needs_register)
>  	xe_gt_assert(gt, !xe_guc_ct_enabled(ct));
>  
>  	if (needs_register) {
> -		xe_map_memset(xe, &ct->bo->vmap, 0, 0, xe_bo_size(ct->bo));
> -		guc_ct_ctb_h2g_init(xe, &ct->ctbs.h2g, &ct->bo->vmap);
> -		guc_ct_ctb_g2h_init(xe, &ct->ctbs.g2h, &ct->bo->vmap);
> +		xe_map_memset(xe, &ct->bo_h2g->vmap, 0, 0,
> +			      xe_bo_size(ct->bo_h2g));
> +		xe_map_memset(xe, &ct->bo_g2h->vmap, 0, 0,
> +			      xe_bo_size(ct->bo_g2h));
> +		guc_ct_ctb_h2g_init(xe, &ct->ctbs.h2g, &ct->bo_h2g->vmap);
> +		guc_ct_ctb_g2h_init(xe, &ct->ctbs.g2h, &ct->bo_g2h->vmap);
>  
>  		err = guc_ct_ctb_h2g_register(ct);
>  		if (err)
> @@ -624,7 +641,7 @@ static int __xe_guc_ct_start(struct xe_guc_ct *ct, bool needs_register)
>  		ct->ctbs.h2g.info.broken = false;
>  		ct->ctbs.g2h.info.broken = false;
>  		/* Skip everything in H2G buffer */
> -		xe_map_memset(xe, &ct->bo->vmap, CTB_H2G_BUFFER_OFFSET, 0,
> +		xe_map_memset(xe, &ct->bo_h2g->vmap, CTB_H2G_BUFFER_OFFSET, 0,
>  			      CTB_H2G_BUFFER_SIZE);
>  	}
>  
> @@ -1963,8 +1980,9 @@ static struct xe_guc_ct_snapshot *guc_ct_snapshot_alloc(struct xe_guc_ct *ct, bo
>  	if (!snapshot)
>  		return NULL;
>  
> -	if (ct->bo && want_ctb) {
> -		snapshot->ctb_size = xe_bo_size(ct->bo);
> +	if (ct->bo_h2g && ct->bo_g2h && want_ctb) {
> +		snapshot->ctb_size = xe_bo_size(ct->bo_h2g) +
> +			xe_bo_size(ct->bo_g2h);
>  		snapshot->ctb = kmalloc(snapshot->ctb_size, atomic ? GFP_ATOMIC : GFP_KERNEL);
>  	}
>  
> @@ -2012,8 +2030,12 @@ static struct xe_guc_ct_snapshot *guc_ct_snapshot_capture(struct xe_guc_ct *ct,
>  		guc_ctb_snapshot_capture(xe, &ct->ctbs.g2h, &snapshot->g2h);
>  	}
>  
> -	if (ct->bo && snapshot->ctb)
> -		xe_map_memcpy_from(xe, snapshot->ctb, &ct->bo->vmap, 0, snapshot->ctb_size);
> +	if (ct->bo_h2g && ct->bo_g2h && snapshot->ctb) {
> +		xe_map_memcpy_from(xe, snapshot->ctb, &ct->bo_h2g->vmap, 0,
> +				   xe_bo_size(ct->bo_h2g));
> +		xe_map_memcpy_from(xe, snapshot->ctb, &ct->bo_g2h->vmap,
> +				   xe_bo_size(ct->bo_h2g), xe_bo_size(ct->bo_g2h));

Logic bug...

xe_map_memcpy_from(xe, snapshot->ctb + xe_bo_size(ct->bo_h2g), &ct->bo_g2h->vmap, 0, xe_bo_size(ct->bo_g2h));

Ignore this rev and skipped CI.

Matt

> +	}
>  
>  	return snapshot;
>  }
> diff --git a/drivers/gpu/drm/xe/xe_guc_ct_types.h b/drivers/gpu/drm/xe/xe_guc_ct_types.h
> index 09d7ff1ef42a..385a607e4777 100644
> --- a/drivers/gpu/drm/xe/xe_guc_ct_types.h
> +++ b/drivers/gpu/drm/xe/xe_guc_ct_types.h
> @@ -126,8 +126,10 @@ struct xe_fast_req_fence {
>   * for the H2G and G2H requests sent and received through the buffers.
>   */
>  struct xe_guc_ct {
> -	/** @bo: Xe BO for CT */
> -	struct xe_bo *bo;
> +	/** @bo_h2g: Xe BO for H2G */
> +	struct xe_bo *bo_h2g;
> +	/** @bo_g2h: Xe BO for G2H */
> +	struct xe_bo *bo_g2h;
>  	/** @lock: protects everything in CT layer */
>  	struct mutex lock;
>  	/** @fast_lock: protects G2H channel and credits */
> -- 
> 2.34.1
> 

^ permalink raw reply	[flat|nested] 7+ messages in thread

* [PATCH 2/2] drm/xe: Remove H2G reads in CT send path in non-debug builds
  2026-02-13 20:50 [PATCH 0/2] GuC CT memory optimizations Matthew Brost
  2026-02-13 20:50 ` [PATCH 1/2] drm/xe: Split H2G and G2H into separate buffer objects Matthew Brost
@ 2026-02-13 20:50 ` Matthew Brost
  2026-02-13 20:57 ` ✓ CI.KUnit: success for GuC CT memory optimizations Patchwork
                   ` (2 subsequent siblings)
  4 siblings, 0 replies; 7+ messages in thread
From: Matthew Brost @ 2026-02-13 20:50 UTC (permalink / raw)
  To: intel-xe; +Cc: francois.dugast, daniele.ceraolospurio, michal.wajdeczko

A single VRAM read on BMG can take over 1µs. While small, this is a
non-trivial amount of time in a hot path. Remove the descriptor H2G read
(potentially a VRAM access) from non-debug builds, as this
error-checking code is not needed outside of debug configurations.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
 drivers/gpu/drm/xe/xe_guc_ct.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c b/drivers/gpu/drm/xe/xe_guc_ct.c
index 5d8d90a4f879..333a621825d3 100644
--- a/drivers/gpu/drm/xe/xe_guc_ct.c
+++ b/drivers/gpu/drm/xe/xe_guc_ct.c
@@ -939,22 +939,22 @@ static int h2g_write(struct xe_guc_ct *ct, const u32 *action, u32 len,
 	u32 full_len;
 	struct iosys_map map = IOSYS_MAP_INIT_OFFSET(&h2g->cmds,
 							 tail * sizeof(u32));
-	u32 desc_status;
 
 	full_len = len + GUC_CTB_HDR_LEN;
 
 	lockdep_assert_held(&ct->lock);
 	xe_gt_assert(gt, full_len <= GUC_CTB_MSG_MAX_LEN);
 
-	desc_status = desc_read(xe, h2g, status);
-	if (desc_status) {
-		xe_gt_err(gt, "CT write: non-zero status: %u\n", desc_status);
-		goto corrupted;
-	}
-
 	if (IS_ENABLED(CONFIG_DRM_XE_DEBUG)) {
 		u32 desc_tail = desc_read(xe, h2g, tail);
 		u32 desc_head = desc_read(xe, h2g, head);
+		u32 desc_status;
+
+		desc_status = desc_read(xe, h2g, status);
+		if (desc_status) {
+			xe_gt_err(gt, "CT write: non-zero status: %u\n", desc_status);
+			goto corrupted;
+		}
 
 		if (tail != desc_tail) {
 			desc_write(xe, h2g, status, desc_status | GUC_CTB_STATUS_MISMATCH);
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 7+ messages in thread

* ✓ CI.KUnit: success for GuC CT memory optimizations
  2026-02-13 20:50 [PATCH 0/2] GuC CT memory optimizations Matthew Brost
  2026-02-13 20:50 ` [PATCH 1/2] drm/xe: Split H2G and G2H into separate buffer objects Matthew Brost
  2026-02-13 20:50 ` [PATCH 2/2] drm/xe: Remove H2G reads in CT send path in non-debug builds Matthew Brost
@ 2026-02-13 20:57 ` Patchwork
  2026-02-13 21:53 ` ✓ Xe.CI.BAT: " Patchwork
  2026-02-14 20:14 ` ✗ Xe.CI.FULL: failure " Patchwork
  4 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2026-02-13 20:57 UTC (permalink / raw)
  To: Matthew Brost; +Cc: intel-xe

== Series Details ==

Series: GuC CT memory optimizations
URL   : https://patchwork.freedesktop.org/series/161603/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[20:55:53] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[20:55:57] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[20:56:30] Starting KUnit Kernel (1/1)...
[20:56:30] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[20:56:30] ================== guc_buf (11 subtests) ===================
[20:56:30] [PASSED] test_smallest
[20:56:30] [PASSED] test_largest
[20:56:30] [PASSED] test_granular
[20:56:30] [PASSED] test_unique
[20:56:30] [PASSED] test_overlap
[20:56:30] [PASSED] test_reusable
[20:56:30] [PASSED] test_too_big
[20:56:30] [PASSED] test_flush
[20:56:30] [PASSED] test_lookup
[20:56:30] [PASSED] test_data
[20:56:30] [PASSED] test_class
[20:56:30] ===================== [PASSED] guc_buf =====================
[20:56:30] =================== guc_dbm (7 subtests) ===================
[20:56:30] [PASSED] test_empty
[20:56:30] [PASSED] test_default
[20:56:30] ======================== test_size  ========================
[20:56:30] [PASSED] 4
[20:56:30] [PASSED] 8
[20:56:30] [PASSED] 32
[20:56:30] [PASSED] 256
[20:56:30] ==================== [PASSED] test_size ====================
[20:56:30] ======================= test_reuse  ========================
[20:56:30] [PASSED] 4
[20:56:30] [PASSED] 8
[20:56:30] [PASSED] 32
[20:56:30] [PASSED] 256
[20:56:30] =================== [PASSED] test_reuse ====================
[20:56:30] =================== test_range_overlap  ====================
[20:56:30] [PASSED] 4
[20:56:30] [PASSED] 8
[20:56:30] [PASSED] 32
[20:56:30] [PASSED] 256
[20:56:30] =============== [PASSED] test_range_overlap ================
[20:56:30] =================== test_range_compact  ====================
[20:56:30] [PASSED] 4
[20:56:30] [PASSED] 8
[20:56:30] [PASSED] 32
[20:56:30] [PASSED] 256
[20:56:30] =============== [PASSED] test_range_compact ================
[20:56:30] ==================== test_range_spare  =====================
[20:56:30] [PASSED] 4
[20:56:30] [PASSED] 8
[20:56:30] [PASSED] 32
[20:56:30] [PASSED] 256
[20:56:30] ================ [PASSED] test_range_spare =================
[20:56:30] ===================== [PASSED] guc_dbm =====================
[20:56:30] =================== guc_idm (6 subtests) ===================
[20:56:30] [PASSED] bad_init
[20:56:30] [PASSED] no_init
[20:56:30] [PASSED] init_fini
[20:56:30] [PASSED] check_used
[20:56:30] [PASSED] check_quota
[20:56:30] [PASSED] check_all
[20:56:30] ===================== [PASSED] guc_idm =====================
[20:56:30] ================== no_relay (3 subtests) ===================
[20:56:30] [PASSED] xe_drops_guc2pf_if_not_ready
[20:56:30] [PASSED] xe_drops_guc2vf_if_not_ready
[20:56:30] [PASSED] xe_rejects_send_if_not_ready
[20:56:30] ==================== [PASSED] no_relay =====================
[20:56:30] ================== pf_relay (14 subtests) ==================
[20:56:30] [PASSED] pf_rejects_guc2pf_too_short
[20:56:30] [PASSED] pf_rejects_guc2pf_too_long
[20:56:30] [PASSED] pf_rejects_guc2pf_no_payload
[20:56:30] [PASSED] pf_fails_no_payload
[20:56:30] [PASSED] pf_fails_bad_origin
[20:56:30] [PASSED] pf_fails_bad_type
[20:56:30] [PASSED] pf_txn_reports_error
[20:56:30] [PASSED] pf_txn_sends_pf2guc
[20:56:30] [PASSED] pf_sends_pf2guc
[20:56:30] [SKIPPED] pf_loopback_nop
[20:56:30] [SKIPPED] pf_loopback_echo
[20:56:30] [SKIPPED] pf_loopback_fail
[20:56:30] [SKIPPED] pf_loopback_busy
[20:56:30] [SKIPPED] pf_loopback_retry
[20:56:30] ==================== [PASSED] pf_relay =====================
[20:56:30] ================== vf_relay (3 subtests) ===================
[20:56:30] [PASSED] vf_rejects_guc2vf_too_short
[20:56:30] [PASSED] vf_rejects_guc2vf_too_long
[20:56:30] [PASSED] vf_rejects_guc2vf_no_payload
[20:56:30] ==================== [PASSED] vf_relay =====================
[20:56:30] ================ pf_gt_config (6 subtests) =================
[20:56:30] [PASSED] fair_contexts_1vf
[20:56:30] [PASSED] fair_doorbells_1vf
[20:56:30] [PASSED] fair_ggtt_1vf
[20:56:30] ====================== fair_contexts  ======================
[20:56:30] [PASSED] 1 VF
[20:56:30] [PASSED] 2 VFs
[20:56:30] [PASSED] 3 VFs
[20:56:30] [PASSED] 4 VFs
[20:56:30] [PASSED] 5 VFs
[20:56:30] [PASSED] 6 VFs
[20:56:30] [PASSED] 7 VFs
[20:56:30] [PASSED] 8 VFs
[20:56:30] [PASSED] 9 VFs
[20:56:30] [PASSED] 10 VFs
[20:56:30] [PASSED] 11 VFs
[20:56:30] [PASSED] 12 VFs
[20:56:30] [PASSED] 13 VFs
[20:56:30] [PASSED] 14 VFs
[20:56:30] [PASSED] 15 VFs
[20:56:30] [PASSED] 16 VFs
[20:56:30] [PASSED] 17 VFs
[20:56:30] [PASSED] 18 VFs
[20:56:30] [PASSED] 19 VFs
[20:56:30] [PASSED] 20 VFs
[20:56:30] [PASSED] 21 VFs
[20:56:30] [PASSED] 22 VFs
[20:56:30] [PASSED] 23 VFs
[20:56:30] [PASSED] 24 VFs
[20:56:30] [PASSED] 25 VFs
[20:56:30] [PASSED] 26 VFs
[20:56:30] [PASSED] 27 VFs
[20:56:30] [PASSED] 28 VFs
[20:56:30] [PASSED] 29 VFs
[20:56:30] [PASSED] 30 VFs
[20:56:30] [PASSED] 31 VFs
[20:56:30] [PASSED] 32 VFs
[20:56:30] [PASSED] 33 VFs
[20:56:30] [PASSED] 34 VFs
[20:56:30] [PASSED] 35 VFs
[20:56:30] [PASSED] 36 VFs
[20:56:30] [PASSED] 37 VFs
[20:56:30] [PASSED] 38 VFs
[20:56:30] [PASSED] 39 VFs
[20:56:30] [PASSED] 40 VFs
[20:56:30] [PASSED] 41 VFs
[20:56:30] [PASSED] 42 VFs
[20:56:30] [PASSED] 43 VFs
[20:56:30] [PASSED] 44 VFs
[20:56:30] [PASSED] 45 VFs
[20:56:30] [PASSED] 46 VFs
[20:56:30] [PASSED] 47 VFs
[20:56:30] [PASSED] 48 VFs
[20:56:30] [PASSED] 49 VFs
[20:56:30] [PASSED] 50 VFs
[20:56:30] [PASSED] 51 VFs
[20:56:30] [PASSED] 52 VFs
[20:56:30] [PASSED] 53 VFs
[20:56:30] [PASSED] 54 VFs
[20:56:30] [PASSED] 55 VFs
[20:56:30] [PASSED] 56 VFs
[20:56:30] [PASSED] 57 VFs
[20:56:30] [PASSED] 58 VFs
[20:56:30] [PASSED] 59 VFs
[20:56:30] [PASSED] 60 VFs
[20:56:30] [PASSED] 61 VFs
[20:56:30] [PASSED] 62 VFs
[20:56:30] [PASSED] 63 VFs
[20:56:30] ================== [PASSED] fair_contexts ==================
[20:56:30] ===================== fair_doorbells  ======================
[20:56:30] [PASSED] 1 VF
[20:56:30] [PASSED] 2 VFs
[20:56:30] [PASSED] 3 VFs
[20:56:30] [PASSED] 4 VFs
[20:56:30] [PASSED] 5 VFs
[20:56:30] [PASSED] 6 VFs
[20:56:30] [PASSED] 7 VFs
[20:56:30] [PASSED] 8 VFs
[20:56:30] [PASSED] 9 VFs
[20:56:30] [PASSED] 10 VFs
[20:56:30] [PASSED] 11 VFs
[20:56:30] [PASSED] 12 VFs
[20:56:30] [PASSED] 13 VFs
[20:56:30] [PASSED] 14 VFs
[20:56:30] [PASSED] 15 VFs
[20:56:30] [PASSED] 16 VFs
[20:56:30] [PASSED] 17 VFs
[20:56:30] [PASSED] 18 VFs
[20:56:30] [PASSED] 19 VFs
[20:56:30] [PASSED] 20 VFs
[20:56:30] [PASSED] 21 VFs
[20:56:30] [PASSED] 22 VFs
[20:56:30] [PASSED] 23 VFs
[20:56:30] [PASSED] 24 VFs
[20:56:30] [PASSED] 25 VFs
[20:56:30] [PASSED] 26 VFs
[20:56:30] [PASSED] 27 VFs
[20:56:30] [PASSED] 28 VFs
[20:56:30] [PASSED] 29 VFs
[20:56:30] [PASSED] 30 VFs
[20:56:30] [PASSED] 31 VFs
[20:56:30] [PASSED] 32 VFs
[20:56:30] [PASSED] 33 VFs
[20:56:30] [PASSED] 34 VFs
[20:56:30] [PASSED] 35 VFs
[20:56:30] [PASSED] 36 VFs
[20:56:30] [PASSED] 37 VFs
[20:56:30] [PASSED] 38 VFs
[20:56:30] [PASSED] 39 VFs
[20:56:30] [PASSED] 40 VFs
[20:56:30] [PASSED] 41 VFs
[20:56:30] [PASSED] 42 VFs
[20:56:30] [PASSED] 43 VFs
[20:56:30] [PASSED] 44 VFs
[20:56:30] [PASSED] 45 VFs
[20:56:30] [PASSED] 46 VFs
[20:56:30] [PASSED] 47 VFs
[20:56:30] [PASSED] 48 VFs
[20:56:30] [PASSED] 49 VFs
[20:56:30] [PASSED] 50 VFs
[20:56:30] [PASSED] 51 VFs
[20:56:30] [PASSED] 52 VFs
[20:56:30] [PASSED] 53 VFs
[20:56:30] [PASSED] 54 VFs
[20:56:30] [PASSED] 55 VFs
[20:56:30] [PASSED] 56 VFs
[20:56:30] [PASSED] 57 VFs
[20:56:30] [PASSED] 58 VFs
[20:56:30] [PASSED] 59 VFs
[20:56:30] [PASSED] 60 VFs
[20:56:30] [PASSED] 61 VFs
[20:56:30] [PASSED] 62 VFs
[20:56:30] [PASSED] 63 VFs
[20:56:30] ================= [PASSED] fair_doorbells ==================
[20:56:30] ======================== fair_ggtt  ========================
[20:56:30] [PASSED] 1 VF
[20:56:30] [PASSED] 2 VFs
[20:56:30] [PASSED] 3 VFs
[20:56:30] [PASSED] 4 VFs
[20:56:30] [PASSED] 5 VFs
[20:56:30] [PASSED] 6 VFs
[20:56:30] [PASSED] 7 VFs
[20:56:30] [PASSED] 8 VFs
[20:56:30] [PASSED] 9 VFs
[20:56:30] [PASSED] 10 VFs
[20:56:30] [PASSED] 11 VFs
[20:56:30] [PASSED] 12 VFs
[20:56:30] [PASSED] 13 VFs
[20:56:30] [PASSED] 14 VFs
[20:56:30] [PASSED] 15 VFs
[20:56:30] [PASSED] 16 VFs
[20:56:30] [PASSED] 17 VFs
[20:56:30] [PASSED] 18 VFs
[20:56:30] [PASSED] 19 VFs
[20:56:30] [PASSED] 20 VFs
[20:56:30] [PASSED] 21 VFs
[20:56:30] [PASSED] 22 VFs
[20:56:30] [PASSED] 23 VFs
[20:56:30] [PASSED] 24 VFs
[20:56:30] [PASSED] 25 VFs
[20:56:30] [PASSED] 26 VFs
[20:56:30] [PASSED] 27 VFs
[20:56:30] [PASSED] 28 VFs
[20:56:30] [PASSED] 29 VFs
[20:56:30] [PASSED] 30 VFs
[20:56:30] [PASSED] 31 VFs
[20:56:30] [PASSED] 32 VFs
[20:56:30] [PASSED] 33 VFs
[20:56:30] [PASSED] 34 VFs
[20:56:30] [PASSED] 35 VFs
[20:56:30] [PASSED] 36 VFs
[20:56:30] [PASSED] 37 VFs
[20:56:30] [PASSED] 38 VFs
[20:56:30] [PASSED] 39 VFs
[20:56:30] [PASSED] 40 VFs
[20:56:30] [PASSED] 41 VFs
[20:56:30] [PASSED] 42 VFs
[20:56:30] [PASSED] 43 VFs
[20:56:30] [PASSED] 44 VFs
[20:56:30] [PASSED] 45 VFs
[20:56:30] [PASSED] 46 VFs
[20:56:30] [PASSED] 47 VFs
[20:56:30] [PASSED] 48 VFs
[20:56:30] [PASSED] 49 VFs
[20:56:30] [PASSED] 50 VFs
[20:56:30] [PASSED] 51 VFs
[20:56:30] [PASSED] 52 VFs
[20:56:30] [PASSED] 53 VFs
[20:56:30] [PASSED] 54 VFs
[20:56:30] [PASSED] 55 VFs
[20:56:30] [PASSED] 56 VFs
[20:56:30] [PASSED] 57 VFs
[20:56:30] [PASSED] 58 VFs
[20:56:30] [PASSED] 59 VFs
[20:56:30] [PASSED] 60 VFs
[20:56:30] [PASSED] 61 VFs
[20:56:30] [PASSED] 62 VFs
[20:56:30] [PASSED] 63 VFs
[20:56:30] ==================== [PASSED] fair_ggtt ====================
[20:56:30] ================== [PASSED] pf_gt_config ===================
[20:56:30] ===================== lmtt (1 subtest) =====================
[20:56:30] ======================== test_ops  =========================
[20:56:30] [PASSED] 2-level
[20:56:30] [PASSED] multi-level
[20:56:30] ==================== [PASSED] test_ops =====================
[20:56:30] ====================== [PASSED] lmtt =======================
[20:56:30] ================= pf_service (11 subtests) =================
[20:56:30] [PASSED] pf_negotiate_any
[20:56:30] [PASSED] pf_negotiate_base_match
[20:56:30] [PASSED] pf_negotiate_base_newer
[20:56:30] [PASSED] pf_negotiate_base_next
[20:56:30] [SKIPPED] pf_negotiate_base_older
[20:56:30] [PASSED] pf_negotiate_base_prev
[20:56:30] [PASSED] pf_negotiate_latest_match
[20:56:30] [PASSED] pf_negotiate_latest_newer
[20:56:30] [PASSED] pf_negotiate_latest_next
[20:56:30] [SKIPPED] pf_negotiate_latest_older
[20:56:30] [SKIPPED] pf_negotiate_latest_prev
[20:56:30] =================== [PASSED] pf_service ====================
[20:56:30] ================= xe_guc_g2g (2 subtests) ==================
[20:56:30] ============== xe_live_guc_g2g_kunit_default  ==============
[20:56:30] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[20:56:30] ============== xe_live_guc_g2g_kunit_allmem  ===============
[20:56:30] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[20:56:30] =================== [SKIPPED] xe_guc_g2g ===================
[20:56:30] =================== xe_mocs (2 subtests) ===================
[20:56:30] ================ xe_live_mocs_kernel_kunit  ================
[20:56:30] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[20:56:30] ================ xe_live_mocs_reset_kunit  =================
[20:56:30] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[20:56:30] ==================== [SKIPPED] xe_mocs =====================
[20:56:30] ================= xe_migrate (2 subtests) ==================
[20:56:30] ================= xe_migrate_sanity_kunit  =================
[20:56:30] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[20:56:30] ================== xe_validate_ccs_kunit  ==================
[20:56:30] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[20:56:30] =================== [SKIPPED] xe_migrate ===================
[20:56:30] ================== xe_dma_buf (1 subtest) ==================
[20:56:30] ==================== xe_dma_buf_kunit  =====================
[20:56:30] ================ [SKIPPED] xe_dma_buf_kunit ================
[20:56:30] =================== [SKIPPED] xe_dma_buf ===================
[20:56:30] ================= xe_bo_shrink (1 subtest) =================
[20:56:30] =================== xe_bo_shrink_kunit  ====================
[20:56:30] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[20:56:30] ================== [SKIPPED] xe_bo_shrink ==================
[20:56:30] ==================== xe_bo (2 subtests) ====================
[20:56:30] ================== xe_ccs_migrate_kunit  ===================
[20:56:30] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[20:56:30] ==================== xe_bo_evict_kunit  ====================
[20:56:30] =============== [SKIPPED] xe_bo_evict_kunit ================
[20:56:30] ===================== [SKIPPED] xe_bo ======================
[20:56:30] ==================== args (13 subtests) ====================
[20:56:30] [PASSED] count_args_test
[20:56:30] [PASSED] call_args_example
[20:56:30] [PASSED] call_args_test
[20:56:30] [PASSED] drop_first_arg_example
[20:56:30] [PASSED] drop_first_arg_test
[20:56:30] [PASSED] first_arg_example
[20:56:30] [PASSED] first_arg_test
[20:56:30] [PASSED] last_arg_example
[20:56:30] [PASSED] last_arg_test
[20:56:30] [PASSED] pick_arg_example
[20:56:30] [PASSED] if_args_example
[20:56:30] [PASSED] if_args_test
[20:56:30] [PASSED] sep_comma_example
[20:56:30] ====================== [PASSED] args =======================
[20:56:30] =================== xe_pci (3 subtests) ====================
[20:56:30] ==================== check_graphics_ip  ====================
[20:56:30] [PASSED] 12.00 Xe_LP
[20:56:30] [PASSED] 12.10 Xe_LP+
[20:56:30] [PASSED] 12.55 Xe_HPG
[20:56:30] [PASSED] 12.60 Xe_HPC
[20:56:30] [PASSED] 12.70 Xe_LPG
[20:56:30] [PASSED] 12.71 Xe_LPG
[20:56:30] [PASSED] 12.74 Xe_LPG+
[20:56:30] [PASSED] 20.01 Xe2_HPG
[20:56:30] [PASSED] 20.02 Xe2_HPG
[20:56:30] [PASSED] 20.04 Xe2_LPG
[20:56:30] [PASSED] 30.00 Xe3_LPG
[20:56:30] [PASSED] 30.01 Xe3_LPG
[20:56:30] [PASSED] 30.03 Xe3_LPG
[20:56:30] [PASSED] 30.04 Xe3_LPG
[20:56:30] [PASSED] 30.05 Xe3_LPG
[20:56:30] [PASSED] 35.10 Xe3p_LPG
[20:56:30] [PASSED] 35.11 Xe3p_XPC
[20:56:30] ================ [PASSED] check_graphics_ip ================
[20:56:30] ===================== check_media_ip  ======================
[20:56:30] [PASSED] 12.00 Xe_M
[20:56:30] [PASSED] 12.55 Xe_HPM
[20:56:30] [PASSED] 13.00 Xe_LPM+
[20:56:30] [PASSED] 13.01 Xe2_HPM
[20:56:30] [PASSED] 20.00 Xe2_LPM
[20:56:30] [PASSED] 30.00 Xe3_LPM
[20:56:30] [PASSED] 30.02 Xe3_LPM
[20:56:30] [PASSED] 35.00 Xe3p_LPM
[20:56:30] [PASSED] 35.03 Xe3p_HPM
[20:56:30] ================= [PASSED] check_media_ip ==================
[20:56:30] =================== check_platform_desc  ===================
[20:56:30] [PASSED] 0x9A60 (TIGERLAKE)
[20:56:30] [PASSED] 0x9A68 (TIGERLAKE)
[20:56:30] [PASSED] 0x9A70 (TIGERLAKE)
[20:56:30] [PASSED] 0x9A40 (TIGERLAKE)
[20:56:30] [PASSED] 0x9A49 (TIGERLAKE)
[20:56:30] [PASSED] 0x9A59 (TIGERLAKE)
[20:56:30] [PASSED] 0x9A78 (TIGERLAKE)
[20:56:30] [PASSED] 0x9AC0 (TIGERLAKE)
[20:56:30] [PASSED] 0x9AC9 (TIGERLAKE)
[20:56:30] [PASSED] 0x9AD9 (TIGERLAKE)
[20:56:30] [PASSED] 0x9AF8 (TIGERLAKE)
[20:56:30] [PASSED] 0x4C80 (ROCKETLAKE)
[20:56:30] [PASSED] 0x4C8A (ROCKETLAKE)
[20:56:30] [PASSED] 0x4C8B (ROCKETLAKE)
[20:56:30] [PASSED] 0x4C8C (ROCKETLAKE)
[20:56:30] [PASSED] 0x4C90 (ROCKETLAKE)
[20:56:30] [PASSED] 0x4C9A (ROCKETLAKE)
[20:56:30] [PASSED] 0x4680 (ALDERLAKE_S)
[20:56:30] [PASSED] 0x4682 (ALDERLAKE_S)
[20:56:30] [PASSED] 0x4688 (ALDERLAKE_S)
[20:56:30] [PASSED] 0x468A (ALDERLAKE_S)
[20:56:30] [PASSED] 0x468B (ALDERLAKE_S)
[20:56:30] [PASSED] 0x4690 (ALDERLAKE_S)
[20:56:30] [PASSED] 0x4692 (ALDERLAKE_S)
[20:56:30] [PASSED] 0x4693 (ALDERLAKE_S)
[20:56:30] [PASSED] 0x46A0 (ALDERLAKE_P)
[20:56:30] [PASSED] 0x46A1 (ALDERLAKE_P)
[20:56:30] [PASSED] 0x46A2 (ALDERLAKE_P)
[20:56:30] [PASSED] 0x46A3 (ALDERLAKE_P)
[20:56:30] [PASSED] 0x46A6 (ALDERLAKE_P)
[20:56:30] [PASSED] 0x46A8 (ALDERLAKE_P)
[20:56:30] [PASSED] 0x46AA (ALDERLAKE_P)
[20:56:30] [PASSED] 0x462A (ALDERLAKE_P)
[20:56:30] [PASSED] 0x4626 (ALDERLAKE_P)
stty: 'standard input': Inappropriate ioctl for device
[20:56:30] [PASSED] 0x4628 (ALDERLAKE_P)
[20:56:30] [PASSED] 0x46B0 (ALDERLAKE_P)
[20:56:30] [PASSED] 0x46B1 (ALDERLAKE_P)
[20:56:30] [PASSED] 0x46B2 (ALDERLAKE_P)
[20:56:30] [PASSED] 0x46B3 (ALDERLAKE_P)
[20:56:30] [PASSED] 0x46C0 (ALDERLAKE_P)
[20:56:30] [PASSED] 0x46C1 (ALDERLAKE_P)
[20:56:30] [PASSED] 0x46C2 (ALDERLAKE_P)
[20:56:30] [PASSED] 0x46C3 (ALDERLAKE_P)
[20:56:30] [PASSED] 0x46D0 (ALDERLAKE_N)
[20:56:30] [PASSED] 0x46D1 (ALDERLAKE_N)
[20:56:30] [PASSED] 0x46D2 (ALDERLAKE_N)
[20:56:30] [PASSED] 0x46D3 (ALDERLAKE_N)
[20:56:30] [PASSED] 0x46D4 (ALDERLAKE_N)
[20:56:30] [PASSED] 0xA721 (ALDERLAKE_P)
[20:56:30] [PASSED] 0xA7A1 (ALDERLAKE_P)
[20:56:30] [PASSED] 0xA7A9 (ALDERLAKE_P)
[20:56:30] [PASSED] 0xA7AC (ALDERLAKE_P)
[20:56:30] [PASSED] 0xA7AD (ALDERLAKE_P)
[20:56:30] [PASSED] 0xA720 (ALDERLAKE_P)
[20:56:30] [PASSED] 0xA7A0 (ALDERLAKE_P)
[20:56:30] [PASSED] 0xA7A8 (ALDERLAKE_P)
[20:56:30] [PASSED] 0xA7AA (ALDERLAKE_P)
[20:56:30] [PASSED] 0xA7AB (ALDERLAKE_P)
[20:56:30] [PASSED] 0xA780 (ALDERLAKE_S)
[20:56:30] [PASSED] 0xA781 (ALDERLAKE_S)
[20:56:30] [PASSED] 0xA782 (ALDERLAKE_S)
[20:56:30] [PASSED] 0xA783 (ALDERLAKE_S)
[20:56:30] [PASSED] 0xA788 (ALDERLAKE_S)
[20:56:30] [PASSED] 0xA789 (ALDERLAKE_S)
[20:56:30] [PASSED] 0xA78A (ALDERLAKE_S)
[20:56:30] [PASSED] 0xA78B (ALDERLAKE_S)
[20:56:30] [PASSED] 0x4905 (DG1)
[20:56:30] [PASSED] 0x4906 (DG1)
[20:56:30] [PASSED] 0x4907 (DG1)
[20:56:30] [PASSED] 0x4908 (DG1)
[20:56:30] [PASSED] 0x4909 (DG1)
[20:56:30] [PASSED] 0x56C0 (DG2)
[20:56:30] [PASSED] 0x56C2 (DG2)
[20:56:30] [PASSED] 0x56C1 (DG2)
[20:56:30] [PASSED] 0x7D51 (METEORLAKE)
[20:56:30] [PASSED] 0x7DD1 (METEORLAKE)
[20:56:30] [PASSED] 0x7D41 (METEORLAKE)
[20:56:30] [PASSED] 0x7D67 (METEORLAKE)
[20:56:30] [PASSED] 0xB640 (METEORLAKE)
[20:56:30] [PASSED] 0x56A0 (DG2)
[20:56:30] [PASSED] 0x56A1 (DG2)
[20:56:30] [PASSED] 0x56A2 (DG2)
[20:56:30] [PASSED] 0x56BE (DG2)
[20:56:30] [PASSED] 0x56BF (DG2)
[20:56:30] [PASSED] 0x5690 (DG2)
[20:56:30] [PASSED] 0x5691 (DG2)
[20:56:30] [PASSED] 0x5692 (DG2)
[20:56:30] [PASSED] 0x56A5 (DG2)
[20:56:30] [PASSED] 0x56A6 (DG2)
[20:56:30] [PASSED] 0x56B0 (DG2)
[20:56:30] [PASSED] 0x56B1 (DG2)
[20:56:30] [PASSED] 0x56BA (DG2)
[20:56:30] [PASSED] 0x56BB (DG2)
[20:56:30] [PASSED] 0x56BC (DG2)
[20:56:30] [PASSED] 0x56BD (DG2)
[20:56:30] [PASSED] 0x5693 (DG2)
[20:56:30] [PASSED] 0x5694 (DG2)
[20:56:30] [PASSED] 0x5695 (DG2)
[20:56:30] [PASSED] 0x56A3 (DG2)
[20:56:30] [PASSED] 0x56A4 (DG2)
[20:56:30] [PASSED] 0x56B2 (DG2)
[20:56:30] [PASSED] 0x56B3 (DG2)
[20:56:30] [PASSED] 0x5696 (DG2)
[20:56:30] [PASSED] 0x5697 (DG2)
[20:56:30] [PASSED] 0xB69 (PVC)
[20:56:30] [PASSED] 0xB6E (PVC)
[20:56:30] [PASSED] 0xBD4 (PVC)
[20:56:30] [PASSED] 0xBD5 (PVC)
[20:56:30] [PASSED] 0xBD6 (PVC)
[20:56:30] [PASSED] 0xBD7 (PVC)
[20:56:30] [PASSED] 0xBD8 (PVC)
[20:56:30] [PASSED] 0xBD9 (PVC)
[20:56:30] [PASSED] 0xBDA (PVC)
[20:56:30] [PASSED] 0xBDB (PVC)
[20:56:30] [PASSED] 0xBE0 (PVC)
[20:56:30] [PASSED] 0xBE1 (PVC)
[20:56:30] [PASSED] 0xBE5 (PVC)
[20:56:30] [PASSED] 0x7D40 (METEORLAKE)
[20:56:30] [PASSED] 0x7D45 (METEORLAKE)
[20:56:30] [PASSED] 0x7D55 (METEORLAKE)
[20:56:30] [PASSED] 0x7D60 (METEORLAKE)
[20:56:30] [PASSED] 0x7DD5 (METEORLAKE)
[20:56:30] [PASSED] 0x6420 (LUNARLAKE)
[20:56:30] [PASSED] 0x64A0 (LUNARLAKE)
[20:56:30] [PASSED] 0x64B0 (LUNARLAKE)
[20:56:30] [PASSED] 0xE202 (BATTLEMAGE)
[20:56:30] [PASSED] 0xE209 (BATTLEMAGE)
[20:56:30] [PASSED] 0xE20B (BATTLEMAGE)
[20:56:30] [PASSED] 0xE20C (BATTLEMAGE)
[20:56:30] [PASSED] 0xE20D (BATTLEMAGE)
[20:56:30] [PASSED] 0xE210 (BATTLEMAGE)
[20:56:30] [PASSED] 0xE211 (BATTLEMAGE)
[20:56:30] [PASSED] 0xE212 (BATTLEMAGE)
[20:56:30] [PASSED] 0xE216 (BATTLEMAGE)
[20:56:30] [PASSED] 0xE220 (BATTLEMAGE)
[20:56:30] [PASSED] 0xE221 (BATTLEMAGE)
[20:56:30] [PASSED] 0xE222 (BATTLEMAGE)
[20:56:30] [PASSED] 0xE223 (BATTLEMAGE)
[20:56:30] [PASSED] 0xB080 (PANTHERLAKE)
[20:56:30] [PASSED] 0xB081 (PANTHERLAKE)
[20:56:30] [PASSED] 0xB082 (PANTHERLAKE)
[20:56:30] [PASSED] 0xB083 (PANTHERLAKE)
[20:56:30] [PASSED] 0xB084 (PANTHERLAKE)
[20:56:30] [PASSED] 0xB085 (PANTHERLAKE)
[20:56:30] [PASSED] 0xB086 (PANTHERLAKE)
[20:56:30] [PASSED] 0xB087 (PANTHERLAKE)
[20:56:30] [PASSED] 0xB08F (PANTHERLAKE)
[20:56:30] [PASSED] 0xB090 (PANTHERLAKE)
[20:56:30] [PASSED] 0xB0A0 (PANTHERLAKE)
[20:56:30] [PASSED] 0xB0B0 (PANTHERLAKE)
[20:56:30] [PASSED] 0xFD80 (PANTHERLAKE)
[20:56:30] [PASSED] 0xFD81 (PANTHERLAKE)
[20:56:30] [PASSED] 0xD740 (NOVALAKE_S)
[20:56:30] [PASSED] 0xD741 (NOVALAKE_S)
[20:56:30] [PASSED] 0xD742 (NOVALAKE_S)
[20:56:30] [PASSED] 0xD743 (NOVALAKE_S)
[20:56:30] [PASSED] 0xD744 (NOVALAKE_S)
[20:56:30] [PASSED] 0xD745 (NOVALAKE_S)
[20:56:30] [PASSED] 0x674C (CRESCENTISLAND)
[20:56:30] [PASSED] 0xD750 (NOVALAKE_P)
[20:56:30] [PASSED] 0xD751 (NOVALAKE_P)
[20:56:30] [PASSED] 0xD752 (NOVALAKE_P)
[20:56:30] [PASSED] 0xD753 (NOVALAKE_P)
[20:56:30] [PASSED] 0xD754 (NOVALAKE_P)
[20:56:30] [PASSED] 0xD755 (NOVALAKE_P)
[20:56:30] [PASSED] 0xD756 (NOVALAKE_P)
[20:56:30] [PASSED] 0xD757 (NOVALAKE_P)
[20:56:30] [PASSED] 0xD75F (NOVALAKE_P)
[20:56:30] =============== [PASSED] check_platform_desc ===============
[20:56:30] ===================== [PASSED] xe_pci ======================
[20:56:30] =================== xe_rtp (2 subtests) ====================
[20:56:30] =============== xe_rtp_process_to_sr_tests  ================
[20:56:30] [PASSED] coalesce-same-reg
[20:56:30] [PASSED] no-match-no-add
[20:56:30] [PASSED] match-or
[20:56:30] [PASSED] match-or-xfail
[20:56:30] [PASSED] no-match-no-add-multiple-rules
[20:56:30] [PASSED] two-regs-two-entries
[20:56:30] [PASSED] clr-one-set-other
[20:56:30] [PASSED] set-field
[20:56:30] [PASSED] conflict-duplicate
[20:56:30] [PASSED] conflict-not-disjoint
[20:56:30] [PASSED] conflict-reg-type
[20:56:30] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[20:56:30] ================== xe_rtp_process_tests  ===================
[20:56:30] [PASSED] active1
[20:56:30] [PASSED] active2
[20:56:30] [PASSED] active-inactive
[20:56:30] [PASSED] inactive-active
[20:56:30] [PASSED] inactive-1st_or_active-inactive
[20:56:30] [PASSED] inactive-2nd_or_active-inactive
[20:56:30] [PASSED] inactive-last_or_active-inactive
[20:56:30] [PASSED] inactive-no_or_active-inactive
[20:56:30] ============== [PASSED] xe_rtp_process_tests ===============
[20:56:30] ===================== [PASSED] xe_rtp ======================
[20:56:30] ==================== xe_wa (1 subtest) =====================
[20:56:30] ======================== xe_wa_gt  =========================
[20:56:30] [PASSED] TIGERLAKE B0
[20:56:30] [PASSED] DG1 A0
[20:56:30] [PASSED] DG1 B0
[20:56:30] [PASSED] ALDERLAKE_S A0
[20:56:30] [PASSED] ALDERLAKE_S B0
[20:56:30] [PASSED] ALDERLAKE_S C0
[20:56:30] [PASSED] ALDERLAKE_S D0
[20:56:30] [PASSED] ALDERLAKE_P A0
[20:56:30] [PASSED] ALDERLAKE_P B0
[20:56:30] [PASSED] ALDERLAKE_P C0
[20:56:30] [PASSED] ALDERLAKE_S RPLS D0
[20:56:30] [PASSED] ALDERLAKE_P RPLU E0
[20:56:30] [PASSED] DG2 G10 C0
[20:56:30] [PASSED] DG2 G11 B1
[20:56:30] [PASSED] DG2 G12 A1
[20:56:30] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[20:56:30] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[20:56:30] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[20:56:30] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[20:56:30] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[20:56:30] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[20:56:30] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[20:56:30] ==================== [PASSED] xe_wa_gt =====================
[20:56:30] ====================== [PASSED] xe_wa ======================
[20:56:30] ============================================================
[20:56:30] Testing complete. Ran 522 tests: passed: 504, skipped: 18
[20:56:30] Elapsed time: 37.291s total, 4.215s configuring, 32.559s building, 0.482s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[20:56:30] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[20:56:32] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[20:56:58] Starting KUnit Kernel (1/1)...
[20:56:58] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[20:56:58] ============ drm_test_pick_cmdline (2 subtests) ============
[20:56:58] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[20:56:58] =============== drm_test_pick_cmdline_named  ===============
[20:56:58] [PASSED] NTSC
[20:56:58] [PASSED] NTSC-J
[20:56:58] [PASSED] PAL
[20:56:58] [PASSED] PAL-M
[20:56:58] =========== [PASSED] drm_test_pick_cmdline_named ===========
[20:56:58] ============== [PASSED] drm_test_pick_cmdline ==============
[20:56:58] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[20:56:58] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[20:56:58] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[20:56:58] =========== drm_validate_clone_mode (2 subtests) ===========
[20:56:58] ============== drm_test_check_in_clone_mode  ===============
[20:56:58] [PASSED] in_clone_mode
[20:56:58] [PASSED] not_in_clone_mode
[20:56:58] ========== [PASSED] drm_test_check_in_clone_mode ===========
[20:56:58] =============== drm_test_check_valid_clones  ===============
[20:56:58] [PASSED] not_in_clone_mode
[20:56:58] [PASSED] valid_clone
[20:56:58] [PASSED] invalid_clone
[20:56:58] =========== [PASSED] drm_test_check_valid_clones ===========
[20:56:58] ============= [PASSED] drm_validate_clone_mode =============
[20:56:58] ============= drm_validate_modeset (1 subtest) =============
[20:56:58] [PASSED] drm_test_check_connector_changed_modeset
[20:56:58] ============== [PASSED] drm_validate_modeset ===============
[20:56:58] ====== drm_test_bridge_get_current_state (2 subtests) ======
[20:56:58] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[20:56:58] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[20:56:58] ======== [PASSED] drm_test_bridge_get_current_state ========
[20:56:58] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[20:56:58] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[20:56:58] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[20:56:58] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[20:56:58] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[20:56:58] ============== drm_bridge_alloc (2 subtests) ===============
[20:56:58] [PASSED] drm_test_drm_bridge_alloc_basic
[20:56:58] [PASSED] drm_test_drm_bridge_alloc_get_put
[20:56:58] ================ [PASSED] drm_bridge_alloc =================
[20:56:58] ============= drm_cmdline_parser (40 subtests) =============
[20:56:58] [PASSED] drm_test_cmdline_force_d_only
[20:56:58] [PASSED] drm_test_cmdline_force_D_only_dvi
[20:56:58] [PASSED] drm_test_cmdline_force_D_only_hdmi
[20:56:58] [PASSED] drm_test_cmdline_force_D_only_not_digital
[20:56:58] [PASSED] drm_test_cmdline_force_e_only
[20:56:58] [PASSED] drm_test_cmdline_res
[20:56:58] [PASSED] drm_test_cmdline_res_vesa
[20:56:58] [PASSED] drm_test_cmdline_res_vesa_rblank
[20:56:58] [PASSED] drm_test_cmdline_res_rblank
[20:56:58] [PASSED] drm_test_cmdline_res_bpp
[20:56:58] [PASSED] drm_test_cmdline_res_refresh
[20:56:58] [PASSED] drm_test_cmdline_res_bpp_refresh
[20:56:58] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[20:56:58] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[20:56:58] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[20:56:58] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[20:56:58] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[20:56:58] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[20:56:58] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[20:56:58] [PASSED] drm_test_cmdline_res_margins_force_on
[20:56:58] [PASSED] drm_test_cmdline_res_vesa_margins
[20:56:58] [PASSED] drm_test_cmdline_name
[20:56:58] [PASSED] drm_test_cmdline_name_bpp
[20:56:58] [PASSED] drm_test_cmdline_name_option
[20:56:58] [PASSED] drm_test_cmdline_name_bpp_option
[20:56:58] [PASSED] drm_test_cmdline_rotate_0
[20:56:58] [PASSED] drm_test_cmdline_rotate_90
[20:56:58] [PASSED] drm_test_cmdline_rotate_180
[20:56:58] [PASSED] drm_test_cmdline_rotate_270
[20:56:58] [PASSED] drm_test_cmdline_hmirror
[20:56:58] [PASSED] drm_test_cmdline_vmirror
[20:56:58] [PASSED] drm_test_cmdline_margin_options
[20:56:58] [PASSED] drm_test_cmdline_multiple_options
[20:56:58] [PASSED] drm_test_cmdline_bpp_extra_and_option
[20:56:58] [PASSED] drm_test_cmdline_extra_and_option
[20:56:58] [PASSED] drm_test_cmdline_freestanding_options
[20:56:58] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[20:56:58] [PASSED] drm_test_cmdline_panel_orientation
[20:56:58] ================ drm_test_cmdline_invalid  =================
[20:56:58] [PASSED] margin_only
[20:56:58] [PASSED] interlace_only
[20:56:58] [PASSED] res_missing_x
[20:56:58] [PASSED] res_missing_y
[20:56:58] [PASSED] res_bad_y
[20:56:58] [PASSED] res_missing_y_bpp
[20:56:58] [PASSED] res_bad_bpp
[20:56:58] [PASSED] res_bad_refresh
[20:56:58] [PASSED] res_bpp_refresh_force_on_off
[20:56:58] [PASSED] res_invalid_mode
[20:56:58] [PASSED] res_bpp_wrong_place_mode
[20:56:58] [PASSED] name_bpp_refresh
[20:56:58] [PASSED] name_refresh
[20:56:58] [PASSED] name_refresh_wrong_mode
[20:56:58] [PASSED] name_refresh_invalid_mode
[20:56:58] [PASSED] rotate_multiple
[20:56:58] [PASSED] rotate_invalid_val
[20:56:58] [PASSED] rotate_truncated
[20:56:58] [PASSED] invalid_option
[20:56:58] [PASSED] invalid_tv_option
[20:56:58] [PASSED] truncated_tv_option
[20:56:58] ============ [PASSED] drm_test_cmdline_invalid =============
[20:56:58] =============== drm_test_cmdline_tv_options  ===============
[20:56:58] [PASSED] NTSC
[20:56:58] [PASSED] NTSC_443
[20:56:58] [PASSED] NTSC_J
[20:56:58] [PASSED] PAL
[20:56:58] [PASSED] PAL_M
[20:56:58] [PASSED] PAL_N
[20:56:58] [PASSED] SECAM
[20:56:58] [PASSED] MONO_525
[20:56:58] [PASSED] MONO_625
[20:56:58] =========== [PASSED] drm_test_cmdline_tv_options ===========
[20:56:58] =============== [PASSED] drm_cmdline_parser ================
[20:56:58] ========== drmm_connector_hdmi_init (20 subtests) ==========
[20:56:58] [PASSED] drm_test_connector_hdmi_init_valid
[20:56:58] [PASSED] drm_test_connector_hdmi_init_bpc_8
[20:56:58] [PASSED] drm_test_connector_hdmi_init_bpc_10
[20:56:58] [PASSED] drm_test_connector_hdmi_init_bpc_12
[20:56:58] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[20:56:58] [PASSED] drm_test_connector_hdmi_init_bpc_null
[20:56:58] [PASSED] drm_test_connector_hdmi_init_formats_empty
[20:56:58] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[20:56:58] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[20:56:58] [PASSED] supported_formats=0x9 yuv420_allowed=1
[20:56:58] [PASSED] supported_formats=0x9 yuv420_allowed=0
[20:56:58] [PASSED] supported_formats=0x3 yuv420_allowed=1
[20:56:58] [PASSED] supported_formats=0x3 yuv420_allowed=0
[20:56:58] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[20:56:58] [PASSED] drm_test_connector_hdmi_init_null_ddc
[20:56:58] [PASSED] drm_test_connector_hdmi_init_null_product
[20:56:58] [PASSED] drm_test_connector_hdmi_init_null_vendor
[20:56:58] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[20:56:58] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[20:56:58] [PASSED] drm_test_connector_hdmi_init_product_valid
[20:56:58] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[20:56:58] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[20:56:58] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[20:56:58] ========= drm_test_connector_hdmi_init_type_valid  =========
[20:56:58] [PASSED] HDMI-A
[20:56:58] [PASSED] HDMI-B
[20:56:58] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[20:56:58] ======== drm_test_connector_hdmi_init_type_invalid  ========
[20:56:58] [PASSED] Unknown
[20:56:58] [PASSED] VGA
[20:56:58] [PASSED] DVI-I
[20:56:58] [PASSED] DVI-D
[20:56:58] [PASSED] DVI-A
[20:56:58] [PASSED] Composite
[20:56:58] [PASSED] SVIDEO
[20:56:58] [PASSED] LVDS
[20:56:58] [PASSED] Component
[20:56:58] [PASSED] DIN
[20:56:58] [PASSED] DP
[20:56:58] [PASSED] TV
[20:56:58] [PASSED] eDP
[20:56:58] [PASSED] Virtual
[20:56:58] [PASSED] DSI
[20:56:58] [PASSED] DPI
[20:56:58] [PASSED] Writeback
[20:56:58] [PASSED] SPI
[20:56:58] [PASSED] USB
[20:56:58] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[20:56:58] ============ [PASSED] drmm_connector_hdmi_init =============
[20:56:58] ============= drmm_connector_init (3 subtests) =============
[20:56:58] [PASSED] drm_test_drmm_connector_init
[20:56:58] [PASSED] drm_test_drmm_connector_init_null_ddc
[20:56:58] ========= drm_test_drmm_connector_init_type_valid  =========
[20:56:58] [PASSED] Unknown
[20:56:58] [PASSED] VGA
[20:56:58] [PASSED] DVI-I
[20:56:58] [PASSED] DVI-D
[20:56:58] [PASSED] DVI-A
[20:56:58] [PASSED] Composite
[20:56:58] [PASSED] SVIDEO
[20:56:58] [PASSED] LVDS
[20:56:58] [PASSED] Component
[20:56:58] [PASSED] DIN
[20:56:58] [PASSED] DP
[20:56:58] [PASSED] HDMI-A
[20:56:58] [PASSED] HDMI-B
[20:56:58] [PASSED] TV
[20:56:58] [PASSED] eDP
[20:56:58] [PASSED] Virtual
[20:56:58] [PASSED] DSI
[20:56:58] [PASSED] DPI
[20:56:58] [PASSED] Writeback
[20:56:58] [PASSED] SPI
[20:56:58] [PASSED] USB
[20:56:58] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[20:56:58] =============== [PASSED] drmm_connector_init ===============
[20:56:58] ========= drm_connector_dynamic_init (6 subtests) ==========
[20:56:58] [PASSED] drm_test_drm_connector_dynamic_init
[20:56:58] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[20:56:58] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[20:56:58] [PASSED] drm_test_drm_connector_dynamic_init_properties
[20:56:58] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[20:56:58] [PASSED] Unknown
[20:56:58] [PASSED] VGA
[20:56:58] [PASSED] DVI-I
[20:56:58] [PASSED] DVI-D
[20:56:58] [PASSED] DVI-A
[20:56:58] [PASSED] Composite
[20:56:58] [PASSED] SVIDEO
[20:56:58] [PASSED] LVDS
[20:56:58] [PASSED] Component
[20:56:58] [PASSED] DIN
[20:56:58] [PASSED] DP
[20:56:58] [PASSED] HDMI-A
[20:56:58] [PASSED] HDMI-B
[20:56:58] [PASSED] TV
[20:56:58] [PASSED] eDP
[20:56:58] [PASSED] Virtual
[20:56:58] [PASSED] DSI
[20:56:58] [PASSED] DPI
[20:56:58] [PASSED] Writeback
[20:56:58] [PASSED] SPI
[20:56:58] [PASSED] USB
[20:56:58] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[20:56:58] ======== drm_test_drm_connector_dynamic_init_name  =========
[20:56:58] [PASSED] Unknown
[20:56:58] [PASSED] VGA
[20:56:58] [PASSED] DVI-I
[20:56:58] [PASSED] DVI-D
[20:56:58] [PASSED] DVI-A
[20:56:58] [PASSED] Composite
[20:56:58] [PASSED] SVIDEO
[20:56:58] [PASSED] LVDS
[20:56:58] [PASSED] Component
[20:56:58] [PASSED] DIN
[20:56:58] [PASSED] DP
[20:56:58] [PASSED] HDMI-A
[20:56:58] [PASSED] HDMI-B
[20:56:58] [PASSED] TV
[20:56:58] [PASSED] eDP
[20:56:58] [PASSED] Virtual
[20:56:58] [PASSED] DSI
[20:56:58] [PASSED] DPI
[20:56:58] [PASSED] Writeback
[20:56:58] [PASSED] SPI
[20:56:58] [PASSED] USB
[20:56:58] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[20:56:58] =========== [PASSED] drm_connector_dynamic_init ============
[20:56:58] ==== drm_connector_dynamic_register_early (4 subtests) =====
[20:56:58] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[20:56:58] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[20:56:58] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[20:56:58] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[20:56:58] ====== [PASSED] drm_connector_dynamic_register_early =======
[20:56:58] ======= drm_connector_dynamic_register (7 subtests) ========
[20:56:58] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[20:56:58] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[20:56:58] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[20:56:58] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[20:56:58] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[20:56:58] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[20:56:58] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[20:56:58] ========= [PASSED] drm_connector_dynamic_register ==========
[20:56:58] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[20:56:58] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[20:56:58] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[20:56:58] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[20:56:58] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[20:56:58] ========== drm_test_get_tv_mode_from_name_valid  ===========
[20:56:58] [PASSED] NTSC
[20:56:58] [PASSED] NTSC-443
[20:56:58] [PASSED] NTSC-J
[20:56:58] [PASSED] PAL
[20:56:58] [PASSED] PAL-M
[20:56:58] [PASSED] PAL-N
[20:56:58] [PASSED] SECAM
[20:56:58] [PASSED] Mono
[20:56:58] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[20:56:58] [PASSED] drm_test_get_tv_mode_from_name_truncated
[20:56:58] ============ [PASSED] drm_get_tv_mode_from_name ============
[20:56:58] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[20:56:58] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[20:56:58] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[20:56:58] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[20:56:58] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[20:56:58] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[20:56:58] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[20:56:58] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[20:56:58] [PASSED] VIC 96
[20:56:58] [PASSED] VIC 97
[20:56:58] [PASSED] VIC 101
[20:56:58] [PASSED] VIC 102
[20:56:58] [PASSED] VIC 106
[20:56:58] [PASSED] VIC 107
[20:56:58] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[20:56:58] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[20:56:58] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[20:56:58] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[20:56:58] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[20:56:58] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[20:56:58] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[20:56:58] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[20:56:58] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[20:56:58] [PASSED] Automatic
[20:56:58] [PASSED] Full
[20:56:58] [PASSED] Limited 16:235
[20:56:58] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[20:56:58] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[20:56:58] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[20:56:58] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[20:56:58] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[20:56:58] [PASSED] RGB
[20:56:58] [PASSED] YUV 4:2:0
[20:56:58] [PASSED] YUV 4:2:2
[20:56:58] [PASSED] YUV 4:4:4
[20:56:58] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[20:56:58] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[20:56:58] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[20:56:58] ============= drm_damage_helper (21 subtests) ==============
[20:56:58] [PASSED] drm_test_damage_iter_no_damage
[20:56:58] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[20:56:58] [PASSED] drm_test_damage_iter_no_damage_src_moved
[20:56:58] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[20:56:58] [PASSED] drm_test_damage_iter_no_damage_not_visible
[20:56:58] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[20:56:58] [PASSED] drm_test_damage_iter_no_damage_no_fb
[20:56:58] [PASSED] drm_test_damage_iter_simple_damage
[20:56:58] [PASSED] drm_test_damage_iter_single_damage
[20:56:58] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[20:56:58] [PASSED] drm_test_damage_iter_single_damage_outside_src
[20:56:58] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[20:56:58] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[20:56:58] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[20:56:58] [PASSED] drm_test_damage_iter_single_damage_src_moved
[20:56:58] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[20:56:58] [PASSED] drm_test_damage_iter_damage
[20:56:58] [PASSED] drm_test_damage_iter_damage_one_intersect
[20:56:58] [PASSED] drm_test_damage_iter_damage_one_outside
[20:56:58] [PASSED] drm_test_damage_iter_damage_src_moved
[20:56:58] [PASSED] drm_test_damage_iter_damage_not_visible
[20:56:58] ================ [PASSED] drm_damage_helper ================
[20:56:58] ============== drm_dp_mst_helper (3 subtests) ==============
[20:56:58] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[20:56:58] [PASSED] Clock 154000 BPP 30 DSC disabled
[20:56:58] [PASSED] Clock 234000 BPP 30 DSC disabled
[20:56:58] [PASSED] Clock 297000 BPP 24 DSC disabled
[20:56:58] [PASSED] Clock 332880 BPP 24 DSC enabled
[20:56:58] [PASSED] Clock 324540 BPP 24 DSC enabled
[20:56:58] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[20:56:58] ============== drm_test_dp_mst_calc_pbn_div  ===============
[20:56:58] [PASSED] Link rate 2000000 lane count 4
[20:56:58] [PASSED] Link rate 2000000 lane count 2
[20:56:58] [PASSED] Link rate 2000000 lane count 1
[20:56:58] [PASSED] Link rate 1350000 lane count 4
[20:56:58] [PASSED] Link rate 1350000 lane count 2
[20:56:58] [PASSED] Link rate 1350000 lane count 1
[20:56:58] [PASSED] Link rate 1000000 lane count 4
[20:56:58] [PASSED] Link rate 1000000 lane count 2
[20:56:58] [PASSED] Link rate 1000000 lane count 1
[20:56:58] [PASSED] Link rate 810000 lane count 4
[20:56:58] [PASSED] Link rate 810000 lane count 2
[20:56:58] [PASSED] Link rate 810000 lane count 1
[20:56:58] [PASSED] Link rate 540000 lane count 4
[20:56:58] [PASSED] Link rate 540000 lane count 2
[20:56:58] [PASSED] Link rate 540000 lane count 1
[20:56:58] [PASSED] Link rate 270000 lane count 4
[20:56:58] [PASSED] Link rate 270000 lane count 2
[20:56:58] [PASSED] Link rate 270000 lane count 1
[20:56:58] [PASSED] Link rate 162000 lane count 4
[20:56:58] [PASSED] Link rate 162000 lane count 2
[20:56:58] [PASSED] Link rate 162000 lane count 1
[20:56:58] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[20:56:58] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[20:56:58] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[20:56:58] [PASSED] DP_POWER_UP_PHY with port number
[20:56:58] [PASSED] DP_POWER_DOWN_PHY with port number
[20:56:58] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[20:56:58] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[20:56:58] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[20:56:58] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[20:56:58] [PASSED] DP_QUERY_PAYLOAD with port number
[20:56:58] [PASSED] DP_QUERY_PAYLOAD with VCPI
[20:56:58] [PASSED] DP_REMOTE_DPCD_READ with port number
[20:56:58] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[20:56:58] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[20:56:58] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[20:56:58] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[20:56:58] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[20:56:58] [PASSED] DP_REMOTE_I2C_READ with port number
[20:56:58] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[20:56:58] [PASSED] DP_REMOTE_I2C_READ with transactions array
[20:56:58] [PASSED] DP_REMOTE_I2C_WRITE with port number
[20:56:58] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[20:56:58] [PASSED] DP_REMOTE_I2C_WRITE with data array
[20:56:58] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[20:56:58] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[20:56:58] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[20:56:58] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[20:56:58] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[20:56:58] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[20:56:58] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[20:56:58] ================ [PASSED] drm_dp_mst_helper ================
[20:56:58] ================== drm_exec (7 subtests) ===================
[20:56:58] [PASSED] sanitycheck
[20:56:58] [PASSED] test_lock
[20:56:58] [PASSED] test_lock_unlock
[20:56:58] [PASSED] test_duplicates
[20:56:58] [PASSED] test_prepare
[20:56:58] [PASSED] test_prepare_array
[20:56:58] [PASSED] test_multiple_loops
[20:56:58] ==================== [PASSED] drm_exec =====================
[20:56:58] =========== drm_format_helper_test (17 subtests) ===========
[20:56:58] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[20:56:58] [PASSED] single_pixel_source_buffer
[20:56:58] [PASSED] single_pixel_clip_rectangle
[20:56:58] [PASSED] well_known_colors
[20:56:58] [PASSED] destination_pitch
[20:56:58] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[20:56:58] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[20:56:58] [PASSED] single_pixel_source_buffer
[20:56:58] [PASSED] single_pixel_clip_rectangle
[20:56:58] [PASSED] well_known_colors
[20:56:58] [PASSED] destination_pitch
[20:56:58] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[20:56:58] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[20:56:58] [PASSED] single_pixel_source_buffer
[20:56:58] [PASSED] single_pixel_clip_rectangle
[20:56:58] [PASSED] well_known_colors
[20:56:58] [PASSED] destination_pitch
[20:56:58] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[20:56:58] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[20:56:58] [PASSED] single_pixel_source_buffer
[20:56:58] [PASSED] single_pixel_clip_rectangle
[20:56:58] [PASSED] well_known_colors
[20:56:58] [PASSED] destination_pitch
[20:56:58] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[20:56:58] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[20:56:58] [PASSED] single_pixel_source_buffer
[20:56:58] [PASSED] single_pixel_clip_rectangle
[20:56:58] [PASSED] well_known_colors
[20:56:58] [PASSED] destination_pitch
[20:56:58] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[20:56:58] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[20:56:58] [PASSED] single_pixel_source_buffer
[20:56:58] [PASSED] single_pixel_clip_rectangle
[20:56:58] [PASSED] well_known_colors
[20:56:58] [PASSED] destination_pitch
[20:56:58] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[20:56:58] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[20:56:58] [PASSED] single_pixel_source_buffer
[20:56:58] [PASSED] single_pixel_clip_rectangle
[20:56:58] [PASSED] well_known_colors
[20:56:58] [PASSED] destination_pitch
[20:56:58] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[20:56:58] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[20:56:58] [PASSED] single_pixel_source_buffer
[20:56:58] [PASSED] single_pixel_clip_rectangle
[20:56:58] [PASSED] well_known_colors
[20:56:58] [PASSED] destination_pitch
[20:56:58] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[20:56:58] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[20:56:58] [PASSED] single_pixel_source_buffer
[20:56:58] [PASSED] single_pixel_clip_rectangle
[20:56:58] [PASSED] well_known_colors
[20:56:58] [PASSED] destination_pitch
[20:56:58] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[20:56:58] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[20:56:58] [PASSED] single_pixel_source_buffer
[20:56:58] [PASSED] single_pixel_clip_rectangle
[20:56:58] [PASSED] well_known_colors
[20:56:58] [PASSED] destination_pitch
[20:56:58] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[20:56:58] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[20:56:58] [PASSED] single_pixel_source_buffer
[20:56:58] [PASSED] single_pixel_clip_rectangle
[20:56:58] [PASSED] well_known_colors
[20:56:58] [PASSED] destination_pitch
[20:56:58] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[20:56:58] ============== drm_test_fb_xrgb8888_to_mono  ===============
[20:56:58] [PASSED] single_pixel_source_buffer
[20:56:58] [PASSED] single_pixel_clip_rectangle
[20:56:58] [PASSED] well_known_colors
[20:56:58] [PASSED] destination_pitch
[20:56:58] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[20:56:58] ==================== drm_test_fb_swab  =====================
[20:56:58] [PASSED] single_pixel_source_buffer
[20:56:58] [PASSED] single_pixel_clip_rectangle
[20:56:58] [PASSED] well_known_colors
[20:56:58] [PASSED] destination_pitch
[20:56:58] ================ [PASSED] drm_test_fb_swab =================
[20:56:58] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[20:56:58] [PASSED] single_pixel_source_buffer
[20:56:58] [PASSED] single_pixel_clip_rectangle
[20:56:58] [PASSED] well_known_colors
[20:56:58] [PASSED] destination_pitch
[20:56:58] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[20:56:58] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[20:56:58] [PASSED] single_pixel_source_buffer
[20:56:58] [PASSED] single_pixel_clip_rectangle
[20:56:58] [PASSED] well_known_colors
[20:56:58] [PASSED] destination_pitch
[20:56:58] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[20:56:58] ================= drm_test_fb_clip_offset  =================
[20:56:58] [PASSED] pass through
[20:56:58] [PASSED] horizontal offset
[20:56:58] [PASSED] vertical offset
[20:56:58] [PASSED] horizontal and vertical offset
[20:56:58] [PASSED] horizontal offset (custom pitch)
[20:56:58] [PASSED] vertical offset (custom pitch)
[20:56:58] [PASSED] horizontal and vertical offset (custom pitch)
[20:56:58] ============= [PASSED] drm_test_fb_clip_offset =============
[20:56:58] =================== drm_test_fb_memcpy  ====================
[20:56:58] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[20:56:58] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[20:56:58] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[20:56:58] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[20:56:58] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[20:56:58] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[20:56:58] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[20:56:58] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[20:56:58] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[20:56:58] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[20:56:58] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[20:56:58] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[20:56:58] =============== [PASSED] drm_test_fb_memcpy ================
[20:56:58] ============= [PASSED] drm_format_helper_test ==============
[20:56:58] ================= drm_format (18 subtests) =================
[20:56:58] [PASSED] drm_test_format_block_width_invalid
[20:56:58] [PASSED] drm_test_format_block_width_one_plane
[20:56:58] [PASSED] drm_test_format_block_width_two_plane
[20:56:58] [PASSED] drm_test_format_block_width_three_plane
[20:56:58] [PASSED] drm_test_format_block_width_tiled
[20:56:58] [PASSED] drm_test_format_block_height_invalid
[20:56:58] [PASSED] drm_test_format_block_height_one_plane
[20:56:58] [PASSED] drm_test_format_block_height_two_plane
[20:56:58] [PASSED] drm_test_format_block_height_three_plane
[20:56:58] [PASSED] drm_test_format_block_height_tiled
[20:56:58] [PASSED] drm_test_format_min_pitch_invalid
[20:56:58] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[20:56:58] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[20:56:58] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[20:56:58] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[20:56:58] [PASSED] drm_test_format_min_pitch_two_plane
[20:56:58] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[20:56:58] [PASSED] drm_test_format_min_pitch_tiled
[20:56:58] =================== [PASSED] drm_format ====================
[20:56:58] ============== drm_framebuffer (10 subtests) ===============
[20:56:58] ========== drm_test_framebuffer_check_src_coords  ==========
[20:56:58] [PASSED] Success: source fits into fb
[20:56:58] [PASSED] Fail: overflowing fb with x-axis coordinate
[20:56:58] [PASSED] Fail: overflowing fb with y-axis coordinate
[20:56:58] [PASSED] Fail: overflowing fb with source width
[20:56:58] [PASSED] Fail: overflowing fb with source height
[20:56:58] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[20:56:58] [PASSED] drm_test_framebuffer_cleanup
[20:56:58] =============== drm_test_framebuffer_create  ===============
[20:56:58] [PASSED] ABGR8888 normal sizes
[20:56:58] [PASSED] ABGR8888 max sizes
[20:56:58] [PASSED] ABGR8888 pitch greater than min required
[20:56:58] [PASSED] ABGR8888 pitch less than min required
[20:56:58] [PASSED] ABGR8888 Invalid width
[20:56:58] [PASSED] ABGR8888 Invalid buffer handle
[20:56:58] [PASSED] No pixel format
[20:56:58] [PASSED] ABGR8888 Width 0
[20:56:58] [PASSED] ABGR8888 Height 0
[20:56:58] [PASSED] ABGR8888 Out of bound height * pitch combination
[20:56:58] [PASSED] ABGR8888 Large buffer offset
[20:56:58] [PASSED] ABGR8888 Buffer offset for inexistent plane
[20:56:58] [PASSED] ABGR8888 Invalid flag
[20:56:58] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[20:56:58] [PASSED] ABGR8888 Valid buffer modifier
[20:56:58] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[20:56:58] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[20:56:58] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[20:56:58] [PASSED] NV12 Normal sizes
[20:56:58] [PASSED] NV12 Max sizes
[20:56:58] [PASSED] NV12 Invalid pitch
[20:56:58] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[20:56:58] [PASSED] NV12 different  modifier per-plane
[20:56:58] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[20:56:58] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[20:56:58] [PASSED] NV12 Modifier for inexistent plane
[20:56:58] [PASSED] NV12 Handle for inexistent plane
[20:56:58] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[20:56:58] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[20:56:58] [PASSED] YVU420 Normal sizes
[20:56:58] [PASSED] YVU420 Max sizes
[20:56:58] [PASSED] YVU420 Invalid pitch
[20:56:58] [PASSED] YVU420 Different pitches
[20:56:58] [PASSED] YVU420 Different buffer offsets/pitches
[20:56:58] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[20:56:58] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[20:56:58] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[20:56:58] [PASSED] YVU420 Valid modifier
[20:56:58] [PASSED] YVU420 Different modifiers per plane
[20:56:58] [PASSED] YVU420 Modifier for inexistent plane
[20:56:58] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[20:56:58] [PASSED] X0L2 Normal sizes
[20:56:58] [PASSED] X0L2 Max sizes
[20:56:58] [PASSED] X0L2 Invalid pitch
[20:56:58] [PASSED] X0L2 Pitch greater than minimum required
[20:56:58] [PASSED] X0L2 Handle for inexistent plane
[20:56:58] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[20:56:58] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[20:56:58] [PASSED] X0L2 Valid modifier
[20:56:58] [PASSED] X0L2 Modifier for inexistent plane
[20:56:58] =========== [PASSED] drm_test_framebuffer_create ===========
[20:56:58] [PASSED] drm_test_framebuffer_free
[20:56:58] [PASSED] drm_test_framebuffer_init
[20:56:58] [PASSED] drm_test_framebuffer_init_bad_format
[20:56:58] [PASSED] drm_test_framebuffer_init_dev_mismatch
[20:56:58] [PASSED] drm_test_framebuffer_lookup
[20:56:58] [PASSED] drm_test_framebuffer_lookup_inexistent
[20:56:58] [PASSED] drm_test_framebuffer_modifiers_not_supported
[20:56:58] ================= [PASSED] drm_framebuffer =================
[20:56:58] ================ drm_gem_shmem (8 subtests) ================
[20:56:58] [PASSED] drm_gem_shmem_test_obj_create
[20:56:58] [PASSED] drm_gem_shmem_test_obj_create_private
[20:56:58] [PASSED] drm_gem_shmem_test_pin_pages
[20:56:58] [PASSED] drm_gem_shmem_test_vmap
[20:56:58] [PASSED] drm_gem_shmem_test_get_sg_table
[20:56:58] [PASSED] drm_gem_shmem_test_get_pages_sgt
[20:56:58] [PASSED] drm_gem_shmem_test_madvise
[20:56:58] [PASSED] drm_gem_shmem_test_purge
[20:56:58] ================== [PASSED] drm_gem_shmem ==================
[20:56:58] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[20:56:58] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[20:56:58] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[20:56:58] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[20:56:58] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[20:56:58] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[20:56:58] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[20:56:58] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[20:56:58] [PASSED] Automatic
[20:56:58] [PASSED] Full
[20:56:58] [PASSED] Limited 16:235
[20:56:58] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[20:56:58] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[20:56:58] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[20:56:58] [PASSED] drm_test_check_disable_connector
[20:56:58] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[20:56:58] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[20:56:58] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[20:56:58] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[20:56:58] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[20:56:58] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[20:56:58] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[20:56:58] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[20:56:58] [PASSED] drm_test_check_output_bpc_dvi
[20:56:58] [PASSED] drm_test_check_output_bpc_format_vic_1
[20:56:58] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[20:56:58] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[20:56:58] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[20:56:58] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[20:56:58] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[20:56:58] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[20:56:58] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[20:56:58] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[20:56:58] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[20:56:58] [PASSED] drm_test_check_broadcast_rgb_value
[20:56:58] [PASSED] drm_test_check_bpc_8_value
[20:56:58] [PASSED] drm_test_check_bpc_10_value
[20:56:58] [PASSED] drm_test_check_bpc_12_value
[20:56:58] [PASSED] drm_test_check_format_value
[20:56:58] [PASSED] drm_test_check_tmds_char_value
[20:56:58] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[20:56:58] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[20:56:58] [PASSED] drm_test_check_mode_valid
[20:56:58] [PASSED] drm_test_check_mode_valid_reject
[20:56:58] [PASSED] drm_test_check_mode_valid_reject_rate
[20:56:58] [PASSED] drm_test_check_mode_valid_reject_max_clock
[20:56:58] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[20:56:58] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[20:56:58] [PASSED] drm_test_check_infoframes
[20:56:58] [PASSED] drm_test_check_reject_avi_infoframe
[20:56:58] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[20:56:58] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[20:56:58] [PASSED] drm_test_check_reject_audio_infoframe
[20:56:58] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[20:56:58] ================= drm_managed (2 subtests) =================
[20:56:58] [PASSED] drm_test_managed_release_action
[20:56:58] [PASSED] drm_test_managed_run_action
[20:56:58] =================== [PASSED] drm_managed ===================
[20:56:58] =================== drm_mm (6 subtests) ====================
[20:56:58] [PASSED] drm_test_mm_init
[20:56:58] [PASSED] drm_test_mm_debug
[20:56:58] [PASSED] drm_test_mm_align32
[20:56:58] [PASSED] drm_test_mm_align64
[20:56:58] [PASSED] drm_test_mm_lowest
[20:56:58] [PASSED] drm_test_mm_highest
[20:56:58] ===================== [PASSED] drm_mm ======================
[20:56:58] ============= drm_modes_analog_tv (5 subtests) =============
[20:56:58] [PASSED] drm_test_modes_analog_tv_mono_576i
[20:56:58] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[20:56:58] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[20:56:58] [PASSED] drm_test_modes_analog_tv_pal_576i
[20:56:58] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[20:56:58] =============== [PASSED] drm_modes_analog_tv ===============
[20:56:58] ============== drm_plane_helper (2 subtests) ===============
[20:56:58] =============== drm_test_check_plane_state  ================
[20:56:58] [PASSED] clipping_simple
[20:56:58] [PASSED] clipping_rotate_reflect
[20:56:58] [PASSED] positioning_simple
[20:56:58] [PASSED] upscaling
[20:56:58] [PASSED] downscaling
[20:56:58] [PASSED] rounding1
[20:56:58] [PASSED] rounding2
[20:56:58] [PASSED] rounding3
[20:56:58] [PASSED] rounding4
[20:56:58] =========== [PASSED] drm_test_check_plane_state ============
[20:56:58] =========== drm_test_check_invalid_plane_state  ============
[20:56:58] [PASSED] positioning_invalid
[20:56:58] [PASSED] upscaling_invalid
[20:56:58] [PASSED] downscaling_invalid
[20:56:58] ======= [PASSED] drm_test_check_invalid_plane_state ========
[20:56:58] ================ [PASSED] drm_plane_helper =================
[20:56:58] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[20:56:58] ====== drm_test_connector_helper_tv_get_modes_check  =======
[20:56:58] [PASSED] None
[20:56:58] [PASSED] PAL
[20:56:58] [PASSED] NTSC
[20:56:58] [PASSED] Both, NTSC Default
[20:56:58] [PASSED] Both, PAL Default
[20:56:58] [PASSED] Both, NTSC Default, with PAL on command-line
[20:56:58] [PASSED] Both, PAL Default, with NTSC on command-line
[20:56:58] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[20:56:58] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[20:56:58] ================== drm_rect (9 subtests) ===================
[20:56:58] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[20:56:58] [PASSED] drm_test_rect_clip_scaled_not_clipped
[20:56:58] [PASSED] drm_test_rect_clip_scaled_clipped
[20:56:58] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[20:56:58] ================= drm_test_rect_intersect  =================
[20:56:58] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[20:56:58] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[20:56:58] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[20:56:58] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[20:56:58] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[20:56:58] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[20:56:58] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[20:56:58] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[20:56:58] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[20:56:58] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[20:56:58] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[20:56:58] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[20:56:58] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[20:56:58] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[20:56:58] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[20:56:58] ============= [PASSED] drm_test_rect_intersect =============
[20:56:58] ================ drm_test_rect_calc_hscale  ================
[20:56:58] [PASSED] normal use
[20:56:58] [PASSED] out of max range
[20:56:58] [PASSED] out of min range
[20:56:58] [PASSED] zero dst
[20:56:58] [PASSED] negative src
[20:56:58] [PASSED] negative dst
[20:56:58] ============ [PASSED] drm_test_rect_calc_hscale ============
[20:56:58] ================ drm_test_rect_calc_vscale  ================
[20:56:58] [PASSED] normal use
[20:56:58] [PASSED] out of max range
[20:56:58] [PASSED] out of min range
[20:56:58] [PASSED] zero dst
[20:56:58] [PASSED] negative src
[20:56:58] [PASSED] negative dst
stty: 'standard input': Inappropriate ioctl for device
[20:56:58] ============ [PASSED] drm_test_rect_calc_vscale ============
[20:56:58] ================== drm_test_rect_rotate  ===================
[20:56:58] [PASSED] reflect-x
[20:56:58] [PASSED] reflect-y
[20:56:58] [PASSED] rotate-0
[20:56:58] [PASSED] rotate-90
[20:56:58] [PASSED] rotate-180
[20:56:58] [PASSED] rotate-270
[20:56:58] ============== [PASSED] drm_test_rect_rotate ===============
[20:56:58] ================ drm_test_rect_rotate_inv  =================
[20:56:58] [PASSED] reflect-x
[20:56:58] [PASSED] reflect-y
[20:56:58] [PASSED] rotate-0
[20:56:58] [PASSED] rotate-90
[20:56:58] [PASSED] rotate-180
[20:56:58] [PASSED] rotate-270
[20:56:58] ============ [PASSED] drm_test_rect_rotate_inv =============
[20:56:58] ==================== [PASSED] drm_rect =====================
[20:56:58] ============ drm_sysfb_modeset_test (1 subtest) ============
[20:56:58] ============ drm_test_sysfb_build_fourcc_list  =============
[20:56:58] [PASSED] no native formats
[20:56:58] [PASSED] XRGB8888 as native format
[20:56:58] [PASSED] remove duplicates
[20:56:58] [PASSED] convert alpha formats
[20:56:58] [PASSED] random formats
[20:56:58] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[20:56:58] ============= [PASSED] drm_sysfb_modeset_test ==============
[20:56:58] ================== drm_fixp (2 subtests) ===================
[20:56:58] [PASSED] drm_test_int2fixp
[20:56:58] [PASSED] drm_test_sm2fixp
[20:56:58] ==================== [PASSED] drm_fixp =====================
[20:56:58] ============================================================
[20:56:58] Testing complete. Ran 621 tests: passed: 621
[20:56:58] Elapsed time: 27.916s total, 1.689s configuring, 26.056s building, 0.137s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[20:56:58] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[20:57:00] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[20:57:10] Starting KUnit Kernel (1/1)...
[20:57:10] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[20:57:10] ================= ttm_device (5 subtests) ==================
[20:57:10] [PASSED] ttm_device_init_basic
[20:57:10] [PASSED] ttm_device_init_multiple
[20:57:10] [PASSED] ttm_device_fini_basic
[20:57:10] [PASSED] ttm_device_init_no_vma_man
[20:57:10] ================== ttm_device_init_pools  ==================
[20:57:10] [PASSED] No DMA allocations, no DMA32 required
[20:57:10] [PASSED] DMA allocations, DMA32 required
[20:57:10] [PASSED] No DMA allocations, DMA32 required
[20:57:10] [PASSED] DMA allocations, no DMA32 required
[20:57:10] ============== [PASSED] ttm_device_init_pools ==============
[20:57:10] =================== [PASSED] ttm_device ====================
[20:57:10] ================== ttm_pool (8 subtests) ===================
[20:57:10] ================== ttm_pool_alloc_basic  ===================
[20:57:10] [PASSED] One page
[20:57:10] [PASSED] More than one page
[20:57:10] [PASSED] Above the allocation limit
[20:57:10] [PASSED] One page, with coherent DMA mappings enabled
[20:57:10] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[20:57:10] ============== [PASSED] ttm_pool_alloc_basic ===============
[20:57:10] ============== ttm_pool_alloc_basic_dma_addr  ==============
[20:57:10] [PASSED] One page
[20:57:10] [PASSED] More than one page
[20:57:10] [PASSED] Above the allocation limit
[20:57:10] [PASSED] One page, with coherent DMA mappings enabled
[20:57:10] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[20:57:10] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[20:57:10] [PASSED] ttm_pool_alloc_order_caching_match
[20:57:10] [PASSED] ttm_pool_alloc_caching_mismatch
[20:57:10] [PASSED] ttm_pool_alloc_order_mismatch
[20:57:10] [PASSED] ttm_pool_free_dma_alloc
[20:57:10] [PASSED] ttm_pool_free_no_dma_alloc
[20:57:10] [PASSED] ttm_pool_fini_basic
[20:57:10] ==================== [PASSED] ttm_pool =====================
[20:57:10] ================ ttm_resource (8 subtests) =================
[20:57:10] ================= ttm_resource_init_basic  =================
[20:57:10] [PASSED] Init resource in TTM_PL_SYSTEM
[20:57:10] [PASSED] Init resource in TTM_PL_VRAM
[20:57:10] [PASSED] Init resource in a private placement
[20:57:10] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[20:57:10] ============= [PASSED] ttm_resource_init_basic =============
[20:57:10] [PASSED] ttm_resource_init_pinned
[20:57:10] [PASSED] ttm_resource_fini_basic
[20:57:10] [PASSED] ttm_resource_manager_init_basic
[20:57:10] [PASSED] ttm_resource_manager_usage_basic
[20:57:10] [PASSED] ttm_resource_manager_set_used_basic
[20:57:10] [PASSED] ttm_sys_man_alloc_basic
[20:57:10] [PASSED] ttm_sys_man_free_basic
[20:57:10] ================== [PASSED] ttm_resource ===================
[20:57:10] =================== ttm_tt (15 subtests) ===================
[20:57:10] ==================== ttm_tt_init_basic  ====================
[20:57:10] [PASSED] Page-aligned size
[20:57:10] [PASSED] Extra pages requested
[20:57:10] ================ [PASSED] ttm_tt_init_basic ================
[20:57:10] [PASSED] ttm_tt_init_misaligned
[20:57:10] [PASSED] ttm_tt_fini_basic
[20:57:10] [PASSED] ttm_tt_fini_sg
[20:57:10] [PASSED] ttm_tt_fini_shmem
[20:57:10] [PASSED] ttm_tt_create_basic
[20:57:10] [PASSED] ttm_tt_create_invalid_bo_type
[20:57:10] [PASSED] ttm_tt_create_ttm_exists
[20:57:10] [PASSED] ttm_tt_create_failed
[20:57:10] [PASSED] ttm_tt_destroy_basic
[20:57:10] [PASSED] ttm_tt_populate_null_ttm
[20:57:10] [PASSED] ttm_tt_populate_populated_ttm
[20:57:10] [PASSED] ttm_tt_unpopulate_basic
[20:57:10] [PASSED] ttm_tt_unpopulate_empty_ttm
[20:57:10] [PASSED] ttm_tt_swapin_basic
[20:57:10] ===================== [PASSED] ttm_tt ======================
[20:57:10] =================== ttm_bo (14 subtests) ===================
[20:57:10] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[20:57:10] [PASSED] Cannot be interrupted and sleeps
[20:57:10] [PASSED] Cannot be interrupted, locks straight away
[20:57:10] [PASSED] Can be interrupted, sleeps
[20:57:10] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[20:57:10] [PASSED] ttm_bo_reserve_locked_no_sleep
[20:57:10] [PASSED] ttm_bo_reserve_no_wait_ticket
[20:57:10] [PASSED] ttm_bo_reserve_double_resv
[20:57:10] [PASSED] ttm_bo_reserve_interrupted
[20:57:10] [PASSED] ttm_bo_reserve_deadlock
[20:57:10] [PASSED] ttm_bo_unreserve_basic
[20:57:10] [PASSED] ttm_bo_unreserve_pinned
[20:57:10] [PASSED] ttm_bo_unreserve_bulk
[20:57:10] [PASSED] ttm_bo_fini_basic
[20:57:10] [PASSED] ttm_bo_fini_shared_resv
[20:57:10] [PASSED] ttm_bo_pin_basic
[20:57:10] [PASSED] ttm_bo_pin_unpin_resource
[20:57:10] [PASSED] ttm_bo_multiple_pin_one_unpin
[20:57:10] ===================== [PASSED] ttm_bo ======================
[20:57:10] ============== ttm_bo_validate (21 subtests) ===============
[20:57:10] ============== ttm_bo_init_reserved_sys_man  ===============
[20:57:10] [PASSED] Buffer object for userspace
[20:57:10] [PASSED] Kernel buffer object
[20:57:10] [PASSED] Shared buffer object
[20:57:10] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[20:57:10] ============== ttm_bo_init_reserved_mock_man  ==============
[20:57:10] [PASSED] Buffer object for userspace
[20:57:10] [PASSED] Kernel buffer object
[20:57:10] [PASSED] Shared buffer object
[20:57:10] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[20:57:10] [PASSED] ttm_bo_init_reserved_resv
[20:57:10] ================== ttm_bo_validate_basic  ==================
[20:57:10] [PASSED] Buffer object for userspace
[20:57:10] [PASSED] Kernel buffer object
[20:57:10] [PASSED] Shared buffer object
[20:57:10] ============== [PASSED] ttm_bo_validate_basic ==============
[20:57:10] [PASSED] ttm_bo_validate_invalid_placement
[20:57:10] ============= ttm_bo_validate_same_placement  ==============
[20:57:10] [PASSED] System manager
[20:57:10] [PASSED] VRAM manager
[20:57:10] ========= [PASSED] ttm_bo_validate_same_placement ==========
[20:57:10] [PASSED] ttm_bo_validate_failed_alloc
[20:57:10] [PASSED] ttm_bo_validate_pinned
[20:57:10] [PASSED] ttm_bo_validate_busy_placement
[20:57:10] ================ ttm_bo_validate_multihop  =================
[20:57:10] [PASSED] Buffer object for userspace
[20:57:10] [PASSED] Kernel buffer object
[20:57:10] [PASSED] Shared buffer object
[20:57:10] ============ [PASSED] ttm_bo_validate_multihop =============
[20:57:10] ========== ttm_bo_validate_no_placement_signaled  ==========
[20:57:10] [PASSED] Buffer object in system domain, no page vector
[20:57:10] [PASSED] Buffer object in system domain with an existing page vector
[20:57:10] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[20:57:10] ======== ttm_bo_validate_no_placement_not_signaled  ========
[20:57:10] [PASSED] Buffer object for userspace
[20:57:10] [PASSED] Kernel buffer object
[20:57:10] [PASSED] Shared buffer object
[20:57:10] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[20:57:10] [PASSED] ttm_bo_validate_move_fence_signaled
[20:57:10] ========= ttm_bo_validate_move_fence_not_signaled  =========
[20:57:10] [PASSED] Waits for GPU
[20:57:10] [PASSED] Tries to lock straight away
[20:57:10] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[20:57:10] [PASSED] ttm_bo_validate_happy_evict
[20:57:10] [PASSED] ttm_bo_validate_all_pinned_evict
[20:57:10] [PASSED] ttm_bo_validate_allowed_only_evict
[20:57:10] [PASSED] ttm_bo_validate_deleted_evict
[20:57:10] [PASSED] ttm_bo_validate_busy_domain_evict
[20:57:10] [PASSED] ttm_bo_validate_evict_gutting
[20:57:10] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[20:57:10] ================= [PASSED] ttm_bo_validate =================
[20:57:10] ============================================================
[20:57:10] Testing complete. Ran 101 tests: passed: 101
[20:57:10] Elapsed time: 11.637s total, 1.705s configuring, 9.666s building, 0.228s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel



^ permalink raw reply	[flat|nested] 7+ messages in thread

* ✓ Xe.CI.BAT: success for GuC CT memory optimizations
  2026-02-13 20:50 [PATCH 0/2] GuC CT memory optimizations Matthew Brost
                   ` (2 preceding siblings ...)
  2026-02-13 20:57 ` ✓ CI.KUnit: success for GuC CT memory optimizations Patchwork
@ 2026-02-13 21:53 ` Patchwork
  2026-02-14 20:14 ` ✗ Xe.CI.FULL: failure " Patchwork
  4 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2026-02-13 21:53 UTC (permalink / raw)
  To: Matthew Brost; +Cc: intel-xe

[-- Attachment #1: Type: text/plain, Size: 850 bytes --]

== Series Details ==

Series: GuC CT memory optimizations
URL   : https://patchwork.freedesktop.org/series/161603/
State : success

== Summary ==

CI Bug Log - changes from xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288_BAT -> xe-pw-161603v1_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (14 -> 14)
------------------------------

  No changes in participating hosts


Changes
-------

  No changes found


Build changes
-------------

  * Linux: xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288 -> xe-pw-161603v1

  IGT_8753: 8753
  xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288: 69686d26e229ebcd8068fd86b7c39bc0832e8288
  xe-pw-161603v1: 161603v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/index.html

[-- Attachment #2: Type: text/html, Size: 1398 bytes --]

^ permalink raw reply	[flat|nested] 7+ messages in thread

* ✗ Xe.CI.FULL: failure for GuC CT memory optimizations
  2026-02-13 20:50 [PATCH 0/2] GuC CT memory optimizations Matthew Brost
                   ` (3 preceding siblings ...)
  2026-02-13 21:53 ` ✓ Xe.CI.BAT: " Patchwork
@ 2026-02-14 20:14 ` Patchwork
  4 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2026-02-14 20:14 UTC (permalink / raw)
  To: Matthew Brost; +Cc: intel-xe

[-- Attachment #1: Type: text/plain, Size: 21581 bytes --]

== Series Details ==

Series: GuC CT memory optimizations
URL   : https://patchwork.freedesktop.org/series/161603/
State : failure

== Summary ==

CI Bug Log - changes from xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288_FULL -> xe-pw-161603v1_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-161603v1_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-161603v1_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-161603v1_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@runner@aborted:
    - shard-bmg:          NOTRUN -> ([FAIL][1], [FAIL][2], [FAIL][3], [FAIL][4], [FAIL][5], [FAIL][6], [FAIL][7], [FAIL][8], [FAIL][9], [FAIL][10], [FAIL][11], [FAIL][12], [FAIL][13], [FAIL][14], [FAIL][15], [FAIL][16], [FAIL][17], [FAIL][18], [FAIL][19], [FAIL][20], [FAIL][21], [FAIL][22], [FAIL][23], [FAIL][24], [FAIL][25])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-bmg-8/igt@runner@aborted.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-bmg-10/igt@runner@aborted.html
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-bmg-8/igt@runner@aborted.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-bmg-1/igt@runner@aborted.html
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-bmg-9/igt@runner@aborted.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-bmg-4/igt@runner@aborted.html
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-bmg-10/igt@runner@aborted.html
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-bmg-5/igt@runner@aborted.html
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-bmg-4/igt@runner@aborted.html
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-bmg-2/igt@runner@aborted.html
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-bmg-3/igt@runner@aborted.html
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-bmg-6/igt@runner@aborted.html
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-bmg-6/igt@runner@aborted.html
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-bmg-1/igt@runner@aborted.html
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-bmg-6/igt@runner@aborted.html
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-bmg-2/igt@runner@aborted.html
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-bmg-10/igt@runner@aborted.html
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-bmg-2/igt@runner@aborted.html
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-bmg-1/igt@runner@aborted.html
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-bmg-5/igt@runner@aborted.html
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-bmg-5/igt@runner@aborted.html
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-bmg-8/igt@runner@aborted.html
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-bmg-7/igt@runner@aborted.html
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-bmg-7/igt@runner@aborted.html
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-bmg-9/igt@runner@aborted.html
    - shard-lnl:          NOTRUN -> ([FAIL][26], [FAIL][27], [FAIL][28], [FAIL][29], [FAIL][30], [FAIL][31], [FAIL][32], [FAIL][33], [FAIL][34], [FAIL][35], [FAIL][36], [FAIL][37], [FAIL][38], [FAIL][39], [FAIL][40], [FAIL][41], [FAIL][42], [FAIL][43], [FAIL][44], [FAIL][45], [FAIL][46], [FAIL][47], [FAIL][48], [FAIL][49], [FAIL][50])
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-lnl-2/igt@runner@aborted.html
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-lnl-8/igt@runner@aborted.html
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-lnl-3/igt@runner@aborted.html
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-lnl-1/igt@runner@aborted.html
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-lnl-5/igt@runner@aborted.html
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-lnl-4/igt@runner@aborted.html
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-lnl-3/igt@runner@aborted.html
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-lnl-5/igt@runner@aborted.html
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-lnl-6/igt@runner@aborted.html
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-lnl-6/igt@runner@aborted.html
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-lnl-1/igt@runner@aborted.html
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-lnl-4/igt@runner@aborted.html
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-lnl-4/igt@runner@aborted.html
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-lnl-8/igt@runner@aborted.html
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-lnl-1/igt@runner@aborted.html
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-lnl-2/igt@runner@aborted.html
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-lnl-5/igt@runner@aborted.html
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-lnl-8/igt@runner@aborted.html
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-lnl-7/igt@runner@aborted.html
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-lnl-7/igt@runner@aborted.html
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-lnl-1/igt@runner@aborted.html
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-lnl-2/igt@runner@aborted.html
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-lnl-3/igt@runner@aborted.html
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-lnl-5/igt@runner@aborted.html
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-lnl-6/igt@runner@aborted.html

  
Known issues
------------

  Here are the changes found in xe-pw-161603v1_FULL that come from known issues:

### IGT changes ###

#### Possible fixes ####

  * igt@xe_module_load@load:
    - shard-lnl:          ([PASS][51], [PASS][52], [PASS][53], [PASS][54], [PASS][55], [PASS][56], [PASS][57], [PASS][58], [PASS][59], [PASS][60], [PASS][61], [PASS][62], [PASS][63], [PASS][64], [SKIP][65], [PASS][66], [PASS][67], [PASS][68], [PASS][69], [PASS][70], [PASS][71], [PASS][72], [PASS][73], [PASS][74], [PASS][75], [PASS][76]) ([Intel XE#378]) -> ([PASS][77], [PASS][78], [PASS][79], [PASS][80], [PASS][81], [PASS][82], [PASS][83], [PASS][84], [PASS][85], [PASS][86], [PASS][87], [PASS][88], [PASS][89], [PASS][90], [PASS][91], [PASS][92], [PASS][93], [PASS][94], [PASS][95], [PASS][96], [PASS][97], [PASS][98], [PASS][99], [PASS][100], [PASS][101])
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-lnl-8/igt@xe_module_load@load.html
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-lnl-8/igt@xe_module_load@load.html
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-lnl-4/igt@xe_module_load@load.html
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-lnl-4/igt@xe_module_load@load.html
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-lnl-2/igt@xe_module_load@load.html
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-lnl-1/igt@xe_module_load@load.html
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-lnl-3/igt@xe_module_load@load.html
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-lnl-3/igt@xe_module_load@load.html
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-lnl-5/igt@xe_module_load@load.html
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-lnl-3/igt@xe_module_load@load.html
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-lnl-2/igt@xe_module_load@load.html
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-lnl-8/igt@xe_module_load@load.html
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-lnl-1/igt@xe_module_load@load.html
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-lnl-5/igt@xe_module_load@load.html
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-lnl-8/igt@xe_module_load@load.html
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-lnl-7/igt@xe_module_load@load.html
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-lnl-7/igt@xe_module_load@load.html
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-lnl-2/igt@xe_module_load@load.html
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-lnl-1/igt@xe_module_load@load.html
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-lnl-3/igt@xe_module_load@load.html
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-lnl-2/igt@xe_module_load@load.html
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-lnl-6/igt@xe_module_load@load.html
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-lnl-4/igt@xe_module_load@load.html
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-lnl-6/igt@xe_module_load@load.html
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-lnl-8/igt@xe_module_load@load.html
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-lnl-6/igt@xe_module_load@load.html
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-lnl-7/igt@xe_module_load@load.html
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-lnl-2/igt@xe_module_load@load.html
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-lnl-2/igt@xe_module_load@load.html
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-lnl-2/igt@xe_module_load@load.html
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-lnl-7/igt@xe_module_load@load.html
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-lnl-3/igt@xe_module_load@load.html
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-lnl-1/igt@xe_module_load@load.html
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-lnl-3/igt@xe_module_load@load.html
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-lnl-3/igt@xe_module_load@load.html
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-lnl-5/igt@xe_module_load@load.html
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-lnl-5/igt@xe_module_load@load.html
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-lnl-5/igt@xe_module_load@load.html
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-lnl-6/igt@xe_module_load@load.html
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-lnl-6/igt@xe_module_load@load.html
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-lnl-6/igt@xe_module_load@load.html
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-lnl-5/igt@xe_module_load@load.html
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-lnl-4/igt@xe_module_load@load.html
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-lnl-4/igt@xe_module_load@load.html
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-lnl-4/igt@xe_module_load@load.html
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-lnl-8/igt@xe_module_load@load.html
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-lnl-8/igt@xe_module_load@load.html
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-lnl-8/igt@xe_module_load@load.html
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-lnl-1/igt@xe_module_load@load.html
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-lnl-1/igt@xe_module_load@load.html
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-lnl-1/igt@xe_module_load@load.html
    - shard-bmg:          ([PASS][102], [PASS][103], [PASS][104], [PASS][105], [PASS][106], [PASS][107], [PASS][108], [PASS][109], [PASS][110], [PASS][111], [SKIP][112], [PASS][113], [PASS][114], [PASS][115], [PASS][116], [PASS][117], [PASS][118], [PASS][119], [PASS][120], [PASS][121], [PASS][122], [PASS][123], [PASS][124], [PASS][125], [PASS][126], [PASS][127]) ([Intel XE#2457]) -> ([PASS][128], [PASS][129], [PASS][130], [PASS][131], [PASS][132], [PASS][133], [PASS][134], [PASS][135], [PASS][136], [PASS][137], [PASS][138], [PASS][139], [PASS][140], [PASS][141], [PASS][142], [PASS][143], [PASS][144], [PASS][145], [PASS][146], [PASS][147], [PASS][148], [PASS][149], [PASS][150], [PASS][151], [PASS][152])
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-bmg-3/igt@xe_module_load@load.html
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-bmg-8/igt@xe_module_load@load.html
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-bmg-2/igt@xe_module_load@load.html
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-bmg-6/igt@xe_module_load@load.html
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-bmg-3/igt@xe_module_load@load.html
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-bmg-5/igt@xe_module_load@load.html
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-bmg-7/igt@xe_module_load@load.html
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-bmg-7/igt@xe_module_load@load.html
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-bmg-10/igt@xe_module_load@load.html
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-bmg-10/igt@xe_module_load@load.html
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-bmg-2/igt@xe_module_load@load.html
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-bmg-9/igt@xe_module_load@load.html
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-bmg-1/igt@xe_module_load@load.html
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-bmg-10/igt@xe_module_load@load.html
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-bmg-5/igt@xe_module_load@load.html
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-bmg-7/igt@xe_module_load@load.html
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-bmg-9/igt@xe_module_load@load.html
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-bmg-9/igt@xe_module_load@load.html
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-bmg-8/igt@xe_module_load@load.html
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-bmg-1/igt@xe_module_load@load.html
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-bmg-4/igt@xe_module_load@load.html
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-bmg-2/igt@xe_module_load@load.html
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-bmg-4/igt@xe_module_load@load.html
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-bmg-6/igt@xe_module_load@load.html
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-bmg-4/igt@xe_module_load@load.html
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-bmg-2/igt@xe_module_load@load.html
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-bmg-5/igt@xe_module_load@load.html
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-bmg-3/igt@xe_module_load@load.html
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-bmg-6/igt@xe_module_load@load.html
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-bmg-6/igt@xe_module_load@load.html
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-bmg-6/igt@xe_module_load@load.html
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-bmg-2/igt@xe_module_load@load.html
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-bmg-2/igt@xe_module_load@load.html
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-bmg-2/igt@xe_module_load@load.html
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-bmg-9/igt@xe_module_load@load.html
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-bmg-9/igt@xe_module_load@load.html
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-bmg-7/igt@xe_module_load@load.html
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-bmg-7/igt@xe_module_load@load.html
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-bmg-1/igt@xe_module_load@load.html
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-bmg-1/igt@xe_module_load@load.html
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-bmg-1/igt@xe_module_load@load.html
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-bmg-10/igt@xe_module_load@load.html
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-bmg-10/igt@xe_module_load@load.html
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-bmg-10/igt@xe_module_load@load.html
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-bmg-8/igt@xe_module_load@load.html
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-bmg-8/igt@xe_module_load@load.html
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-bmg-8/igt@xe_module_load@load.html
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-bmg-5/igt@xe_module_load@load.html
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-bmg-4/igt@xe_module_load@load.html
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-bmg-4/igt@xe_module_load@load.html
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/shard-bmg-5/igt@xe_module_load@load.html

  
  [Intel XE#2457]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2457
  [Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378


Build changes
-------------

  * Linux: xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288 -> xe-pw-161603v1

  IGT_8753: 8753
  xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288: 69686d26e229ebcd8068fd86b7c39bc0832e8288
  xe-pw-161603v1: 161603v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161603v1/index.html

[-- Attachment #2: Type: text/html, Size: 22015 bytes --]

^ permalink raw reply	[flat|nested] 7+ messages in thread

end of thread, other threads:[~2026-02-14 20:14 UTC | newest]

Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-02-13 20:50 [PATCH 0/2] GuC CT memory optimizations Matthew Brost
2026-02-13 20:50 ` [PATCH 1/2] drm/xe: Split H2G and G2H into separate buffer objects Matthew Brost
2026-02-13 21:17   ` Matthew Brost
2026-02-13 20:50 ` [PATCH 2/2] drm/xe: Remove H2G reads in CT send path in non-debug builds Matthew Brost
2026-02-13 20:57 ` ✓ CI.KUnit: success for GuC CT memory optimizations Patchwork
2026-02-13 21:53 ` ✓ Xe.CI.BAT: " Patchwork
2026-02-14 20:14 ` ✗ Xe.CI.FULL: failure " Patchwork

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