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From: Mika Kahola <mika.kahola@intel.com>
To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Cc: Mika Kahola <mika.kahola@intel.com>
Subject: [PATCH v3 23/24] drm/i915/lt_phy: Remove LT PHY specific state verification
Date: Fri,  6 Mar 2026 11:43:48 +0000	[thread overview]
Message-ID: <20260306114348.1161663-1-mika.kahola@intel.com> (raw)
In-Reply-To: <20260304131423.1017821-24-mika.kahola@intel.com>

Remove LT PHY specific state verification as DPLL framework
has state verification check.

v2: Reuse intel_lt_phy_pll_compare_hw_state() as only config[0]
    and config[0] parameters are reliable with LT PHY (Suraj)
v3: Rephrase handling of LT PHY case when verifying the state (CI)

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 14 +++++--
 drivers/gpu/drm/i915/display/intel_lt_phy.c   | 39 -------------------
 drivers/gpu/drm/i915/display/intel_lt_phy.h   |  2 -
 .../drm/i915/display/intel_modeset_verify.c   |  1 -
 4 files changed, 11 insertions(+), 45 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 534cc691979f..c3f35250f192 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -5075,6 +5075,7 @@ verify_single_dpll_state(struct intel_display *display,
 			 const struct intel_crtc_state *new_crtc_state)
 {
 	struct intel_dpll_hw_state dpll_hw_state = {};
+	bool pll_mismatch = false;
 	u8 pipe_mask;
 	bool active;
 
@@ -5116,9 +5117,16 @@ verify_single_dpll_state(struct intel_display *display,
 				 "%s: pll enabled crtcs mismatch (expected 0x%x in 0x%x)\n",
 				 pll->info->name, pipe_mask, pll->state.pipe_mask);
 
-	if (INTEL_DISPLAY_STATE_WARN(display,
-				     pll->on && memcmp(&pll->state.hw_state, &dpll_hw_state,
-						       sizeof(dpll_hw_state)),
+	if (pll->on) {
+		const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;
+
+		if (HAS_LT_PHY(display))
+			pll_mismatch = !dpll_mgr->compare_hw_state(&pll->state.hw_state, &dpll_hw_state);
+		else
+			pll_mismatch = memcmp(&pll->state.hw_state, &dpll_hw_state, sizeof(dpll_hw_state));
+	}
+
+	if (INTEL_DISPLAY_STATE_WARN(display, pll_mismatch,
 				     "%s: pll hw state mismatch\n",
 				     pll->info->name)) {
 		struct drm_printer p = drm_dbg_printer(display->drm, DRM_UT_KMS, NULL);
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 746b0182362a..032fd80664c6 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -2263,45 +2263,6 @@ bool intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
 	return true;
 }
 
-void intel_lt_phy_pll_state_verify(struct intel_atomic_state *state,
-				   struct intel_crtc *crtc)
-{
-	struct intel_display *display = to_intel_display(state);
-	struct intel_digital_port *dig_port;
-	const struct intel_crtc_state *new_crtc_state =
-		intel_atomic_get_new_crtc_state(state, crtc);
-	struct intel_encoder *encoder;
-	struct intel_lt_phy_pll_state pll_hw_state = {};
-	const struct intel_lt_phy_pll_state *pll_sw_state = &new_crtc_state->dpll_hw_state.ltpll;
-
-	if (DISPLAY_VER(display) < 35)
-		return;
-
-	if (!new_crtc_state->hw.active)
-		return;
-
-	/* intel_get_crtc_new_encoder() only works for modeset/fastset commits */
-	if (!intel_crtc_needs_modeset(new_crtc_state) &&
-	    !intel_crtc_needs_fastset(new_crtc_state))
-		return;
-
-	encoder = intel_get_crtc_new_encoder(state, new_crtc_state);
-	intel_lt_phy_pll_readout_hw_state(encoder, &pll_hw_state);
-
-	dig_port = enc_to_dig_port(encoder);
-	if (intel_tc_port_in_tbt_alt_mode(dig_port))
-		return;
-
-	INTEL_DISPLAY_STATE_WARN(display, pll_hw_state.config[0] != pll_sw_state->config[0],
-				 "[CRTC:%d:%s] mismatch in LT PHY PLL CONFIG 0: (expected 0x%04x, found 0x%04x)",
-				 crtc->base.base.id, crtc->base.name,
-				 pll_sw_state->config[0], pll_hw_state.config[0]);
-	INTEL_DISPLAY_STATE_WARN(display, pll_hw_state.config[2] != pll_sw_state->config[2],
-				 "[CRTC:%d:%s] mismatch in LT PHY PLL CONFIG 2: (expected 0x%04x, found 0x%04x)",
-				 crtc->base.base.id, crtc->base.name,
-				 pll_sw_state->config[2], pll_hw_state.config[2]);
-}
-
 void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
 			      struct intel_dpll *pll,
 			      const struct intel_dpll_hw_state *dpll_hw_state)
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h
index 1c2ec438cd10..8b98997b3107 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
@@ -41,8 +41,6 @@ bool intel_lt_phy_tbt_pll_readout_hw_state(struct intel_display *display,
 					   struct intel_dpll_hw_state *hw_state);
 bool intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
 				       struct intel_lt_phy_pll_state *pll_state);
-void intel_lt_phy_pll_state_verify(struct intel_atomic_state *state,
-				   struct intel_crtc *crtc);
 int
 intel_lt_phy_calculate_hdmi_state(struct intel_lt_phy_pll_state *lt_state,
 				  u32 frequency_khz);
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
index 12a00121c274..2ec17c2bfe0f 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
@@ -246,7 +246,6 @@ void intel_modeset_verify_crtc(struct intel_atomic_state *state,
 	verify_crtc_state(state, crtc);
 	intel_dpll_state_verify(state, crtc);
 	intel_mpllb_state_verify(state, crtc);
-	intel_lt_phy_pll_state_verify(state, crtc);
 }
 
 void intel_modeset_verify_disabled(struct intel_atomic_state *state)
-- 
2.43.0


  reply	other threads:[~2026-03-06 11:43 UTC|newest]

Thread overview: 67+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-03-04 13:13 [PATCH v2 00/24] Refactor LT PHY PLL handling to use DPLL framework Mika Kahola
2026-03-04 13:14 ` [PATCH v2 01/24] drm/i915/lt_phy: Dump missing PLL state parameters Mika Kahola
2026-03-10  2:57   ` Kandpal, Suraj
2026-03-10  3:10     ` Kandpal, Suraj
2026-03-04 13:14 ` [PATCH v2 02/24] drm/i915/lt_phy: Add check if PLL is enabled Mika Kahola
2026-03-10  3:09   ` Kandpal, Suraj
2026-03-04 13:14 ` [PATCH v2 03/24] drm/i915/lt_phy: Add PLL information for xe3plpd Mika Kahola
2026-03-10  3:54   ` Kandpal, Suraj
2026-03-04 13:14 ` [PATCH v2 04/24] drm/i915/lt_phy: Refactor LT PHY PLL handling to use explicit PLL state Mika Kahola
2026-03-04 14:04   ` Imre Deak
2026-03-05  8:19     ` Kahola, Mika
2026-03-10  4:02       ` Kandpal, Suraj
2026-03-10  7:36         ` Kahola, Mika
2026-03-10  8:33           ` Kandpal, Suraj
2026-03-10 13:36   ` [PATCH v3 03/24] " Mika Kahola
2026-03-10 15:38     ` [PATCH v3 04/24] " Mika Kahola
2026-03-11  4:18       ` Kandpal, Suraj
2026-03-11  6:15         ` Kandpal, Suraj
2026-03-11  8:12           ` Kahola, Mika
2026-03-04 13:14 ` [PATCH v2 05/24] drm/i915/lt_phy: Add lane_count to " Mika Kahola
2026-03-10  4:05   ` Kandpal, Suraj
2026-03-04 13:14 ` [PATCH v2 06/24] drm/i915/lt_phy: Add xe3plpd .compute_dplls hook Mika Kahola
2026-03-10  5:02   ` Kandpal, Suraj
2026-03-04 13:14 ` [PATCH v2 07/24] drm/i915/lt_phy: Add xe3plpd .get_dplls hook Mika Kahola
2026-03-04 13:14 ` [PATCH v2 08/24] drm/i915/lt_phy: Add xe3plpd .put_dplls hook Mika Kahola
2026-03-04 13:14 ` [PATCH v2 09/24] drm/i915/lt_phy: Add xe3plpd .update_active_dpll hook Mika Kahola
2026-03-04 13:14 ` [PATCH v2 10/24] drm/i915/lt_phy: Add xe3plpd .update_dpll_ref_clks hook Mika Kahola
2026-03-04 13:14 ` [PATCH v2 11/24] drm/i915/lt_phy: Add xe3plpd .dump_hw_state hook Mika Kahola
2026-03-10  6:19   ` Kandpal, Suraj
2026-03-10  6:32     ` Kandpal, Suraj
2026-03-04 13:14 ` [PATCH v2 12/24] drm/i915/lt_phy: Add xe3plpd .compare_hw_state hook Mika Kahola
2026-03-10  6:23   ` Kandpal, Suraj
2026-03-04 13:14 ` [PATCH v2 13/24] drm/i915/lt_phy: Add xe3plpd .get_hw_state hook Mika Kahola
2026-03-04 13:14 ` [PATCH v2 14/24] drm/i915/lt_phy: Add xe3plpd .get_freq hook Mika Kahola
2026-03-11  4:24   ` Kandpal, Suraj
2026-03-11 13:32     ` Kahola, Mika
2026-03-04 13:14 ` [PATCH v2 15/24] drm/i915/lt_phy: Add xe3plpd .crtc_get_dpll Mika Kahola
2026-03-04 13:14 ` [PATCH v2 16/24] drm/i915/lt_phy: Replace crtc compute clock Mika Kahola
2026-03-11  4:30   ` Kandpal, Suraj
2026-03-04 13:14 ` [PATCH v2 17/24] drm/i915/lt_phy: Add .enable_clock hook on DDI Mika Kahola
2026-03-11  4:48   ` Kandpal, Suraj
2026-03-04 13:14 ` [PATCH v2 18/24] drm/i915/lt_phy: Add .disable_clock " Mika Kahola
2026-03-11  5:31   ` Kandpal, Suraj
2026-03-11  5:59     ` Kandpal, Suraj
2026-03-11 11:34       ` Kahola, Mika
2026-03-04 13:14 ` [PATCH v2 19/24] drm/i915/lt_phy: Dump lane count for HW state Mika Kahola
2026-03-11  5:46   ` Kandpal, Suraj
2026-03-04 13:14 ` [PATCH v2 20/24] drm/i915/lt_phy: Readout lane count Mika Kahola
2026-03-04 13:14 ` [PATCH v2 21/24] drm/i915/lt_phy: Get encoder configuration for xe3plpd platform Mika Kahola
2026-03-11  5:55   ` Kandpal, Suraj
2026-03-04 13:14 ` [PATCH v2 22/24] drm/i915/lt_phy: Add xe3plpd Thunderbolt pll hooks Mika Kahola
2026-03-11  6:05   ` Kandpal, Suraj
2026-03-04 13:14 ` [PATCH v2 23/24] drm/i915/lt_phy: Remove LT PHY specific state verification Mika Kahola
2026-03-06 11:43   ` Mika Kahola [this message]
2026-03-10  8:40     ` [PATCH v3 " Kandpal, Suraj
2026-03-04 13:14 ` [PATCH v2 24/24] drm/i915/lt_phy: Enable dpll framework for xe3plpd Mika Kahola
2026-03-11  6:12   ` Kandpal, Suraj
2026-03-05 17:15 ` ✗ CI.checkpatch: warning for Refactor LT PHY PLL handling to use DPLL framework (rev2) Patchwork
2026-03-05 17:16 ` ✓ CI.KUnit: success " Patchwork
2026-03-05 18:32 ` ✗ Xe.CI.BAT: failure " Patchwork
2026-03-06  7:59 ` ✗ Xe.CI.FULL: " Patchwork
2026-03-06 20:27 ` ✗ CI.checkpatch: warning for Refactor LT PHY PLL handling to use DPLL framework (rev3) Patchwork
2026-03-06 20:28 ` ✓ CI.KUnit: success " Patchwork
2026-03-06 21:14 ` ✓ Xe.CI.BAT: " Patchwork
2026-03-07 23:48 ` ✗ Xe.CI.FULL: failure " Patchwork
2026-03-10 16:09 ` ✗ CI.checkpatch: warning for Refactor LT PHY PLL handling to use DPLL framework (rev5) Patchwork
2026-03-10 16:09 ` ✗ CI.KUnit: failure " Patchwork

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