[PATCH v2 00/24] Refactor LT PHY PLL handling to use DPLL framework

[PATCH v2 00/24] Refactor LT PHY PLL handling to use DPLL framework

[Mika Kahola]

This is v2 of [1], with the following changes
 - Split .enable_clock/disable_clock patch into separate, smaller patches
 - Use PCLK ack register to check if PLL is locked or not
 - Commit message updates

[1] https://lore.kernel.org/intel-gfx/20260213122615.1083654-1-mika.kahola@intel.com

Mika Kahola (24):
  drm/i915/lt_phy: Dump missing PLL state parameters
  drm/i915/lt_phy: Add check if PLL is enabled
  drm/i915/lt_phy: Add PLL information for xe3plpd
  drm/i915/lt_phy: Refactor LT PHY PLL handling to use explicit PLL
    state
  drm/i915/lt_phy: Add lane_count to PLL state
  drm/i915/lt_phy: Add xe3plpd .compute_dplls hook
  drm/i915/lt_phy: Add xe3plpd .get_dplls hook
  drm/i915/lt_phy: Add xe3plpd .put_dplls hook
  drm/i915/lt_phy: Add xe3plpd .update_active_dpll hook
  drm/i915/lt_phy: Add xe3plpd .update_dpll_ref_clks hook
  drm/i915/lt_phy: Add xe3plpd .dump_hw_state hook
  drm/i915/lt_phy: Add xe3plpd .compare_hw_state hook
  drm/i915/lt_phy: Add xe3plpd .get_hw_state hook
  drm/i915/lt_phy: Add xe3plpd .get_freq hook
  drm/i915/lt_phy: Add xe3plpd .crtc_get_dpll
  drm/i915/lt_phy: Replace crtc compute clock
  drm/i915/lt_phy: Add .enable_clock hook on DDI
  drm/i915/lt_phy: Add .disable_clock hook on DDI
  drm/i915/lt_phy: Dump lane count for HW state
  drm/i915/lt_phy: Readout lane count
  drm/i915/lt_phy: Get encoder configuration for xe3plpd platform
  drm/i915/lt_phy: Add xe3plpd Thunderbolt pll hooks
  drm/i915/lt_phy: Remove LT PHY specific state verification
  drm/i915/lt_phy: Enable dpll framework for xe3plpd

 drivers/gpu/drm/i915/display/intel_cx0_phy.c  |  10 +-
 drivers/gpu/drm/i915/display/intel_cx0_phy.h  |   1 +
 drivers/gpu/drm/i915/display/intel_ddi.c      |  26 +--
 drivers/gpu/drm/i915/display/intel_display.c  |  32 ---
 drivers/gpu/drm/i915/display/intel_dpll.c     |  26 +--
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 175 +++++++++++++++-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.h |   1 +
 drivers/gpu/drm/i915/display/intel_lt_phy.c   | 194 ++++++++++--------
 drivers/gpu/drm/i915/display/intel_lt_phy.h   |  26 ++-
 .../drm/i915/display/intel_modeset_verify.c   |   1 -
 10 files changed, 319 insertions(+), 173 deletions(-)

-- 
2.43.0

[PATCH v2 01/24] drm/i915/lt_phy: Dump missing PLL state parameters

[Mika Kahola]

Dump missing PLL structure members ssc_enabled and tbt_mode
in order to enhance debugging.

v2: Drop addr_lsb and addr_msb printouts

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_lt_phy.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index eced8493e566..f768804122c1 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -2141,7 +2141,9 @@ void intel_lt_phy_dump_hw_state(struct intel_display *display,
 {
 	int i, j;
 
-	drm_dbg_kms(display->drm, "lt_phy_pll_hw_state:\n");
+	drm_dbg_kms(display->drm, "lt_phy_pll_hw_state: ssc enabled: %d, tbt mode: %d\n",
+		    hw_state->ssc_enabled, hw_state->tbt_mode);
+
 	for (i = 0; i < 3; i++) {
 		drm_dbg_kms(display->drm, "config[%d] = 0x%.4x,\n",
 			    i, hw_state->config[i]);
-- 
2.43.0

RE: [PATCH v2 01/24] drm/i915/lt_phy: Dump missing PLL state parameters

[Kandpal, Suraj]

> Subject: [PATCH v2 01/24] drm/i915/lt_phy: Dump missing PLL state
> parameters
> 
> Dump missing PLL structure members ssc_enabled and tbt_mode in order to
> enhance debugging.
> 
> v2: Drop addr_lsb and addr_msb printouts
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>

LGTM,
Reviewed-by : Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_lt_phy.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index eced8493e566..f768804122c1 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -2141,7 +2141,9 @@ void intel_lt_phy_dump_hw_state(struct
> intel_display *display,  {
>  	int i, j;
> 
> -	drm_dbg_kms(display->drm, "lt_phy_pll_hw_state:\n");
> +	drm_dbg_kms(display->drm, "lt_phy_pll_hw_state: ssc enabled: %d,
> tbt mode: %d\n",
> +		    hw_state->ssc_enabled, hw_state->tbt_mode);
> +
>  	for (i = 0; i < 3; i++) {
>  		drm_dbg_kms(display->drm, "config[%d] = 0x%.4x,\n",
>  			    i, hw_state->config[i]);
> --
> 2.43.0

RE: [PATCH v2 01/24] drm/i915/lt_phy: Dump missing PLL state parameters

[Kandpal, Suraj]

> 
> > Subject: [PATCH v2 01/24] drm/i915/lt_phy: Dump missing PLL state
> > parameters
> >
> > Dump missing PLL structure members ssc_enabled and tbt_mode in order
> > to enhance debugging.
> >
> > v2: Drop addr_lsb and addr_msb printouts
> >
> > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> 
> LGTM,
> Reviewed-by : Suraj Kandpal <suraj.kandpal@intel.com>
> 

Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> > ---
> >  drivers/gpu/drm/i915/display/intel_lt_phy.c | 4 +++-
> >  1 file changed, 3 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > index eced8493e566..f768804122c1 100644
> > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > @@ -2141,7 +2141,9 @@ void intel_lt_phy_dump_hw_state(struct
> > intel_display *display,  {
> >  	int i, j;
> >
> > -	drm_dbg_kms(display->drm, "lt_phy_pll_hw_state:\n");
> > +	drm_dbg_kms(display->drm, "lt_phy_pll_hw_state: ssc enabled: %d,
> > tbt mode: %d\n",
> > +		    hw_state->ssc_enabled, hw_state->tbt_mode);
> > +
> >  	for (i = 0; i < 3; i++) {
> >  		drm_dbg_kms(display->drm, "config[%d] = 0x%.4x,\n",
> >  			    i, hw_state->config[i]);
> > --
> > 2.43.0

[PATCH v2 02/24] drm/i915/lt_phy: Add check if PLL is enabled

[Mika Kahola]

Add check for PLL enabling and return early if
PLL is not enabled.

v2: Use PCLK PLL request to check if PLL is enabled (Suraj)

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_lt_phy.c | 24 +++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index f768804122c1..8fe61cfdb706 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -2176,6 +2176,27 @@ intel_lt_phy_pll_compare_hw_state(const struct intel_lt_phy_pll_state *a,
 	return false;
 }
 
+static u32 intel_lt_phy_get_pclk_pll_ack(u8 lane_mask)
+{
+	u32 val = 0;
+	int lane = 0;
+
+	for_each_lt_phy_lane_in_mask(lane_mask, lane)
+		val |= XELPDP_LANE_PCLK_PLL_ACK(lane);
+
+	return val;
+}
+
+static bool intel_lt_phy_pll_is_enabled(struct intel_encoder *encoder)
+{
+	struct intel_display *display = to_intel_display(encoder);
+	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+	u8 lane = dig_port->lane_reversal ? INTEL_LT_PHY_LANE1 : INTEL_LT_PHY_LANE0;
+
+	return intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port)) &
+			     intel_lt_phy_get_pclk_pll_ack(lane);
+}
+
 void intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
 				       const struct intel_crtc_state *crtc_state,
 				       struct intel_lt_phy_pll_state *pll_state)
@@ -2185,6 +2206,9 @@ void intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
 	struct ref_tracker *wakeref;
 	int i, j, k;
 
+	if (!intel_lt_phy_pll_is_enabled(encoder))
+		return;
+
 	pll_state->tbt_mode = intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder));
 	if (pll_state->tbt_mode)
 		return;
-- 
2.43.0

RE: [PATCH v2 02/24] drm/i915/lt_phy: Add check if PLL is enabled

[Kandpal, Suraj]

> Subject: [PATCH v2 02/24] drm/i915/lt_phy: Add check if PLL is enabled
> 
> Add check for PLL enabling and return early if PLL is not enabled.
> 
> v2: Use PCLK PLL request to check if PLL is enabled (Suraj)
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_lt_phy.c | 24 +++++++++++++++++++++
>  1 file changed, 24 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index f768804122c1..8fe61cfdb706 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -2176,6 +2176,27 @@ intel_lt_phy_pll_compare_hw_state(const struct
> intel_lt_phy_pll_state *a,
>  	return false;
>  }
> 
> +static u32 intel_lt_phy_get_pclk_pll_ack(u8 lane_mask) {
> +	u32 val = 0;
> +	int lane = 0;
> +
> +	for_each_lt_phy_lane_in_mask(lane_mask, lane)
> +		val |= XELPDP_LANE_PCLK_PLL_ACK(lane);
> +

I think you forgot to implement the changes here they patch looks identical to previous one.
Maybe I wasn't able to get my point across properly.
Leaving the same comment again
unlike CX0 PHY where we the step is
Set PORT_CLOCK_CTL register PCLK PLL Request LN<Lane for maxPCLK**> to "1" to enable PLL.
That is not the case for LT PHY there we request and wait for ACK on Lane 0
Program PORT_CLOCK_CTL[PCLK PLL Request LN0] = 1. This will assert the MacCLK Request.
Poll for PORT_CLOCK_CTL[PCLK PLL Ack LN0]= 1. This is the MacCLKAck assertion. Expected MACCLK_TURNON_LATENCY is 100 us.
So all we need to do is check PCLK PLL ACK on LN0

Regards,
Suraj Kandpal

> +	return val;
> +}
> +
> +static bool intel_lt_phy_pll_is_enabled(struct intel_encoder *encoder)
> +{
> +	struct intel_display *display = to_intel_display(encoder);
> +	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> +	u8 lane = dig_port->lane_reversal ? INTEL_LT_PHY_LANE1 :
> +INTEL_LT_PHY_LANE0;
> +
> +	return intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display,
> encoder->port)) &
> +			     intel_lt_phy_get_pclk_pll_ack(lane);
> +}
> +
>  void intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
>  				       const struct intel_crtc_state *crtc_state,
>  				       struct intel_lt_phy_pll_state *pll_state)
> @@ -2185,6 +2206,9 @@ void intel_lt_phy_pll_readout_hw_state(struct
> intel_encoder *encoder,
>  	struct ref_tracker *wakeref;
>  	int i, j, k;
> 
> +	if (!intel_lt_phy_pll_is_enabled(encoder))
> +		return;
> +
>  	pll_state->tbt_mode =
> intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder));
>  	if (pll_state->tbt_mode)
>  		return;
> --
> 2.43.0

[PATCH v2 03/24] drm/i915/lt_phy: Add PLL information for xe3plpd

[Mika Kahola]

Start bringing in xe3plpd as part of dpll framework. The work is
started by adding PLL information and related function hooks.

v2: Fix xe3plpd type (Suraj)
    Remove empty line between BSpec link and Signed-off-by (Suraj)

BSpec: 74304
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index f35a9252f4e1..4185c8e136da 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4571,6 +4571,25 @@ static const struct intel_dpll_mgr mtl_pll_mgr = {
 	.compare_hw_state = mtl_compare_hw_state,
 };
 
+static const struct intel_dpll_funcs xe3plpd_pll_funcs = {
+};
+
+static const struct dpll_info xe3plpd_plls[] = {
+	{ .name = "DPLL 0", .funcs = &xe3plpd_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
+	{ .name = "DPLL 1", .funcs = &xe3plpd_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
+	/* TODO: Add TBT */
+	{ .name = "TC PLL 1", .funcs = &xe3plpd_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
+	{ .name = "TC PLL 2", .funcs = &xe3plpd_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
+	{ .name = "TC PLL 3", .funcs = &xe3plpd_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, },
+	{ .name = "TC PLL 4", .funcs = &xe3plpd_pll_funcs, .id = DPLL_ID_ICL_MGPLL4, },
+	{}
+};
+
+__maybe_unused
+static const struct intel_dpll_mgr xe3plpd_pll_mgr = {
+	.dpll_info = xe3plpd_plls,
+};
+
 /**
  * intel_dpll_init - Initialize DPLLs
  * @display: intel_display device
-- 
2.43.0

RE: [PATCH v2 03/24] drm/i915/lt_phy: Add PLL information for xe3plpd

[Kandpal, Suraj]

> Subject: [PATCH v2 03/24] drm/i915/lt_phy: Add PLL information for xe3plpd
> 
> Start bringing in xe3plpd as part of dpll framework. The work is started by
> adding PLL information and related function hooks.
> 
> v2: Fix xe3plpd type (Suraj)
>     Remove empty line between BSpec link and Signed-off-by (Suraj)
> 
> BSpec: 74304
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index f35a9252f4e1..4185c8e136da 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -4571,6 +4571,25 @@ static const struct intel_dpll_mgr mtl_pll_mgr = {
>  	.compare_hw_state = mtl_compare_hw_state,  };
> 
> +static const struct intel_dpll_funcs xe3plpd_pll_funcs = { };
> +
> +static const struct dpll_info xe3plpd_plls[] = {
> +	{ .name = "DPLL 0", .funcs = &xe3plpd_pll_funcs, .id =
> DPLL_ID_ICL_DPLL0, },
> +	{ .name = "DPLL 1", .funcs = &xe3plpd_pll_funcs, .id =
> DPLL_ID_ICL_DPLL1, },
> +	/* TODO: Add TBT */
> +	{ .name = "TC PLL 1", .funcs = &xe3plpd_pll_funcs, .id =
> DPLL_ID_ICL_MGPLL1, },
> +	{ .name = "TC PLL 2", .funcs = &xe3plpd_pll_funcs, .id =
> DPLL_ID_ICL_MGPLL2, },
> +	{ .name = "TC PLL 3", .funcs = &xe3plpd_pll_funcs, .id =
> DPLL_ID_ICL_MGPLL3, },
> +	{ .name = "TC PLL 4", .funcs = &xe3plpd_pll_funcs, .id =
> DPLL_ID_ICL_MGPLL4, },
> +	{}
> +};
> +
> +__maybe_unused
> +static const struct intel_dpll_mgr xe3plpd_pll_mgr = {
> +	.dpll_info = xe3plpd_plls,
> +};
> +
>  /**
>   * intel_dpll_init - Initialize DPLLs
>   * @display: intel_display device
> --
> 2.43.0

[PATCH v2 04/24] drm/i915/lt_phy: Refactor LT PHY PLL handling to use explicit PLL state

[Mika Kahola]

The LT PHY implementation currently pulls PLL and port_clock
information directly from the CRTC state. This ties the PHY
programming logic too tightly to the CRTC state and makes it
harder to clearly express the PHY’s own PLL configuration.

Introduce an explicit "struct intel_lt_phy_pll_state" argument
for the PHY functions and update callers accordingly.

No functional change is intended — this is a preparatory cleanup for
to bring LT PHY PLL handling as part of PLL framework.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_lt_phy.c | 48 ++++++++++++---------
 1 file changed, 27 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 8fe61cfdb706..ebdcab58df4a 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -1178,7 +1178,8 @@ intel_lt_phy_lane_reset(struct intel_encoder *encoder,
 
 static void
 intel_lt_phy_program_port_clock_ctl(struct intel_encoder *encoder,
-				    const struct intel_crtc_state *crtc_state,
+				    const struct intel_lt_phy_pll_state *ltpll,
+				    int port_clock,
 				    bool lane_reversal)
 {
 	struct intel_display *display = to_intel_display(encoder);
@@ -1195,17 +1196,17 @@ intel_lt_phy_program_port_clock_ctl(struct intel_encoder *encoder,
 	 * but since the register bits still remain the same we use
 	 * the same definition
 	 */
-	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
-	    intel_hdmi_is_frl(crtc_state->port_clock))
+	if (encoder->type == INTEL_OUTPUT_HDMI &&
+	    intel_hdmi_is_frl(port_clock))
 		val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_DIV18CLK);
 	else
 		val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_MAXPCLK);
 
 	 /* DP2.0 10G and 20G rates enable MPLLA*/
-	if (crtc_state->port_clock == 1000000 || crtc_state->port_clock == 2000000)
+	if (port_clock == 1000000 || port_clock == 2000000)
 		val |= XELPDP_SSC_ENABLE_PLLA;
 	else
-		val |= crtc_state->dpll_hw_state.ltpll.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
+		val |= ltpll->ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
 
 	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
 		     XELPDP_LANE1_PHY_CLOCK_SELECT | XELPDP_FORWARD_CLOCK_UNGATE |
@@ -1248,10 +1249,12 @@ static u32 intel_lt_phy_get_dp_clock(u8 rate)
 
 static bool
 intel_lt_phy_config_changed(struct intel_encoder *encoder,
-			    const struct intel_crtc_state *crtc_state)
+			    const struct intel_lt_phy_pll_state *ltpll)
 {
+	struct intel_display *display = to_intel_display(encoder);
 	u8 val, rate;
 	u32 clock;
+	u32 port_clock = intel_lt_phy_calc_port_clock(display, ltpll);
 
 	val = intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0,
 				LT_PHY_VDR_0_CONFIG);
@@ -1262,9 +1265,10 @@ intel_lt_phy_config_changed(struct intel_encoder *encoder,
 	 * using 1.62 Gbps clock since PHY PLL defaults to that
 	 * otherwise we always need to reconfigure it.
 	 */
-	if (intel_crtc_has_dp_encoder(crtc_state)) {
+	if (encoder->type == INTEL_OUTPUT_DP ||
+	    encoder->type == INTEL_OUTPUT_EDP) {
 		clock = intel_lt_phy_get_dp_clock(rate);
-		if (crtc_state->port_clock == 1620000 && crtc_state->port_clock == clock)
+		if (port_clock == 1620000 && port_clock == clock)
 			return false;
 	}
 
@@ -1759,41 +1763,41 @@ intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
 
 static void
 intel_lt_phy_program_pll(struct intel_encoder *encoder,
-			 const struct intel_crtc_state *crtc_state)
+			 const struct intel_lt_phy_pll_state *ltpll)
 {
 	u8 owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder);
 	int i, j, k;
 
 	intel_lt_phy_write(encoder, owned_lane_mask, LT_PHY_VDR_0_CONFIG,
-			   crtc_state->dpll_hw_state.ltpll.config[0], MB_WRITE_COMMITTED);
+			   ltpll->config[0], MB_WRITE_COMMITTED);
 	intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_VDR_1_CONFIG,
-			   crtc_state->dpll_hw_state.ltpll.config[1], MB_WRITE_COMMITTED);
+			   ltpll->config[1], MB_WRITE_COMMITTED);
 	intel_lt_phy_write(encoder, owned_lane_mask, LT_PHY_VDR_2_CONFIG,
-			   crtc_state->dpll_hw_state.ltpll.config[2], MB_WRITE_COMMITTED);
+			   ltpll->config[2], MB_WRITE_COMMITTED);
 
 	for (i = 0; i <= 12; i++) {
 		intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_VDR_X_ADDR_MSB(i),
-				   crtc_state->dpll_hw_state.ltpll.addr_msb[i],
+				   ltpll->addr_msb[i],
 				   MB_WRITE_COMMITTED);
 		intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_VDR_X_ADDR_LSB(i),
-				   crtc_state->dpll_hw_state.ltpll.addr_lsb[i],
+				   ltpll->addr_lsb[i],
 				   MB_WRITE_COMMITTED);
 
 		for (j = 3, k = 0; j >= 0; j--, k++)
 			intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0,
 					   LT_PHY_VDR_X_DATAY(i, j),
-					   crtc_state->dpll_hw_state.ltpll.data[i][k],
+					   ltpll->data[i][k],
 					   MB_WRITE_COMMITTED);
 	}
 }
 
 static void
 intel_lt_phy_enable_disable_tx(struct intel_encoder *encoder,
-			       const struct intel_crtc_state *crtc_state)
+			       const struct intel_lt_phy_pll_state *ltpll,
+			       u8 lane_count)
 {
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 	bool lane_reversal = dig_port->lane_reversal;
-	u8 lane_count = crtc_state->lane_count;
 	bool is_dp_alt =
 		intel_tc_port_in_dp_alt_mode(dig_port);
 	enum intel_tc_pin_assignment tc_pin =
@@ -1895,7 +1899,8 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
 	intel_lt_phy_lane_reset(encoder, crtc_state->lane_count);
 
 	/* 2. Program PORT_CLOCK_CTL register to configure clock muxes, gating, and SSC. */
-	intel_lt_phy_program_port_clock_ctl(encoder, crtc_state, lane_reversal);
+	intel_lt_phy_program_port_clock_ctl(encoder, &crtc_state->dpll_hw_state.ltpll,
+					    crtc_state->port_clock, lane_reversal);
 
 	/* 3. Change owned PHY lanes power to Ready state. */
 	intel_lt_phy_powerdown_change_sequence(encoder, owned_lane_mask,
@@ -1905,12 +1910,12 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
 	 * 4. Read the PHY message bus VDR register PHY_VDR_0_Config check enabled PLL type,
 	 * encoded rate and encoded mode.
 	 */
-	if (intel_lt_phy_config_changed(encoder, crtc_state)) {
+	if (intel_lt_phy_config_changed(encoder, &crtc_state->dpll_hw_state.ltpll)) {
 		/*
 		 * 5. Program the PHY internal PLL registers over PHY message bus for the desired
 		 * frequency and protocol type
 		 */
-		intel_lt_phy_program_pll(encoder, crtc_state);
+		intel_lt_phy_program_pll(encoder, &crtc_state->dpll_hw_state.ltpll);
 
 		/* 6. Use the P2P transaction flow */
 		/*
@@ -2001,7 +2006,8 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
 	intel_lt_phy_powerdown_change_sequence(encoder, owned_lane_mask,
 					       XELPDP_P0_STATE_ACTIVE);
 
-	intel_lt_phy_enable_disable_tx(encoder, crtc_state);
+	intel_lt_phy_enable_disable_tx(encoder, &crtc_state->dpll_hw_state.ltpll,
+				       crtc_state->lane_count);
 	intel_lt_phy_transaction_end(encoder, wakeref);
 }
 
-- 
2.43.0

Re: [PATCH v2 04/24] drm/i915/lt_phy: Refactor LT PHY PLL handling to use explicit PLL state

[Imre Deak]

On Wed, Mar 04, 2026 at 01:14:03PM +0000, Mika Kahola wrote:
> The LT PHY implementation currently pulls PLL and port_clock
> information directly from the CRTC state. This ties the PHY
> programming logic too tightly to the CRTC state and makes it
> harder to clearly express the PHY’s own PLL configuration.
> 
> Introduce an explicit "struct intel_lt_phy_pll_state" argument
> for the PHY functions and update callers accordingly.
> 
> No functional change is intended — this is a preparatory cleanup for
> to bring LT PHY PLL handling as part of PLL framework.
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_lt_phy.c | 48 ++++++++++++---------
>  1 file changed, 27 insertions(+), 21 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index 8fe61cfdb706..ebdcab58df4a 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -1178,7 +1178,8 @@ intel_lt_phy_lane_reset(struct intel_encoder *encoder,
>  
>  static void
>  intel_lt_phy_program_port_clock_ctl(struct intel_encoder *encoder,
> -				    const struct intel_crtc_state *crtc_state,
> +				    const struct intel_lt_phy_pll_state *ltpll,
> +				    int port_clock,
>  				    bool lane_reversal)
>  {
>  	struct intel_display *display = to_intel_display(encoder);
> @@ -1195,17 +1196,17 @@ intel_lt_phy_program_port_clock_ctl(struct intel_encoder *encoder,
>  	 * but since the register bits still remain the same we use
>  	 * the same definition
>  	 */
> -	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
> -	    intel_hdmi_is_frl(crtc_state->port_clock))
> +	if (encoder->type == INTEL_OUTPUT_HDMI &&

This was discussed already elsewhere: encoder->type can't be used to
determine if the encoder is in HDMI or DP mode. In fact on LT PHY
platforms encoder->type will be never INTEL_OUTPUT_HDMI, rather it's
INTEL_OUTPUT_DDI, where the actual mode of the DDI encoder could be
either HDMI or DP.

The ideal would be to deduct the DP/HDMI mode from the
intel_lt_phy_pll_state instead. AFAICS ltpll->config[0] is explicitly
set to 0x84 for both the computed and table-specified HDMI PLL
configurations and config[0] is not 0x84 for any DP PLL configurations.
Could be used that instead to distinguish the HDMI and DP configs?

> +	    intel_hdmi_is_frl(port_clock))
>  		val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_DIV18CLK);
>  	else
>  		val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_MAXPCLK);
>  
>  	 /* DP2.0 10G and 20G rates enable MPLLA*/
> -	if (crtc_state->port_clock == 1000000 || crtc_state->port_clock == 2000000)
> +	if (port_clock == 1000000 || port_clock == 2000000)
>  		val |= XELPDP_SSC_ENABLE_PLLA;
>  	else
> -		val |= crtc_state->dpll_hw_state.ltpll.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
> +		val |= ltpll->ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
>  
>  	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
>  		     XELPDP_LANE1_PHY_CLOCK_SELECT | XELPDP_FORWARD_CLOCK_UNGATE |
> @@ -1248,10 +1249,12 @@ static u32 intel_lt_phy_get_dp_clock(u8 rate)
>  
>  static bool
>  intel_lt_phy_config_changed(struct intel_encoder *encoder,
> -			    const struct intel_crtc_state *crtc_state)
> +			    const struct intel_lt_phy_pll_state *ltpll)
>  {
> +	struct intel_display *display = to_intel_display(encoder);
>  	u8 val, rate;
>  	u32 clock;
> +	u32 port_clock = intel_lt_phy_calc_port_clock(display, ltpll);
>  
>  	val = intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0,
>  				LT_PHY_VDR_0_CONFIG);
> @@ -1262,9 +1265,10 @@ intel_lt_phy_config_changed(struct intel_encoder *encoder,
>  	 * using 1.62 Gbps clock since PHY PLL defaults to that
>  	 * otherwise we always need to reconfigure it.
>  	 */
> -	if (intel_crtc_has_dp_encoder(crtc_state)) {
> +	if (encoder->type == INTEL_OUTPUT_DP ||
> +	    encoder->type == INTEL_OUTPUT_EDP) {

Same as above, encoder->type can't be used here.

>  		clock = intel_lt_phy_get_dp_clock(rate);
> -		if (crtc_state->port_clock == 1620000 && crtc_state->port_clock == clock)
> +		if (port_clock == 1620000 && port_clock == clock)
>  			return false;
>  	}
>  
> @@ -1759,41 +1763,41 @@ intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
>  
>  static void
>  intel_lt_phy_program_pll(struct intel_encoder *encoder,
> -			 const struct intel_crtc_state *crtc_state)
> +			 const struct intel_lt_phy_pll_state *ltpll)
>  {
>  	u8 owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder);
>  	int i, j, k;
>  
>  	intel_lt_phy_write(encoder, owned_lane_mask, LT_PHY_VDR_0_CONFIG,
> -			   crtc_state->dpll_hw_state.ltpll.config[0], MB_WRITE_COMMITTED);
> +			   ltpll->config[0], MB_WRITE_COMMITTED);
>  	intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_VDR_1_CONFIG,
> -			   crtc_state->dpll_hw_state.ltpll.config[1], MB_WRITE_COMMITTED);
> +			   ltpll->config[1], MB_WRITE_COMMITTED);
>  	intel_lt_phy_write(encoder, owned_lane_mask, LT_PHY_VDR_2_CONFIG,
> -			   crtc_state->dpll_hw_state.ltpll.config[2], MB_WRITE_COMMITTED);
> +			   ltpll->config[2], MB_WRITE_COMMITTED);
>  
>  	for (i = 0; i <= 12; i++) {
>  		intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_VDR_X_ADDR_MSB(i),
> -				   crtc_state->dpll_hw_state.ltpll.addr_msb[i],
> +				   ltpll->addr_msb[i],
>  				   MB_WRITE_COMMITTED);
>  		intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_VDR_X_ADDR_LSB(i),
> -				   crtc_state->dpll_hw_state.ltpll.addr_lsb[i],
> +				   ltpll->addr_lsb[i],
>  				   MB_WRITE_COMMITTED);
>  
>  		for (j = 3, k = 0; j >= 0; j--, k++)
>  			intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0,
>  					   LT_PHY_VDR_X_DATAY(i, j),
> -					   crtc_state->dpll_hw_state.ltpll.data[i][k],
> +					   ltpll->data[i][k],
>  					   MB_WRITE_COMMITTED);
>  	}
>  }
>  
>  static void
>  intel_lt_phy_enable_disable_tx(struct intel_encoder *encoder,
> -			       const struct intel_crtc_state *crtc_state)
> +			       const struct intel_lt_phy_pll_state *ltpll,
> +			       u8 lane_count)
>  {
>  	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>  	bool lane_reversal = dig_port->lane_reversal;
> -	u8 lane_count = crtc_state->lane_count;
>  	bool is_dp_alt =
>  		intel_tc_port_in_dp_alt_mode(dig_port);
>  	enum intel_tc_pin_assignment tc_pin =
> @@ -1895,7 +1899,8 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
>  	intel_lt_phy_lane_reset(encoder, crtc_state->lane_count);
>  
>  	/* 2. Program PORT_CLOCK_CTL register to configure clock muxes, gating, and SSC. */
> -	intel_lt_phy_program_port_clock_ctl(encoder, crtc_state, lane_reversal);
> +	intel_lt_phy_program_port_clock_ctl(encoder, &crtc_state->dpll_hw_state.ltpll,
> +					    crtc_state->port_clock, lane_reversal);
>  
>  	/* 3. Change owned PHY lanes power to Ready state. */
>  	intel_lt_phy_powerdown_change_sequence(encoder, owned_lane_mask,
> @@ -1905,12 +1910,12 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
>  	 * 4. Read the PHY message bus VDR register PHY_VDR_0_Config check enabled PLL type,
>  	 * encoded rate and encoded mode.
>  	 */
> -	if (intel_lt_phy_config_changed(encoder, crtc_state)) {
> +	if (intel_lt_phy_config_changed(encoder, &crtc_state->dpll_hw_state.ltpll)) {
>  		/*
>  		 * 5. Program the PHY internal PLL registers over PHY message bus for the desired
>  		 * frequency and protocol type
>  		 */
> -		intel_lt_phy_program_pll(encoder, crtc_state);
> +		intel_lt_phy_program_pll(encoder, &crtc_state->dpll_hw_state.ltpll);
>  
>  		/* 6. Use the P2P transaction flow */
>  		/*
> @@ -2001,7 +2006,8 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
>  	intel_lt_phy_powerdown_change_sequence(encoder, owned_lane_mask,
>  					       XELPDP_P0_STATE_ACTIVE);
>  
> -	intel_lt_phy_enable_disable_tx(encoder, crtc_state);
> +	intel_lt_phy_enable_disable_tx(encoder, &crtc_state->dpll_hw_state.ltpll,
> +				       crtc_state->lane_count);
>  	intel_lt_phy_transaction_end(encoder, wakeref);
>  }
>  
> -- 
> 2.43.0
> 

RE: [PATCH v2 04/24] drm/i915/lt_phy: Refactor LT PHY PLL handling to use explicit PLL state

[Kahola, Mika]

> -----Original Message-----
> From: Deak, Imre <imre.deak@intel.com>
> Sent: Wednesday, 4 March 2026 16.05
> To: Kahola, Mika <mika.kahola@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Subject: Re: [PATCH v2 04/24] drm/i915/lt_phy: Refactor LT PHY PLL handling to use explicit PLL state
> 
> On Wed, Mar 04, 2026 at 01:14:03PM +0000, Mika Kahola wrote:
> > The LT PHY implementation currently pulls PLL and port_clock
> > information directly from the CRTC state. This ties the PHY
> > programming logic too tightly to the CRTC state and makes it harder to
> > clearly express the PHY’s own PLL configuration.
> >
> > Introduce an explicit "struct intel_lt_phy_pll_state" argument for the
> > PHY functions and update callers accordingly.
> >
> > No functional change is intended — this is a preparatory cleanup for
> > to bring LT PHY PLL handling as part of PLL framework.
> >
> > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_lt_phy.c | 48
> > ++++++++++++---------
> >  1 file changed, 27 insertions(+), 21 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > index 8fe61cfdb706..ebdcab58df4a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > @@ -1178,7 +1178,8 @@ intel_lt_phy_lane_reset(struct intel_encoder
> > *encoder,
> >
> >  static void
> >  intel_lt_phy_program_port_clock_ctl(struct intel_encoder *encoder,
> > -				    const struct intel_crtc_state *crtc_state,
> > +				    const struct intel_lt_phy_pll_state *ltpll,
> > +				    int port_clock,
> >  				    bool lane_reversal)
> >  {
> >  	struct intel_display *display = to_intel_display(encoder); @@
> > -1195,17 +1196,17 @@ intel_lt_phy_program_port_clock_ctl(struct intel_encoder *encoder,
> >  	 * but since the register bits still remain the same we use
> >  	 * the same definition
> >  	 */
> > -	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
> > -	    intel_hdmi_is_frl(crtc_state->port_clock))
> > +	if (encoder->type == INTEL_OUTPUT_HDMI &&
> 
> This was discussed already elsewhere: encoder->type can't be used to determine if the encoder is in HDMI or DP mode. In fact on
> LT PHY platforms encoder->type will be never INTEL_OUTPUT_HDMI, rather it's INTEL_OUTPUT_DDI, where the actual mode of
> the DDI encoder could be either HDMI or DP.
> 
> The ideal would be to deduct the DP/HDMI mode from the intel_lt_phy_pll_state instead. AFAICS ltpll->config[0] is explicitly set to
> 0x84 for both the computed and table-specified HDMI PLL configurations and config[0] is not 0x84 for any DP PLL configurations.
> Could be used that instead to distinguish the HDMI and DP configs?

Right. I keep forgetting this that "encoder->type" can be both DP and HDMI. The naming to me seems a bit misleading and hence I keep forgetting this. Anyway, this approach cannot be used here but I must come up with better solution.

I could switch to use config[0] to distinguish HDMI.

Thanks for a review!

-Mika-
 
> 
> > +	    intel_hdmi_is_frl(port_clock))
> >  		val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_DIV18CLK);
> >  	else
> >  		val |= XELPDP_DDI_CLOCK_SELECT_PREP(display,
> > XELPDP_DDI_CLOCK_SELECT_MAXPCLK);
> >
> >  	 /* DP2.0 10G and 20G rates enable MPLLA*/
> > -	if (crtc_state->port_clock == 1000000 || crtc_state->port_clock == 2000000)
> > +	if (port_clock == 1000000 || port_clock == 2000000)
> >  		val |= XELPDP_SSC_ENABLE_PLLA;
> >  	else
> > -		val |= crtc_state->dpll_hw_state.ltpll.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
> > +		val |= ltpll->ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
> >
> >  	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
> >  		     XELPDP_LANE1_PHY_CLOCK_SELECT | XELPDP_FORWARD_CLOCK_UNGATE |
> > @@ -1248,10 +1249,12 @@ static u32 intel_lt_phy_get_dp_clock(u8 rate)
> >
> >  static bool
> >  intel_lt_phy_config_changed(struct intel_encoder *encoder,
> > -			    const struct intel_crtc_state *crtc_state)
> > +			    const struct intel_lt_phy_pll_state *ltpll)
> >  {
> > +	struct intel_display *display = to_intel_display(encoder);
> >  	u8 val, rate;
> >  	u32 clock;
> > +	u32 port_clock = intel_lt_phy_calc_port_clock(display, ltpll);
> >
> >  	val = intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0,
> >  				LT_PHY_VDR_0_CONFIG);
> > @@ -1262,9 +1265,10 @@ intel_lt_phy_config_changed(struct intel_encoder *encoder,
> >  	 * using 1.62 Gbps clock since PHY PLL defaults to that
> >  	 * otherwise we always need to reconfigure it.
> >  	 */
> > -	if (intel_crtc_has_dp_encoder(crtc_state)) {
> > +	if (encoder->type == INTEL_OUTPUT_DP ||
> > +	    encoder->type == INTEL_OUTPUT_EDP) {
> 
> Same as above, encoder->type can't be used here.
> 
> >  		clock = intel_lt_phy_get_dp_clock(rate);
> > -		if (crtc_state->port_clock == 1620000 && crtc_state->port_clock == clock)
> > +		if (port_clock == 1620000 && port_clock == clock)
> >  			return false;
> >  	}
> >
> > @@ -1759,41 +1763,41 @@ intel_lt_phy_pll_calc_state(struct
> > intel_crtc_state *crtc_state,
> >
> >  static void
> >  intel_lt_phy_program_pll(struct intel_encoder *encoder,
> > -			 const struct intel_crtc_state *crtc_state)
> > +			 const struct intel_lt_phy_pll_state *ltpll)
> >  {
> >  	u8 owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder);
> >  	int i, j, k;
> >
> >  	intel_lt_phy_write(encoder, owned_lane_mask, LT_PHY_VDR_0_CONFIG,
> > -			   crtc_state->dpll_hw_state.ltpll.config[0], MB_WRITE_COMMITTED);
> > +			   ltpll->config[0], MB_WRITE_COMMITTED);
> >  	intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_VDR_1_CONFIG,
> > -			   crtc_state->dpll_hw_state.ltpll.config[1], MB_WRITE_COMMITTED);
> > +			   ltpll->config[1], MB_WRITE_COMMITTED);
> >  	intel_lt_phy_write(encoder, owned_lane_mask, LT_PHY_VDR_2_CONFIG,
> > -			   crtc_state->dpll_hw_state.ltpll.config[2], MB_WRITE_COMMITTED);
> > +			   ltpll->config[2], MB_WRITE_COMMITTED);
> >
> >  	for (i = 0; i <= 12; i++) {
> >  		intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_VDR_X_ADDR_MSB(i),
> > -				   crtc_state->dpll_hw_state.ltpll.addr_msb[i],
> > +				   ltpll->addr_msb[i],
> >  				   MB_WRITE_COMMITTED);
> >  		intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_VDR_X_ADDR_LSB(i),
> > -				   crtc_state->dpll_hw_state.ltpll.addr_lsb[i],
> > +				   ltpll->addr_lsb[i],
> >  				   MB_WRITE_COMMITTED);
> >
> >  		for (j = 3, k = 0; j >= 0; j--, k++)
> >  			intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0,
> >  					   LT_PHY_VDR_X_DATAY(i, j),
> > -					   crtc_state->dpll_hw_state.ltpll.data[i][k],
> > +					   ltpll->data[i][k],
> >  					   MB_WRITE_COMMITTED);
> >  	}
> >  }
> >
> >  static void
> >  intel_lt_phy_enable_disable_tx(struct intel_encoder *encoder,
> > -			       const struct intel_crtc_state *crtc_state)
> > +			       const struct intel_lt_phy_pll_state *ltpll,
> > +			       u8 lane_count)
> >  {
> >  	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> >  	bool lane_reversal = dig_port->lane_reversal;
> > -	u8 lane_count = crtc_state->lane_count;
> >  	bool is_dp_alt =
> >  		intel_tc_port_in_dp_alt_mode(dig_port);
> >  	enum intel_tc_pin_assignment tc_pin = @@ -1895,7 +1899,8 @@ void
> > intel_lt_phy_pll_enable(struct intel_encoder *encoder,
> >  	intel_lt_phy_lane_reset(encoder, crtc_state->lane_count);
> >
> >  	/* 2. Program PORT_CLOCK_CTL register to configure clock muxes, gating, and SSC. */
> > -	intel_lt_phy_program_port_clock_ctl(encoder, crtc_state, lane_reversal);
> > +	intel_lt_phy_program_port_clock_ctl(encoder, &crtc_state->dpll_hw_state.ltpll,
> > +					    crtc_state->port_clock, lane_reversal);
> >
> >  	/* 3. Change owned PHY lanes power to Ready state. */
> >  	intel_lt_phy_powerdown_change_sequence(encoder, owned_lane_mask, @@
> > -1905,12 +1910,12 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
> >  	 * 4. Read the PHY message bus VDR register PHY_VDR_0_Config check enabled PLL type,
> >  	 * encoded rate and encoded mode.
> >  	 */
> > -	if (intel_lt_phy_config_changed(encoder, crtc_state)) {
> > +	if (intel_lt_phy_config_changed(encoder,
> > +&crtc_state->dpll_hw_state.ltpll)) {
> >  		/*
> >  		 * 5. Program the PHY internal PLL registers over PHY message bus for the desired
> >  		 * frequency and protocol type
> >  		 */
> > -		intel_lt_phy_program_pll(encoder, crtc_state);
> > +		intel_lt_phy_program_pll(encoder,
> > +&crtc_state->dpll_hw_state.ltpll);
> >
> >  		/* 6. Use the P2P transaction flow */
> >  		/*
> > @@ -2001,7 +2006,8 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
> >  	intel_lt_phy_powerdown_change_sequence(encoder, owned_lane_mask,
> >  					       XELPDP_P0_STATE_ACTIVE);
> >
> > -	intel_lt_phy_enable_disable_tx(encoder, crtc_state);
> > +	intel_lt_phy_enable_disable_tx(encoder, &crtc_state->dpll_hw_state.ltpll,
> > +				       crtc_state->lane_count);
> >  	intel_lt_phy_transaction_end(encoder, wakeref);  }
> >
> > --
> > 2.43.0
> >

RE: [PATCH v2 04/24] drm/i915/lt_phy: Refactor LT PHY PLL handling to use explicit PLL state

[Kandpal, Suraj]

> Subject: RE: [PATCH v2 04/24] drm/i915/lt_phy: Refactor LT PHY PLL handling
> to use explicit PLL state
> 
> > -----Original Message-----
> > From: Deak, Imre <imre.deak@intel.com>
> > Sent: Wednesday, 4 March 2026 16.05
> > To: Kahola, Mika <mika.kahola@intel.com>
> > Cc: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> > Subject: Re: [PATCH v2 04/24] drm/i915/lt_phy: Refactor LT PHY PLL
> > handling to use explicit PLL state
> >
> > On Wed, Mar 04, 2026 at 01:14:03PM +0000, Mika Kahola wrote:
> > > The LT PHY implementation currently pulls PLL and port_clock
> > > information directly from the CRTC state. This ties the PHY
> > > programming logic too tightly to the CRTC state and makes it harder
> > > to clearly express the PHY’s own PLL configuration.
> > >
> > > Introduce an explicit "struct intel_lt_phy_pll_state" argument for
> > > the PHY functions and update callers accordingly.
> > >
> > > No functional change is intended — this is a preparatory cleanup for
> > > to bring LT PHY PLL handling as part of PLL framework.
> > >
> > > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_lt_phy.c | 48
> > > ++++++++++++---------
> > >  1 file changed, 27 insertions(+), 21 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > > b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > > index 8fe61cfdb706..ebdcab58df4a 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > > @@ -1178,7 +1178,8 @@ intel_lt_phy_lane_reset(struct intel_encoder
> > > *encoder,
> > >
> > >  static void
> > >  intel_lt_phy_program_port_clock_ctl(struct intel_encoder *encoder,
> > > -				    const struct intel_crtc_state *crtc_state,
> > > +				    const struct intel_lt_phy_pll_state *ltpll,
> > > +				    int port_clock,
> > >  				    bool lane_reversal)
> > >  {
> > >  	struct intel_display *display = to_intel_display(encoder); @@
> > > -1195,17 +1196,17 @@ intel_lt_phy_program_port_clock_ctl(struct
> intel_encoder *encoder,
> > >  	 * but since the register bits still remain the same we use
> > >  	 * the same definition
> > >  	 */
> > > -	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
> > > -	    intel_hdmi_is_frl(crtc_state->port_clock))
> > > +	if (encoder->type == INTEL_OUTPUT_HDMI &&
> >
> > This was discussed already elsewhere: encoder->type can't be used to
> > determine if the encoder is in HDMI or DP mode. In fact on LT PHY
> > platforms encoder->type will be never INTEL_OUTPUT_HDMI, rather it's
> INTEL_OUTPUT_DDI, where the actual mode of the DDI encoder could be
> either HDMI or DP.
> >
> > The ideal would be to deduct the DP/HDMI mode from the
> > intel_lt_phy_pll_state instead. AFAICS ltpll->config[0] is explicitly
> > set to
> > 0x84 for both the computed and table-specified HDMI PLL configurations
> and config[0] is not 0x84 for any DP PLL configurations.
> > Could be used that instead to distinguish the HDMI and DP configs?
> 
> Right. I keep forgetting this that "encoder->type" can be both DP and HDMI.
> The naming to me seems a bit misleading and hence I keep forgetting this.
> Anyway, this approach cannot be used here but I must come up with better
> solution.
> 
> I could switch to use config[0] to distinguish HDMI.

We could also use intel_encoder_is_dp() that makes sure we skip HDMI connectors in that case.

Otherwise,
mode = REG_FIELD_GET8(LT_PHY_VDR_MODE_ENCODING_MASK, val);
mode & MODE_DP will also work

Regards,
Suraj Kandpal

> 
> Thanks for a review!
> 
> -Mika-
> 
> >
> > > +	    intel_hdmi_is_frl(port_clock))
> > >  		val |= XELPDP_DDI_CLOCK_SELECT_PREP(display,
> XELPDP_DDI_CLOCK_SELECT_DIV18CLK);
> > >  	else
> > >  		val |= XELPDP_DDI_CLOCK_SELECT_PREP(display,
> > > XELPDP_DDI_CLOCK_SELECT_MAXPCLK);
> > >
> > >  	 /* DP2.0 10G and 20G rates enable MPLLA*/
> > > -	if (crtc_state->port_clock == 1000000 || crtc_state->port_clock ==
> 2000000)
> > > +	if (port_clock == 1000000 || port_clock == 2000000)
> > >  		val |= XELPDP_SSC_ENABLE_PLLA;
> > >  	else
> > > -		val |= crtc_state->dpll_hw_state.ltpll.ssc_enabled ?
> XELPDP_SSC_ENABLE_PLLB : 0;
> > > +		val |= ltpll->ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
> > >
> > >  	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder-
> >port),
> > >  		     XELPDP_LANE1_PHY_CLOCK_SELECT |
> XELPDP_FORWARD_CLOCK_UNGATE
> > > | @@ -1248,10 +1249,12 @@ static u32 intel_lt_phy_get_dp_clock(u8
> > > rate)
> > >
> > >  static bool
> > >  intel_lt_phy_config_changed(struct intel_encoder *encoder,
> > > -			    const struct intel_crtc_state *crtc_state)
> > > +			    const struct intel_lt_phy_pll_state *ltpll)
> > >  {
> > > +	struct intel_display *display = to_intel_display(encoder);
> > >  	u8 val, rate;
> > >  	u32 clock;
> > > +	u32 port_clock = intel_lt_phy_calc_port_clock(display, ltpll);
> > >
> > >  	val = intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0,
> > >  				LT_PHY_VDR_0_CONFIG);
> > > @@ -1262,9 +1265,10 @@ intel_lt_phy_config_changed(struct
> intel_encoder *encoder,
> > >  	 * using 1.62 Gbps clock since PHY PLL defaults to that
> > >  	 * otherwise we always need to reconfigure it.
> > >  	 */
> > > -	if (intel_crtc_has_dp_encoder(crtc_state)) {
> > > +	if (encoder->type == INTEL_OUTPUT_DP ||
> > > +	    encoder->type == INTEL_OUTPUT_EDP) {
> >
> > Same as above, encoder->type can't be used here.
> >
> > >  		clock = intel_lt_phy_get_dp_clock(rate);
> > > -		if (crtc_state->port_clock == 1620000 && crtc_state-
> >port_clock == clock)
> > > +		if (port_clock == 1620000 && port_clock == clock)
> > >  			return false;
> > >  	}
> > >
> > > @@ -1759,41 +1763,41 @@ intel_lt_phy_pll_calc_state(struct
> > > intel_crtc_state *crtc_state,
> > >
> > >  static void
> > >  intel_lt_phy_program_pll(struct intel_encoder *encoder,
> > > -			 const struct intel_crtc_state *crtc_state)
> > > +			 const struct intel_lt_phy_pll_state *ltpll)
> > >  {
> > >  	u8 owned_lane_mask =
> intel_lt_phy_get_owned_lane_mask(encoder);
> > >  	int i, j, k;
> > >
> > >  	intel_lt_phy_write(encoder, owned_lane_mask,
> LT_PHY_VDR_0_CONFIG,
> > > -			   crtc_state->dpll_hw_state.ltpll.config[0],
> MB_WRITE_COMMITTED);
> > > +			   ltpll->config[0], MB_WRITE_COMMITTED);
> > >  	intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0,
> LT_PHY_VDR_1_CONFIG,
> > > -			   crtc_state->dpll_hw_state.ltpll.config[1],
> MB_WRITE_COMMITTED);
> > > +			   ltpll->config[1], MB_WRITE_COMMITTED);
> > >  	intel_lt_phy_write(encoder, owned_lane_mask,
> LT_PHY_VDR_2_CONFIG,
> > > -			   crtc_state->dpll_hw_state.ltpll.config[2],
> MB_WRITE_COMMITTED);
> > > +			   ltpll->config[2], MB_WRITE_COMMITTED);
> > >
> > >  	for (i = 0; i <= 12; i++) {
> > >  		intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0,
> LT_PHY_VDR_X_ADDR_MSB(i),
> > > -				   crtc_state->dpll_hw_state.ltpll.addr_msb[i],
> > > +				   ltpll->addr_msb[i],
> > >  				   MB_WRITE_COMMITTED);
> > >  		intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0,
> LT_PHY_VDR_X_ADDR_LSB(i),
> > > -				   crtc_state->dpll_hw_state.ltpll.addr_lsb[i],
> > > +				   ltpll->addr_lsb[i],
> > >  				   MB_WRITE_COMMITTED);
> > >
> > >  		for (j = 3, k = 0; j >= 0; j--, k++)
> > >  			intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0,
> > >  					   LT_PHY_VDR_X_DATAY(i, j),
> > > -					   crtc_state-
> >dpll_hw_state.ltpll.data[i][k],
> > > +					   ltpll->data[i][k],
> > >  					   MB_WRITE_COMMITTED);
> > >  	}
> > >  }
> > >
> > >  static void
> > >  intel_lt_phy_enable_disable_tx(struct intel_encoder *encoder,
> > > -			       const struct intel_crtc_state *crtc_state)
> > > +			       const struct intel_lt_phy_pll_state *ltpll,
> > > +			       u8 lane_count)
> > >  {
> > >  	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> > >  	bool lane_reversal = dig_port->lane_reversal;
> > > -	u8 lane_count = crtc_state->lane_count;
> > >  	bool is_dp_alt =
> > >  		intel_tc_port_in_dp_alt_mode(dig_port);
> > >  	enum intel_tc_pin_assignment tc_pin = @@ -1895,7 +1899,8 @@
> void
> > > intel_lt_phy_pll_enable(struct intel_encoder *encoder,
> > >  	intel_lt_phy_lane_reset(encoder, crtc_state->lane_count);
> > >
> > >  	/* 2. Program PORT_CLOCK_CTL register to configure clock muxes,
> gating, and SSC. */
> > > -	intel_lt_phy_program_port_clock_ctl(encoder, crtc_state,
> lane_reversal);
> > > +	intel_lt_phy_program_port_clock_ctl(encoder, &crtc_state-
> >dpll_hw_state.ltpll,
> > > +					    crtc_state->port_clock,
> lane_reversal);
> > >
> > >  	/* 3. Change owned PHY lanes power to Ready state. */
> > >  	intel_lt_phy_powerdown_change_sequence(encoder,
> owned_lane_mask,
> > > @@
> > > -1905,12 +1910,12 @@ void intel_lt_phy_pll_enable(struct intel_encoder
> *encoder,
> > >  	 * 4. Read the PHY message bus VDR register PHY_VDR_0_Config
> check enabled PLL type,
> > >  	 * encoded rate and encoded mode.
> > >  	 */
> > > -	if (intel_lt_phy_config_changed(encoder, crtc_state)) {
> > > +	if (intel_lt_phy_config_changed(encoder,
> > > +&crtc_state->dpll_hw_state.ltpll)) {
> > >  		/*
> > >  		 * 5. Program the PHY internal PLL registers over PHY
> message bus for the desired
> > >  		 * frequency and protocol type
> > >  		 */
> > > -		intel_lt_phy_program_pll(encoder, crtc_state);
> > > +		intel_lt_phy_program_pll(encoder,
> > > +&crtc_state->dpll_hw_state.ltpll);
> > >
> > >  		/* 6. Use the P2P transaction flow */
> > >  		/*
> > > @@ -2001,7 +2006,8 @@ void intel_lt_phy_pll_enable(struct
> intel_encoder *encoder,
> > >  	intel_lt_phy_powerdown_change_sequence(encoder,
> owned_lane_mask,
> > >  					       XELPDP_P0_STATE_ACTIVE);
> > >
> > > -	intel_lt_phy_enable_disable_tx(encoder, crtc_state);
> > > +	intel_lt_phy_enable_disable_tx(encoder, &crtc_state-
> >dpll_hw_state.ltpll,
> > > +				       crtc_state->lane_count);
> > >  	intel_lt_phy_transaction_end(encoder, wakeref);  }
> > >
> > > --
> > > 2.43.0
> > >

RE: [PATCH v2 04/24] drm/i915/lt_phy: Refactor LT PHY PLL handling to use explicit PLL state

[Kahola, Mika]

> -----Original Message-----
> From: Kandpal, Suraj <suraj.kandpal@intel.com>
> Sent: Tuesday, 10 March 2026 6.03
> To: Kahola, Mika <mika.kahola@intel.com>; Deak, Imre <imre.deak@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Subject: RE: [PATCH v2 04/24] drm/i915/lt_phy: Refactor LT PHY PLL handling to use explicit PLL state
> 
> > Subject: RE: [PATCH v2 04/24] drm/i915/lt_phy: Refactor LT PHY PLL
> > handling to use explicit PLL state
> >
> > > -----Original Message-----
> > > From: Deak, Imre <imre.deak@intel.com>
> > > Sent: Wednesday, 4 March 2026 16.05
> > > To: Kahola, Mika <mika.kahola@intel.com>
> > > Cc: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> > > Subject: Re: [PATCH v2 04/24] drm/i915/lt_phy: Refactor LT PHY PLL
> > > handling to use explicit PLL state
> > >
> > > On Wed, Mar 04, 2026 at 01:14:03PM +0000, Mika Kahola wrote:
> > > > The LT PHY implementation currently pulls PLL and port_clock
> > > > information directly from the CRTC state. This ties the PHY
> > > > programming logic too tightly to the CRTC state and makes it
> > > > harder to clearly express the PHY’s own PLL configuration.
> > > >
> > > > Introduce an explicit "struct intel_lt_phy_pll_state" argument for
> > > > the PHY functions and update callers accordingly.
> > > >
> > > > No functional change is intended — this is a preparatory cleanup
> > > > for to bring LT PHY PLL handling as part of PLL framework.
> > > >
> > > > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/display/intel_lt_phy.c | 48
> > > > ++++++++++++---------
> > > >  1 file changed, 27 insertions(+), 21 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > > > b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > > > index 8fe61cfdb706..ebdcab58df4a 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > > > @@ -1178,7 +1178,8 @@ intel_lt_phy_lane_reset(struct intel_encoder
> > > > *encoder,
> > > >
> > > >  static void
> > > >  intel_lt_phy_program_port_clock_ctl(struct intel_encoder *encoder,
> > > > -				    const struct intel_crtc_state *crtc_state,
> > > > +				    const struct intel_lt_phy_pll_state *ltpll,
> > > > +				    int port_clock,
> > > >  				    bool lane_reversal)
> > > >  {
> > > >  	struct intel_display *display = to_intel_display(encoder); @@
> > > > -1195,17 +1196,17 @@ intel_lt_phy_program_port_clock_ctl(struct
> > intel_encoder *encoder,
> > > >  	 * but since the register bits still remain the same we use
> > > >  	 * the same definition
> > > >  	 */
> > > > -	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
> > > > -	    intel_hdmi_is_frl(crtc_state->port_clock))
> > > > +	if (encoder->type == INTEL_OUTPUT_HDMI &&
> > >
> > > This was discussed already elsewhere: encoder->type can't be used to
> > > determine if the encoder is in HDMI or DP mode. In fact on LT PHY
> > > platforms encoder->type will be never INTEL_OUTPUT_HDMI, rather it's
> > INTEL_OUTPUT_DDI, where the actual mode of the DDI encoder could be
> > either HDMI or DP.
> > >
> > > The ideal would be to deduct the DP/HDMI mode from the
> > > intel_lt_phy_pll_state instead. AFAICS ltpll->config[0] is
> > > explicitly set to
> > > 0x84 for both the computed and table-specified HDMI PLL
> > > configurations
> > and config[0] is not 0x84 for any DP PLL configurations.
> > > Could be used that instead to distinguish the HDMI and DP configs?
> >
> > Right. I keep forgetting this that "encoder->type" can be both DP and HDMI.
> > The naming to me seems a bit misleading and hence I keep forgetting this.
> > Anyway, this approach cannot be used here but I must come up with
> > better solution.
> >
> > I could switch to use config[0] to distinguish HDMI.
> 
> We could also use intel_encoder_is_dp() that makes sure we skip HDMI connectors in that case.
> 
> Otherwise,
> mode = REG_FIELD_GET8(LT_PHY_VDR_MODE_ENCODING_MASK, val); mode & MODE_DP will also work

I have this latter one implemented but I haven't sent this patch to mailing list yet. It seems that for VDR configuration 0 register the bits 2:0 define the mode and for HDMI we either have 0x4 for HDMI and 0x5 for HDMI FRL. 

-Mika-

> 
> Regards,
> Suraj Kandpal
> 
> >
> > Thanks for a review!
> >
> > -Mika-
> >
> > >
> > > > +	    intel_hdmi_is_frl(port_clock))
> > > >  		val |= XELPDP_DDI_CLOCK_SELECT_PREP(display,
> > XELPDP_DDI_CLOCK_SELECT_DIV18CLK);
> > > >  	else
> > > >  		val |= XELPDP_DDI_CLOCK_SELECT_PREP(display,
> > > > XELPDP_DDI_CLOCK_SELECT_MAXPCLK);
> > > >
> > > >  	 /* DP2.0 10G and 20G rates enable MPLLA*/
> > > > -	if (crtc_state->port_clock == 1000000 || crtc_state->port_clock ==
> > 2000000)
> > > > +	if (port_clock == 1000000 || port_clock == 2000000)
> > > >  		val |= XELPDP_SSC_ENABLE_PLLA;
> > > >  	else
> > > > -		val |= crtc_state->dpll_hw_state.ltpll.ssc_enabled ?
> > XELPDP_SSC_ENABLE_PLLB : 0;
> > > > +		val |= ltpll->ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
> > > >
> > > >  	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder-
> > >port),
> > > >  		     XELPDP_LANE1_PHY_CLOCK_SELECT |
> > XELPDP_FORWARD_CLOCK_UNGATE
> > > > | @@ -1248,10 +1249,12 @@ static u32 intel_lt_phy_get_dp_clock(u8
> > > > rate)
> > > >
> > > >  static bool
> > > >  intel_lt_phy_config_changed(struct intel_encoder *encoder,
> > > > -			    const struct intel_crtc_state *crtc_state)
> > > > +			    const struct intel_lt_phy_pll_state *ltpll)
> > > >  {
> > > > +	struct intel_display *display = to_intel_display(encoder);
> > > >  	u8 val, rate;
> > > >  	u32 clock;
> > > > +	u32 port_clock = intel_lt_phy_calc_port_clock(display, ltpll);
> > > >
> > > >  	val = intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0,
> > > >  				LT_PHY_VDR_0_CONFIG);
> > > > @@ -1262,9 +1265,10 @@ intel_lt_phy_config_changed(struct
> > intel_encoder *encoder,
> > > >  	 * using 1.62 Gbps clock since PHY PLL defaults to that
> > > >  	 * otherwise we always need to reconfigure it.
> > > >  	 */
> > > > -	if (intel_crtc_has_dp_encoder(crtc_state)) {
> > > > +	if (encoder->type == INTEL_OUTPUT_DP ||
> > > > +	    encoder->type == INTEL_OUTPUT_EDP) {
> > >
> > > Same as above, encoder->type can't be used here.
> > >
> > > >  		clock = intel_lt_phy_get_dp_clock(rate);
> > > > -		if (crtc_state->port_clock == 1620000 && crtc_state-
> > >port_clock == clock)
> > > > +		if (port_clock == 1620000 && port_clock == clock)
> > > >  			return false;
> > > >  	}
> > > >
> > > > @@ -1759,41 +1763,41 @@ intel_lt_phy_pll_calc_state(struct
> > > > intel_crtc_state *crtc_state,
> > > >
> > > >  static void
> > > >  intel_lt_phy_program_pll(struct intel_encoder *encoder,
> > > > -			 const struct intel_crtc_state *crtc_state)
> > > > +			 const struct intel_lt_phy_pll_state *ltpll)
> > > >  {
> > > >  	u8 owned_lane_mask =
> > intel_lt_phy_get_owned_lane_mask(encoder);
> > > >  	int i, j, k;
> > > >
> > > >  	intel_lt_phy_write(encoder, owned_lane_mask,
> > LT_PHY_VDR_0_CONFIG,
> > > > -			   crtc_state->dpll_hw_state.ltpll.config[0],
> > MB_WRITE_COMMITTED);
> > > > +			   ltpll->config[0], MB_WRITE_COMMITTED);
> > > >  	intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0,
> > LT_PHY_VDR_1_CONFIG,
> > > > -			   crtc_state->dpll_hw_state.ltpll.config[1],
> > MB_WRITE_COMMITTED);
> > > > +			   ltpll->config[1], MB_WRITE_COMMITTED);
> > > >  	intel_lt_phy_write(encoder, owned_lane_mask,
> > LT_PHY_VDR_2_CONFIG,
> > > > -			   crtc_state->dpll_hw_state.ltpll.config[2],
> > MB_WRITE_COMMITTED);
> > > > +			   ltpll->config[2], MB_WRITE_COMMITTED);
> > > >
> > > >  	for (i = 0; i <= 12; i++) {
> > > >  		intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0,
> > LT_PHY_VDR_X_ADDR_MSB(i),
> > > > -				   crtc_state->dpll_hw_state.ltpll.addr_msb[i],
> > > > +				   ltpll->addr_msb[i],
> > > >  				   MB_WRITE_COMMITTED);
> > > >  		intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0,
> > LT_PHY_VDR_X_ADDR_LSB(i),
> > > > -				   crtc_state->dpll_hw_state.ltpll.addr_lsb[i],
> > > > +				   ltpll->addr_lsb[i],
> > > >  				   MB_WRITE_COMMITTED);
> > > >
> > > >  		for (j = 3, k = 0; j >= 0; j--, k++)
> > > >  			intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0,
> > > >  					   LT_PHY_VDR_X_DATAY(i, j),
> > > > -					   crtc_state-
> > >dpll_hw_state.ltpll.data[i][k],
> > > > +					   ltpll->data[i][k],
> > > >  					   MB_WRITE_COMMITTED);
> > > >  	}
> > > >  }
> > > >
> > > >  static void
> > > >  intel_lt_phy_enable_disable_tx(struct intel_encoder *encoder,
> > > > -			       const struct intel_crtc_state *crtc_state)
> > > > +			       const struct intel_lt_phy_pll_state *ltpll,
> > > > +			       u8 lane_count)
> > > >  {
> > > >  	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> > > >  	bool lane_reversal = dig_port->lane_reversal;
> > > > -	u8 lane_count = crtc_state->lane_count;
> > > >  	bool is_dp_alt =
> > > >  		intel_tc_port_in_dp_alt_mode(dig_port);
> > > >  	enum intel_tc_pin_assignment tc_pin = @@ -1895,7 +1899,8 @@
> > void
> > > > intel_lt_phy_pll_enable(struct intel_encoder *encoder,
> > > >  	intel_lt_phy_lane_reset(encoder, crtc_state->lane_count);
> > > >
> > > >  	/* 2. Program PORT_CLOCK_CTL register to configure clock muxes,
> > gating, and SSC. */
> > > > -	intel_lt_phy_program_port_clock_ctl(encoder, crtc_state,
> > lane_reversal);
> > > > +	intel_lt_phy_program_port_clock_ctl(encoder, &crtc_state-
> > >dpll_hw_state.ltpll,
> > > > +					    crtc_state->port_clock,
> > lane_reversal);
> > > >
> > > >  	/* 3. Change owned PHY lanes power to Ready state. */
> > > >  	intel_lt_phy_powerdown_change_sequence(encoder,
> > owned_lane_mask,
> > > > @@
> > > > -1905,12 +1910,12 @@ void intel_lt_phy_pll_enable(struct
> > > > intel_encoder
> > *encoder,
> > > >  	 * 4. Read the PHY message bus VDR register PHY_VDR_0_Config
> > check enabled PLL type,
> > > >  	 * encoded rate and encoded mode.
> > > >  	 */
> > > > -	if (intel_lt_phy_config_changed(encoder, crtc_state)) {
> > > > +	if (intel_lt_phy_config_changed(encoder,
> > > > +&crtc_state->dpll_hw_state.ltpll)) {
> > > >  		/*
> > > >  		 * 5. Program the PHY internal PLL registers over PHY
> > message bus for the desired
> > > >  		 * frequency and protocol type
> > > >  		 */
> > > > -		intel_lt_phy_program_pll(encoder, crtc_state);
> > > > +		intel_lt_phy_program_pll(encoder,
> > > > +&crtc_state->dpll_hw_state.ltpll);
> > > >
> > > >  		/* 6. Use the P2P transaction flow */
> > > >  		/*
> > > > @@ -2001,7 +2006,8 @@ void intel_lt_phy_pll_enable(struct
> > intel_encoder *encoder,
> > > >  	intel_lt_phy_powerdown_change_sequence(encoder,
> > owned_lane_mask,
> > > >  					       XELPDP_P0_STATE_ACTIVE);
> > > >
> > > > -	intel_lt_phy_enable_disable_tx(encoder, crtc_state);
> > > > +	intel_lt_phy_enable_disable_tx(encoder, &crtc_state-
> > >dpll_hw_state.ltpll,
> > > > +				       crtc_state->lane_count);
> > > >  	intel_lt_phy_transaction_end(encoder, wakeref);  }
> > > >
> > > > --
> > > > 2.43.0
> > > >

RE: [PATCH v2 04/24] drm/i915/lt_phy: Refactor LT PHY PLL handling to use explicit PLL state

[Kandpal, Suraj]

> 
> 
> 
> > -----Original Message-----
> > From: Kandpal, Suraj <suraj.kandpal@intel.com>
> > Sent: Tuesday, 10 March 2026 6.03
> > To: Kahola, Mika <mika.kahola@intel.com>; Deak, Imre
> > <imre.deak@intel.com>
> > Cc: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> > Subject: RE: [PATCH v2 04/24] drm/i915/lt_phy: Refactor LT PHY PLL
> > handling to use explicit PLL state
> >
> > > Subject: RE: [PATCH v2 04/24] drm/i915/lt_phy: Refactor LT PHY PLL
> > > handling to use explicit PLL state
> > >
> > > > -----Original Message-----
> > > > From: Deak, Imre <imre.deak@intel.com>
> > > > Sent: Wednesday, 4 March 2026 16.05
> > > > To: Kahola, Mika <mika.kahola@intel.com>
> > > > Cc: intel-gfx@lists.freedesktop.org;
> > > > intel-xe@lists.freedesktop.org
> > > > Subject: Re: [PATCH v2 04/24] drm/i915/lt_phy: Refactor LT PHY PLL
> > > > handling to use explicit PLL state
> > > >
> > > > On Wed, Mar 04, 2026 at 01:14:03PM +0000, Mika Kahola wrote:
> > > > > The LT PHY implementation currently pulls PLL and port_clock
> > > > > information directly from the CRTC state. This ties the PHY
> > > > > programming logic too tightly to the CRTC state and makes it
> > > > > harder to clearly express the PHY’s own PLL configuration.
> > > > >
> > > > > Introduce an explicit "struct intel_lt_phy_pll_state" argument
> > > > > for the PHY functions and update callers accordingly.
> > > > >
> > > > > No functional change is intended — this is a preparatory cleanup
> > > > > for to bring LT PHY PLL handling as part of PLL framework.
> > > > >
> > > > > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > > > > ---
> > > > >  drivers/gpu/drm/i915/display/intel_lt_phy.c | 48
> > > > > ++++++++++++---------
> > > > >  1 file changed, 27 insertions(+), 21 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > > > > b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > > > > index 8fe61cfdb706..ebdcab58df4a 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > > > > @@ -1178,7 +1178,8 @@ intel_lt_phy_lane_reset(struct
> > > > > intel_encoder *encoder,
> > > > >
> > > > >  static void
> > > > >  intel_lt_phy_program_port_clock_ctl(struct intel_encoder *encoder,
> > > > > -				    const struct intel_crtc_state *crtc_state,
> > > > > +				    const struct intel_lt_phy_pll_state
> *ltpll,
> > > > > +				    int port_clock,
> > > > >  				    bool lane_reversal)
> > > > >  {
> > > > >  	struct intel_display *display = to_intel_display(encoder); @@
> > > > > -1195,17 +1196,17 @@ intel_lt_phy_program_port_clock_ctl(struct
> > > intel_encoder *encoder,
> > > > >  	 * but since the register bits still remain the same we use
> > > > >  	 * the same definition
> > > > >  	 */
> > > > > -	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
> > > > > -	    intel_hdmi_is_frl(crtc_state->port_clock))
> > > > > +	if (encoder->type == INTEL_OUTPUT_HDMI &&
> > > >
> > > > This was discussed already elsewhere: encoder->type can't be used
> > > > to determine if the encoder is in HDMI or DP mode. In fact on LT
> > > > PHY platforms encoder->type will be never INTEL_OUTPUT_HDMI,
> > > > rather it's
> > > INTEL_OUTPUT_DDI, where the actual mode of the DDI encoder could be
> > > either HDMI or DP.
> > > >
> > > > The ideal would be to deduct the DP/HDMI mode from the
> > > > intel_lt_phy_pll_state instead. AFAICS ltpll->config[0] is
> > > > explicitly set to
> > > > 0x84 for both the computed and table-specified HDMI PLL
> > > > configurations
> > > and config[0] is not 0x84 for any DP PLL configurations.
> > > > Could be used that instead to distinguish the HDMI and DP configs?
> > >
> > > Right. I keep forgetting this that "encoder->type" can be both DP and HDMI.
> > > The naming to me seems a bit misleading and hence I keep forgetting this.
> > > Anyway, this approach cannot be used here but I must come up with
> > > better solution.
> > >
> > > I could switch to use config[0] to distinguish HDMI.
> >
> > We could also use intel_encoder_is_dp() that makes sure we skip HDMI
> connectors in that case.
> >
> > Otherwise,
> > mode = REG_FIELD_GET8(LT_PHY_VDR_MODE_ENCODING_MASK, val); mode
> &
> > MODE_DP will also work
> 
> I have this latter one implemented but I haven't sent this patch to mailing list
> yet. It seems that for VDR configuration 0 register the bits 2:0 define the mode
> and for HDMI we either have 0x4 for HDMI and 0x5 for HDMI FRL.

Yes and 3 for DP/EDP which makes life easier was actually added for this same purpose in LT PHY.

Regards,
Suraj Kandpal

> 
> -Mika-
> 
> >
> > Regards,
> > Suraj Kandpal
> >
> > >
> > > Thanks for a review!
> > >
> > > -Mika-
> > >
> > > >
> > > > > +	    intel_hdmi_is_frl(port_clock))
> > > > >  		val |= XELPDP_DDI_CLOCK_SELECT_PREP(display,
> > > XELPDP_DDI_CLOCK_SELECT_DIV18CLK);
> > > > >  	else
> > > > >  		val |= XELPDP_DDI_CLOCK_SELECT_PREP(display,
> > > > > XELPDP_DDI_CLOCK_SELECT_MAXPCLK);
> > > > >
> > > > >  	 /* DP2.0 10G and 20G rates enable MPLLA*/
> > > > > -	if (crtc_state->port_clock == 1000000 || crtc_state->port_clock ==
> > > 2000000)
> > > > > +	if (port_clock == 1000000 || port_clock == 2000000)
> > > > >  		val |= XELPDP_SSC_ENABLE_PLLA;
> > > > >  	else
> > > > > -		val |= crtc_state->dpll_hw_state.ltpll.ssc_enabled ?
> > > XELPDP_SSC_ENABLE_PLLB : 0;
> > > > > +		val |= ltpll->ssc_enabled ? XELPDP_SSC_ENABLE_PLLB :
> 0;
> > > > >
> > > > >  	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder-
> > > >port),
> > > > >  		     XELPDP_LANE1_PHY_CLOCK_SELECT |
> > > XELPDP_FORWARD_CLOCK_UNGATE
> > > > > | @@ -1248,10 +1249,12 @@ static u32
> > > > > | intel_lt_phy_get_dp_clock(u8
> > > > > rate)
> > > > >
> > > > >  static bool
> > > > >  intel_lt_phy_config_changed(struct intel_encoder *encoder,
> > > > > -			    const struct intel_crtc_state *crtc_state)
> > > > > +			    const struct intel_lt_phy_pll_state *ltpll)
> > > > >  {
> > > > > +	struct intel_display *display = to_intel_display(encoder);
> > > > >  	u8 val, rate;
> > > > >  	u32 clock;
> > > > > +	u32 port_clock = intel_lt_phy_calc_port_clock(display, ltpll);
> > > > >
> > > > >  	val = intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0,
> > > > >  				LT_PHY_VDR_0_CONFIG);
> > > > > @@ -1262,9 +1265,10 @@ intel_lt_phy_config_changed(struct
> > > intel_encoder *encoder,
> > > > >  	 * using 1.62 Gbps clock since PHY PLL defaults to that
> > > > >  	 * otherwise we always need to reconfigure it.
> > > > >  	 */
> > > > > -	if (intel_crtc_has_dp_encoder(crtc_state)) {
> > > > > +	if (encoder->type == INTEL_OUTPUT_DP ||
> > > > > +	    encoder->type == INTEL_OUTPUT_EDP) {
> > > >
> > > > Same as above, encoder->type can't be used here.
> > > >
> > > > >  		clock = intel_lt_phy_get_dp_clock(rate);
> > > > > -		if (crtc_state->port_clock == 1620000 && crtc_state-
> > > >port_clock == clock)
> > > > > +		if (port_clock == 1620000 && port_clock == clock)
> > > > >  			return false;
> > > > >  	}
> > > > >
> > > > > @@ -1759,41 +1763,41 @@ intel_lt_phy_pll_calc_state(struct
> > > > > intel_crtc_state *crtc_state,
> > > > >
> > > > >  static void
> > > > >  intel_lt_phy_program_pll(struct intel_encoder *encoder,
> > > > > -			 const struct intel_crtc_state *crtc_state)
> > > > > +			 const struct intel_lt_phy_pll_state *ltpll)
> > > > >  {
> > > > >  	u8 owned_lane_mask =
> > > intel_lt_phy_get_owned_lane_mask(encoder);
> > > > >  	int i, j, k;
> > > > >
> > > > >  	intel_lt_phy_write(encoder, owned_lane_mask,
> > > LT_PHY_VDR_0_CONFIG,
> > > > > -			   crtc_state->dpll_hw_state.ltpll.config[0],
> > > MB_WRITE_COMMITTED);
> > > > > +			   ltpll->config[0], MB_WRITE_COMMITTED);
> > > > >  	intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0,
> > > LT_PHY_VDR_1_CONFIG,
> > > > > -			   crtc_state->dpll_hw_state.ltpll.config[1],
> > > MB_WRITE_COMMITTED);
> > > > > +			   ltpll->config[1], MB_WRITE_COMMITTED);
> > > > >  	intel_lt_phy_write(encoder, owned_lane_mask,
> > > LT_PHY_VDR_2_CONFIG,
> > > > > -			   crtc_state->dpll_hw_state.ltpll.config[2],
> > > MB_WRITE_COMMITTED);
> > > > > +			   ltpll->config[2], MB_WRITE_COMMITTED);
> > > > >
> > > > >  	for (i = 0; i <= 12; i++) {
> > > > >  		intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0,
> > > LT_PHY_VDR_X_ADDR_MSB(i),
> > > > > -				   crtc_state->dpll_hw_state.ltpll.addr_msb[i],
> > > > > +				   ltpll->addr_msb[i],
> > > > >  				   MB_WRITE_COMMITTED);
> > > > >  		intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0,
> > > LT_PHY_VDR_X_ADDR_LSB(i),
> > > > > -				   crtc_state->dpll_hw_state.ltpll.addr_lsb[i],
> > > > > +				   ltpll->addr_lsb[i],
> > > > >  				   MB_WRITE_COMMITTED);
> > > > >
> > > > >  		for (j = 3, k = 0; j >= 0; j--, k++)
> > > > >  			intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0,
> > > > >  					   LT_PHY_VDR_X_DATAY(i, j),
> > > > > -					   crtc_state-
> > > >dpll_hw_state.ltpll.data[i][k],
> > > > > +					   ltpll->data[i][k],
> > > > >  					   MB_WRITE_COMMITTED);
> > > > >  	}
> > > > >  }
> > > > >
> > > > >  static void
> > > > >  intel_lt_phy_enable_disable_tx(struct intel_encoder *encoder,
> > > > > -			       const struct intel_crtc_state *crtc_state)
> > > > > +			       const struct intel_lt_phy_pll_state *ltpll,
> > > > > +			       u8 lane_count)
> > > > >  {
> > > > >  	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> > > > >  	bool lane_reversal = dig_port->lane_reversal;
> > > > > -	u8 lane_count = crtc_state->lane_count;
> > > > >  	bool is_dp_alt =
> > > > >  		intel_tc_port_in_dp_alt_mode(dig_port);
> > > > >  	enum intel_tc_pin_assignment tc_pin = @@ -1895,7 +1899,8 @@
> > > void
> > > > > intel_lt_phy_pll_enable(struct intel_encoder *encoder,
> > > > >  	intel_lt_phy_lane_reset(encoder, crtc_state->lane_count);
> > > > >
> > > > >  	/* 2. Program PORT_CLOCK_CTL register to configure clock
> > > > > muxes,
> > > gating, and SSC. */
> > > > > -	intel_lt_phy_program_port_clock_ctl(encoder, crtc_state,
> > > lane_reversal);
> > > > > +	intel_lt_phy_program_port_clock_ctl(encoder, &crtc_state-
> > > >dpll_hw_state.ltpll,
> > > > > +					    crtc_state->port_clock,
> > > lane_reversal);
> > > > >
> > > > >  	/* 3. Change owned PHY lanes power to Ready state. */
> > > > >  	intel_lt_phy_powerdown_change_sequence(encoder,
> > > owned_lane_mask,
> > > > > @@
> > > > > -1905,12 +1910,12 @@ void intel_lt_phy_pll_enable(struct
> > > > > intel_encoder
> > > *encoder,
> > > > >  	 * 4. Read the PHY message bus VDR register PHY_VDR_0_Config
> > > check enabled PLL type,
> > > > >  	 * encoded rate and encoded mode.
> > > > >  	 */
> > > > > -	if (intel_lt_phy_config_changed(encoder, crtc_state)) {
> > > > > +	if (intel_lt_phy_config_changed(encoder,
> > > > > +&crtc_state->dpll_hw_state.ltpll)) {
> > > > >  		/*
> > > > >  		 * 5. Program the PHY internal PLL registers over PHY
> > > message bus for the desired
> > > > >  		 * frequency and protocol type
> > > > >  		 */
> > > > > -		intel_lt_phy_program_pll(encoder, crtc_state);
> > > > > +		intel_lt_phy_program_pll(encoder,
> > > > > +&crtc_state->dpll_hw_state.ltpll);
> > > > >
> > > > >  		/* 6. Use the P2P transaction flow */
> > > > >  		/*
> > > > > @@ -2001,7 +2006,8 @@ void intel_lt_phy_pll_enable(struct
> > > intel_encoder *encoder,
> > > > >  	intel_lt_phy_powerdown_change_sequence(encoder,
> > > owned_lane_mask,
> > > > >  					       XELPDP_P0_STATE_ACTIVE);
> > > > >
> > > > > -	intel_lt_phy_enable_disable_tx(encoder, crtc_state);
> > > > > +	intel_lt_phy_enable_disable_tx(encoder, &crtc_state-
> > > >dpll_hw_state.ltpll,
> > > > > +				       crtc_state->lane_count);
> > > > >  	intel_lt_phy_transaction_end(encoder, wakeref);  }
> > > > >
> > > > > --
> > > > > 2.43.0
> > > > >

[PATCH v3 03/24] drm/i915/lt_phy: Refactor LT PHY PLL handling to use explicit PLL state

[Mika Kahola]

The LT PHY implementation currently pulls PLL and port_clock
information directly from the CRTC state. This ties the PHY
programming logic too tightly to the CRTC state and makes it
harder to clearly express the PHY’s own PLL configuration.

Introduce an explicit "struct intel_lt_phy_pll_state" argument
for the PHY functions and update callers accordingly.

No functional change is intended — this is a preparatory cleanup for
to bring LT PHY PLL handling as part of PLL framework.

v2:  DP, HDMI 2.0, and HDMI FRL modes are port of the VDR configuration 0
    register. These modes are defined by bits 2:0. Decode these to
    differentiate DP and HDMI modes when programming PLL's. (Imre, Suraj)

BSpec: 744921

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_lt_phy.c | 67 ++++++++++++++-------
 1 file changed, 46 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index f173d1788af8..06d83282c495 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -33,6 +33,7 @@
 #define PCLK_PLL_ACK_LN0		REG_BIT(30)
 #define MODE_DP				3
 #define MODE_HDMI_20			4
+#define MODE_HDMI_FRL			5
 #define Q32_TO_INT(x)	((x) >> 32)
 #define Q32_TO_FRAC(x)	((x) & 0xFFFFFFFF)
 #define DCO_MIN_FREQ_MHZ	11850
@@ -1177,9 +1178,30 @@ intel_lt_phy_lane_reset(struct intel_encoder *encoder,
 	intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), lane_phy_pulse_status, 0);
 }
 
+static bool intel_lt_phy_is_hdmi(const struct intel_lt_phy_pll_state *ltpll)
+{
+	u8 mode = REG_FIELD_GET8(LT_PHY_VDR_MODE_ENCODING_MASK, ltpll->config[0]);
+
+	if (mode == MODE_HDMI_20 || mode == MODE_HDMI_FRL)
+		return true;
+
+	return false;
+}
+
+static bool intel_lt_phy_is_dp(const struct intel_lt_phy_pll_state *ltpll)
+{
+	u8 mode = REG_FIELD_GET8(LT_PHY_VDR_MODE_ENCODING_MASK, ltpll->config[0]);
+
+	if (mode == MODE_DP)
+		return true;
+
+	return false;
+}
+
 static void
 intel_lt_phy_program_port_clock_ctl(struct intel_encoder *encoder,
-				    const struct intel_crtc_state *crtc_state,
+				    const struct intel_lt_phy_pll_state *ltpll,
+				    int port_clock,
 				    bool lane_reversal)
 {
 	struct intel_display *display = to_intel_display(encoder);
@@ -1196,17 +1218,16 @@ intel_lt_phy_program_port_clock_ctl(struct intel_encoder *encoder,
 	 * but since the register bits still remain the same we use
 	 * the same definition
 	 */
-	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
-	    intel_hdmi_is_frl(crtc_state->port_clock))
+	if (intel_lt_phy_is_hdmi(ltpll) && intel_hdmi_is_frl(port_clock))
 		val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_DIV18CLK);
 	else
 		val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_MAXPCLK);
 
 	 /* DP2.0 10G and 20G rates enable MPLLA*/
-	if (crtc_state->port_clock == 1000000 || crtc_state->port_clock == 2000000)
+	if (port_clock == 1000000 || port_clock == 2000000)
 		val |= XELPDP_SSC_ENABLE_PLLA;
 	else
-		val |= crtc_state->dpll_hw_state.ltpll.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
+		val |= ltpll->ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
 
 	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
 		     XELPDP_LANE1_PHY_CLOCK_SELECT | XELPDP_FORWARD_CLOCK_UNGATE |
@@ -1249,10 +1270,12 @@ static u32 intel_lt_phy_get_dp_clock(u8 rate)
 
 static bool
 intel_lt_phy_config_changed(struct intel_encoder *encoder,
-			    const struct intel_crtc_state *crtc_state)
+			    const struct intel_lt_phy_pll_state *ltpll)
 {
+	struct intel_display *display = to_intel_display(encoder);
 	u8 val, rate;
 	u32 clock;
+	u32 port_clock = intel_lt_phy_calc_port_clock(display, ltpll);
 
 	val = intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0,
 				LT_PHY_VDR_0_CONFIG);
@@ -1263,9 +1286,9 @@ intel_lt_phy_config_changed(struct intel_encoder *encoder,
 	 * using 1.62 Gbps clock since PHY PLL defaults to that
 	 * otherwise we always need to reconfigure it.
 	 */
-	if (intel_crtc_has_dp_encoder(crtc_state)) {
+	if (intel_lt_phy_is_dp(ltpll)) {
 		clock = intel_lt_phy_get_dp_clock(rate);
-		if (crtc_state->port_clock == 1620000 && crtc_state->port_clock == clock)
+		if (port_clock == 1620000 && port_clock == clock)
 			return false;
 	}
 
@@ -1760,41 +1783,41 @@ intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
 
 static void
 intel_lt_phy_program_pll(struct intel_encoder *encoder,
-			 const struct intel_crtc_state *crtc_state)
+			 const struct intel_lt_phy_pll_state *ltpll)
 {
 	u8 owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder);
 	int i, j, k;
 
 	intel_lt_phy_write(encoder, owned_lane_mask, LT_PHY_VDR_0_CONFIG,
-			   crtc_state->dpll_hw_state.ltpll.config[0], MB_WRITE_COMMITTED);
+			   ltpll->config[0], MB_WRITE_COMMITTED);
 	intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_VDR_1_CONFIG,
-			   crtc_state->dpll_hw_state.ltpll.config[1], MB_WRITE_COMMITTED);
+			   ltpll->config[1], MB_WRITE_COMMITTED);
 	intel_lt_phy_write(encoder, owned_lane_mask, LT_PHY_VDR_2_CONFIG,
-			   crtc_state->dpll_hw_state.ltpll.config[2], MB_WRITE_COMMITTED);
+			   ltpll->config[2], MB_WRITE_COMMITTED);
 
 	for (i = 0; i <= 12; i++) {
 		intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_VDR_X_ADDR_MSB(i),
-				   crtc_state->dpll_hw_state.ltpll.addr_msb[i],
+				   ltpll->addr_msb[i],
 				   MB_WRITE_COMMITTED);
 		intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_VDR_X_ADDR_LSB(i),
-				   crtc_state->dpll_hw_state.ltpll.addr_lsb[i],
+				   ltpll->addr_lsb[i],
 				   MB_WRITE_COMMITTED);
 
 		for (j = 3, k = 0; j >= 0; j--, k++)
 			intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0,
 					   LT_PHY_VDR_X_DATAY(i, j),
-					   crtc_state->dpll_hw_state.ltpll.data[i][k],
+					   ltpll->data[i][k],
 					   MB_WRITE_COMMITTED);
 	}
 }
 
 static void
 intel_lt_phy_enable_disable_tx(struct intel_encoder *encoder,
-			       const struct intel_crtc_state *crtc_state)
+			       const struct intel_lt_phy_pll_state *ltpll,
+			       u8 lane_count)
 {
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 	bool lane_reversal = dig_port->lane_reversal;
-	u8 lane_count = crtc_state->lane_count;
 	bool is_dp_alt =
 		intel_tc_port_in_dp_alt_mode(dig_port);
 	enum intel_tc_pin_assignment tc_pin =
@@ -1896,7 +1919,8 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
 	intel_lt_phy_lane_reset(encoder, crtc_state->lane_count);
 
 	/* 2. Program PORT_CLOCK_CTL register to configure clock muxes, gating, and SSC. */
-	intel_lt_phy_program_port_clock_ctl(encoder, crtc_state, lane_reversal);
+	intel_lt_phy_program_port_clock_ctl(encoder, &crtc_state->dpll_hw_state.ltpll,
+					    crtc_state->port_clock, lane_reversal);
 
 	/* 3. Change owned PHY lanes power to Ready state. */
 	intel_lt_phy_powerdown_change_sequence(encoder, owned_lane_mask,
@@ -1906,12 +1930,12 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
 	 * 4. Read the PHY message bus VDR register PHY_VDR_0_Config check enabled PLL type,
 	 * encoded rate and encoded mode.
 	 */
-	if (intel_lt_phy_config_changed(encoder, crtc_state)) {
+	if (intel_lt_phy_config_changed(encoder, &crtc_state->dpll_hw_state.ltpll)) {
 		/*
 		 * 5. Program the PHY internal PLL registers over PHY message bus for the desired
 		 * frequency and protocol type
 		 */
-		intel_lt_phy_program_pll(encoder, crtc_state);
+		intel_lt_phy_program_pll(encoder, &crtc_state->dpll_hw_state.ltpll);
 
 		/* 6. Use the P2P transaction flow */
 		/*
@@ -2002,7 +2026,8 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
 	intel_lt_phy_powerdown_change_sequence(encoder, owned_lane_mask,
 					       XELPDP_P0_STATE_ACTIVE);
 
-	intel_lt_phy_enable_disable_tx(encoder, crtc_state);
+	intel_lt_phy_enable_disable_tx(encoder, &crtc_state->dpll_hw_state.ltpll,
+				       crtc_state->lane_count);
 	intel_lt_phy_transaction_end(encoder, wakeref);
 }
 
-- 
2.43.0

[PATCH v3 04/24] drm/i915/lt_phy: Refactor LT PHY PLL handling to use explicit PLL state

[Mika Kahola]

The LT PHY implementation currently pulls PLL and port_clock
information directly from the CRTC state. This ties the PHY
programming logic too tightly to the CRTC state and makes it
harder to clearly express the PHY’s own PLL configuration.

Introduce an explicit "struct intel_lt_phy_pll_state" argument
for the PHY functions and update callers accordingly.

No functional change is intended — this is a preparatory cleanup for
to bring LT PHY PLL handling as part of PLL framework.

v2:  DP, HDMI 2.0, and HDMI FRL modes are port of the VDR configuration 0
    register. These modes are defined by bits 2:0. Decode these to
    differentiate DP and HDMI modes when programming PLL's. (Imre, Suraj)

BSpec: 744921

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_lt_phy.c | 67 ++++++++++++++-------
 1 file changed, 46 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 8fe61cfdb706..76acffb2e840 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -32,6 +32,7 @@
 					 INTEL_LT_PHY_LANE0)
 #define MODE_DP				3
 #define MODE_HDMI_20			4
+#define MODE_HDMI_FRL			5
 #define Q32_TO_INT(x)	((x) >> 32)
 #define Q32_TO_FRAC(x)	((x) & 0xFFFFFFFF)
 #define DCO_MIN_FREQ_MHZ	11850
@@ -1176,9 +1177,30 @@ intel_lt_phy_lane_reset(struct intel_encoder *encoder,
 	intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), lane_phy_pulse_status, 0);
 }
 
+static bool intel_lt_phy_is_hdmi(const struct intel_lt_phy_pll_state *ltpll)
+{
+	u8 mode = REG_FIELD_GET8(LT_PHY_VDR_MODE_ENCODING_MASK, ltpll->config[0]);
+
+	if (mode == MODE_HDMI_20 || mode == MODE_HDMI_FRL)
+		return true;
+
+	return false;
+}
+
+static bool intel_lt_phy_is_dp(const struct intel_lt_phy_pll_state *ltpll)
+{
+	u8 mode = REG_FIELD_GET8(LT_PHY_VDR_MODE_ENCODING_MASK, ltpll->config[0]);
+
+	if (mode == MODE_DP)
+		return true;
+
+	return false;
+}
+
 static void
 intel_lt_phy_program_port_clock_ctl(struct intel_encoder *encoder,
-				    const struct intel_crtc_state *crtc_state,
+				    const struct intel_lt_phy_pll_state *ltpll,
+				    int port_clock,
 				    bool lane_reversal)
 {
 	struct intel_display *display = to_intel_display(encoder);
@@ -1195,17 +1217,16 @@ intel_lt_phy_program_port_clock_ctl(struct intel_encoder *encoder,
 	 * but since the register bits still remain the same we use
 	 * the same definition
 	 */
-	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
-	    intel_hdmi_is_frl(crtc_state->port_clock))
+	if (intel_lt_phy_is_hdmi(ltpll) && intel_hdmi_is_frl(port_clock))
 		val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_DIV18CLK);
 	else
 		val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_MAXPCLK);
 
 	 /* DP2.0 10G and 20G rates enable MPLLA*/
-	if (crtc_state->port_clock == 1000000 || crtc_state->port_clock == 2000000)
+	if (port_clock == 1000000 || port_clock == 2000000)
 		val |= XELPDP_SSC_ENABLE_PLLA;
 	else
-		val |= crtc_state->dpll_hw_state.ltpll.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
+		val |= ltpll->ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
 
 	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
 		     XELPDP_LANE1_PHY_CLOCK_SELECT | XELPDP_FORWARD_CLOCK_UNGATE |
@@ -1248,10 +1269,12 @@ static u32 intel_lt_phy_get_dp_clock(u8 rate)
 
 static bool
 intel_lt_phy_config_changed(struct intel_encoder *encoder,
-			    const struct intel_crtc_state *crtc_state)
+			    const struct intel_lt_phy_pll_state *ltpll)
 {
+	struct intel_display *display = to_intel_display(encoder);
 	u8 val, rate;
 	u32 clock;
+	u32 port_clock = intel_lt_phy_calc_port_clock(display, ltpll);
 
 	val = intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0,
 				LT_PHY_VDR_0_CONFIG);
@@ -1262,9 +1285,9 @@ intel_lt_phy_config_changed(struct intel_encoder *encoder,
 	 * using 1.62 Gbps clock since PHY PLL defaults to that
 	 * otherwise we always need to reconfigure it.
 	 */
-	if (intel_crtc_has_dp_encoder(crtc_state)) {
+	if (intel_lt_phy_is_dp(ltpll)) {
 		clock = intel_lt_phy_get_dp_clock(rate);
-		if (crtc_state->port_clock == 1620000 && crtc_state->port_clock == clock)
+		if (port_clock == 1620000 && port_clock == clock)
 			return false;
 	}
 
@@ -1759,41 +1782,41 @@ intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
 
 static void
 intel_lt_phy_program_pll(struct intel_encoder *encoder,
-			 const struct intel_crtc_state *crtc_state)
+			 const struct intel_lt_phy_pll_state *ltpll)
 {
 	u8 owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder);
 	int i, j, k;
 
 	intel_lt_phy_write(encoder, owned_lane_mask, LT_PHY_VDR_0_CONFIG,
-			   crtc_state->dpll_hw_state.ltpll.config[0], MB_WRITE_COMMITTED);
+			   ltpll->config[0], MB_WRITE_COMMITTED);
 	intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_VDR_1_CONFIG,
-			   crtc_state->dpll_hw_state.ltpll.config[1], MB_WRITE_COMMITTED);
+			   ltpll->config[1], MB_WRITE_COMMITTED);
 	intel_lt_phy_write(encoder, owned_lane_mask, LT_PHY_VDR_2_CONFIG,
-			   crtc_state->dpll_hw_state.ltpll.config[2], MB_WRITE_COMMITTED);
+			   ltpll->config[2], MB_WRITE_COMMITTED);
 
 	for (i = 0; i <= 12; i++) {
 		intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_VDR_X_ADDR_MSB(i),
-				   crtc_state->dpll_hw_state.ltpll.addr_msb[i],
+				   ltpll->addr_msb[i],
 				   MB_WRITE_COMMITTED);
 		intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_VDR_X_ADDR_LSB(i),
-				   crtc_state->dpll_hw_state.ltpll.addr_lsb[i],
+				   ltpll->addr_lsb[i],
 				   MB_WRITE_COMMITTED);
 
 		for (j = 3, k = 0; j >= 0; j--, k++)
 			intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0,
 					   LT_PHY_VDR_X_DATAY(i, j),
-					   crtc_state->dpll_hw_state.ltpll.data[i][k],
+					   ltpll->data[i][k],
 					   MB_WRITE_COMMITTED);
 	}
 }
 
 static void
 intel_lt_phy_enable_disable_tx(struct intel_encoder *encoder,
-			       const struct intel_crtc_state *crtc_state)
+			       const struct intel_lt_phy_pll_state *ltpll,
+			       u8 lane_count)
 {
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 	bool lane_reversal = dig_port->lane_reversal;
-	u8 lane_count = crtc_state->lane_count;
 	bool is_dp_alt =
 		intel_tc_port_in_dp_alt_mode(dig_port);
 	enum intel_tc_pin_assignment tc_pin =
@@ -1895,7 +1918,8 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
 	intel_lt_phy_lane_reset(encoder, crtc_state->lane_count);
 
 	/* 2. Program PORT_CLOCK_CTL register to configure clock muxes, gating, and SSC. */
-	intel_lt_phy_program_port_clock_ctl(encoder, crtc_state, lane_reversal);
+	intel_lt_phy_program_port_clock_ctl(encoder, &crtc_state->dpll_hw_state.ltpll,
+					    crtc_state->port_clock, lane_reversal);
 
 	/* 3. Change owned PHY lanes power to Ready state. */
 	intel_lt_phy_powerdown_change_sequence(encoder, owned_lane_mask,
@@ -1905,12 +1929,12 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
 	 * 4. Read the PHY message bus VDR register PHY_VDR_0_Config check enabled PLL type,
 	 * encoded rate and encoded mode.
 	 */
-	if (intel_lt_phy_config_changed(encoder, crtc_state)) {
+	if (intel_lt_phy_config_changed(encoder, &crtc_state->dpll_hw_state.ltpll)) {
 		/*
 		 * 5. Program the PHY internal PLL registers over PHY message bus for the desired
 		 * frequency and protocol type
 		 */
-		intel_lt_phy_program_pll(encoder, crtc_state);
+		intel_lt_phy_program_pll(encoder, &crtc_state->dpll_hw_state.ltpll);
 
 		/* 6. Use the P2P transaction flow */
 		/*
@@ -2001,7 +2025,8 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
 	intel_lt_phy_powerdown_change_sequence(encoder, owned_lane_mask,
 					       XELPDP_P0_STATE_ACTIVE);
 
-	intel_lt_phy_enable_disable_tx(encoder, crtc_state);
+	intel_lt_phy_enable_disable_tx(encoder, &crtc_state->dpll_hw_state.ltpll,
+				       crtc_state->lane_count);
 	intel_lt_phy_transaction_end(encoder, wakeref);
 }
 
-- 
2.43.0

RE: [PATCH v3 04/24] drm/i915/lt_phy: Refactor LT PHY PLL handling to use explicit PLL state

[Kandpal, Suraj]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Mika
> Kahola
> Sent: Tuesday, March 10, 2026 9:08 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Kahola, Mika <mika.kahola@intel.com>
> Subject: [PATCH v3 04/24] drm/i915/lt_phy: Refactor LT PHY PLL handling to use
> explicit PLL state
> 
> The LT PHY implementation currently pulls PLL and port_clock information
> directly from the CRTC state. This ties the PHY programming logic too tightly to
> the CRTC state and makes it harder to clearly express the PHY’s own PLL
> configuration.
> 
> Introduce an explicit "struct intel_lt_phy_pll_state" argument for the PHY
> functions and update callers accordingly.
> 
> No functional change is intended — this is a preparatory cleanup for to bring LT
> PHY PLL handling as part of PLL framework.
> 
> v2:  DP, HDMI 2.0, and HDMI FRL modes are port of the VDR configuration 0
>     register. These modes are defined by bits 2:0. Decode these to
>     differentiate DP and HDMI modes when programming PLL's. (Imre, Suraj)
> 
> BSpec: 744921

No new line needed here

> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_lt_phy.c | 67 ++++++++++++++-------
>  1 file changed, 46 insertions(+), 21 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index 8fe61cfdb706..76acffb2e840 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -32,6 +32,7 @@
>  					 INTEL_LT_PHY_LANE0)
>  #define MODE_DP				3
>  #define MODE_HDMI_20			4
> +#define MODE_HDMI_FRL			5
>  #define Q32_TO_INT(x)	((x) >> 32)
>  #define Q32_TO_FRAC(x)	((x) & 0xFFFFFFFF)
>  #define DCO_MIN_FREQ_MHZ	11850
> @@ -1176,9 +1177,30 @@ intel_lt_phy_lane_reset(struct intel_encoder
> *encoder,
>  	intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
> lane_phy_pulse_status, 0);  }
> 
> +static bool intel_lt_phy_is_hdmi(const struct intel_lt_phy_pll_state
> +*ltpll) {
> +	u8 mode = REG_FIELD_GET8(LT_PHY_VDR_MODE_ENCODING_MASK,
> +ltpll->config[0]);
> +
> +	if (mode == MODE_HDMI_20 || mode == MODE_HDMI_FRL)
> +		return true;
> +
> +	return false;
> +}
> +
> +static bool intel_lt_phy_is_dp(const struct intel_lt_phy_pll_state
> +*ltpll) {
> +	u8 mode = REG_FIELD_GET8(LT_PHY_VDR_MODE_ENCODING_MASK,
> +ltpll->config[0]);
> +
> +	if (mode == MODE_DP)
> +		return true;
> +
> +	return false;
> +}
> +
>  static void
>  intel_lt_phy_program_port_clock_ctl(struct intel_encoder *encoder,
> -				    const struct intel_crtc_state *crtc_state,
> +				    const struct intel_lt_phy_pll_state *ltpll,
> +				    int port_clock,
>  				    bool lane_reversal)
>  {
>  	struct intel_display *display = to_intel_display(encoder); @@ -1195,17
> +1217,16 @@ intel_lt_phy_program_port_clock_ctl(struct intel_encoder
> *encoder,
>  	 * but since the register bits still remain the same we use
>  	 * the same definition
>  	 */
> -	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
> -	    intel_hdmi_is_frl(crtc_state->port_clock))
> +	if (intel_lt_phy_is_hdmi(ltpll) && intel_hdmi_is_frl(port_clock))
>  		val |= XELPDP_DDI_CLOCK_SELECT_PREP(display,
> XELPDP_DDI_CLOCK_SELECT_DIV18CLK);
>  	else
>  		val |= XELPDP_DDI_CLOCK_SELECT_PREP(display,
> XELPDP_DDI_CLOCK_SELECT_MAXPCLK);
> 
>  	 /* DP2.0 10G and 20G rates enable MPLLA*/
> -	if (crtc_state->port_clock == 1000000 || crtc_state->port_clock ==
> 2000000)
> +	if (port_clock == 1000000 || port_clock == 2000000)
>  		val |= XELPDP_SSC_ENABLE_PLLA;
>  	else
> -		val |= crtc_state->dpll_hw_state.ltpll.ssc_enabled ?
> XELPDP_SSC_ENABLE_PLLB : 0;
> +		val |= ltpll->ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
> 
>  	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder-
> >port),
>  		     XELPDP_LANE1_PHY_CLOCK_SELECT |
> XELPDP_FORWARD_CLOCK_UNGATE | @@ -1248,10 +1269,12 @@ static u32
> intel_lt_phy_get_dp_clock(u8 rate)
> 
>  static bool
>  intel_lt_phy_config_changed(struct intel_encoder *encoder,
> -			    const struct intel_crtc_state *crtc_state)
> +			    const struct intel_lt_phy_pll_state *ltpll)

Why are we changing this?

>  {
> +	struct intel_display *display = to_intel_display(encoder);
>  	u8 val, rate;
>  	u32 clock;
> +	u32 port_clock = intel_lt_phy_calc_port_clock(display, ltpll);

No need to have this recalculated again
If we really want to change the arguments to send ltpll state
Then I recommend sending the crtc_state->port_clock as an argument

Otherwise rest looks good to me here

Regards,
Suraj Kandpal
 
> 
>  	val = intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0,
>  				LT_PHY_VDR_0_CONFIG);
> @@ -1262,9 +1285,9 @@ intel_lt_phy_config_changed(struct intel_encoder
> *encoder,
>  	 * using 1.62 Gbps clock since PHY PLL defaults to that
>  	 * otherwise we always need to reconfigure it.
>  	 */
> -	if (intel_crtc_has_dp_encoder(crtc_state)) {
> +	if (intel_lt_phy_is_dp(ltpll)) {
>  		clock = intel_lt_phy_get_dp_clock(rate);
> -		if (crtc_state->port_clock == 1620000 && crtc_state-
> >port_clock == clock)
> +		if (port_clock == 1620000 && port_clock == clock)
>  			return false;
>  	}
> 
> @@ -1759,41 +1782,41 @@ intel_lt_phy_pll_calc_state(struct intel_crtc_state
> *crtc_state,
> 
>  static void
>  intel_lt_phy_program_pll(struct intel_encoder *encoder,
> -			 const struct intel_crtc_state *crtc_state)
> +			 const struct intel_lt_phy_pll_state *ltpll)
>  {
>  	u8 owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder);
>  	int i, j, k;
> 
>  	intel_lt_phy_write(encoder, owned_lane_mask,
> LT_PHY_VDR_0_CONFIG,
> -			   crtc_state->dpll_hw_state.ltpll.config[0],
> MB_WRITE_COMMITTED);
> +			   ltpll->config[0], MB_WRITE_COMMITTED);
>  	intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0,
> LT_PHY_VDR_1_CONFIG,
> -			   crtc_state->dpll_hw_state.ltpll.config[1],
> MB_WRITE_COMMITTED);
> +			   ltpll->config[1], MB_WRITE_COMMITTED);
>  	intel_lt_phy_write(encoder, owned_lane_mask,
> LT_PHY_VDR_2_CONFIG,
> -			   crtc_state->dpll_hw_state.ltpll.config[2],
> MB_WRITE_COMMITTED);
> +			   ltpll->config[2], MB_WRITE_COMMITTED);
> 
>  	for (i = 0; i <= 12; i++) {
>  		intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0,
> LT_PHY_VDR_X_ADDR_MSB(i),
> -				   crtc_state->dpll_hw_state.ltpll.addr_msb[i],
> +				   ltpll->addr_msb[i],
>  				   MB_WRITE_COMMITTED);
>  		intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0,
> LT_PHY_VDR_X_ADDR_LSB(i),
> -				   crtc_state->dpll_hw_state.ltpll.addr_lsb[i],
> +				   ltpll->addr_lsb[i],
>  				   MB_WRITE_COMMITTED);
> 
>  		for (j = 3, k = 0; j >= 0; j--, k++)
>  			intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0,
>  					   LT_PHY_VDR_X_DATAY(i, j),
> -					   crtc_state-
> >dpll_hw_state.ltpll.data[i][k],
> +					   ltpll->data[i][k],
>  					   MB_WRITE_COMMITTED);
>  	}
>  }
> 
>  static void
>  intel_lt_phy_enable_disable_tx(struct intel_encoder *encoder,
> -			       const struct intel_crtc_state *crtc_state)
> +			       const struct intel_lt_phy_pll_state *ltpll,
> +			       u8 lane_count)
>  {
>  	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>  	bool lane_reversal = dig_port->lane_reversal;
> -	u8 lane_count = crtc_state->lane_count;
>  	bool is_dp_alt =
>  		intel_tc_port_in_dp_alt_mode(dig_port);
>  	enum intel_tc_pin_assignment tc_pin =
> @@ -1895,7 +1918,8 @@ void intel_lt_phy_pll_enable(struct intel_encoder
> *encoder,
>  	intel_lt_phy_lane_reset(encoder, crtc_state->lane_count);
> 
>  	/* 2. Program PORT_CLOCK_CTL register to configure clock muxes,
> gating, and SSC. */
> -	intel_lt_phy_program_port_clock_ctl(encoder, crtc_state,
> lane_reversal);
> +	intel_lt_phy_program_port_clock_ctl(encoder, &crtc_state-
> >dpll_hw_state.ltpll,
> +					    crtc_state->port_clock,
> lane_reversal);
> 
>  	/* 3. Change owned PHY lanes power to Ready state. */
>  	intel_lt_phy_powerdown_change_sequence(encoder,
> owned_lane_mask, @@ -1905,12 +1929,12 @@ void
> intel_lt_phy_pll_enable(struct intel_encoder *encoder,
>  	 * 4. Read the PHY message bus VDR register PHY_VDR_0_Config check
> enabled PLL type,
>  	 * encoded rate and encoded mode.
>  	 */
> -	if (intel_lt_phy_config_changed(encoder, crtc_state)) {
> +	if (intel_lt_phy_config_changed(encoder,
> +&crtc_state->dpll_hw_state.ltpll)) {
>  		/*
>  		 * 5. Program the PHY internal PLL registers over PHY message
> bus for the desired
>  		 * frequency and protocol type
>  		 */
> -		intel_lt_phy_program_pll(encoder, crtc_state);
> +		intel_lt_phy_program_pll(encoder, &crtc_state-
> >dpll_hw_state.ltpll);
> 
>  		/* 6. Use the P2P transaction flow */
>  		/*
> @@ -2001,7 +2025,8 @@ void intel_lt_phy_pll_enable(struct intel_encoder
> *encoder,
>  	intel_lt_phy_powerdown_change_sequence(encoder,
> owned_lane_mask,
>  					       XELPDP_P0_STATE_ACTIVE);
> 
> -	intel_lt_phy_enable_disable_tx(encoder, crtc_state);
> +	intel_lt_phy_enable_disable_tx(encoder, &crtc_state-
> >dpll_hw_state.ltpll,
> +				       crtc_state->lane_count);
>  	intel_lt_phy_transaction_end(encoder, wakeref);  }
> 
> --
> 2.43.0

RE: [PATCH v3 04/24] drm/i915/lt_phy: Refactor LT PHY PLL handling to use explicit PLL state

[Kandpal, Suraj]

> > Subject: [PATCH v3 04/24] drm/i915/lt_phy: Refactor LT PHY PLL
> > handling to use explicit PLL state
> >
> > The LT PHY implementation currently pulls PLL and port_clock
> > information directly from the CRTC state. This ties the PHY
> > programming logic too tightly to the CRTC state and makes it harder to
> > clearly express the PHY’s own PLL configuration.
> >
> > Introduce an explicit "struct intel_lt_phy_pll_state" argument for the
> > PHY functions and update callers accordingly.
> >
> > No functional change is intended — this is a preparatory cleanup for
> > to bring LT PHY PLL handling as part of PLL framework.
> >
> > v2:  DP, HDMI 2.0, and HDMI FRL modes are port of the VDR configuration 0
> >     register. These modes are defined by bits 2:0. Decode these to
> >     differentiate DP and HDMI modes when programming PLL's. (Imre,
> > Suraj)
> >
> > BSpec: 744921
> 
> No new line needed here
> 
> >
> > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_lt_phy.c | 67
> > ++++++++++++++-------
> >  1 file changed, 46 insertions(+), 21 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > index 8fe61cfdb706..76acffb2e840 100644
> > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > @@ -32,6 +32,7 @@
> >  					 INTEL_LT_PHY_LANE0)
> >  #define MODE_DP				3
> >  #define MODE_HDMI_20			4
> > +#define MODE_HDMI_FRL			5
> >  #define Q32_TO_INT(x)	((x) >> 32)
> >  #define Q32_TO_FRAC(x)	((x) & 0xFFFFFFFF)
> >  #define DCO_MIN_FREQ_MHZ	11850
> > @@ -1176,9 +1177,30 @@ intel_lt_phy_lane_reset(struct intel_encoder
> > *encoder,
> >  	intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
> > lane_phy_pulse_status, 0);  }
> >
> > +static bool intel_lt_phy_is_hdmi(const struct intel_lt_phy_pll_state
> > +*ltpll) {
> > +	u8 mode =
> REG_FIELD_GET8(LT_PHY_VDR_MODE_ENCODING_MASK,
> > +ltpll->config[0]);
> > +
> > +	if (mode == MODE_HDMI_20 || mode == MODE_HDMI_FRL)
> > +		return true;
> > +
> > +	return false;
> > +}
> > +
> > +static bool intel_lt_phy_is_dp(const struct intel_lt_phy_pll_state
> > +*ltpll) {
> > +	u8 mode =
> REG_FIELD_GET8(LT_PHY_VDR_MODE_ENCODING_MASK,
> > +ltpll->config[0]);
> > +
> > +	if (mode == MODE_DP)
> > +		return true;
> > +
> > +	return false;
> > +}
> > +
> >  static void
> >  intel_lt_phy_program_port_clock_ctl(struct intel_encoder *encoder,
> > -				    const struct intel_crtc_state *crtc_state,
> > +				    const struct intel_lt_phy_pll_state *ltpll,
> > +				    int port_clock,
> >  				    bool lane_reversal)
> >  {
> >  	struct intel_display *display = to_intel_display(encoder); @@
> > -1195,17
> > +1217,16 @@ intel_lt_phy_program_port_clock_ctl(struct intel_encoder
> > *encoder,
> >  	 * but since the register bits still remain the same we use
> >  	 * the same definition
> >  	 */
> > -	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
> > -	    intel_hdmi_is_frl(crtc_state->port_clock))
> > +	if (intel_lt_phy_is_hdmi(ltpll) && intel_hdmi_is_frl(port_clock))
> >  		val |= XELPDP_DDI_CLOCK_SELECT_PREP(display,
> > XELPDP_DDI_CLOCK_SELECT_DIV18CLK);
> >  	else
> >  		val |= XELPDP_DDI_CLOCK_SELECT_PREP(display,
> > XELPDP_DDI_CLOCK_SELECT_MAXPCLK);
> >
> >  	 /* DP2.0 10G and 20G rates enable MPLLA*/
> > -	if (crtc_state->port_clock == 1000000 || crtc_state->port_clock ==
> > 2000000)
> > +	if (port_clock == 1000000 || port_clock == 2000000)
> >  		val |= XELPDP_SSC_ENABLE_PLLA;
> >  	else
> > -		val |= crtc_state->dpll_hw_state.ltpll.ssc_enabled ?
> > XELPDP_SSC_ENABLE_PLLB : 0;
> > +		val |= ltpll->ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
> >
> >  	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder-
> > >port),
> >  		     XELPDP_LANE1_PHY_CLOCK_SELECT |
> XELPDP_FORWARD_CLOCK_UNGATE |
> > @@ -1248,10 +1269,12 @@ static u32
> > intel_lt_phy_get_dp_clock(u8 rate)
> >
> >  static bool
> >  intel_lt_phy_config_changed(struct intel_encoder *encoder,
> > -			    const struct intel_crtc_state *crtc_state)
> > +			    const struct intel_lt_phy_pll_state *ltpll)
> 
> Why are we changing this?
> 
> >  {
> > +	struct intel_display *display = to_intel_display(encoder);
> >  	u8 val, rate;
> >  	u32 clock;
> > +	u32 port_clock = intel_lt_phy_calc_port_clock(display, ltpll);
> 
> No need to have this recalculated again
> If we really want to change the arguments to send ltpll state Then I
> recommend sending the crtc_state->port_clock as an argument

Had a look at this part seems like you need it in later patches when you switch to the dpll framework since
Crtc_state is not available so then it makes sense to recalculate.

But please move the calculation right after intel_display declaration.

Regards,
Suraj Kandpal

> 
> Otherwise rest looks good to me here
> 
> Regards,
> Suraj Kandpal
> 
> >
> >  	val = intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0,
> >  				LT_PHY_VDR_0_CONFIG);
> > @@ -1262,9 +1285,9 @@ intel_lt_phy_config_changed(struct
> intel_encoder
> > *encoder,
> >  	 * using 1.62 Gbps clock since PHY PLL defaults to that
> >  	 * otherwise we always need to reconfigure it.
> >  	 */
> > -	if (intel_crtc_has_dp_encoder(crtc_state)) {
> > +	if (intel_lt_phy_is_dp(ltpll)) {
> >  		clock = intel_lt_phy_get_dp_clock(rate);
> > -		if (crtc_state->port_clock == 1620000 && crtc_state-
> > >port_clock == clock)
> > +		if (port_clock == 1620000 && port_clock == clock)
> >  			return false;
> >  	}
> >
> > @@ -1759,41 +1782,41 @@ intel_lt_phy_pll_calc_state(struct
> > intel_crtc_state *crtc_state,
> >
> >  static void
> >  intel_lt_phy_program_pll(struct intel_encoder *encoder,
> > -			 const struct intel_crtc_state *crtc_state)
> > +			 const struct intel_lt_phy_pll_state *ltpll)
> >  {
> >  	u8 owned_lane_mask =
> intel_lt_phy_get_owned_lane_mask(encoder);
> >  	int i, j, k;
> >
> >  	intel_lt_phy_write(encoder, owned_lane_mask,
> LT_PHY_VDR_0_CONFIG,
> > -			   crtc_state->dpll_hw_state.ltpll.config[0],
> > MB_WRITE_COMMITTED);
> > +			   ltpll->config[0], MB_WRITE_COMMITTED);
> >  	intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0,
> LT_PHY_VDR_1_CONFIG,
> > -			   crtc_state->dpll_hw_state.ltpll.config[1],
> > MB_WRITE_COMMITTED);
> > +			   ltpll->config[1], MB_WRITE_COMMITTED);
> >  	intel_lt_phy_write(encoder, owned_lane_mask,
> LT_PHY_VDR_2_CONFIG,
> > -			   crtc_state->dpll_hw_state.ltpll.config[2],
> > MB_WRITE_COMMITTED);
> > +			   ltpll->config[2], MB_WRITE_COMMITTED);
> >
> >  	for (i = 0; i <= 12; i++) {
> >  		intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0,
> > LT_PHY_VDR_X_ADDR_MSB(i),
> > -				   crtc_state->dpll_hw_state.ltpll.addr_msb[i],
> > +				   ltpll->addr_msb[i],
> >  				   MB_WRITE_COMMITTED);
> >  		intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0,
> > LT_PHY_VDR_X_ADDR_LSB(i),
> > -				   crtc_state->dpll_hw_state.ltpll.addr_lsb[i],
> > +				   ltpll->addr_lsb[i],
> >  				   MB_WRITE_COMMITTED);
> >
> >  		for (j = 3, k = 0; j >= 0; j--, k++)
> >  			intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0,
> >  					   LT_PHY_VDR_X_DATAY(i, j),
> > -					   crtc_state-
> > >dpll_hw_state.ltpll.data[i][k],
> > +					   ltpll->data[i][k],
> >  					   MB_WRITE_COMMITTED);
> >  	}
> >  }
> >
> >  static void
> >  intel_lt_phy_enable_disable_tx(struct intel_encoder *encoder,
> > -			       const struct intel_crtc_state *crtc_state)
> > +			       const struct intel_lt_phy_pll_state *ltpll,
> > +			       u8 lane_count)
> >  {
> >  	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> >  	bool lane_reversal = dig_port->lane_reversal;
> > -	u8 lane_count = crtc_state->lane_count;
> >  	bool is_dp_alt =
> >  		intel_tc_port_in_dp_alt_mode(dig_port);
> >  	enum intel_tc_pin_assignment tc_pin = @@ -1895,7 +1918,8 @@
> void
> > intel_lt_phy_pll_enable(struct intel_encoder *encoder,
> >  	intel_lt_phy_lane_reset(encoder, crtc_state->lane_count);
> >
> >  	/* 2. Program PORT_CLOCK_CTL register to configure clock muxes,
> > gating, and SSC. */
> > -	intel_lt_phy_program_port_clock_ctl(encoder, crtc_state,
> > lane_reversal);
> > +	intel_lt_phy_program_port_clock_ctl(encoder, &crtc_state-
> > >dpll_hw_state.ltpll,
> > +					    crtc_state->port_clock,
> > lane_reversal);
> >
> >  	/* 3. Change owned PHY lanes power to Ready state. */
> >  	intel_lt_phy_powerdown_change_sequence(encoder,
> > owned_lane_mask, @@ -1905,12 +1929,12 @@ void
> > intel_lt_phy_pll_enable(struct intel_encoder *encoder,
> >  	 * 4. Read the PHY message bus VDR register PHY_VDR_0_Config
> check
> > enabled PLL type,
> >  	 * encoded rate and encoded mode.
> >  	 */
> > -	if (intel_lt_phy_config_changed(encoder, crtc_state)) {
> > +	if (intel_lt_phy_config_changed(encoder,
> > +&crtc_state->dpll_hw_state.ltpll)) {
> >  		/*
> >  		 * 5. Program the PHY internal PLL registers over PHY
> message bus
> > for the desired
> >  		 * frequency and protocol type
> >  		 */
> > -		intel_lt_phy_program_pll(encoder, crtc_state);
> > +		intel_lt_phy_program_pll(encoder, &crtc_state-
> > >dpll_hw_state.ltpll);
> >
> >  		/* 6. Use the P2P transaction flow */
> >  		/*
> > @@ -2001,7 +2025,8 @@ void intel_lt_phy_pll_enable(struct
> > intel_encoder *encoder,
> >  	intel_lt_phy_powerdown_change_sequence(encoder,
> > owned_lane_mask,
> >  					       XELPDP_P0_STATE_ACTIVE);
> >
> > -	intel_lt_phy_enable_disable_tx(encoder, crtc_state);
> > +	intel_lt_phy_enable_disable_tx(encoder, &crtc_state-
> > >dpll_hw_state.ltpll,
> > +				       crtc_state->lane_count);
> >  	intel_lt_phy_transaction_end(encoder, wakeref);  }
> >
> > --
> > 2.43.0

Re: [PATCH v3 04/24] drm/i915/lt_phy: Refactor LT PHY PLL handling to use explicit PLL state

[Kahola, Mika]

________________________________________
From: Kandpal, Suraj <suraj.kandpal@intel.com>
Sent: Wednesday, March 11, 2026 8:15 AM
To: Kandpal, Suraj; Kahola, Mika; intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
Cc: Kahola, Mika
Subject: RE: [PATCH v3 04/24] drm/i915/lt_phy: Refactor LT PHY PLL handling to use explicit PLL state

> > Subject: [PATCH v3 04/24] drm/i915/lt_phy: Refactor LT PHY PLL
> > handling to use explicit PLL state
> >
> > The LT PHY implementation currently pulls PLL and port_clock
> > information directly from the CRTC state. This ties the PHY
> > programming logic too tightly to the CRTC state and makes it harder to
> > clearly express the PHY’s own PLL configuration.
> >
> > Introduce an explicit "struct intel_lt_phy_pll_state" argument for the
> > PHY functions and update callers accordingly.
> >
> > No functional change is intended — this is a preparatory cleanup for
> > to bring LT PHY PLL handling as part of PLL framework.
> >
> > v2:  DP, HDMI 2.0, and HDMI FRL modes are port of the VDR configuration 0
> >     register. These modes are defined by bits 2:0. Decode these to
> >     differentiate DP and HDMI modes when programming PLL's. (Imre,
> > Suraj)
> >
> > BSpec: 744921
>
> No new line needed here

Right, I will remove the new line.

>
> >
> > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_lt_phy.c | 67
> > ++++++++++++++-------
> >  1 file changed, 46 insertions(+), 21 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > index 8fe61cfdb706..76acffb2e840 100644
> > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > @@ -32,6 +32,7 @@
> >                                      INTEL_LT_PHY_LANE0)
> >  #define MODE_DP                            3
> >  #define MODE_HDMI_20                       4
> > +#define MODE_HDMI_FRL                      5
> >  #define Q32_TO_INT(x)      ((x) >> 32)
> >  #define Q32_TO_FRAC(x)     ((x) & 0xFFFFFFFF)
> >  #define DCO_MIN_FREQ_MHZ   11850
> > @@ -1176,9 +1177,30 @@ intel_lt_phy_lane_reset(struct intel_encoder
> > *encoder,
> >     intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
> > lane_phy_pulse_status, 0);  }
> >
> > +static bool intel_lt_phy_is_hdmi(const struct intel_lt_phy_pll_state
> > +*ltpll) {
> > +   u8 mode =
> REG_FIELD_GET8(LT_PHY_VDR_MODE_ENCODING_MASK,
> > +ltpll->config[0]);
> > +
> > +   if (mode == MODE_HDMI_20 || mode == MODE_HDMI_FRL)
> > +           return true;
> > +
> > +   return false;
> > +}
> > +
> > +static bool intel_lt_phy_is_dp(const struct intel_lt_phy_pll_state
> > +*ltpll) {
> > +   u8 mode =
> REG_FIELD_GET8(LT_PHY_VDR_MODE_ENCODING_MASK,
> > +ltpll->config[0]);
> > +
> > +   if (mode == MODE_DP)
> > +           return true;
> > +
> > +   return false;
> > +}
> > +
> >  static void
> >  intel_lt_phy_program_port_clock_ctl(struct intel_encoder *encoder,
> > -                               const struct intel_crtc_state *crtc_state,
> > +                               const struct intel_lt_phy_pll_state *ltpll,
> > +                               int port_clock,
> >                                 bool lane_reversal)
> >  {
> >     struct intel_display *display = to_intel_display(encoder); @@
> > -1195,17
> > +1217,16 @@ intel_lt_phy_program_port_clock_ctl(struct intel_encoder
> > *encoder,
> >      * but since the register bits still remain the same we use
> >      * the same definition
> >      */
> > -   if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
> > -       intel_hdmi_is_frl(crtc_state->port_clock))
> > +   if (intel_lt_phy_is_hdmi(ltpll) && intel_hdmi_is_frl(port_clock))
> >             val |= XELPDP_DDI_CLOCK_SELECT_PREP(display,
> > XELPDP_DDI_CLOCK_SELECT_DIV18CLK);
> >     else
> >             val |= XELPDP_DDI_CLOCK_SELECT_PREP(display,
> > XELPDP_DDI_CLOCK_SELECT_MAXPCLK);
> >
> >      /* DP2.0 10G and 20G rates enable MPLLA*/
> > -   if (crtc_state->port_clock == 1000000 || crtc_state->port_clock ==
> > 2000000)
> > +   if (port_clock == 1000000 || port_clock == 2000000)
> >             val |= XELPDP_SSC_ENABLE_PLLA;
> >     else
> > -           val |= crtc_state->dpll_hw_state.ltpll.ssc_enabled ?
> > XELPDP_SSC_ENABLE_PLLB : 0;
> > +           val |= ltpll->ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
> >
> >     intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder-
> > >port),
> >                  XELPDP_LANE1_PHY_CLOCK_SELECT |
> XELPDP_FORWARD_CLOCK_UNGATE |
> > @@ -1248,10 +1269,12 @@ static u32
> > intel_lt_phy_get_dp_clock(u8 rate)
> >
> >  static bool
> >  intel_lt_phy_config_changed(struct intel_encoder *encoder,
> > -                       const struct intel_crtc_state *crtc_state)
> > +                       const struct intel_lt_phy_pll_state *ltpll)
>
> Why are we changing this?

crtc_state is removed just that we don't need to pass around this large structure. We did similarly with the Cx0 series.

>
> >  {
> > +   struct intel_display *display = to_intel_display(encoder);
> >     u8 val, rate;
> >     u32 clock;
> > +   u32 port_clock = intel_lt_phy_calc_port_clock(display, ltpll);
>
> No need to have this recalculated again
> If we really want to change the arguments to send ltpll state Then I
> recommend sending the crtc_state->port_clock as an argument
>
> Had a look at this part seems like you need it in later patches when you switch to the dpll framework since
> Crtc_state is not available so then it makes sense to recalculate.

Port clock could still be passed as argument. Maybe that would be a cleaner solution rather than recalculate port clock. 

Thanks!

-Mika-
>
> But please move the calculation right after intel_display declaration.
>
>Regards,
>Suraj Kandpal

>
> Otherwise rest looks good to me here
>
> Regards,
> Suraj Kandpal
>
> >
> >     val = intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0,
> >                             LT_PHY_VDR_0_CONFIG);
> > @@ -1262,9 +1285,9 @@ intel_lt_phy_config_changed(struct
> intel_encoder
> > *encoder,
> >      * using 1.62 Gbps clock since PHY PLL defaults to that
> >      * otherwise we always need to reconfigure it.
> >      */
> > -   if (intel_crtc_has_dp_encoder(crtc_state)) {
> > +   if (intel_lt_phy_is_dp(ltpll)) {
> >             clock = intel_lt_phy_get_dp_clock(rate);
> > -           if (crtc_state->port_clock == 1620000 && crtc_state-
> > >port_clock == clock)
> > +           if (port_clock == 1620000 && port_clock == clock)
> >                     return false;
> >     }
> >
> > @@ -1759,41 +1782,41 @@ intel_lt_phy_pll_calc_state(struct
> > intel_crtc_state *crtc_state,
> >
> >  static void
> >  intel_lt_phy_program_pll(struct intel_encoder *encoder,
> > -                    const struct intel_crtc_state *crtc_state)
> > +                    const struct intel_lt_phy_pll_state *ltpll)
> >  {
> >     u8 owned_lane_mask =
> intel_lt_phy_get_owned_lane_mask(encoder);
> >     int i, j, k;
> >
> >     intel_lt_phy_write(encoder, owned_lane_mask,
> LT_PHY_VDR_0_CONFIG,
> > -                      crtc_state->dpll_hw_state.ltpll.config[0],
> > MB_WRITE_COMMITTED);
> > +                      ltpll->config[0], MB_WRITE_COMMITTED);
> >     intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0,
> LT_PHY_VDR_1_CONFIG,
> > -                      crtc_state->dpll_hw_state.ltpll.config[1],
> > MB_WRITE_COMMITTED);
> > +                      ltpll->config[1], MB_WRITE_COMMITTED);
> >     intel_lt_phy_write(encoder, owned_lane_mask,
> LT_PHY_VDR_2_CONFIG,
> > -                      crtc_state->dpll_hw_state.ltpll.config[2],
> > MB_WRITE_COMMITTED);
> > +                      ltpll->config[2], MB_WRITE_COMMITTED);
> >
> >     for (i = 0; i <= 12; i++) {
> >             intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0,
> > LT_PHY_VDR_X_ADDR_MSB(i),
> > -                              crtc_state->dpll_hw_state.ltpll.addr_msb[i],
> > +                              ltpll->addr_msb[i],
> >                                MB_WRITE_COMMITTED);
> >             intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0,
> > LT_PHY_VDR_X_ADDR_LSB(i),
> > -                              crtc_state->dpll_hw_state.ltpll.addr_lsb[i],
> > +                              ltpll->addr_lsb[i],
> >                                MB_WRITE_COMMITTED);
> >
> >             for (j = 3, k = 0; j >= 0; j--, k++)
> >                     intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0,
> >                                        LT_PHY_VDR_X_DATAY(i, j),
> > -                                      crtc_state-
> > >dpll_hw_state.ltpll.data[i][k],
> > +                                      ltpll->data[i][k],
> >                                        MB_WRITE_COMMITTED);
> >     }
> >  }
> >
> >  static void
> >  intel_lt_phy_enable_disable_tx(struct intel_encoder *encoder,
> > -                          const struct intel_crtc_state *crtc_state)
> > +                          const struct intel_lt_phy_pll_state *ltpll,
> > +                          u8 lane_count)
> >  {
> >     struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> >     bool lane_reversal = dig_port->lane_reversal;
> > -   u8 lane_count = crtc_state->lane_count;
> >     bool is_dp_alt =
> >             intel_tc_port_in_dp_alt_mode(dig_port);
> >     enum intel_tc_pin_assignment tc_pin = @@ -1895,7 +1918,8 @@
> void
> > intel_lt_phy_pll_enable(struct intel_encoder *encoder,
> >     intel_lt_phy_lane_reset(encoder, crtc_state->lane_count);
> >
> >     /* 2. Program PORT_CLOCK_CTL register to configure clock muxes,
> > gating, and SSC. */
> > -   intel_lt_phy_program_port_clock_ctl(encoder, crtc_state,
> > lane_reversal);
> > +   intel_lt_phy_program_port_clock_ctl(encoder, &crtc_state-
> > >dpll_hw_state.ltpll,
> > +                                       crtc_state->port_clock,
> > lane_reversal);
> >
> >     /* 3. Change owned PHY lanes power to Ready state. */
> >     intel_lt_phy_powerdown_change_sequence(encoder,
> > owned_lane_mask, @@ -1905,12 +1929,12 @@ void
> > intel_lt_phy_pll_enable(struct intel_encoder *encoder,
> >      * 4. Read the PHY message bus VDR register PHY_VDR_0_Config
> check
> > enabled PLL type,
> >      * encoded rate and encoded mode.
> >      */
> > -   if (intel_lt_phy_config_changed(encoder, crtc_state)) {
> > +   if (intel_lt_phy_config_changed(encoder,
> > +&crtc_state->dpll_hw_state.ltpll)) {
> >             /*
> >              * 5. Program the PHY internal PLL registers over PHY
> message bus
> > for the desired
> >              * frequency and protocol type
> >              */
> > -           intel_lt_phy_program_pll(encoder, crtc_state);
> > +           intel_lt_phy_program_pll(encoder, &crtc_state-
> > >dpll_hw_state.ltpll);
> >
> >             /* 6. Use the P2P transaction flow */
> >             /*
> > @@ -2001,7 +2025,8 @@ void intel_lt_phy_pll_enable(struct
> > intel_encoder *encoder,
> >     intel_lt_phy_powerdown_change_sequence(encoder,
> > owned_lane_mask,
> >                                            XELPDP_P0_STATE_ACTIVE);
> >
> > -   intel_lt_phy_enable_disable_tx(encoder, crtc_state);
> > +   intel_lt_phy_enable_disable_tx(encoder, &crtc_state-
> > >dpll_hw_state.ltpll,
> > +                                  crtc_state->lane_count);
> >     intel_lt_phy_transaction_end(encoder, wakeref);  }
> >
> > --
> > 2.43.0

[PATCH v2 05/24] drm/i915/lt_phy: Add lane_count to PLL state

[Mika Kahola]

Cache lane count as part of PLL state.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 1 +
 drivers/gpu/drm/i915/display/intel_lt_phy.c   | 9 +++++----
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 4cc14ce5eebe..d408ccf6f902 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -278,6 +278,7 @@ struct intel_lt_phy_pll_state {
 	u8 config[3];
 	bool ssc_enabled;
 	bool tbt_mode;
+	int lane_count;
 };
 
 struct intel_dpll_hw_state {
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index ebdcab58df4a..07eab4d7bcff 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -1749,11 +1749,13 @@ intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
 			}
 			crtc_state->dpll_hw_state.ltpll.ssc_enabled =
 				intel_lt_phy_pll_is_ssc_enabled(crtc_state, encoder);
+			crtc_state->dpll_hw_state.ltpll.lane_count = crtc_state->lane_count;
 			return 0;
 		}
 	}
 
 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
+		crtc_state->dpll_hw_state.ltpll.lane_count = crtc_state->lane_count;
 		return intel_lt_phy_calculate_hdmi_state(&crtc_state->dpll_hw_state.ltpll,
 							 crtc_state->port_clock);
 	}
@@ -1793,11 +1795,11 @@ intel_lt_phy_program_pll(struct intel_encoder *encoder,
 
 static void
 intel_lt_phy_enable_disable_tx(struct intel_encoder *encoder,
-			       const struct intel_lt_phy_pll_state *ltpll,
-			       u8 lane_count)
+			       const struct intel_lt_phy_pll_state *ltpll)
 {
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 	bool lane_reversal = dig_port->lane_reversal;
+	u8 lane_count = ltpll->lane_count;
 	bool is_dp_alt =
 		intel_tc_port_in_dp_alt_mode(dig_port);
 	enum intel_tc_pin_assignment tc_pin =
@@ -2006,8 +2008,7 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
 	intel_lt_phy_powerdown_change_sequence(encoder, owned_lane_mask,
 					       XELPDP_P0_STATE_ACTIVE);
 
-	intel_lt_phy_enable_disable_tx(encoder, &crtc_state->dpll_hw_state.ltpll,
-				       crtc_state->lane_count);
+	intel_lt_phy_enable_disable_tx(encoder, &crtc_state->dpll_hw_state.ltpll);
 	intel_lt_phy_transaction_end(encoder, wakeref);
 }
 
-- 
2.43.0

RE: [PATCH v2 05/24] drm/i915/lt_phy: Add lane_count to PLL state

[Kandpal, Suraj]

> Subject: [PATCH v2 05/24] drm/i915/lt_phy: Add lane_count to PLL state
> 
> Cache lane count as part of PLL state.
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 1 +
>  drivers/gpu/drm/i915/display/intel_lt_phy.c   | 9 +++++----
>  2 files changed, 6 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index 4cc14ce5eebe..d408ccf6f902 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -278,6 +278,7 @@ struct intel_lt_phy_pll_state {
>  	u8 config[3];
>  	bool ssc_enabled;
>  	bool tbt_mode;
> +	int lane_count;
>  };
> 
>  struct intel_dpll_hw_state {
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index ebdcab58df4a..07eab4d7bcff 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -1749,11 +1749,13 @@ intel_lt_phy_pll_calc_state(struct
> intel_crtc_state *crtc_state,
>  			}
>  			crtc_state->dpll_hw_state.ltpll.ssc_enabled =
>  				intel_lt_phy_pll_is_ssc_enabled(crtc_state,
> encoder);
> +			crtc_state->dpll_hw_state.ltpll.lane_count =
> crtc_state->lane_count;
>  			return 0;
>  		}
>  	}
> 
>  	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
> +		crtc_state->dpll_hw_state.ltpll.lane_count = crtc_state-
> >lane_count;
>  		return intel_lt_phy_calculate_hdmi_state(&crtc_state-
> >dpll_hw_state.ltpll,
>  							 crtc_state-
> >port_clock);
>  	}
> @@ -1793,11 +1795,11 @@ intel_lt_phy_program_pll(struct intel_encoder
> *encoder,
> 
>  static void
>  intel_lt_phy_enable_disable_tx(struct intel_encoder *encoder,
> -			       const struct intel_lt_phy_pll_state *ltpll,
> -			       u8 lane_count)
> +			       const struct intel_lt_phy_pll_state *ltpll)
>  {
>  	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>  	bool lane_reversal = dig_port->lane_reversal;
> +	u8 lane_count = ltpll->lane_count;
>  	bool is_dp_alt =
>  		intel_tc_port_in_dp_alt_mode(dig_port);
>  	enum intel_tc_pin_assignment tc_pin =
> @@ -2006,8 +2008,7 @@ void intel_lt_phy_pll_enable(struct intel_encoder
> *encoder,
>  	intel_lt_phy_powerdown_change_sequence(encoder,
> owned_lane_mask,
>  					       XELPDP_P0_STATE_ACTIVE);
> 
> -	intel_lt_phy_enable_disable_tx(encoder, &crtc_state-
> >dpll_hw_state.ltpll,
> -				       crtc_state->lane_count);
> +	intel_lt_phy_enable_disable_tx(encoder,
> +&crtc_state->dpll_hw_state.ltpll);
>  	intel_lt_phy_transaction_end(encoder, wakeref);  }
> 
> --
> 2.43.0

[PATCH v2 06/24] drm/i915/lt_phy: Add xe3plpd .compute_dplls hook

[Mika Kahola]

Add compute dpll hook for xe3plpd platform and bring
PLL state calculation to support PLL framework.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll.c     |  2 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 65 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_lt_phy.c   | 17 +++--
 drivers/gpu/drm/i915/display/intel_lt_phy.h   |  3 +-
 4 files changed, 78 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 8433e3ff0319..147baa777856 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1222,7 +1222,7 @@ static int xe3plpd_crtc_compute_clock(struct intel_atomic_state *state,
 	struct intel_display *display = to_intel_display(encoder);
 	int ret;
 
-	ret = intel_lt_phy_pll_calc_state(crtc_state, encoder);
+	ret = intel_lt_phy_pll_calc_state(crtc_state, encoder, &crtc_state->dpll_hw_state);
 	if (ret)
 		return ret;
 
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 4185c8e136da..58c24e2164ca 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4585,9 +4585,74 @@ static const struct dpll_info xe3plpd_plls[] = {
 	{}
 };
 
+static int xe3plpd_compute_non_tc_phy_dpll(struct intel_atomic_state *state,
+					   struct intel_crtc *crtc,
+					   struct intel_encoder *encoder)
+{
+	struct intel_display *display = to_intel_display(encoder);
+	struct intel_crtc_state *crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
+	struct icl_port_dpll *port_dpll =
+		&crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
+	int ret;
+
+	ret = intel_lt_phy_pll_calc_state(crtc_state, encoder, &port_dpll->hw_state);
+	if (ret)
+		return ret;
+
+	/* this is mainly for the fastset check */
+	icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT);
+
+	crtc_state->port_clock = intel_lt_phy_calc_port_clock(display, &port_dpll->hw_state.ltpll);
+
+	return 0;
+}
+
+static int xe3plpd_compute_tc_phy_dplls(struct intel_atomic_state *state,
+					struct intel_crtc *crtc,
+					struct intel_encoder *encoder)
+{
+	struct intel_display *display = to_intel_display(encoder);
+	struct intel_crtc_state *crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
+	const struct intel_crtc_state *old_crtc_state =
+		intel_atomic_get_old_crtc_state(state, crtc);
+	struct icl_port_dpll *port_dpll;
+	int ret;
+
+	/* TODO: Add state calculation for TBT PLL */
+
+	port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
+	ret = intel_lt_phy_pll_calc_state(crtc_state, encoder, &port_dpll->hw_state);
+	if (ret)
+		return ret;
+
+	/* this is mainly for the fastset check */
+	if (old_crtc_state->intel_dpll &&
+	    old_crtc_state->intel_dpll->info->id == DPLL_ID_ICL_TBTPLL)
+		icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT);
+	else
+		icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_MG_PHY);
+
+	crtc_state->port_clock = intel_lt_phy_calc_port_clock(display, &port_dpll->hw_state.ltpll);
+
+	return 0;
+}
+
+static int xe3plpd_compute_dplls(struct intel_atomic_state *state,
+				 struct intel_crtc *crtc,
+				 struct intel_encoder *encoder)
+{
+	if (intel_encoder_is_tc(encoder))
+		return xe3plpd_compute_tc_phy_dplls(state, crtc, encoder);
+	else
+		return xe3plpd_compute_non_tc_phy_dpll(state, crtc, encoder);
+}
+
 __maybe_unused
 static const struct intel_dpll_mgr xe3plpd_pll_mgr = {
 	.dpll_info = xe3plpd_plls,
+	.compute_dplls = xe3plpd_compute_dplls,
 };
 
 /**
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 07eab4d7bcff..ca31b3c1440c 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -1727,12 +1727,15 @@ intel_lt_phy_calc_port_clock(struct intel_display *display,
 
 int
 intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
-			    struct intel_encoder *encoder)
+			    struct intel_encoder *encoder,
+			    struct intel_dpll_hw_state *hw_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 	const struct intel_lt_phy_pll_params *tables;
 	int i;
 
+	memset(hw_state, 0, sizeof(*hw_state));
+
 	tables = intel_lt_phy_pll_tables_get(crtc_state, encoder);
 	if (!tables)
 		return -EINVAL;
@@ -1742,21 +1745,21 @@ intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
 
 		drm_WARN_ON(display->drm, !intel_dpll_clock_matches(clock, tables[i].clock_rate));
 		if (intel_dpll_clock_matches(crtc_state->port_clock, clock)) {
-			crtc_state->dpll_hw_state.ltpll = *tables[i].state;
+			hw_state->ltpll = *tables[i].state;
 			if (intel_crtc_has_dp_encoder(crtc_state)) {
 				if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
-					crtc_state->dpll_hw_state.ltpll.config[2] = 1;
+					hw_state->ltpll.config[2] = 1;
 			}
-			crtc_state->dpll_hw_state.ltpll.ssc_enabled =
+			hw_state->ltpll.ssc_enabled =
 				intel_lt_phy_pll_is_ssc_enabled(crtc_state, encoder);
-			crtc_state->dpll_hw_state.ltpll.lane_count = crtc_state->lane_count;
+			hw_state->ltpll.lane_count = crtc_state->lane_count;
 			return 0;
 		}
 	}
 
 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
-		crtc_state->dpll_hw_state.ltpll.lane_count = crtc_state->lane_count;
-		return intel_lt_phy_calculate_hdmi_state(&crtc_state->dpll_hw_state.ltpll,
+		hw_state->ltpll.lane_count = crtc_state->lane_count;
+		return intel_lt_phy_calculate_hdmi_state(&hw_state->ltpll,
 							 crtc_state->port_clock);
 	}
 
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h
index db905668f86d..61ec0e5d8888 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
@@ -20,7 +20,8 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
 void intel_lt_phy_pll_disable(struct intel_encoder *encoder);
 int
 intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
-			    struct intel_encoder *encoder);
+			    struct intel_encoder *encoder,
+			    struct intel_dpll_hw_state *hw_state);
 int intel_lt_phy_calc_port_clock(struct intel_display *display,
 				 const struct intel_lt_phy_pll_state *lt_state);
 void intel_lt_phy_set_signal_levels(struct intel_encoder *encoder,
-- 
2.43.0

RE: [PATCH v2 06/24] drm/i915/lt_phy: Add xe3plpd .compute_dplls hook

[Kandpal, Suraj]

> Subject: [PATCH v2 06/24] drm/i915/lt_phy: Add xe3plpd .compute_dplls hook
> 
> Add compute dpll hook for xe3plpd platform and bring PLL state calculation to
> support PLL framework.
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dpll.c     |  2 +-
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 65 +++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_lt_phy.c   | 17 +++--
>  drivers/gpu/drm/i915/display/intel_lt_phy.h   |  3 +-
>  4 files changed, 78 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c
> b/drivers/gpu/drm/i915/display/intel_dpll.c
> index 8433e3ff0319..147baa777856 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -1222,7 +1222,7 @@ static int xe3plpd_crtc_compute_clock(struct
> intel_atomic_state *state,
>  	struct intel_display *display = to_intel_display(encoder);
>  	int ret;
> 
> -	ret = intel_lt_phy_pll_calc_state(crtc_state, encoder);
> +	ret = intel_lt_phy_pll_calc_state(crtc_state, encoder,
> +&crtc_state->dpll_hw_state);
>  	if (ret)
>  		return ret;
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 4185c8e136da..58c24e2164ca 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -4585,9 +4585,74 @@ static const struct dpll_info xe3plpd_plls[] = {
>  	{}
>  };
> 
> +static int xe3plpd_compute_non_tc_phy_dpll(struct intel_atomic_state
> *state,
> +					   struct intel_crtc *crtc,
> +					   struct intel_encoder *encoder)
> +{
> +	struct intel_display *display = to_intel_display(encoder);
> +	struct intel_crtc_state *crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
> +	struct icl_port_dpll *port_dpll =
> +		&crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
> +	int ret;
> +
> +	ret = intel_lt_phy_pll_calc_state(crtc_state, encoder, &port_dpll-
> >hw_state);
> +	if (ret)
> +		return ret;
> +
> +	/* this is mainly for the fastset check */
> +	icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT);
> +
> +	crtc_state->port_clock = intel_lt_phy_calc_port_clock(display,
> +&port_dpll->hw_state.ltpll);
> +
> +	return 0;
> +}
> +
> +static int xe3plpd_compute_tc_phy_dplls(struct intel_atomic_state *state,
> +					struct intel_crtc *crtc,
> +					struct intel_encoder *encoder)
> +{
> +	struct intel_display *display = to_intel_display(encoder);
> +	struct intel_crtc_state *crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
> +	const struct intel_crtc_state *old_crtc_state =
> +		intel_atomic_get_old_crtc_state(state, crtc);
> +	struct icl_port_dpll *port_dpll;
> +	int ret;
> +
> +	/* TODO: Add state calculation for TBT PLL */
> +
> +	port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
> +	ret = intel_lt_phy_pll_calc_state(crtc_state, encoder, &port_dpll-
> >hw_state);
> +	if (ret)
> +		return ret;
> +
> +	/* this is mainly for the fastset check */
> +	if (old_crtc_state->intel_dpll &&
> +	    old_crtc_state->intel_dpll->info->id == DPLL_ID_ICL_TBTPLL)
> +		icl_set_active_port_dpll(crtc_state,
> ICL_PORT_DPLL_DEFAULT);
> +	else
> +		icl_set_active_port_dpll(crtc_state,
> ICL_PORT_DPLL_MG_PHY);
> +
> +	crtc_state->port_clock = intel_lt_phy_calc_port_clock(display,
> +&port_dpll->hw_state.ltpll);
> +
> +	return 0;
> +}
> +
> +static int xe3plpd_compute_dplls(struct intel_atomic_state *state,
> +				 struct intel_crtc *crtc,
> +				 struct intel_encoder *encoder)
> +{
> +	if (intel_encoder_is_tc(encoder))
> +		return xe3plpd_compute_tc_phy_dplls(state, crtc, encoder);
> +	else
> +		return xe3plpd_compute_non_tc_phy_dpll(state, crtc,
> encoder); }
> +
>  __maybe_unused
>  static const struct intel_dpll_mgr xe3plpd_pll_mgr = {
>  	.dpll_info = xe3plpd_plls,
> +	.compute_dplls = xe3plpd_compute_dplls,
>  };
> 
>  /**
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index 07eab4d7bcff..ca31b3c1440c 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -1727,12 +1727,15 @@ intel_lt_phy_calc_port_clock(struct intel_display
> *display,
> 
>  int
>  intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
> -			    struct intel_encoder *encoder)
> +			    struct intel_encoder *encoder,
> +			    struct intel_dpll_hw_state *hw_state)

I would rather this be named dpll_state
But I do see everywhere else it is name hw_state so I am okay either way

LGTM
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

>  {
>  	struct intel_display *display = to_intel_display(crtc_state);
>  	const struct intel_lt_phy_pll_params *tables;
>  	int i;
> 
> +	memset(hw_state, 0, sizeof(*hw_state));
> +
>  	tables = intel_lt_phy_pll_tables_get(crtc_state, encoder);
>  	if (!tables)
>  		return -EINVAL;
> @@ -1742,21 +1745,21 @@ intel_lt_phy_pll_calc_state(struct
> intel_crtc_state *crtc_state,
> 
>  		drm_WARN_ON(display->drm,
> !intel_dpll_clock_matches(clock, tables[i].clock_rate));
>  		if (intel_dpll_clock_matches(crtc_state->port_clock, clock)) {
> -			crtc_state->dpll_hw_state.ltpll = *tables[i].state;
> +			hw_state->ltpll = *tables[i].state;
>  			if (intel_crtc_has_dp_encoder(crtc_state)) {
>  				if (intel_crtc_has_type(crtc_state,
> INTEL_OUTPUT_EDP))
> -					crtc_state-
> >dpll_hw_state.ltpll.config[2] = 1;
> +					hw_state->ltpll.config[2] = 1;
>  			}
> -			crtc_state->dpll_hw_state.ltpll.ssc_enabled =
> +			hw_state->ltpll.ssc_enabled =
>  				intel_lt_phy_pll_is_ssc_enabled(crtc_state,
> encoder);
> -			crtc_state->dpll_hw_state.ltpll.lane_count =
> crtc_state->lane_count;
> +			hw_state->ltpll.lane_count = crtc_state->lane_count;
>  			return 0;
>  		}
>  	}
> 
>  	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
> -		crtc_state->dpll_hw_state.ltpll.lane_count = crtc_state-
> >lane_count;
> -		return intel_lt_phy_calculate_hdmi_state(&crtc_state-
> >dpll_hw_state.ltpll,
> +		hw_state->ltpll.lane_count = crtc_state->lane_count;
> +		return intel_lt_phy_calculate_hdmi_state(&hw_state->ltpll,
>  							 crtc_state-
> >port_clock);
>  	}
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h
> b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> index db905668f86d..61ec0e5d8888 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> @@ -20,7 +20,8 @@ void intel_lt_phy_pll_enable(struct intel_encoder
> *encoder,  void intel_lt_phy_pll_disable(struct intel_encoder *encoder);  int
> intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
> -			    struct intel_encoder *encoder);
> +			    struct intel_encoder *encoder,
> +			    struct intel_dpll_hw_state *hw_state);
>  int intel_lt_phy_calc_port_clock(struct intel_display *display,
>  				 const struct intel_lt_phy_pll_state *lt_state);
> void intel_lt_phy_set_signal_levels(struct intel_encoder *encoder,
> --
> 2.43.0

[PATCH v2 07/24] drm/i915/lt_phy: Add xe3plpd .get_dplls hook

[Mika Kahola]

Add .get_dplls function pointer for xe3plpd platforms
to support dpll framework. Reuse the ICL function
pointer.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 58c24e2164ca..9aa8eb0a7d4a 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4653,6 +4653,7 @@ __maybe_unused
 static const struct intel_dpll_mgr xe3plpd_pll_mgr = {
 	.dpll_info = xe3plpd_plls,
 	.compute_dplls = xe3plpd_compute_dplls,
+	.get_dplls = mtl_get_dplls,
 };
 
 /**
-- 
2.43.0

[PATCH v2 08/24] drm/i915/lt_phy: Add xe3plpd .put_dplls hook

[Mika Kahola]

Add .put_dplls function pointer to support xe3plpd platform
on dpll framework. Reuse ICL function pointer.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 9aa8eb0a7d4a..af2613eeaf92 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4654,6 +4654,7 @@ static const struct intel_dpll_mgr xe3plpd_pll_mgr = {
 	.dpll_info = xe3plpd_plls,
 	.compute_dplls = xe3plpd_compute_dplls,
 	.get_dplls = mtl_get_dplls,
+	.put_dplls = icl_put_dplls,
 };
 
 /**
-- 
2.43.0

[PATCH v2 09/24] drm/i915/lt_phy: Add xe3plpd .update_active_dpll hook

[Mika Kahola]

Add .update_active_dpll function pointer to support
dpll framework for xe3plpd platform. Reuse ICL function
pointer.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index af2613eeaf92..c1ed44b23bba 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4655,6 +4655,7 @@ static const struct intel_dpll_mgr xe3plpd_pll_mgr = {
 	.compute_dplls = xe3plpd_compute_dplls,
 	.get_dplls = mtl_get_dplls,
 	.put_dplls = icl_put_dplls,
+	.update_active_dpll = icl_update_active_dpll,
 };
 
 /**
-- 
2.43.0

[PATCH v2 10/24] drm/i915/lt_phy: Add xe3plpd .update_dpll_ref_clks hook

[Mika Kahola]

Add .update_dpll_ref_clks function pointer to xe3plpd
platform to support dpll framework. Reuse ICL
function pointer.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index c1ed44b23bba..b50f02303356 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4656,6 +4656,7 @@ static const struct intel_dpll_mgr xe3plpd_pll_mgr = {
 	.get_dplls = mtl_get_dplls,
 	.put_dplls = icl_put_dplls,
 	.update_active_dpll = icl_update_active_dpll,
+	.update_ref_clks = icl_update_dpll_ref_clks,
 };
 
 /**
-- 
2.43.0

[PATCH v2 11/24] drm/i915/lt_phy: Add xe3plpd .dump_hw_state hook

[Mika Kahola]

Add .dump_hw_state function pointer for xe3plpd platform
to support dpll framework. While at it, switch to use
drm_printer structure to print hw state information.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  |  5 ++---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c |  7 +++++++
 drivers/gpu/drm/i915/display/intel_lt_phy.c   | 16 ++++++++--------
 drivers/gpu/drm/i915/display/intel_lt_phy.h   |  3 ++-
 4 files changed, 19 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 27354585ba92..d67ec81c0b01 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5065,15 +5065,14 @@ pipe_config_lt_phy_pll_mismatch(struct drm_printer *p, bool fastset,
 				const struct intel_lt_phy_pll_state *a,
 				const struct intel_lt_phy_pll_state *b)
 {
-	struct intel_display *display = to_intel_display(crtc);
 	char *chipname = "LTPHY";
 
 	pipe_config_mismatch(p, fastset, crtc, name, chipname);
 
 	drm_printf(p, "expected:\n");
-	intel_lt_phy_dump_hw_state(display, a);
+	intel_lt_phy_dump_hw_state(p, a);
 	drm_printf(p, "found:\n");
-	intel_lt_phy_dump_hw_state(display, b);
+	intel_lt_phy_dump_hw_state(p, b);
 }
 
 bool
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index b50f02303356..26b78063dd94 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4649,6 +4649,12 @@ static int xe3plpd_compute_dplls(struct intel_atomic_state *state,
 		return xe3plpd_compute_non_tc_phy_dpll(state, crtc, encoder);
 }
 
+static void xe3plpd_dump_hw_state(struct drm_printer *p,
+				  const struct intel_dpll_hw_state *dpll_hw_state)
+{
+	intel_lt_phy_dump_hw_state(p, &dpll_hw_state->ltpll);
+}
+
 __maybe_unused
 static const struct intel_dpll_mgr xe3plpd_pll_mgr = {
 	.dpll_info = xe3plpd_plls,
@@ -4657,6 +4663,7 @@ static const struct intel_dpll_mgr xe3plpd_pll_mgr = {
 	.put_dplls = icl_put_dplls,
 	.update_active_dpll = icl_update_active_dpll,
 	.update_ref_clks = icl_update_dpll_ref_clks,
+	.dump_hw_state = xe3plpd_dump_hw_state,
 };
 
 /**
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index ca31b3c1440c..923ee132ec3c 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -2146,23 +2146,23 @@ void intel_lt_phy_set_signal_levels(struct intel_encoder *encoder,
 	intel_lt_phy_transaction_end(encoder, wakeref);
 }
 
-void intel_lt_phy_dump_hw_state(struct intel_display *display,
+void intel_lt_phy_dump_hw_state(struct drm_printer *p,
 				const struct intel_lt_phy_pll_state *hw_state)
 {
 	int i, j;
 
-	drm_dbg_kms(display->drm, "lt_phy_pll_hw_state: ssc enabled: %d, tbt mode: %d\n",
-		    hw_state->ssc_enabled, hw_state->tbt_mode);
+	drm_printf(p, "lt_phy_pll_hw_state: ssc enabled: %d, tbt mode: %d\n",
+		   hw_state->ssc_enabled, hw_state->tbt_mode);
 
 	for (i = 0; i < 3; i++) {
-		drm_dbg_kms(display->drm, "config[%d] = 0x%.4x,\n",
-			    i, hw_state->config[i]);
+		drm_printf(p, "config[%d] = 0x%.4x,\n",
+			   i, hw_state->config[i]);
 	}
 
 	for (i = 0; i <= 12; i++)
 		for (j = 3; j >= 0; j--)
-			drm_dbg_kms(display->drm, "vdr_data[%d][%d] = 0x%.4x,\n",
-				    i, j, hw_state->data[i][j]);
+			drm_printf(p, "vdr_data[%d][%d] = 0x%.4x,\n",
+				   i, j, hw_state->data[i][j]);
 }
 
 bool
@@ -2330,7 +2330,7 @@ static void intel_lt_phy_pll_verify_clock(struct intel_display *display,
 	drm_printf(&p, "PLL state %s (%s):\n",
 		   pll_state_name,
 		   is_precomputed_state ? "precomputed" : "computed");
-	intel_lt_phy_dump_hw_state(display, pll_state);
+	intel_lt_phy_dump_hw_state(&p, pll_state);
 }
 
 static void intel_lt_phy_pll_verify_params(struct intel_display *display,
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h
index 61ec0e5d8888..b208bbd6f8ca 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
@@ -8,6 +8,7 @@
 
 #include <linux/types.h>
 
+struct drm_printer;
 struct intel_atomic_state;
 struct intel_display;
 struct intel_encoder;
@@ -26,7 +27,7 @@ int intel_lt_phy_calc_port_clock(struct intel_display *display,
 				 const struct intel_lt_phy_pll_state *lt_state);
 void intel_lt_phy_set_signal_levels(struct intel_encoder *encoder,
 				    const struct intel_crtc_state *crtc_state);
-void intel_lt_phy_dump_hw_state(struct intel_display *display,
+void intel_lt_phy_dump_hw_state(struct drm_printer *p,
 				const struct intel_lt_phy_pll_state *hw_state);
 bool
 intel_lt_phy_pll_compare_hw_state(const struct intel_lt_phy_pll_state *a,
-- 
2.43.0

RE: [PATCH v2 11/24] drm/i915/lt_phy: Add xe3plpd .dump_hw_state hook

[Kandpal, Suraj]

> Subject: [PATCH v2 11/24] drm/i915/lt_phy: Add xe3plpd .dump_hw_state
> hook
> 
> Add .dump_hw_state function pointer for xe3plpd platform to support dpll
> framework. While at it, switch to use drm_printer structure to print hw state
> information.
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c  |  5 ++---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c |  7 +++++++
>  drivers/gpu/drm/i915/display/intel_lt_phy.c   | 16 ++++++++--------
>  drivers/gpu/drm/i915/display/intel_lt_phy.h   |  3 ++-
>  4 files changed, 19 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 27354585ba92..d67ec81c0b01 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5065,15 +5065,14 @@ pipe_config_lt_phy_pll_mismatch(struct
> drm_printer *p, bool fastset,
>  				const struct intel_lt_phy_pll_state *a,
>  				const struct intel_lt_phy_pll_state *b)  {
> -	struct intel_display *display = to_intel_display(crtc);
>  	char *chipname = "LTPHY";
> 
>  	pipe_config_mismatch(p, fastset, crtc, name, chipname);
> 
>  	drm_printf(p, "expected:\n");
> -	intel_lt_phy_dump_hw_state(display, a);
> +	intel_lt_phy_dump_hw_state(p, a);
>  	drm_printf(p, "found:\n");
> -	intel_lt_phy_dump_hw_state(display, b);
> +	intel_lt_phy_dump_hw_state(p, b);
>  }
> 
>  bool
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index b50f02303356..26b78063dd94 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -4649,6 +4649,12 @@ static int xe3plpd_compute_dplls(struct
> intel_atomic_state *state,
>  		return xe3plpd_compute_non_tc_phy_dpll(state, crtc,
> encoder);  }
> 
> +static void xe3plpd_dump_hw_state(struct drm_printer *p,
> +				  const struct intel_dpll_hw_state
> *dpll_hw_state) {
> +	intel_lt_phy_dump_hw_state(p, &dpll_hw_state->ltpll); }
> +
>  __maybe_unused
>  static const struct intel_dpll_mgr xe3plpd_pll_mgr = {
>  	.dpll_info = xe3plpd_plls,
> @@ -4657,6 +4663,7 @@ static const struct intel_dpll_mgr xe3plpd_pll_mgr = {
>  	.put_dplls = icl_put_dplls,
>  	.update_active_dpll = icl_update_active_dpll,
>  	.update_ref_clks = icl_update_dpll_ref_clks,
> +	.dump_hw_state = xe3plpd_dump_hw_state,
>  };
> 
>  /**
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index ca31b3c1440c..923ee132ec3c 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -2146,23 +2146,23 @@ void intel_lt_phy_set_signal_levels(struct
> intel_encoder *encoder,
>  	intel_lt_phy_transaction_end(encoder, wakeref);  }
> 
> -void intel_lt_phy_dump_hw_state(struct intel_display *display,
> +void intel_lt_phy_dump_hw_state(struct drm_printer *p,
>  				const struct intel_lt_phy_pll_state *hw_state)
> {
>  	int i, j;
> 
> -	drm_dbg_kms(display->drm, "lt_phy_pll_hw_state: ssc enabled: %d,
> tbt mode: %d\n",
> -		    hw_state->ssc_enabled, hw_state->tbt_mode);
> +	drm_printf(p, "lt_phy_pll_hw_state: ssc enabled: %d, tbt mode: %d\n",
> +		   hw_state->ssc_enabled, hw_state->tbt_mode);

Maybe not something for this patch to fix but a separate patch adding debug print for
Lane_count since we cache it now

Otherwise,
LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> 
>  	for (i = 0; i < 3; i++) {
> -		drm_dbg_kms(display->drm, "config[%d] = 0x%.4x,\n",
> -			    i, hw_state->config[i]);
> +		drm_printf(p, "config[%d] = 0x%.4x,\n",
> +			   i, hw_state->config[i]);
>  	}
> 
>  	for (i = 0; i <= 12; i++)
>  		for (j = 3; j >= 0; j--)
> -			drm_dbg_kms(display->drm, "vdr_data[%d][%d] =
> 0x%.4x,\n",
> -				    i, j, hw_state->data[i][j]);
> +			drm_printf(p, "vdr_data[%d][%d] = 0x%.4x,\n",
> +				   i, j, hw_state->data[i][j]);
>  }
> 
>  bool
> @@ -2330,7 +2330,7 @@ static void intel_lt_phy_pll_verify_clock(struct
> intel_display *display,
>  	drm_printf(&p, "PLL state %s (%s):\n",
>  		   pll_state_name,
>  		   is_precomputed_state ? "precomputed" : "computed");
> -	intel_lt_phy_dump_hw_state(display, pll_state);
> +	intel_lt_phy_dump_hw_state(&p, pll_state);
>  }
> 
>  static void intel_lt_phy_pll_verify_params(struct intel_display *display, diff --git
> a/drivers/gpu/drm/i915/display/intel_lt_phy.h
> b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> index 61ec0e5d8888..b208bbd6f8ca 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> @@ -8,6 +8,7 @@
> 
>  #include <linux/types.h>
> 
> +struct drm_printer;
>  struct intel_atomic_state;
>  struct intel_display;
>  struct intel_encoder;
> @@ -26,7 +27,7 @@ int intel_lt_phy_calc_port_clock(struct intel_display
> *display,
>  				 const struct intel_lt_phy_pll_state *lt_state);
> void intel_lt_phy_set_signal_levels(struct intel_encoder *encoder,
>  				    const struct intel_crtc_state *crtc_state); -
> void intel_lt_phy_dump_hw_state(struct intel_display *display,
> +void intel_lt_phy_dump_hw_state(struct drm_printer *p,
>  				const struct intel_lt_phy_pll_state *hw_state);
> bool  intel_lt_phy_pll_compare_hw_state(const struct intel_lt_phy_pll_state *a,
> --
> 2.43.0

RE: [PATCH v2 11/24] drm/i915/lt_phy: Add xe3plpd .dump_hw_state hook

[Kandpal, Suraj]

> Subject: RE: [PATCH v2 11/24] drm/i915/lt_phy: Add xe3plpd .dump_hw_state
> hook
> 
> > Subject: [PATCH v2 11/24] drm/i915/lt_phy: Add xe3plpd .dump_hw_state
> > hook
> >
> > Add .dump_hw_state function pointer for xe3plpd platform to support
> > dpll framework. While at it, switch to use drm_printer structure to
> > print hw state information.
> >

Ahh ohkay so you do the change here,
Maybe move the patch right after the patch where you introduce drm_printer
Otherwise,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_display.c  |  5 ++---
> > drivers/gpu/drm/i915/display/intel_dpll_mgr.c |  7 +++++++
> >  drivers/gpu/drm/i915/display/intel_lt_phy.c   | 16 ++++++++--------
> >  drivers/gpu/drm/i915/display/intel_lt_phy.h   |  3 ++-
> >  4 files changed, 19 insertions(+), 12 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 27354585ba92..d67ec81c0b01 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -5065,15 +5065,14 @@ pipe_config_lt_phy_pll_mismatch(struct
> > drm_printer *p, bool fastset,
> >  				const struct intel_lt_phy_pll_state *a,
> >  				const struct intel_lt_phy_pll_state *b)  {
> > -	struct intel_display *display = to_intel_display(crtc);
> >  	char *chipname = "LTPHY";
> >
> >  	pipe_config_mismatch(p, fastset, crtc, name, chipname);
> >
> >  	drm_printf(p, "expected:\n");
> > -	intel_lt_phy_dump_hw_state(display, a);
> > +	intel_lt_phy_dump_hw_state(p, a);
> >  	drm_printf(p, "found:\n");
> > -	intel_lt_phy_dump_hw_state(display, b);
> > +	intel_lt_phy_dump_hw_state(p, b);
> >  }
> >
> >  bool
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > index b50f02303356..26b78063dd94 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > @@ -4649,6 +4649,12 @@ static int xe3plpd_compute_dplls(struct
> > intel_atomic_state *state,
> >  		return xe3plpd_compute_non_tc_phy_dpll(state, crtc,
> encoder);  }
> >
> > +static void xe3plpd_dump_hw_state(struct drm_printer *p,
> > +				  const struct intel_dpll_hw_state
> > *dpll_hw_state) {
> > +	intel_lt_phy_dump_hw_state(p, &dpll_hw_state->ltpll); }
> > +
> >  __maybe_unused
> >  static const struct intel_dpll_mgr xe3plpd_pll_mgr = {
> >  	.dpll_info = xe3plpd_plls,
> > @@ -4657,6 +4663,7 @@ static const struct intel_dpll_mgr
> xe3plpd_pll_mgr = {
> >  	.put_dplls = icl_put_dplls,
> >  	.update_active_dpll = icl_update_active_dpll,
> >  	.update_ref_clks = icl_update_dpll_ref_clks,
> > +	.dump_hw_state = xe3plpd_dump_hw_state,
> >  };
> >
> >  /**
> > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > index ca31b3c1440c..923ee132ec3c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > @@ -2146,23 +2146,23 @@ void intel_lt_phy_set_signal_levels(struct
> > intel_encoder *encoder,
> >  	intel_lt_phy_transaction_end(encoder, wakeref);  }
> >
> > -void intel_lt_phy_dump_hw_state(struct intel_display *display,
> > +void intel_lt_phy_dump_hw_state(struct drm_printer *p,
> >  				const struct intel_lt_phy_pll_state *hw_state)
> {
> >  	int i, j;
> >
> > -	drm_dbg_kms(display->drm, "lt_phy_pll_hw_state: ssc enabled: %d,
> > tbt mode: %d\n",
> > -		    hw_state->ssc_enabled, hw_state->tbt_mode);
> > +	drm_printf(p, "lt_phy_pll_hw_state: ssc enabled: %d, tbt mode:
> %d\n",
> > +		   hw_state->ssc_enabled, hw_state->tbt_mode);
> 
> Maybe not something for this patch to fix but a separate patch adding debug
> print for Lane_count since we cache it now
> 
> Otherwise,
> LGTM,
> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> 
> >
> >  	for (i = 0; i < 3; i++) {
> > -		drm_dbg_kms(display->drm, "config[%d] = 0x%.4x,\n",
> > -			    i, hw_state->config[i]);
> > +		drm_printf(p, "config[%d] = 0x%.4x,\n",
> > +			   i, hw_state->config[i]);
> >  	}
> >
> >  	for (i = 0; i <= 12; i++)
> >  		for (j = 3; j >= 0; j--)
> > -			drm_dbg_kms(display->drm, "vdr_data[%d][%d] =
> > 0x%.4x,\n",
> > -				    i, j, hw_state->data[i][j]);
> > +			drm_printf(p, "vdr_data[%d][%d] = 0x%.4x,\n",
> > +				   i, j, hw_state->data[i][j]);
> >  }
> >
> >  bool
> > @@ -2330,7 +2330,7 @@ static void intel_lt_phy_pll_verify_clock(struct
> > intel_display *display,
> >  	drm_printf(&p, "PLL state %s (%s):\n",
> >  		   pll_state_name,
> >  		   is_precomputed_state ? "precomputed" : "computed");
> > -	intel_lt_phy_dump_hw_state(display, pll_state);
> > +	intel_lt_phy_dump_hw_state(&p, pll_state);
> >  }
> >
> >  static void intel_lt_phy_pll_verify_params(struct intel_display
> > *display, diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h
> > b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> > index 61ec0e5d8888..b208bbd6f8ca 100644
> > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
> > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> > @@ -8,6 +8,7 @@
> >
> >  #include <linux/types.h>
> >
> > +struct drm_printer;
> >  struct intel_atomic_state;
> >  struct intel_display;
> >  struct intel_encoder;
> > @@ -26,7 +27,7 @@ int intel_lt_phy_calc_port_clock(struct
> > intel_display *display,
> >  				 const struct intel_lt_phy_pll_state *lt_state);
> void
> > intel_lt_phy_set_signal_levels(struct intel_encoder *encoder,
> >  				    const struct intel_crtc_state *crtc_state); -
> void
> > intel_lt_phy_dump_hw_state(struct intel_display *display,
> > +void intel_lt_phy_dump_hw_state(struct drm_printer *p,
> >  				const struct intel_lt_phy_pll_state
> *hw_state); bool
> > intel_lt_phy_pll_compare_hw_state(const struct intel_lt_phy_pll_state
> > *a,
> > --
> > 2.43.0

[PATCH v2 12/24] drm/i915/lt_phy: Add xe3plpd .compare_hw_state hook

[Mika Kahola]

Add .compare_hw_state function pointer for xe3plpd platform
to support dpll framework.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 26b78063dd94..c1d7d9909544 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4655,6 +4655,15 @@ static void xe3plpd_dump_hw_state(struct drm_printer *p,
 	intel_lt_phy_dump_hw_state(p, &dpll_hw_state->ltpll);
 }
 
+static bool xe3plpd_compare_hw_state(const struct intel_dpll_hw_state *_a,
+				     const struct intel_dpll_hw_state *_b)
+{
+	const struct intel_lt_phy_pll_state *a = &_a->ltpll;
+	const struct intel_lt_phy_pll_state *b = &_b->ltpll;
+
+	return intel_lt_phy_pll_compare_hw_state(a, b);
+}
+
 __maybe_unused
 static const struct intel_dpll_mgr xe3plpd_pll_mgr = {
 	.dpll_info = xe3plpd_plls,
@@ -4664,6 +4673,7 @@ static const struct intel_dpll_mgr xe3plpd_pll_mgr = {
 	.update_active_dpll = icl_update_active_dpll,
 	.update_ref_clks = icl_update_dpll_ref_clks,
 	.dump_hw_state = xe3plpd_dump_hw_state,
+	.compare_hw_state = xe3plpd_compare_hw_state,
 };
 
 /**
-- 
2.43.0

RE: [PATCH v2 12/24] drm/i915/lt_phy: Add xe3plpd .compare_hw_state hook

[Kandpal, Suraj]

> Subject: [PATCH v2 12/24] drm/i915/lt_phy: Add xe3plpd .compare_hw_state
> hook
> 
> Add .compare_hw_state function pointer for xe3plpd platform to support dpll
> framework.
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 26b78063dd94..c1d7d9909544 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -4655,6 +4655,15 @@ static void xe3plpd_dump_hw_state(struct
> drm_printer *p,
>  	intel_lt_phy_dump_hw_state(p, &dpll_hw_state->ltpll);  }
> 
> +static bool xe3plpd_compare_hw_state(const struct intel_dpll_hw_state *_a,
> +				     const struct intel_dpll_hw_state *_b) {
> +	const struct intel_lt_phy_pll_state *a = &_a->ltpll;
> +	const struct intel_lt_phy_pll_state *b = &_b->ltpll;
> +
> +	return intel_lt_phy_pll_compare_hw_state(a, b); }
> +
>  __maybe_unused
>  static const struct intel_dpll_mgr xe3plpd_pll_mgr = {
>  	.dpll_info = xe3plpd_plls,
> @@ -4664,6 +4673,7 @@ static const struct intel_dpll_mgr xe3plpd_pll_mgr
> = {
>  	.update_active_dpll = icl_update_active_dpll,
>  	.update_ref_clks = icl_update_dpll_ref_clks,
>  	.dump_hw_state = xe3plpd_dump_hw_state,
> +	.compare_hw_state = xe3plpd_compare_hw_state,
>  };
> 
>  /**
> --
> 2.43.0

[PATCH v2 13/24] drm/i915/lt_phy: Add xe3plpd .get_hw_state hook

[Mika Kahola]

Add .get_hw_state hook to xe3plpd platform for dpll framework
and update intel_lt_phy_pll_readout_hw_state() function
accordingly to support dpll framework.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c      |  2 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 13 +++++++++++++
 drivers/gpu/drm/i915/display/intel_lt_phy.c   | 11 ++++++-----
 drivers/gpu/drm/i915/display/intel_lt_phy.h   |  3 +--
 4 files changed, 21 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 94ae583e907f..76ba308f32ad 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4248,7 +4248,7 @@ static void xe3plpd_ddi_get_config(struct intel_encoder *encoder,
 {
 	struct intel_display *display = to_intel_display(encoder);
 
-	intel_lt_phy_pll_readout_hw_state(encoder, crtc_state, &crtc_state->dpll_hw_state.ltpll);
+	intel_lt_phy_pll_readout_hw_state(encoder, &crtc_state->dpll_hw_state.ltpll);
 
 	if (crtc_state->dpll_hw_state.ltpll.tbt_mode)
 		crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index c1d7d9909544..6502916793f5 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4571,7 +4571,20 @@ static const struct intel_dpll_mgr mtl_pll_mgr = {
 	.compare_hw_state = mtl_compare_hw_state,
 };
 
+static bool xe3plpd_pll_get_hw_state(struct intel_display *display,
+				     struct intel_dpll *pll,
+				     struct intel_dpll_hw_state *dpll_hw_state)
+{
+	struct intel_encoder *encoder = get_intel_encoder(display, pll);
+
+	if (!encoder)
+		return false;
+
+	return intel_lt_phy_pll_readout_hw_state(encoder, &dpll_hw_state->ltpll);
+}
+
 static const struct intel_dpll_funcs xe3plpd_pll_funcs = {
+	.get_hw_state = xe3plpd_pll_get_hw_state,
 };
 
 static const struct dpll_info xe3plpd_plls[] = {
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 923ee132ec3c..c3686ac6adc9 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -2207,8 +2207,7 @@ static bool intel_lt_phy_pll_is_enabled(struct intel_encoder *encoder)
 			     intel_lt_phy_get_pclk_pll_ack(lane);
 }
 
-void intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
-				       const struct intel_crtc_state *crtc_state,
+bool intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
 				       struct intel_lt_phy_pll_state *pll_state)
 {
 	u8 owned_lane_mask;
@@ -2217,11 +2216,11 @@ void intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
 	int i, j, k;
 
 	if (!intel_lt_phy_pll_is_enabled(encoder))
-		return;
+		return false;
 
 	pll_state->tbt_mode = intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder));
 	if (pll_state->tbt_mode)
-		return;
+		return false;
 
 	owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder);
 	lane = owned_lane_mask & INTEL_LT_PHY_LANE0 ? : INTEL_LT_PHY_LANE1;
@@ -2239,6 +2238,8 @@ void intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
 	}
 
 	intel_lt_phy_transaction_end(encoder, wakeref);
+
+	return true;
 }
 
 void intel_lt_phy_pll_state_verify(struct intel_atomic_state *state,
@@ -2264,7 +2265,7 @@ void intel_lt_phy_pll_state_verify(struct intel_atomic_state *state,
 		return;
 
 	encoder = intel_get_crtc_new_encoder(state, new_crtc_state);
-	intel_lt_phy_pll_readout_hw_state(encoder, new_crtc_state, &pll_hw_state);
+	intel_lt_phy_pll_readout_hw_state(encoder, &pll_hw_state);
 
 	dig_port = enc_to_dig_port(encoder);
 	if (intel_tc_port_in_tbt_alt_mode(dig_port))
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h
index b208bbd6f8ca..0053bb5489e5 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
@@ -32,8 +32,7 @@ void intel_lt_phy_dump_hw_state(struct drm_printer *p,
 bool
 intel_lt_phy_pll_compare_hw_state(const struct intel_lt_phy_pll_state *a,
 				  const struct intel_lt_phy_pll_state *b);
-void intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
-				       const struct intel_crtc_state *crtc_state,
+bool intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
 				       struct intel_lt_phy_pll_state *pll_state);
 void intel_lt_phy_pll_state_verify(struct intel_atomic_state *state,
 				   struct intel_crtc *crtc);
-- 
2.43.0

[PATCH v2 14/24] drm/i915/lt_phy: Add xe3plpd .get_freq hook

[Mika Kahola]

Add .get_freq function hook to support dpll framework for xe3plpd
platform.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll.c     |  5 -----
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 13 +++++++++++++
 2 files changed, 13 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 147baa777856..88f11cb8c5e1 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1219,17 +1219,12 @@ static int xe3plpd_crtc_compute_clock(struct intel_atomic_state *state,
 		intel_atomic_get_new_crtc_state(state, crtc);
 	struct intel_encoder *encoder =
 		intel_get_crtc_new_encoder(state, crtc_state);
-	struct intel_display *display = to_intel_display(encoder);
 	int ret;
 
 	ret = intel_lt_phy_pll_calc_state(crtc_state, encoder, &crtc_state->dpll_hw_state);
 	if (ret)
 		return ret;
 
-	/* TODO: Do the readback via intel_compute_shared_dplls() */
-	crtc_state->port_clock =
-			intel_lt_phy_calc_port_clock(display, &crtc_state->dpll_hw_state.ltpll);
-
 	crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
 
 	return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 6502916793f5..412582e29ca6 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4583,8 +4583,21 @@ static bool xe3plpd_pll_get_hw_state(struct intel_display *display,
 	return intel_lt_phy_pll_readout_hw_state(encoder, &dpll_hw_state->ltpll);
 }
 
+static int xe3plpd_pll_get_freq(struct intel_display *display,
+				const struct intel_dpll *pll,
+				const struct intel_dpll_hw_state *dpll_hw_state)
+{
+	struct intel_encoder *encoder = get_intel_encoder(display, pll);
+
+	if (drm_WARN_ON(display->drm, !encoder))
+		return -EINVAL;
+
+	return intel_lt_phy_calc_port_clock(display, &dpll_hw_state->ltpll);
+}
+
 static const struct intel_dpll_funcs xe3plpd_pll_funcs = {
 	.get_hw_state = xe3plpd_pll_get_hw_state,
+	.get_freq = xe3plpd_pll_get_freq,
 };
 
 static const struct dpll_info xe3plpd_plls[] = {
-- 
2.43.0

RE: [PATCH v2 14/24] drm/i915/lt_phy: Add xe3plpd .get_freq hook

[Kandpal, Suraj]

> Subject: [PATCH v2 14/24] drm/i915/lt_phy: Add xe3plpd .get_freq hook
> 
> Add .get_freq function hook to support dpll framework for xe3plpd platform.
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dpll.c     |  5 -----
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 13 +++++++++++++
>  2 files changed, 13 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c
> b/drivers/gpu/drm/i915/display/intel_dpll.c
> index 147baa777856..88f11cb8c5e1 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -1219,17 +1219,12 @@ static int xe3plpd_crtc_compute_clock(struct
> intel_atomic_state *state,
>  		intel_atomic_get_new_crtc_state(state, crtc);
>  	struct intel_encoder *encoder =
>  		intel_get_crtc_new_encoder(state, crtc_state);
> -	struct intel_display *display = to_intel_display(encoder);
>  	int ret;
> 
>  	ret = intel_lt_phy_pll_calc_state(crtc_state, encoder, &crtc_state-
> >dpll_hw_state);
>  	if (ret)
>  		return ret;
> 
> -	/* TODO: Do the readback via intel_compute_shared_dplls() */
> -	crtc_state->port_clock =
> -			intel_lt_phy_calc_port_clock(display, &crtc_state-
> >dpll_hw_state.ltpll);
> -

Don't remove this here in this patch right now
xe3plpd_pll_get_freq won't get called till we totally enable dpll framework
breaking the functionality in between.
Just keep the function definition and assignment to respective hook here.
Ill go through all the patches and identify the best place to remove it to
Preserve bisectability

Regards,
Suraj Kandpal

>  	crtc_state->hw.adjusted_mode.crtc_clock =
> intel_crtc_dotclock(crtc_state);
> 
>  	return 0;
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 6502916793f5..412582e29ca6 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -4583,8 +4583,21 @@ static bool xe3plpd_pll_get_hw_state(struct
> intel_display *display,
>  	return intel_lt_phy_pll_readout_hw_state(encoder, &dpll_hw_state-
> >ltpll);  }
> 
> +static int xe3plpd_pll_get_freq(struct intel_display *display,
> +				const struct intel_dpll *pll,
> +				const struct intel_dpll_hw_state
> *dpll_hw_state) {
> +	struct intel_encoder *encoder = get_intel_encoder(display, pll);
> +
> +	if (drm_WARN_ON(display->drm, !encoder))
> +		return -EINVAL;
> +
> +	return intel_lt_phy_calc_port_clock(display, &dpll_hw_state->ltpll); }
> +
>  static const struct intel_dpll_funcs xe3plpd_pll_funcs = {
>  	.get_hw_state = xe3plpd_pll_get_hw_state,
> +	.get_freq = xe3plpd_pll_get_freq,
>  };
> 
>  static const struct dpll_info xe3plpd_plls[] = {
> --
> 2.43.0

RE: [PATCH v2 14/24] drm/i915/lt_phy: Add xe3plpd .get_freq hook

[Kahola, Mika]

> -----Original Message-----
> From: Kandpal, Suraj <suraj.kandpal@intel.com>
> Sent: Wednesday, 11 March 2026 6.25
> To: Kahola, Mika <mika.kahola@intel.com>; intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Kahola, Mika <mika.kahola@intel.com>
> Subject: RE: [PATCH v2 14/24] drm/i915/lt_phy: Add xe3plpd .get_freq hook
> 
> > Subject: [PATCH v2 14/24] drm/i915/lt_phy: Add xe3plpd .get_freq hook
> >
> > Add .get_freq function hook to support dpll framework for xe3plpd platform.
> >
> > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_dpll.c     |  5 -----
> >  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 13 +++++++++++++
> >  2 files changed, 13 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c
> > b/drivers/gpu/drm/i915/display/intel_dpll.c
> > index 147baa777856..88f11cb8c5e1 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> > @@ -1219,17 +1219,12 @@ static int xe3plpd_crtc_compute_clock(struct
> > intel_atomic_state *state,
> >  		intel_atomic_get_new_crtc_state(state, crtc);
> >  	struct intel_encoder *encoder =
> >  		intel_get_crtc_new_encoder(state, crtc_state);
> > -	struct intel_display *display = to_intel_display(encoder);
> >  	int ret;
> >
> >  	ret = intel_lt_phy_pll_calc_state(crtc_state, encoder, &crtc_state-
> > >dpll_hw_state);
> >  	if (ret)
> >  		return ret;
> >
> > -	/* TODO: Do the readback via intel_compute_shared_dplls() */
> > -	crtc_state->port_clock =
> > -			intel_lt_phy_calc_port_clock(display, &crtc_state-
> > >dpll_hw_state.ltpll);
> > -
> 
> Don’t remove this here in this patch right now xe3plpd_pll_get_freq won't get called till we totally enable dpll framework
> breaking the functionality in between.
> Just keep the function definition and assignment to respective hook here.
> Ill go through all the patches and identify the best place to remove it to Preserve bisectability

Ok, I will keep these lines here for now.

Thanks!

-Mika-

> 
> Regards,
> Suraj Kandpal
> 
> >  	crtc_state->hw.adjusted_mode.crtc_clock =
> > intel_crtc_dotclock(crtc_state);
> >
> >  	return 0;
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > index 6502916793f5..412582e29ca6 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > @@ -4583,8 +4583,21 @@ static bool xe3plpd_pll_get_hw_state(struct
> > intel_display *display,
> >  	return intel_lt_phy_pll_readout_hw_state(encoder, &dpll_hw_state-
> > >ltpll);  }
> >
> > +static int xe3plpd_pll_get_freq(struct intel_display *display,
> > +				const struct intel_dpll *pll,
> > +				const struct intel_dpll_hw_state
> > *dpll_hw_state) {
> > +	struct intel_encoder *encoder = get_intel_encoder(display, pll);
> > +
> > +	if (drm_WARN_ON(display->drm, !encoder))
> > +		return -EINVAL;
> > +
> > +	return intel_lt_phy_calc_port_clock(display, &dpll_hw_state->ltpll);
> > +}
> > +
> >  static const struct intel_dpll_funcs xe3plpd_pll_funcs = {
> >  	.get_hw_state = xe3plpd_pll_get_hw_state,
> > +	.get_freq = xe3plpd_pll_get_freq,
> >  };
> >
> >  static const struct dpll_info xe3plpd_plls[] = {
> > --
> > 2.43.0

[PATCH v2 15/24] drm/i915/lt_phy: Add xe3plpd .crtc_get_dpll

[Mika Kahola]

Add .crtc_get_dpll function pointer to support xe3plpd
platform.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 88f11cb8c5e1..abc85ee9b832 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1691,6 +1691,7 @@ static int i8xx_crtc_compute_clock(struct intel_atomic_state *state,
 
 static const struct intel_dpll_global_funcs xe3plpd_dpll_funcs = {
 	.crtc_compute_clock = xe3plpd_crtc_compute_clock,
+	.crtc_get_dpll = hsw_crtc_get_dpll,
 };
 
 static const struct intel_dpll_global_funcs mtl_dpll_funcs = {
-- 
2.43.0

[PATCH v2 16/24] drm/i915/lt_phy: Replace crtc compute clock

[Mika Kahola]

The existing DPLL compute clock callback for the XE3PLPD platform
(`xe3plpd_crtc_compute_clock`) was specific to that platform. Replace it
with the more generic Haswell (`hsw_crtc_compute_clock`) implementation
so that the compute clock path does not rely on the XE3PLPD
hook.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll.c | 20 +-------------------
 1 file changed, 1 insertion(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index abc85ee9b832..c7d37e74fbe9 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1212,24 +1212,6 @@ static int dg2_crtc_compute_clock(struct intel_atomic_state *state,
 	return 0;
 }
 
-static int xe3plpd_crtc_compute_clock(struct intel_atomic_state *state,
-				      struct intel_crtc *crtc)
-{
-	struct intel_crtc_state *crtc_state =
-		intel_atomic_get_new_crtc_state(state, crtc);
-	struct intel_encoder *encoder =
-		intel_get_crtc_new_encoder(state, crtc_state);
-	int ret;
-
-	ret = intel_lt_phy_pll_calc_state(crtc_state, encoder, &crtc_state->dpll_hw_state);
-	if (ret)
-		return ret;
-
-	crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
-
-	return 0;
-}
-
 static int ilk_fb_cb_factor(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
@@ -1690,7 +1672,7 @@ static int i8xx_crtc_compute_clock(struct intel_atomic_state *state,
 }
 
 static const struct intel_dpll_global_funcs xe3plpd_dpll_funcs = {
-	.crtc_compute_clock = xe3plpd_crtc_compute_clock,
+	.crtc_compute_clock = hsw_crtc_compute_clock,
 	.crtc_get_dpll = hsw_crtc_get_dpll,
 };
 
-- 
2.43.0

RE: [PATCH v2 16/24] drm/i915/lt_phy: Replace crtc compute clock

[Kandpal, Suraj]

> Subject: [PATCH v2 16/24] drm/i915/lt_phy: Replace crtc compute clock
> 
> The existing DPLL compute clock callback for the XE3PLPD platform
> (`xe3plpd_crtc_compute_clock`) was specific to that platform. Replace it with
> the more generic Haswell (`hsw_crtc_compute_clock`) implementation so that
> the compute clock path does not rely on the XE3PLPD hook.
> 

Patch looks good mostly but does not belong here.
This breaks bisectability reason being dpll_mgr is currently null for LT PHY
And it will never do the  compute_dpll  call without warning.
Still going through patches will call out where it can be added.

Regards,
Suraj Kandpal

> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dpll.c | 20 +-------------------
>  1 file changed, 1 insertion(+), 19 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c
> b/drivers/gpu/drm/i915/display/intel_dpll.c
> index abc85ee9b832..c7d37e74fbe9 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -1212,24 +1212,6 @@ static int dg2_crtc_compute_clock(struct
> intel_atomic_state *state,
>  	return 0;
>  }
> 
> -static int xe3plpd_crtc_compute_clock(struct intel_atomic_state *state,
> -				      struct intel_crtc *crtc)
> -{
> -	struct intel_crtc_state *crtc_state =
> -		intel_atomic_get_new_crtc_state(state, crtc);
> -	struct intel_encoder *encoder =
> -		intel_get_crtc_new_encoder(state, crtc_state);
> -	int ret;
> -
> -	ret = intel_lt_phy_pll_calc_state(crtc_state, encoder, &crtc_state-
> >dpll_hw_state);
> -	if (ret)
> -		return ret;
> -
> -	crtc_state->hw.adjusted_mode.crtc_clock =
> intel_crtc_dotclock(crtc_state);
> -
> -	return 0;
> -}
> -
>  static int ilk_fb_cb_factor(const struct intel_crtc_state *crtc_state)  {
>  	struct intel_display *display = to_intel_display(crtc_state); @@ -
> 1690,7 +1672,7 @@ static int i8xx_crtc_compute_clock(struct
> intel_atomic_state *state,  }
> 
>  static const struct intel_dpll_global_funcs xe3plpd_dpll_funcs = {
> -	.crtc_compute_clock = xe3plpd_crtc_compute_clock,
> +	.crtc_compute_clock = hsw_crtc_compute_clock,
>  	.crtc_get_dpll = hsw_crtc_get_dpll,
>  };
> 
> --
> 2.43.0

[PATCH v2 17/24] drm/i915/lt_phy: Add .enable_clock hook on DDI

[Mika Kahola]

Enable PLL clock on DDI by moving part of the PLL enabling
sequence into a DDI clock enabling function.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c      |  2 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 13 ++++++++
 drivers/gpu/drm/i915/display/intel_lt_phy.c   | 33 ++++++++++++-------
 drivers/gpu/drm/i915/display/intel_lt_phy.h   | 10 ++++--
 4 files changed, 43 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 76ba308f32ad..51403d09c477 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -5298,7 +5298,7 @@ void intel_ddi_init(struct intel_display *display,
 	encoder->pipe_mask = ~0;
 
 	if (HAS_LT_PHY(display)) {
-		encoder->enable_clock = intel_xe3plpd_pll_enable;
+		encoder->enable_clock = intel_xe3plpd_pll_enable_clock;
 		encoder->disable_clock = intel_xe3plpd_pll_disable;
 		encoder->port_pll_type = intel_mtl_port_pll_type;
 		encoder->get_config = xe3plpd_ddi_get_config;
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 412582e29ca6..54c7a255b3a5 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4595,7 +4595,20 @@ static int xe3plpd_pll_get_freq(struct intel_display *display,
 	return intel_lt_phy_calc_port_clock(display, &dpll_hw_state->ltpll);
 }
 
+static void xe3plpd_pll_enable(struct intel_display *display,
+			       struct intel_dpll *pll,
+			       const struct intel_dpll_hw_state *dpll_hw_state)
+{
+	struct intel_encoder *encoder = get_intel_encoder(display, pll);
+
+	if (drm_WARN_ON(display->drm, !encoder))
+		return;
+
+	intel_xe3plpd_pll_enable(encoder, pll, dpll_hw_state);
+}
+
 static const struct intel_dpll_funcs xe3plpd_pll_funcs = {
+	.enable = xe3plpd_pll_enable,
 	.get_hw_state = xe3plpd_pll_get_hw_state,
 	.get_freq = xe3plpd_pll_get_freq,
 };
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index c3686ac6adc9..6bc32d1734a7 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -1883,9 +1883,11 @@ intel_lt_phy_enable_disable_tx(struct intel_encoder *encoder,
 }
 
 void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
-			     const struct intel_crtc_state *crtc_state)
+			     struct intel_dpll *pll,
+			     const struct intel_dpll_hw_state *dpll_hw_state)
 {
 	struct intel_display *display = to_intel_display(encoder);
+	int port_clock = intel_lt_phy_calc_port_clock(display, &dpll_hw_state->ltpll);
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 	bool lane_reversal = dig_port->lane_reversal;
 	u8 owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder);
@@ -1901,11 +1903,11 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
 	wakeref = intel_lt_phy_transaction_begin(encoder);
 
 	/* 1. Enable MacCLK at default 162 MHz frequency. */
-	intel_lt_phy_lane_reset(encoder, crtc_state->lane_count);
+	intel_lt_phy_lane_reset(encoder, dpll_hw_state->ltpll.lane_count);
 
 	/* 2. Program PORT_CLOCK_CTL register to configure clock muxes, gating, and SSC. */
-	intel_lt_phy_program_port_clock_ctl(encoder, &crtc_state->dpll_hw_state.ltpll,
-					    crtc_state->port_clock, lane_reversal);
+	intel_lt_phy_program_port_clock_ctl(encoder, &dpll_hw_state->ltpll,
+					    port_clock, lane_reversal);
 
 	/* 3. Change owned PHY lanes power to Ready state. */
 	intel_lt_phy_powerdown_change_sequence(encoder, owned_lane_mask,
@@ -1915,12 +1917,12 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
 	 * 4. Read the PHY message bus VDR register PHY_VDR_0_Config check enabled PLL type,
 	 * encoded rate and encoded mode.
 	 */
-	if (intel_lt_phy_config_changed(encoder, &crtc_state->dpll_hw_state.ltpll)) {
+	if (intel_lt_phy_config_changed(encoder, &dpll_hw_state->ltpll)) {
 		/*
 		 * 5. Program the PHY internal PLL registers over PHY message bus for the desired
 		 * frequency and protocol type
 		 */
-		intel_lt_phy_program_pll(encoder, &crtc_state->dpll_hw_state.ltpll);
+		intel_lt_phy_program_pll(encoder, &dpll_hw_state->ltpll);
 
 		/* 6. Use the P2P transaction flow */
 		/*
@@ -1952,8 +1954,7 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
 		 * Change. We handle this step in bxt_set_cdclk().
 		 */
 		/* 10. Program DDI_CLK_VALFREQ to match intended DDI clock frequency. */
-		intel_de_write(display, DDI_CLK_VALFREQ(encoder->port),
-			       crtc_state->port_clock);
+		intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), port_clock);
 
 		/* 11. Program PORT_CLOCK_CTL[PCLK PLL Request LN0] = 1. */
 		intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
@@ -2000,7 +2001,7 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
 			     lane_phy_pulse_status,
 			     lane_phy_pulse_status);
 	} else {
-		intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), crtc_state->port_clock);
+		intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), port_clock);
 	}
 
 	/*
@@ -2011,7 +2012,7 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
 	intel_lt_phy_powerdown_change_sequence(encoder, owned_lane_mask,
 					       XELPDP_P0_STATE_ACTIVE);
 
-	intel_lt_phy_enable_disable_tx(encoder, &crtc_state->dpll_hw_state.ltpll);
+	intel_lt_phy_enable_disable_tx(encoder, &dpll_hw_state->ltpll);
 	intel_lt_phy_transaction_end(encoder, wakeref);
 }
 
@@ -2282,14 +2283,22 @@ void intel_lt_phy_pll_state_verify(struct intel_atomic_state *state,
 }
 
 void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
-			      const struct intel_crtc_state *crtc_state)
+			      struct intel_dpll *pll,
+			      const struct intel_dpll_hw_state *dpll_hw_state)
+{
+	intel_lt_phy_pll_enable(encoder, pll, dpll_hw_state);
+}
+
+void intel_xe3plpd_pll_enable_clock(struct intel_encoder *encoder,
+				    const struct intel_crtc_state *crtc_state)
 {
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 
 	if (intel_tc_port_in_tbt_alt_mode(dig_port))
 		intel_mtl_tbt_pll_enable_clock(encoder, crtc_state->port_clock);
 	else
-		intel_lt_phy_pll_enable(encoder, crtc_state);
+		/* TODO: remove when PLL mgr is in place. */
+		intel_xe3plpd_pll_enable(encoder, NULL, &crtc_state->dpll_hw_state);
 }
 
 void intel_xe3plpd_pll_disable(struct intel_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h
index 0053bb5489e5..9188ce980119 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
@@ -11,13 +11,16 @@
 struct drm_printer;
 struct intel_atomic_state;
 struct intel_display;
+struct intel_dpll;
+struct intel_dpll_hw_state;
 struct intel_encoder;
 struct intel_crtc_state;
 struct intel_crtc;
 struct intel_lt_phy_pll_state;
 
 void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
-			     const struct intel_crtc_state *crtc_state);
+			     struct intel_dpll *pll,
+			     const struct intel_dpll_hw_state *dpll_hw_state);
 void intel_lt_phy_pll_disable(struct intel_encoder *encoder);
 int
 intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
@@ -40,8 +43,11 @@ int
 intel_lt_phy_calculate_hdmi_state(struct intel_lt_phy_pll_state *lt_state,
 				  u32 frequency_khz);
 void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
-			      const struct intel_crtc_state *crtc_state);
+			      struct intel_dpll *pll,
+			      const struct intel_dpll_hw_state *dpll_hw_state);
 void intel_xe3plpd_pll_disable(struct intel_encoder *encoder);
 void intel_lt_phy_verify_plls(struct intel_display *display);
+void intel_xe3plpd_pll_enable_clock(struct intel_encoder *encoder,
+				    const struct intel_crtc_state *crtc_state);
 
 #endif /* __INTEL_LT_PHY_H__ */
-- 
2.43.0

RE: [PATCH v2 17/24] drm/i915/lt_phy: Add .enable_clock hook on DDI

[Kandpal, Suraj]

> Subject: [PATCH v2 17/24] drm/i915/lt_phy: Add .enable_clock hook on DDI
> 
> Enable PLL clock on DDI by moving part of the PLL enabling sequence into a
> DDI clock enabling function.
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c      |  2 +-
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 13 ++++++++
>  drivers/gpu/drm/i915/display/intel_lt_phy.c   | 33 ++++++++++++-------
>  drivers/gpu/drm/i915/display/intel_lt_phy.h   | 10 ++++--
>  4 files changed, 43 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 76ba308f32ad..51403d09c477 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -5298,7 +5298,7 @@ void intel_ddi_init(struct intel_display *display,
>  	encoder->pipe_mask = ~0;
> 
>  	if (HAS_LT_PHY(display)) {
> -		encoder->enable_clock = intel_xe3plpd_pll_enable;
> +		encoder->enable_clock = intel_xe3plpd_pll_enable_clock;
>  		encoder->disable_clock = intel_xe3plpd_pll_disable;
>  		encoder->port_pll_type = intel_mtl_port_pll_type;
>  		encoder->get_config = xe3plpd_ddi_get_config; diff --git
> a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 412582e29ca6..54c7a255b3a5 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -4595,7 +4595,20 @@ static int xe3plpd_pll_get_freq(struct intel_display
> *display,
>  	return intel_lt_phy_calc_port_clock(display, &dpll_hw_state->ltpll);  }
> 
> +static void xe3plpd_pll_enable(struct intel_display *display,
> +			       struct intel_dpll *pll,
> +			       const struct intel_dpll_hw_state *dpll_hw_state) {
> +	struct intel_encoder *encoder = get_intel_encoder(display, pll);
> +
> +	if (drm_WARN_ON(display->drm, !encoder))
> +		return;
> +
> +	intel_xe3plpd_pll_enable(encoder, pll, dpll_hw_state); }
> +
>  static const struct intel_dpll_funcs xe3plpd_pll_funcs = {
> +	.enable = xe3plpd_pll_enable,
>  	.get_hw_state = xe3plpd_pll_get_hw_state,
>  	.get_freq = xe3plpd_pll_get_freq,
>  };
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index c3686ac6adc9..6bc32d1734a7 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -1883,9 +1883,11 @@ intel_lt_phy_enable_disable_tx(struct
> intel_encoder *encoder,  }
> 
>  void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
> -			     const struct intel_crtc_state *crtc_state)
> +			     struct intel_dpll *pll,
> +			     const struct intel_dpll_hw_state *dpll_hw_state)
>  {
>  	struct intel_display *display = to_intel_display(encoder);
> +	int port_clock = intel_lt_phy_calc_port_clock(display,
> +&dpll_hw_state->ltpll);
>  	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>  	bool lane_reversal = dig_port->lane_reversal;
>  	u8 owned_lane_mask =
> intel_lt_phy_get_owned_lane_mask(encoder);
> @@ -1901,11 +1903,11 @@ void intel_lt_phy_pll_enable(struct
> intel_encoder *encoder,
>  	wakeref = intel_lt_phy_transaction_begin(encoder);
> 
>  	/* 1. Enable MacCLK at default 162 MHz frequency. */
> -	intel_lt_phy_lane_reset(encoder, crtc_state->lane_count);
> +	intel_lt_phy_lane_reset(encoder, dpll_hw_state->ltpll.lane_count);
> 
>  	/* 2. Program PORT_CLOCK_CTL register to configure clock muxes,
> gating, and SSC. */
> -	intel_lt_phy_program_port_clock_ctl(encoder, &crtc_state-
> >dpll_hw_state.ltpll,
> -					    crtc_state->port_clock,
> lane_reversal);
> +	intel_lt_phy_program_port_clock_ctl(encoder, &dpll_hw_state->ltpll,
> +					    port_clock, lane_reversal);
> 
>  	/* 3. Change owned PHY lanes power to Ready state. */
>  	intel_lt_phy_powerdown_change_sequence(encoder,
> owned_lane_mask, @@ -1915,12 +1917,12 @@ void
> intel_lt_phy_pll_enable(struct intel_encoder *encoder,
>  	 * 4. Read the PHY message bus VDR register PHY_VDR_0_Config
> check enabled PLL type,
>  	 * encoded rate and encoded mode.
>  	 */
> -	if (intel_lt_phy_config_changed(encoder, &crtc_state-
> >dpll_hw_state.ltpll)) {
> +	if (intel_lt_phy_config_changed(encoder, &dpll_hw_state->ltpll)) {
>  		/*
>  		 * 5. Program the PHY internal PLL registers over PHY
> message bus for the desired
>  		 * frequency and protocol type
>  		 */
> -		intel_lt_phy_program_pll(encoder, &crtc_state-
> >dpll_hw_state.ltpll);
> +		intel_lt_phy_program_pll(encoder, &dpll_hw_state->ltpll);
> 
>  		/* 6. Use the P2P transaction flow */
>  		/*
> @@ -1952,8 +1954,7 @@ void intel_lt_phy_pll_enable(struct intel_encoder
> *encoder,
>  		 * Change. We handle this step in bxt_set_cdclk().
>  		 */
>  		/* 10. Program DDI_CLK_VALFREQ to match intended DDI
> clock frequency. */
> -		intel_de_write(display, DDI_CLK_VALFREQ(encoder->port),
> -			       crtc_state->port_clock);
> +		intel_de_write(display, DDI_CLK_VALFREQ(encoder->port),
> port_clock);
> 
>  		/* 11. Program PORT_CLOCK_CTL[PCLK PLL Request LN0] =
> 1. */
>  		intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display,
> port), @@ -2000,7 +2001,7 @@ void intel_lt_phy_pll_enable(struct
> intel_encoder *encoder,
>  			     lane_phy_pulse_status,
>  			     lane_phy_pulse_status);
>  	} else {
> -		intel_de_write(display, DDI_CLK_VALFREQ(encoder->port),
> crtc_state->port_clock);
> +		intel_de_write(display, DDI_CLK_VALFREQ(encoder->port),
> port_clock);
>  	}
> 
>  	/*
> @@ -2011,7 +2012,7 @@ void intel_lt_phy_pll_enable(struct intel_encoder
> *encoder,
>  	intel_lt_phy_powerdown_change_sequence(encoder,
> owned_lane_mask,
>  					       XELPDP_P0_STATE_ACTIVE);
> 
> -	intel_lt_phy_enable_disable_tx(encoder, &crtc_state-
> >dpll_hw_state.ltpll);
> +	intel_lt_phy_enable_disable_tx(encoder, &dpll_hw_state->ltpll);
>  	intel_lt_phy_transaction_end(encoder, wakeref);  }
> 
> @@ -2282,14 +2283,22 @@ void intel_lt_phy_pll_state_verify(struct
> intel_atomic_state *state,  }
> 
>  void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
> -			      const struct intel_crtc_state *crtc_state)
> +			      struct intel_dpll *pll,
> +			      const struct intel_dpll_hw_state *dpll_hw_state) {
> +	intel_lt_phy_pll_enable(encoder, pll, dpll_hw_state); }
> +
> +void intel_xe3plpd_pll_enable_clock(struct intel_encoder *encoder,
> +				    const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> 
>  	if (intel_tc_port_in_tbt_alt_mode(dig_port))
>  		intel_mtl_tbt_pll_enable_clock(encoder, crtc_state-
> >port_clock);
>  	else
> -		intel_lt_phy_pll_enable(encoder, crtc_state);
> +		/* TODO: remove when PLL mgr is in place. */
> +		intel_xe3plpd_pll_enable(encoder, NULL, &crtc_state-
> >dpll_hw_state);
>  }
> 
>  void intel_xe3plpd_pll_disable(struct intel_encoder *encoder) diff --git
> a/drivers/gpu/drm/i915/display/intel_lt_phy.h
> b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> index 0053bb5489e5..9188ce980119 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> @@ -11,13 +11,16 @@
>  struct drm_printer;
>  struct intel_atomic_state;
>  struct intel_display;
> +struct intel_dpll;
> +struct intel_dpll_hw_state;
>  struct intel_encoder;
>  struct intel_crtc_state;
>  struct intel_crtc;
>  struct intel_lt_phy_pll_state;
> 
>  void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
> -			     const struct intel_crtc_state *crtc_state);
> +			     struct intel_dpll *pll,
> +			     const struct intel_dpll_hw_state *dpll_hw_state);
>  void intel_lt_phy_pll_disable(struct intel_encoder *encoder);  int
> intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state, @@ -40,8
> +43,11 @@ int  intel_lt_phy_calculate_hdmi_state(struct
> intel_lt_phy_pll_state *lt_state,
>  				  u32 frequency_khz);
>  void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
> -			      const struct intel_crtc_state *crtc_state);
> +			      struct intel_dpll *pll,
> +			      const struct intel_dpll_hw_state *dpll_hw_state);
>  void intel_xe3plpd_pll_disable(struct intel_encoder *encoder);  void
> intel_lt_phy_verify_plls(struct intel_display *display);
> +void intel_xe3plpd_pll_enable_clock(struct intel_encoder *encoder,
> +				    const struct intel_crtc_state *crtc_state);
> 
>  #endif /* __INTEL_LT_PHY_H__ */
> --
> 2.43.0

[PATCH v2 18/24] drm/i915/lt_phy: Add .disable_clock hook on DDI

[Mika Kahola]

Disable PLL clock on DDI by moving part of the PLL disabling
sequence into a DDI clock disabling function.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c      |  2 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 12 ++++++++++++
 drivers/gpu/drm/i915/display/intel_lt_phy.c   | 11 +++++++++++
 drivers/gpu/drm/i915/display/intel_lt_phy.h   |  1 +
 4 files changed, 25 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 51403d09c477..191ae7cf81fb 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -5299,7 +5299,7 @@ void intel_ddi_init(struct intel_display *display,
 
 	if (HAS_LT_PHY(display)) {
 		encoder->enable_clock = intel_xe3plpd_pll_enable_clock;
-		encoder->disable_clock = intel_xe3plpd_pll_disable;
+		encoder->disable_clock = intel_xe3plpd_pll_disable_clock;
 		encoder->port_pll_type = intel_mtl_port_pll_type;
 		encoder->get_config = xe3plpd_ddi_get_config;
 	} else if (DISPLAY_VER(display) >= 14) {
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 54c7a255b3a5..28c560417409 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4607,8 +4607,20 @@ static void xe3plpd_pll_enable(struct intel_display *display,
 	intel_xe3plpd_pll_enable(encoder, pll, dpll_hw_state);
 }
 
+static void xe3plpd_pll_disable(struct intel_display *display,
+				struct intel_dpll *pll)
+{
+	struct intel_encoder *encoder = get_intel_encoder(display, pll);
+
+	if (drm_WARN_ON(display->drm, !encoder))
+		return;
+
+	intel_xe3plpd_pll_disable(encoder);
+}
+
 static const struct intel_dpll_funcs xe3plpd_pll_funcs = {
 	.enable = xe3plpd_pll_enable,
+	.disable = xe3plpd_pll_disable,
 	.get_hw_state = xe3plpd_pll_get_hw_state,
 	.get_freq = xe3plpd_pll_get_freq,
 };
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 6bc32d1734a7..3230d2e28d9c 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -2309,6 +2309,17 @@ void intel_xe3plpd_pll_disable(struct intel_encoder *encoder)
 		intel_mtl_tbt_pll_disable_clock(encoder);
 	else
 		intel_lt_phy_pll_disable(encoder);
+}
+
+void intel_xe3plpd_pll_disable_clock(struct intel_encoder *encoder)
+{
+	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+
+	if (intel_tc_port_in_tbt_alt_mode(dig_port))
+		intel_mtl_tbt_pll_disable_clock(encoder);
+	else
+		/* TODO: remove when PLL mgr is in place. */
+		intel_xe3plpd_pll_disable(encoder);
 
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h
index 9188ce980119..3838e9326773 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
@@ -49,5 +49,6 @@ void intel_xe3plpd_pll_disable(struct intel_encoder *encoder);
 void intel_lt_phy_verify_plls(struct intel_display *display);
 void intel_xe3plpd_pll_enable_clock(struct intel_encoder *encoder,
 				    const struct intel_crtc_state *crtc_state);
+void intel_xe3plpd_pll_disable_clock(struct intel_encoder *encoder);
 
 #endif /* __INTEL_LT_PHY_H__ */
-- 
2.43.0

RE: [PATCH v2 18/24] drm/i915/lt_phy: Add .disable_clock hook on DDI

[Kandpal, Suraj]

> Subject: [PATCH v2 18/24] drm/i915/lt_phy: Add .disable_clock hook on DDI
> 
> Disable PLL clock on DDI by moving part of the PLL disabling sequence into a
> DDI clock disabling function.
> 

Commit message needs to be something like
"Add new pll_disable_clock functions so that they can be hooked up to dpll->disable.
This is just a wrapper over the exitisting intel_xe3plpd_pll_disable to make it compatible
With dpll->disable function"


> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c      |  2 +-
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 12 ++++++++++++
>  drivers/gpu/drm/i915/display/intel_lt_phy.c   | 11 +++++++++++
>  drivers/gpu/drm/i915/display/intel_lt_phy.h   |  1 +
>  4 files changed, 25 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 51403d09c477..191ae7cf81fb 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -5299,7 +5299,7 @@ void intel_ddi_init(struct intel_display *display,
> 
>  	if (HAS_LT_PHY(display)) {
>  		encoder->enable_clock = intel_xe3plpd_pll_enable_clock;
> -		encoder->disable_clock = intel_xe3plpd_pll_disable;
> +		encoder->disable_clock = intel_xe3plpd_pll_disable_clock;
>  		encoder->port_pll_type = intel_mtl_port_pll_type;
>  		encoder->get_config = xe3plpd_ddi_get_config;
>  	} else if (DISPLAY_VER(display) >= 14) { diff --git
> a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 54c7a255b3a5..28c560417409 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -4607,8 +4607,20 @@ static void xe3plpd_pll_enable(struct intel_display
> *display,
>  	intel_xe3plpd_pll_enable(encoder, pll, dpll_hw_state);  }
> 
> +static void xe3plpd_pll_disable(struct intel_display *display,
> +				struct intel_dpll *pll)
> +{
> +	struct intel_encoder *encoder = get_intel_encoder(display, pll);
> +
> +	if (drm_WARN_ON(display->drm, !encoder))
> +		return;
> +
> +	intel_xe3plpd_pll_disable(encoder);
> +}
> +
>  static const struct intel_dpll_funcs xe3plpd_pll_funcs = {
>  	.enable = xe3plpd_pll_enable,
> +	.disable = xe3plpd_pll_disable,
>  	.get_hw_state = xe3plpd_pll_get_hw_state,
>  	.get_freq = xe3plpd_pll_get_freq,
>  };
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index 6bc32d1734a7..3230d2e28d9c 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -2309,6 +2309,17 @@ void intel_xe3plpd_pll_disable(struct
> intel_encoder *encoder)
>  		intel_mtl_tbt_pll_disable_clock(encoder);
>  	else
>  		intel_lt_phy_pll_disable(encoder);
> +}
> +
> +void intel_xe3plpd_pll_disable_clock(struct intel_encoder *encoder) {
> +	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> +
> +	if (intel_tc_port_in_tbt_alt_mode(dig_port))
> +		intel_mtl_tbt_pll_disable_clock(encoder);

This is already called inside intel_mtl_tbt_pll_disable clock.
Is there any specific reason to add a wrapper around this other than naming if not
You can drop this wrapper and proceed without the below change
-		encoder->disable_clock = intel_xe3plpd_pll_disable;
+		encoder->disable_clock = intel_xe3plpd_pll_disable_clock;

Regards,
Suraj Kandpal

> +	else
> +		/* TODO: remove when PLL mgr is in place. */
> +		intel_xe3plpd_pll_disable(encoder);
> 
>  }
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h
> b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> index 9188ce980119..3838e9326773 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> @@ -49,5 +49,6 @@ void intel_xe3plpd_pll_disable(struct intel_encoder
> *encoder);  void intel_lt_phy_verify_plls(struct intel_display *display);  void
> intel_xe3plpd_pll_enable_clock(struct intel_encoder *encoder,
>  				    const struct intel_crtc_state *crtc_state);
> +void intel_xe3plpd_pll_disable_clock(struct intel_encoder *encoder);
> 
>  #endif /* __INTEL_LT_PHY_H__ */
> --
> 2.43.0

RE: [PATCH v2 18/24] drm/i915/lt_phy: Add .disable_clock hook on DDI

[Kandpal, Suraj]

> Subject: RE: [PATCH v2 18/24] drm/i915/lt_phy: Add .disable_clock hook on
> DDI
> 
> > Subject: [PATCH v2 18/24] drm/i915/lt_phy: Add .disable_clock hook on
> > DDI
> >
> > Disable PLL clock on DDI by moving part of the PLL disabling sequence
> > into a DDI clock disabling function.
> >
> 
> Commit message needs to be something like "Add new pll_disable_clock
> functions so that they can be hooked up to dpll->disable.
> This is just a wrapper over the exitisting intel_xe3plpd_pll_disable to make it
> compatible With dpll->disable function"
> 
> 
> > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_ddi.c      |  2 +-
> >  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 12 ++++++++++++
> >  drivers/gpu/drm/i915/display/intel_lt_phy.c   | 11 +++++++++++
> >  drivers/gpu/drm/i915/display/intel_lt_phy.h   |  1 +
> >  4 files changed, 25 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 51403d09c477..191ae7cf81fb 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -5299,7 +5299,7 @@ void intel_ddi_init(struct intel_display
> > *display,
> >
> >  	if (HAS_LT_PHY(display)) {
> >  		encoder->enable_clock = intel_xe3plpd_pll_enable_clock;
> > -		encoder->disable_clock = intel_xe3plpd_pll_disable;
> > +		encoder->disable_clock = intel_xe3plpd_pll_disable_clock;
> >  		encoder->port_pll_type = intel_mtl_port_pll_type;
> >  		encoder->get_config = xe3plpd_ddi_get_config;
> >  	} else if (DISPLAY_VER(display) >= 14) { diff --git
> > a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > index 54c7a255b3a5..28c560417409 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > @@ -4607,8 +4607,20 @@ static void xe3plpd_pll_enable(struct
> > intel_display *display,
> >  	intel_xe3plpd_pll_enable(encoder, pll, dpll_hw_state);  }
> >
> > +static void xe3plpd_pll_disable(struct intel_display *display,
> > +				struct intel_dpll *pll)
> > +{
> > +	struct intel_encoder *encoder = get_intel_encoder(display, pll);
> > +
> > +	if (drm_WARN_ON(display->drm, !encoder))
> > +		return;
> > +
> > +	intel_xe3plpd_pll_disable(encoder);
> > +}
> > +
> >  static const struct intel_dpll_funcs xe3plpd_pll_funcs = {
> >  	.enable = xe3plpd_pll_enable,
> > +	.disable = xe3plpd_pll_disable,
> >  	.get_hw_state = xe3plpd_pll_get_hw_state,
> >  	.get_freq = xe3plpd_pll_get_freq,
> >  };
> > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > index 6bc32d1734a7..3230d2e28d9c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > @@ -2309,6 +2309,17 @@ void intel_xe3plpd_pll_disable(struct
> > intel_encoder *encoder)
> >  		intel_mtl_tbt_pll_disable_clock(encoder);
> >  	else
> >  		intel_lt_phy_pll_disable(encoder);
> > +}
> > +
> > +void intel_xe3plpd_pll_disable_clock(struct intel_encoder *encoder) {
> > +	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> > +
> > +	if (intel_tc_port_in_tbt_alt_mode(dig_port))
> > +		intel_mtl_tbt_pll_disable_clock(encoder);
> 
> This is already called inside intel_mtl_tbt_pll_disable clock.
> Is there any specific reason to add a wrapper around this other than naming if
> not You can drop this wrapper and proceed without the below change
> -		encoder->disable_clock = intel_xe3plpd_pll_disable;
> +		encoder->disable_clock = intel_xe3plpd_pll_disable_clock;
> 
> Regards,
> Suraj Kandpal
> 
> > +	else
> > +		/* TODO: remove when PLL mgr is in place. */
> > +		intel_xe3plpd_pll_disable(encoder);
> >
> >  }
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h
> > b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> > index 9188ce980119..3838e9326773 100644
> > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
> > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> > @@ -49,5 +49,6 @@ void intel_xe3plpd_pll_disable(struct intel_encoder
> > *encoder);  void intel_lt_phy_verify_plls(struct intel_display
> > *display);  void intel_xe3plpd_pll_enable_clock(struct intel_encoder
> *encoder,
> >  				    const struct intel_crtc_state *crtc_state);
> > +void intel_xe3plpd_pll_disable_clock(struct intel_encoder *encoder);

Also rearrange in ASCIIBETICAL order

Regards,
Suraj Kandpal

> >
> >  #endif /* __INTEL_LT_PHY_H__ */
> > --
> > 2.43.0

RE: [PATCH v2 18/24] drm/i915/lt_phy: Add .disable_clock hook on DDI

[Kahola, Mika]

> -----Original Message-----
> From: Kandpal, Suraj <suraj.kandpal@intel.com>
> Sent: Wednesday, 11 March 2026 8.00
> To: Kandpal, Suraj <suraj.kandpal@intel.com>; Kahola, Mika <mika.kahola@intel.com>; intel-gfx@lists.freedesktop.org; intel-
> xe@lists.freedesktop.org
> Cc: Kahola, Mika <mika.kahola@intel.com>
> Subject: RE: [PATCH v2 18/24] drm/i915/lt_phy: Add .disable_clock hook on DDI
> 
> > Subject: RE: [PATCH v2 18/24] drm/i915/lt_phy: Add .disable_clock hook
> > on DDI
> >
> > > Subject: [PATCH v2 18/24] drm/i915/lt_phy: Add .disable_clock hook
> > > on DDI
> > >
> > > Disable PLL clock on DDI by moving part of the PLL disabling
> > > sequence into a DDI clock disabling function.
> > >
> >
> > Commit message needs to be something like "Add new pll_disable_clock
> > functions so that they can be hooked up to dpll->disable.
> > This is just a wrapper over the exitisting intel_xe3plpd_pll_disable
> > to make it compatible With dpll->disable function"
> >
> >
> > > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_ddi.c      |  2 +-
> > >  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 12 ++++++++++++
> > >  drivers/gpu/drm/i915/display/intel_lt_phy.c   | 11 +++++++++++
> > >  drivers/gpu/drm/i915/display/intel_lt_phy.h   |  1 +
> > >  4 files changed, 25 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > index 51403d09c477..191ae7cf81fb 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > @@ -5299,7 +5299,7 @@ void intel_ddi_init(struct intel_display
> > > *display,
> > >
> > >  	if (HAS_LT_PHY(display)) {
> > >  		encoder->enable_clock = intel_xe3plpd_pll_enable_clock;
> > > -		encoder->disable_clock = intel_xe3plpd_pll_disable;
> > > +		encoder->disable_clock = intel_xe3plpd_pll_disable_clock;
> > >  		encoder->port_pll_type = intel_mtl_port_pll_type;
> > >  		encoder->get_config = xe3plpd_ddi_get_config;
> > >  	} else if (DISPLAY_VER(display) >= 14) { diff --git
> > > a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > > index 54c7a255b3a5..28c560417409 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > > @@ -4607,8 +4607,20 @@ static void xe3plpd_pll_enable(struct
> > > intel_display *display,
> > >  	intel_xe3plpd_pll_enable(encoder, pll, dpll_hw_state);  }
> > >
> > > +static void xe3plpd_pll_disable(struct intel_display *display,
> > > +				struct intel_dpll *pll)
> > > +{
> > > +	struct intel_encoder *encoder = get_intel_encoder(display, pll);
> > > +
> > > +	if (drm_WARN_ON(display->drm, !encoder))
> > > +		return;
> > > +
> > > +	intel_xe3plpd_pll_disable(encoder);
> > > +}
> > > +
> > >  static const struct intel_dpll_funcs xe3plpd_pll_funcs = {
> > >  	.enable = xe3plpd_pll_enable,
> > > +	.disable = xe3plpd_pll_disable,
> > >  	.get_hw_state = xe3plpd_pll_get_hw_state,
> > >  	.get_freq = xe3plpd_pll_get_freq,
> > >  };
> > > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > > b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > > index 6bc32d1734a7..3230d2e28d9c 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > > @@ -2309,6 +2309,17 @@ void intel_xe3plpd_pll_disable(struct
> > > intel_encoder *encoder)
> > >  		intel_mtl_tbt_pll_disable_clock(encoder);
> > >  	else
> > >  		intel_lt_phy_pll_disable(encoder);
> > > +}
> > > +
> > > +void intel_xe3plpd_pll_disable_clock(struct intel_encoder *encoder) {
> > > +	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> > > +
> > > +	if (intel_tc_port_in_tbt_alt_mode(dig_port))
> > > +		intel_mtl_tbt_pll_disable_clock(encoder);
> >
> > This is already called inside intel_mtl_tbt_pll_disable clock.
> > Is there any specific reason to add a wrapper around this other than
> > naming if not You can drop this wrapper and proceed without the below change
> > -		encoder->disable_clock = intel_xe3plpd_pll_disable;
> > +		encoder->disable_clock = intel_xe3plpd_pll_disable_clock;

This was just a naming to have TBT mode as a separate as it's PLL handling is different.

I can drop this for the next revision.

> >
> > Regards,
> > Suraj Kandpal
> >
> > > +	else
> > > +		/* TODO: remove when PLL mgr is in place. */
> > > +		intel_xe3plpd_pll_disable(encoder);
> > >
> > >  }
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h
> > > b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> > > index 9188ce980119..3838e9326773 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> > > @@ -49,5 +49,6 @@ void intel_xe3plpd_pll_disable(struct
> > > intel_encoder *encoder);  void intel_lt_phy_verify_plls(struct
> > > intel_display *display);  void intel_xe3plpd_pll_enable_clock(struct
> > > intel_encoder
> > *encoder,
> > >  				    const struct intel_crtc_state *crtc_state);
> > > +void intel_xe3plpd_pll_disable_clock(struct intel_encoder
> > > +*encoder);
> 
> Also rearrange in ASCIIBETICAL order

Yes!

Thanks for the review!

-Mika-

> 
> Regards,
> Suraj Kandpal
> 
> > >
> > >  #endif /* __INTEL_LT_PHY_H__ */
> > > --
> > > 2.43.0

[PATCH v2 19/24] drm/i915/lt_phy: Dump lane count for HW state

[Mika Kahola]

Add lane count as part of HW state dump.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_lt_phy.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 3230d2e28d9c..066e2f16791c 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -2152,8 +2152,8 @@ void intel_lt_phy_dump_hw_state(struct drm_printer *p,
 {
 	int i, j;
 
-	drm_printf(p, "lt_phy_pll_hw_state: ssc enabled: %d, tbt mode: %d\n",
-		   hw_state->ssc_enabled, hw_state->tbt_mode);
+	drm_printf(p, "lt_phy_pll_hw_state: lane count: %d, ssc enabled: %d, tbt mode: %d\n",
+		   hw_state->lane_count, hw_state->ssc_enabled, hw_state->tbt_mode);
 
 	for (i = 0; i < 3; i++) {
 		drm_printf(p, "config[%d] = 0x%.4x,\n",
-- 
2.43.0

RE: [PATCH v2 19/24] drm/i915/lt_phy: Dump lane count for HW state

[Kandpal, Suraj]

> Subject: [PATCH v2 19/24] drm/i915/lt_phy: Dump lane count for HW state
> 
> Add lane count as part of HW state dump.

Nit: Add " To increase debuggability" 

Otherwise LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_lt_phy.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index 3230d2e28d9c..066e2f16791c 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -2152,8 +2152,8 @@ void intel_lt_phy_dump_hw_state(struct drm_printer
> *p,  {
>  	int i, j;
> 
> -	drm_printf(p, "lt_phy_pll_hw_state: ssc enabled: %d, tbt mode: %d\n",
> -		   hw_state->ssc_enabled, hw_state->tbt_mode);
> +	drm_printf(p, "lt_phy_pll_hw_state: lane count: %d, ssc enabled: %d,
> tbt mode: %d\n",
> +		   hw_state->lane_count, hw_state->ssc_enabled, hw_state-
> >tbt_mode);
> 
>  	for (i = 0; i < 3; i++) {
>  		drm_printf(p, "config[%d] = 0x%.4x,\n",
> --
> 2.43.0

[PATCH v2 20/24] drm/i915/lt_phy: Readout lane count

[Mika Kahola]

Readout lane count back from HW. Reuse existing function
for Cx0 for LT PHY case with minor modification to add
lanes as function parameters.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 10 ++++++----
 drivers/gpu/drm/i915/display/intel_cx0_phy.h |  1 +
 drivers/gpu/drm/i915/display/intel_lt_phy.c  |  2 ++
 3 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 6a471c021c0e..7e59409bbf01 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2180,7 +2180,7 @@ static int intel_c10pll_calc_state(const struct intel_crtc_state *crtc_state,
 	return 0;
 }
 
-static int readout_enabled_lane_count(struct intel_encoder *encoder)
+int intel_readout_lane_count(struct intel_encoder *encoder, int lane0, int lane1)
 {
 	struct intel_display *display = to_intel_display(encoder);
 	u8 enabled_tx_lane_count = 0;
@@ -2212,7 +2212,7 @@ static int readout_enabled_lane_count(struct intel_encoder *encoder)
 		max_tx_lane_count = round_up(max_tx_lane_count, 2);
 
 	for (tx_lane = 0; tx_lane < max_tx_lane_count; tx_lane++) {
-		u8 phy_lane_mask = tx_lane < 2 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1;
+		u8 phy_lane_mask = tx_lane < 2 ? lane0 : lane1;
 		int tx = tx_lane % 2 + 1;
 		u8 val;
 
@@ -2252,7 +2252,8 @@ static void intel_c10pll_readout_hw_state(struct intel_encoder *encoder,
 	 */
 	intel_c10_msgbus_access_begin(encoder, lane);
 
-	cx0pll_state->lane_count = readout_enabled_lane_count(encoder);
+	cx0pll_state->lane_count = intel_readout_lane_count(encoder, INTEL_CX0_LANE0,
+							    INTEL_CX0_LANE1);
 
 	for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++)
 		pll_state->pll[i] = intel_cx0_read(encoder, lane, PHY_C10_VDR_PLL(i));
@@ -2707,7 +2708,8 @@ static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
 
 	wakeref = intel_cx0_phy_transaction_begin(encoder);
 
-	cx0pll_state->lane_count = readout_enabled_lane_count(encoder);
+	cx0pll_state->lane_count = intel_readout_lane_count(encoder, INTEL_CX0_LANE0,
+							    INTEL_CX0_LANE1);
 
 	/* 1. Read VDR params and current context selection */
 	intel_c20_readout_vdr_params(encoder, &pll_state->vdr, &cntx);
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index 1d4480b8bf39..1428e7a5a318 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -28,6 +28,7 @@ struct intel_hdmi;
 void intel_cx0_clear_response_ready_flag(struct intel_encoder *encoder,
 					 int lane);
 bool intel_encoder_is_c10phy(struct intel_encoder *encoder);
+int intel_readout_lane_count(struct intel_encoder *encoder, int lane0, int lane1);
 void intel_mtl_pll_enable(struct intel_encoder *encoder,
 			  struct intel_dpll *pll,
 			  const struct intel_dpll_hw_state *dpll_hw_state);
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 066e2f16791c..232f14d69ec8 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -2227,6 +2227,8 @@ bool intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
 	lane = owned_lane_mask & INTEL_LT_PHY_LANE0 ? : INTEL_LT_PHY_LANE1;
 	wakeref = intel_lt_phy_transaction_begin(encoder);
 
+	pll_state->lane_count = intel_readout_lane_count(encoder, INTEL_LT_PHY_LANE0,
+							 INTEL_LT_PHY_LANE1);
 	pll_state->config[0] = intel_lt_phy_read(encoder, lane, LT_PHY_VDR_0_CONFIG);
 	pll_state->config[1] = intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0, LT_PHY_VDR_1_CONFIG);
 	pll_state->config[2] = intel_lt_phy_read(encoder, lane, LT_PHY_VDR_2_CONFIG);
-- 
2.43.0

[PATCH v2 21/24] drm/i915/lt_phy: Get encoder configuration for xe3plpd platform

[Mika Kahola]

For DDI initialization get encoder configuration by reusing
MTL+ configuration.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 20 ++++----------------
 1 file changed, 4 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 191ae7cf81fb..385d6b26693d 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4243,21 +4243,6 @@ void intel_ddi_get_clock(struct intel_encoder *encoder,
 						     &crtc_state->dpll_hw_state);
 }
 
-static void xe3plpd_ddi_get_config(struct intel_encoder *encoder,
-				   struct intel_crtc_state *crtc_state)
-{
-	struct intel_display *display = to_intel_display(encoder);
-
-	intel_lt_phy_pll_readout_hw_state(encoder, &crtc_state->dpll_hw_state.ltpll);
-
-	if (crtc_state->dpll_hw_state.ltpll.tbt_mode)
-		crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder);
-	else
-		crtc_state->port_clock =
-			intel_lt_phy_calc_port_clock(display, &crtc_state->dpll_hw_state.ltpll);
-	intel_ddi_get_config(encoder, crtc_state);
-}
-
 static bool icl_ddi_tc_pll_is_tbt(const struct intel_dpll *pll)
 {
 	return pll->info->id == DPLL_ID_ICL_TBTPLL;
@@ -5301,7 +5286,10 @@ void intel_ddi_init(struct intel_display *display,
 		encoder->enable_clock = intel_xe3plpd_pll_enable_clock;
 		encoder->disable_clock = intel_xe3plpd_pll_disable_clock;
 		encoder->port_pll_type = intel_mtl_port_pll_type;
-		encoder->get_config = xe3plpd_ddi_get_config;
+		if (intel_encoder_is_tc(encoder))
+			encoder->get_config = mtl_ddi_tc_phy_get_config;
+		else
+			encoder->get_config = mtl_ddi_non_tc_phy_get_config;
 	} else if (DISPLAY_VER(display) >= 14) {
 		encoder->enable_clock = intel_mtl_pll_enable_clock;
 		encoder->disable_clock = intel_mtl_pll_disable_clock;
-- 
2.43.0

RE: [PATCH v2 21/24] drm/i915/lt_phy: Get encoder configuration for xe3plpd platform

[Kandpal, Suraj]

> Subject: [PATCH v2 21/24] drm/i915/lt_phy: Get encoder configuration for
> xe3plpd platform
> 
> For DDI initialization get encoder configuration by reusing
> MTL+ configuration.

Reframe commit message
" Reuse mtl_ddi_*_get_config functions now that all hooks are in place"

With that fixed LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 20 ++++----------------
>  1 file changed, 4 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 191ae7cf81fb..385d6b26693d 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4243,21 +4243,6 @@ void intel_ddi_get_clock(struct intel_encoder
> *encoder,
>  						     &crtc_state-
> >dpll_hw_state);  }
> 
> -static void xe3plpd_ddi_get_config(struct intel_encoder *encoder,
> -				   struct intel_crtc_state *crtc_state)
> -{
> -	struct intel_display *display = to_intel_display(encoder);
> -
> -	intel_lt_phy_pll_readout_hw_state(encoder, &crtc_state-
> >dpll_hw_state.ltpll);
> -
> -	if (crtc_state->dpll_hw_state.ltpll.tbt_mode)
> -		crtc_state->port_clock =
> intel_mtl_tbt_calc_port_clock(encoder);
> -	else
> -		crtc_state->port_clock =
> -			intel_lt_phy_calc_port_clock(display, &crtc_state-
> >dpll_hw_state.ltpll);
> -	intel_ddi_get_config(encoder, crtc_state);
> -}
> -
>  static bool icl_ddi_tc_pll_is_tbt(const struct intel_dpll *pll)  {
>  	return pll->info->id == DPLL_ID_ICL_TBTPLL; @@ -5301,7 +5286,10
> @@ void intel_ddi_init(struct intel_display *display,
>  		encoder->enable_clock = intel_xe3plpd_pll_enable_clock;
>  		encoder->disable_clock = intel_xe3plpd_pll_disable_clock;
>  		encoder->port_pll_type = intel_mtl_port_pll_type;
> -		encoder->get_config = xe3plpd_ddi_get_config;
> +		if (intel_encoder_is_tc(encoder))
> +			encoder->get_config = mtl_ddi_tc_phy_get_config;
> +		else
> +			encoder->get_config =
> mtl_ddi_non_tc_phy_get_config;
>  	} else if (DISPLAY_VER(display) >= 14) {
>  		encoder->enable_clock = intel_mtl_pll_enable_clock;
>  		encoder->disable_clock = intel_mtl_pll_disable_clock;
> --
> 2.43.0

[PATCH v2 22/24] drm/i915/lt_phy: Add xe3plpd Thunderbolt pll hooks

[Mika Kahola]

Add the PLL hooks for the TBT PLL on xe3plpd. These are simple stubs
similarly to the TBT PLL on earlier platforms, since this PLL is always
on from the display POV - so no PLL enable/disable programming is
required as opposed to the non-TBT PLLs - and the clocks for different
link rates are enabled/disabled at a different level, via the
intel_encoder::enable_clock()/disable_clock() interface.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 13 +++++++++++--
 drivers/gpu/drm/i915/display/intel_lt_phy.c   | 18 ++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_lt_phy.h   |  4 ++++
 3 files changed, 33 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 28c560417409..534cc691979f 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4618,6 +4618,13 @@ static void xe3plpd_pll_disable(struct intel_display *display,
 	intel_xe3plpd_pll_disable(encoder);
 }
 
+static const struct intel_dpll_funcs xe3plpd_tbt_pll_funcs = {
+	.enable = mtl_tbt_pll_enable,
+	.disable = mtl_tbt_pll_disable,
+	.get_hw_state = intel_lt_phy_tbt_pll_readout_hw_state,
+	.get_freq = mtl_tbt_pll_get_freq,
+};
+
 static const struct intel_dpll_funcs xe3plpd_pll_funcs = {
 	.enable = xe3plpd_pll_enable,
 	.disable = xe3plpd_pll_disable,
@@ -4628,7 +4635,8 @@ static const struct intel_dpll_funcs xe3plpd_pll_funcs = {
 static const struct dpll_info xe3plpd_plls[] = {
 	{ .name = "DPLL 0", .funcs = &xe3plpd_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
 	{ .name = "DPLL 1", .funcs = &xe3plpd_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
-	/* TODO: Add TBT */
+	{ .name = "TBT PLL", .funcs = &xe3plpd_tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
+	  .is_alt_port_dpll = true, .always_on = true },
 	{ .name = "TC PLL 1", .funcs = &xe3plpd_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
 	{ .name = "TC PLL 2", .funcs = &xe3plpd_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
 	{ .name = "TC PLL 3", .funcs = &xe3plpd_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, },
@@ -4671,7 +4679,8 @@ static int xe3plpd_compute_tc_phy_dplls(struct intel_atomic_state *state,
 	struct icl_port_dpll *port_dpll;
 	int ret;
 
-	/* TODO: Add state calculation for TBT PLL */
+	port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
+	intel_lt_phy_tbt_pll_calc_state(&port_dpll->hw_state);
 
 	port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
 	ret = intel_lt_phy_pll_calc_state(crtc_state, encoder, &port_dpll->hw_state);
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 232f14d69ec8..746b0182362a 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -1766,6 +1766,13 @@ intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
 	return -EINVAL;
 }
 
+void intel_lt_phy_tbt_pll_calc_state(struct intel_dpll_hw_state *hw_state)
+{
+	memset(hw_state, 0, sizeof(*hw_state));
+
+	hw_state->ltpll.tbt_mode = true;
+}
+
 static void
 intel_lt_phy_program_pll(struct intel_encoder *encoder,
 			 const struct intel_lt_phy_pll_state *ltpll)
@@ -2208,6 +2215,17 @@ static bool intel_lt_phy_pll_is_enabled(struct intel_encoder *encoder)
 			     intel_lt_phy_get_pclk_pll_ack(lane);
 }
 
+bool intel_lt_phy_tbt_pll_readout_hw_state(struct intel_display *display,
+					   struct intel_dpll *pll,
+					   struct intel_dpll_hw_state *hw_state)
+{
+	memset(hw_state, 0, sizeof(*hw_state));
+
+	hw_state->ltpll.tbt_mode = true;
+
+	return true;
+}
+
 bool intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
 				       struct intel_lt_phy_pll_state *pll_state)
 {
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h
index 3838e9326773..1c2ec438cd10 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
@@ -26,6 +26,7 @@ int
 intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
 			    struct intel_encoder *encoder,
 			    struct intel_dpll_hw_state *hw_state);
+void intel_lt_phy_tbt_pll_calc_state(struct intel_dpll_hw_state *hw_state);
 int intel_lt_phy_calc_port_clock(struct intel_display *display,
 				 const struct intel_lt_phy_pll_state *lt_state);
 void intel_lt_phy_set_signal_levels(struct intel_encoder *encoder,
@@ -35,6 +36,9 @@ void intel_lt_phy_dump_hw_state(struct drm_printer *p,
 bool
 intel_lt_phy_pll_compare_hw_state(const struct intel_lt_phy_pll_state *a,
 				  const struct intel_lt_phy_pll_state *b);
+bool intel_lt_phy_tbt_pll_readout_hw_state(struct intel_display *display,
+					   struct intel_dpll *pll,
+					   struct intel_dpll_hw_state *hw_state);
 bool intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
 				       struct intel_lt_phy_pll_state *pll_state);
 void intel_lt_phy_pll_state_verify(struct intel_atomic_state *state,
-- 
2.43.0

RE: [PATCH v2 22/24] drm/i915/lt_phy: Add xe3plpd Thunderbolt pll hooks

[Kandpal, Suraj]

> Subject: [PATCH v2 22/24] drm/i915/lt_phy: Add xe3plpd Thunderbolt pll
> hooks

* PLL

> 
> Add the PLL hooks for the TBT PLL on xe3plpd. These are simple stubs similarly

* similar to the ...

> to the TBT PLL on earlier platforms, since this PLL is always on from the display
> POV - so no PLL enable/disable programming is required as opposed to the
> non-TBT PLLs - and the clocks for different link rates are enabled/disabled at a
> different level, via the
> intel_encoder::enable_clock()/disable_clock() interface.
> 

With above fixed LGTM
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 13 +++++++++++--
>  drivers/gpu/drm/i915/display/intel_lt_phy.c   | 18 ++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_lt_phy.h   |  4 ++++
>  3 files changed, 33 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 28c560417409..534cc691979f 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -4618,6 +4618,13 @@ static void xe3plpd_pll_disable(struct intel_display
> *display,
>  	intel_xe3plpd_pll_disable(encoder);
>  }
> 
> +static const struct intel_dpll_funcs xe3plpd_tbt_pll_funcs = {
> +	.enable = mtl_tbt_pll_enable,
> +	.disable = mtl_tbt_pll_disable,
> +	.get_hw_state = intel_lt_phy_tbt_pll_readout_hw_state,
> +	.get_freq = mtl_tbt_pll_get_freq,
> +};
> +
>  static const struct intel_dpll_funcs xe3plpd_pll_funcs = {
>  	.enable = xe3plpd_pll_enable,
>  	.disable = xe3plpd_pll_disable,
> @@ -4628,7 +4635,8 @@ static const struct intel_dpll_funcs
> xe3plpd_pll_funcs = {  static const struct dpll_info xe3plpd_plls[] = {
>  	{ .name = "DPLL 0", .funcs = &xe3plpd_pll_funcs, .id =
> DPLL_ID_ICL_DPLL0, },
>  	{ .name = "DPLL 1", .funcs = &xe3plpd_pll_funcs, .id =
> DPLL_ID_ICL_DPLL1, },
> -	/* TODO: Add TBT */
> +	{ .name = "TBT PLL", .funcs = &xe3plpd_tbt_pll_funcs, .id =
> DPLL_ID_ICL_TBTPLL,
> +	  .is_alt_port_dpll = true, .always_on = true },
>  	{ .name = "TC PLL 1", .funcs = &xe3plpd_pll_funcs, .id =
> DPLL_ID_ICL_MGPLL1, },
>  	{ .name = "TC PLL 2", .funcs = &xe3plpd_pll_funcs, .id =
> DPLL_ID_ICL_MGPLL2, },
>  	{ .name = "TC PLL 3", .funcs = &xe3plpd_pll_funcs, .id =
> DPLL_ID_ICL_MGPLL3, }, @@ -4671,7 +4679,8 @@ static int
> xe3plpd_compute_tc_phy_dplls(struct intel_atomic_state *state,
>  	struct icl_port_dpll *port_dpll;
>  	int ret;
> 
> -	/* TODO: Add state calculation for TBT PLL */
> +	port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
> +	intel_lt_phy_tbt_pll_calc_state(&port_dpll->hw_state);
> 
>  	port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
>  	ret = intel_lt_phy_pll_calc_state(crtc_state, encoder, &port_dpll-
> >hw_state); diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index 232f14d69ec8..746b0182362a 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -1766,6 +1766,13 @@ intel_lt_phy_pll_calc_state(struct intel_crtc_state
> *crtc_state,
>  	return -EINVAL;
>  }
> 
> +void intel_lt_phy_tbt_pll_calc_state(struct intel_dpll_hw_state
> +*hw_state) {
> +	memset(hw_state, 0, sizeof(*hw_state));
> +
> +	hw_state->ltpll.tbt_mode = true;
> +}
> +
>  static void
>  intel_lt_phy_program_pll(struct intel_encoder *encoder,
>  			 const struct intel_lt_phy_pll_state *ltpll) @@ -2208,6
> +2215,17 @@ static bool intel_lt_phy_pll_is_enabled(struct intel_encoder
> *encoder)
>  			     intel_lt_phy_get_pclk_pll_ack(lane);
>  }
> 
> +bool intel_lt_phy_tbt_pll_readout_hw_state(struct intel_display *display,
> +					   struct intel_dpll *pll,
> +					   struct intel_dpll_hw_state
> *hw_state) {
> +	memset(hw_state, 0, sizeof(*hw_state));
> +
> +	hw_state->ltpll.tbt_mode = true;
> +
> +	return true;
> +}
> +
>  bool intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
>  				       struct intel_lt_phy_pll_state *pll_state)  {
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h
> b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> index 3838e9326773..1c2ec438cd10 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> @@ -26,6 +26,7 @@ int
>  intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
>  			    struct intel_encoder *encoder,
>  			    struct intel_dpll_hw_state *hw_state);
> +void intel_lt_phy_tbt_pll_calc_state(struct intel_dpll_hw_state
> +*hw_state);
>  int intel_lt_phy_calc_port_clock(struct intel_display *display,
>  				 const struct intel_lt_phy_pll_state *lt_state);
> void intel_lt_phy_set_signal_levels(struct intel_encoder *encoder, @@ -35,6
> +36,9 @@ void intel_lt_phy_dump_hw_state(struct drm_printer *p,  bool
> intel_lt_phy_pll_compare_hw_state(const struct intel_lt_phy_pll_state *a,
>  				  const struct intel_lt_phy_pll_state *b);
> +bool intel_lt_phy_tbt_pll_readout_hw_state(struct intel_display *display,
> +					   struct intel_dpll *pll,
> +					   struct intel_dpll_hw_state
> *hw_state);
>  bool intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
>  				       struct intel_lt_phy_pll_state *pll_state);
> void intel_lt_phy_pll_state_verify(struct intel_atomic_state *state,
> --
> 2.43.0

[PATCH v2 23/24] drm/i915/lt_phy: Remove LT PHY specific state verification

[Mika Kahola]

Remove LT PHY specific state verification as DPLL framework
has state verification check.

v2: Reuse intel_lt_phy_pll_compare_hw_state() as only config[0]
    and config[0] parameters are reliable with LT PHY (Suraj)

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c |  5 ++-
 drivers/gpu/drm/i915/display/intel_lt_phy.c   | 39 -------------------
 drivers/gpu/drm/i915/display/intel_lt_phy.h   |  2 -
 .../drm/i915/display/intel_modeset_verify.c   |  1 -
 4 files changed, 3 insertions(+), 44 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 534cc691979f..63a0469d4e65 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -5117,8 +5117,9 @@ verify_single_dpll_state(struct intel_display *display,
 				 pll->info->name, pipe_mask, pll->state.pipe_mask);
 
 	if (INTEL_DISPLAY_STATE_WARN(display,
-				     pll->on && memcmp(&pll->state.hw_state, &dpll_hw_state,
-						       sizeof(dpll_hw_state)),
+				     pll->on && HAS_LT_PHY(display) ?
+				     !intel_lt_phy_pll_compare_hw_state(&pll->state.hw_state.ltpll, &dpll_hw_state.ltpll) :
+				     memcmp(&pll->state.hw_state, &dpll_hw_state, sizeof(dpll_hw_state)),
 				     "%s: pll hw state mismatch\n",
 				     pll->info->name)) {
 		struct drm_printer p = drm_dbg_printer(display->drm, DRM_UT_KMS, NULL);
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 746b0182362a..032fd80664c6 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -2263,45 +2263,6 @@ bool intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
 	return true;
 }
 
-void intel_lt_phy_pll_state_verify(struct intel_atomic_state *state,
-				   struct intel_crtc *crtc)
-{
-	struct intel_display *display = to_intel_display(state);
-	struct intel_digital_port *dig_port;
-	const struct intel_crtc_state *new_crtc_state =
-		intel_atomic_get_new_crtc_state(state, crtc);
-	struct intel_encoder *encoder;
-	struct intel_lt_phy_pll_state pll_hw_state = {};
-	const struct intel_lt_phy_pll_state *pll_sw_state = &new_crtc_state->dpll_hw_state.ltpll;
-
-	if (DISPLAY_VER(display) < 35)
-		return;
-
-	if (!new_crtc_state->hw.active)
-		return;
-
-	/* intel_get_crtc_new_encoder() only works for modeset/fastset commits */
-	if (!intel_crtc_needs_modeset(new_crtc_state) &&
-	    !intel_crtc_needs_fastset(new_crtc_state))
-		return;
-
-	encoder = intel_get_crtc_new_encoder(state, new_crtc_state);
-	intel_lt_phy_pll_readout_hw_state(encoder, &pll_hw_state);
-
-	dig_port = enc_to_dig_port(encoder);
-	if (intel_tc_port_in_tbt_alt_mode(dig_port))
-		return;
-
-	INTEL_DISPLAY_STATE_WARN(display, pll_hw_state.config[0] != pll_sw_state->config[0],
-				 "[CRTC:%d:%s] mismatch in LT PHY PLL CONFIG 0: (expected 0x%04x, found 0x%04x)",
-				 crtc->base.base.id, crtc->base.name,
-				 pll_sw_state->config[0], pll_hw_state.config[0]);
-	INTEL_DISPLAY_STATE_WARN(display, pll_hw_state.config[2] != pll_sw_state->config[2],
-				 "[CRTC:%d:%s] mismatch in LT PHY PLL CONFIG 2: (expected 0x%04x, found 0x%04x)",
-				 crtc->base.base.id, crtc->base.name,
-				 pll_sw_state->config[2], pll_hw_state.config[2]);
-}
-
 void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
 			      struct intel_dpll *pll,
 			      const struct intel_dpll_hw_state *dpll_hw_state)
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h
index 1c2ec438cd10..8b98997b3107 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
@@ -41,8 +41,6 @@ bool intel_lt_phy_tbt_pll_readout_hw_state(struct intel_display *display,
 					   struct intel_dpll_hw_state *hw_state);
 bool intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
 				       struct intel_lt_phy_pll_state *pll_state);
-void intel_lt_phy_pll_state_verify(struct intel_atomic_state *state,
-				   struct intel_crtc *crtc);
 int
 intel_lt_phy_calculate_hdmi_state(struct intel_lt_phy_pll_state *lt_state,
 				  u32 frequency_khz);
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
index 12a00121c274..2ec17c2bfe0f 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
@@ -246,7 +246,6 @@ void intel_modeset_verify_crtc(struct intel_atomic_state *state,
 	verify_crtc_state(state, crtc);
 	intel_dpll_state_verify(state, crtc);
 	intel_mpllb_state_verify(state, crtc);
-	intel_lt_phy_pll_state_verify(state, crtc);
 }
 
 void intel_modeset_verify_disabled(struct intel_atomic_state *state)
-- 
2.43.0

[PATCH v3 23/24] drm/i915/lt_phy: Remove LT PHY specific state verification

[Mika Kahola]

Remove LT PHY specific state verification as DPLL framework
has state verification check.

v2: Reuse intel_lt_phy_pll_compare_hw_state() as only config[0]
    and config[0] parameters are reliable with LT PHY (Suraj)
v3: Rephrase handling of LT PHY case when verifying the state (CI)

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 14 +++++--
 drivers/gpu/drm/i915/display/intel_lt_phy.c   | 39 -------------------
 drivers/gpu/drm/i915/display/intel_lt_phy.h   |  2 -
 .../drm/i915/display/intel_modeset_verify.c   |  1 -
 4 files changed, 11 insertions(+), 45 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 534cc691979f..c3f35250f192 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -5075,6 +5075,7 @@ verify_single_dpll_state(struct intel_display *display,
 			 const struct intel_crtc_state *new_crtc_state)
 {
 	struct intel_dpll_hw_state dpll_hw_state = {};
+	bool pll_mismatch = false;
 	u8 pipe_mask;
 	bool active;
 
@@ -5116,9 +5117,16 @@ verify_single_dpll_state(struct intel_display *display,
 				 "%s: pll enabled crtcs mismatch (expected 0x%x in 0x%x)\n",
 				 pll->info->name, pipe_mask, pll->state.pipe_mask);
 
-	if (INTEL_DISPLAY_STATE_WARN(display,
-				     pll->on && memcmp(&pll->state.hw_state, &dpll_hw_state,
-						       sizeof(dpll_hw_state)),
+	if (pll->on) {
+		const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;
+
+		if (HAS_LT_PHY(display))
+			pll_mismatch = !dpll_mgr->compare_hw_state(&pll->state.hw_state, &dpll_hw_state);
+		else
+			pll_mismatch = memcmp(&pll->state.hw_state, &dpll_hw_state, sizeof(dpll_hw_state));
+	}
+
+	if (INTEL_DISPLAY_STATE_WARN(display, pll_mismatch,
 				     "%s: pll hw state mismatch\n",
 				     pll->info->name)) {
 		struct drm_printer p = drm_dbg_printer(display->drm, DRM_UT_KMS, NULL);
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 746b0182362a..032fd80664c6 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -2263,45 +2263,6 @@ bool intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
 	return true;
 }
 
-void intel_lt_phy_pll_state_verify(struct intel_atomic_state *state,
-				   struct intel_crtc *crtc)
-{
-	struct intel_display *display = to_intel_display(state);
-	struct intel_digital_port *dig_port;
-	const struct intel_crtc_state *new_crtc_state =
-		intel_atomic_get_new_crtc_state(state, crtc);
-	struct intel_encoder *encoder;
-	struct intel_lt_phy_pll_state pll_hw_state = {};
-	const struct intel_lt_phy_pll_state *pll_sw_state = &new_crtc_state->dpll_hw_state.ltpll;
-
-	if (DISPLAY_VER(display) < 35)
-		return;
-
-	if (!new_crtc_state->hw.active)
-		return;
-
-	/* intel_get_crtc_new_encoder() only works for modeset/fastset commits */
-	if (!intel_crtc_needs_modeset(new_crtc_state) &&
-	    !intel_crtc_needs_fastset(new_crtc_state))
-		return;
-
-	encoder = intel_get_crtc_new_encoder(state, new_crtc_state);
-	intel_lt_phy_pll_readout_hw_state(encoder, &pll_hw_state);
-
-	dig_port = enc_to_dig_port(encoder);
-	if (intel_tc_port_in_tbt_alt_mode(dig_port))
-		return;
-
-	INTEL_DISPLAY_STATE_WARN(display, pll_hw_state.config[0] != pll_sw_state->config[0],
-				 "[CRTC:%d:%s] mismatch in LT PHY PLL CONFIG 0: (expected 0x%04x, found 0x%04x)",
-				 crtc->base.base.id, crtc->base.name,
-				 pll_sw_state->config[0], pll_hw_state.config[0]);
-	INTEL_DISPLAY_STATE_WARN(display, pll_hw_state.config[2] != pll_sw_state->config[2],
-				 "[CRTC:%d:%s] mismatch in LT PHY PLL CONFIG 2: (expected 0x%04x, found 0x%04x)",
-				 crtc->base.base.id, crtc->base.name,
-				 pll_sw_state->config[2], pll_hw_state.config[2]);
-}
-
 void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
 			      struct intel_dpll *pll,
 			      const struct intel_dpll_hw_state *dpll_hw_state)
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h
index 1c2ec438cd10..8b98997b3107 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
@@ -41,8 +41,6 @@ bool intel_lt_phy_tbt_pll_readout_hw_state(struct intel_display *display,
 					   struct intel_dpll_hw_state *hw_state);
 bool intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
 				       struct intel_lt_phy_pll_state *pll_state);
-void intel_lt_phy_pll_state_verify(struct intel_atomic_state *state,
-				   struct intel_crtc *crtc);
 int
 intel_lt_phy_calculate_hdmi_state(struct intel_lt_phy_pll_state *lt_state,
 				  u32 frequency_khz);
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
index 12a00121c274..2ec17c2bfe0f 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
@@ -246,7 +246,6 @@ void intel_modeset_verify_crtc(struct intel_atomic_state *state,
 	verify_crtc_state(state, crtc);
 	intel_dpll_state_verify(state, crtc);
 	intel_mpllb_state_verify(state, crtc);
-	intel_lt_phy_pll_state_verify(state, crtc);
 }
 
 void intel_modeset_verify_disabled(struct intel_atomic_state *state)
-- 
2.43.0

RE: [PATCH v3 23/24] drm/i915/lt_phy: Remove LT PHY specific state verification

[Kandpal, Suraj]

> Subject: [PATCH v3 23/24] drm/i915/lt_phy: Remove LT PHY specific state
> verification
> 
> Remove LT PHY specific state verification as DPLL framework has state
> verification check.
> 
> v2: Reuse intel_lt_phy_pll_compare_hw_state() as only config[0]
>     and config[0] parameters are reliable with LT PHY (Suraj)
> v3: Rephrase handling of LT PHY case when verifying the state (CI)
> 

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 14 +++++--
>  drivers/gpu/drm/i915/display/intel_lt_phy.c   | 39 -------------------
>  drivers/gpu/drm/i915/display/intel_lt_phy.h   |  2 -
>  .../drm/i915/display/intel_modeset_verify.c   |  1 -
>  4 files changed, 11 insertions(+), 45 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 534cc691979f..c3f35250f192 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -5075,6 +5075,7 @@ verify_single_dpll_state(struct intel_display *display,
>  			 const struct intel_crtc_state *new_crtc_state)  {
>  	struct intel_dpll_hw_state dpll_hw_state = {};
> +	bool pll_mismatch = false;
>  	u8 pipe_mask;
>  	bool active;
> 
> @@ -5116,9 +5117,16 @@ verify_single_dpll_state(struct intel_display
> *display,
>  				 "%s: pll enabled crtcs mismatch (expected
> 0x%x in 0x%x)\n",
>  				 pll->info->name, pipe_mask, pll-
> >state.pipe_mask);
> 
> -	if (INTEL_DISPLAY_STATE_WARN(display,
> -				     pll->on && memcmp(&pll->state.hw_state,
> &dpll_hw_state,
> -						       sizeof(dpll_hw_state)),
> +	if (pll->on) {
> +		const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;
> +
> +		if (HAS_LT_PHY(display))
> +			pll_mismatch = !dpll_mgr->compare_hw_state(&pll-
> >state.hw_state, &dpll_hw_state);
> +		else
> +			pll_mismatch = memcmp(&pll->state.hw_state,
> &dpll_hw_state, sizeof(dpll_hw_state));
> +	}
> +
> +	if (INTEL_DISPLAY_STATE_WARN(display, pll_mismatch,
>  				     "%s: pll hw state mismatch\n",
>  				     pll->info->name)) {
>  		struct drm_printer p = drm_dbg_printer(display->drm,
> DRM_UT_KMS, NULL); diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index 746b0182362a..032fd80664c6 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -2263,45 +2263,6 @@ bool intel_lt_phy_pll_readout_hw_state(struct
> intel_encoder *encoder,
>  	return true;
>  }
> 
> -void intel_lt_phy_pll_state_verify(struct intel_atomic_state *state,
> -				   struct intel_crtc *crtc)
> -{
> -	struct intel_display *display = to_intel_display(state);
> -	struct intel_digital_port *dig_port;
> -	const struct intel_crtc_state *new_crtc_state =
> -		intel_atomic_get_new_crtc_state(state, crtc);
> -	struct intel_encoder *encoder;
> -	struct intel_lt_phy_pll_state pll_hw_state = {};
> -	const struct intel_lt_phy_pll_state *pll_sw_state = &new_crtc_state-
> >dpll_hw_state.ltpll;
> -
> -	if (DISPLAY_VER(display) < 35)
> -		return;
> -
> -	if (!new_crtc_state->hw.active)
> -		return;
> -
> -	/* intel_get_crtc_new_encoder() only works for modeset/fastset
> commits */
> -	if (!intel_crtc_needs_modeset(new_crtc_state) &&
> -	    !intel_crtc_needs_fastset(new_crtc_state))
> -		return;
> -
> -	encoder = intel_get_crtc_new_encoder(state, new_crtc_state);
> -	intel_lt_phy_pll_readout_hw_state(encoder, &pll_hw_state);
> -
> -	dig_port = enc_to_dig_port(encoder);
> -	if (intel_tc_port_in_tbt_alt_mode(dig_port))
> -		return;
> -
> -	INTEL_DISPLAY_STATE_WARN(display, pll_hw_state.config[0] !=
> pll_sw_state->config[0],
> -				 "[CRTC:%d:%s] mismatch in LT PHY PLL
> CONFIG 0: (expected 0x%04x, found 0x%04x)",
> -				 crtc->base.base.id, crtc->base.name,
> -				 pll_sw_state->config[0],
> pll_hw_state.config[0]);
> -	INTEL_DISPLAY_STATE_WARN(display, pll_hw_state.config[2] !=
> pll_sw_state->config[2],
> -				 "[CRTC:%d:%s] mismatch in LT PHY PLL
> CONFIG 2: (expected 0x%04x, found 0x%04x)",
> -				 crtc->base.base.id, crtc->base.name,
> -				 pll_sw_state->config[2],
> pll_hw_state.config[2]);
> -}
> -
>  void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
>  			      struct intel_dpll *pll,
>  			      const struct intel_dpll_hw_state *dpll_hw_state)
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h
> b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> index 1c2ec438cd10..8b98997b3107 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> @@ -41,8 +41,6 @@ bool intel_lt_phy_tbt_pll_readout_hw_state(struct
> intel_display *display,
>  					   struct intel_dpll_hw_state
> *hw_state);  bool intel_lt_phy_pll_readout_hw_state(struct intel_encoder
> *encoder,
>  				       struct intel_lt_phy_pll_state *pll_state); -
> void intel_lt_phy_pll_state_verify(struct intel_atomic_state *state,
> -				   struct intel_crtc *crtc);
>  int
>  intel_lt_phy_calculate_hdmi_state(struct intel_lt_phy_pll_state *lt_state,
>  				  u32 frequency_khz);
> diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> index 12a00121c274..2ec17c2bfe0f 100644
> --- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> +++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> @@ -246,7 +246,6 @@ void intel_modeset_verify_crtc(struct
> intel_atomic_state *state,
>  	verify_crtc_state(state, crtc);
>  	intel_dpll_state_verify(state, crtc);
>  	intel_mpllb_state_verify(state, crtc);
> -	intel_lt_phy_pll_state_verify(state, crtc);
>  }
> 
>  void intel_modeset_verify_disabled(struct intel_atomic_state *state)
> --
> 2.43.0

[PATCH v2 24/24] drm/i915/lt_phy: Enable dpll framework for xe3plpd

[Mika Kahola]

xe3plpd platform is supported by dpll framework remove a separate
check for hw comparison and rely solely on dpll framework
hw comparison.

Finally, all required hooks are now in place so initialize
PLL manager for xe3plpd platform and remove the redirections
to the legacy code paths for clock enable/disable as well as
state mismatch checks that are no longer needed.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c      |  2 +-
 drivers/gpu/drm/i915/display/intel_display.c  | 31 -------------------
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c |  7 +++--
 drivers/gpu/drm/i915/display/intel_lt_phy.c   |  8 +----
 4 files changed, 6 insertions(+), 42 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 385d6b26693d..c3cceaf781ab 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -5285,7 +5285,7 @@ void intel_ddi_init(struct intel_display *display,
 	if (HAS_LT_PHY(display)) {
 		encoder->enable_clock = intel_xe3plpd_pll_enable_clock;
 		encoder->disable_clock = intel_xe3plpd_pll_disable_clock;
-		encoder->port_pll_type = intel_mtl_port_pll_type;
+		encoder->port_pll_type = icl_ddi_tc_port_pll_type;
 		if (intel_encoder_is_tc(encoder))
 			encoder->get_config = mtl_ddi_tc_phy_get_config;
 		else
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index d67ec81c0b01..af02a666c3a1 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5058,23 +5058,6 @@ static bool allow_vblank_delay_fastset(const struct intel_crtc_state *old_crtc_s
 	       !intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI);
 }
 
-static void
-pipe_config_lt_phy_pll_mismatch(struct drm_printer *p, bool fastset,
-				const struct intel_crtc *crtc,
-				const char *name,
-				const struct intel_lt_phy_pll_state *a,
-				const struct intel_lt_phy_pll_state *b)
-{
-	char *chipname = "LTPHY";
-
-	pipe_config_mismatch(p, fastset, crtc, name, chipname);
-
-	drm_printf(p, "expected:\n");
-	intel_lt_phy_dump_hw_state(p, a);
-	drm_printf(p, "found:\n");
-	intel_lt_phy_dump_hw_state(p, b);
-}
-
 bool
 intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 			  const struct intel_crtc_state *pipe_config,
@@ -5189,16 +5172,6 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	} \
 } while (0)
 
-#define PIPE_CONF_CHECK_PLL_LT(name) do { \
-	if (!intel_lt_phy_pll_compare_hw_state(&current_config->name, \
-					       &pipe_config->name)) { \
-		pipe_config_lt_phy_pll_mismatch(&p, fastset, crtc, __stringify(name), \
-						&current_config->name, \
-						&pipe_config->name); \
-		ret = false; \
-	} \
-} while (0)
-
 #define PIPE_CONF_CHECK_TIMINGS(name) do {     \
 	PIPE_CONF_CHECK_I(name.crtc_hdisplay); \
 	PIPE_CONF_CHECK_I(name.crtc_htotal); \
@@ -5425,10 +5398,6 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	if (display->dpll.mgr || HAS_GMCH(display))
 		PIPE_CONF_CHECK_PLL(dpll_hw_state);
 
-	/* FIXME convert MTL+ platforms over to dpll_mgr */
-	if (HAS_LT_PHY(display))
-		PIPE_CONF_CHECK_PLL_LT(dpll_hw_state.ltpll);
-
 	PIPE_CONF_CHECK_X(dsi_pll.ctrl);
 	PIPE_CONF_CHECK_X(dsi_pll.div);
 
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 63a0469d4e65..c4add325d8d6 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4724,7 +4724,6 @@ static bool xe3plpd_compare_hw_state(const struct intel_dpll_hw_state *_a,
 	return intel_lt_phy_pll_compare_hw_state(a, b);
 }
 
-__maybe_unused
 static const struct intel_dpll_mgr xe3plpd_pll_mgr = {
 	.dpll_info = xe3plpd_plls,
 	.compute_dplls = xe3plpd_compute_dplls,
@@ -4750,9 +4749,11 @@ void intel_dpll_init(struct intel_display *display)
 
 	mutex_init(&display->dpll.lock);
 
-	if (DISPLAY_VER(display) >= 35 || display->platform.dg2)
-		/* No shared DPLLs on NVL or DG2; port PLLs are part of the PHY */
+	if (display->platform.dg2)
+		/* No shared DPLLs on DG2; port PLLs are part of the PHY */
 		dpll_mgr = NULL;
+	else if (DISPLAY_VER(display) >= 35)
+		dpll_mgr = &xe3plpd_pll_mgr;
 	else if (DISPLAY_VER(display) >= 14)
 		dpll_mgr = &mtl_pll_mgr;
 	else if (display->platform.alderlake_p)
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 032fd80664c6..31669a435582 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -11,6 +11,7 @@
 #include "intel_ddi_buf_trans.h"
 #include "intel_de.h"
 #include "intel_display.h"
+#include "intel_display_regs.h"
 #include "intel_display_types.h"
 #include "intel_display_utils.h"
 #include "intel_dpll.h"
@@ -2277,9 +2278,6 @@ void intel_xe3plpd_pll_enable_clock(struct intel_encoder *encoder,
 
 	if (intel_tc_port_in_tbt_alt_mode(dig_port))
 		intel_mtl_tbt_pll_enable_clock(encoder, crtc_state->port_clock);
-	else
-		/* TODO: remove when PLL mgr is in place. */
-		intel_xe3plpd_pll_enable(encoder, NULL, &crtc_state->dpll_hw_state);
 }
 
 void intel_xe3plpd_pll_disable(struct intel_encoder *encoder)
@@ -2298,10 +2296,6 @@ void intel_xe3plpd_pll_disable_clock(struct intel_encoder *encoder)
 
 	if (intel_tc_port_in_tbt_alt_mode(dig_port))
 		intel_mtl_tbt_pll_disable_clock(encoder);
-	else
-		/* TODO: remove when PLL mgr is in place. */
-		intel_xe3plpd_pll_disable(encoder);
-
 }
 
 static void intel_lt_phy_pll_verify_clock(struct intel_display *display,
-- 
2.43.0

RE: [PATCH v2 24/24] drm/i915/lt_phy: Enable dpll framework for xe3plpd

[Kandpal, Suraj]

> Subject: [PATCH v2 24/24] drm/i915/lt_phy: Enable dpll framework for
> xe3plpd
> 
> xe3plpd platform is supported by dpll framework remove a separate check for
> hw comparison and rely solely on dpll framework hw comparison.
> 
> Finally, all required hooks are now in place so initialize PLL manager for
> xe3plpd platform and remove the redirections to the legacy code paths for
> clock enable/disable as well as state mismatch checks that are no longer
> needed.
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>

Patch 16 need to be moved after this patch according to me
While also making sure that the change in patch 14 where we drop 
-	/* TODO: Do the readback via intel_compute_shared_dplls() */
-	crtc_state->port_clock =
-			intel_lt_phy_calc_port_clock(display, &crtc_state->dpll_hw_state.ltpll);
-

Is not done in that patch

Rest looks good to me

Regards,
Suraj Kandpal

> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c      |  2 +-
>  drivers/gpu/drm/i915/display/intel_display.c  | 31 -------------------
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c |  7 +++--
>  drivers/gpu/drm/i915/display/intel_lt_phy.c   |  8 +----
>  4 files changed, 6 insertions(+), 42 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 385d6b26693d..c3cceaf781ab 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -5285,7 +5285,7 @@ void intel_ddi_init(struct intel_display *display,
>  	if (HAS_LT_PHY(display)) {
>  		encoder->enable_clock = intel_xe3plpd_pll_enable_clock;
>  		encoder->disable_clock = intel_xe3plpd_pll_disable_clock;
> -		encoder->port_pll_type = intel_mtl_port_pll_type;
> +		encoder->port_pll_type = icl_ddi_tc_port_pll_type;
>  		if (intel_encoder_is_tc(encoder))
>  			encoder->get_config = mtl_ddi_tc_phy_get_config;
>  		else
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index d67ec81c0b01..af02a666c3a1 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5058,23 +5058,6 @@ static bool allow_vblank_delay_fastset(const
> struct intel_crtc_state *old_crtc_s
>  	       !intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI);  }
> 
> -static void
> -pipe_config_lt_phy_pll_mismatch(struct drm_printer *p, bool fastset,
> -				const struct intel_crtc *crtc,
> -				const char *name,
> -				const struct intel_lt_phy_pll_state *a,
> -				const struct intel_lt_phy_pll_state *b)
> -{
> -	char *chipname = "LTPHY";
> -
> -	pipe_config_mismatch(p, fastset, crtc, name, chipname);
> -
> -	drm_printf(p, "expected:\n");
> -	intel_lt_phy_dump_hw_state(p, a);
> -	drm_printf(p, "found:\n");
> -	intel_lt_phy_dump_hw_state(p, b);
> -}
> -
>  bool
>  intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>  			  const struct intel_crtc_state *pipe_config, @@ -
> 5189,16 +5172,6 @@ intel_pipe_config_compare(const struct intel_crtc_state
> *current_config,
>  	} \
>  } while (0)
> 
> -#define PIPE_CONF_CHECK_PLL_LT(name) do { \
> -	if (!intel_lt_phy_pll_compare_hw_state(&current_config->name, \
> -					       &pipe_config->name)) { \
> -		pipe_config_lt_phy_pll_mismatch(&p, fastset, crtc,
> __stringify(name), \
> -						&current_config->name, \
> -						&pipe_config->name); \
> -		ret = false; \
> -	} \
> -} while (0)
> -
>  #define PIPE_CONF_CHECK_TIMINGS(name) do {     \
>  	PIPE_CONF_CHECK_I(name.crtc_hdisplay); \
>  	PIPE_CONF_CHECK_I(name.crtc_htotal); \ @@ -5425,10 +5398,6
> @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>  	if (display->dpll.mgr || HAS_GMCH(display))
>  		PIPE_CONF_CHECK_PLL(dpll_hw_state);
> 
> -	/* FIXME convert MTL+ platforms over to dpll_mgr */
> -	if (HAS_LT_PHY(display))
> -		PIPE_CONF_CHECK_PLL_LT(dpll_hw_state.ltpll);
> -
>  	PIPE_CONF_CHECK_X(dsi_pll.ctrl);
>  	PIPE_CONF_CHECK_X(dsi_pll.div);
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 63a0469d4e65..c4add325d8d6 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -4724,7 +4724,6 @@ static bool xe3plpd_compare_hw_state(const
> struct intel_dpll_hw_state *_a,
>  	return intel_lt_phy_pll_compare_hw_state(a, b);  }
> 
> -__maybe_unused
>  static const struct intel_dpll_mgr xe3plpd_pll_mgr = {
>  	.dpll_info = xe3plpd_plls,
>  	.compute_dplls = xe3plpd_compute_dplls, @@ -4750,9 +4749,11 @@
> void intel_dpll_init(struct intel_display *display)
> 
>  	mutex_init(&display->dpll.lock);
> 
> -	if (DISPLAY_VER(display) >= 35 || display->platform.dg2)
> -		/* No shared DPLLs on NVL or DG2; port PLLs are part of the
> PHY */
> +	if (display->platform.dg2)
> +		/* No shared DPLLs on DG2; port PLLs are part of the PHY */
>  		dpll_mgr = NULL;
> +	else if (DISPLAY_VER(display) >= 35)
> +		dpll_mgr = &xe3plpd_pll_mgr;
>  	else if (DISPLAY_VER(display) >= 14)
>  		dpll_mgr = &mtl_pll_mgr;
>  	else if (display->platform.alderlake_p) diff --git
> a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index 032fd80664c6..31669a435582 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -11,6 +11,7 @@
>  #include "intel_ddi_buf_trans.h"
>  #include "intel_de.h"
>  #include "intel_display.h"
> +#include "intel_display_regs.h"
>  #include "intel_display_types.h"
>  #include "intel_display_utils.h"
>  #include "intel_dpll.h"
> @@ -2277,9 +2278,6 @@ void intel_xe3plpd_pll_enable_clock(struct
> intel_encoder *encoder,
> 
>  	if (intel_tc_port_in_tbt_alt_mode(dig_port))
>  		intel_mtl_tbt_pll_enable_clock(encoder, crtc_state-
> >port_clock);
> -	else
> -		/* TODO: remove when PLL mgr is in place. */
> -		intel_xe3plpd_pll_enable(encoder, NULL, &crtc_state-
> >dpll_hw_state);
>  }
> 
>  void intel_xe3plpd_pll_disable(struct intel_encoder *encoder) @@ -2298,10
> +2296,6 @@ void intel_xe3plpd_pll_disable_clock(struct intel_encoder
> *encoder)
> 
>  	if (intel_tc_port_in_tbt_alt_mode(dig_port))
>  		intel_mtl_tbt_pll_disable_clock(encoder);
> -	else
> -		/* TODO: remove when PLL mgr is in place. */
> -		intel_xe3plpd_pll_disable(encoder);
> -
>  }
> 
>  static void intel_lt_phy_pll_verify_clock(struct intel_display *display,
> --
> 2.43.0

✗ CI.checkpatch: warning for Refactor LT PHY PLL handling to use DPLL framework (rev2)

[Patchwork]

== Series Details ==

Series: Refactor LT PHY PLL handling to use DPLL framework (rev2)
URL   : https://patchwork.freedesktop.org/series/161586/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
1f57ba1afceae32108bd24770069f764d940a0e4
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 4ef8f7bd6cb9707138ba9e53dd4661bbd49b4fc7
Author: Mika Kahola <mika.kahola@intel.com>
Date:   Wed Mar 4 13:14:23 2026 +0000

    drm/i915/lt_phy: Enable dpll framework for xe3plpd
    
    xe3plpd platform is supported by dpll framework remove a separate
    check for hw comparison and rely solely on dpll framework
    hw comparison.
    
    Finally, all required hooks are now in place so initialize
    PLL manager for xe3plpd platform and remove the redirections
    to the legacy code paths for clock enable/disable as well as
    state mismatch checks that are no longer needed.
    
    Signed-off-by: Mika Kahola <mika.kahola@intel.com>
+ /mt/dim checkpatch 5bd71a4c0dc55d4f935fce39a7b5f604d1a67183 drm-intel
7b58eeb1fe63 drm/i915/lt_phy: Dump missing PLL state parameters
88640f9e0cf2 drm/i915/lt_phy: Add check if PLL is enabled
cccdcc11fa59 drm/i915/lt_phy: Add PLL information for xe3plpd
54465ff5827d drm/i915/lt_phy: Refactor LT PHY PLL handling to use explicit PLL state
db70ecd3b57a drm/i915/lt_phy: Add lane_count to PLL state
b304abbf2494 drm/i915/lt_phy: Add xe3plpd .compute_dplls hook
887e28203f88 drm/i915/lt_phy: Add xe3plpd .get_dplls hook
663b76c0d489 drm/i915/lt_phy: Add xe3plpd .put_dplls hook
3cdcf6d8b136 drm/i915/lt_phy: Add xe3plpd .update_active_dpll hook
1371ab163b94 drm/i915/lt_phy: Add xe3plpd .update_dpll_ref_clks hook
d6c5efd1e12a drm/i915/lt_phy: Add xe3plpd .dump_hw_state hook
7fff3b44ed20 drm/i915/lt_phy: Add xe3plpd .compare_hw_state hook
087636513ffb drm/i915/lt_phy: Add xe3plpd .get_hw_state hook
046386c67c11 drm/i915/lt_phy: Add xe3plpd .get_freq hook
cc96212b2240 drm/i915/lt_phy: Add xe3plpd .crtc_get_dpll
a9b6b88d96c7 drm/i915/lt_phy: Replace crtc compute clock
6bbd6f87d7cb drm/i915/lt_phy: Add .enable_clock hook on DDI
5aad04983151 drm/i915/lt_phy: Add .disable_clock hook on DDI
69af7a944662 drm/i915/lt_phy: Dump lane count for HW state
930d0676c6a1 drm/i915/lt_phy: Readout lane count
a7bded2578e7 drm/i915/lt_phy: Get encoder configuration for xe3plpd platform
1c12a81af8d7 drm/i915/lt_phy: Add xe3plpd Thunderbolt pll hooks
ff549f3db077 drm/i915/lt_phy: Remove LT PHY specific state verification
-:25: WARNING:LONG_LINE: line length of 123 exceeds 100 columns
#25: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:5121:
+				     !intel_lt_phy_pll_compare_hw_state(&pll->state.hw_state.ltpll, &dpll_hw_state.ltpll) :

-:26: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#26: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:5122:
+				     memcmp(&pll->state.hw_state, &dpll_hw_state, sizeof(dpll_hw_state)),

total: 0 errors, 2 warnings, 0 checks, 71 lines checked
4ef8f7bd6cb9 drm/i915/lt_phy: Enable dpll framework for xe3plpd

✓ CI.KUnit: success for Refactor LT PHY PLL handling to use DPLL framework (rev2)

[Patchwork]

== Series Details ==

Series: Refactor LT PHY PLL handling to use DPLL framework (rev2)
URL   : https://patchwork.freedesktop.org/series/161586/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[17:15:27] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[17:15:32] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[17:16:02] Starting KUnit Kernel (1/1)...
[17:16:02] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[17:16:02] ================== guc_buf (11 subtests) ===================
[17:16:02] [PASSED] test_smallest
[17:16:02] [PASSED] test_largest
[17:16:02] [PASSED] test_granular
[17:16:02] [PASSED] test_unique
[17:16:02] [PASSED] test_overlap
[17:16:02] [PASSED] test_reusable
[17:16:02] [PASSED] test_too_big
[17:16:02] [PASSED] test_flush
[17:16:02] [PASSED] test_lookup
[17:16:02] [PASSED] test_data
[17:16:02] [PASSED] test_class
[17:16:02] ===================== [PASSED] guc_buf =====================
[17:16:02] =================== guc_dbm (7 subtests) ===================
[17:16:02] [PASSED] test_empty
[17:16:02] [PASSED] test_default
[17:16:02] ======================== test_size  ========================
[17:16:02] [PASSED] 4
[17:16:02] [PASSED] 8
[17:16:02] [PASSED] 32
[17:16:02] [PASSED] 256
[17:16:02] ==================== [PASSED] test_size ====================
[17:16:02] ======================= test_reuse  ========================
[17:16:02] [PASSED] 4
[17:16:02] [PASSED] 8
[17:16:02] [PASSED] 32
[17:16:02] [PASSED] 256
[17:16:02] =================== [PASSED] test_reuse ====================
[17:16:02] =================== test_range_overlap  ====================
[17:16:02] [PASSED] 4
[17:16:02] [PASSED] 8
[17:16:02] [PASSED] 32
[17:16:02] [PASSED] 256
[17:16:02] =============== [PASSED] test_range_overlap ================
[17:16:02] =================== test_range_compact  ====================
[17:16:02] [PASSED] 4
[17:16:02] [PASSED] 8
[17:16:02] [PASSED] 32
[17:16:02] [PASSED] 256
[17:16:02] =============== [PASSED] test_range_compact ================
[17:16:02] ==================== test_range_spare  =====================
[17:16:02] [PASSED] 4
[17:16:02] [PASSED] 8
[17:16:02] [PASSED] 32
[17:16:02] [PASSED] 256
[17:16:02] ================ [PASSED] test_range_spare =================
[17:16:02] ===================== [PASSED] guc_dbm =====================
[17:16:02] =================== guc_idm (6 subtests) ===================
[17:16:02] [PASSED] bad_init
[17:16:02] [PASSED] no_init
[17:16:02] [PASSED] init_fini
[17:16:02] [PASSED] check_used
[17:16:02] [PASSED] check_quota
[17:16:02] [PASSED] check_all
[17:16:02] ===================== [PASSED] guc_idm =====================
[17:16:02] ================== no_relay (3 subtests) ===================
[17:16:02] [PASSED] xe_drops_guc2pf_if_not_ready
[17:16:02] [PASSED] xe_drops_guc2vf_if_not_ready
[17:16:02] [PASSED] xe_rejects_send_if_not_ready
[17:16:02] ==================== [PASSED] no_relay =====================
[17:16:02] ================== pf_relay (14 subtests) ==================
[17:16:02] [PASSED] pf_rejects_guc2pf_too_short
[17:16:02] [PASSED] pf_rejects_guc2pf_too_long
[17:16:02] [PASSED] pf_rejects_guc2pf_no_payload
[17:16:02] [PASSED] pf_fails_no_payload
[17:16:02] [PASSED] pf_fails_bad_origin
[17:16:02] [PASSED] pf_fails_bad_type
[17:16:02] [PASSED] pf_txn_reports_error
[17:16:02] [PASSED] pf_txn_sends_pf2guc
[17:16:02] [PASSED] pf_sends_pf2guc
[17:16:02] [SKIPPED] pf_loopback_nop
[17:16:02] [SKIPPED] pf_loopback_echo
[17:16:02] [SKIPPED] pf_loopback_fail
[17:16:02] [SKIPPED] pf_loopback_busy
[17:16:02] [SKIPPED] pf_loopback_retry
[17:16:02] ==================== [PASSED] pf_relay =====================
[17:16:02] ================== vf_relay (3 subtests) ===================
[17:16:02] [PASSED] vf_rejects_guc2vf_too_short
[17:16:02] [PASSED] vf_rejects_guc2vf_too_long
[17:16:02] [PASSED] vf_rejects_guc2vf_no_payload
[17:16:02] ==================== [PASSED] vf_relay =====================
[17:16:02] ================ pf_gt_config (9 subtests) =================
[17:16:02] [PASSED] fair_contexts_1vf
[17:16:02] [PASSED] fair_doorbells_1vf
[17:16:02] [PASSED] fair_ggtt_1vf
[17:16:02] ====================== fair_vram_1vf  ======================
[17:16:02] [PASSED] 3.50 GiB
[17:16:02] [PASSED] 11.5 GiB
[17:16:02] [PASSED] 15.5 GiB
[17:16:02] [PASSED] 31.5 GiB
[17:16:02] [PASSED] 63.5 GiB
[17:16:02] [PASSED] 1.91 GiB
[17:16:02] ================== [PASSED] fair_vram_1vf ==================
[17:16:02] ================ fair_vram_1vf_admin_only  =================
[17:16:02] [PASSED] 3.50 GiB
[17:16:02] [PASSED] 11.5 GiB
[17:16:02] [PASSED] 15.5 GiB
[17:16:02] [PASSED] 31.5 GiB
[17:16:02] [PASSED] 63.5 GiB
[17:16:02] [PASSED] 1.91 GiB
[17:16:02] ============ [PASSED] fair_vram_1vf_admin_only =============
[17:16:02] ====================== fair_contexts  ======================
[17:16:02] [PASSED] 1 VF
[17:16:02] [PASSED] 2 VFs
[17:16:02] [PASSED] 3 VFs
[17:16:02] [PASSED] 4 VFs
[17:16:02] [PASSED] 5 VFs
[17:16:02] [PASSED] 6 VFs
[17:16:02] [PASSED] 7 VFs
[17:16:02] [PASSED] 8 VFs
[17:16:02] [PASSED] 9 VFs
[17:16:02] [PASSED] 10 VFs
[17:16:02] [PASSED] 11 VFs
[17:16:02] [PASSED] 12 VFs
[17:16:02] [PASSED] 13 VFs
[17:16:02] [PASSED] 14 VFs
[17:16:02] [PASSED] 15 VFs
[17:16:02] [PASSED] 16 VFs
[17:16:02] [PASSED] 17 VFs
[17:16:02] [PASSED] 18 VFs
[17:16:02] [PASSED] 19 VFs
[17:16:02] [PASSED] 20 VFs
[17:16:02] [PASSED] 21 VFs
[17:16:02] [PASSED] 22 VFs
[17:16:02] [PASSED] 23 VFs
[17:16:02] [PASSED] 24 VFs
[17:16:02] [PASSED] 25 VFs
[17:16:02] [PASSED] 26 VFs
[17:16:02] [PASSED] 27 VFs
[17:16:02] [PASSED] 28 VFs
[17:16:02] [PASSED] 29 VFs
[17:16:02] [PASSED] 30 VFs
[17:16:02] [PASSED] 31 VFs
[17:16:02] [PASSED] 32 VFs
[17:16:02] [PASSED] 33 VFs
[17:16:02] [PASSED] 34 VFs
[17:16:02] [PASSED] 35 VFs
[17:16:02] [PASSED] 36 VFs
[17:16:02] [PASSED] 37 VFs
[17:16:02] [PASSED] 38 VFs
[17:16:02] [PASSED] 39 VFs
[17:16:02] [PASSED] 40 VFs
[17:16:02] [PASSED] 41 VFs
[17:16:02] [PASSED] 42 VFs
[17:16:02] [PASSED] 43 VFs
[17:16:02] [PASSED] 44 VFs
[17:16:02] [PASSED] 45 VFs
[17:16:02] [PASSED] 46 VFs
[17:16:02] [PASSED] 47 VFs
[17:16:02] [PASSED] 48 VFs
[17:16:02] [PASSED] 49 VFs
[17:16:02] [PASSED] 50 VFs
[17:16:02] [PASSED] 51 VFs
[17:16:02] [PASSED] 52 VFs
[17:16:02] [PASSED] 53 VFs
[17:16:02] [PASSED] 54 VFs
[17:16:02] [PASSED] 55 VFs
[17:16:02] [PASSED] 56 VFs
[17:16:02] [PASSED] 57 VFs
[17:16:02] [PASSED] 58 VFs
[17:16:02] [PASSED] 59 VFs
[17:16:02] [PASSED] 60 VFs
[17:16:02] [PASSED] 61 VFs
[17:16:02] [PASSED] 62 VFs
[17:16:02] [PASSED] 63 VFs
[17:16:02] ================== [PASSED] fair_contexts ==================
[17:16:02] ===================== fair_doorbells  ======================
[17:16:02] [PASSED] 1 VF
[17:16:02] [PASSED] 2 VFs
[17:16:02] [PASSED] 3 VFs
[17:16:02] [PASSED] 4 VFs
[17:16:02] [PASSED] 5 VFs
[17:16:02] [PASSED] 6 VFs
[17:16:02] [PASSED] 7 VFs
[17:16:02] [PASSED] 8 VFs
[17:16:02] [PASSED] 9 VFs
[17:16:02] [PASSED] 10 VFs
[17:16:02] [PASSED] 11 VFs
[17:16:02] [PASSED] 12 VFs
[17:16:02] [PASSED] 13 VFs
[17:16:02] [PASSED] 14 VFs
[17:16:02] [PASSED] 15 VFs
[17:16:02] [PASSED] 16 VFs
[17:16:02] [PASSED] 17 VFs
[17:16:02] [PASSED] 18 VFs
[17:16:02] [PASSED] 19 VFs
[17:16:02] [PASSED] 20 VFs
[17:16:02] [PASSED] 21 VFs
[17:16:02] [PASSED] 22 VFs
[17:16:02] [PASSED] 23 VFs
[17:16:02] [PASSED] 24 VFs
[17:16:02] [PASSED] 25 VFs
[17:16:02] [PASSED] 26 VFs
[17:16:02] [PASSED] 27 VFs
[17:16:02] [PASSED] 28 VFs
[17:16:02] [PASSED] 29 VFs
[17:16:02] [PASSED] 30 VFs
[17:16:02] [PASSED] 31 VFs
[17:16:02] [PASSED] 32 VFs
[17:16:02] [PASSED] 33 VFs
[17:16:02] [PASSED] 34 VFs
[17:16:02] [PASSED] 35 VFs
[17:16:02] [PASSED] 36 VFs
[17:16:02] [PASSED] 37 VFs
[17:16:02] [PASSED] 38 VFs
[17:16:02] [PASSED] 39 VFs
[17:16:02] [PASSED] 40 VFs
[17:16:02] [PASSED] 41 VFs
[17:16:02] [PASSED] 42 VFs
[17:16:02] [PASSED] 43 VFs
[17:16:02] [PASSED] 44 VFs
[17:16:02] [PASSED] 45 VFs
[17:16:02] [PASSED] 46 VFs
[17:16:02] [PASSED] 47 VFs
[17:16:02] [PASSED] 48 VFs
[17:16:02] [PASSED] 49 VFs
[17:16:02] [PASSED] 50 VFs
[17:16:02] [PASSED] 51 VFs
[17:16:02] [PASSED] 52 VFs
[17:16:02] [PASSED] 53 VFs
[17:16:02] [PASSED] 54 VFs
[17:16:02] [PASSED] 55 VFs
[17:16:02] [PASSED] 56 VFs
[17:16:02] [PASSED] 57 VFs
[17:16:02] [PASSED] 58 VFs
[17:16:02] [PASSED] 59 VFs
[17:16:02] [PASSED] 60 VFs
[17:16:02] [PASSED] 61 VFs
[17:16:02] [PASSED] 62 VFs
[17:16:02] [PASSED] 63 VFs
[17:16:02] ================= [PASSED] fair_doorbells ==================
[17:16:02] ======================== fair_ggtt  ========================
[17:16:02] [PASSED] 1 VF
[17:16:02] [PASSED] 2 VFs
[17:16:02] [PASSED] 3 VFs
[17:16:02] [PASSED] 4 VFs
[17:16:02] [PASSED] 5 VFs
[17:16:02] [PASSED] 6 VFs
[17:16:02] [PASSED] 7 VFs
[17:16:02] [PASSED] 8 VFs
[17:16:02] [PASSED] 9 VFs
[17:16:02] [PASSED] 10 VFs
[17:16:02] [PASSED] 11 VFs
[17:16:02] [PASSED] 12 VFs
[17:16:02] [PASSED] 13 VFs
[17:16:02] [PASSED] 14 VFs
[17:16:02] [PASSED] 15 VFs
[17:16:02] [PASSED] 16 VFs
[17:16:02] [PASSED] 17 VFs
[17:16:02] [PASSED] 18 VFs
[17:16:02] [PASSED] 19 VFs
[17:16:02] [PASSED] 20 VFs
[17:16:02] [PASSED] 21 VFs
[17:16:02] [PASSED] 22 VFs
[17:16:02] [PASSED] 23 VFs
[17:16:02] [PASSED] 24 VFs
[17:16:02] [PASSED] 25 VFs
[17:16:02] [PASSED] 26 VFs
[17:16:02] [PASSED] 27 VFs
[17:16:02] [PASSED] 28 VFs
[17:16:02] [PASSED] 29 VFs
[17:16:02] [PASSED] 30 VFs
[17:16:02] [PASSED] 31 VFs
[17:16:02] [PASSED] 32 VFs
[17:16:02] [PASSED] 33 VFs
[17:16:02] [PASSED] 34 VFs
[17:16:02] [PASSED] 35 VFs
[17:16:02] [PASSED] 36 VFs
[17:16:02] [PASSED] 37 VFs
[17:16:02] [PASSED] 38 VFs
[17:16:02] [PASSED] 39 VFs
[17:16:02] [PASSED] 40 VFs
[17:16:02] [PASSED] 41 VFs
[17:16:02] [PASSED] 42 VFs
[17:16:02] [PASSED] 43 VFs
[17:16:02] [PASSED] 44 VFs
[17:16:02] [PASSED] 45 VFs
[17:16:02] [PASSED] 46 VFs
[17:16:02] [PASSED] 47 VFs
[17:16:02] [PASSED] 48 VFs
[17:16:02] [PASSED] 49 VFs
[17:16:02] [PASSED] 50 VFs
[17:16:02] [PASSED] 51 VFs
[17:16:02] [PASSED] 52 VFs
[17:16:02] [PASSED] 53 VFs
[17:16:02] [PASSED] 54 VFs
[17:16:02] [PASSED] 55 VFs
[17:16:02] [PASSED] 56 VFs
[17:16:02] [PASSED] 57 VFs
[17:16:02] [PASSED] 58 VFs
[17:16:02] [PASSED] 59 VFs
[17:16:02] [PASSED] 60 VFs
[17:16:02] [PASSED] 61 VFs
[17:16:02] [PASSED] 62 VFs
[17:16:02] [PASSED] 63 VFs
[17:16:02] ==================== [PASSED] fair_ggtt ====================
[17:16:02] ======================== fair_vram  ========================
[17:16:02] [PASSED] 1 VF
[17:16:02] [PASSED] 2 VFs
[17:16:02] [PASSED] 3 VFs
[17:16:02] [PASSED] 4 VFs
[17:16:02] [PASSED] 5 VFs
[17:16:02] [PASSED] 6 VFs
[17:16:02] [PASSED] 7 VFs
[17:16:02] [PASSED] 8 VFs
[17:16:02] [PASSED] 9 VFs
[17:16:02] [PASSED] 10 VFs
[17:16:02] [PASSED] 11 VFs
[17:16:02] [PASSED] 12 VFs
[17:16:02] [PASSED] 13 VFs
[17:16:02] [PASSED] 14 VFs
[17:16:02] [PASSED] 15 VFs
[17:16:02] [PASSED] 16 VFs
[17:16:02] [PASSED] 17 VFs
[17:16:02] [PASSED] 18 VFs
[17:16:02] [PASSED] 19 VFs
[17:16:02] [PASSED] 20 VFs
[17:16:02] [PASSED] 21 VFs
[17:16:02] [PASSED] 22 VFs
[17:16:02] [PASSED] 23 VFs
[17:16:02] [PASSED] 24 VFs
[17:16:02] [PASSED] 25 VFs
[17:16:03] [PASSED] 26 VFs
[17:16:03] [PASSED] 27 VFs
[17:16:03] [PASSED] 28 VFs
[17:16:03] [PASSED] 29 VFs
[17:16:03] [PASSED] 30 VFs
[17:16:03] [PASSED] 31 VFs
[17:16:03] [PASSED] 32 VFs
[17:16:03] [PASSED] 33 VFs
[17:16:03] [PASSED] 34 VFs
[17:16:03] [PASSED] 35 VFs
[17:16:03] [PASSED] 36 VFs
[17:16:03] [PASSED] 37 VFs
[17:16:03] [PASSED] 38 VFs
[17:16:03] [PASSED] 39 VFs
[17:16:03] [PASSED] 40 VFs
[17:16:03] [PASSED] 41 VFs
[17:16:03] [PASSED] 42 VFs
[17:16:03] [PASSED] 43 VFs
[17:16:03] [PASSED] 44 VFs
[17:16:03] [PASSED] 45 VFs
[17:16:03] [PASSED] 46 VFs
[17:16:03] [PASSED] 47 VFs
[17:16:03] [PASSED] 48 VFs
[17:16:03] [PASSED] 49 VFs
[17:16:03] [PASSED] 50 VFs
[17:16:03] [PASSED] 51 VFs
[17:16:03] [PASSED] 52 VFs
[17:16:03] [PASSED] 53 VFs
[17:16:03] [PASSED] 54 VFs
[17:16:03] [PASSED] 55 VFs
[17:16:03] [PASSED] 56 VFs
[17:16:03] [PASSED] 57 VFs
[17:16:03] [PASSED] 58 VFs
[17:16:03] [PASSED] 59 VFs
[17:16:03] [PASSED] 60 VFs
[17:16:03] [PASSED] 61 VFs
[17:16:03] [PASSED] 62 VFs
[17:16:03] [PASSED] 63 VFs
[17:16:03] ==================== [PASSED] fair_vram ====================
[17:16:03] ================== [PASSED] pf_gt_config ===================
[17:16:03] ===================== lmtt (1 subtest) =====================
[17:16:03] ======================== test_ops  =========================
[17:16:03] [PASSED] 2-level
[17:16:03] [PASSED] multi-level
[17:16:03] ==================== [PASSED] test_ops =====================
[17:16:03] ====================== [PASSED] lmtt =======================
[17:16:03] ================= pf_service (11 subtests) =================
[17:16:03] [PASSED] pf_negotiate_any
[17:16:03] [PASSED] pf_negotiate_base_match
[17:16:03] [PASSED] pf_negotiate_base_newer
[17:16:03] [PASSED] pf_negotiate_base_next
[17:16:03] [SKIPPED] pf_negotiate_base_older
[17:16:03] [PASSED] pf_negotiate_base_prev
[17:16:03] [PASSED] pf_negotiate_latest_match
[17:16:03] [PASSED] pf_negotiate_latest_newer
[17:16:03] [PASSED] pf_negotiate_latest_next
[17:16:03] [SKIPPED] pf_negotiate_latest_older
[17:16:03] [SKIPPED] pf_negotiate_latest_prev
[17:16:03] =================== [PASSED] pf_service ====================
[17:16:03] ================= xe_guc_g2g (2 subtests) ==================
[17:16:03] ============== xe_live_guc_g2g_kunit_default  ==============
[17:16:03] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[17:16:03] ============== xe_live_guc_g2g_kunit_allmem  ===============
[17:16:03] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[17:16:03] =================== [SKIPPED] xe_guc_g2g ===================
[17:16:03] =================== xe_mocs (2 subtests) ===================
[17:16:03] ================ xe_live_mocs_kernel_kunit  ================
[17:16:03] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[17:16:03] ================ xe_live_mocs_reset_kunit  =================
[17:16:03] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[17:16:03] ==================== [SKIPPED] xe_mocs =====================
[17:16:03] ================= xe_migrate (2 subtests) ==================
[17:16:03] ================= xe_migrate_sanity_kunit  =================
[17:16:03] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[17:16:03] ================== xe_validate_ccs_kunit  ==================
[17:16:03] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[17:16:03] =================== [SKIPPED] xe_migrate ===================
[17:16:03] ================== xe_dma_buf (1 subtest) ==================
[17:16:03] ==================== xe_dma_buf_kunit  =====================
[17:16:03] ================ [SKIPPED] xe_dma_buf_kunit ================
[17:16:03] =================== [SKIPPED] xe_dma_buf ===================
[17:16:03] ================= xe_bo_shrink (1 subtest) =================
[17:16:03] =================== xe_bo_shrink_kunit  ====================
[17:16:03] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[17:16:03] ================== [SKIPPED] xe_bo_shrink ==================
[17:16:03] ==================== xe_bo (2 subtests) ====================
[17:16:03] ================== xe_ccs_migrate_kunit  ===================
[17:16:03] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[17:16:03] ==================== xe_bo_evict_kunit  ====================
[17:16:03] =============== [SKIPPED] xe_bo_evict_kunit ================
[17:16:03] ===================== [SKIPPED] xe_bo ======================
[17:16:03] ==================== args (13 subtests) ====================
[17:16:03] [PASSED] count_args_test
[17:16:03] [PASSED] call_args_example
[17:16:03] [PASSED] call_args_test
[17:16:03] [PASSED] drop_first_arg_example
[17:16:03] [PASSED] drop_first_arg_test
[17:16:03] [PASSED] first_arg_example
[17:16:03] [PASSED] first_arg_test
[17:16:03] [PASSED] last_arg_example
[17:16:03] [PASSED] last_arg_test
[17:16:03] [PASSED] pick_arg_example
[17:16:03] [PASSED] if_args_example
[17:16:03] [PASSED] if_args_test
[17:16:03] [PASSED] sep_comma_example
[17:16:03] ====================== [PASSED] args =======================
[17:16:03] =================== xe_pci (3 subtests) ====================
[17:16:03] ==================== check_graphics_ip  ====================
[17:16:03] [PASSED] 12.00 Xe_LP
[17:16:03] [PASSED] 12.10 Xe_LP+
[17:16:03] [PASSED] 12.55 Xe_HPG
[17:16:03] [PASSED] 12.60 Xe_HPC
[17:16:03] [PASSED] 12.70 Xe_LPG
[17:16:03] [PASSED] 12.71 Xe_LPG
[17:16:03] [PASSED] 12.74 Xe_LPG+
[17:16:03] [PASSED] 20.01 Xe2_HPG
[17:16:03] [PASSED] 20.02 Xe2_HPG
[17:16:03] [PASSED] 20.04 Xe2_LPG
[17:16:03] [PASSED] 30.00 Xe3_LPG
[17:16:03] [PASSED] 30.01 Xe3_LPG
[17:16:03] [PASSED] 30.03 Xe3_LPG
[17:16:03] [PASSED] 30.04 Xe3_LPG
[17:16:03] [PASSED] 30.05 Xe3_LPG
[17:16:03] [PASSED] 35.10 Xe3p_LPG
[17:16:03] [PASSED] 35.11 Xe3p_XPC
[17:16:03] ================ [PASSED] check_graphics_ip ================
[17:16:03] ===================== check_media_ip  ======================
[17:16:03] [PASSED] 12.00 Xe_M
[17:16:03] [PASSED] 12.55 Xe_HPM
[17:16:03] [PASSED] 13.00 Xe_LPM+
[17:16:03] [PASSED] 13.01 Xe2_HPM
[17:16:03] [PASSED] 20.00 Xe2_LPM
[17:16:03] [PASSED] 30.00 Xe3_LPM
[17:16:03] [PASSED] 30.02 Xe3_LPM
[17:16:03] [PASSED] 35.00 Xe3p_LPM
[17:16:03] [PASSED] 35.03 Xe3p_HPM
[17:16:03] ================= [PASSED] check_media_ip ==================
[17:16:03] =================== check_platform_desc  ===================
[17:16:03] [PASSED] 0x9A60 (TIGERLAKE)
[17:16:03] [PASSED] 0x9A68 (TIGERLAKE)
[17:16:03] [PASSED] 0x9A70 (TIGERLAKE)
[17:16:03] [PASSED] 0x9A40 (TIGERLAKE)
[17:16:03] [PASSED] 0x9A49 (TIGERLAKE)
[17:16:03] [PASSED] 0x9A59 (TIGERLAKE)
[17:16:03] [PASSED] 0x9A78 (TIGERLAKE)
[17:16:03] [PASSED] 0x9AC0 (TIGERLAKE)
[17:16:03] [PASSED] 0x9AC9 (TIGERLAKE)
[17:16:03] [PASSED] 0x9AD9 (TIGERLAKE)
[17:16:03] [PASSED] 0x9AF8 (TIGERLAKE)
[17:16:03] [PASSED] 0x4C80 (ROCKETLAKE)
[17:16:03] [PASSED] 0x4C8A (ROCKETLAKE)
[17:16:03] [PASSED] 0x4C8B (ROCKETLAKE)
[17:16:03] [PASSED] 0x4C8C (ROCKETLAKE)
[17:16:03] [PASSED] 0x4C90 (ROCKETLAKE)
[17:16:03] [PASSED] 0x4C9A (ROCKETLAKE)
[17:16:03] [PASSED] 0x4680 (ALDERLAKE_S)
[17:16:03] [PASSED] 0x4682 (ALDERLAKE_S)
[17:16:03] [PASSED] 0x4688 (ALDERLAKE_S)
[17:16:03] [PASSED] 0x468A (ALDERLAKE_S)
[17:16:03] [PASSED] 0x468B (ALDERLAKE_S)
[17:16:03] [PASSED] 0x4690 (ALDERLAKE_S)
[17:16:03] [PASSED] 0x4692 (ALDERLAKE_S)
[17:16:03] [PASSED] 0x4693 (ALDERLAKE_S)
[17:16:03] [PASSED] 0x46A0 (ALDERLAKE_P)
[17:16:03] [PASSED] 0x46A1 (ALDERLAKE_P)
[17:16:03] [PASSED] 0x46A2 (ALDERLAKE_P)
[17:16:03] [PASSED] 0x46A3 (ALDERLAKE_P)
[17:16:03] [PASSED] 0x46A6 (ALDERLAKE_P)
[17:16:03] [PASSED] 0x46A8 (ALDERLAKE_P)
[17:16:03] [PASSED] 0x46AA (ALDERLAKE_P)
[17:16:03] [PASSED] 0x462A (ALDERLAKE_P)
[17:16:03] [PASSED] 0x4626 (ALDERLAKE_P)
[17:16:03] [PASSED] 0x4628 (ALDERLAKE_P)
[17:16:03] [PASSED] 0x46B0 (ALDERLAKE_P)
[17:16:03] [PASSED] 0x46B1 (ALDERLAKE_P)
[17:16:03] [PASSED] 0x46B2 (ALDERLAKE_P)
[17:16:03] [PASSED] 0x46B3 (ALDERLAKE_P)
[17:16:03] [PASSED] 0x46C0 (ALDERLAKE_P)
[17:16:03] [PASSED] 0x46C1 (ALDERLAKE_P)
[17:16:03] [PASSED] 0x46C2 (ALDERLAKE_P)
[17:16:03] [PASSED] 0x46C3 (ALDERLAKE_P)
[17:16:03] [PASSED] 0x46D0 (ALDERLAKE_N)
[17:16:03] [PASSED] 0x46D1 (ALDERLAKE_N)
[17:16:03] [PASSED] 0x46D2 (ALDERLAKE_N)
[17:16:03] [PASSED] 0x46D3 (ALDERLAKE_N)
[17:16:03] [PASSED] 0x46D4 (ALDERLAKE_N)
[17:16:03] [PASSED] 0xA721 (ALDERLAKE_P)
[17:16:03] [PASSED] 0xA7A1 (ALDERLAKE_P)
[17:16:03] [PASSED] 0xA7A9 (ALDERLAKE_P)
[17:16:03] [PASSED] 0xA7AC (ALDERLAKE_P)
[17:16:03] [PASSED] 0xA7AD (ALDERLAKE_P)
[17:16:03] [PASSED] 0xA720 (ALDERLAKE_P)
[17:16:03] [PASSED] 0xA7A0 (ALDERLAKE_P)
[17:16:03] [PASSED] 0xA7A8 (ALDERLAKE_P)
[17:16:03] [PASSED] 0xA7AA (ALDERLAKE_P)
[17:16:03] [PASSED] 0xA7AB (ALDERLAKE_P)
[17:16:03] [PASSED] 0xA780 (ALDERLAKE_S)
[17:16:03] [PASSED] 0xA781 (ALDERLAKE_S)
[17:16:03] [PASSED] 0xA782 (ALDERLAKE_S)
[17:16:03] [PASSED] 0xA783 (ALDERLAKE_S)
[17:16:03] [PASSED] 0xA788 (ALDERLAKE_S)
[17:16:03] [PASSED] 0xA789 (ALDERLAKE_S)
[17:16:03] [PASSED] 0xA78A (ALDERLAKE_S)
[17:16:03] [PASSED] 0xA78B (ALDERLAKE_S)
[17:16:03] [PASSED] 0x4905 (DG1)
[17:16:03] [PASSED] 0x4906 (DG1)
[17:16:03] [PASSED] 0x4907 (DG1)
[17:16:03] [PASSED] 0x4908 (DG1)
[17:16:03] [PASSED] 0x4909 (DG1)
[17:16:03] [PASSED] 0x56C0 (DG2)
[17:16:03] [PASSED] 0x56C2 (DG2)
[17:16:03] [PASSED] 0x56C1 (DG2)
[17:16:03] [PASSED] 0x7D51 (METEORLAKE)
[17:16:03] [PASSED] 0x7DD1 (METEORLAKE)
[17:16:03] [PASSED] 0x7D41 (METEORLAKE)
[17:16:03] [PASSED] 0x7D67 (METEORLAKE)
[17:16:03] [PASSED] 0xB640 (METEORLAKE)
[17:16:03] [PASSED] 0x56A0 (DG2)
[17:16:03] [PASSED] 0x56A1 (DG2)
[17:16:03] [PASSED] 0x56A2 (DG2)
[17:16:03] [PASSED] 0x56BE (DG2)
[17:16:03] [PASSED] 0x56BF (DG2)
[17:16:03] [PASSED] 0x5690 (DG2)
[17:16:03] [PASSED] 0x5691 (DG2)
[17:16:03] [PASSED] 0x5692 (DG2)
[17:16:03] [PASSED] 0x56A5 (DG2)
[17:16:03] [PASSED] 0x56A6 (DG2)
[17:16:03] [PASSED] 0x56B0 (DG2)
[17:16:03] [PASSED] 0x56B1 (DG2)
[17:16:03] [PASSED] 0x56BA (DG2)
[17:16:03] [PASSED] 0x56BB (DG2)
[17:16:03] [PASSED] 0x56BC (DG2)
[17:16:03] [PASSED] 0x56BD (DG2)
[17:16:03] [PASSED] 0x5693 (DG2)
[17:16:03] [PASSED] 0x5694 (DG2)
[17:16:03] [PASSED] 0x5695 (DG2)
[17:16:03] [PASSED] 0x56A3 (DG2)
[17:16:03] [PASSED] 0x56A4 (DG2)
[17:16:03] [PASSED] 0x56B2 (DG2)
[17:16:03] [PASSED] 0x56B3 (DG2)
[17:16:03] [PASSED] 0x5696 (DG2)
[17:16:03] [PASSED] 0x5697 (DG2)
[17:16:03] [PASSED] 0xB69 (PVC)
[17:16:03] [PASSED] 0xB6E (PVC)
[17:16:03] [PASSED] 0xBD4 (PVC)
[17:16:03] [PASSED] 0xBD5 (PVC)
[17:16:03] [PASSED] 0xBD6 (PVC)
[17:16:03] [PASSED] 0xBD7 (PVC)
[17:16:03] [PASSED] 0xBD8 (PVC)
[17:16:03] [PASSED] 0xBD9 (PVC)
[17:16:03] [PASSED] 0xBDA (PVC)
[17:16:03] [PASSED] 0xBDB (PVC)
[17:16:03] [PASSED] 0xBE0 (PVC)
[17:16:03] [PASSED] 0xBE1 (PVC)
[17:16:03] [PASSED] 0xBE5 (PVC)
[17:16:03] [PASSED] 0x7D40 (METEORLAKE)
[17:16:03] [PASSED] 0x7D45 (METEORLAKE)
[17:16:03] [PASSED] 0x7D55 (METEORLAKE)
[17:16:03] [PASSED] 0x7D60 (METEORLAKE)
[17:16:03] [PASSED] 0x7DD5 (METEORLAKE)
[17:16:03] [PASSED] 0x6420 (LUNARLAKE)
[17:16:03] [PASSED] 0x64A0 (LUNARLAKE)
[17:16:03] [PASSED] 0x64B0 (LUNARLAKE)
[17:16:03] [PASSED] 0xE202 (BATTLEMAGE)
[17:16:03] [PASSED] 0xE209 (BATTLEMAGE)
[17:16:03] [PASSED] 0xE20B (BATTLEMAGE)
[17:16:03] [PASSED] 0xE20C (BATTLEMAGE)
[17:16:03] [PASSED] 0xE20D (BATTLEMAGE)
[17:16:03] [PASSED] 0xE210 (BATTLEMAGE)
[17:16:03] [PASSED] 0xE211 (BATTLEMAGE)
[17:16:03] [PASSED] 0xE212 (BATTLEMAGE)
[17:16:03] [PASSED] 0xE216 (BATTLEMAGE)
[17:16:03] [PASSED] 0xE220 (BATTLEMAGE)
[17:16:03] [PASSED] 0xE221 (BATTLEMAGE)
[17:16:03] [PASSED] 0xE222 (BATTLEMAGE)
[17:16:03] [PASSED] 0xE223 (BATTLEMAGE)
[17:16:03] [PASSED] 0xB080 (PANTHERLAKE)
[17:16:03] [PASSED] 0xB081 (PANTHERLAKE)
[17:16:03] [PASSED] 0xB082 (PANTHERLAKE)
[17:16:03] [PASSED] 0xB083 (PANTHERLAKE)
[17:16:03] [PASSED] 0xB084 (PANTHERLAKE)
[17:16:03] [PASSED] 0xB085 (PANTHERLAKE)
[17:16:03] [PASSED] 0xB086 (PANTHERLAKE)
[17:16:03] [PASSED] 0xB087 (PANTHERLAKE)
[17:16:03] [PASSED] 0xB08F (PANTHERLAKE)
[17:16:03] [PASSED] 0xB090 (PANTHERLAKE)
[17:16:03] [PASSED] 0xB0A0 (PANTHERLAKE)
[17:16:03] [PASSED] 0xB0B0 (PANTHERLAKE)
[17:16:03] [PASSED] 0xFD80 (PANTHERLAKE)
[17:16:03] [PASSED] 0xFD81 (PANTHERLAKE)
[17:16:03] [PASSED] 0xD740 (NOVALAKE_S)
[17:16:03] [PASSED] 0xD741 (NOVALAKE_S)
[17:16:03] [PASSED] 0xD742 (NOVALAKE_S)
[17:16:03] [PASSED] 0xD743 (NOVALAKE_S)
[17:16:03] [PASSED] 0xD744 (NOVALAKE_S)
[17:16:03] [PASSED] 0xD745 (NOVALAKE_S)
[17:16:03] [PASSED] 0x674C (CRESCENTISLAND)
[17:16:03] [PASSED] 0xD750 (NOVALAKE_P)
[17:16:03] [PASSED] 0xD751 (NOVALAKE_P)
[17:16:03] [PASSED] 0xD752 (NOVALAKE_P)
[17:16:03] [PASSED] 0xD753 (NOVALAKE_P)
[17:16:03] [PASSED] 0xD754 (NOVALAKE_P)
[17:16:03] [PASSED] 0xD755 (NOVALAKE_P)
[17:16:03] [PASSED] 0xD756 (NOVALAKE_P)
[17:16:03] [PASSED] 0xD757 (NOVALAKE_P)
[17:16:03] [PASSED] 0xD75F (NOVALAKE_P)
[17:16:03] =============== [PASSED] check_platform_desc ===============
[17:16:03] ===================== [PASSED] xe_pci ======================
[17:16:03] =================== xe_rtp (2 subtests) ====================
[17:16:03] =============== xe_rtp_process_to_sr_tests  ================
[17:16:03] [PASSED] coalesce-same-reg
[17:16:03] [PASSED] no-match-no-add
[17:16:03] [PASSED] match-or
[17:16:03] [PASSED] match-or-xfail
[17:16:03] [PASSED] no-match-no-add-multiple-rules
[17:16:03] [PASSED] two-regs-two-entries
[17:16:03] [PASSED] clr-one-set-other
[17:16:03] [PASSED] set-field
[17:16:03] [PASSED] conflict-duplicate
stty: 'standard input': Inappropriate ioctl for device
[17:16:03] [PASSED] conflict-not-disjoint
[17:16:03] [PASSED] conflict-reg-type
[17:16:03] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[17:16:03] ================== xe_rtp_process_tests  ===================
[17:16:03] [PASSED] active1
[17:16:03] [PASSED] active2
[17:16:03] [PASSED] active-inactive
[17:16:03] [PASSED] inactive-active
[17:16:03] [PASSED] inactive-1st_or_active-inactive
[17:16:03] [PASSED] inactive-2nd_or_active-inactive
[17:16:03] [PASSED] inactive-last_or_active-inactive
[17:16:03] [PASSED] inactive-no_or_active-inactive
[17:16:03] ============== [PASSED] xe_rtp_process_tests ===============
[17:16:03] ===================== [PASSED] xe_rtp ======================
[17:16:03] ==================== xe_wa (1 subtest) =====================
[17:16:03] ======================== xe_wa_gt  =========================
[17:16:03] [PASSED] TIGERLAKE B0
[17:16:03] [PASSED] DG1 A0
[17:16:03] [PASSED] DG1 B0
[17:16:03] [PASSED] ALDERLAKE_S A0
[17:16:03] [PASSED] ALDERLAKE_S B0
[17:16:03] [PASSED] ALDERLAKE_S C0
[17:16:03] [PASSED] ALDERLAKE_S D0
[17:16:03] [PASSED] ALDERLAKE_P A0
[17:16:03] [PASSED] ALDERLAKE_P B0
[17:16:03] [PASSED] ALDERLAKE_P C0
[17:16:03] [PASSED] ALDERLAKE_S RPLS D0
[17:16:03] [PASSED] ALDERLAKE_P RPLU E0
[17:16:03] [PASSED] DG2 G10 C0
[17:16:03] [PASSED] DG2 G11 B1
[17:16:03] [PASSED] DG2 G12 A1
[17:16:03] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[17:16:03] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[17:16:03] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[17:16:03] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[17:16:03] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[17:16:03] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[17:16:03] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[17:16:03] ==================== [PASSED] xe_wa_gt =====================
[17:16:03] ====================== [PASSED] xe_wa ======================
[17:16:03] ============================================================
[17:16:03] Testing complete. Ran 597 tests: passed: 579, skipped: 18
[17:16:03] Elapsed time: 35.305s total, 4.281s configuring, 30.406s building, 0.612s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[17:16:03] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[17:16:04] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[17:16:29] Starting KUnit Kernel (1/1)...
[17:16:29] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[17:16:29] ============ drm_test_pick_cmdline (2 subtests) ============
[17:16:29] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[17:16:29] =============== drm_test_pick_cmdline_named  ===============
[17:16:29] [PASSED] NTSC
[17:16:29] [PASSED] NTSC-J
[17:16:29] [PASSED] PAL
[17:16:29] [PASSED] PAL-M
[17:16:29] =========== [PASSED] drm_test_pick_cmdline_named ===========
[17:16:29] ============== [PASSED] drm_test_pick_cmdline ==============
[17:16:29] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[17:16:29] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[17:16:29] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[17:16:29] =========== drm_validate_clone_mode (2 subtests) ===========
[17:16:29] ============== drm_test_check_in_clone_mode  ===============
[17:16:29] [PASSED] in_clone_mode
[17:16:29] [PASSED] not_in_clone_mode
[17:16:29] ========== [PASSED] drm_test_check_in_clone_mode ===========
[17:16:29] =============== drm_test_check_valid_clones  ===============
[17:16:29] [PASSED] not_in_clone_mode
[17:16:29] [PASSED] valid_clone
[17:16:29] [PASSED] invalid_clone
[17:16:29] =========== [PASSED] drm_test_check_valid_clones ===========
[17:16:29] ============= [PASSED] drm_validate_clone_mode =============
[17:16:29] ============= drm_validate_modeset (1 subtest) =============
[17:16:29] [PASSED] drm_test_check_connector_changed_modeset
[17:16:29] ============== [PASSED] drm_validate_modeset ===============
[17:16:29] ====== drm_test_bridge_get_current_state (2 subtests) ======
[17:16:29] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[17:16:29] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[17:16:29] ======== [PASSED] drm_test_bridge_get_current_state ========
[17:16:29] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[17:16:29] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[17:16:29] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[17:16:29] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[17:16:29] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[17:16:29] ============== drm_bridge_alloc (2 subtests) ===============
[17:16:29] [PASSED] drm_test_drm_bridge_alloc_basic
[17:16:29] [PASSED] drm_test_drm_bridge_alloc_get_put
[17:16:29] ================ [PASSED] drm_bridge_alloc =================
[17:16:29] ============= drm_cmdline_parser (40 subtests) =============
[17:16:29] [PASSED] drm_test_cmdline_force_d_only
[17:16:29] [PASSED] drm_test_cmdline_force_D_only_dvi
[17:16:29] [PASSED] drm_test_cmdline_force_D_only_hdmi
[17:16:29] [PASSED] drm_test_cmdline_force_D_only_not_digital
[17:16:29] [PASSED] drm_test_cmdline_force_e_only
[17:16:29] [PASSED] drm_test_cmdline_res
[17:16:29] [PASSED] drm_test_cmdline_res_vesa
[17:16:29] [PASSED] drm_test_cmdline_res_vesa_rblank
[17:16:29] [PASSED] drm_test_cmdline_res_rblank
[17:16:29] [PASSED] drm_test_cmdline_res_bpp
[17:16:29] [PASSED] drm_test_cmdline_res_refresh
[17:16:29] [PASSED] drm_test_cmdline_res_bpp_refresh
[17:16:29] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[17:16:29] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[17:16:29] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[17:16:29] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[17:16:29] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[17:16:29] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[17:16:29] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[17:16:29] [PASSED] drm_test_cmdline_res_margins_force_on
[17:16:29] [PASSED] drm_test_cmdline_res_vesa_margins
[17:16:29] [PASSED] drm_test_cmdline_name
[17:16:29] [PASSED] drm_test_cmdline_name_bpp
[17:16:29] [PASSED] drm_test_cmdline_name_option
[17:16:29] [PASSED] drm_test_cmdline_name_bpp_option
[17:16:29] [PASSED] drm_test_cmdline_rotate_0
[17:16:29] [PASSED] drm_test_cmdline_rotate_90
[17:16:29] [PASSED] drm_test_cmdline_rotate_180
[17:16:29] [PASSED] drm_test_cmdline_rotate_270
[17:16:29] [PASSED] drm_test_cmdline_hmirror
[17:16:29] [PASSED] drm_test_cmdline_vmirror
[17:16:29] [PASSED] drm_test_cmdline_margin_options
[17:16:29] [PASSED] drm_test_cmdline_multiple_options
[17:16:29] [PASSED] drm_test_cmdline_bpp_extra_and_option
[17:16:29] [PASSED] drm_test_cmdline_extra_and_option
[17:16:29] [PASSED] drm_test_cmdline_freestanding_options
[17:16:29] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[17:16:29] [PASSED] drm_test_cmdline_panel_orientation
[17:16:29] ================ drm_test_cmdline_invalid  =================
[17:16:29] [PASSED] margin_only
[17:16:29] [PASSED] interlace_only
[17:16:29] [PASSED] res_missing_x
[17:16:29] [PASSED] res_missing_y
[17:16:29] [PASSED] res_bad_y
[17:16:29] [PASSED] res_missing_y_bpp
[17:16:29] [PASSED] res_bad_bpp
[17:16:29] [PASSED] res_bad_refresh
[17:16:29] [PASSED] res_bpp_refresh_force_on_off
[17:16:29] [PASSED] res_invalid_mode
[17:16:29] [PASSED] res_bpp_wrong_place_mode
[17:16:29] [PASSED] name_bpp_refresh
[17:16:29] [PASSED] name_refresh
[17:16:29] [PASSED] name_refresh_wrong_mode
[17:16:29] [PASSED] name_refresh_invalid_mode
[17:16:29] [PASSED] rotate_multiple
[17:16:29] [PASSED] rotate_invalid_val
[17:16:29] [PASSED] rotate_truncated
[17:16:29] [PASSED] invalid_option
[17:16:29] [PASSED] invalid_tv_option
[17:16:29] [PASSED] truncated_tv_option
[17:16:29] ============ [PASSED] drm_test_cmdline_invalid =============
[17:16:29] =============== drm_test_cmdline_tv_options  ===============
[17:16:29] [PASSED] NTSC
[17:16:29] [PASSED] NTSC_443
[17:16:29] [PASSED] NTSC_J
[17:16:29] [PASSED] PAL
[17:16:29] [PASSED] PAL_M
[17:16:29] [PASSED] PAL_N
[17:16:29] [PASSED] SECAM
[17:16:29] [PASSED] MONO_525
[17:16:29] [PASSED] MONO_625
[17:16:29] =========== [PASSED] drm_test_cmdline_tv_options ===========
[17:16:29] =============== [PASSED] drm_cmdline_parser ================
[17:16:29] ========== drmm_connector_hdmi_init (20 subtests) ==========
[17:16:29] [PASSED] drm_test_connector_hdmi_init_valid
[17:16:29] [PASSED] drm_test_connector_hdmi_init_bpc_8
[17:16:29] [PASSED] drm_test_connector_hdmi_init_bpc_10
[17:16:29] [PASSED] drm_test_connector_hdmi_init_bpc_12
[17:16:29] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[17:16:29] [PASSED] drm_test_connector_hdmi_init_bpc_null
[17:16:29] [PASSED] drm_test_connector_hdmi_init_formats_empty
[17:16:29] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[17:16:29] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[17:16:29] [PASSED] supported_formats=0x9 yuv420_allowed=1
[17:16:29] [PASSED] supported_formats=0x9 yuv420_allowed=0
[17:16:29] [PASSED] supported_formats=0x3 yuv420_allowed=1
[17:16:29] [PASSED] supported_formats=0x3 yuv420_allowed=0
[17:16:29] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[17:16:29] [PASSED] drm_test_connector_hdmi_init_null_ddc
[17:16:29] [PASSED] drm_test_connector_hdmi_init_null_product
[17:16:29] [PASSED] drm_test_connector_hdmi_init_null_vendor
[17:16:29] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[17:16:29] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[17:16:29] [PASSED] drm_test_connector_hdmi_init_product_valid
[17:16:29] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[17:16:29] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[17:16:29] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[17:16:29] ========= drm_test_connector_hdmi_init_type_valid  =========
[17:16:29] [PASSED] HDMI-A
[17:16:29] [PASSED] HDMI-B
[17:16:29] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[17:16:29] ======== drm_test_connector_hdmi_init_type_invalid  ========
[17:16:29] [PASSED] Unknown
[17:16:29] [PASSED] VGA
[17:16:29] [PASSED] DVI-I
[17:16:29] [PASSED] DVI-D
[17:16:29] [PASSED] DVI-A
[17:16:29] [PASSED] Composite
[17:16:29] [PASSED] SVIDEO
[17:16:29] [PASSED] LVDS
[17:16:29] [PASSED] Component
[17:16:29] [PASSED] DIN
[17:16:29] [PASSED] DP
[17:16:29] [PASSED] TV
[17:16:29] [PASSED] eDP
[17:16:29] [PASSED] Virtual
[17:16:29] [PASSED] DSI
[17:16:29] [PASSED] DPI
[17:16:29] [PASSED] Writeback
[17:16:29] [PASSED] SPI
[17:16:29] [PASSED] USB
[17:16:29] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[17:16:29] ============ [PASSED] drmm_connector_hdmi_init =============
[17:16:29] ============= drmm_connector_init (3 subtests) =============
[17:16:29] [PASSED] drm_test_drmm_connector_init
[17:16:29] [PASSED] drm_test_drmm_connector_init_null_ddc
[17:16:29] ========= drm_test_drmm_connector_init_type_valid  =========
[17:16:29] [PASSED] Unknown
[17:16:29] [PASSED] VGA
[17:16:29] [PASSED] DVI-I
[17:16:29] [PASSED] DVI-D
[17:16:29] [PASSED] DVI-A
[17:16:29] [PASSED] Composite
[17:16:29] [PASSED] SVIDEO
[17:16:29] [PASSED] LVDS
[17:16:29] [PASSED] Component
[17:16:29] [PASSED] DIN
[17:16:29] [PASSED] DP
[17:16:29] [PASSED] HDMI-A
[17:16:29] [PASSED] HDMI-B
[17:16:29] [PASSED] TV
[17:16:29] [PASSED] eDP
[17:16:29] [PASSED] Virtual
[17:16:29] [PASSED] DSI
[17:16:29] [PASSED] DPI
[17:16:29] [PASSED] Writeback
[17:16:29] [PASSED] SPI
[17:16:29] [PASSED] USB
[17:16:29] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[17:16:29] =============== [PASSED] drmm_connector_init ===============
[17:16:29] ========= drm_connector_dynamic_init (6 subtests) ==========
[17:16:29] [PASSED] drm_test_drm_connector_dynamic_init
[17:16:29] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[17:16:29] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[17:16:29] [PASSED] drm_test_drm_connector_dynamic_init_properties
[17:16:29] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[17:16:29] [PASSED] Unknown
[17:16:29] [PASSED] VGA
[17:16:29] [PASSED] DVI-I
[17:16:29] [PASSED] DVI-D
[17:16:29] [PASSED] DVI-A
[17:16:29] [PASSED] Composite
[17:16:29] [PASSED] SVIDEO
[17:16:29] [PASSED] LVDS
[17:16:29] [PASSED] Component
[17:16:29] [PASSED] DIN
[17:16:29] [PASSED] DP
[17:16:29] [PASSED] HDMI-A
[17:16:29] [PASSED] HDMI-B
[17:16:29] [PASSED] TV
[17:16:29] [PASSED] eDP
[17:16:29] [PASSED] Virtual
[17:16:29] [PASSED] DSI
[17:16:29] [PASSED] DPI
[17:16:29] [PASSED] Writeback
[17:16:29] [PASSED] SPI
[17:16:29] [PASSED] USB
[17:16:29] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[17:16:29] ======== drm_test_drm_connector_dynamic_init_name  =========
[17:16:29] [PASSED] Unknown
[17:16:29] [PASSED] VGA
[17:16:29] [PASSED] DVI-I
[17:16:29] [PASSED] DVI-D
[17:16:29] [PASSED] DVI-A
[17:16:29] [PASSED] Composite
[17:16:29] [PASSED] SVIDEO
[17:16:29] [PASSED] LVDS
[17:16:29] [PASSED] Component
[17:16:29] [PASSED] DIN
[17:16:29] [PASSED] DP
[17:16:29] [PASSED] HDMI-A
[17:16:29] [PASSED] HDMI-B
[17:16:29] [PASSED] TV
[17:16:29] [PASSED] eDP
[17:16:29] [PASSED] Virtual
[17:16:29] [PASSED] DSI
[17:16:29] [PASSED] DPI
[17:16:29] [PASSED] Writeback
[17:16:29] [PASSED] SPI
[17:16:29] [PASSED] USB
[17:16:29] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[17:16:29] =========== [PASSED] drm_connector_dynamic_init ============
[17:16:29] ==== drm_connector_dynamic_register_early (4 subtests) =====
[17:16:29] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[17:16:29] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[17:16:29] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[17:16:29] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[17:16:29] ====== [PASSED] drm_connector_dynamic_register_early =======
[17:16:29] ======= drm_connector_dynamic_register (7 subtests) ========
[17:16:29] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[17:16:29] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[17:16:29] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[17:16:29] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[17:16:29] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[17:16:29] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[17:16:29] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[17:16:29] ========= [PASSED] drm_connector_dynamic_register ==========
[17:16:29] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[17:16:29] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[17:16:29] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[17:16:29] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[17:16:29] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[17:16:29] ========== drm_test_get_tv_mode_from_name_valid  ===========
[17:16:29] [PASSED] NTSC
[17:16:29] [PASSED] NTSC-443
[17:16:29] [PASSED] NTSC-J
[17:16:29] [PASSED] PAL
[17:16:29] [PASSED] PAL-M
[17:16:29] [PASSED] PAL-N
[17:16:29] [PASSED] SECAM
[17:16:29] [PASSED] Mono
[17:16:29] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[17:16:29] [PASSED] drm_test_get_tv_mode_from_name_truncated
[17:16:29] ============ [PASSED] drm_get_tv_mode_from_name ============
[17:16:29] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[17:16:29] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[17:16:29] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[17:16:29] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[17:16:29] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[17:16:29] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[17:16:29] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[17:16:29] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[17:16:29] [PASSED] VIC 96
[17:16:29] [PASSED] VIC 97
[17:16:29] [PASSED] VIC 101
[17:16:29] [PASSED] VIC 102
[17:16:29] [PASSED] VIC 106
[17:16:29] [PASSED] VIC 107
[17:16:29] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[17:16:29] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[17:16:29] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[17:16:29] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[17:16:29] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[17:16:29] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[17:16:29] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[17:16:29] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[17:16:29] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[17:16:29] [PASSED] Automatic
[17:16:29] [PASSED] Full
[17:16:29] [PASSED] Limited 16:235
[17:16:29] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[17:16:29] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[17:16:29] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[17:16:29] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[17:16:29] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[17:16:29] [PASSED] RGB
[17:16:29] [PASSED] YUV 4:2:0
[17:16:29] [PASSED] YUV 4:2:2
[17:16:29] [PASSED] YUV 4:4:4
[17:16:29] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[17:16:29] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[17:16:29] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[17:16:29] ============= drm_damage_helper (21 subtests) ==============
[17:16:29] [PASSED] drm_test_damage_iter_no_damage
[17:16:29] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[17:16:29] [PASSED] drm_test_damage_iter_no_damage_src_moved
[17:16:29] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[17:16:29] [PASSED] drm_test_damage_iter_no_damage_not_visible
[17:16:29] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[17:16:29] [PASSED] drm_test_damage_iter_no_damage_no_fb
[17:16:29] [PASSED] drm_test_damage_iter_simple_damage
[17:16:29] [PASSED] drm_test_damage_iter_single_damage
[17:16:29] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[17:16:29] [PASSED] drm_test_damage_iter_single_damage_outside_src
[17:16:29] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[17:16:29] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[17:16:29] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[17:16:29] [PASSED] drm_test_damage_iter_single_damage_src_moved
[17:16:29] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[17:16:29] [PASSED] drm_test_damage_iter_damage
[17:16:29] [PASSED] drm_test_damage_iter_damage_one_intersect
[17:16:29] [PASSED] drm_test_damage_iter_damage_one_outside
[17:16:29] [PASSED] drm_test_damage_iter_damage_src_moved
[17:16:29] [PASSED] drm_test_damage_iter_damage_not_visible
[17:16:29] ================ [PASSED] drm_damage_helper ================
[17:16:29] ============== drm_dp_mst_helper (3 subtests) ==============
[17:16:29] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[17:16:29] [PASSED] Clock 154000 BPP 30 DSC disabled
[17:16:29] [PASSED] Clock 234000 BPP 30 DSC disabled
[17:16:29] [PASSED] Clock 297000 BPP 24 DSC disabled
[17:16:29] [PASSED] Clock 332880 BPP 24 DSC enabled
[17:16:29] [PASSED] Clock 324540 BPP 24 DSC enabled
[17:16:29] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[17:16:29] ============== drm_test_dp_mst_calc_pbn_div  ===============
[17:16:29] [PASSED] Link rate 2000000 lane count 4
[17:16:29] [PASSED] Link rate 2000000 lane count 2
[17:16:29] [PASSED] Link rate 2000000 lane count 1
[17:16:29] [PASSED] Link rate 1350000 lane count 4
[17:16:29] [PASSED] Link rate 1350000 lane count 2
[17:16:29] [PASSED] Link rate 1350000 lane count 1
[17:16:29] [PASSED] Link rate 1000000 lane count 4
[17:16:29] [PASSED] Link rate 1000000 lane count 2
[17:16:29] [PASSED] Link rate 1000000 lane count 1
[17:16:29] [PASSED] Link rate 810000 lane count 4
[17:16:29] [PASSED] Link rate 810000 lane count 2
[17:16:29] [PASSED] Link rate 810000 lane count 1
[17:16:29] [PASSED] Link rate 540000 lane count 4
[17:16:29] [PASSED] Link rate 540000 lane count 2
[17:16:29] [PASSED] Link rate 540000 lane count 1
[17:16:29] [PASSED] Link rate 270000 lane count 4
[17:16:29] [PASSED] Link rate 270000 lane count 2
[17:16:29] [PASSED] Link rate 270000 lane count 1
[17:16:29] [PASSED] Link rate 162000 lane count 4
[17:16:29] [PASSED] Link rate 162000 lane count 2
[17:16:29] [PASSED] Link rate 162000 lane count 1
[17:16:29] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[17:16:29] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[17:16:29] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[17:16:29] [PASSED] DP_POWER_UP_PHY with port number
[17:16:29] [PASSED] DP_POWER_DOWN_PHY with port number
[17:16:29] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[17:16:29] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[17:16:29] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[17:16:29] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[17:16:29] [PASSED] DP_QUERY_PAYLOAD with port number
[17:16:29] [PASSED] DP_QUERY_PAYLOAD with VCPI
[17:16:29] [PASSED] DP_REMOTE_DPCD_READ with port number
[17:16:29] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[17:16:29] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[17:16:29] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[17:16:29] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[17:16:29] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[17:16:29] [PASSED] DP_REMOTE_I2C_READ with port number
[17:16:29] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[17:16:29] [PASSED] DP_REMOTE_I2C_READ with transactions array
[17:16:29] [PASSED] DP_REMOTE_I2C_WRITE with port number
[17:16:29] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[17:16:29] [PASSED] DP_REMOTE_I2C_WRITE with data array
[17:16:29] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[17:16:29] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[17:16:29] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[17:16:29] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[17:16:29] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[17:16:29] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[17:16:29] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[17:16:29] ================ [PASSED] drm_dp_mst_helper ================
[17:16:29] ================== drm_exec (7 subtests) ===================
[17:16:29] [PASSED] sanitycheck
[17:16:29] [PASSED] test_lock
[17:16:29] [PASSED] test_lock_unlock
[17:16:29] [PASSED] test_duplicates
[17:16:29] [PASSED] test_prepare
[17:16:29] [PASSED] test_prepare_array
[17:16:29] [PASSED] test_multiple_loops
[17:16:29] ==================== [PASSED] drm_exec =====================
[17:16:29] =========== drm_format_helper_test (17 subtests) ===========
[17:16:29] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[17:16:29] [PASSED] single_pixel_source_buffer
[17:16:29] [PASSED] single_pixel_clip_rectangle
[17:16:29] [PASSED] well_known_colors
[17:16:29] [PASSED] destination_pitch
[17:16:29] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[17:16:29] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[17:16:29] [PASSED] single_pixel_source_buffer
[17:16:29] [PASSED] single_pixel_clip_rectangle
[17:16:29] [PASSED] well_known_colors
[17:16:29] [PASSED] destination_pitch
[17:16:29] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[17:16:29] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[17:16:29] [PASSED] single_pixel_source_buffer
[17:16:29] [PASSED] single_pixel_clip_rectangle
[17:16:29] [PASSED] well_known_colors
[17:16:29] [PASSED] destination_pitch
[17:16:29] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[17:16:29] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[17:16:29] [PASSED] single_pixel_source_buffer
[17:16:29] [PASSED] single_pixel_clip_rectangle
[17:16:29] [PASSED] well_known_colors
[17:16:29] [PASSED] destination_pitch
[17:16:29] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[17:16:29] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[17:16:29] [PASSED] single_pixel_source_buffer
[17:16:29] [PASSED] single_pixel_clip_rectangle
[17:16:29] [PASSED] well_known_colors
[17:16:29] [PASSED] destination_pitch
[17:16:29] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[17:16:29] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[17:16:29] [PASSED] single_pixel_source_buffer
[17:16:29] [PASSED] single_pixel_clip_rectangle
[17:16:29] [PASSED] well_known_colors
[17:16:29] [PASSED] destination_pitch
[17:16:29] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[17:16:29] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[17:16:29] [PASSED] single_pixel_source_buffer
[17:16:29] [PASSED] single_pixel_clip_rectangle
[17:16:29] [PASSED] well_known_colors
[17:16:29] [PASSED] destination_pitch
[17:16:29] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[17:16:29] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[17:16:29] [PASSED] single_pixel_source_buffer
[17:16:29] [PASSED] single_pixel_clip_rectangle
[17:16:29] [PASSED] well_known_colors
[17:16:29] [PASSED] destination_pitch
[17:16:29] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[17:16:29] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[17:16:29] [PASSED] single_pixel_source_buffer
[17:16:29] [PASSED] single_pixel_clip_rectangle
[17:16:29] [PASSED] well_known_colors
[17:16:29] [PASSED] destination_pitch
[17:16:29] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[17:16:29] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[17:16:29] [PASSED] single_pixel_source_buffer
[17:16:29] [PASSED] single_pixel_clip_rectangle
[17:16:29] [PASSED] well_known_colors
[17:16:29] [PASSED] destination_pitch
[17:16:29] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[17:16:29] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[17:16:29] [PASSED] single_pixel_source_buffer
[17:16:29] [PASSED] single_pixel_clip_rectangle
[17:16:29] [PASSED] well_known_colors
[17:16:29] [PASSED] destination_pitch
[17:16:29] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[17:16:29] ============== drm_test_fb_xrgb8888_to_mono  ===============
[17:16:29] [PASSED] single_pixel_source_buffer
[17:16:29] [PASSED] single_pixel_clip_rectangle
[17:16:29] [PASSED] well_known_colors
[17:16:29] [PASSED] destination_pitch
[17:16:29] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[17:16:29] ==================== drm_test_fb_swab  =====================
[17:16:29] [PASSED] single_pixel_source_buffer
[17:16:29] [PASSED] single_pixel_clip_rectangle
[17:16:29] [PASSED] well_known_colors
[17:16:29] [PASSED] destination_pitch
[17:16:29] ================ [PASSED] drm_test_fb_swab =================
[17:16:29] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[17:16:29] [PASSED] single_pixel_source_buffer
[17:16:29] [PASSED] single_pixel_clip_rectangle
[17:16:29] [PASSED] well_known_colors
[17:16:29] [PASSED] destination_pitch
[17:16:29] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[17:16:29] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[17:16:29] [PASSED] single_pixel_source_buffer
[17:16:29] [PASSED] single_pixel_clip_rectangle
[17:16:29] [PASSED] well_known_colors
[17:16:29] [PASSED] destination_pitch
[17:16:29] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[17:16:29] ================= drm_test_fb_clip_offset  =================
[17:16:29] [PASSED] pass through
[17:16:29] [PASSED] horizontal offset
[17:16:29] [PASSED] vertical offset
[17:16:29] [PASSED] horizontal and vertical offset
[17:16:29] [PASSED] horizontal offset (custom pitch)
[17:16:29] [PASSED] vertical offset (custom pitch)
[17:16:29] [PASSED] horizontal and vertical offset (custom pitch)
[17:16:29] ============= [PASSED] drm_test_fb_clip_offset =============
[17:16:29] =================== drm_test_fb_memcpy  ====================
[17:16:29] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[17:16:29] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[17:16:29] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[17:16:29] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[17:16:29] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[17:16:29] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[17:16:29] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[17:16:29] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[17:16:29] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[17:16:29] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[17:16:29] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[17:16:29] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[17:16:29] =============== [PASSED] drm_test_fb_memcpy ================
[17:16:29] ============= [PASSED] drm_format_helper_test ==============
[17:16:29] ================= drm_format (18 subtests) =================
[17:16:29] [PASSED] drm_test_format_block_width_invalid
[17:16:29] [PASSED] drm_test_format_block_width_one_plane
[17:16:29] [PASSED] drm_test_format_block_width_two_plane
[17:16:29] [PASSED] drm_test_format_block_width_three_plane
[17:16:29] [PASSED] drm_test_format_block_width_tiled
[17:16:29] [PASSED] drm_test_format_block_height_invalid
[17:16:29] [PASSED] drm_test_format_block_height_one_plane
[17:16:29] [PASSED] drm_test_format_block_height_two_plane
[17:16:29] [PASSED] drm_test_format_block_height_three_plane
[17:16:29] [PASSED] drm_test_format_block_height_tiled
[17:16:29] [PASSED] drm_test_format_min_pitch_invalid
[17:16:29] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[17:16:29] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[17:16:29] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[17:16:29] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[17:16:29] [PASSED] drm_test_format_min_pitch_two_plane
[17:16:29] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[17:16:29] [PASSED] drm_test_format_min_pitch_tiled
[17:16:29] =================== [PASSED] drm_format ====================
[17:16:29] ============== drm_framebuffer (10 subtests) ===============
[17:16:29] ========== drm_test_framebuffer_check_src_coords  ==========
[17:16:29] [PASSED] Success: source fits into fb
[17:16:29] [PASSED] Fail: overflowing fb with x-axis coordinate
[17:16:29] [PASSED] Fail: overflowing fb with y-axis coordinate
[17:16:29] [PASSED] Fail: overflowing fb with source width
[17:16:29] [PASSED] Fail: overflowing fb with source height
[17:16:29] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[17:16:29] [PASSED] drm_test_framebuffer_cleanup
[17:16:29] =============== drm_test_framebuffer_create  ===============
[17:16:29] [PASSED] ABGR8888 normal sizes
[17:16:29] [PASSED] ABGR8888 max sizes
[17:16:29] [PASSED] ABGR8888 pitch greater than min required
[17:16:29] [PASSED] ABGR8888 pitch less than min required
[17:16:29] [PASSED] ABGR8888 Invalid width
[17:16:29] [PASSED] ABGR8888 Invalid buffer handle
[17:16:29] [PASSED] No pixel format
[17:16:29] [PASSED] ABGR8888 Width 0
[17:16:29] [PASSED] ABGR8888 Height 0
[17:16:29] [PASSED] ABGR8888 Out of bound height * pitch combination
[17:16:29] [PASSED] ABGR8888 Large buffer offset
[17:16:29] [PASSED] ABGR8888 Buffer offset for inexistent plane
[17:16:29] [PASSED] ABGR8888 Invalid flag
[17:16:29] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[17:16:29] [PASSED] ABGR8888 Valid buffer modifier
[17:16:29] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[17:16:29] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[17:16:29] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[17:16:29] [PASSED] NV12 Normal sizes
[17:16:29] [PASSED] NV12 Max sizes
[17:16:29] [PASSED] NV12 Invalid pitch
[17:16:29] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[17:16:29] [PASSED] NV12 different  modifier per-plane
[17:16:29] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[17:16:29] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[17:16:29] [PASSED] NV12 Modifier for inexistent plane
[17:16:29] [PASSED] NV12 Handle for inexistent plane
[17:16:29] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[17:16:29] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[17:16:29] [PASSED] YVU420 Normal sizes
[17:16:29] [PASSED] YVU420 Max sizes
[17:16:29] [PASSED] YVU420 Invalid pitch
[17:16:29] [PASSED] YVU420 Different pitches
[17:16:29] [PASSED] YVU420 Different buffer offsets/pitches
[17:16:29] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[17:16:29] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[17:16:29] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[17:16:29] [PASSED] YVU420 Valid modifier
[17:16:29] [PASSED] YVU420 Different modifiers per plane
[17:16:29] [PASSED] YVU420 Modifier for inexistent plane
[17:16:29] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[17:16:29] [PASSED] X0L2 Normal sizes
[17:16:29] [PASSED] X0L2 Max sizes
[17:16:29] [PASSED] X0L2 Invalid pitch
[17:16:29] [PASSED] X0L2 Pitch greater than minimum required
[17:16:29] [PASSED] X0L2 Handle for inexistent plane
[17:16:29] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[17:16:29] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[17:16:29] [PASSED] X0L2 Valid modifier
[17:16:29] [PASSED] X0L2 Modifier for inexistent plane
[17:16:29] =========== [PASSED] drm_test_framebuffer_create ===========
[17:16:29] [PASSED] drm_test_framebuffer_free
[17:16:29] [PASSED] drm_test_framebuffer_init
[17:16:29] [PASSED] drm_test_framebuffer_init_bad_format
[17:16:29] [PASSED] drm_test_framebuffer_init_dev_mismatch
[17:16:29] [PASSED] drm_test_framebuffer_lookup
[17:16:29] [PASSED] drm_test_framebuffer_lookup_inexistent
[17:16:29] [PASSED] drm_test_framebuffer_modifiers_not_supported
[17:16:29] ================= [PASSED] drm_framebuffer =================
[17:16:29] ================ drm_gem_shmem (8 subtests) ================
[17:16:29] [PASSED] drm_gem_shmem_test_obj_create
[17:16:29] [PASSED] drm_gem_shmem_test_obj_create_private
[17:16:29] [PASSED] drm_gem_shmem_test_pin_pages
[17:16:29] [PASSED] drm_gem_shmem_test_vmap
[17:16:29] [PASSED] drm_gem_shmem_test_get_sg_table
[17:16:29] [PASSED] drm_gem_shmem_test_get_pages_sgt
[17:16:29] [PASSED] drm_gem_shmem_test_madvise
[17:16:29] [PASSED] drm_gem_shmem_test_purge
[17:16:29] ================== [PASSED] drm_gem_shmem ==================
[17:16:29] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[17:16:29] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[17:16:29] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[17:16:29] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[17:16:29] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[17:16:29] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[17:16:29] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[17:16:29] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[17:16:29] [PASSED] Automatic
[17:16:29] [PASSED] Full
[17:16:29] [PASSED] Limited 16:235
[17:16:29] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[17:16:29] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[17:16:29] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[17:16:29] [PASSED] drm_test_check_disable_connector
[17:16:29] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[17:16:29] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[17:16:29] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[17:16:29] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[17:16:29] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[17:16:29] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[17:16:29] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[17:16:29] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[17:16:29] [PASSED] drm_test_check_output_bpc_dvi
[17:16:29] [PASSED] drm_test_check_output_bpc_format_vic_1
[17:16:29] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[17:16:29] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[17:16:29] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[17:16:29] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[17:16:29] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[17:16:29] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[17:16:29] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[17:16:29] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[17:16:29] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[17:16:29] [PASSED] drm_test_check_broadcast_rgb_value
[17:16:29] [PASSED] drm_test_check_bpc_8_value
[17:16:29] [PASSED] drm_test_check_bpc_10_value
[17:16:29] [PASSED] drm_test_check_bpc_12_value
[17:16:29] [PASSED] drm_test_check_format_value
[17:16:29] [PASSED] drm_test_check_tmds_char_value
[17:16:29] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[17:16:29] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[17:16:29] [PASSED] drm_test_check_mode_valid
[17:16:29] [PASSED] drm_test_check_mode_valid_reject
[17:16:29] [PASSED] drm_test_check_mode_valid_reject_rate
[17:16:29] [PASSED] drm_test_check_mode_valid_reject_max_clock
[17:16:29] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[17:16:29] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[17:16:29] [PASSED] drm_test_check_infoframes
[17:16:29] [PASSED] drm_test_check_reject_avi_infoframe
[17:16:29] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[17:16:29] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[17:16:29] [PASSED] drm_test_check_reject_audio_infoframe
[17:16:29] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[17:16:29] ================= drm_managed (2 subtests) =================
[17:16:29] [PASSED] drm_test_managed_release_action
[17:16:29] [PASSED] drm_test_managed_run_action
[17:16:29] =================== [PASSED] drm_managed ===================
[17:16:29] =================== drm_mm (6 subtests) ====================
[17:16:29] [PASSED] drm_test_mm_init
[17:16:29] [PASSED] drm_test_mm_debug
[17:16:29] [PASSED] drm_test_mm_align32
[17:16:29] [PASSED] drm_test_mm_align64
[17:16:29] [PASSED] drm_test_mm_lowest
[17:16:29] [PASSED] drm_test_mm_highest
[17:16:29] ===================== [PASSED] drm_mm ======================
[17:16:29] ============= drm_modes_analog_tv (5 subtests) =============
[17:16:29] [PASSED] drm_test_modes_analog_tv_mono_576i
[17:16:29] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[17:16:29] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[17:16:29] [PASSED] drm_test_modes_analog_tv_pal_576i
[17:16:29] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[17:16:29] =============== [PASSED] drm_modes_analog_tv ===============
[17:16:29] ============== drm_plane_helper (2 subtests) ===============
[17:16:29] =============== drm_test_check_plane_state  ================
[17:16:29] [PASSED] clipping_simple
[17:16:29] [PASSED] clipping_rotate_reflect
[17:16:29] [PASSED] positioning_simple
[17:16:29] [PASSED] upscaling
[17:16:29] [PASSED] downscaling
[17:16:29] [PASSED] rounding1
[17:16:29] [PASSED] rounding2
[17:16:29] [PASSED] rounding3
[17:16:29] [PASSED] rounding4
[17:16:29] =========== [PASSED] drm_test_check_plane_state ============
[17:16:29] =========== drm_test_check_invalid_plane_state  ============
[17:16:29] [PASSED] positioning_invalid
[17:16:29] [PASSED] upscaling_invalid
[17:16:29] [PASSED] downscaling_invalid
[17:16:29] ======= [PASSED] drm_test_check_invalid_plane_state ========
[17:16:29] ================ [PASSED] drm_plane_helper =================
[17:16:29] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[17:16:29] ====== drm_test_connector_helper_tv_get_modes_check  =======
[17:16:29] [PASSED] None
[17:16:29] [PASSED] PAL
[17:16:29] [PASSED] NTSC
[17:16:29] [PASSED] Both, NTSC Default
[17:16:29] [PASSED] Both, PAL Default
[17:16:29] [PASSED] Both, NTSC Default, with PAL on command-line
[17:16:29] [PASSED] Both, PAL Default, with NTSC on command-line
[17:16:29] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[17:16:29] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[17:16:29] ================== drm_rect (9 subtests) ===================
[17:16:29] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[17:16:29] [PASSED] drm_test_rect_clip_scaled_not_clipped
[17:16:29] [PASSED] drm_test_rect_clip_scaled_clipped
[17:16:29] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[17:16:29] ================= drm_test_rect_intersect  =================
[17:16:29] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[17:16:29] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[17:16:29] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[17:16:29] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[17:16:29] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[17:16:29] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[17:16:29] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[17:16:29] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[17:16:29] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[17:16:29] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[17:16:29] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[17:16:29] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[17:16:29] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[17:16:29] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[17:16:29] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[17:16:29] ============= [PASSED] drm_test_rect_intersect =============
[17:16:29] ================ drm_test_rect_calc_hscale  ================
[17:16:29] [PASSED] normal use
[17:16:29] [PASSED] out of max range
[17:16:29] [PASSED] out of min range
[17:16:29] [PASSED] zero dst
[17:16:29] [PASSED] negative src
[17:16:29] [PASSED] negative dst
[17:16:29] ============ [PASSED] drm_test_rect_calc_hscale ============
[17:16:29] ================ drm_test_rect_calc_vscale  ================
[17:16:29] [PASSED] normal use
[17:16:29] [PASSED] out of max range
[17:16:29] [PASSED] out of min range
[17:16:29] [PASSED] zero dst
[17:16:29] [PASSED] negative src
[17:16:29] [PASSED] negative dst
stty: 'standard input': Inappropriate ioctl for device
[17:16:29] ============ [PASSED] drm_test_rect_calc_vscale ============
[17:16:29] ================== drm_test_rect_rotate  ===================
[17:16:29] [PASSED] reflect-x
[17:16:29] [PASSED] reflect-y
[17:16:29] [PASSED] rotate-0
[17:16:29] [PASSED] rotate-90
[17:16:29] [PASSED] rotate-180
[17:16:29] [PASSED] rotate-270
[17:16:29] ============== [PASSED] drm_test_rect_rotate ===============
[17:16:29] ================ drm_test_rect_rotate_inv  =================
[17:16:29] [PASSED] reflect-x
[17:16:29] [PASSED] reflect-y
[17:16:29] [PASSED] rotate-0
[17:16:29] [PASSED] rotate-90
[17:16:29] [PASSED] rotate-180
[17:16:29] [PASSED] rotate-270
[17:16:29] ============ [PASSED] drm_test_rect_rotate_inv =============
[17:16:29] ==================== [PASSED] drm_rect =====================
[17:16:29] ============ drm_sysfb_modeset_test (1 subtest) ============
[17:16:29] ============ drm_test_sysfb_build_fourcc_list  =============
[17:16:29] [PASSED] no native formats
[17:16:29] [PASSED] XRGB8888 as native format
[17:16:29] [PASSED] remove duplicates
[17:16:29] [PASSED] convert alpha formats
[17:16:29] [PASSED] random formats
[17:16:29] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[17:16:29] ============= [PASSED] drm_sysfb_modeset_test ==============
[17:16:29] ================== drm_fixp (2 subtests) ===================
[17:16:29] [PASSED] drm_test_int2fixp
[17:16:29] [PASSED] drm_test_sm2fixp
[17:16:29] ==================== [PASSED] drm_fixp =====================
[17:16:29] ============================================================
[17:16:29] Testing complete. Ran 621 tests: passed: 621
[17:16:29] Elapsed time: 26.405s total, 1.732s configuring, 24.456s building, 0.181s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[17:16:29] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[17:16:31] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[17:16:40] Starting KUnit Kernel (1/1)...
[17:16:40] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[17:16:40] ================= ttm_device (5 subtests) ==================
[17:16:40] [PASSED] ttm_device_init_basic
[17:16:40] [PASSED] ttm_device_init_multiple
[17:16:40] [PASSED] ttm_device_fini_basic
[17:16:40] [PASSED] ttm_device_init_no_vma_man
[17:16:40] ================== ttm_device_init_pools  ==================
[17:16:40] [PASSED] No DMA allocations, no DMA32 required
[17:16:40] [PASSED] DMA allocations, DMA32 required
[17:16:40] [PASSED] No DMA allocations, DMA32 required
[17:16:40] [PASSED] DMA allocations, no DMA32 required
[17:16:40] ============== [PASSED] ttm_device_init_pools ==============
[17:16:40] =================== [PASSED] ttm_device ====================
[17:16:40] ================== ttm_pool (8 subtests) ===================
[17:16:40] ================== ttm_pool_alloc_basic  ===================
[17:16:40] [PASSED] One page
[17:16:40] [PASSED] More than one page
[17:16:40] [PASSED] Above the allocation limit
[17:16:40] [PASSED] One page, with coherent DMA mappings enabled
[17:16:40] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[17:16:40] ============== [PASSED] ttm_pool_alloc_basic ===============
[17:16:40] ============== ttm_pool_alloc_basic_dma_addr  ==============
[17:16:40] [PASSED] One page
[17:16:40] [PASSED] More than one page
[17:16:40] [PASSED] Above the allocation limit
[17:16:40] [PASSED] One page, with coherent DMA mappings enabled
[17:16:40] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[17:16:40] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[17:16:40] [PASSED] ttm_pool_alloc_order_caching_match
[17:16:40] [PASSED] ttm_pool_alloc_caching_mismatch
[17:16:40] [PASSED] ttm_pool_alloc_order_mismatch
[17:16:40] [PASSED] ttm_pool_free_dma_alloc
[17:16:40] [PASSED] ttm_pool_free_no_dma_alloc
[17:16:40] [PASSED] ttm_pool_fini_basic
[17:16:40] ==================== [PASSED] ttm_pool =====================
[17:16:40] ================ ttm_resource (8 subtests) =================
[17:16:40] ================= ttm_resource_init_basic  =================
[17:16:40] [PASSED] Init resource in TTM_PL_SYSTEM
[17:16:40] [PASSED] Init resource in TTM_PL_VRAM
[17:16:40] [PASSED] Init resource in a private placement
[17:16:40] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[17:16:40] ============= [PASSED] ttm_resource_init_basic =============
[17:16:40] [PASSED] ttm_resource_init_pinned
[17:16:40] [PASSED] ttm_resource_fini_basic
[17:16:40] [PASSED] ttm_resource_manager_init_basic
[17:16:40] [PASSED] ttm_resource_manager_usage_basic
[17:16:40] [PASSED] ttm_resource_manager_set_used_basic
[17:16:40] [PASSED] ttm_sys_man_alloc_basic
[17:16:40] [PASSED] ttm_sys_man_free_basic
[17:16:40] ================== [PASSED] ttm_resource ===================
[17:16:40] =================== ttm_tt (15 subtests) ===================
[17:16:40] ==================== ttm_tt_init_basic  ====================
[17:16:40] [PASSED] Page-aligned size
[17:16:40] [PASSED] Extra pages requested
[17:16:40] ================ [PASSED] ttm_tt_init_basic ================
[17:16:40] [PASSED] ttm_tt_init_misaligned
[17:16:40] [PASSED] ttm_tt_fini_basic
[17:16:40] [PASSED] ttm_tt_fini_sg
[17:16:40] [PASSED] ttm_tt_fini_shmem
[17:16:40] [PASSED] ttm_tt_create_basic
[17:16:40] [PASSED] ttm_tt_create_invalid_bo_type
[17:16:40] [PASSED] ttm_tt_create_ttm_exists
[17:16:40] [PASSED] ttm_tt_create_failed
[17:16:40] [PASSED] ttm_tt_destroy_basic
[17:16:40] [PASSED] ttm_tt_populate_null_ttm
[17:16:40] [PASSED] ttm_tt_populate_populated_ttm
[17:16:40] [PASSED] ttm_tt_unpopulate_basic
[17:16:40] [PASSED] ttm_tt_unpopulate_empty_ttm
[17:16:40] [PASSED] ttm_tt_swapin_basic
[17:16:40] ===================== [PASSED] ttm_tt ======================
[17:16:40] =================== ttm_bo (14 subtests) ===================
[17:16:40] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[17:16:40] [PASSED] Cannot be interrupted and sleeps
[17:16:40] [PASSED] Cannot be interrupted, locks straight away
[17:16:40] [PASSED] Can be interrupted, sleeps
[17:16:40] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[17:16:40] [PASSED] ttm_bo_reserve_locked_no_sleep
[17:16:40] [PASSED] ttm_bo_reserve_no_wait_ticket
[17:16:40] [PASSED] ttm_bo_reserve_double_resv
[17:16:40] [PASSED] ttm_bo_reserve_interrupted
[17:16:40] [PASSED] ttm_bo_reserve_deadlock
[17:16:40] [PASSED] ttm_bo_unreserve_basic
[17:16:40] [PASSED] ttm_bo_unreserve_pinned
[17:16:40] [PASSED] ttm_bo_unreserve_bulk
[17:16:40] [PASSED] ttm_bo_fini_basic
[17:16:40] [PASSED] ttm_bo_fini_shared_resv
[17:16:40] [PASSED] ttm_bo_pin_basic
[17:16:40] [PASSED] ttm_bo_pin_unpin_resource
[17:16:40] [PASSED] ttm_bo_multiple_pin_one_unpin
[17:16:40] ===================== [PASSED] ttm_bo ======================
[17:16:40] ============== ttm_bo_validate (21 subtests) ===============
[17:16:40] ============== ttm_bo_init_reserved_sys_man  ===============
[17:16:40] [PASSED] Buffer object for userspace
[17:16:40] [PASSED] Kernel buffer object
[17:16:40] [PASSED] Shared buffer object
[17:16:40] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[17:16:40] ============== ttm_bo_init_reserved_mock_man  ==============
[17:16:40] [PASSED] Buffer object for userspace
[17:16:40] [PASSED] Kernel buffer object
[17:16:40] [PASSED] Shared buffer object
[17:16:40] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[17:16:40] [PASSED] ttm_bo_init_reserved_resv
[17:16:40] ================== ttm_bo_validate_basic  ==================
[17:16:40] [PASSED] Buffer object for userspace
[17:16:40] [PASSED] Kernel buffer object
[17:16:40] [PASSED] Shared buffer object
[17:16:40] ============== [PASSED] ttm_bo_validate_basic ==============
[17:16:40] [PASSED] ttm_bo_validate_invalid_placement
[17:16:40] ============= ttm_bo_validate_same_placement  ==============
[17:16:40] [PASSED] System manager
[17:16:40] [PASSED] VRAM manager
[17:16:40] ========= [PASSED] ttm_bo_validate_same_placement ==========
[17:16:40] [PASSED] ttm_bo_validate_failed_alloc
[17:16:40] [PASSED] ttm_bo_validate_pinned
[17:16:40] [PASSED] ttm_bo_validate_busy_placement
[17:16:40] ================ ttm_bo_validate_multihop  =================
[17:16:40] [PASSED] Buffer object for userspace
[17:16:40] [PASSED] Kernel buffer object
[17:16:40] [PASSED] Shared buffer object
[17:16:40] ============ [PASSED] ttm_bo_validate_multihop =============
[17:16:40] ========== ttm_bo_validate_no_placement_signaled  ==========
[17:16:40] [PASSED] Buffer object in system domain, no page vector
[17:16:40] [PASSED] Buffer object in system domain with an existing page vector
[17:16:40] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[17:16:40] ======== ttm_bo_validate_no_placement_not_signaled  ========
[17:16:40] [PASSED] Buffer object for userspace
[17:16:40] [PASSED] Kernel buffer object
[17:16:40] [PASSED] Shared buffer object
[17:16:40] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[17:16:40] [PASSED] ttm_bo_validate_move_fence_signaled
[17:16:40] ========= ttm_bo_validate_move_fence_not_signaled  =========
[17:16:40] [PASSED] Waits for GPU
[17:16:40] [PASSED] Tries to lock straight away
[17:16:40] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[17:16:40] [PASSED] ttm_bo_validate_happy_evict
[17:16:40] [PASSED] ttm_bo_validate_all_pinned_evict
[17:16:40] [PASSED] ttm_bo_validate_allowed_only_evict
[17:16:40] [PASSED] ttm_bo_validate_deleted_evict
[17:16:40] [PASSED] ttm_bo_validate_busy_domain_evict
[17:16:40] [PASSED] ttm_bo_validate_evict_gutting
[17:16:40] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[17:16:40] ================= [PASSED] ttm_bo_validate =================
[17:16:40] ============================================================
[17:16:40] Testing complete. Ran 101 tests: passed: 101
[17:16:40] Elapsed time: 11.209s total, 1.729s configuring, 9.264s building, 0.177s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✗ Xe.CI.BAT: failure for Refactor LT PHY PLL handling to use DPLL framework (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 5418 bytes --]

== Series Details ==

Series: Refactor LT PHY PLL handling to use DPLL framework (rev2)
URL   : https://patchwork.freedesktop.org/series/161586/
State : failure

== Summary ==

CI Bug Log - changes from xe-4661-1242b36e0da950a66f2267e1c15395962dad569c_BAT -> xe-pw-161586v2_BAT
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-161586v2_BAT absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-161586v2_BAT, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (14 -> 14)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-161586v2_BAT:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_flip@basic-flip-vs-dpms:
    - bat-ptl-2:          [PASS][1] -> [ABORT][2] +1 other test abort
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/bat-ptl-2/igt@kms_flip@basic-flip-vs-dpms.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/bat-ptl-2/igt@kms_flip@basic-flip-vs-dpms.html

  * igt@kms_flip@basic-flip-vs-dpms@a-edp1:
    - bat-wcl-1:          [PASS][3] -> [ABORT][4] +1 other test abort
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/bat-wcl-1/igt@kms_flip@basic-flip-vs-dpms@a-edp1.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/bat-wcl-1/igt@kms_flip@basic-flip-vs-dpms@a-edp1.html
    - bat-lnl-1:          [PASS][5] -> [ABORT][6] +1 other test abort
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/bat-lnl-1/igt@kms_flip@basic-flip-vs-dpms@a-edp1.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/bat-lnl-1/igt@kms_flip@basic-flip-vs-dpms@a-edp1.html

  * igt@kms_flip@basic-flip-vs-dpms@a-hdmi-a3:
    - bat-bmg-1:          [PASS][7] -> [ABORT][8] +1 other test abort
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/bat-bmg-1/igt@kms_flip@basic-flip-vs-dpms@a-hdmi-a3.html
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/bat-bmg-1/igt@kms_flip@basic-flip-vs-dpms@a-hdmi-a3.html

  * igt@kms_flip@basic-flip-vs-dpms@b-edp1:
    - bat-lnl-1:          [PASS][9] -> [DMESG-WARN][10] +1 other test dmesg-warn
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/bat-lnl-1/igt@kms_flip@basic-flip-vs-dpms@b-edp1.html
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/bat-lnl-1/igt@kms_flip@basic-flip-vs-dpms@b-edp1.html

  * igt@kms_flip@basic-flip-vs-dpms@c-edp1:
    - bat-ptl-2:          [PASS][11] -> [DMESG-WARN][12] +2 other tests dmesg-warn
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/bat-ptl-2/igt@kms_flip@basic-flip-vs-dpms@c-edp1.html
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/bat-ptl-2/igt@kms_flip@basic-flip-vs-dpms@c-edp1.html
    - bat-wcl-1:          [PASS][13] -> [DMESG-WARN][14] +1 other test dmesg-warn
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/bat-wcl-1/igt@kms_flip@basic-flip-vs-dpms@c-edp1.html
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/bat-wcl-1/igt@kms_flip@basic-flip-vs-dpms@c-edp1.html

  * igt@kms_flip@basic-flip-vs-dpms@d-edp1:
    - bat-adlp-7:         [PASS][15] -> [DMESG-WARN][16] +1 other test dmesg-warn
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/bat-adlp-7/igt@kms_flip@basic-flip-vs-dpms@d-edp1.html
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/bat-adlp-7/igt@kms_flip@basic-flip-vs-dpms@d-edp1.html

  * igt@kms_flip@basic-flip-vs-dpms@d-hdmi-a3:
    - bat-bmg-1:          [PASS][17] -> [DMESG-WARN][18] +2 other tests dmesg-warn
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/bat-bmg-1/igt@kms_flip@basic-flip-vs-dpms@d-hdmi-a3.html
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/bat-bmg-1/igt@kms_flip@basic-flip-vs-dpms@d-hdmi-a3.html

  
#### Warnings ####

  * igt@kms_flip@basic-flip-vs-dpms:
    - bat-adlp-7:         [DMESG-WARN][19] ([Intel XE#7483]) -> [ABORT][20] +1 other test abort
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/bat-adlp-7/igt@kms_flip@basic-flip-vs-dpms.html
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/bat-adlp-7/igt@kms_flip@basic-flip-vs-dpms.html

  
  [Intel XE#7483]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7483


Build changes
-------------

  * Linux: xe-4661-1242b36e0da950a66f2267e1c15395962dad569c -> xe-pw-161586v2

  IGT_8781: 911c75d8ee24b6d42d31e76bc60149a9350f1190 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-4661-1242b36e0da950a66f2267e1c15395962dad569c: 1242b36e0da950a66f2267e1c15395962dad569c
  xe-pw-161586v2: 161586v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/index.html

[-- Attachment #2: Type: text/html, Size: 6220 bytes --]

✗ Xe.CI.FULL: failure for Refactor LT PHY PLL handling to use DPLL framework (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 35493 bytes --]

== Series Details ==

Series: Refactor LT PHY PLL handling to use DPLL framework (rev2)
URL   : https://patchwork.freedesktop.org/series/161586/
State : failure

== Summary ==

CI Bug Log - changes from xe-4661-1242b36e0da950a66f2267e1c15395962dad569c_FULL -> xe-pw-161586v2_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-161586v2_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-161586v2_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-161586v2_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_flip@2x-dpms-vs-vblank-race@cd-dp2-hdmi-a3:
    - shard-bmg:          [PASS][1] -> [DMESG-WARN][2] +41 other tests dmesg-warn
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-bmg-9/igt@kms_flip@2x-dpms-vs-vblank-race@cd-dp2-hdmi-a3.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-bmg-9/igt@kms_flip@2x-dpms-vs-vblank-race@cd-dp2-hdmi-a3.html

  * igt@kms_flip@basic-flip-vs-dpms@c-dp2:
    - shard-bmg:          NOTRUN -> [DMESG-WARN][3] +3 other tests dmesg-warn
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-bmg-1/igt@kms_flip@basic-flip-vs-dpms@c-dp2.html

  * igt@kms_flip@dpms-vs-vblank-race@b-edp1:
    - shard-lnl:          [PASS][4] -> [DMESG-WARN][5] +17 other tests dmesg-warn
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-lnl-5/igt@kms_flip@dpms-vs-vblank-race@b-edp1.html
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-1/igt@kms_flip@dpms-vs-vblank-race@b-edp1.html

  * igt@kms_flip@single-buffer-flip-vs-dpms-off-vs-modeset-interruptible@a-dp2:
    - shard-bmg:          [PASS][6] -> [ABORT][7] +19 other tests abort
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-bmg-4/igt@kms_flip@single-buffer-flip-vs-dpms-off-vs-modeset-interruptible@a-dp2.html
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-bmg-3/igt@kms_flip@single-buffer-flip-vs-dpms-off-vs-modeset-interruptible@a-dp2.html

  * igt@kms_pm_dc@dc9-dpms:
    - shard-lnl:          [PASS][8] -> [ABORT][9] +20 other tests abort
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-lnl-7/igt@kms_pm_dc@dc9-dpms.html
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-6/igt@kms_pm_dc@dc9-dpms.html

  * igt@kms_vblank@ts-continuation-dpms-rpm@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [ABORT][10] +1 other test abort
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-bmg-6/igt@kms_vblank@ts-continuation-dpms-rpm@pipe-a-dp-2.html

  * igt@kms_vblank@ts-continuation-dpms-suspend@pipe-c-edp-1:
    - shard-lnl:          [PASS][11] -> [INCOMPLETE][12]
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-lnl-5/igt@kms_vblank@ts-continuation-dpms-suspend@pipe-c-edp-1.html
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-7/igt@kms_vblank@ts-continuation-dpms-suspend@pipe-c-edp-1.html

  * igt@xe_pm@s3-d3hot-basic-exec:
    - shard-lnl:          NOTRUN -> [ABORT][13]
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-3/igt@xe_pm@s3-d3hot-basic-exec.html

  
#### Warnings ####

  * igt@xe_pm@d3cold-i2c:
    - shard-lnl:          [SKIP][14] ([Intel XE#5694] / [Intel XE#7370]) -> [ABORT][15]
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-lnl-7/igt@xe_pm@d3cold-i2c.html
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-4/igt@xe_pm@d3cold-i2c.html

  * igt@xe_pm@d3cold-mmap-vram:
    - shard-lnl:          [SKIP][16] ([Intel XE#2284] / [Intel XE#366] / [Intel XE#7370]) -> [ABORT][17] +3 other tests abort
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-lnl-4/igt@xe_pm@d3cold-mmap-vram.html
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-6/igt@xe_pm@d3cold-mmap-vram.html

  * igt@xe_pm@d3cold-mocs:
    - shard-lnl:          [SKIP][18] ([Intel XE#2284] / [Intel XE#7370]) -> [ABORT][19]
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-lnl-8/igt@xe_pm@d3cold-mocs.html
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-3/igt@xe_pm@d3cold-mocs.html

  * igt@xe_pm@d3hot-mmap-vram:
    - shard-lnl:          [SKIP][20] ([Intel XE#1948]) -> [ABORT][21]
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-lnl-2/igt@xe_pm@d3hot-mmap-vram.html
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-8/igt@xe_pm@d3hot-mmap-vram.html

  * igt@xe_pm@s2idle-d3cold-basic-exec:
    - shard-bmg:          [SKIP][22] ([Intel XE#2284] / [Intel XE#7370]) -> [ABORT][23] +3 other tests abort
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-bmg-2/igt@xe_pm@s2idle-d3cold-basic-exec.html
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-bmg-7/igt@xe_pm@s2idle-d3cold-basic-exec.html

  
Known issues
------------

  Here are the changes found in xe-pw-161586v2_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_3d@basic:
    - shard-lnl:          NOTRUN -> [SKIP][24] ([Intel XE#6011])
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-3/igt@kms_3d@basic.html

  * igt@kms_big_fb@y-tiled-8bpp-rotate-180:
    - shard-lnl:          NOTRUN -> [SKIP][25] ([Intel XE#1124])
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-3/igt@kms_big_fb@y-tiled-8bpp-rotate-180.html

  * igt@kms_bw@connected-linear-tiling-3-displays-2160x1440p:
    - shard-lnl:          NOTRUN -> [SKIP][26] ([Intel XE#2191] / [Intel XE#7373])
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-3/igt@kms_bw@connected-linear-tiling-3-displays-2160x1440p.html

  * igt@kms_bw@linear-tiling-4-displays-2160x1440p:
    - shard-lnl:          NOTRUN -> [SKIP][27] ([Intel XE#1512] / [Intel XE#7392])
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-3/igt@kms_bw@linear-tiling-4-displays-2160x1440p.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-rc-ccs:
    - shard-lnl:          NOTRUN -> [SKIP][28] ([Intel XE#2887])
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-3/igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-rc-ccs.html

  * igt@kms_chamelium_frames@hdmi-crc-planes-random:
    - shard-lnl:          NOTRUN -> [SKIP][29] ([Intel XE#373]) +1 other test skip
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-3/igt@kms_chamelium_frames@hdmi-crc-planes-random.html

  * igt@kms_content_protection@atomic-dpms@pipe-a-dp-1:
    - shard-bmg:          NOTRUN -> [FAIL][30] ([Intel XE#3304] / [Intel XE#7374])
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-bmg-5/igt@kms_content_protection@atomic-dpms@pipe-a-dp-1.html

  * igt@kms_content_protection@dp-mst-lic-type-1:
    - shard-lnl:          NOTRUN -> [SKIP][31] ([Intel XE#307] / [Intel XE#6974])
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-3/igt@kms_content_protection@dp-mst-lic-type-1.html

  * igt@kms_content_protection@lic-type-0-hdcp14@pipe-a-dp-1:
    - shard-bmg:          NOTRUN -> [FAIL][32] ([Intel XE#3304])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-bmg-5/igt@kms_content_protection@lic-type-0-hdcp14@pipe-a-dp-1.html

  * igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-dirtyfb-tests:
    - shard-lnl:          NOTRUN -> [SKIP][33] ([Intel XE#4422] / [Intel XE#7442])
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-3/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-dirtyfb-tests.html

  * igt@kms_flip@2x-flip-vs-rmfb-interruptible:
    - shard-lnl:          NOTRUN -> [SKIP][34] ([Intel XE#1421]) +1 other test skip
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-3/igt@kms_flip@2x-flip-vs-rmfb-interruptible.html

  * igt@kms_flip@flip-vs-suspend@c-hdmi-a3:
    - shard-bmg:          [PASS][35] -> [INCOMPLETE][36] ([Intel XE#2049] / [Intel XE#2597]) +1 other test incomplete
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-bmg-9/igt@kms_flip@flip-vs-suspend@c-hdmi-a3.html
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-bmg-4/igt@kms_flip@flip-vs-suspend@c-hdmi-a3.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling:
    - shard-lnl:          NOTRUN -> [SKIP][37] ([Intel XE#7178] / [Intel XE#7349])
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-3/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html

  * igt@kms_frontbuffer_tracking@fbc-abgr161616f-draw-mmap-wc:
    - shard-lnl:          NOTRUN -> [SKIP][38] ([Intel XE#7061] / [Intel XE#7356])
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-3/igt@kms_frontbuffer_tracking@fbc-abgr161616f-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-shrfb-draw-blt:
    - shard-lnl:          NOTRUN -> [SKIP][39] ([Intel XE#6312] / [Intel XE#651]) +2 other tests skip
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-3/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-blt:
    - shard-lnl:          NOTRUN -> [SKIP][40] ([Intel XE#656]) +1 other test skip
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-3/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-blt.html

  * igt@kms_hdmi_inject@inject-audio:
    - shard-lnl:          NOTRUN -> [SKIP][41] ([Intel XE#1470] / [Intel XE#2853])
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-3/igt@kms_hdmi_inject@inject-audio.html

  * igt@kms_hdr@invalid-hdr:
    - shard-bmg:          [PASS][42] -> [SKIP][43] ([Intel XE#1503])
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-bmg-8/igt@kms_hdr@invalid-hdr.html
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-bmg-9/igt@kms_hdr@invalid-hdr.html

  * igt@kms_psr2_sf@pr-plane-move-sf-dmg-area:
    - shard-lnl:          NOTRUN -> [SKIP][44] ([Intel XE#2893] / [Intel XE#7304])
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-3/igt@kms_psr2_sf@pr-plane-move-sf-dmg-area.html

  * igt@kms_psr2_su@page_flip-xrgb8888:
    - shard-lnl:          NOTRUN -> [SKIP][45] ([Intel XE#1128] / [Intel XE#7413])
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-3/igt@kms_psr2_su@page_flip-xrgb8888.html

  * igt@kms_psr@pr-sprite-render:
    - shard-lnl:          NOTRUN -> [SKIP][46] ([Intel XE#1406])
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-3/igt@kms_psr@pr-sprite-render.html

  * igt@kms_vrr@cmrr@pipe-a-edp-1:
    - shard-lnl:          [PASS][47] -> [FAIL][48] ([Intel XE#4459]) +1 other test fail
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-lnl-2/igt@kms_vrr@cmrr@pipe-a-edp-1.html
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-8/igt@kms_vrr@cmrr@pipe-a-edp-1.html

  * igt@kms_vrr@lobf@pipe-a-edp-1:
    - shard-lnl:          NOTRUN -> [FAIL][49] ([Intel XE#6390] / [Intel XE#7461]) +1 other test fail
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-3/igt@kms_vrr@lobf@pipe-a-edp-1.html

  * igt@xe_eudebug_online@tdctl-parameters:
    - shard-lnl:          NOTRUN -> [SKIP][50] ([Intel XE#4837] / [Intel XE#6665])
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-3/igt@xe_eudebug_online@tdctl-parameters.html

  * igt@xe_evict@evict-threads-large:
    - shard-lnl:          NOTRUN -> [SKIP][51] ([Intel XE#6540] / [Intel XE#688]) +1 other test skip
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-3/igt@xe_evict@evict-threads-large.html

  * igt@xe_exec_balancer@no-exec-cm-virtual-userptr-invalidate-race:
    - shard-lnl:          NOTRUN -> [SKIP][52] ([Intel XE#7482]) +2 other tests skip
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-3/igt@xe_exec_balancer@no-exec-cm-virtual-userptr-invalidate-race.html

  * igt@xe_exec_basic@multigpu-no-exec-null-rebind:
    - shard-lnl:          NOTRUN -> [SKIP][53] ([Intel XE#1392])
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-3/igt@xe_exec_basic@multigpu-no-exec-null-rebind.html

  * igt@xe_exec_fault_mode@many-execqueues-multi-queue-prefetch:
    - shard-lnl:          NOTRUN -> [SKIP][54] ([Intel XE#7136])
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-3/igt@xe_exec_fault_mode@many-execqueues-multi-queue-prefetch.html

  * igt@xe_exec_multi_queue@many-queues-userptr:
    - shard-lnl:          NOTRUN -> [SKIP][55] ([Intel XE#6874]) +2 other tests skip
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-3/igt@xe_exec_multi_queue@many-queues-userptr.html

  * igt@xe_live_ktest@xe_eudebug:
    - shard-lnl:          NOTRUN -> [SKIP][56] ([Intel XE#2833])
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-3/igt@xe_live_ktest@xe_eudebug.html

  * igt@xe_sriov_auto_provisioning@resources-released-on-vfs-disabling:
    - shard-lnl:          NOTRUN -> [SKIP][57] ([Intel XE#4130] / [Intel XE#7366])
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-3/igt@xe_sriov_auto_provisioning@resources-released-on-vfs-disabling.html

  * igt@xe_sriov_flr@flr-vf1-clear:
    - shard-lnl:          NOTRUN -> [SKIP][58] ([Intel XE#3342])
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-3/igt@xe_sriov_flr@flr-vf1-clear.html

  
#### Possible fixes ####

  * igt@kms_bw@linear-tiling-1-displays-3840x2160p:
    - shard-bmg:          [SKIP][59] ([Intel XE#367] / [Intel XE#7354]) -> [PASS][60]
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-bmg-2/igt@kms_bw@linear-tiling-1-displays-3840x2160p.html
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-bmg-5/igt@kms_bw@linear-tiling-1-displays-3840x2160p.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-lnl:          [FAIL][61] ([Intel XE#301]) -> [PASS][62] +1 other test pass
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-6/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@xe_evict@evict-beng-mixed-many-threads-small:
    - shard-bmg:          [INCOMPLETE][63] ([Intel XE#6321]) -> [PASS][64]
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-bmg-2/igt@xe_evict@evict-beng-mixed-many-threads-small.html
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-bmg-5/igt@xe_evict@evict-beng-mixed-many-threads-small.html

  * igt@xe_exec_threads@threads-mixed-shared-vm-userptr-invalidate:
    - shard-lnl:          [ABORT][65] -> [PASS][66]
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-lnl-8/igt@xe_exec_threads@threads-mixed-shared-vm-userptr-invalidate.html
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-3/igt@xe_exec_threads@threads-mixed-shared-vm-userptr-invalidate.html

  * igt@xe_module_load@load:
    - shard-lnl:          ([PASS][67], [PASS][68], [PASS][69], [PASS][70], [PASS][71], [PASS][72], [PASS][73], [PASS][74], [PASS][75], [PASS][76], [PASS][77], [PASS][78], [PASS][79], [PASS][80], [PASS][81], [PASS][82], [PASS][83], [PASS][84], [PASS][85], [PASS][86], [SKIP][87], [PASS][88], [PASS][89], [PASS][90], [PASS][91], [PASS][92]) ([Intel XE#378] / [Intel XE#7405]) -> ([PASS][93], [PASS][94], [PASS][95], [PASS][96], [PASS][97], [PASS][98], [PASS][99], [PASS][100], [PASS][101], [PASS][102], [PASS][103], [PASS][104], [PASS][105], [PASS][106], [PASS][107], [PASS][108], [PASS][109], [PASS][110], [PASS][111], [PASS][112], [PASS][113], [PASS][114], [PASS][115], [PASS][116], [PASS][117])
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-lnl-6/igt@xe_module_load@load.html
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-lnl-1/igt@xe_module_load@load.html
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-lnl-4/igt@xe_module_load@load.html
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-lnl-5/igt@xe_module_load@load.html
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-lnl-5/igt@xe_module_load@load.html
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-lnl-6/igt@xe_module_load@load.html
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-lnl-2/igt@xe_module_load@load.html
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-lnl-3/igt@xe_module_load@load.html
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-lnl-5/igt@xe_module_load@load.html
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-lnl-3/igt@xe_module_load@load.html
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-lnl-3/igt@xe_module_load@load.html
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-lnl-6/igt@xe_module_load@load.html
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-lnl-4/igt@xe_module_load@load.html
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-lnl-8/igt@xe_module_load@load.html
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-lnl-8/igt@xe_module_load@load.html
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-lnl-4/igt@xe_module_load@load.html
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-lnl-2/igt@xe_module_load@load.html
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-lnl-2/igt@xe_module_load@load.html
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-lnl-8/igt@xe_module_load@load.html
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-lnl-8/igt@xe_module_load@load.html
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-lnl-1/igt@xe_module_load@load.html
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-lnl-7/igt@xe_module_load@load.html
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-lnl-7/igt@xe_module_load@load.html
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-lnl-7/igt@xe_module_load@load.html
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-lnl-1/igt@xe_module_load@load.html
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-lnl-1/igt@xe_module_load@load.html
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-7/igt@xe_module_load@load.html
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-1/igt@xe_module_load@load.html
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-2/igt@xe_module_load@load.html
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-3/igt@xe_module_load@load.html
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-8/igt@xe_module_load@load.html
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-2/igt@xe_module_load@load.html
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-2/igt@xe_module_load@load.html
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-3/igt@xe_module_load@load.html
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-1/igt@xe_module_load@load.html
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-1/igt@xe_module_load@load.html
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-7/igt@xe_module_load@load.html
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-6/igt@xe_module_load@load.html
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-1/igt@xe_module_load@load.html
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-6/igt@xe_module_load@load.html
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-4/igt@xe_module_load@load.html
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-8/igt@xe_module_load@load.html
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-4/igt@xe_module_load@load.html
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-8/igt@xe_module_load@load.html
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-4/igt@xe_module_load@load.html
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-5/igt@xe_module_load@load.html
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-5/igt@xe_module_load@load.html
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-3/igt@xe_module_load@load.html
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-5/igt@xe_module_load@load.html
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-6/igt@xe_module_load@load.html
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-lnl-7/igt@xe_module_load@load.html
    - shard-bmg:          ([PASS][118], [PASS][119], [PASS][120], [PASS][121], [PASS][122], [PASS][123], [PASS][124], [PASS][125], [SKIP][126], [PASS][127], [PASS][128], [PASS][129], [PASS][130], [PASS][131], [PASS][132], [PASS][133], [PASS][134], [PASS][135], [PASS][136], [PASS][137], [PASS][138], [PASS][139], [PASS][140], [PASS][141], [PASS][142], [PASS][143]) ([Intel XE#2457] / [Intel XE#7405]) -> ([PASS][144], [PASS][145], [PASS][146], [PASS][147], [PASS][148], [PASS][149], [PASS][150], [PASS][151], [PASS][152], [PASS][153], [PASS][154], [PASS][155], [PASS][156], [PASS][157], [PASS][158], [PASS][159], [PASS][160], [PASS][161], [PASS][162], [PASS][163], [PASS][164], [PASS][165], [PASS][166], [PASS][167])
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-bmg-5/igt@xe_module_load@load.html
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-bmg-4/igt@xe_module_load@load.html
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-bmg-4/igt@xe_module_load@load.html
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-bmg-5/igt@xe_module_load@load.html
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-bmg-7/igt@xe_module_load@load.html
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-bmg-7/igt@xe_module_load@load.html
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-bmg-4/igt@xe_module_load@load.html
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-bmg-5/igt@xe_module_load@load.html
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-bmg-2/igt@xe_module_load@load.html
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-bmg-8/igt@xe_module_load@load.html
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-bmg-8/igt@xe_module_load@load.html
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-bmg-9/igt@xe_module_load@load.html
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-bmg-9/igt@xe_module_load@load.html
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-bmg-9/igt@xe_module_load@load.html
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-bmg-1/igt@xe_module_load@load.html
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-bmg-1/igt@xe_module_load@load.html
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-bmg-1/igt@xe_module_load@load.html
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-bmg-3/igt@xe_module_load@load.html
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-bmg-6/igt@xe_module_load@load.html
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-bmg-6/igt@xe_module_load@load.html
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-bmg-3/igt@xe_module_load@load.html
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-bmg-8/igt@xe_module_load@load.html
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-bmg-2/igt@xe_module_load@load.html
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-bmg-2/igt@xe_module_load@load.html
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-bmg-4/igt@xe_module_load@load.html
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4661-1242b36e0da950a66f2267e1c15395962dad569c/shard-bmg-5/igt@xe_module_load@load.html
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-bmg-6/igt@xe_module_load@load.html
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-bmg-4/igt@xe_module_load@load.html
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-bmg-6/igt@xe_module_load@load.html
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-bmg-6/igt@xe_module_load@load.html
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-bmg-6/igt@xe_module_load@load.html
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-bmg-8/igt@xe_module_load@load.html
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-bmg-8/igt@xe_module_load@load.html
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-bmg-8/igt@xe_module_load@load.html
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-bmg-1/igt@xe_module_load@load.html
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-bmg-1/igt@xe_module_load@load.html
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-bmg-3/igt@xe_module_load@load.html
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-bmg-3/igt@xe_module_load@load.html
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-bmg-5/igt@xe_module_load@load.html
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-bmg-4/igt@xe_module_load@load.html
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-bmg-3/igt@xe_module_load@load.html
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-bmg-8/igt@xe_module_load@load.html
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-bmg-3/igt@xe_module_load@load.html
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-bmg-5/igt@xe_module_load@load.html
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-bmg-9/igt@xe_module_load@load.html
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-bmg-9/igt@xe_module_load@load.html
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-bmg-1/igt@xe_module_load@load.html
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-bmg-1/igt@xe_module_load@load.html
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-bmg-7/igt@xe_module_load@load.html
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/shard-bmg-7/igt@xe_module_load@load.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1128]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1128
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
  [Intel XE#1470]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1470
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1512]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1512
  [Intel XE#1948]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1948
  [Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
  [Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2457]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2457
  [Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597
  [Intel XE#2833]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2833
  [Intel XE#2853]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2853
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/307
  [Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
  [Intel XE#3342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3342
  [Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378
  [Intel XE#4130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4130
  [Intel XE#4422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4422
  [Intel XE#4459]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4459
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#5694]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5694
  [Intel XE#6011]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6011
  [Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
  [Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
  [Intel XE#6390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6390
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#6540]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6540
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#6665]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6665
  [Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#6974]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6974
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7136
  [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
  [Intel XE#7304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7304
  [Intel XE#7349]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7349
  [Intel XE#7354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7354
  [Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
  [Intel XE#7366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7366
  [Intel XE#7370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7370
  [Intel XE#7373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7373
  [Intel XE#7374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7374
  [Intel XE#7392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7392
  [Intel XE#7405]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7405
  [Intel XE#7413]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7413
  [Intel XE#7442]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7442
  [Intel XE#7461]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7461
  [Intel XE#7482]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7482


Build changes
-------------

  * Linux: xe-4661-1242b36e0da950a66f2267e1c15395962dad569c -> xe-pw-161586v2

  IGT_8781: 911c75d8ee24b6d42d31e76bc60149a9350f1190 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-4661-1242b36e0da950a66f2267e1c15395962dad569c: 1242b36e0da950a66f2267e1c15395962dad569c
  xe-pw-161586v2: 161586v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v2/index.html

[-- Attachment #2: Type: text/html, Size: 37735 bytes --]

✗ CI.checkpatch: warning for Refactor LT PHY PLL handling to use DPLL framework (rev3)

[Patchwork]

== Series Details ==

Series: Refactor LT PHY PLL handling to use DPLL framework (rev3)
URL   : https://patchwork.freedesktop.org/series/161586/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
1f57ba1afceae32108bd24770069f764d940a0e4
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit b0a054e5d124b5778deaec4b78d20de54d3235aa
Author: Mika Kahola <mika.kahola@intel.com>
Date:   Wed Mar 4 13:14:23 2026 +0000

    drm/i915/lt_phy: Enable dpll framework for xe3plpd
    
    xe3plpd platform is supported by dpll framework remove a separate
    check for hw comparison and rely solely on dpll framework
    hw comparison.
    
    Finally, all required hooks are now in place so initialize
    PLL manager for xe3plpd platform and remove the redirections
    to the legacy code paths for clock enable/disable as well as
    state mismatch checks that are no longer needed.
    
    Signed-off-by: Mika Kahola <mika.kahola@intel.com>
+ /mt/dim checkpatch a48305e6a2e6a1ed90df374101dd29542c105d8f drm-intel
062b78f8cb0b drm/i915/lt_phy: Dump missing PLL state parameters
247584a7e68c drm/i915/lt_phy: Add check if PLL is enabled
b00e5a8c2ea4 drm/i915/lt_phy: Add PLL information for xe3plpd
f811c80ff2fa drm/i915/lt_phy: Refactor LT PHY PLL handling to use explicit PLL state
55ffe1635ea4 drm/i915/lt_phy: Add lane_count to PLL state
eab118dbfca0 drm/i915/lt_phy: Add xe3plpd .compute_dplls hook
8538a959f558 drm/i915/lt_phy: Add xe3plpd .get_dplls hook
424fc35a155c drm/i915/lt_phy: Add xe3plpd .put_dplls hook
db54c54edd38 drm/i915/lt_phy: Add xe3plpd .update_active_dpll hook
806e26c69408 drm/i915/lt_phy: Add xe3plpd .update_dpll_ref_clks hook
df7e88a1bd72 drm/i915/lt_phy: Add xe3plpd .dump_hw_state hook
0dedce6b3205 drm/i915/lt_phy: Add xe3plpd .compare_hw_state hook
b20964187517 drm/i915/lt_phy: Add xe3plpd .get_hw_state hook
5cd12ea0eb9d drm/i915/lt_phy: Add xe3plpd .get_freq hook
3bcf94757d32 drm/i915/lt_phy: Add xe3plpd .crtc_get_dpll
d029fba7acca drm/i915/lt_phy: Replace crtc compute clock
9c857c6df07a drm/i915/lt_phy: Add .enable_clock hook on DDI
5cd7eee5c48d drm/i915/lt_phy: Add .disable_clock hook on DDI
50312fe6f8c6 drm/i915/lt_phy: Dump lane count for HW state
6efe6b2cf226 drm/i915/lt_phy: Readout lane count
4e24285215ef drm/i915/lt_phy: Get encoder configuration for xe3plpd platform
09735c1e243f drm/i915/lt_phy: Add xe3plpd Thunderbolt pll hooks
dc91b6e24cd1 drm/i915/lt_phy: Remove LT PHY specific state verification
-:38: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#38: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:5124:
+			pll_mismatch = !dpll_mgr->compare_hw_state(&pll->state.hw_state, &dpll_hw_state);

-:40: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#40: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:5126:
+			pll_mismatch = memcmp(&pll->state.hw_state, &dpll_hw_state, sizeof(dpll_hw_state));

total: 0 errors, 2 warnings, 0 checks, 86 lines checked
b0a054e5d124 drm/i915/lt_phy: Enable dpll framework for xe3plpd

✓ CI.KUnit: success for Refactor LT PHY PLL handling to use DPLL framework (rev3)

[Patchwork]

== Series Details ==

Series: Refactor LT PHY PLL handling to use DPLL framework (rev3)
URL   : https://patchwork.freedesktop.org/series/161586/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[20:27:28] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[20:27:32] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[20:28:10] Starting KUnit Kernel (1/1)...
[20:28:10] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[20:28:10] ================== guc_buf (11 subtests) ===================
[20:28:10] [PASSED] test_smallest
[20:28:10] [PASSED] test_largest
[20:28:10] [PASSED] test_granular
[20:28:10] [PASSED] test_unique
[20:28:10] [PASSED] test_overlap
[20:28:10] [PASSED] test_reusable
[20:28:10] [PASSED] test_too_big
[20:28:10] [PASSED] test_flush
[20:28:10] [PASSED] test_lookup
[20:28:10] [PASSED] test_data
[20:28:10] [PASSED] test_class
[20:28:10] ===================== [PASSED] guc_buf =====================
[20:28:10] =================== guc_dbm (7 subtests) ===================
[20:28:10] [PASSED] test_empty
[20:28:10] [PASSED] test_default
[20:28:10] ======================== test_size  ========================
[20:28:10] [PASSED] 4
[20:28:10] [PASSED] 8
[20:28:10] [PASSED] 32
[20:28:10] [PASSED] 256
[20:28:10] ==================== [PASSED] test_size ====================
[20:28:10] ======================= test_reuse  ========================
[20:28:10] [PASSED] 4
[20:28:10] [PASSED] 8
[20:28:10] [PASSED] 32
[20:28:10] [PASSED] 256
[20:28:10] =================== [PASSED] test_reuse ====================
[20:28:10] =================== test_range_overlap  ====================
[20:28:10] [PASSED] 4
[20:28:10] [PASSED] 8
[20:28:10] [PASSED] 32
[20:28:10] [PASSED] 256
[20:28:10] =============== [PASSED] test_range_overlap ================
[20:28:10] =================== test_range_compact  ====================
[20:28:10] [PASSED] 4
[20:28:10] [PASSED] 8
[20:28:10] [PASSED] 32
[20:28:10] [PASSED] 256
[20:28:10] =============== [PASSED] test_range_compact ================
[20:28:10] ==================== test_range_spare  =====================
[20:28:10] [PASSED] 4
[20:28:10] [PASSED] 8
[20:28:10] [PASSED] 32
[20:28:10] [PASSED] 256
[20:28:10] ================ [PASSED] test_range_spare =================
[20:28:10] ===================== [PASSED] guc_dbm =====================
[20:28:10] =================== guc_idm (6 subtests) ===================
[20:28:10] [PASSED] bad_init
[20:28:10] [PASSED] no_init
[20:28:10] [PASSED] init_fini
[20:28:10] [PASSED] check_used
[20:28:10] [PASSED] check_quota
[20:28:10] [PASSED] check_all
[20:28:10] ===================== [PASSED] guc_idm =====================
[20:28:10] ================== no_relay (3 subtests) ===================
[20:28:10] [PASSED] xe_drops_guc2pf_if_not_ready
[20:28:10] [PASSED] xe_drops_guc2vf_if_not_ready
[20:28:10] [PASSED] xe_rejects_send_if_not_ready
[20:28:10] ==================== [PASSED] no_relay =====================
[20:28:10] ================== pf_relay (14 subtests) ==================
[20:28:10] [PASSED] pf_rejects_guc2pf_too_short
[20:28:10] [PASSED] pf_rejects_guc2pf_too_long
[20:28:10] [PASSED] pf_rejects_guc2pf_no_payload
[20:28:10] [PASSED] pf_fails_no_payload
[20:28:10] [PASSED] pf_fails_bad_origin
[20:28:10] [PASSED] pf_fails_bad_type
[20:28:10] [PASSED] pf_txn_reports_error
[20:28:10] [PASSED] pf_txn_sends_pf2guc
[20:28:10] [PASSED] pf_sends_pf2guc
[20:28:10] [SKIPPED] pf_loopback_nop
[20:28:10] [SKIPPED] pf_loopback_echo
[20:28:10] [SKIPPED] pf_loopback_fail
[20:28:10] [SKIPPED] pf_loopback_busy
[20:28:10] [SKIPPED] pf_loopback_retry
[20:28:10] ==================== [PASSED] pf_relay =====================
[20:28:10] ================== vf_relay (3 subtests) ===================
[20:28:10] [PASSED] vf_rejects_guc2vf_too_short
[20:28:10] [PASSED] vf_rejects_guc2vf_too_long
[20:28:10] [PASSED] vf_rejects_guc2vf_no_payload
[20:28:10] ==================== [PASSED] vf_relay =====================
[20:28:10] ================ pf_gt_config (9 subtests) =================
[20:28:10] [PASSED] fair_contexts_1vf
[20:28:10] [PASSED] fair_doorbells_1vf
[20:28:10] [PASSED] fair_ggtt_1vf
[20:28:10] ====================== fair_vram_1vf  ======================
[20:28:10] [PASSED] 3.50 GiB
[20:28:10] [PASSED] 11.5 GiB
[20:28:10] [PASSED] 15.5 GiB
[20:28:10] [PASSED] 31.5 GiB
[20:28:10] [PASSED] 63.5 GiB
[20:28:10] [PASSED] 1.91 GiB
[20:28:10] ================== [PASSED] fair_vram_1vf ==================
[20:28:10] ================ fair_vram_1vf_admin_only  =================
[20:28:10] [PASSED] 3.50 GiB
[20:28:10] [PASSED] 11.5 GiB
[20:28:10] [PASSED] 15.5 GiB
[20:28:10] [PASSED] 31.5 GiB
[20:28:10] [PASSED] 63.5 GiB
[20:28:10] [PASSED] 1.91 GiB
[20:28:10] ============ [PASSED] fair_vram_1vf_admin_only =============
[20:28:10] ====================== fair_contexts  ======================
[20:28:10] [PASSED] 1 VF
[20:28:10] [PASSED] 2 VFs
[20:28:10] [PASSED] 3 VFs
[20:28:10] [PASSED] 4 VFs
[20:28:10] [PASSED] 5 VFs
[20:28:10] [PASSED] 6 VFs
[20:28:10] [PASSED] 7 VFs
[20:28:10] [PASSED] 8 VFs
[20:28:10] [PASSED] 9 VFs
[20:28:10] [PASSED] 10 VFs
[20:28:10] [PASSED] 11 VFs
[20:28:10] [PASSED] 12 VFs
[20:28:10] [PASSED] 13 VFs
[20:28:10] [PASSED] 14 VFs
[20:28:10] [PASSED] 15 VFs
[20:28:10] [PASSED] 16 VFs
[20:28:10] [PASSED] 17 VFs
[20:28:10] [PASSED] 18 VFs
[20:28:10] [PASSED] 19 VFs
[20:28:10] [PASSED] 20 VFs
[20:28:10] [PASSED] 21 VFs
[20:28:10] [PASSED] 22 VFs
[20:28:10] [PASSED] 23 VFs
[20:28:10] [PASSED] 24 VFs
[20:28:10] [PASSED] 25 VFs
[20:28:10] [PASSED] 26 VFs
[20:28:10] [PASSED] 27 VFs
[20:28:10] [PASSED] 28 VFs
[20:28:10] [PASSED] 29 VFs
[20:28:10] [PASSED] 30 VFs
[20:28:10] [PASSED] 31 VFs
[20:28:10] [PASSED] 32 VFs
[20:28:10] [PASSED] 33 VFs
[20:28:10] [PASSED] 34 VFs
[20:28:10] [PASSED] 35 VFs
[20:28:10] [PASSED] 36 VFs
[20:28:10] [PASSED] 37 VFs
[20:28:10] [PASSED] 38 VFs
[20:28:10] [PASSED] 39 VFs
[20:28:10] [PASSED] 40 VFs
[20:28:10] [PASSED] 41 VFs
[20:28:10] [PASSED] 42 VFs
[20:28:10] [PASSED] 43 VFs
[20:28:10] [PASSED] 44 VFs
[20:28:10] [PASSED] 45 VFs
[20:28:10] [PASSED] 46 VFs
[20:28:10] [PASSED] 47 VFs
[20:28:10] [PASSED] 48 VFs
[20:28:10] [PASSED] 49 VFs
[20:28:10] [PASSED] 50 VFs
[20:28:10] [PASSED] 51 VFs
[20:28:10] [PASSED] 52 VFs
[20:28:10] [PASSED] 53 VFs
[20:28:10] [PASSED] 54 VFs
[20:28:10] [PASSED] 55 VFs
[20:28:10] [PASSED] 56 VFs
[20:28:10] [PASSED] 57 VFs
[20:28:10] [PASSED] 58 VFs
[20:28:10] [PASSED] 59 VFs
[20:28:10] [PASSED] 60 VFs
[20:28:10] [PASSED] 61 VFs
[20:28:10] [PASSED] 62 VFs
[20:28:10] [PASSED] 63 VFs
[20:28:10] ================== [PASSED] fair_contexts ==================
[20:28:10] ===================== fair_doorbells  ======================
[20:28:10] [PASSED] 1 VF
[20:28:10] [PASSED] 2 VFs
[20:28:10] [PASSED] 3 VFs
[20:28:10] [PASSED] 4 VFs
[20:28:10] [PASSED] 5 VFs
[20:28:10] [PASSED] 6 VFs
[20:28:10] [PASSED] 7 VFs
[20:28:10] [PASSED] 8 VFs
[20:28:10] [PASSED] 9 VFs
[20:28:10] [PASSED] 10 VFs
[20:28:10] [PASSED] 11 VFs
[20:28:10] [PASSED] 12 VFs
[20:28:10] [PASSED] 13 VFs
[20:28:10] [PASSED] 14 VFs
[20:28:10] [PASSED] 15 VFs
[20:28:10] [PASSED] 16 VFs
[20:28:10] [PASSED] 17 VFs
[20:28:10] [PASSED] 18 VFs
[20:28:10] [PASSED] 19 VFs
[20:28:10] [PASSED] 20 VFs
[20:28:10] [PASSED] 21 VFs
[20:28:10] [PASSED] 22 VFs
[20:28:10] [PASSED] 23 VFs
[20:28:10] [PASSED] 24 VFs
[20:28:10] [PASSED] 25 VFs
[20:28:10] [PASSED] 26 VFs
[20:28:10] [PASSED] 27 VFs
[20:28:10] [PASSED] 28 VFs
[20:28:10] [PASSED] 29 VFs
[20:28:10] [PASSED] 30 VFs
[20:28:10] [PASSED] 31 VFs
[20:28:10] [PASSED] 32 VFs
[20:28:10] [PASSED] 33 VFs
[20:28:10] [PASSED] 34 VFs
[20:28:10] [PASSED] 35 VFs
[20:28:10] [PASSED] 36 VFs
[20:28:10] [PASSED] 37 VFs
[20:28:10] [PASSED] 38 VFs
[20:28:10] [PASSED] 39 VFs
[20:28:10] [PASSED] 40 VFs
[20:28:10] [PASSED] 41 VFs
[20:28:10] [PASSED] 42 VFs
[20:28:10] [PASSED] 43 VFs
[20:28:10] [PASSED] 44 VFs
[20:28:10] [PASSED] 45 VFs
[20:28:10] [PASSED] 46 VFs
[20:28:10] [PASSED] 47 VFs
[20:28:10] [PASSED] 48 VFs
[20:28:10] [PASSED] 49 VFs
[20:28:10] [PASSED] 50 VFs
[20:28:10] [PASSED] 51 VFs
[20:28:10] [PASSED] 52 VFs
[20:28:10] [PASSED] 53 VFs
[20:28:10] [PASSED] 54 VFs
[20:28:10] [PASSED] 55 VFs
[20:28:10] [PASSED] 56 VFs
[20:28:10] [PASSED] 57 VFs
[20:28:10] [PASSED] 58 VFs
[20:28:10] [PASSED] 59 VFs
[20:28:10] [PASSED] 60 VFs
[20:28:10] [PASSED] 61 VFs
[20:28:10] [PASSED] 62 VFs
[20:28:10] [PASSED] 63 VFs
[20:28:10] ================= [PASSED] fair_doorbells ==================
[20:28:10] ======================== fair_ggtt  ========================
[20:28:10] [PASSED] 1 VF
[20:28:10] [PASSED] 2 VFs
[20:28:10] [PASSED] 3 VFs
[20:28:10] [PASSED] 4 VFs
[20:28:10] [PASSED] 5 VFs
[20:28:10] [PASSED] 6 VFs
[20:28:10] [PASSED] 7 VFs
[20:28:10] [PASSED] 8 VFs
[20:28:10] [PASSED] 9 VFs
[20:28:10] [PASSED] 10 VFs
[20:28:10] [PASSED] 11 VFs
[20:28:10] [PASSED] 12 VFs
[20:28:10] [PASSED] 13 VFs
[20:28:10] [PASSED] 14 VFs
[20:28:10] [PASSED] 15 VFs
[20:28:10] [PASSED] 16 VFs
[20:28:10] [PASSED] 17 VFs
[20:28:10] [PASSED] 18 VFs
[20:28:10] [PASSED] 19 VFs
[20:28:10] [PASSED] 20 VFs
[20:28:10] [PASSED] 21 VFs
[20:28:10] [PASSED] 22 VFs
[20:28:10] [PASSED] 23 VFs
[20:28:10] [PASSED] 24 VFs
[20:28:10] [PASSED] 25 VFs
[20:28:10] [PASSED] 26 VFs
[20:28:10] [PASSED] 27 VFs
[20:28:10] [PASSED] 28 VFs
[20:28:10] [PASSED] 29 VFs
[20:28:10] [PASSED] 30 VFs
[20:28:10] [PASSED] 31 VFs
[20:28:10] [PASSED] 32 VFs
[20:28:10] [PASSED] 33 VFs
[20:28:10] [PASSED] 34 VFs
[20:28:10] [PASSED] 35 VFs
[20:28:10] [PASSED] 36 VFs
[20:28:10] [PASSED] 37 VFs
[20:28:10] [PASSED] 38 VFs
[20:28:10] [PASSED] 39 VFs
[20:28:10] [PASSED] 40 VFs
[20:28:10] [PASSED] 41 VFs
[20:28:10] [PASSED] 42 VFs
[20:28:10] [PASSED] 43 VFs
[20:28:10] [PASSED] 44 VFs
[20:28:10] [PASSED] 45 VFs
[20:28:10] [PASSED] 46 VFs
[20:28:10] [PASSED] 47 VFs
[20:28:10] [PASSED] 48 VFs
[20:28:10] [PASSED] 49 VFs
[20:28:10] [PASSED] 50 VFs
[20:28:10] [PASSED] 51 VFs
[20:28:10] [PASSED] 52 VFs
[20:28:10] [PASSED] 53 VFs
[20:28:10] [PASSED] 54 VFs
[20:28:10] [PASSED] 55 VFs
[20:28:10] [PASSED] 56 VFs
[20:28:10] [PASSED] 57 VFs
[20:28:10] [PASSED] 58 VFs
[20:28:10] [PASSED] 59 VFs
[20:28:10] [PASSED] 60 VFs
[20:28:10] [PASSED] 61 VFs
[20:28:10] [PASSED] 62 VFs
[20:28:10] [PASSED] 63 VFs
[20:28:10] ==================== [PASSED] fair_ggtt ====================
[20:28:10] ======================== fair_vram  ========================
[20:28:10] [PASSED] 1 VF
[20:28:10] [PASSED] 2 VFs
[20:28:10] [PASSED] 3 VFs
[20:28:10] [PASSED] 4 VFs
[20:28:10] [PASSED] 5 VFs
[20:28:10] [PASSED] 6 VFs
[20:28:10] [PASSED] 7 VFs
[20:28:10] [PASSED] 8 VFs
[20:28:10] [PASSED] 9 VFs
[20:28:10] [PASSED] 10 VFs
[20:28:10] [PASSED] 11 VFs
[20:28:10] [PASSED] 12 VFs
[20:28:10] [PASSED] 13 VFs
[20:28:10] [PASSED] 14 VFs
[20:28:10] [PASSED] 15 VFs
[20:28:10] [PASSED] 16 VFs
[20:28:10] [PASSED] 17 VFs
[20:28:10] [PASSED] 18 VFs
[20:28:10] [PASSED] 19 VFs
[20:28:10] [PASSED] 20 VFs
[20:28:10] [PASSED] 21 VFs
[20:28:10] [PASSED] 22 VFs
[20:28:10] [PASSED] 23 VFs
[20:28:10] [PASSED] 24 VFs
[20:28:10] [PASSED] 25 VFs
[20:28:10] [PASSED] 26 VFs
[20:28:10] [PASSED] 27 VFs
[20:28:10] [PASSED] 28 VFs
[20:28:10] [PASSED] 29 VFs
[20:28:10] [PASSED] 30 VFs
[20:28:10] [PASSED] 31 VFs
[20:28:10] [PASSED] 32 VFs
[20:28:10] [PASSED] 33 VFs
[20:28:10] [PASSED] 34 VFs
[20:28:10] [PASSED] 35 VFs
[20:28:10] [PASSED] 36 VFs
[20:28:10] [PASSED] 37 VFs
[20:28:10] [PASSED] 38 VFs
[20:28:10] [PASSED] 39 VFs
[20:28:10] [PASSED] 40 VFs
[20:28:10] [PASSED] 41 VFs
[20:28:10] [PASSED] 42 VFs
[20:28:10] [PASSED] 43 VFs
[20:28:10] [PASSED] 44 VFs
[20:28:10] [PASSED] 45 VFs
[20:28:10] [PASSED] 46 VFs
[20:28:10] [PASSED] 47 VFs
[20:28:10] [PASSED] 48 VFs
[20:28:10] [PASSED] 49 VFs
[20:28:10] [PASSED] 50 VFs
[20:28:10] [PASSED] 51 VFs
[20:28:10] [PASSED] 52 VFs
[20:28:10] [PASSED] 53 VFs
[20:28:10] [PASSED] 54 VFs
[20:28:10] [PASSED] 55 VFs
[20:28:10] [PASSED] 56 VFs
[20:28:10] [PASSED] 57 VFs
[20:28:10] [PASSED] 58 VFs
[20:28:10] [PASSED] 59 VFs
[20:28:10] [PASSED] 60 VFs
[20:28:10] [PASSED] 61 VFs
[20:28:10] [PASSED] 62 VFs
[20:28:10] [PASSED] 63 VFs
[20:28:10] ==================== [PASSED] fair_vram ====================
[20:28:10] ================== [PASSED] pf_gt_config ===================
[20:28:10] ===================== lmtt (1 subtest) =====================
[20:28:10] ======================== test_ops  =========================
[20:28:10] [PASSED] 2-level
[20:28:10] [PASSED] multi-level
[20:28:10] ==================== [PASSED] test_ops =====================
[20:28:10] ====================== [PASSED] lmtt =======================
[20:28:10] ================= pf_service (11 subtests) =================
[20:28:10] [PASSED] pf_negotiate_any
[20:28:10] [PASSED] pf_negotiate_base_match
[20:28:10] [PASSED] pf_negotiate_base_newer
[20:28:10] [PASSED] pf_negotiate_base_next
[20:28:10] [SKIPPED] pf_negotiate_base_older
[20:28:10] [PASSED] pf_negotiate_base_prev
[20:28:10] [PASSED] pf_negotiate_latest_match
[20:28:10] [PASSED] pf_negotiate_latest_newer
[20:28:10] [PASSED] pf_negotiate_latest_next
[20:28:10] [SKIPPED] pf_negotiate_latest_older
[20:28:10] [SKIPPED] pf_negotiate_latest_prev
[20:28:10] =================== [PASSED] pf_service ====================
[20:28:10] ================= xe_guc_g2g (2 subtests) ==================
[20:28:10] ============== xe_live_guc_g2g_kunit_default  ==============
[20:28:10] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[20:28:10] ============== xe_live_guc_g2g_kunit_allmem  ===============
[20:28:10] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[20:28:10] =================== [SKIPPED] xe_guc_g2g ===================
[20:28:10] =================== xe_mocs (2 subtests) ===================
[20:28:10] ================ xe_live_mocs_kernel_kunit  ================
[20:28:10] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[20:28:10] ================ xe_live_mocs_reset_kunit  =================
[20:28:10] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[20:28:10] ==================== [SKIPPED] xe_mocs =====================
[20:28:10] ================= xe_migrate (2 subtests) ==================
[20:28:10] ================= xe_migrate_sanity_kunit  =================
[20:28:10] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[20:28:10] ================== xe_validate_ccs_kunit  ==================
[20:28:10] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[20:28:10] =================== [SKIPPED] xe_migrate ===================
[20:28:10] ================== xe_dma_buf (1 subtest) ==================
[20:28:10] ==================== xe_dma_buf_kunit  =====================
[20:28:10] ================ [SKIPPED] xe_dma_buf_kunit ================
[20:28:10] =================== [SKIPPED] xe_dma_buf ===================
[20:28:10] ================= xe_bo_shrink (1 subtest) =================
[20:28:10] =================== xe_bo_shrink_kunit  ====================
[20:28:10] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[20:28:10] ================== [SKIPPED] xe_bo_shrink ==================
[20:28:10] ==================== xe_bo (2 subtests) ====================
[20:28:10] ================== xe_ccs_migrate_kunit  ===================
[20:28:10] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[20:28:10] ==================== xe_bo_evict_kunit  ====================
[20:28:10] =============== [SKIPPED] xe_bo_evict_kunit ================
[20:28:10] ===================== [SKIPPED] xe_bo ======================
[20:28:10] ==================== args (13 subtests) ====================
[20:28:10] [PASSED] count_args_test
[20:28:10] [PASSED] call_args_example
[20:28:10] [PASSED] call_args_test
[20:28:10] [PASSED] drop_first_arg_example
[20:28:10] [PASSED] drop_first_arg_test
[20:28:10] [PASSED] first_arg_example
[20:28:10] [PASSED] first_arg_test
[20:28:10] [PASSED] last_arg_example
[20:28:10] [PASSED] last_arg_test
[20:28:10] [PASSED] pick_arg_example
[20:28:10] [PASSED] if_args_example
[20:28:10] [PASSED] if_args_test
[20:28:10] [PASSED] sep_comma_example
[20:28:10] ====================== [PASSED] args =======================
[20:28:10] =================== xe_pci (3 subtests) ====================
[20:28:10] ==================== check_graphics_ip  ====================
[20:28:10] [PASSED] 12.00 Xe_LP
[20:28:10] [PASSED] 12.10 Xe_LP+
[20:28:10] [PASSED] 12.55 Xe_HPG
[20:28:10] [PASSED] 12.60 Xe_HPC
[20:28:10] [PASSED] 12.70 Xe_LPG
[20:28:10] [PASSED] 12.71 Xe_LPG
[20:28:10] [PASSED] 12.74 Xe_LPG+
[20:28:10] [PASSED] 20.01 Xe2_HPG
[20:28:10] [PASSED] 20.02 Xe2_HPG
[20:28:10] [PASSED] 20.04 Xe2_LPG
[20:28:10] [PASSED] 30.00 Xe3_LPG
[20:28:10] [PASSED] 30.01 Xe3_LPG
[20:28:10] [PASSED] 30.03 Xe3_LPG
[20:28:10] [PASSED] 30.04 Xe3_LPG
[20:28:10] [PASSED] 30.05 Xe3_LPG
[20:28:10] [PASSED] 35.10 Xe3p_LPG
[20:28:10] [PASSED] 35.11 Xe3p_XPC
[20:28:10] ================ [PASSED] check_graphics_ip ================
[20:28:10] ===================== check_media_ip  ======================
[20:28:10] [PASSED] 12.00 Xe_M
[20:28:10] [PASSED] 12.55 Xe_HPM
[20:28:10] [PASSED] 13.00 Xe_LPM+
[20:28:10] [PASSED] 13.01 Xe2_HPM
[20:28:10] [PASSED] 20.00 Xe2_LPM
[20:28:10] [PASSED] 30.00 Xe3_LPM
[20:28:10] [PASSED] 30.02 Xe3_LPM
[20:28:10] [PASSED] 35.00 Xe3p_LPM
[20:28:10] [PASSED] 35.03 Xe3p_HPM
[20:28:10] ================= [PASSED] check_media_ip ==================
[20:28:10] =================== check_platform_desc  ===================
[20:28:10] [PASSED] 0x9A60 (TIGERLAKE)
[20:28:10] [PASSED] 0x9A68 (TIGERLAKE)
[20:28:10] [PASSED] 0x9A70 (TIGERLAKE)
[20:28:10] [PASSED] 0x9A40 (TIGERLAKE)
[20:28:10] [PASSED] 0x9A49 (TIGERLAKE)
[20:28:10] [PASSED] 0x9A59 (TIGERLAKE)
[20:28:10] [PASSED] 0x9A78 (TIGERLAKE)
[20:28:10] [PASSED] 0x9AC0 (TIGERLAKE)
[20:28:10] [PASSED] 0x9AC9 (TIGERLAKE)
[20:28:10] [PASSED] 0x9AD9 (TIGERLAKE)
[20:28:10] [PASSED] 0x9AF8 (TIGERLAKE)
[20:28:10] [PASSED] 0x4C80 (ROCKETLAKE)
[20:28:10] [PASSED] 0x4C8A (ROCKETLAKE)
[20:28:10] [PASSED] 0x4C8B (ROCKETLAKE)
[20:28:10] [PASSED] 0x4C8C (ROCKETLAKE)
[20:28:10] [PASSED] 0x4C90 (ROCKETLAKE)
[20:28:10] [PASSED] 0x4C9A (ROCKETLAKE)
[20:28:10] [PASSED] 0x4680 (ALDERLAKE_S)
[20:28:10] [PASSED] 0x4682 (ALDERLAKE_S)
[20:28:10] [PASSED] 0x4688 (ALDERLAKE_S)
[20:28:10] [PASSED] 0x468A (ALDERLAKE_S)
[20:28:10] [PASSED] 0x468B (ALDERLAKE_S)
[20:28:10] [PASSED] 0x4690 (ALDERLAKE_S)
[20:28:10] [PASSED] 0x4692 (ALDERLAKE_S)
[20:28:10] [PASSED] 0x4693 (ALDERLAKE_S)
[20:28:10] [PASSED] 0x46A0 (ALDERLAKE_P)
[20:28:10] [PASSED] 0x46A1 (ALDERLAKE_P)
[20:28:10] [PASSED] 0x46A2 (ALDERLAKE_P)
[20:28:10] [PASSED] 0x46A3 (ALDERLAKE_P)
[20:28:10] [PASSED] 0x46A6 (ALDERLAKE_P)
[20:28:10] [PASSED] 0x46A8 (ALDERLAKE_P)
[20:28:10] [PASSED] 0x46AA (ALDERLAKE_P)
[20:28:10] [PASSED] 0x462A (ALDERLAKE_P)
[20:28:10] [PASSED] 0x4626 (ALDERLAKE_P)
[20:28:10] [PASSED] 0x4628 (ALDERLAKE_P)
[20:28:10] [PASSED] 0x46B0 (ALDERLAKE_P)
[20:28:10] [PASSED] 0x46B1 (ALDERLAKE_P)
[20:28:10] [PASSED] 0x46B2 (ALDERLAKE_P)
[20:28:10] [PASSED] 0x46B3 (ALDERLAKE_P)
[20:28:10] [PASSED] 0x46C0 (ALDERLAKE_P)
[20:28:10] [PASSED] 0x46C1 (ALDERLAKE_P)
[20:28:10] [PASSED] 0x46C2 (ALDERLAKE_P)
[20:28:10] [PASSED] 0x46C3 (ALDERLAKE_P)
[20:28:10] [PASSED] 0x46D0 (ALDERLAKE_N)
[20:28:10] [PASSED] 0x46D1 (ALDERLAKE_N)
[20:28:10] [PASSED] 0x46D2 (ALDERLAKE_N)
[20:28:10] [PASSED] 0x46D3 (ALDERLAKE_N)
[20:28:10] [PASSED] 0x46D4 (ALDERLAKE_N)
[20:28:10] [PASSED] 0xA721 (ALDERLAKE_P)
[20:28:10] [PASSED] 0xA7A1 (ALDERLAKE_P)
[20:28:10] [PASSED] 0xA7A9 (ALDERLAKE_P)
[20:28:10] [PASSED] 0xA7AC (ALDERLAKE_P)
[20:28:10] [PASSED] 0xA7AD (ALDERLAKE_P)
[20:28:10] [PASSED] 0xA720 (ALDERLAKE_P)
[20:28:10] [PASSED] 0xA7A0 (ALDERLAKE_P)
[20:28:10] [PASSED] 0xA7A8 (ALDERLAKE_P)
[20:28:10] [PASSED] 0xA7AA (ALDERLAKE_P)
[20:28:10] [PASSED] 0xA7AB (ALDERLAKE_P)
[20:28:10] [PASSED] 0xA780 (ALDERLAKE_S)
[20:28:10] [PASSED] 0xA781 (ALDERLAKE_S)
[20:28:10] [PASSED] 0xA782 (ALDERLAKE_S)
[20:28:10] [PASSED] 0xA783 (ALDERLAKE_S)
[20:28:10] [PASSED] 0xA788 (ALDERLAKE_S)
[20:28:10] [PASSED] 0xA789 (ALDERLAKE_S)
[20:28:10] [PASSED] 0xA78A (ALDERLAKE_S)
[20:28:10] [PASSED] 0xA78B (ALDERLAKE_S)
[20:28:10] [PASSED] 0x4905 (DG1)
[20:28:10] [PASSED] 0x4906 (DG1)
[20:28:10] [PASSED] 0x4907 (DG1)
[20:28:10] [PASSED] 0x4908 (DG1)
[20:28:10] [PASSED] 0x4909 (DG1)
[20:28:10] [PASSED] 0x56C0 (DG2)
[20:28:10] [PASSED] 0x56C2 (DG2)
[20:28:10] [PASSED] 0x56C1 (DG2)
[20:28:10] [PASSED] 0x7D51 (METEORLAKE)
[20:28:10] [PASSED] 0x7DD1 (METEORLAKE)
[20:28:10] [PASSED] 0x7D41 (METEORLAKE)
[20:28:10] [PASSED] 0x7D67 (METEORLAKE)
[20:28:10] [PASSED] 0xB640 (METEORLAKE)
[20:28:10] [PASSED] 0x56A0 (DG2)
[20:28:10] [PASSED] 0x56A1 (DG2)
[20:28:10] [PASSED] 0x56A2 (DG2)
[20:28:10] [PASSED] 0x56BE (DG2)
[20:28:10] [PASSED] 0x56BF (DG2)
[20:28:10] [PASSED] 0x5690 (DG2)
[20:28:10] [PASSED] 0x5691 (DG2)
[20:28:10] [PASSED] 0x5692 (DG2)
[20:28:10] [PASSED] 0x56A5 (DG2)
[20:28:10] [PASSED] 0x56A6 (DG2)
[20:28:10] [PASSED] 0x56B0 (DG2)
[20:28:10] [PASSED] 0x56B1 (DG2)
[20:28:10] [PASSED] 0x56BA (DG2)
[20:28:10] [PASSED] 0x56BB (DG2)
[20:28:10] [PASSED] 0x56BC (DG2)
[20:28:10] [PASSED] 0x56BD (DG2)
[20:28:10] [PASSED] 0x5693 (DG2)
[20:28:10] [PASSED] 0x5694 (DG2)
[20:28:10] [PASSED] 0x5695 (DG2)
[20:28:10] [PASSED] 0x56A3 (DG2)
[20:28:10] [PASSED] 0x56A4 (DG2)
[20:28:10] [PASSED] 0x56B2 (DG2)
[20:28:10] [PASSED] 0x56B3 (DG2)
[20:28:10] [PASSED] 0x5696 (DG2)
[20:28:10] [PASSED] 0x5697 (DG2)
[20:28:10] [PASSED] 0xB69 (PVC)
[20:28:10] [PASSED] 0xB6E (PVC)
[20:28:10] [PASSED] 0xBD4 (PVC)
[20:28:10] [PASSED] 0xBD5 (PVC)
[20:28:10] [PASSED] 0xBD6 (PVC)
[20:28:10] [PASSED] 0xBD7 (PVC)
[20:28:10] [PASSED] 0xBD8 (PVC)
[20:28:10] [PASSED] 0xBD9 (PVC)
[20:28:10] [PASSED] 0xBDA (PVC)
[20:28:10] [PASSED] 0xBDB (PVC)
[20:28:10] [PASSED] 0xBE0 (PVC)
[20:28:10] [PASSED] 0xBE1 (PVC)
[20:28:10] [PASSED] 0xBE5 (PVC)
[20:28:10] [PASSED] 0x7D40 (METEORLAKE)
[20:28:10] [PASSED] 0x7D45 (METEORLAKE)
[20:28:10] [PASSED] 0x7D55 (METEORLAKE)
[20:28:10] [PASSED] 0x7D60 (METEORLAKE)
[20:28:10] [PASSED] 0x7DD5 (METEORLAKE)
[20:28:10] [PASSED] 0x6420 (LUNARLAKE)
[20:28:10] [PASSED] 0x64A0 (LUNARLAKE)
[20:28:10] [PASSED] 0x64B0 (LUNARLAKE)
[20:28:10] [PASSED] 0xE202 (BATTLEMAGE)
[20:28:10] [PASSED] 0xE209 (BATTLEMAGE)
[20:28:10] [PASSED] 0xE20B (BATTLEMAGE)
[20:28:10] [PASSED] 0xE20C (BATTLEMAGE)
[20:28:10] [PASSED] 0xE20D (BATTLEMAGE)
[20:28:10] [PASSED] 0xE210 (BATTLEMAGE)
[20:28:10] [PASSED] 0xE211 (BATTLEMAGE)
[20:28:10] [PASSED] 0xE212 (BATTLEMAGE)
[20:28:10] [PASSED] 0xE216 (BATTLEMAGE)
[20:28:10] [PASSED] 0xE220 (BATTLEMAGE)
[20:28:10] [PASSED] 0xE221 (BATTLEMAGE)
[20:28:10] [PASSED] 0xE222 (BATTLEMAGE)
[20:28:10] [PASSED] 0xE223 (BATTLEMAGE)
[20:28:10] [PASSED] 0xB080 (PANTHERLAKE)
[20:28:10] [PASSED] 0xB081 (PANTHERLAKE)
[20:28:10] [PASSED] 0xB082 (PANTHERLAKE)
[20:28:10] [PASSED] 0xB083 (PANTHERLAKE)
[20:28:10] [PASSED] 0xB084 (PANTHERLAKE)
[20:28:10] [PASSED] 0xB085 (PANTHERLAKE)
[20:28:10] [PASSED] 0xB086 (PANTHERLAKE)
[20:28:10] [PASSED] 0xB087 (PANTHERLAKE)
[20:28:10] [PASSED] 0xB08F (PANTHERLAKE)
[20:28:10] [PASSED] 0xB090 (PANTHERLAKE)
[20:28:10] [PASSED] 0xB0A0 (PANTHERLAKE)
[20:28:10] [PASSED] 0xB0B0 (PANTHERLAKE)
[20:28:10] [PASSED] 0xFD80 (PANTHERLAKE)
[20:28:10] [PASSED] 0xFD81 (PANTHERLAKE)
[20:28:10] [PASSED] 0xD740 (NOVALAKE_S)
[20:28:10] [PASSED] 0xD741 (NOVALAKE_S)
[20:28:10] [PASSED] 0xD742 (NOVALAKE_S)
[20:28:10] [PASSED] 0xD743 (NOVALAKE_S)
[20:28:10] [PASSED] 0xD744 (NOVALAKE_S)
[20:28:10] [PASSED] 0xD745 (NOVALAKE_S)
[20:28:10] [PASSED] 0x674C (CRESCENTISLAND)
[20:28:10] [PASSED] 0xD750 (NOVALAKE_P)
[20:28:10] [PASSED] 0xD751 (NOVALAKE_P)
[20:28:10] [PASSED] 0xD752 (NOVALAKE_P)
[20:28:10] [PASSED] 0xD753 (NOVALAKE_P)
[20:28:10] [PASSED] 0xD754 (NOVALAKE_P)
[20:28:10] [PASSED] 0xD755 (NOVALAKE_P)
[20:28:10] [PASSED] 0xD756 (NOVALAKE_P)
[20:28:10] [PASSED] 0xD757 (NOVALAKE_P)
[20:28:10] [PASSED] 0xD75F (NOVALAKE_P)
[20:28:10] =============== [PASSED] check_platform_desc ===============
[20:28:10] ===================== [PASSED] xe_pci ======================
[20:28:10] =================== xe_rtp (2 subtests) ====================
[20:28:10] =============== xe_rtp_process_to_sr_tests  ================
[20:28:10] [PASSED] coalesce-same-reg
[20:28:10] [PASSED] no-match-no-add
[20:28:10] [PASSED] match-or
[20:28:10] [PASSED] match-or-xfail
[20:28:10] [PASSED] no-match-no-add-multiple-rules
[20:28:10] [PASSED] two-regs-two-entries
[20:28:10] [PASSED] clr-one-set-other
[20:28:10] [PASSED] set-field
[20:28:10] [PASSED] conflict-duplicate
stty: 'standard input': Inappropriate ioctl for device
[20:28:10] [PASSED] conflict-not-disjoint
[20:28:10] [PASSED] conflict-reg-type
[20:28:10] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[20:28:10] ================== xe_rtp_process_tests  ===================
[20:28:10] [PASSED] active1
[20:28:10] [PASSED] active2
[20:28:10] [PASSED] active-inactive
[20:28:10] [PASSED] inactive-active
[20:28:10] [PASSED] inactive-1st_or_active-inactive
[20:28:10] [PASSED] inactive-2nd_or_active-inactive
[20:28:10] [PASSED] inactive-last_or_active-inactive
[20:28:10] [PASSED] inactive-no_or_active-inactive
[20:28:10] ============== [PASSED] xe_rtp_process_tests ===============
[20:28:10] ===================== [PASSED] xe_rtp ======================
[20:28:10] ==================== xe_wa (1 subtest) =====================
[20:28:10] ======================== xe_wa_gt  =========================
[20:28:10] [PASSED] TIGERLAKE B0
[20:28:10] [PASSED] DG1 A0
[20:28:10] [PASSED] DG1 B0
[20:28:10] [PASSED] ALDERLAKE_S A0
[20:28:10] [PASSED] ALDERLAKE_S B0
[20:28:10] [PASSED] ALDERLAKE_S C0
[20:28:10] [PASSED] ALDERLAKE_S D0
[20:28:10] [PASSED] ALDERLAKE_P A0
[20:28:10] [PASSED] ALDERLAKE_P B0
[20:28:10] [PASSED] ALDERLAKE_P C0
[20:28:10] [PASSED] ALDERLAKE_S RPLS D0
[20:28:10] [PASSED] ALDERLAKE_P RPLU E0
[20:28:10] [PASSED] DG2 G10 C0
[20:28:10] [PASSED] DG2 G11 B1
[20:28:10] [PASSED] DG2 G12 A1
[20:28:10] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[20:28:10] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[20:28:10] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[20:28:10] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[20:28:10] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[20:28:10] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[20:28:10] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[20:28:10] ==================== [PASSED] xe_wa_gt =====================
[20:28:10] ====================== [PASSED] xe_wa ======================
[20:28:10] ============================================================
[20:28:10] Testing complete. Ran 597 tests: passed: 579, skipped: 18
[20:28:10] Elapsed time: 42.593s total, 4.362s configuring, 37.564s building, 0.610s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[20:28:10] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[20:28:12] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[20:28:41] Starting KUnit Kernel (1/1)...
[20:28:41] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[20:28:41] ============ drm_test_pick_cmdline (2 subtests) ============
[20:28:41] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[20:28:41] =============== drm_test_pick_cmdline_named  ===============
[20:28:41] [PASSED] NTSC
[20:28:41] [PASSED] NTSC-J
[20:28:41] [PASSED] PAL
[20:28:41] [PASSED] PAL-M
[20:28:41] =========== [PASSED] drm_test_pick_cmdline_named ===========
[20:28:41] ============== [PASSED] drm_test_pick_cmdline ==============
[20:28:41] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[20:28:41] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[20:28:41] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[20:28:41] =========== drm_validate_clone_mode (2 subtests) ===========
[20:28:41] ============== drm_test_check_in_clone_mode  ===============
[20:28:41] [PASSED] in_clone_mode
[20:28:41] [PASSED] not_in_clone_mode
[20:28:41] ========== [PASSED] drm_test_check_in_clone_mode ===========
[20:28:41] =============== drm_test_check_valid_clones  ===============
[20:28:41] [PASSED] not_in_clone_mode
[20:28:41] [PASSED] valid_clone
[20:28:41] [PASSED] invalid_clone
[20:28:41] =========== [PASSED] drm_test_check_valid_clones ===========
[20:28:41] ============= [PASSED] drm_validate_clone_mode =============
[20:28:41] ============= drm_validate_modeset (1 subtest) =============
[20:28:41] [PASSED] drm_test_check_connector_changed_modeset
[20:28:41] ============== [PASSED] drm_validate_modeset ===============
[20:28:41] ====== drm_test_bridge_get_current_state (2 subtests) ======
[20:28:41] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[20:28:41] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[20:28:41] ======== [PASSED] drm_test_bridge_get_current_state ========
[20:28:41] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[20:28:41] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[20:28:41] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[20:28:41] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[20:28:41] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[20:28:41] ============== drm_bridge_alloc (2 subtests) ===============
[20:28:41] [PASSED] drm_test_drm_bridge_alloc_basic
[20:28:41] [PASSED] drm_test_drm_bridge_alloc_get_put
[20:28:41] ================ [PASSED] drm_bridge_alloc =================
[20:28:41] ============= drm_cmdline_parser (40 subtests) =============
[20:28:41] [PASSED] drm_test_cmdline_force_d_only
[20:28:41] [PASSED] drm_test_cmdline_force_D_only_dvi
[20:28:41] [PASSED] drm_test_cmdline_force_D_only_hdmi
[20:28:41] [PASSED] drm_test_cmdline_force_D_only_not_digital
[20:28:41] [PASSED] drm_test_cmdline_force_e_only
[20:28:41] [PASSED] drm_test_cmdline_res
[20:28:41] [PASSED] drm_test_cmdline_res_vesa
[20:28:41] [PASSED] drm_test_cmdline_res_vesa_rblank
[20:28:41] [PASSED] drm_test_cmdline_res_rblank
[20:28:41] [PASSED] drm_test_cmdline_res_bpp
[20:28:41] [PASSED] drm_test_cmdline_res_refresh
[20:28:41] [PASSED] drm_test_cmdline_res_bpp_refresh
[20:28:41] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[20:28:41] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[20:28:41] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[20:28:41] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[20:28:41] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[20:28:41] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[20:28:41] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[20:28:41] [PASSED] drm_test_cmdline_res_margins_force_on
[20:28:41] [PASSED] drm_test_cmdline_res_vesa_margins
[20:28:41] [PASSED] drm_test_cmdline_name
[20:28:41] [PASSED] drm_test_cmdline_name_bpp
[20:28:41] [PASSED] drm_test_cmdline_name_option
[20:28:41] [PASSED] drm_test_cmdline_name_bpp_option
[20:28:41] [PASSED] drm_test_cmdline_rotate_0
[20:28:41] [PASSED] drm_test_cmdline_rotate_90
[20:28:41] [PASSED] drm_test_cmdline_rotate_180
[20:28:41] [PASSED] drm_test_cmdline_rotate_270
[20:28:41] [PASSED] drm_test_cmdline_hmirror
[20:28:41] [PASSED] drm_test_cmdline_vmirror
[20:28:41] [PASSED] drm_test_cmdline_margin_options
[20:28:41] [PASSED] drm_test_cmdline_multiple_options
[20:28:41] [PASSED] drm_test_cmdline_bpp_extra_and_option
[20:28:41] [PASSED] drm_test_cmdline_extra_and_option
[20:28:41] [PASSED] drm_test_cmdline_freestanding_options
[20:28:41] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[20:28:41] [PASSED] drm_test_cmdline_panel_orientation
[20:28:41] ================ drm_test_cmdline_invalid  =================
[20:28:41] [PASSED] margin_only
[20:28:41] [PASSED] interlace_only
[20:28:41] [PASSED] res_missing_x
[20:28:41] [PASSED] res_missing_y
[20:28:41] [PASSED] res_bad_y
[20:28:41] [PASSED] res_missing_y_bpp
[20:28:41] [PASSED] res_bad_bpp
[20:28:41] [PASSED] res_bad_refresh
[20:28:41] [PASSED] res_bpp_refresh_force_on_off
[20:28:41] [PASSED] res_invalid_mode
[20:28:41] [PASSED] res_bpp_wrong_place_mode
[20:28:41] [PASSED] name_bpp_refresh
[20:28:41] [PASSED] name_refresh
[20:28:41] [PASSED] name_refresh_wrong_mode
[20:28:41] [PASSED] name_refresh_invalid_mode
[20:28:41] [PASSED] rotate_multiple
[20:28:41] [PASSED] rotate_invalid_val
[20:28:41] [PASSED] rotate_truncated
[20:28:41] [PASSED] invalid_option
[20:28:41] [PASSED] invalid_tv_option
[20:28:41] [PASSED] truncated_tv_option
[20:28:41] ============ [PASSED] drm_test_cmdline_invalid =============
[20:28:41] =============== drm_test_cmdline_tv_options  ===============
[20:28:41] [PASSED] NTSC
[20:28:41] [PASSED] NTSC_443
[20:28:41] [PASSED] NTSC_J
[20:28:41] [PASSED] PAL
[20:28:41] [PASSED] PAL_M
[20:28:41] [PASSED] PAL_N
[20:28:41] [PASSED] SECAM
[20:28:41] [PASSED] MONO_525
[20:28:41] [PASSED] MONO_625
[20:28:41] =========== [PASSED] drm_test_cmdline_tv_options ===========
[20:28:41] =============== [PASSED] drm_cmdline_parser ================
[20:28:41] ========== drmm_connector_hdmi_init (20 subtests) ==========
[20:28:41] [PASSED] drm_test_connector_hdmi_init_valid
[20:28:41] [PASSED] drm_test_connector_hdmi_init_bpc_8
[20:28:41] [PASSED] drm_test_connector_hdmi_init_bpc_10
[20:28:41] [PASSED] drm_test_connector_hdmi_init_bpc_12
[20:28:41] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[20:28:41] [PASSED] drm_test_connector_hdmi_init_bpc_null
[20:28:41] [PASSED] drm_test_connector_hdmi_init_formats_empty
[20:28:41] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[20:28:41] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[20:28:41] [PASSED] supported_formats=0x9 yuv420_allowed=1
[20:28:41] [PASSED] supported_formats=0x9 yuv420_allowed=0
[20:28:41] [PASSED] supported_formats=0x3 yuv420_allowed=1
[20:28:41] [PASSED] supported_formats=0x3 yuv420_allowed=0
[20:28:41] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[20:28:41] [PASSED] drm_test_connector_hdmi_init_null_ddc
[20:28:41] [PASSED] drm_test_connector_hdmi_init_null_product
[20:28:41] [PASSED] drm_test_connector_hdmi_init_null_vendor
[20:28:41] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[20:28:41] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[20:28:41] [PASSED] drm_test_connector_hdmi_init_product_valid
[20:28:41] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[20:28:41] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[20:28:41] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[20:28:41] ========= drm_test_connector_hdmi_init_type_valid  =========
[20:28:41] [PASSED] HDMI-A
[20:28:41] [PASSED] HDMI-B
[20:28:41] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[20:28:41] ======== drm_test_connector_hdmi_init_type_invalid  ========
[20:28:41] [PASSED] Unknown
[20:28:41] [PASSED] VGA
[20:28:41] [PASSED] DVI-I
[20:28:41] [PASSED] DVI-D
[20:28:41] [PASSED] DVI-A
[20:28:41] [PASSED] Composite
[20:28:41] [PASSED] SVIDEO
[20:28:41] [PASSED] LVDS
[20:28:41] [PASSED] Component
[20:28:41] [PASSED] DIN
[20:28:41] [PASSED] DP
[20:28:41] [PASSED] TV
[20:28:41] [PASSED] eDP
[20:28:41] [PASSED] Virtual
[20:28:41] [PASSED] DSI
[20:28:41] [PASSED] DPI
[20:28:41] [PASSED] Writeback
[20:28:41] [PASSED] SPI
[20:28:41] [PASSED] USB
[20:28:41] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[20:28:41] ============ [PASSED] drmm_connector_hdmi_init =============
[20:28:41] ============= drmm_connector_init (3 subtests) =============
[20:28:41] [PASSED] drm_test_drmm_connector_init
[20:28:41] [PASSED] drm_test_drmm_connector_init_null_ddc
[20:28:41] ========= drm_test_drmm_connector_init_type_valid  =========
[20:28:41] [PASSED] Unknown
[20:28:41] [PASSED] VGA
[20:28:41] [PASSED] DVI-I
[20:28:41] [PASSED] DVI-D
[20:28:41] [PASSED] DVI-A
[20:28:41] [PASSED] Composite
[20:28:41] [PASSED] SVIDEO
[20:28:41] [PASSED] LVDS
[20:28:41] [PASSED] Component
[20:28:41] [PASSED] DIN
[20:28:41] [PASSED] DP
[20:28:41] [PASSED] HDMI-A
[20:28:41] [PASSED] HDMI-B
[20:28:41] [PASSED] TV
[20:28:41] [PASSED] eDP
[20:28:41] [PASSED] Virtual
[20:28:41] [PASSED] DSI
[20:28:41] [PASSED] DPI
[20:28:41] [PASSED] Writeback
[20:28:41] [PASSED] SPI
[20:28:41] [PASSED] USB
[20:28:41] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[20:28:41] =============== [PASSED] drmm_connector_init ===============
[20:28:41] ========= drm_connector_dynamic_init (6 subtests) ==========
[20:28:41] [PASSED] drm_test_drm_connector_dynamic_init
[20:28:41] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[20:28:41] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[20:28:41] [PASSED] drm_test_drm_connector_dynamic_init_properties
[20:28:41] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[20:28:41] [PASSED] Unknown
[20:28:41] [PASSED] VGA
[20:28:41] [PASSED] DVI-I
[20:28:41] [PASSED] DVI-D
[20:28:41] [PASSED] DVI-A
[20:28:41] [PASSED] Composite
[20:28:41] [PASSED] SVIDEO
[20:28:41] [PASSED] LVDS
[20:28:41] [PASSED] Component
[20:28:41] [PASSED] DIN
[20:28:41] [PASSED] DP
[20:28:41] [PASSED] HDMI-A
[20:28:41] [PASSED] HDMI-B
[20:28:41] [PASSED] TV
[20:28:41] [PASSED] eDP
[20:28:41] [PASSED] Virtual
[20:28:41] [PASSED] DSI
[20:28:41] [PASSED] DPI
[20:28:41] [PASSED] Writeback
[20:28:41] [PASSED] SPI
[20:28:41] [PASSED] USB
[20:28:41] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[20:28:41] ======== drm_test_drm_connector_dynamic_init_name  =========
[20:28:41] [PASSED] Unknown
[20:28:41] [PASSED] VGA
[20:28:41] [PASSED] DVI-I
[20:28:41] [PASSED] DVI-D
[20:28:41] [PASSED] DVI-A
[20:28:41] [PASSED] Composite
[20:28:41] [PASSED] SVIDEO
[20:28:41] [PASSED] LVDS
[20:28:41] [PASSED] Component
[20:28:41] [PASSED] DIN
[20:28:41] [PASSED] DP
[20:28:41] [PASSED] HDMI-A
[20:28:41] [PASSED] HDMI-B
[20:28:41] [PASSED] TV
[20:28:41] [PASSED] eDP
[20:28:41] [PASSED] Virtual
[20:28:41] [PASSED] DSI
[20:28:41] [PASSED] DPI
[20:28:41] [PASSED] Writeback
[20:28:41] [PASSED] SPI
[20:28:41] [PASSED] USB
[20:28:41] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[20:28:41] =========== [PASSED] drm_connector_dynamic_init ============
[20:28:41] ==== drm_connector_dynamic_register_early (4 subtests) =====
[20:28:41] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[20:28:41] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[20:28:41] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[20:28:41] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[20:28:41] ====== [PASSED] drm_connector_dynamic_register_early =======
[20:28:41] ======= drm_connector_dynamic_register (7 subtests) ========
[20:28:41] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[20:28:41] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[20:28:41] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[20:28:41] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[20:28:41] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[20:28:41] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[20:28:41] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[20:28:41] ========= [PASSED] drm_connector_dynamic_register ==========
[20:28:41] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[20:28:41] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[20:28:41] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[20:28:41] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[20:28:41] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[20:28:41] ========== drm_test_get_tv_mode_from_name_valid  ===========
[20:28:41] [PASSED] NTSC
[20:28:41] [PASSED] NTSC-443
[20:28:41] [PASSED] NTSC-J
[20:28:41] [PASSED] PAL
[20:28:41] [PASSED] PAL-M
[20:28:41] [PASSED] PAL-N
[20:28:41] [PASSED] SECAM
[20:28:41] [PASSED] Mono
[20:28:41] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[20:28:41] [PASSED] drm_test_get_tv_mode_from_name_truncated
[20:28:41] ============ [PASSED] drm_get_tv_mode_from_name ============
[20:28:41] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[20:28:41] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[20:28:41] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[20:28:41] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[20:28:41] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[20:28:41] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[20:28:41] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[20:28:41] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[20:28:41] [PASSED] VIC 96
[20:28:41] [PASSED] VIC 97
[20:28:41] [PASSED] VIC 101
[20:28:41] [PASSED] VIC 102
[20:28:41] [PASSED] VIC 106
[20:28:41] [PASSED] VIC 107
[20:28:41] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[20:28:41] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[20:28:41] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[20:28:41] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[20:28:41] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[20:28:41] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[20:28:41] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[20:28:41] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[20:28:41] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[20:28:41] [PASSED] Automatic
[20:28:41] [PASSED] Full
[20:28:41] [PASSED] Limited 16:235
[20:28:41] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[20:28:41] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[20:28:41] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[20:28:41] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[20:28:41] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[20:28:41] [PASSED] RGB
[20:28:41] [PASSED] YUV 4:2:0
[20:28:41] [PASSED] YUV 4:2:2
[20:28:41] [PASSED] YUV 4:4:4
[20:28:41] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[20:28:41] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[20:28:41] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[20:28:41] ============= drm_damage_helper (21 subtests) ==============
[20:28:41] [PASSED] drm_test_damage_iter_no_damage
[20:28:41] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[20:28:41] [PASSED] drm_test_damage_iter_no_damage_src_moved
[20:28:41] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[20:28:41] [PASSED] drm_test_damage_iter_no_damage_not_visible
[20:28:41] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[20:28:41] [PASSED] drm_test_damage_iter_no_damage_no_fb
[20:28:41] [PASSED] drm_test_damage_iter_simple_damage
[20:28:41] [PASSED] drm_test_damage_iter_single_damage
[20:28:41] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[20:28:41] [PASSED] drm_test_damage_iter_single_damage_outside_src
[20:28:41] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[20:28:41] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[20:28:41] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[20:28:41] [PASSED] drm_test_damage_iter_single_damage_src_moved
[20:28:41] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[20:28:41] [PASSED] drm_test_damage_iter_damage
[20:28:41] [PASSED] drm_test_damage_iter_damage_one_intersect
[20:28:41] [PASSED] drm_test_damage_iter_damage_one_outside
[20:28:41] [PASSED] drm_test_damage_iter_damage_src_moved
[20:28:41] [PASSED] drm_test_damage_iter_damage_not_visible
[20:28:41] ================ [PASSED] drm_damage_helper ================
[20:28:41] ============== drm_dp_mst_helper (3 subtests) ==============
[20:28:41] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[20:28:41] [PASSED] Clock 154000 BPP 30 DSC disabled
[20:28:41] [PASSED] Clock 234000 BPP 30 DSC disabled
[20:28:41] [PASSED] Clock 297000 BPP 24 DSC disabled
[20:28:41] [PASSED] Clock 332880 BPP 24 DSC enabled
[20:28:41] [PASSED] Clock 324540 BPP 24 DSC enabled
[20:28:41] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[20:28:41] ============== drm_test_dp_mst_calc_pbn_div  ===============
[20:28:41] [PASSED] Link rate 2000000 lane count 4
[20:28:41] [PASSED] Link rate 2000000 lane count 2
[20:28:41] [PASSED] Link rate 2000000 lane count 1
[20:28:41] [PASSED] Link rate 1350000 lane count 4
[20:28:41] [PASSED] Link rate 1350000 lane count 2
[20:28:41] [PASSED] Link rate 1350000 lane count 1
[20:28:41] [PASSED] Link rate 1000000 lane count 4
[20:28:41] [PASSED] Link rate 1000000 lane count 2
[20:28:41] [PASSED] Link rate 1000000 lane count 1
[20:28:41] [PASSED] Link rate 810000 lane count 4
[20:28:41] [PASSED] Link rate 810000 lane count 2
[20:28:41] [PASSED] Link rate 810000 lane count 1
[20:28:41] [PASSED] Link rate 540000 lane count 4
[20:28:41] [PASSED] Link rate 540000 lane count 2
[20:28:41] [PASSED] Link rate 540000 lane count 1
[20:28:41] [PASSED] Link rate 270000 lane count 4
[20:28:41] [PASSED] Link rate 270000 lane count 2
[20:28:41] [PASSED] Link rate 270000 lane count 1
[20:28:41] [PASSED] Link rate 162000 lane count 4
[20:28:41] [PASSED] Link rate 162000 lane count 2
[20:28:41] [PASSED] Link rate 162000 lane count 1
[20:28:41] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[20:28:41] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[20:28:41] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[20:28:41] [PASSED] DP_POWER_UP_PHY with port number
[20:28:41] [PASSED] DP_POWER_DOWN_PHY with port number
[20:28:41] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[20:28:41] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[20:28:41] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[20:28:41] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[20:28:41] [PASSED] DP_QUERY_PAYLOAD with port number
[20:28:41] [PASSED] DP_QUERY_PAYLOAD with VCPI
[20:28:41] [PASSED] DP_REMOTE_DPCD_READ with port number
[20:28:41] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[20:28:41] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[20:28:41] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[20:28:41] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[20:28:41] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[20:28:41] [PASSED] DP_REMOTE_I2C_READ with port number
[20:28:41] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[20:28:41] [PASSED] DP_REMOTE_I2C_READ with transactions array
[20:28:41] [PASSED] DP_REMOTE_I2C_WRITE with port number
[20:28:41] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[20:28:41] [PASSED] DP_REMOTE_I2C_WRITE with data array
[20:28:41] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[20:28:41] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[20:28:41] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[20:28:41] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[20:28:41] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[20:28:41] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[20:28:41] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[20:28:41] ================ [PASSED] drm_dp_mst_helper ================
[20:28:41] ================== drm_exec (7 subtests) ===================
[20:28:41] [PASSED] sanitycheck
[20:28:41] [PASSED] test_lock
[20:28:41] [PASSED] test_lock_unlock
[20:28:41] [PASSED] test_duplicates
[20:28:41] [PASSED] test_prepare
[20:28:41] [PASSED] test_prepare_array
[20:28:41] [PASSED] test_multiple_loops
[20:28:41] ==================== [PASSED] drm_exec =====================
[20:28:41] =========== drm_format_helper_test (17 subtests) ===========
[20:28:41] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[20:28:41] [PASSED] single_pixel_source_buffer
[20:28:41] [PASSED] single_pixel_clip_rectangle
[20:28:41] [PASSED] well_known_colors
[20:28:41] [PASSED] destination_pitch
[20:28:41] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[20:28:41] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[20:28:41] [PASSED] single_pixel_source_buffer
[20:28:41] [PASSED] single_pixel_clip_rectangle
[20:28:41] [PASSED] well_known_colors
[20:28:41] [PASSED] destination_pitch
[20:28:41] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[20:28:41] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[20:28:41] [PASSED] single_pixel_source_buffer
[20:28:41] [PASSED] single_pixel_clip_rectangle
[20:28:41] [PASSED] well_known_colors
[20:28:41] [PASSED] destination_pitch
[20:28:41] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[20:28:41] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[20:28:41] [PASSED] single_pixel_source_buffer
[20:28:41] [PASSED] single_pixel_clip_rectangle
[20:28:41] [PASSED] well_known_colors
[20:28:41] [PASSED] destination_pitch
[20:28:41] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[20:28:41] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[20:28:41] [PASSED] single_pixel_source_buffer
[20:28:41] [PASSED] single_pixel_clip_rectangle
[20:28:41] [PASSED] well_known_colors
[20:28:41] [PASSED] destination_pitch
[20:28:41] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[20:28:41] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[20:28:41] [PASSED] single_pixel_source_buffer
[20:28:41] [PASSED] single_pixel_clip_rectangle
[20:28:41] [PASSED] well_known_colors
[20:28:41] [PASSED] destination_pitch
[20:28:41] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[20:28:41] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[20:28:41] [PASSED] single_pixel_source_buffer
[20:28:41] [PASSED] single_pixel_clip_rectangle
[20:28:41] [PASSED] well_known_colors
[20:28:41] [PASSED] destination_pitch
[20:28:41] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[20:28:41] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[20:28:41] [PASSED] single_pixel_source_buffer
[20:28:41] [PASSED] single_pixel_clip_rectangle
[20:28:41] [PASSED] well_known_colors
[20:28:41] [PASSED] destination_pitch
[20:28:41] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[20:28:41] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[20:28:41] [PASSED] single_pixel_source_buffer
[20:28:41] [PASSED] single_pixel_clip_rectangle
[20:28:41] [PASSED] well_known_colors
[20:28:41] [PASSED] destination_pitch
[20:28:41] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[20:28:41] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[20:28:41] [PASSED] single_pixel_source_buffer
[20:28:41] [PASSED] single_pixel_clip_rectangle
[20:28:41] [PASSED] well_known_colors
[20:28:41] [PASSED] destination_pitch
[20:28:41] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[20:28:41] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[20:28:41] [PASSED] single_pixel_source_buffer
[20:28:41] [PASSED] single_pixel_clip_rectangle
[20:28:41] [PASSED] well_known_colors
[20:28:41] [PASSED] destination_pitch
[20:28:41] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[20:28:41] ============== drm_test_fb_xrgb8888_to_mono  ===============
[20:28:41] [PASSED] single_pixel_source_buffer
[20:28:41] [PASSED] single_pixel_clip_rectangle
[20:28:41] [PASSED] well_known_colors
[20:28:41] [PASSED] destination_pitch
[20:28:41] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[20:28:41] ==================== drm_test_fb_swab  =====================
[20:28:41] [PASSED] single_pixel_source_buffer
[20:28:41] [PASSED] single_pixel_clip_rectangle
[20:28:41] [PASSED] well_known_colors
[20:28:41] [PASSED] destination_pitch
[20:28:41] ================ [PASSED] drm_test_fb_swab =================
[20:28:41] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[20:28:41] [PASSED] single_pixel_source_buffer
[20:28:41] [PASSED] single_pixel_clip_rectangle
[20:28:41] [PASSED] well_known_colors
[20:28:41] [PASSED] destination_pitch
[20:28:41] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[20:28:41] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[20:28:41] [PASSED] single_pixel_source_buffer
[20:28:41] [PASSED] single_pixel_clip_rectangle
[20:28:41] [PASSED] well_known_colors
[20:28:41] [PASSED] destination_pitch
[20:28:41] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[20:28:41] ================= drm_test_fb_clip_offset  =================
[20:28:41] [PASSED] pass through
[20:28:41] [PASSED] horizontal offset
[20:28:41] [PASSED] vertical offset
[20:28:41] [PASSED] horizontal and vertical offset
[20:28:41] [PASSED] horizontal offset (custom pitch)
[20:28:41] [PASSED] vertical offset (custom pitch)
[20:28:41] [PASSED] horizontal and vertical offset (custom pitch)
[20:28:41] ============= [PASSED] drm_test_fb_clip_offset =============
[20:28:41] =================== drm_test_fb_memcpy  ====================
[20:28:41] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[20:28:41] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[20:28:41] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[20:28:41] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[20:28:41] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[20:28:41] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[20:28:41] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[20:28:41] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[20:28:41] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[20:28:41] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[20:28:41] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[20:28:41] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[20:28:41] =============== [PASSED] drm_test_fb_memcpy ================
[20:28:41] ============= [PASSED] drm_format_helper_test ==============
[20:28:41] ================= drm_format (18 subtests) =================
[20:28:41] [PASSED] drm_test_format_block_width_invalid
[20:28:41] [PASSED] drm_test_format_block_width_one_plane
[20:28:41] [PASSED] drm_test_format_block_width_two_plane
[20:28:41] [PASSED] drm_test_format_block_width_three_plane
[20:28:41] [PASSED] drm_test_format_block_width_tiled
[20:28:41] [PASSED] drm_test_format_block_height_invalid
[20:28:41] [PASSED] drm_test_format_block_height_one_plane
[20:28:41] [PASSED] drm_test_format_block_height_two_plane
[20:28:41] [PASSED] drm_test_format_block_height_three_plane
[20:28:41] [PASSED] drm_test_format_block_height_tiled
[20:28:41] [PASSED] drm_test_format_min_pitch_invalid
[20:28:41] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[20:28:41] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[20:28:41] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[20:28:41] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[20:28:41] [PASSED] drm_test_format_min_pitch_two_plane
[20:28:41] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[20:28:41] [PASSED] drm_test_format_min_pitch_tiled
[20:28:41] =================== [PASSED] drm_format ====================
[20:28:41] ============== drm_framebuffer (10 subtests) ===============
[20:28:41] ========== drm_test_framebuffer_check_src_coords  ==========
[20:28:41] [PASSED] Success: source fits into fb
[20:28:41] [PASSED] Fail: overflowing fb with x-axis coordinate
[20:28:41] [PASSED] Fail: overflowing fb with y-axis coordinate
[20:28:41] [PASSED] Fail: overflowing fb with source width
[20:28:41] [PASSED] Fail: overflowing fb with source height
[20:28:41] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[20:28:41] [PASSED] drm_test_framebuffer_cleanup
[20:28:41] =============== drm_test_framebuffer_create  ===============
[20:28:41] [PASSED] ABGR8888 normal sizes
[20:28:41] [PASSED] ABGR8888 max sizes
[20:28:41] [PASSED] ABGR8888 pitch greater than min required
[20:28:41] [PASSED] ABGR8888 pitch less than min required
[20:28:41] [PASSED] ABGR8888 Invalid width
[20:28:41] [PASSED] ABGR8888 Invalid buffer handle
[20:28:41] [PASSED] No pixel format
[20:28:41] [PASSED] ABGR8888 Width 0
[20:28:41] [PASSED] ABGR8888 Height 0
[20:28:41] [PASSED] ABGR8888 Out of bound height * pitch combination
[20:28:41] [PASSED] ABGR8888 Large buffer offset
[20:28:41] [PASSED] ABGR8888 Buffer offset for inexistent plane
[20:28:41] [PASSED] ABGR8888 Invalid flag
[20:28:41] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[20:28:41] [PASSED] ABGR8888 Valid buffer modifier
[20:28:41] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[20:28:41] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[20:28:41] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[20:28:41] [PASSED] NV12 Normal sizes
[20:28:41] [PASSED] NV12 Max sizes
[20:28:41] [PASSED] NV12 Invalid pitch
[20:28:41] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[20:28:41] [PASSED] NV12 different  modifier per-plane
[20:28:41] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[20:28:41] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[20:28:41] [PASSED] NV12 Modifier for inexistent plane
[20:28:41] [PASSED] NV12 Handle for inexistent plane
[20:28:41] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[20:28:41] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[20:28:41] [PASSED] YVU420 Normal sizes
[20:28:41] [PASSED] YVU420 Max sizes
[20:28:41] [PASSED] YVU420 Invalid pitch
[20:28:41] [PASSED] YVU420 Different pitches
[20:28:41] [PASSED] YVU420 Different buffer offsets/pitches
[20:28:41] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[20:28:41] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[20:28:41] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[20:28:41] [PASSED] YVU420 Valid modifier
[20:28:41] [PASSED] YVU420 Different modifiers per plane
[20:28:41] [PASSED] YVU420 Modifier for inexistent plane
[20:28:41] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[20:28:41] [PASSED] X0L2 Normal sizes
[20:28:41] [PASSED] X0L2 Max sizes
[20:28:41] [PASSED] X0L2 Invalid pitch
[20:28:41] [PASSED] X0L2 Pitch greater than minimum required
[20:28:41] [PASSED] X0L2 Handle for inexistent plane
[20:28:41] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[20:28:41] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[20:28:41] [PASSED] X0L2 Valid modifier
[20:28:41] [PASSED] X0L2 Modifier for inexistent plane
[20:28:41] =========== [PASSED] drm_test_framebuffer_create ===========
[20:28:41] [PASSED] drm_test_framebuffer_free
[20:28:41] [PASSED] drm_test_framebuffer_init
[20:28:41] [PASSED] drm_test_framebuffer_init_bad_format
[20:28:41] [PASSED] drm_test_framebuffer_init_dev_mismatch
[20:28:41] [PASSED] drm_test_framebuffer_lookup
[20:28:41] [PASSED] drm_test_framebuffer_lookup_inexistent
[20:28:41] [PASSED] drm_test_framebuffer_modifiers_not_supported
[20:28:41] ================= [PASSED] drm_framebuffer =================
[20:28:41] ================ drm_gem_shmem (8 subtests) ================
[20:28:41] [PASSED] drm_gem_shmem_test_obj_create
[20:28:41] [PASSED] drm_gem_shmem_test_obj_create_private
[20:28:41] [PASSED] drm_gem_shmem_test_pin_pages
[20:28:41] [PASSED] drm_gem_shmem_test_vmap
[20:28:41] [PASSED] drm_gem_shmem_test_get_sg_table
[20:28:41] [PASSED] drm_gem_shmem_test_get_pages_sgt
[20:28:41] [PASSED] drm_gem_shmem_test_madvise
[20:28:41] [PASSED] drm_gem_shmem_test_purge
[20:28:41] ================== [PASSED] drm_gem_shmem ==================
[20:28:41] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[20:28:41] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[20:28:41] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[20:28:41] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[20:28:41] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[20:28:41] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[20:28:41] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[20:28:41] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[20:28:41] [PASSED] Automatic
[20:28:41] [PASSED] Full
[20:28:41] [PASSED] Limited 16:235
[20:28:41] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[20:28:41] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[20:28:41] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[20:28:41] [PASSED] drm_test_check_disable_connector
[20:28:41] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[20:28:41] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[20:28:41] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[20:28:41] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[20:28:41] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[20:28:41] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[20:28:41] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[20:28:41] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[20:28:41] [PASSED] drm_test_check_output_bpc_dvi
[20:28:41] [PASSED] drm_test_check_output_bpc_format_vic_1
[20:28:41] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[20:28:41] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[20:28:41] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[20:28:41] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[20:28:41] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[20:28:41] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[20:28:41] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[20:28:41] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[20:28:41] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[20:28:41] [PASSED] drm_test_check_broadcast_rgb_value
[20:28:41] [PASSED] drm_test_check_bpc_8_value
[20:28:41] [PASSED] drm_test_check_bpc_10_value
[20:28:41] [PASSED] drm_test_check_bpc_12_value
[20:28:41] [PASSED] drm_test_check_format_value
[20:28:41] [PASSED] drm_test_check_tmds_char_value
[20:28:41] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[20:28:41] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[20:28:41] [PASSED] drm_test_check_mode_valid
[20:28:41] [PASSED] drm_test_check_mode_valid_reject
[20:28:41] [PASSED] drm_test_check_mode_valid_reject_rate
[20:28:41] [PASSED] drm_test_check_mode_valid_reject_max_clock
[20:28:41] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[20:28:41] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[20:28:41] [PASSED] drm_test_check_infoframes
[20:28:41] [PASSED] drm_test_check_reject_avi_infoframe
[20:28:41] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[20:28:41] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[20:28:41] [PASSED] drm_test_check_reject_audio_infoframe
[20:28:41] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[20:28:41] ================= drm_managed (2 subtests) =================
[20:28:41] [PASSED] drm_test_managed_release_action
[20:28:41] [PASSED] drm_test_managed_run_action
[20:28:41] =================== [PASSED] drm_managed ===================
[20:28:41] =================== drm_mm (6 subtests) ====================
[20:28:41] [PASSED] drm_test_mm_init
[20:28:41] [PASSED] drm_test_mm_debug
[20:28:41] [PASSED] drm_test_mm_align32
[20:28:41] [PASSED] drm_test_mm_align64
[20:28:41] [PASSED] drm_test_mm_lowest
[20:28:41] [PASSED] drm_test_mm_highest
[20:28:41] ===================== [PASSED] drm_mm ======================
[20:28:41] ============= drm_modes_analog_tv (5 subtests) =============
[20:28:41] [PASSED] drm_test_modes_analog_tv_mono_576i
[20:28:41] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[20:28:41] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[20:28:41] [PASSED] drm_test_modes_analog_tv_pal_576i
[20:28:41] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[20:28:41] =============== [PASSED] drm_modes_analog_tv ===============
[20:28:41] ============== drm_plane_helper (2 subtests) ===============
[20:28:41] =============== drm_test_check_plane_state  ================
[20:28:41] [PASSED] clipping_simple
[20:28:41] [PASSED] clipping_rotate_reflect
[20:28:41] [PASSED] positioning_simple
[20:28:41] [PASSED] upscaling
[20:28:41] [PASSED] downscaling
[20:28:41] [PASSED] rounding1
[20:28:41] [PASSED] rounding2
[20:28:41] [PASSED] rounding3
[20:28:41] [PASSED] rounding4
[20:28:41] =========== [PASSED] drm_test_check_plane_state ============
[20:28:41] =========== drm_test_check_invalid_plane_state  ============
[20:28:41] [PASSED] positioning_invalid
[20:28:41] [PASSED] upscaling_invalid
[20:28:41] [PASSED] downscaling_invalid
[20:28:41] ======= [PASSED] drm_test_check_invalid_plane_state ========
[20:28:41] ================ [PASSED] drm_plane_helper =================
[20:28:41] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[20:28:41] ====== drm_test_connector_helper_tv_get_modes_check  =======
[20:28:41] [PASSED] None
[20:28:41] [PASSED] PAL
[20:28:41] [PASSED] NTSC
[20:28:41] [PASSED] Both, NTSC Default
[20:28:41] [PASSED] Both, PAL Default
[20:28:41] [PASSED] Both, NTSC Default, with PAL on command-line
[20:28:41] [PASSED] Both, PAL Default, with NTSC on command-line
[20:28:41] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[20:28:41] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[20:28:41] ================== drm_rect (9 subtests) ===================
[20:28:41] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[20:28:41] [PASSED] drm_test_rect_clip_scaled_not_clipped
[20:28:41] [PASSED] drm_test_rect_clip_scaled_clipped
[20:28:41] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[20:28:41] ================= drm_test_rect_intersect  =================
[20:28:41] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[20:28:41] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[20:28:41] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[20:28:41] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[20:28:41] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[20:28:41] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[20:28:41] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[20:28:41] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[20:28:41] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[20:28:41] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[20:28:41] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[20:28:41] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[20:28:41] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[20:28:41] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[20:28:41] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[20:28:41] ============= [PASSED] drm_test_rect_intersect =============
[20:28:41] ================ drm_test_rect_calc_hscale  ================
[20:28:41] [PASSED] normal use
[20:28:41] [PASSED] out of max range
[20:28:41] [PASSED] out of min range
[20:28:41] [PASSED] zero dst
[20:28:41] [PASSED] negative src
[20:28:41] [PASSED] negative dst
[20:28:41] ============ [PASSED] drm_test_rect_calc_hscale ============
[20:28:41] ================ drm_test_rect_calc_vscale  ================
[20:28:41] [PASSED] normal use
[20:28:41] [PASSED] out of max range
[20:28:41] [PASSED] out of min range
[20:28:41] [PASSED] zero dst
[20:28:41] [PASSED] negative src
[20:28:41] [PASSED] negative dst
stty: 'standard input': Inappropriate ioctl for device
[20:28:41] ============ [PASSED] drm_test_rect_calc_vscale ============
[20:28:41] ================== drm_test_rect_rotate  ===================
[20:28:41] [PASSED] reflect-x
[20:28:41] [PASSED] reflect-y
[20:28:41] [PASSED] rotate-0
[20:28:41] [PASSED] rotate-90
[20:28:41] [PASSED] rotate-180
[20:28:41] [PASSED] rotate-270
[20:28:41] ============== [PASSED] drm_test_rect_rotate ===============
[20:28:41] ================ drm_test_rect_rotate_inv  =================
[20:28:41] [PASSED] reflect-x
[20:28:41] [PASSED] reflect-y
[20:28:41] [PASSED] rotate-0
[20:28:41] [PASSED] rotate-90
[20:28:41] [PASSED] rotate-180
[20:28:41] [PASSED] rotate-270
[20:28:41] ============ [PASSED] drm_test_rect_rotate_inv =============
[20:28:41] ==================== [PASSED] drm_rect =====================
[20:28:41] ============ drm_sysfb_modeset_test (1 subtest) ============
[20:28:41] ============ drm_test_sysfb_build_fourcc_list  =============
[20:28:41] [PASSED] no native formats
[20:28:41] [PASSED] XRGB8888 as native format
[20:28:41] [PASSED] remove duplicates
[20:28:41] [PASSED] convert alpha formats
[20:28:41] [PASSED] random formats
[20:28:41] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[20:28:41] ============= [PASSED] drm_sysfb_modeset_test ==============
[20:28:41] ================== drm_fixp (2 subtests) ===================
[20:28:41] [PASSED] drm_test_int2fixp
[20:28:41] [PASSED] drm_test_sm2fixp
[20:28:41] ==================== [PASSED] drm_fixp =====================
[20:28:41] ============================================================
[20:28:41] Testing complete. Ran 621 tests: passed: 621
[20:28:41] Elapsed time: 30.904s total, 1.648s configuring, 29.039s building, 0.174s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[20:28:41] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[20:28:43] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[20:28:52] Starting KUnit Kernel (1/1)...
[20:28:52] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[20:28:52] ================= ttm_device (5 subtests) ==================
[20:28:52] [PASSED] ttm_device_init_basic
[20:28:52] [PASSED] ttm_device_init_multiple
[20:28:52] [PASSED] ttm_device_fini_basic
[20:28:52] [PASSED] ttm_device_init_no_vma_man
[20:28:52] ================== ttm_device_init_pools  ==================
[20:28:52] [PASSED] No DMA allocations, no DMA32 required
[20:28:52] [PASSED] DMA allocations, DMA32 required
[20:28:52] [PASSED] No DMA allocations, DMA32 required
[20:28:52] [PASSED] DMA allocations, no DMA32 required
[20:28:52] ============== [PASSED] ttm_device_init_pools ==============
[20:28:52] =================== [PASSED] ttm_device ====================
[20:28:52] ================== ttm_pool (8 subtests) ===================
[20:28:52] ================== ttm_pool_alloc_basic  ===================
[20:28:52] [PASSED] One page
[20:28:52] [PASSED] More than one page
[20:28:52] [PASSED] Above the allocation limit
[20:28:52] [PASSED] One page, with coherent DMA mappings enabled
[20:28:52] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[20:28:52] ============== [PASSED] ttm_pool_alloc_basic ===============
[20:28:52] ============== ttm_pool_alloc_basic_dma_addr  ==============
[20:28:52] [PASSED] One page
[20:28:52] [PASSED] More than one page
[20:28:52] [PASSED] Above the allocation limit
[20:28:52] [PASSED] One page, with coherent DMA mappings enabled
[20:28:52] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[20:28:52] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[20:28:52] [PASSED] ttm_pool_alloc_order_caching_match
[20:28:52] [PASSED] ttm_pool_alloc_caching_mismatch
[20:28:52] [PASSED] ttm_pool_alloc_order_mismatch
[20:28:52] [PASSED] ttm_pool_free_dma_alloc
[20:28:52] [PASSED] ttm_pool_free_no_dma_alloc
[20:28:52] [PASSED] ttm_pool_fini_basic
[20:28:52] ==================== [PASSED] ttm_pool =====================
[20:28:52] ================ ttm_resource (8 subtests) =================
[20:28:52] ================= ttm_resource_init_basic  =================
[20:28:52] [PASSED] Init resource in TTM_PL_SYSTEM
[20:28:52] [PASSED] Init resource in TTM_PL_VRAM
[20:28:52] [PASSED] Init resource in a private placement
[20:28:52] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[20:28:52] ============= [PASSED] ttm_resource_init_basic =============
[20:28:52] [PASSED] ttm_resource_init_pinned
[20:28:52] [PASSED] ttm_resource_fini_basic
[20:28:52] [PASSED] ttm_resource_manager_init_basic
[20:28:52] [PASSED] ttm_resource_manager_usage_basic
[20:28:52] [PASSED] ttm_resource_manager_set_used_basic
[20:28:52] [PASSED] ttm_sys_man_alloc_basic
[20:28:52] [PASSED] ttm_sys_man_free_basic
[20:28:52] ================== [PASSED] ttm_resource ===================
[20:28:52] =================== ttm_tt (15 subtests) ===================
[20:28:52] ==================== ttm_tt_init_basic  ====================
[20:28:52] [PASSED] Page-aligned size
[20:28:52] [PASSED] Extra pages requested
[20:28:52] ================ [PASSED] ttm_tt_init_basic ================
[20:28:52] [PASSED] ttm_tt_init_misaligned
[20:28:52] [PASSED] ttm_tt_fini_basic
[20:28:52] [PASSED] ttm_tt_fini_sg
[20:28:52] [PASSED] ttm_tt_fini_shmem
[20:28:52] [PASSED] ttm_tt_create_basic
[20:28:52] [PASSED] ttm_tt_create_invalid_bo_type
[20:28:52] [PASSED] ttm_tt_create_ttm_exists
[20:28:52] [PASSED] ttm_tt_create_failed
[20:28:52] [PASSED] ttm_tt_destroy_basic
[20:28:52] [PASSED] ttm_tt_populate_null_ttm
[20:28:52] [PASSED] ttm_tt_populate_populated_ttm
[20:28:52] [PASSED] ttm_tt_unpopulate_basic
[20:28:52] [PASSED] ttm_tt_unpopulate_empty_ttm
[20:28:52] [PASSED] ttm_tt_swapin_basic
[20:28:52] ===================== [PASSED] ttm_tt ======================
[20:28:52] =================== ttm_bo (14 subtests) ===================
[20:28:52] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[20:28:52] [PASSED] Cannot be interrupted and sleeps
[20:28:52] [PASSED] Cannot be interrupted, locks straight away
[20:28:52] [PASSED] Can be interrupted, sleeps
[20:28:52] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[20:28:52] [PASSED] ttm_bo_reserve_locked_no_sleep
[20:28:52] [PASSED] ttm_bo_reserve_no_wait_ticket
[20:28:52] [PASSED] ttm_bo_reserve_double_resv
[20:28:52] [PASSED] ttm_bo_reserve_interrupted
[20:28:52] [PASSED] ttm_bo_reserve_deadlock
[20:28:52] [PASSED] ttm_bo_unreserve_basic
[20:28:52] [PASSED] ttm_bo_unreserve_pinned
[20:28:52] [PASSED] ttm_bo_unreserve_bulk
[20:28:52] [PASSED] ttm_bo_fini_basic
[20:28:52] [PASSED] ttm_bo_fini_shared_resv
[20:28:52] [PASSED] ttm_bo_pin_basic
[20:28:52] [PASSED] ttm_bo_pin_unpin_resource
[20:28:52] [PASSED] ttm_bo_multiple_pin_one_unpin
[20:28:52] ===================== [PASSED] ttm_bo ======================
[20:28:52] ============== ttm_bo_validate (21 subtests) ===============
[20:28:52] ============== ttm_bo_init_reserved_sys_man  ===============
[20:28:52] [PASSED] Buffer object for userspace
[20:28:52] [PASSED] Kernel buffer object
[20:28:52] [PASSED] Shared buffer object
[20:28:52] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[20:28:52] ============== ttm_bo_init_reserved_mock_man  ==============
[20:28:52] [PASSED] Buffer object for userspace
[20:28:52] [PASSED] Kernel buffer object
[20:28:52] [PASSED] Shared buffer object
[20:28:52] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[20:28:52] [PASSED] ttm_bo_init_reserved_resv
[20:28:52] ================== ttm_bo_validate_basic  ==================
[20:28:52] [PASSED] Buffer object for userspace
[20:28:52] [PASSED] Kernel buffer object
[20:28:52] [PASSED] Shared buffer object
[20:28:52] ============== [PASSED] ttm_bo_validate_basic ==============
[20:28:52] [PASSED] ttm_bo_validate_invalid_placement
[20:28:52] ============= ttm_bo_validate_same_placement  ==============
[20:28:52] [PASSED] System manager
[20:28:52] [PASSED] VRAM manager
[20:28:52] ========= [PASSED] ttm_bo_validate_same_placement ==========
[20:28:52] [PASSED] ttm_bo_validate_failed_alloc
[20:28:52] [PASSED] ttm_bo_validate_pinned
[20:28:52] [PASSED] ttm_bo_validate_busy_placement
[20:28:52] ================ ttm_bo_validate_multihop  =================
[20:28:52] [PASSED] Buffer object for userspace
[20:28:52] [PASSED] Kernel buffer object
[20:28:52] [PASSED] Shared buffer object
[20:28:52] ============ [PASSED] ttm_bo_validate_multihop =============
[20:28:52] ========== ttm_bo_validate_no_placement_signaled  ==========
[20:28:52] [PASSED] Buffer object in system domain, no page vector
[20:28:52] [PASSED] Buffer object in system domain with an existing page vector
[20:28:52] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[20:28:52] ======== ttm_bo_validate_no_placement_not_signaled  ========
[20:28:52] [PASSED] Buffer object for userspace
[20:28:52] [PASSED] Kernel buffer object
[20:28:52] [PASSED] Shared buffer object
[20:28:52] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[20:28:52] [PASSED] ttm_bo_validate_move_fence_signaled
[20:28:52] ========= ttm_bo_validate_move_fence_not_signaled  =========
[20:28:52] [PASSED] Waits for GPU
[20:28:52] [PASSED] Tries to lock straight away
[20:28:52] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[20:28:52] [PASSED] ttm_bo_validate_happy_evict
[20:28:52] [PASSED] ttm_bo_validate_all_pinned_evict
[20:28:52] [PASSED] ttm_bo_validate_allowed_only_evict
[20:28:52] [PASSED] ttm_bo_validate_deleted_evict
[20:28:52] [PASSED] ttm_bo_validate_busy_domain_evict
[20:28:52] [PASSED] ttm_bo_validate_evict_gutting
[20:28:52] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[20:28:52] ================= [PASSED] ttm_bo_validate =================
[20:28:52] ============================================================
[20:28:52] Testing complete. Ran 101 tests: passed: 101
[20:28:52] Elapsed time: 11.116s total, 1.643s configuring, 9.206s building, 0.214s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for Refactor LT PHY PLL handling to use DPLL framework (rev3)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 1102 bytes --]

== Series Details ==

Series: Refactor LT PHY PLL handling to use DPLL framework (rev3)
URL   : https://patchwork.freedesktop.org/series/161586/
State : success

== Summary ==

CI Bug Log - changes from xe-4674-a48305e6a2e6a1ed90df374101dd29542c105d8f_BAT -> xe-pw-161586v3_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (15 -> 14)
------------------------------

  Missing    (1): bat-pvc-2 


Changes
-------

  No changes found


Build changes
-------------

  * IGT: IGT_8782 -> IGT_8783
  * Linux: xe-4674-a48305e6a2e6a1ed90df374101dd29542c105d8f -> xe-pw-161586v3

  IGT_8782: eac3b04d1f76b82ac3a183fb293c44e9185d8dba @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  IGT_8783: b5051dc2e867005c758c707312aa9cf9d1dc3291 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-4674-a48305e6a2e6a1ed90df374101dd29542c105d8f: a48305e6a2e6a1ed90df374101dd29542c105d8f
  xe-pw-161586v3: 161586v3

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/index.html

[-- Attachment #2: Type: text/html, Size: 1664 bytes --]

✗ Xe.CI.FULL: failure for Refactor LT PHY PLL handling to use DPLL framework (rev3)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 38455 bytes --]

== Series Details ==

Series: Refactor LT PHY PLL handling to use DPLL framework (rev3)
URL   : https://patchwork.freedesktop.org/series/161586/
State : failure

== Summary ==

CI Bug Log - changes from xe-4674-a48305e6a2e6a1ed90df374101dd29542c105d8f_FULL -> xe-pw-161586v3_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-161586v3_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-161586v3_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-161586v3_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@xe_survivability@i2c-functionality:
    - shard-bmg:          [PASS][1] -> [ABORT][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4674-a48305e6a2e6a1ed90df374101dd29542c105d8f/shard-bmg-8/igt@xe_survivability@i2c-functionality.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-bmg-2/igt@xe_survivability@i2c-functionality.html

  
Known issues
------------

  Here are the changes found in xe-pw-161586v3_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_addfb_basic@invalid-smem-bo-on-discrete:
    - shard-lnl:          NOTRUN -> [SKIP][3] ([Intel XE#3157])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-lnl-7/igt@kms_addfb_basic@invalid-smem-bo-on-discrete.html

  * igt@kms_big_fb@4-tiled-32bpp-rotate-90:
    - shard-bmg:          NOTRUN -> [SKIP][4] ([Intel XE#2327]) +3 other tests skip
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-bmg-2/igt@kms_big_fb@4-tiled-32bpp-rotate-90.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
    - shard-lnl:          NOTRUN -> [SKIP][5] ([Intel XE#3658] / [Intel XE#7360])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-lnl-7/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html

  * igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-bmg:          NOTRUN -> [SKIP][6] ([Intel XE#7059] / [Intel XE#7085])
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-bmg-9/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-180-hflip.html
    - shard-lnl:          NOTRUN -> [SKIP][7] ([Intel XE#7059] / [Intel XE#7085])
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-lnl-7/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
    - shard-bmg:          NOTRUN -> [SKIP][8] ([Intel XE#1124]) +8 other tests skip
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-bmg-8/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
    - shard-lnl:          NOTRUN -> [SKIP][9] ([Intel XE#1124]) +1 other test skip
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-lnl-6/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html

  * igt@kms_bw@connected-linear-tiling-2-displays-2560x1440p:
    - shard-lnl:          NOTRUN -> [SKIP][10] ([Intel XE#2191] / [Intel XE#7373])
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-lnl-6/igt@kms_bw@connected-linear-tiling-2-displays-2560x1440p.html

  * igt@kms_bw@linear-tiling-2-displays-2560x1440p:
    - shard-bmg:          NOTRUN -> [SKIP][11] ([Intel XE#367] / [Intel XE#7354]) +1 other test skip
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-bmg-8/igt@kms_bw@linear-tiling-2-displays-2560x1440p.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs:
    - shard-lnl:          NOTRUN -> [SKIP][12] ([Intel XE#2887]) +2 other tests skip
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-lnl-8/igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs@pipe-d-hdmi-a-3:
    - shard-bmg:          NOTRUN -> [SKIP][13] ([Intel XE#2652]) +17 other tests skip
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-bmg-2/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs@pipe-d-hdmi-a-3.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][14] ([Intel XE#3432]) +1 other test skip
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-bmg-9/igt@kms_ccs@crc-primary-suspend-y-tiled-ccs.html

  * igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][15] ([Intel XE#2887]) +8 other tests skip
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-bmg-7/igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs.html

  * igt@kms_chamelium_color@degamma:
    - shard-lnl:          NOTRUN -> [SKIP][16] ([Intel XE#306] / [Intel XE#7358])
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-lnl-3/igt@kms_chamelium_color@degamma.html
    - shard-bmg:          NOTRUN -> [SKIP][17] ([Intel XE#2325] / [Intel XE#7358]) +1 other test skip
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-bmg-1/igt@kms_chamelium_color@degamma.html

  * igt@kms_chamelium_frames@hdmi-aspect-ratio:
    - shard-bmg:          NOTRUN -> [SKIP][18] ([Intel XE#2252]) +4 other tests skip
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-bmg-4/igt@kms_chamelium_frames@hdmi-aspect-ratio.html

  * igt@kms_chamelium_frames@hdmi-cmp-planar-formats:
    - shard-lnl:          NOTRUN -> [SKIP][19] ([Intel XE#373])
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-lnl-4/igt@kms_chamelium_frames@hdmi-cmp-planar-formats.html

  * igt@kms_color_pipeline@plane-lut1d-pre-ctm3x4@pipe-b-plane-0:
    - shard-lnl:          NOTRUN -> [FAIL][20] ([Intel XE#7305]) +9 other tests fail
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-lnl-8/igt@kms_color_pipeline@plane-lut1d-pre-ctm3x4@pipe-b-plane-0.html

  * igt@kms_cursor_crc@cursor-offscreen-128x42:
    - shard-bmg:          NOTRUN -> [SKIP][21] ([Intel XE#2320]) +3 other tests skip
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-bmg-6/igt@kms_cursor_crc@cursor-offscreen-128x42.html

  * igt@kms_cursor_crc@cursor-offscreen-512x512:
    - shard-bmg:          NOTRUN -> [SKIP][22] ([Intel XE#2321] / [Intel XE#7355])
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-bmg-6/igt@kms_cursor_crc@cursor-offscreen-512x512.html

  * igt@kms_cursor_crc@cursor-rapid-movement-32x10:
    - shard-lnl:          NOTRUN -> [SKIP][23] ([Intel XE#1424]) +1 other test skip
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-lnl-6/igt@kms_cursor_crc@cursor-rapid-movement-32x10.html

  * igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size:
    - shard-bmg:          [PASS][24] -> [ABORT][25] ([Intel XE#5545] / [Intel XE#6652])
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4674-a48305e6a2e6a1ed90df374101dd29542c105d8f/shard-bmg-9/igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size.html
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-bmg-2/igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions:
    - shard-lnl:          NOTRUN -> [SKIP][26] ([Intel XE#309] / [Intel XE#7343]) +1 other test skip
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-lnl-8/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions.html

  * igt@kms_dirtyfb@drrs-dirtyfb-ioctl:
    - shard-lnl:          NOTRUN -> [SKIP][27] ([Intel XE#1508])
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-lnl-3/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html
    - shard-bmg:          NOTRUN -> [SKIP][28] ([Intel XE#1508])
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-bmg-9/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html

  * igt@kms_feature_discovery@chamelium:
    - shard-bmg:          NOTRUN -> [SKIP][29] ([Intel XE#2372] / [Intel XE#7359])
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-bmg-10/igt@kms_feature_discovery@chamelium.html

  * igt@kms_flip@2x-plain-flip:
    - shard-lnl:          NOTRUN -> [SKIP][30] ([Intel XE#1421]) +2 other tests skip
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-lnl-5/igt@kms_flip@2x-plain-flip.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
    - shard-lnl:          NOTRUN -> [SKIP][31] ([Intel XE#7178] / [Intel XE#7351])
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-lnl-7/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling:
    - shard-bmg:          NOTRUN -> [SKIP][32] ([Intel XE#7178] / [Intel XE#7351]) +1 other test skip
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-bmg-7/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-p016-linear-to-p016-linear-reflect-x:
    - shard-bmg:          NOTRUN -> [SKIP][33] ([Intel XE#7179]) +1 other test skip
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-bmg-4/igt@kms_flip_scaled_crc@flip-p016-linear-to-p016-linear-reflect-x.html
    - shard-lnl:          NOTRUN -> [SKIP][34] ([Intel XE#7179])
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-lnl-7/igt@kms_flip_scaled_crc@flip-p016-linear-to-p016-linear-reflect-x.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-msflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][35] ([Intel XE#4141]) +1 other test skip
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-indfb-msflip-blt:
    - shard-lnl:          NOTRUN -> [SKIP][36] ([Intel XE#6312] / [Intel XE#651]) +4 other tests skip
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-lnl-3/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-shrfb-plflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][37] ([Intel XE#2311]) +14 other tests skip
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-shrfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-abgr161616f-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][38] ([Intel XE#7061] / [Intel XE#7356]) +3 other tests skip
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcdrrs-abgr161616f-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-pgflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][39] ([Intel XE#2313]) +23 other tests skip
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-blt:
    - shard-lnl:          NOTRUN -> [SKIP][40] ([Intel XE#656]) +4 other tests skip
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-lnl-3/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-blt.html

  * igt@kms_hdmi_inject@inject-4k:
    - shard-lnl:          NOTRUN -> [SKIP][41] ([Intel XE#1470])
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-lnl-5/igt@kms_hdmi_inject@inject-4k.html

  * igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner:
    - shard-bmg:          NOTRUN -> [SKIP][42] ([Intel XE#4090] / [Intel XE#7443])
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-bmg-6/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html
    - shard-lnl:          NOTRUN -> [SKIP][43] ([Intel XE#7173] / [Intel XE#7294])
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-lnl-1/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html

  * igt@kms_plane@pixel-format-4-tiled-mtl-rc-ccs-modifier-source-clamping:
    - shard-bmg:          NOTRUN -> [SKIP][44] ([Intel XE#7283]) +2 other tests skip
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-bmg-9/igt@kms_plane@pixel-format-4-tiled-mtl-rc-ccs-modifier-source-clamping.html

  * igt@kms_plane_lowres@tiling-yf:
    - shard-bmg:          NOTRUN -> [SKIP][45] ([Intel XE#2393])
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-bmg-4/igt@kms_plane_lowres@tiling-yf.html

  * igt@kms_plane_multiple@2x-tiling-yf:
    - shard-lnl:          NOTRUN -> [SKIP][46] ([Intel XE#4596] / [Intel XE#5854])
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-lnl-3/igt@kms_plane_multiple@2x-tiling-yf.html

  * igt@kms_pm_dc@dc5-psr:
    - shard-bmg:          NOTRUN -> [SKIP][47] ([Intel XE#2392] / [Intel XE#6927])
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-bmg-9/igt@kms_pm_dc@dc5-psr.html

  * igt@kms_pm_rpm@dpms-lpsp:
    - shard-bmg:          NOTRUN -> [SKIP][48] ([Intel XE#1439] / [Intel XE#3141] / [Intel XE#7383] / [Intel XE#836])
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-bmg-3/igt@kms_pm_rpm@dpms-lpsp.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-continuous-sf:
    - shard-lnl:          NOTRUN -> [SKIP][49] ([Intel XE#2893] / [Intel XE#4608] / [Intel XE#7304])
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-lnl-3/igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-continuous-sf.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-continuous-sf@pipe-a-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][50] ([Intel XE#4608])
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-lnl-3/igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-continuous-sf@pipe-a-edp-1.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-continuous-sf@pipe-b-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][51] ([Intel XE#4608] / [Intel XE#7304])
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-lnl-3/igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-continuous-sf@pipe-b-edp-1.html

  * igt@kms_psr2_sf@pr-primary-plane-update-sf-dmg-area:
    - shard-lnl:          NOTRUN -> [SKIP][52] ([Intel XE#2893] / [Intel XE#7304])
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-lnl-5/igt@kms_psr2_sf@pr-primary-plane-update-sf-dmg-area.html

  * igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf:
    - shard-bmg:          NOTRUN -> [SKIP][53] ([Intel XE#1489]) +4 other tests skip
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-bmg-9/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf.html

  * igt@kms_psr@fbc-psr-dpms:
    - shard-bmg:          NOTRUN -> [SKIP][54] ([Intel XE#2234] / [Intel XE#2850]) +9 other tests skip
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-bmg-4/igt@kms_psr@fbc-psr-dpms.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-180:
    - shard-bmg:          NOTRUN -> [SKIP][55] ([Intel XE#2330] / [Intel XE#5813])
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-bmg-8/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html

  * igt@kms_setmode@invalid-clone-exclusive-crtc:
    - shard-bmg:          NOTRUN -> [SKIP][56] ([Intel XE#1435])
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-bmg-7/igt@kms_setmode@invalid-clone-exclusive-crtc.html

  * igt@kms_sharpness_filter@filter-formats:
    - shard-bmg:          NOTRUN -> [SKIP][57] ([Intel XE#6503]) +2 other tests skip
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-bmg-8/igt@kms_sharpness_filter@filter-formats.html

  * igt@kms_vrr@lobf:
    - shard-bmg:          NOTRUN -> [SKIP][58] ([Intel XE#2168] / [Intel XE#7444])
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-bmg-4/igt@kms_vrr@lobf.html

  * igt@kms_vrr@lobf@pipe-a-edp-1:
    - shard-lnl:          NOTRUN -> [FAIL][59] ([Intel XE#6390] / [Intel XE#7461]) +1 other test fail
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-lnl-7/igt@kms_vrr@lobf@pipe-a-edp-1.html

  * igt@xe_compute@ccs-mode-basic:
    - shard-bmg:          NOTRUN -> [SKIP][60] ([Intel XE#6599])
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-bmg-8/igt@xe_compute@ccs-mode-basic.html

  * igt@xe_eudebug@basic-vm-access-parameters-faultable:
    - shard-lnl:          NOTRUN -> [SKIP][61] ([Intel XE#4837]) +1 other test skip
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-lnl-6/igt@xe_eudebug@basic-vm-access-parameters-faultable.html

  * igt@xe_eudebug@basic-vm-bind-ufence:
    - shard-bmg:          NOTRUN -> [SKIP][62] ([Intel XE#4837]) +5 other tests skip
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-bmg-6/igt@xe_eudebug@basic-vm-bind-ufence.html

  * igt@xe_eudebug_online@pagefault-read-stress:
    - shard-lnl:          NOTRUN -> [SKIP][63] ([Intel XE#6665])
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-lnl-5/igt@xe_eudebug_online@pagefault-read-stress.html

  * igt@xe_eudebug_online@single-step:
    - shard-bmg:          NOTRUN -> [SKIP][64] ([Intel XE#4837] / [Intel XE#6665]) +2 other tests skip
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-bmg-9/igt@xe_eudebug_online@single-step.html

  * igt@xe_eudebug_online@writes-caching-vram-bb-sram-target-vram:
    - shard-lnl:          NOTRUN -> [SKIP][65] ([Intel XE#4837] / [Intel XE#6665])
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-lnl-8/igt@xe_eudebug_online@writes-caching-vram-bb-sram-target-vram.html

  * igt@xe_eudebug_sriov@deny-sriov:
    - shard-bmg:          NOTRUN -> [SKIP][66] ([Intel XE#5793] / [Intel XE#7320] / [Intel XE#7464])
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-bmg-10/igt@xe_eudebug_sriov@deny-sriov.html

  * igt@xe_evict@evict-beng-mixed-many-threads-small:
    - shard-bmg:          [PASS][67] -> [INCOMPLETE][68] ([Intel XE#6321])
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4674-a48305e6a2e6a1ed90df374101dd29542c105d8f/shard-bmg-1/igt@xe_evict@evict-beng-mixed-many-threads-small.html
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-bmg-9/igt@xe_evict@evict-beng-mixed-many-threads-small.html

  * igt@xe_evict@evict-small-multi-queue:
    - shard-bmg:          NOTRUN -> [SKIP][69] ([Intel XE#7140]) +1 other test skip
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-bmg-8/igt@xe_evict@evict-small-multi-queue.html
    - shard-lnl:          NOTRUN -> [SKIP][70] ([Intel XE#6540] / [Intel XE#688])
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-lnl-5/igt@xe_evict@evict-small-multi-queue.html

  * igt@xe_exec_balancer@many-virtual-userptr-invalidate-race:
    - shard-lnl:          NOTRUN -> [SKIP][71] ([Intel XE#7482]) +4 other tests skip
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-lnl-4/igt@xe_exec_balancer@many-virtual-userptr-invalidate-race.html

  * igt@xe_exec_basic@multigpu-once-basic:
    - shard-lnl:          NOTRUN -> [SKIP][72] ([Intel XE#1392])
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-lnl-3/igt@xe_exec_basic@multigpu-once-basic.html

  * igt@xe_exec_basic@multigpu-once-basic-defer-bind:
    - shard-bmg:          NOTRUN -> [SKIP][73] ([Intel XE#2322] / [Intel XE#7372]) +5 other tests skip
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-bmg-8/igt@xe_exec_basic@multigpu-once-basic-defer-bind.html

  * igt@xe_exec_fault_mode@many-execqueues-multi-queue-userptr-invalidate:
    - shard-lnl:          NOTRUN -> [SKIP][74] ([Intel XE#7136]) +3 other tests skip
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-lnl-8/igt@xe_exec_fault_mode@many-execqueues-multi-queue-userptr-invalidate.html

  * igt@xe_exec_fault_mode@many-multi-queue-userptr-rebind-prefetch:
    - shard-bmg:          NOTRUN -> [SKIP][75] ([Intel XE#7136]) +5 other tests skip
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-bmg-6/igt@xe_exec_fault_mode@many-multi-queue-userptr-rebind-prefetch.html

  * igt@xe_exec_multi_queue@few-execs-preempt-mode-close-fd-smem:
    - shard-bmg:          NOTRUN -> [SKIP][76] ([Intel XE#6874]) +18 other tests skip
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-bmg-7/igt@xe_exec_multi_queue@few-execs-preempt-mode-close-fd-smem.html

  * igt@xe_exec_multi_queue@many-execs-preempt-mode-fault-dyn-priority:
    - shard-lnl:          NOTRUN -> [SKIP][77] ([Intel XE#6874]) +6 other tests skip
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-lnl-6/igt@xe_exec_multi_queue@many-execs-preempt-mode-fault-dyn-priority.html

  * igt@xe_exec_threads@threads-multi-queue-cm-fd-userptr-rebind:
    - shard-bmg:          NOTRUN -> [SKIP][78] ([Intel XE#7138]) +6 other tests skip
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-bmg-7/igt@xe_exec_threads@threads-multi-queue-cm-fd-userptr-rebind.html

  * igt@xe_exec_threads@threads-multi-queue-shared-vm-userptr-invalidate:
    - shard-lnl:          NOTRUN -> [SKIP][79] ([Intel XE#7138]) +1 other test skip
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-lnl-8/igt@xe_exec_threads@threads-multi-queue-shared-vm-userptr-invalidate.html

  * igt@xe_media_fill@media-fill:
    - shard-bmg:          NOTRUN -> [SKIP][80] ([Intel XE#2459] / [Intel XE#2596] / [Intel XE#7321] / [Intel XE#7453])
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-bmg-3/igt@xe_media_fill@media-fill.html

  * igt@xe_mmap@pci-membarrier-bad-pagesize:
    - shard-lnl:          NOTRUN -> [SKIP][81] ([Intel XE#5100] / [Intel XE#7322] / [Intel XE#7408])
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-lnl-3/igt@xe_mmap@pci-membarrier-bad-pagesize.html

  * igt@xe_mmap@vram:
    - shard-lnl:          NOTRUN -> [SKIP][82] ([Intel XE#1416])
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-lnl-6/igt@xe_mmap@vram.html

  * igt@xe_multigpu_svm@mgpu-migration-basic:
    - shard-bmg:          NOTRUN -> [SKIP][83] ([Intel XE#6964])
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-bmg-4/igt@xe_multigpu_svm@mgpu-migration-basic.html

  * igt@xe_pat@pat-index-xelpg:
    - shard-bmg:          NOTRUN -> [SKIP][84] ([Intel XE#2236])
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-bmg-9/igt@xe_pat@pat-index-xelpg.html

  * igt@xe_pm@d3cold-mmap-system:
    - shard-bmg:          NOTRUN -> [SKIP][85] ([Intel XE#2284] / [Intel XE#7370])
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-bmg-4/igt@xe_pm@d3cold-mmap-system.html

  * igt@xe_pm@s3-vm-bind-prefetch:
    - shard-lnl:          NOTRUN -> [SKIP][86] ([Intel XE#584] / [Intel XE#7369])
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-lnl-4/igt@xe_pm@s3-vm-bind-prefetch.html

  * igt@xe_query@multigpu-query-pxp-status:
    - shard-bmg:          NOTRUN -> [SKIP][87] ([Intel XE#944]) +1 other test skip
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-bmg-3/igt@xe_query@multigpu-query-pxp-status.html

  * igt@xe_sriov_flr@flr-vfs-parallel:
    - shard-lnl:          NOTRUN -> [SKIP][88] ([Intel XE#4273])
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-lnl-1/igt@xe_sriov_flr@flr-vfs-parallel.html

  
#### Possible fixes ####

  * igt@kms_async_flips@async-flip-with-page-flip-events-linear-atomic@pipe-c-edp-1:
    - shard-lnl:          [FAIL][89] ([Intel XE#6054]) -> [PASS][90] +3 other tests pass
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4674-a48305e6a2e6a1ed90df374101dd29542c105d8f/shard-lnl-7/igt@kms_async_flips@async-flip-with-page-flip-events-linear-atomic@pipe-c-edp-1.html
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-lnl-6/igt@kms_async_flips@async-flip-with-page-flip-events-linear-atomic@pipe-c-edp-1.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic:
    - shard-bmg:          [FAIL][91] -> [PASS][92]
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4674-a48305e6a2e6a1ed90df374101dd29542c105d8f/shard-bmg-7/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-bmg-4/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp2:
    - shard-bmg:          [FAIL][93] ([Intel XE#7545]) -> [PASS][94] +1 other test pass
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4674-a48305e6a2e6a1ed90df374101dd29542c105d8f/shard-bmg-1/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp2.html
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-bmg-4/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp2.html

  * igt@kms_flip@flip-vs-expired-vblank@c-edp1:
    - shard-lnl:          [FAIL][95] ([Intel XE#301] / [Intel XE#3149]) -> [PASS][96] +1 other test pass
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4674-a48305e6a2e6a1ed90df374101dd29542c105d8f/shard-lnl-6/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-lnl-6/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html

  * igt@kms_pm_dc@dc5-dpms:
    - shard-lnl:          [FAIL][97] ([Intel XE#7340] / [Intel XE#7504]) -> [PASS][98]
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4674-a48305e6a2e6a1ed90df374101dd29542c105d8f/shard-lnl-7/igt@kms_pm_dc@dc5-dpms.html
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-lnl-3/igt@kms_pm_dc@dc5-dpms.html

  * igt@kms_setmode@basic:
    - shard-bmg:          [FAIL][99] ([Intel XE#6361]) -> [PASS][100] +3 other tests pass
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4674-a48305e6a2e6a1ed90df374101dd29542c105d8f/shard-bmg-9/igt@kms_setmode@basic.html
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-bmg-2/igt@kms_setmode@basic.html

  * igt@kms_setmode@basic@pipe-b-edp-1:
    - shard-lnl:          [FAIL][101] ([Intel XE#6361]) -> [PASS][102] +2 other tests pass
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4674-a48305e6a2e6a1ed90df374101dd29542c105d8f/shard-lnl-1/igt@kms_setmode@basic@pipe-b-edp-1.html
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-lnl-7/igt@kms_setmode@basic@pipe-b-edp-1.html

  * igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1:
    - shard-lnl:          [FAIL][103] ([Intel XE#2142]) -> [PASS][104] +1 other test pass
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4674-a48305e6a2e6a1ed90df374101dd29542c105d8f/shard-lnl-2/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-lnl-4/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html

  
#### Warnings ####

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-bmg:          [SKIP][105] ([Intel XE#2426] / [Intel XE#5848]) -> [FAIL][106] ([Intel XE#1729] / [Intel XE#7424])
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4674-a48305e6a2e6a1ed90df374101dd29542c105d8f/shard-bmg-1/igt@kms_tiled_display@basic-test-pattern.html
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-bmg-4/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-bmg:          [SKIP][107] ([Intel XE#2426] / [Intel XE#5848]) -> [SKIP][108] ([Intel XE#2509] / [Intel XE#7437])
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4674-a48305e6a2e6a1ed90df374101dd29542c105d8f/shard-bmg-8/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/shard-bmg-4/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1416]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1416
  [Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
  [Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
  [Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
  [Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
  [Intel XE#1470]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1470
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1508]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1508
  [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
  [Intel XE#2142]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2142
  [Intel XE#2168]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2168
  [Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2236]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2236
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2330
  [Intel XE#2372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2372
  [Intel XE#2392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2392
  [Intel XE#2393]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2393
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2459]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2459
  [Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
  [Intel XE#2596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2596
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#3141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3141
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#3157]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3157
  [Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
  [Intel XE#3658]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3658
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#4090]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4090
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4273]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4273
  [Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
  [Intel XE#4608]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4608
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#5100]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5100
  [Intel XE#5545]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5545
  [Intel XE#5793]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5793
  [Intel XE#5813]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5813
  [Intel XE#584]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/584
  [Intel XE#5848]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5848
  [Intel XE#5854]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5854
  [Intel XE#5937]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5937
  [Intel XE#6054]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6054
  [Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
  [Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
  [Intel XE#6361]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6361
  [Intel XE#6390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6390
  [Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#6540]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6540
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#6599]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6599
  [Intel XE#6652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6652
  [Intel XE#6665]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6665
  [Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#6927]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6927
  [Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
  [Intel XE#7059]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7059
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7085]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7085
  [Intel XE#7136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7136
  [Intel XE#7138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7138
  [Intel XE#7140]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7140
  [Intel XE#7173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7173
  [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
  [Intel XE#7179]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7179
  [Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
  [Intel XE#7294]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7294
  [Intel XE#7304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7304
  [Intel XE#7305]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7305
  [Intel XE#7320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7320
  [Intel XE#7321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7321
  [Intel XE#7322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7322
  [Intel XE#7340]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7340
  [Intel XE#7343]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7343
  [Intel XE#7351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7351
  [Intel XE#7354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7354
  [Intel XE#7355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7355
  [Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
  [Intel XE#7358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7358
  [Intel XE#7359]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7359
  [Intel XE#7360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7360
  [Intel XE#7369]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7369
  [Intel XE#7370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7370
  [Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
  [Intel XE#7373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7373
  [Intel XE#7383]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7383
  [Intel XE#7408]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7408
  [Intel XE#7424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7424
  [Intel XE#7437]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7437
  [Intel XE#7443]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7443
  [Intel XE#7444]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7444
  [Intel XE#7453]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7453
  [Intel XE#7461]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7461
  [Intel XE#7464]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7464
  [Intel XE#7482]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7482
  [Intel XE#7504]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7504
  [Intel XE#7545]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7545
  [Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * IGT: IGT_8782 -> IGT_8783
  * Linux: xe-4674-a48305e6a2e6a1ed90df374101dd29542c105d8f -> xe-pw-161586v3

  IGT_8782: eac3b04d1f76b82ac3a183fb293c44e9185d8dba @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  IGT_8783: b5051dc2e867005c758c707312aa9cf9d1dc3291 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-4674-a48305e6a2e6a1ed90df374101dd29542c105d8f: a48305e6a2e6a1ed90df374101dd29542c105d8f
  xe-pw-161586v3: 161586v3

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161586v3/index.html

[-- Attachment #2: Type: text/html, Size: 42474 bytes --]

✗ CI.checkpatch: warning for Refactor LT PHY PLL handling to use DPLL framework (rev5)

[Patchwork]

== Series Details ==

Series: Refactor LT PHY PLL handling to use DPLL framework (rev5)
URL   : https://patchwork.freedesktop.org/series/161586/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
1f57ba1afceae32108bd24770069f764d940a0e4
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit c3a7b6958eddefe660aeb2c5f81bd02fa469a8c2
Author: Mika Kahola <mika.kahola@intel.com>
Date:   Wed Mar 4 13:14:23 2026 +0000

    drm/i915/lt_phy: Enable dpll framework for xe3plpd
    
    xe3plpd platform is supported by dpll framework remove a separate
    check for hw comparison and rely solely on dpll framework
    hw comparison.
    
    Finally, all required hooks are now in place so initialize
    PLL manager for xe3plpd platform and remove the redirections
    to the legacy code paths for clock enable/disable as well as
    state mismatch checks that are no longer needed.
    
    Signed-off-by: Mika Kahola <mika.kahola@intel.com>
+ /mt/dim checkpatch adf67fb1258884dab38a71526783f901069dbb81 drm-intel
d40e20787f64 drm/i915/lt_phy: Dump missing PLL state parameters
388729244ec0 drm/i915/lt_phy: Add check if PLL is enabled
0630b9ef675a drm/i915/lt_phy: Add PLL information for xe3plpd
f66fd6cfbe0d drm/i915/lt_phy: Refactor LT PHY PLL handling to use explicit PLL state
1a4ca2304c64 drm/i915/lt_phy: Add lane_count to PLL state
8d5753a4847a drm/i915/lt_phy: Add xe3plpd .compute_dplls hook
219a705953cd drm/i915/lt_phy: Add xe3plpd .get_dplls hook
6bf332452054 drm/i915/lt_phy: Add xe3plpd .put_dplls hook
e79ef1642de1 drm/i915/lt_phy: Add xe3plpd .update_active_dpll hook
60c49b458dfe drm/i915/lt_phy: Add xe3plpd .update_dpll_ref_clks hook
be7f4b731c33 drm/i915/lt_phy: Add xe3plpd .dump_hw_state hook
-:12: WARNING:BAD_SIGN_OFF: Duplicate signature
#12: 
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

total: 0 errors, 1 warnings, 0 checks, 89 lines checked
187754cdb341 drm/i915/lt_phy: Add xe3plpd .compare_hw_state hook
65d0a0e149c9 drm/i915/lt_phy: Add xe3plpd .get_hw_state hook
b380762411fc drm/i915/lt_phy: Add xe3plpd .get_freq hook
6dfde09bde80 drm/i915/lt_phy: Add xe3plpd .crtc_get_dpll
5f6728dc2bf3 drm/i915/lt_phy: Replace crtc compute clock
40f6a74b71da drm/i915/lt_phy: Add .enable_clock hook on DDI
20fac0d0bdfe drm/i915/lt_phy: Add .disable_clock hook on DDI
cd0710e12ba6 drm/i915/lt_phy: Dump lane count for HW state
985cd3b678ec drm/i915/lt_phy: Readout lane count
69ef522ee863 drm/i915/lt_phy: Get encoder configuration for xe3plpd platform
8735498a9efe drm/i915/lt_phy: Add xe3plpd Thunderbolt pll hooks
e21c61ea09e4 drm/i915/lt_phy: Remove LT PHY specific state verification
-:39: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#39: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:5124:
+			pll_mismatch = !dpll_mgr->compare_hw_state(&pll->state.hw_state, &dpll_hw_state);

-:41: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#41: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:5126:
+			pll_mismatch = memcmp(&pll->state.hw_state, &dpll_hw_state, sizeof(dpll_hw_state));

total: 0 errors, 2 warnings, 0 checks, 86 lines checked
c3a7b6958edd drm/i915/lt_phy: Enable dpll framework for xe3plpd

✗ CI.KUnit: failure for Refactor LT PHY PLL handling to use DPLL framework (rev5)

[Patchwork]

== Series Details ==

Series: Refactor LT PHY PLL handling to use DPLL framework (rev5)
URL   : https://patchwork.freedesktop.org/series/161586/
State : failure

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
ERROR:root:../drivers/gpu/drm/xe/xe_lrc.c: In function ‘xe_lrc_ctx_init’:
../drivers/gpu/drm/xe/xe_lrc.c:1554:43: error: implicit declaration of function ‘_MASKED_BIT_ENABLE’; did you mean ‘REG_MASKED_FIELD_ENABLE’? [-Werror=implicit-function-declaration]
 1554 |                 state_cache_perf_fix[2] = _MASKED_BIT_ENABLE(DISABLE_STATE_CACHE_PERF_FIX);
      |                                           ^~~~~~~~~~~~~~~~~~
      |                                           REG_MASKED_FIELD_ENABLE
cc1: some warnings being treated as errors
make[7]: *** [../scripts/Makefile.build:289: drivers/gpu/drm/xe/xe_lrc.o] Error 1
make[7]: *** Waiting for unfinished jobs....
make[6]: *** [../scripts/Makefile.build:548: drivers/gpu/drm/xe] Error 2
make[5]: *** [../scripts/Makefile.build:548: drivers/gpu/drm] Error 2
make[4]: *** [../scripts/Makefile.build:548: drivers/gpu] Error 2
make[3]: *** [../scripts/Makefile.build:548: drivers] Error 2
make[2]: *** [/kernel/Makefile:2101: .] Error 2
make[1]: *** [/kernel/Makefile:248: __sub-make] Error 2
make: *** [Makefile:248: __sub-make] Error 2

[16:09:02] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[16:09:07] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel