* [PATCH] drm/xe: Add min and max context TLB invalidation sizes
@ 2026-03-17 19:50 Stuart Summers
2026-03-17 19:57 ` ✓ CI.KUnit: success for " Patchwork
` (2 more replies)
0 siblings, 3 replies; 15+ messages in thread
From: Stuart Summers @ 2026-03-17 19:50 UTC (permalink / raw)
Cc: matthew.brost, intel-xe, Stuart Summers
Allow platform-defined TLB invalidation min and max lengths.
This gives finer granular control to which invalidations we
decide to send to GuC. The min size is essentially a round
up. The max allows us to switch to a full invalidation.
The expectation here is that GuC will translate the full
invalidation in this instance into a series of per context
invalidations. These are then issued with no H2G or G2H
messages and therefore should be quicker than splitting
the invalidations from the KMD in max size chunks and sending
separately.
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
drivers/gpu/drm/xe/xe_device_types.h | 4 ++++
drivers/gpu/drm/xe/xe_guc_tlb_inval.c | 14 ++++++++------
drivers/gpu/drm/xe/xe_pci.c | 2 ++
drivers/gpu/drm/xe/xe_pci_types.h | 2 ++
4 files changed, 16 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 615218d775b1..0c4168fe2ffb 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -137,6 +137,10 @@ struct xe_device {
u8 vm_max_level;
/** @info.va_bits: Maximum bits of a virtual address */
u8 va_bits;
+ /** @info.min_tlb_inval_size: Minimum size of context based TLB invalidations */
+ u64 min_tlb_inval_size;
+ /** @info.max_tlb_inval_size: Maximum size of context based TLB invalidations */
+ u64 max_tlb_inval_size;
/*
* Keep all flags below alphabetically sorted
diff --git a/drivers/gpu/drm/xe/xe_guc_tlb_inval.c b/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
index ced58f46f846..256759b826bc 100644
--- a/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
+++ b/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
@@ -117,12 +117,12 @@ static int send_page_reclaim(struct xe_guc *guc, u32 seqno,
static u64 normalize_invalidation_range(struct xe_gt *gt, u64 *start, u64 *end)
{
+ struct xe_device *xe = gt_to_xe(gt);
u64 orig_start = *start;
u64 length = *end - *start;
u64 align;
- if (length < SZ_4K)
- length = SZ_4K;
+ length = max_t(u64, xe->info.min_tlb_inval_size, length);
align = roundup_pow_of_two(length);
*start = ALIGN_DOWN(*start, align);
@@ -162,9 +162,12 @@ static int send_tlb_inval_ppgtt(struct xe_guc *guc, u32 seqno, u64 start,
struct xe_gt *gt = guc_to_gt(guc);
struct xe_device *xe = guc_to_xe(guc);
u32 action[MAX_TLB_INVALIDATION_LEN];
- u64 length = end - start;
+ u64 normalize_len, length = end - start;
int len = 0, err;
+ normalize_len = normalize_invalidation_range(gt, &start,
+ &end);
+
xe_gt_assert(gt, (type == XE_GUC_TLB_INVAL_PAGE_SELECTIVE &&
!xe->info.has_ctx_tlb_inval) ||
(type == XE_GUC_TLB_INVAL_PAGE_SELECTIVE_CTX &&
@@ -173,11 +176,10 @@ static int send_tlb_inval_ppgtt(struct xe_guc *guc, u32 seqno, u64 start,
action[len++] = XE_GUC_ACTION_TLB_INVALIDATION;
action[len++] = !prl_sa ? seqno : TLB_INVALIDATION_SEQNO_INVALID;
if (!gt_to_xe(gt)->info.has_range_tlb_inval ||
- length > MAX_RANGE_TLB_INVALIDATION_LENGTH) {
+ length > MAX_RANGE_TLB_INVALIDATION_LENGTH ||
+ normalize_len > xe->info.max_tlb_inval_size) {
action[len++] = MAKE_INVAL_OP(XE_GUC_TLB_INVAL_FULL);
} else {
- u64 normalize_len = normalize_invalidation_range(gt, &start,
- &end);
bool need_flush = !prl_sa &&
seqno != TLB_INVALIDATION_SEQNO_INVALID;
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 189e2a1c29f9..12569367034b 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -742,6 +742,8 @@ static int xe_info_init_early(struct xe_device *xe,
xe->info.va_bits = desc->va_bits;
xe->info.vm_max_level = desc->vm_max_level;
xe->info.vram_flags = desc->vram_flags;
+ xe->info.min_tlb_inval_size = desc->min_tlb_inval_size;
+ xe->info.max_tlb_inval_size = desc->max_tlb_inval_size;
xe->info.is_dgfx = desc->is_dgfx;
xe->info.has_cached_pt = desc->has_cached_pt;
diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
index 8eee4fb1c57c..cd9d3ad96fe0 100644
--- a/drivers/gpu/drm/xe/xe_pci_types.h
+++ b/drivers/gpu/drm/xe/xe_pci_types.h
@@ -34,6 +34,8 @@ struct xe_device_desc {
u8 va_bits;
u8 vm_max_level;
u8 vram_flags;
+ u64 min_tlb_inval_size;
+ u64 max_tlb_inval_size;
u8 require_force_probe:1;
u8 is_dgfx:1;
--
2.43.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* ✓ CI.KUnit: success for drm/xe: Add min and max context TLB invalidation sizes
2026-03-17 19:50 [PATCH] drm/xe: Add min and max context TLB invalidation sizes Stuart Summers
@ 2026-03-17 19:57 ` Patchwork
2026-03-17 21:01 ` ✓ Xe.CI.BAT: " Patchwork
2026-03-19 6:52 ` ✓ Xe.CI.FULL: " Patchwork
2 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2026-03-17 19:57 UTC (permalink / raw)
To: Stuart Summers; +Cc: intel-xe
== Series Details ==
Series: drm/xe: Add min and max context TLB invalidation sizes
URL : https://patchwork.freedesktop.org/series/163403/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[19:55:57] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[19:56:02] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[19:56:32] Starting KUnit Kernel (1/1)...
[19:56:32] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[19:56:32] ================== guc_buf (11 subtests) ===================
[19:56:32] [PASSED] test_smallest
[19:56:32] [PASSED] test_largest
[19:56:32] [PASSED] test_granular
[19:56:32] [PASSED] test_unique
[19:56:32] [PASSED] test_overlap
[19:56:32] [PASSED] test_reusable
[19:56:32] [PASSED] test_too_big
[19:56:32] [PASSED] test_flush
[19:56:32] [PASSED] test_lookup
[19:56:32] [PASSED] test_data
[19:56:32] [PASSED] test_class
[19:56:32] ===================== [PASSED] guc_buf =====================
[19:56:32] =================== guc_dbm (7 subtests) ===================
[19:56:32] [PASSED] test_empty
[19:56:32] [PASSED] test_default
[19:56:32] ======================== test_size ========================
[19:56:32] [PASSED] 4
[19:56:32] [PASSED] 8
[19:56:32] [PASSED] 32
[19:56:32] [PASSED] 256
[19:56:32] ==================== [PASSED] test_size ====================
[19:56:32] ======================= test_reuse ========================
[19:56:32] [PASSED] 4
[19:56:32] [PASSED] 8
[19:56:32] [PASSED] 32
[19:56:32] [PASSED] 256
[19:56:32] =================== [PASSED] test_reuse ====================
[19:56:32] =================== test_range_overlap ====================
[19:56:32] [PASSED] 4
[19:56:32] [PASSED] 8
[19:56:32] [PASSED] 32
[19:56:32] [PASSED] 256
[19:56:32] =============== [PASSED] test_range_overlap ================
[19:56:32] =================== test_range_compact ====================
[19:56:32] [PASSED] 4
[19:56:32] [PASSED] 8
[19:56:32] [PASSED] 32
[19:56:32] [PASSED] 256
[19:56:32] =============== [PASSED] test_range_compact ================
[19:56:32] ==================== test_range_spare =====================
[19:56:32] [PASSED] 4
[19:56:32] [PASSED] 8
[19:56:32] [PASSED] 32
[19:56:32] [PASSED] 256
[19:56:32] ================ [PASSED] test_range_spare =================
[19:56:32] ===================== [PASSED] guc_dbm =====================
[19:56:32] =================== guc_idm (6 subtests) ===================
[19:56:32] [PASSED] bad_init
[19:56:32] [PASSED] no_init
[19:56:32] [PASSED] init_fini
[19:56:32] [PASSED] check_used
[19:56:32] [PASSED] check_quota
[19:56:32] [PASSED] check_all
[19:56:32] ===================== [PASSED] guc_idm =====================
[19:56:32] ================== no_relay (3 subtests) ===================
[19:56:32] [PASSED] xe_drops_guc2pf_if_not_ready
[19:56:32] [PASSED] xe_drops_guc2vf_if_not_ready
[19:56:32] [PASSED] xe_rejects_send_if_not_ready
[19:56:32] ==================== [PASSED] no_relay =====================
[19:56:32] ================== pf_relay (14 subtests) ==================
[19:56:32] [PASSED] pf_rejects_guc2pf_too_short
[19:56:32] [PASSED] pf_rejects_guc2pf_too_long
[19:56:32] [PASSED] pf_rejects_guc2pf_no_payload
[19:56:32] [PASSED] pf_fails_no_payload
[19:56:32] [PASSED] pf_fails_bad_origin
[19:56:32] [PASSED] pf_fails_bad_type
[19:56:32] [PASSED] pf_txn_reports_error
[19:56:32] [PASSED] pf_txn_sends_pf2guc
[19:56:32] [PASSED] pf_sends_pf2guc
[19:56:32] [SKIPPED] pf_loopback_nop
[19:56:32] [SKIPPED] pf_loopback_echo
[19:56:32] [SKIPPED] pf_loopback_fail
[19:56:32] [SKIPPED] pf_loopback_busy
[19:56:32] [SKIPPED] pf_loopback_retry
[19:56:32] ==================== [PASSED] pf_relay =====================
[19:56:32] ================== vf_relay (3 subtests) ===================
[19:56:32] [PASSED] vf_rejects_guc2vf_too_short
[19:56:32] [PASSED] vf_rejects_guc2vf_too_long
[19:56:32] [PASSED] vf_rejects_guc2vf_no_payload
[19:56:32] ==================== [PASSED] vf_relay =====================
[19:56:32] ================ pf_gt_config (9 subtests) =================
[19:56:32] [PASSED] fair_contexts_1vf
[19:56:32] [PASSED] fair_doorbells_1vf
[19:56:32] [PASSED] fair_ggtt_1vf
[19:56:32] ====================== fair_vram_1vf ======================
[19:56:32] [PASSED] 3.50 GiB
[19:56:32] [PASSED] 11.5 GiB
[19:56:32] [PASSED] 15.5 GiB
[19:56:32] [PASSED] 31.5 GiB
[19:56:32] [PASSED] 63.5 GiB
[19:56:32] [PASSED] 1.91 GiB
[19:56:32] ================== [PASSED] fair_vram_1vf ==================
[19:56:32] ================ fair_vram_1vf_admin_only =================
[19:56:32] [PASSED] 3.50 GiB
[19:56:32] [PASSED] 11.5 GiB
[19:56:32] [PASSED] 15.5 GiB
[19:56:32] [PASSED] 31.5 GiB
[19:56:32] [PASSED] 63.5 GiB
[19:56:32] [PASSED] 1.91 GiB
[19:56:32] ============ [PASSED] fair_vram_1vf_admin_only =============
[19:56:32] ====================== fair_contexts ======================
[19:56:32] [PASSED] 1 VF
[19:56:32] [PASSED] 2 VFs
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[19:56:33] [PASSED] 62 VFs
[19:56:33] [PASSED] 63 VFs
[19:56:33] ================== [PASSED] fair_contexts ==================
[19:56:33] ===================== fair_doorbells ======================
[19:56:33] [PASSED] 1 VF
[19:56:33] [PASSED] 2 VFs
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[19:56:33] [PASSED] 57 VFs
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[19:56:33] [PASSED] 60 VFs
[19:56:33] [PASSED] 61 VFs
[19:56:33] [PASSED] 62 VFs
[19:56:33] [PASSED] 63 VFs
[19:56:33] ================= [PASSED] fair_doorbells ==================
[19:56:33] ======================== fair_ggtt ========================
[19:56:33] [PASSED] 1 VF
[19:56:33] [PASSED] 2 VFs
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[19:56:33] [PASSED] 51 VFs
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[19:56:33] [PASSED] 61 VFs
[19:56:33] [PASSED] 62 VFs
[19:56:33] [PASSED] 63 VFs
[19:56:33] ==================== [PASSED] fair_ggtt ====================
[19:56:33] ======================== fair_vram ========================
[19:56:33] [PASSED] 1 VF
[19:56:33] [PASSED] 2 VFs
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[19:56:33] [PASSED] 28 VFs
[19:56:33] [PASSED] 29 VFs
[19:56:33] [PASSED] 30 VFs
[19:56:33] [PASSED] 31 VFs
[19:56:33] [PASSED] 32 VFs
[19:56:33] [PASSED] 33 VFs
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[19:56:33] [PASSED] 35 VFs
[19:56:33] [PASSED] 36 VFs
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[19:56:33] [PASSED] 38 VFs
[19:56:33] [PASSED] 39 VFs
[19:56:33] [PASSED] 40 VFs
[19:56:33] [PASSED] 41 VFs
[19:56:33] [PASSED] 42 VFs
[19:56:33] [PASSED] 43 VFs
[19:56:33] [PASSED] 44 VFs
[19:56:33] [PASSED] 45 VFs
[19:56:33] [PASSED] 46 VFs
[19:56:33] [PASSED] 47 VFs
[19:56:33] [PASSED] 48 VFs
[19:56:33] [PASSED] 49 VFs
[19:56:33] [PASSED] 50 VFs
[19:56:33] [PASSED] 51 VFs
[19:56:33] [PASSED] 52 VFs
[19:56:33] [PASSED] 53 VFs
[19:56:33] [PASSED] 54 VFs
[19:56:33] [PASSED] 55 VFs
[19:56:33] [PASSED] 56 VFs
[19:56:33] [PASSED] 57 VFs
[19:56:33] [PASSED] 58 VFs
[19:56:33] [PASSED] 59 VFs
[19:56:33] [PASSED] 60 VFs
[19:56:33] [PASSED] 61 VFs
[19:56:33] [PASSED] 62 VFs
[19:56:33] [PASSED] 63 VFs
[19:56:33] ==================== [PASSED] fair_vram ====================
[19:56:33] ================== [PASSED] pf_gt_config ===================
[19:56:33] ===================== lmtt (1 subtest) =====================
[19:56:33] ======================== test_ops =========================
[19:56:33] [PASSED] 2-level
[19:56:33] [PASSED] multi-level
[19:56:33] ==================== [PASSED] test_ops =====================
[19:56:33] ====================== [PASSED] lmtt =======================
[19:56:33] ================= pf_service (11 subtests) =================
[19:56:33] [PASSED] pf_negotiate_any
[19:56:33] [PASSED] pf_negotiate_base_match
[19:56:33] [PASSED] pf_negotiate_base_newer
[19:56:33] [PASSED] pf_negotiate_base_next
[19:56:33] [SKIPPED] pf_negotiate_base_older
[19:56:33] [PASSED] pf_negotiate_base_prev
[19:56:33] [PASSED] pf_negotiate_latest_match
[19:56:33] [PASSED] pf_negotiate_latest_newer
[19:56:33] [PASSED] pf_negotiate_latest_next
[19:56:33] [SKIPPED] pf_negotiate_latest_older
[19:56:33] [SKIPPED] pf_negotiate_latest_prev
[19:56:33] =================== [PASSED] pf_service ====================
[19:56:33] ================= xe_guc_g2g (2 subtests) ==================
[19:56:33] ============== xe_live_guc_g2g_kunit_default ==============
[19:56:33] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[19:56:33] ============== xe_live_guc_g2g_kunit_allmem ===============
[19:56:33] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[19:56:33] =================== [SKIPPED] xe_guc_g2g ===================
[19:56:33] =================== xe_mocs (2 subtests) ===================
[19:56:33] ================ xe_live_mocs_kernel_kunit ================
[19:56:33] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[19:56:33] ================ xe_live_mocs_reset_kunit =================
[19:56:33] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[19:56:33] ==================== [SKIPPED] xe_mocs =====================
[19:56:33] ================= xe_migrate (2 subtests) ==================
[19:56:33] ================= xe_migrate_sanity_kunit =================
[19:56:33] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[19:56:33] ================== xe_validate_ccs_kunit ==================
[19:56:33] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[19:56:33] =================== [SKIPPED] xe_migrate ===================
[19:56:33] ================== xe_dma_buf (1 subtest) ==================
[19:56:33] ==================== xe_dma_buf_kunit =====================
[19:56:33] ================ [SKIPPED] xe_dma_buf_kunit ================
[19:56:33] =================== [SKIPPED] xe_dma_buf ===================
[19:56:33] ================= xe_bo_shrink (1 subtest) =================
[19:56:33] =================== xe_bo_shrink_kunit ====================
[19:56:33] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[19:56:33] ================== [SKIPPED] xe_bo_shrink ==================
[19:56:33] ==================== xe_bo (2 subtests) ====================
[19:56:33] ================== xe_ccs_migrate_kunit ===================
[19:56:33] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[19:56:33] ==================== xe_bo_evict_kunit ====================
[19:56:33] =============== [SKIPPED] xe_bo_evict_kunit ================
[19:56:33] ===================== [SKIPPED] xe_bo ======================
[19:56:33] ==================== args (13 subtests) ====================
[19:56:33] [PASSED] count_args_test
[19:56:33] [PASSED] call_args_example
[19:56:33] [PASSED] call_args_test
[19:56:33] [PASSED] drop_first_arg_example
[19:56:33] [PASSED] drop_first_arg_test
[19:56:33] [PASSED] first_arg_example
[19:56:33] [PASSED] first_arg_test
[19:56:33] [PASSED] last_arg_example
[19:56:33] [PASSED] last_arg_test
[19:56:33] [PASSED] pick_arg_example
[19:56:33] [PASSED] if_args_example
[19:56:33] [PASSED] if_args_test
[19:56:33] [PASSED] sep_comma_example
[19:56:33] ====================== [PASSED] args =======================
[19:56:33] =================== xe_pci (3 subtests) ====================
[19:56:33] ==================== check_graphics_ip ====================
[19:56:33] [PASSED] 12.00 Xe_LP
[19:56:33] [PASSED] 12.10 Xe_LP+
[19:56:33] [PASSED] 12.55 Xe_HPG
[19:56:33] [PASSED] 12.60 Xe_HPC
[19:56:33] [PASSED] 12.70 Xe_LPG
[19:56:33] [PASSED] 12.71 Xe_LPG
[19:56:33] [PASSED] 12.74 Xe_LPG+
[19:56:33] [PASSED] 20.01 Xe2_HPG
[19:56:33] [PASSED] 20.02 Xe2_HPG
[19:56:33] [PASSED] 20.04 Xe2_LPG
[19:56:33] [PASSED] 30.00 Xe3_LPG
[19:56:33] [PASSED] 30.01 Xe3_LPG
[19:56:33] [PASSED] 30.03 Xe3_LPG
[19:56:33] [PASSED] 30.04 Xe3_LPG
[19:56:33] [PASSED] 30.05 Xe3_LPG
[19:56:33] [PASSED] 35.10 Xe3p_LPG
[19:56:33] [PASSED] 35.11 Xe3p_XPC
[19:56:33] ================ [PASSED] check_graphics_ip ================
[19:56:33] ===================== check_media_ip ======================
[19:56:33] [PASSED] 12.00 Xe_M
[19:56:33] [PASSED] 12.55 Xe_HPM
[19:56:33] [PASSED] 13.00 Xe_LPM+
[19:56:33] [PASSED] 13.01 Xe2_HPM
[19:56:33] [PASSED] 20.00 Xe2_LPM
[19:56:33] [PASSED] 30.00 Xe3_LPM
[19:56:33] [PASSED] 30.02 Xe3_LPM
[19:56:33] [PASSED] 35.00 Xe3p_LPM
[19:56:33] [PASSED] 35.03 Xe3p_HPM
[19:56:33] ================= [PASSED] check_media_ip ==================
[19:56:33] =================== check_platform_desc ===================
[19:56:33] [PASSED] 0x9A60 (TIGERLAKE)
[19:56:33] [PASSED] 0x9A68 (TIGERLAKE)
[19:56:33] [PASSED] 0x9A70 (TIGERLAKE)
[19:56:33] [PASSED] 0x9A40 (TIGERLAKE)
[19:56:33] [PASSED] 0x9A49 (TIGERLAKE)
[19:56:33] [PASSED] 0x9A59 (TIGERLAKE)
[19:56:33] [PASSED] 0x9A78 (TIGERLAKE)
[19:56:33] [PASSED] 0x9AC0 (TIGERLAKE)
[19:56:33] [PASSED] 0x9AC9 (TIGERLAKE)
[19:56:33] [PASSED] 0x9AD9 (TIGERLAKE)
[19:56:33] [PASSED] 0x9AF8 (TIGERLAKE)
[19:56:33] [PASSED] 0x4C80 (ROCKETLAKE)
[19:56:33] [PASSED] 0x4C8A (ROCKETLAKE)
[19:56:33] [PASSED] 0x4C8B (ROCKETLAKE)
[19:56:33] [PASSED] 0x4C8C (ROCKETLAKE)
[19:56:33] [PASSED] 0x4C90 (ROCKETLAKE)
[19:56:33] [PASSED] 0x4C9A (ROCKETLAKE)
[19:56:33] [PASSED] 0x4680 (ALDERLAKE_S)
[19:56:33] [PASSED] 0x4682 (ALDERLAKE_S)
[19:56:33] [PASSED] 0x4688 (ALDERLAKE_S)
[19:56:33] [PASSED] 0x468A (ALDERLAKE_S)
[19:56:33] [PASSED] 0x468B (ALDERLAKE_S)
[19:56:33] [PASSED] 0x4690 (ALDERLAKE_S)
[19:56:33] [PASSED] 0x4692 (ALDERLAKE_S)
[19:56:33] [PASSED] 0x4693 (ALDERLAKE_S)
[19:56:33] [PASSED] 0x46A0 (ALDERLAKE_P)
[19:56:33] [PASSED] 0x46A1 (ALDERLAKE_P)
[19:56:33] [PASSED] 0x46A2 (ALDERLAKE_P)
[19:56:33] [PASSED] 0x46A3 (ALDERLAKE_P)
[19:56:33] [PASSED] 0x46A6 (ALDERLAKE_P)
[19:56:33] [PASSED] 0x46A8 (ALDERLAKE_P)
[19:56:33] [PASSED] 0x46AA (ALDERLAKE_P)
[19:56:33] [PASSED] 0x462A (ALDERLAKE_P)
[19:56:33] [PASSED] 0x4626 (ALDERLAKE_P)
[19:56:33] [PASSED] 0x4628 (ALDERLAKE_P)
[19:56:33] [PASSED] 0x46B0 (ALDERLAKE_P)
[19:56:33] [PASSED] 0x46B1 (ALDERLAKE_P)
[19:56:33] [PASSED] 0x46B2 (ALDERLAKE_P)
[19:56:33] [PASSED] 0x46B3 (ALDERLAKE_P)
[19:56:33] [PASSED] 0x46C0 (ALDERLAKE_P)
[19:56:33] [PASSED] 0x46C1 (ALDERLAKE_P)
[19:56:33] [PASSED] 0x46C2 (ALDERLAKE_P)
[19:56:33] [PASSED] 0x46C3 (ALDERLAKE_P)
[19:56:33] [PASSED] 0x46D0 (ALDERLAKE_N)
[19:56:33] [PASSED] 0x46D1 (ALDERLAKE_N)
[19:56:33] [PASSED] 0x46D2 (ALDERLAKE_N)
[19:56:33] [PASSED] 0x46D3 (ALDERLAKE_N)
[19:56:33] [PASSED] 0x46D4 (ALDERLAKE_N)
[19:56:33] [PASSED] 0xA721 (ALDERLAKE_P)
[19:56:33] [PASSED] 0xA7A1 (ALDERLAKE_P)
[19:56:33] [PASSED] 0xA7A9 (ALDERLAKE_P)
[19:56:33] [PASSED] 0xA7AC (ALDERLAKE_P)
[19:56:33] [PASSED] 0xA7AD (ALDERLAKE_P)
[19:56:33] [PASSED] 0xA720 (ALDERLAKE_P)
[19:56:33] [PASSED] 0xA7A0 (ALDERLAKE_P)
[19:56:33] [PASSED] 0xA7A8 (ALDERLAKE_P)
[19:56:33] [PASSED] 0xA7AA (ALDERLAKE_P)
[19:56:33] [PASSED] 0xA7AB (ALDERLAKE_P)
[19:56:33] [PASSED] 0xA780 (ALDERLAKE_S)
[19:56:33] [PASSED] 0xA781 (ALDERLAKE_S)
[19:56:33] [PASSED] 0xA782 (ALDERLAKE_S)
[19:56:33] [PASSED] 0xA783 (ALDERLAKE_S)
[19:56:33] [PASSED] 0xA788 (ALDERLAKE_S)
[19:56:33] [PASSED] 0xA789 (ALDERLAKE_S)
[19:56:33] [PASSED] 0xA78A (ALDERLAKE_S)
[19:56:33] [PASSED] 0xA78B (ALDERLAKE_S)
[19:56:33] [PASSED] 0x4905 (DG1)
[19:56:33] [PASSED] 0x4906 (DG1)
[19:56:33] [PASSED] 0x4907 (DG1)
[19:56:33] [PASSED] 0x4908 (DG1)
[19:56:33] [PASSED] 0x4909 (DG1)
[19:56:33] [PASSED] 0x56C0 (DG2)
[19:56:33] [PASSED] 0x56C2 (DG2)
[19:56:33] [PASSED] 0x56C1 (DG2)
[19:56:33] [PASSED] 0x7D51 (METEORLAKE)
[19:56:33] [PASSED] 0x7DD1 (METEORLAKE)
[19:56:33] [PASSED] 0x7D41 (METEORLAKE)
[19:56:33] [PASSED] 0x7D67 (METEORLAKE)
[19:56:33] [PASSED] 0xB640 (METEORLAKE)
[19:56:33] [PASSED] 0x56A0 (DG2)
[19:56:33] [PASSED] 0x56A1 (DG2)
[19:56:33] [PASSED] 0x56A2 (DG2)
[19:56:33] [PASSED] 0x56BE (DG2)
[19:56:33] [PASSED] 0x56BF (DG2)
[19:56:33] [PASSED] 0x5690 (DG2)
[19:56:33] [PASSED] 0x5691 (DG2)
[19:56:33] [PASSED] 0x5692 (DG2)
[19:56:33] [PASSED] 0x56A5 (DG2)
[19:56:33] [PASSED] 0x56A6 (DG2)
[19:56:33] [PASSED] 0x56B0 (DG2)
[19:56:33] [PASSED] 0x56B1 (DG2)
[19:56:33] [PASSED] 0x56BA (DG2)
[19:56:33] [PASSED] 0x56BB (DG2)
[19:56:33] [PASSED] 0x56BC (DG2)
[19:56:33] [PASSED] 0x56BD (DG2)
[19:56:33] [PASSED] 0x5693 (DG2)
[19:56:33] [PASSED] 0x5694 (DG2)
[19:56:33] [PASSED] 0x5695 (DG2)
[19:56:33] [PASSED] 0x56A3 (DG2)
[19:56:33] [PASSED] 0x56A4 (DG2)
[19:56:33] [PASSED] 0x56B2 (DG2)
[19:56:33] [PASSED] 0x56B3 (DG2)
[19:56:33] [PASSED] 0x5696 (DG2)
[19:56:33] [PASSED] 0x5697 (DG2)
[19:56:33] [PASSED] 0xB69 (PVC)
[19:56:33] [PASSED] 0xB6E (PVC)
[19:56:33] [PASSED] 0xBD4 (PVC)
[19:56:33] [PASSED] 0xBD5 (PVC)
[19:56:33] [PASSED] 0xBD6 (PVC)
[19:56:33] [PASSED] 0xBD7 (PVC)
[19:56:33] [PASSED] 0xBD8 (PVC)
[19:56:33] [PASSED] 0xBD9 (PVC)
[19:56:33] [PASSED] 0xBDA (PVC)
[19:56:33] [PASSED] 0xBDB (PVC)
[19:56:33] [PASSED] 0xBE0 (PVC)
[19:56:33] [PASSED] 0xBE1 (PVC)
[19:56:33] [PASSED] 0xBE5 (PVC)
[19:56:33] [PASSED] 0x7D40 (METEORLAKE)
[19:56:33] [PASSED] 0x7D45 (METEORLAKE)
[19:56:33] [PASSED] 0x7D55 (METEORLAKE)
[19:56:33] [PASSED] 0x7D60 (METEORLAKE)
[19:56:33] [PASSED] 0x7DD5 (METEORLAKE)
[19:56:33] [PASSED] 0x6420 (LUNARLAKE)
[19:56:33] [PASSED] 0x64A0 (LUNARLAKE)
[19:56:33] [PASSED] 0x64B0 (LUNARLAKE)
[19:56:33] [PASSED] 0xE202 (BATTLEMAGE)
[19:56:33] [PASSED] 0xE209 (BATTLEMAGE)
[19:56:33] [PASSED] 0xE20B (BATTLEMAGE)
[19:56:33] [PASSED] 0xE20C (BATTLEMAGE)
[19:56:33] [PASSED] 0xE20D (BATTLEMAGE)
[19:56:33] [PASSED] 0xE210 (BATTLEMAGE)
[19:56:33] [PASSED] 0xE211 (BATTLEMAGE)
[19:56:33] [PASSED] 0xE212 (BATTLEMAGE)
[19:56:33] [PASSED] 0xE216 (BATTLEMAGE)
[19:56:33] [PASSED] 0xE220 (BATTLEMAGE)
[19:56:33] [PASSED] 0xE221 (BATTLEMAGE)
[19:56:33] [PASSED] 0xE222 (BATTLEMAGE)
[19:56:33] [PASSED] 0xE223 (BATTLEMAGE)
[19:56:33] [PASSED] 0xB080 (PANTHERLAKE)
[19:56:33] [PASSED] 0xB081 (PANTHERLAKE)
[19:56:33] [PASSED] 0xB082 (PANTHERLAKE)
[19:56:33] [PASSED] 0xB083 (PANTHERLAKE)
[19:56:33] [PASSED] 0xB084 (PANTHERLAKE)
[19:56:33] [PASSED] 0xB085 (PANTHERLAKE)
[19:56:33] [PASSED] 0xB086 (PANTHERLAKE)
[19:56:33] [PASSED] 0xB087 (PANTHERLAKE)
[19:56:33] [PASSED] 0xB08F (PANTHERLAKE)
[19:56:33] [PASSED] 0xB090 (PANTHERLAKE)
[19:56:33] [PASSED] 0xB0A0 (PANTHERLAKE)
[19:56:33] [PASSED] 0xB0B0 (PANTHERLAKE)
[19:56:33] [PASSED] 0xFD80 (PANTHERLAKE)
[19:56:33] [PASSED] 0xFD81 (PANTHERLAKE)
[19:56:33] [PASSED] 0xD740 (NOVALAKE_S)
[19:56:33] [PASSED] 0xD741 (NOVALAKE_S)
[19:56:33] [PASSED] 0xD742 (NOVALAKE_S)
[19:56:33] [PASSED] 0xD743 (NOVALAKE_S)
[19:56:33] [PASSED] 0xD744 (NOVALAKE_S)
[19:56:33] [PASSED] 0xD745 (NOVALAKE_S)
[19:56:33] [PASSED] 0x674C (CRESCENTISLAND)
[19:56:33] [PASSED] 0xD750 (NOVALAKE_P)
[19:56:33] [PASSED] 0xD751 (NOVALAKE_P)
[19:56:33] [PASSED] 0xD752 (NOVALAKE_P)
[19:56:33] [PASSED] 0xD753 (NOVALAKE_P)
[19:56:33] [PASSED] 0xD754 (NOVALAKE_P)
[19:56:33] [PASSED] 0xD755 (NOVALAKE_P)
[19:56:33] [PASSED] 0xD756 (NOVALAKE_P)
[19:56:33] [PASSED] 0xD757 (NOVALAKE_P)
[19:56:33] [PASSED] 0xD75F (NOVALAKE_P)
[19:56:33] =============== [PASSED] check_platform_desc ===============
[19:56:33] ===================== [PASSED] xe_pci ======================
[19:56:33] =================== xe_rtp (2 subtests) ====================
[19:56:33] =============== xe_rtp_process_to_sr_tests ================
[19:56:33] [PASSED] coalesce-same-reg
[19:56:33] [PASSED] no-match-no-add
[19:56:33] [PASSED] match-or
[19:56:33] [PASSED] match-or-xfail
[19:56:33] [PASSED] no-match-no-add-multiple-rules
[19:56:33] [PASSED] two-regs-two-entries
[19:56:33] [PASSED] clr-one-set-other
[19:56:33] [PASSED] set-field
[19:56:33] [PASSED] conflict-duplicate
stty: 'standard input': Inappropriate ioctl for device
[19:56:33] [PASSED] conflict-not-disjoint
[19:56:33] [PASSED] conflict-reg-type
[19:56:33] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[19:56:33] ================== xe_rtp_process_tests ===================
[19:56:33] [PASSED] active1
[19:56:33] [PASSED] active2
[19:56:33] [PASSED] active-inactive
[19:56:33] [PASSED] inactive-active
[19:56:33] [PASSED] inactive-1st_or_active-inactive
[19:56:33] [PASSED] inactive-2nd_or_active-inactive
[19:56:33] [PASSED] inactive-last_or_active-inactive
[19:56:33] [PASSED] inactive-no_or_active-inactive
[19:56:33] ============== [PASSED] xe_rtp_process_tests ===============
[19:56:33] ===================== [PASSED] xe_rtp ======================
[19:56:33] ==================== xe_wa (1 subtest) =====================
[19:56:33] ======================== xe_wa_gt =========================
[19:56:33] [PASSED] TIGERLAKE B0
[19:56:33] [PASSED] DG1 A0
[19:56:33] [PASSED] DG1 B0
[19:56:33] [PASSED] ALDERLAKE_S A0
[19:56:33] [PASSED] ALDERLAKE_S B0
[19:56:33] [PASSED] ALDERLAKE_S C0
[19:56:33] [PASSED] ALDERLAKE_S D0
[19:56:33] [PASSED] ALDERLAKE_P A0
[19:56:33] [PASSED] ALDERLAKE_P B0
[19:56:33] [PASSED] ALDERLAKE_P C0
[19:56:33] [PASSED] ALDERLAKE_S RPLS D0
[19:56:33] [PASSED] ALDERLAKE_P RPLU E0
[19:56:33] [PASSED] DG2 G10 C0
[19:56:33] [PASSED] DG2 G11 B1
[19:56:33] [PASSED] DG2 G12 A1
[19:56:33] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[19:56:33] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[19:56:33] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[19:56:33] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[19:56:33] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[19:56:33] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[19:56:33] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[19:56:33] ==================== [PASSED] xe_wa_gt =====================
[19:56:33] ====================== [PASSED] xe_wa ======================
[19:56:33] ============================================================
[19:56:33] Testing complete. Ran 597 tests: passed: 579, skipped: 18
[19:56:33] Elapsed time: 35.435s total, 4.279s configuring, 30.539s building, 0.603s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[19:56:33] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[19:56:34] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[19:56:59] Starting KUnit Kernel (1/1)...
[19:56:59] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[19:56:59] ============ drm_test_pick_cmdline (2 subtests) ============
[19:56:59] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[19:56:59] =============== drm_test_pick_cmdline_named ===============
[19:56:59] [PASSED] NTSC
[19:56:59] [PASSED] NTSC-J
[19:56:59] [PASSED] PAL
[19:56:59] [PASSED] PAL-M
[19:56:59] =========== [PASSED] drm_test_pick_cmdline_named ===========
[19:56:59] ============== [PASSED] drm_test_pick_cmdline ==============
[19:56:59] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[19:56:59] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[19:56:59] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[19:56:59] =========== drm_validate_clone_mode (2 subtests) ===========
[19:56:59] ============== drm_test_check_in_clone_mode ===============
[19:56:59] [PASSED] in_clone_mode
[19:56:59] [PASSED] not_in_clone_mode
[19:56:59] ========== [PASSED] drm_test_check_in_clone_mode ===========
[19:56:59] =============== drm_test_check_valid_clones ===============
[19:56:59] [PASSED] not_in_clone_mode
[19:56:59] [PASSED] valid_clone
[19:56:59] [PASSED] invalid_clone
[19:56:59] =========== [PASSED] drm_test_check_valid_clones ===========
[19:56:59] ============= [PASSED] drm_validate_clone_mode =============
[19:56:59] ============= drm_validate_modeset (1 subtest) =============
[19:56:59] [PASSED] drm_test_check_connector_changed_modeset
[19:56:59] ============== [PASSED] drm_validate_modeset ===============
[19:56:59] ====== drm_test_bridge_get_current_state (2 subtests) ======
[19:56:59] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[19:56:59] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[19:56:59] ======== [PASSED] drm_test_bridge_get_current_state ========
[19:56:59] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[19:56:59] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[19:56:59] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[19:56:59] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[19:56:59] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[19:56:59] ============== drm_bridge_alloc (2 subtests) ===============
[19:56:59] [PASSED] drm_test_drm_bridge_alloc_basic
[19:56:59] [PASSED] drm_test_drm_bridge_alloc_get_put
[19:56:59] ================ [PASSED] drm_bridge_alloc =================
[19:56:59] ============= drm_cmdline_parser (40 subtests) =============
[19:56:59] [PASSED] drm_test_cmdline_force_d_only
[19:56:59] [PASSED] drm_test_cmdline_force_D_only_dvi
[19:56:59] [PASSED] drm_test_cmdline_force_D_only_hdmi
[19:56:59] [PASSED] drm_test_cmdline_force_D_only_not_digital
[19:56:59] [PASSED] drm_test_cmdline_force_e_only
[19:56:59] [PASSED] drm_test_cmdline_res
[19:56:59] [PASSED] drm_test_cmdline_res_vesa
[19:56:59] [PASSED] drm_test_cmdline_res_vesa_rblank
[19:56:59] [PASSED] drm_test_cmdline_res_rblank
[19:56:59] [PASSED] drm_test_cmdline_res_bpp
[19:56:59] [PASSED] drm_test_cmdline_res_refresh
[19:56:59] [PASSED] drm_test_cmdline_res_bpp_refresh
[19:56:59] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[19:56:59] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[19:56:59] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[19:56:59] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[19:56:59] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[19:56:59] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[19:56:59] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[19:56:59] [PASSED] drm_test_cmdline_res_margins_force_on
[19:56:59] [PASSED] drm_test_cmdline_res_vesa_margins
[19:56:59] [PASSED] drm_test_cmdline_name
[19:56:59] [PASSED] drm_test_cmdline_name_bpp
[19:56:59] [PASSED] drm_test_cmdline_name_option
[19:56:59] [PASSED] drm_test_cmdline_name_bpp_option
[19:56:59] [PASSED] drm_test_cmdline_rotate_0
[19:56:59] [PASSED] drm_test_cmdline_rotate_90
[19:56:59] [PASSED] drm_test_cmdline_rotate_180
[19:56:59] [PASSED] drm_test_cmdline_rotate_270
[19:56:59] [PASSED] drm_test_cmdline_hmirror
[19:56:59] [PASSED] drm_test_cmdline_vmirror
[19:56:59] [PASSED] drm_test_cmdline_margin_options
[19:56:59] [PASSED] drm_test_cmdline_multiple_options
[19:56:59] [PASSED] drm_test_cmdline_bpp_extra_and_option
[19:56:59] [PASSED] drm_test_cmdline_extra_and_option
[19:56:59] [PASSED] drm_test_cmdline_freestanding_options
[19:56:59] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[19:56:59] [PASSED] drm_test_cmdline_panel_orientation
[19:56:59] ================ drm_test_cmdline_invalid =================
[19:56:59] [PASSED] margin_only
[19:56:59] [PASSED] interlace_only
[19:56:59] [PASSED] res_missing_x
[19:56:59] [PASSED] res_missing_y
[19:56:59] [PASSED] res_bad_y
[19:56:59] [PASSED] res_missing_y_bpp
[19:56:59] [PASSED] res_bad_bpp
[19:56:59] [PASSED] res_bad_refresh
[19:56:59] [PASSED] res_bpp_refresh_force_on_off
[19:56:59] [PASSED] res_invalid_mode
[19:56:59] [PASSED] res_bpp_wrong_place_mode
[19:56:59] [PASSED] name_bpp_refresh
[19:56:59] [PASSED] name_refresh
[19:56:59] [PASSED] name_refresh_wrong_mode
[19:56:59] [PASSED] name_refresh_invalid_mode
[19:56:59] [PASSED] rotate_multiple
[19:56:59] [PASSED] rotate_invalid_val
[19:56:59] [PASSED] rotate_truncated
[19:56:59] [PASSED] invalid_option
[19:56:59] [PASSED] invalid_tv_option
[19:56:59] [PASSED] truncated_tv_option
[19:56:59] ============ [PASSED] drm_test_cmdline_invalid =============
[19:56:59] =============== drm_test_cmdline_tv_options ===============
[19:56:59] [PASSED] NTSC
[19:56:59] [PASSED] NTSC_443
[19:56:59] [PASSED] NTSC_J
[19:56:59] [PASSED] PAL
[19:56:59] [PASSED] PAL_M
[19:56:59] [PASSED] PAL_N
[19:56:59] [PASSED] SECAM
[19:56:59] [PASSED] MONO_525
[19:56:59] [PASSED] MONO_625
[19:56:59] =========== [PASSED] drm_test_cmdline_tv_options ===========
[19:56:59] =============== [PASSED] drm_cmdline_parser ================
[19:56:59] ========== drmm_connector_hdmi_init (20 subtests) ==========
[19:56:59] [PASSED] drm_test_connector_hdmi_init_valid
[19:56:59] [PASSED] drm_test_connector_hdmi_init_bpc_8
[19:56:59] [PASSED] drm_test_connector_hdmi_init_bpc_10
[19:56:59] [PASSED] drm_test_connector_hdmi_init_bpc_12
[19:56:59] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[19:56:59] [PASSED] drm_test_connector_hdmi_init_bpc_null
[19:56:59] [PASSED] drm_test_connector_hdmi_init_formats_empty
[19:56:59] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[19:56:59] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[19:56:59] [PASSED] supported_formats=0x9 yuv420_allowed=1
[19:56:59] [PASSED] supported_formats=0x9 yuv420_allowed=0
[19:56:59] [PASSED] supported_formats=0x3 yuv420_allowed=1
[19:56:59] [PASSED] supported_formats=0x3 yuv420_allowed=0
[19:56:59] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[19:56:59] [PASSED] drm_test_connector_hdmi_init_null_ddc
[19:56:59] [PASSED] drm_test_connector_hdmi_init_null_product
[19:56:59] [PASSED] drm_test_connector_hdmi_init_null_vendor
[19:56:59] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[19:56:59] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[19:56:59] [PASSED] drm_test_connector_hdmi_init_product_valid
[19:56:59] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[19:56:59] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[19:56:59] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[19:56:59] ========= drm_test_connector_hdmi_init_type_valid =========
[19:56:59] [PASSED] HDMI-A
[19:56:59] [PASSED] HDMI-B
[19:56:59] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[19:56:59] ======== drm_test_connector_hdmi_init_type_invalid ========
[19:56:59] [PASSED] Unknown
[19:56:59] [PASSED] VGA
[19:56:59] [PASSED] DVI-I
[19:56:59] [PASSED] DVI-D
[19:56:59] [PASSED] DVI-A
[19:56:59] [PASSED] Composite
[19:56:59] [PASSED] SVIDEO
[19:56:59] [PASSED] LVDS
[19:56:59] [PASSED] Component
[19:56:59] [PASSED] DIN
[19:56:59] [PASSED] DP
[19:56:59] [PASSED] TV
[19:56:59] [PASSED] eDP
[19:56:59] [PASSED] Virtual
[19:56:59] [PASSED] DSI
[19:56:59] [PASSED] DPI
[19:56:59] [PASSED] Writeback
[19:56:59] [PASSED] SPI
[19:56:59] [PASSED] USB
[19:56:59] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[19:56:59] ============ [PASSED] drmm_connector_hdmi_init =============
[19:56:59] ============= drmm_connector_init (3 subtests) =============
[19:56:59] [PASSED] drm_test_drmm_connector_init
[19:56:59] [PASSED] drm_test_drmm_connector_init_null_ddc
[19:56:59] ========= drm_test_drmm_connector_init_type_valid =========
[19:56:59] [PASSED] Unknown
[19:56:59] [PASSED] VGA
[19:56:59] [PASSED] DVI-I
[19:56:59] [PASSED] DVI-D
[19:56:59] [PASSED] DVI-A
[19:56:59] [PASSED] Composite
[19:56:59] [PASSED] SVIDEO
[19:56:59] [PASSED] LVDS
[19:56:59] [PASSED] Component
[19:56:59] [PASSED] DIN
[19:56:59] [PASSED] DP
[19:56:59] [PASSED] HDMI-A
[19:56:59] [PASSED] HDMI-B
[19:56:59] [PASSED] TV
[19:56:59] [PASSED] eDP
[19:56:59] [PASSED] Virtual
[19:56:59] [PASSED] DSI
[19:56:59] [PASSED] DPI
[19:56:59] [PASSED] Writeback
[19:56:59] [PASSED] SPI
[19:56:59] [PASSED] USB
[19:56:59] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[19:56:59] =============== [PASSED] drmm_connector_init ===============
[19:56:59] ========= drm_connector_dynamic_init (6 subtests) ==========
[19:56:59] [PASSED] drm_test_drm_connector_dynamic_init
[19:56:59] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[19:56:59] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[19:56:59] [PASSED] drm_test_drm_connector_dynamic_init_properties
[19:56:59] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[19:56:59] [PASSED] Unknown
[19:56:59] [PASSED] VGA
[19:56:59] [PASSED] DVI-I
[19:56:59] [PASSED] DVI-D
[19:56:59] [PASSED] DVI-A
[19:56:59] [PASSED] Composite
[19:56:59] [PASSED] SVIDEO
[19:56:59] [PASSED] LVDS
[19:56:59] [PASSED] Component
[19:56:59] [PASSED] DIN
[19:56:59] [PASSED] DP
[19:56:59] [PASSED] HDMI-A
[19:56:59] [PASSED] HDMI-B
[19:56:59] [PASSED] TV
[19:56:59] [PASSED] eDP
[19:56:59] [PASSED] Virtual
[19:56:59] [PASSED] DSI
[19:56:59] [PASSED] DPI
[19:56:59] [PASSED] Writeback
[19:56:59] [PASSED] SPI
[19:56:59] [PASSED] USB
[19:56:59] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[19:56:59] ======== drm_test_drm_connector_dynamic_init_name =========
[19:56:59] [PASSED] Unknown
[19:56:59] [PASSED] VGA
[19:56:59] [PASSED] DVI-I
[19:56:59] [PASSED] DVI-D
[19:56:59] [PASSED] DVI-A
[19:56:59] [PASSED] Composite
[19:56:59] [PASSED] SVIDEO
[19:56:59] [PASSED] LVDS
[19:56:59] [PASSED] Component
[19:56:59] [PASSED] DIN
[19:56:59] [PASSED] DP
[19:56:59] [PASSED] HDMI-A
[19:56:59] [PASSED] HDMI-B
[19:56:59] [PASSED] TV
[19:56:59] [PASSED] eDP
[19:56:59] [PASSED] Virtual
[19:56:59] [PASSED] DSI
[19:56:59] [PASSED] DPI
[19:56:59] [PASSED] Writeback
[19:56:59] [PASSED] SPI
[19:56:59] [PASSED] USB
[19:56:59] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[19:56:59] =========== [PASSED] drm_connector_dynamic_init ============
[19:56:59] ==== drm_connector_dynamic_register_early (4 subtests) =====
[19:56:59] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[19:56:59] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[19:56:59] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[19:56:59] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[19:56:59] ====== [PASSED] drm_connector_dynamic_register_early =======
[19:56:59] ======= drm_connector_dynamic_register (7 subtests) ========
[19:56:59] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[19:56:59] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[19:56:59] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[19:56:59] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[19:56:59] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[19:56:59] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[19:56:59] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[19:56:59] ========= [PASSED] drm_connector_dynamic_register ==========
[19:56:59] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[19:56:59] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[19:56:59] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[19:56:59] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[19:56:59] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[19:56:59] ========== drm_test_get_tv_mode_from_name_valid ===========
[19:56:59] [PASSED] NTSC
[19:56:59] [PASSED] NTSC-443
[19:56:59] [PASSED] NTSC-J
[19:56:59] [PASSED] PAL
[19:56:59] [PASSED] PAL-M
[19:56:59] [PASSED] PAL-N
[19:56:59] [PASSED] SECAM
[19:56:59] [PASSED] Mono
[19:56:59] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[19:56:59] [PASSED] drm_test_get_tv_mode_from_name_truncated
[19:56:59] ============ [PASSED] drm_get_tv_mode_from_name ============
[19:56:59] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[19:56:59] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[19:56:59] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[19:56:59] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[19:56:59] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[19:56:59] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[19:56:59] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[19:56:59] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[19:56:59] [PASSED] VIC 96
[19:56:59] [PASSED] VIC 97
[19:56:59] [PASSED] VIC 101
[19:56:59] [PASSED] VIC 102
[19:56:59] [PASSED] VIC 106
[19:56:59] [PASSED] VIC 107
[19:56:59] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[19:56:59] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[19:56:59] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[19:56:59] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[19:56:59] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[19:56:59] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[19:56:59] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[19:56:59] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[19:56:59] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[19:56:59] [PASSED] Automatic
[19:56:59] [PASSED] Full
[19:56:59] [PASSED] Limited 16:235
[19:56:59] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[19:56:59] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[19:56:59] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[19:56:59] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[19:56:59] === drm_test_drm_hdmi_connector_get_output_format_name ====
[19:56:59] [PASSED] RGB
[19:56:59] [PASSED] YUV 4:2:0
[19:56:59] [PASSED] YUV 4:2:2
[19:56:59] [PASSED] YUV 4:4:4
[19:56:59] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[19:56:59] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[19:56:59] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[19:56:59] ============= drm_damage_helper (21 subtests) ==============
[19:56:59] [PASSED] drm_test_damage_iter_no_damage
[19:56:59] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[19:56:59] [PASSED] drm_test_damage_iter_no_damage_src_moved
[19:56:59] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[19:56:59] [PASSED] drm_test_damage_iter_no_damage_not_visible
[19:56:59] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[19:56:59] [PASSED] drm_test_damage_iter_no_damage_no_fb
[19:56:59] [PASSED] drm_test_damage_iter_simple_damage
[19:56:59] [PASSED] drm_test_damage_iter_single_damage
[19:56:59] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[19:56:59] [PASSED] drm_test_damage_iter_single_damage_outside_src
[19:56:59] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[19:56:59] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[19:56:59] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[19:56:59] [PASSED] drm_test_damage_iter_single_damage_src_moved
[19:56:59] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[19:56:59] [PASSED] drm_test_damage_iter_damage
[19:56:59] [PASSED] drm_test_damage_iter_damage_one_intersect
[19:56:59] [PASSED] drm_test_damage_iter_damage_one_outside
[19:56:59] [PASSED] drm_test_damage_iter_damage_src_moved
[19:56:59] [PASSED] drm_test_damage_iter_damage_not_visible
[19:56:59] ================ [PASSED] drm_damage_helper ================
[19:56:59] ============== drm_dp_mst_helper (3 subtests) ==============
[19:56:59] ============== drm_test_dp_mst_calc_pbn_mode ==============
[19:56:59] [PASSED] Clock 154000 BPP 30 DSC disabled
[19:56:59] [PASSED] Clock 234000 BPP 30 DSC disabled
[19:56:59] [PASSED] Clock 297000 BPP 24 DSC disabled
[19:56:59] [PASSED] Clock 332880 BPP 24 DSC enabled
[19:56:59] [PASSED] Clock 324540 BPP 24 DSC enabled
[19:56:59] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[19:56:59] ============== drm_test_dp_mst_calc_pbn_div ===============
[19:56:59] [PASSED] Link rate 2000000 lane count 4
[19:56:59] [PASSED] Link rate 2000000 lane count 2
[19:56:59] [PASSED] Link rate 2000000 lane count 1
[19:56:59] [PASSED] Link rate 1350000 lane count 4
[19:56:59] [PASSED] Link rate 1350000 lane count 2
[19:56:59] [PASSED] Link rate 1350000 lane count 1
[19:56:59] [PASSED] Link rate 1000000 lane count 4
[19:56:59] [PASSED] Link rate 1000000 lane count 2
[19:56:59] [PASSED] Link rate 1000000 lane count 1
[19:56:59] [PASSED] Link rate 810000 lane count 4
[19:56:59] [PASSED] Link rate 810000 lane count 2
[19:56:59] [PASSED] Link rate 810000 lane count 1
[19:56:59] [PASSED] Link rate 540000 lane count 4
[19:56:59] [PASSED] Link rate 540000 lane count 2
[19:56:59] [PASSED] Link rate 540000 lane count 1
[19:56:59] [PASSED] Link rate 270000 lane count 4
[19:56:59] [PASSED] Link rate 270000 lane count 2
[19:56:59] [PASSED] Link rate 270000 lane count 1
[19:56:59] [PASSED] Link rate 162000 lane count 4
[19:56:59] [PASSED] Link rate 162000 lane count 2
[19:56:59] [PASSED] Link rate 162000 lane count 1
[19:56:59] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[19:56:59] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[19:56:59] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[19:56:59] [PASSED] DP_POWER_UP_PHY with port number
[19:56:59] [PASSED] DP_POWER_DOWN_PHY with port number
[19:56:59] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[19:56:59] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[19:56:59] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[19:56:59] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[19:56:59] [PASSED] DP_QUERY_PAYLOAD with port number
[19:56:59] [PASSED] DP_QUERY_PAYLOAD with VCPI
[19:56:59] [PASSED] DP_REMOTE_DPCD_READ with port number
[19:56:59] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[19:56:59] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[19:56:59] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[19:56:59] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[19:56:59] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[19:56:59] [PASSED] DP_REMOTE_I2C_READ with port number
[19:56:59] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[19:56:59] [PASSED] DP_REMOTE_I2C_READ with transactions array
[19:56:59] [PASSED] DP_REMOTE_I2C_WRITE with port number
[19:56:59] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[19:56:59] [PASSED] DP_REMOTE_I2C_WRITE with data array
[19:56:59] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[19:56:59] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[19:56:59] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[19:56:59] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[19:56:59] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[19:56:59] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[19:56:59] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[19:56:59] ================ [PASSED] drm_dp_mst_helper ================
[19:56:59] ================== drm_exec (7 subtests) ===================
[19:56:59] [PASSED] sanitycheck
[19:56:59] [PASSED] test_lock
[19:56:59] [PASSED] test_lock_unlock
[19:56:59] [PASSED] test_duplicates
[19:56:59] [PASSED] test_prepare
[19:56:59] [PASSED] test_prepare_array
[19:56:59] [PASSED] test_multiple_loops
[19:56:59] ==================== [PASSED] drm_exec =====================
[19:56:59] =========== drm_format_helper_test (17 subtests) ===========
[19:56:59] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[19:56:59] [PASSED] single_pixel_source_buffer
[19:56:59] [PASSED] single_pixel_clip_rectangle
[19:56:59] [PASSED] well_known_colors
[19:56:59] [PASSED] destination_pitch
[19:56:59] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[19:56:59] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[19:56:59] [PASSED] single_pixel_source_buffer
[19:56:59] [PASSED] single_pixel_clip_rectangle
[19:56:59] [PASSED] well_known_colors
[19:56:59] [PASSED] destination_pitch
[19:56:59] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[19:56:59] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[19:56:59] [PASSED] single_pixel_source_buffer
[19:56:59] [PASSED] single_pixel_clip_rectangle
[19:56:59] [PASSED] well_known_colors
[19:56:59] [PASSED] destination_pitch
[19:56:59] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[19:56:59] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[19:56:59] [PASSED] single_pixel_source_buffer
[19:56:59] [PASSED] single_pixel_clip_rectangle
[19:56:59] [PASSED] well_known_colors
[19:56:59] [PASSED] destination_pitch
[19:56:59] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[19:56:59] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[19:56:59] [PASSED] single_pixel_source_buffer
[19:56:59] [PASSED] single_pixel_clip_rectangle
[19:56:59] [PASSED] well_known_colors
[19:56:59] [PASSED] destination_pitch
[19:56:59] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[19:56:59] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[19:56:59] [PASSED] single_pixel_source_buffer
[19:56:59] [PASSED] single_pixel_clip_rectangle
[19:56:59] [PASSED] well_known_colors
[19:56:59] [PASSED] destination_pitch
[19:56:59] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[19:56:59] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[19:56:59] [PASSED] single_pixel_source_buffer
[19:56:59] [PASSED] single_pixel_clip_rectangle
[19:56:59] [PASSED] well_known_colors
[19:56:59] [PASSED] destination_pitch
[19:56:59] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[19:56:59] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[19:56:59] [PASSED] single_pixel_source_buffer
[19:56:59] [PASSED] single_pixel_clip_rectangle
[19:56:59] [PASSED] well_known_colors
[19:56:59] [PASSED] destination_pitch
[19:56:59] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[19:56:59] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[19:56:59] [PASSED] single_pixel_source_buffer
[19:56:59] [PASSED] single_pixel_clip_rectangle
[19:56:59] [PASSED] well_known_colors
[19:56:59] [PASSED] destination_pitch
[19:56:59] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[19:56:59] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[19:56:59] [PASSED] single_pixel_source_buffer
[19:56:59] [PASSED] single_pixel_clip_rectangle
[19:56:59] [PASSED] well_known_colors
[19:56:59] [PASSED] destination_pitch
[19:56:59] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[19:56:59] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[19:56:59] [PASSED] single_pixel_source_buffer
[19:56:59] [PASSED] single_pixel_clip_rectangle
[19:56:59] [PASSED] well_known_colors
[19:56:59] [PASSED] destination_pitch
[19:56:59] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[19:56:59] ============== drm_test_fb_xrgb8888_to_mono ===============
[19:56:59] [PASSED] single_pixel_source_buffer
[19:56:59] [PASSED] single_pixel_clip_rectangle
[19:56:59] [PASSED] well_known_colors
[19:56:59] [PASSED] destination_pitch
[19:56:59] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[19:56:59] ==================== drm_test_fb_swab =====================
[19:56:59] [PASSED] single_pixel_source_buffer
[19:56:59] [PASSED] single_pixel_clip_rectangle
[19:56:59] [PASSED] well_known_colors
[19:56:59] [PASSED] destination_pitch
[19:56:59] ================ [PASSED] drm_test_fb_swab =================
[19:56:59] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[19:56:59] [PASSED] single_pixel_source_buffer
[19:56:59] [PASSED] single_pixel_clip_rectangle
[19:56:59] [PASSED] well_known_colors
[19:56:59] [PASSED] destination_pitch
[19:56:59] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[19:56:59] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[19:56:59] [PASSED] single_pixel_source_buffer
[19:56:59] [PASSED] single_pixel_clip_rectangle
[19:56:59] [PASSED] well_known_colors
[19:56:59] [PASSED] destination_pitch
[19:56:59] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[19:56:59] ================= drm_test_fb_clip_offset =================
[19:56:59] [PASSED] pass through
[19:56:59] [PASSED] horizontal offset
[19:56:59] [PASSED] vertical offset
[19:56:59] [PASSED] horizontal and vertical offset
[19:56:59] [PASSED] horizontal offset (custom pitch)
[19:56:59] [PASSED] vertical offset (custom pitch)
[19:56:59] [PASSED] horizontal and vertical offset (custom pitch)
[19:56:59] ============= [PASSED] drm_test_fb_clip_offset =============
[19:56:59] =================== drm_test_fb_memcpy ====================
[19:56:59] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[19:56:59] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[19:56:59] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[19:56:59] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[19:56:59] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[19:56:59] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[19:56:59] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[19:56:59] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[19:56:59] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[19:56:59] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[19:56:59] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[19:56:59] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[19:56:59] =============== [PASSED] drm_test_fb_memcpy ================
[19:56:59] ============= [PASSED] drm_format_helper_test ==============
[19:56:59] ================= drm_format (18 subtests) =================
[19:56:59] [PASSED] drm_test_format_block_width_invalid
[19:56:59] [PASSED] drm_test_format_block_width_one_plane
[19:56:59] [PASSED] drm_test_format_block_width_two_plane
[19:56:59] [PASSED] drm_test_format_block_width_three_plane
[19:56:59] [PASSED] drm_test_format_block_width_tiled
[19:56:59] [PASSED] drm_test_format_block_height_invalid
[19:56:59] [PASSED] drm_test_format_block_height_one_plane
[19:56:59] [PASSED] drm_test_format_block_height_two_plane
[19:56:59] [PASSED] drm_test_format_block_height_three_plane
[19:56:59] [PASSED] drm_test_format_block_height_tiled
[19:56:59] [PASSED] drm_test_format_min_pitch_invalid
[19:56:59] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[19:56:59] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[19:56:59] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[19:56:59] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[19:56:59] [PASSED] drm_test_format_min_pitch_two_plane
[19:56:59] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[19:56:59] [PASSED] drm_test_format_min_pitch_tiled
[19:56:59] =================== [PASSED] drm_format ====================
[19:56:59] ============== drm_framebuffer (10 subtests) ===============
[19:56:59] ========== drm_test_framebuffer_check_src_coords ==========
[19:56:59] [PASSED] Success: source fits into fb
[19:56:59] [PASSED] Fail: overflowing fb with x-axis coordinate
[19:56:59] [PASSED] Fail: overflowing fb with y-axis coordinate
[19:56:59] [PASSED] Fail: overflowing fb with source width
[19:56:59] [PASSED] Fail: overflowing fb with source height
[19:56:59] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[19:56:59] [PASSED] drm_test_framebuffer_cleanup
[19:56:59] =============== drm_test_framebuffer_create ===============
[19:56:59] [PASSED] ABGR8888 normal sizes
[19:56:59] [PASSED] ABGR8888 max sizes
[19:56:59] [PASSED] ABGR8888 pitch greater than min required
[19:56:59] [PASSED] ABGR8888 pitch less than min required
[19:56:59] [PASSED] ABGR8888 Invalid width
[19:56:59] [PASSED] ABGR8888 Invalid buffer handle
[19:56:59] [PASSED] No pixel format
[19:56:59] [PASSED] ABGR8888 Width 0
[19:56:59] [PASSED] ABGR8888 Height 0
[19:56:59] [PASSED] ABGR8888 Out of bound height * pitch combination
[19:56:59] [PASSED] ABGR8888 Large buffer offset
[19:56:59] [PASSED] ABGR8888 Buffer offset for inexistent plane
[19:56:59] [PASSED] ABGR8888 Invalid flag
[19:56:59] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[19:56:59] [PASSED] ABGR8888 Valid buffer modifier
[19:56:59] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[19:56:59] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[19:56:59] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[19:56:59] [PASSED] NV12 Normal sizes
[19:56:59] [PASSED] NV12 Max sizes
[19:56:59] [PASSED] NV12 Invalid pitch
[19:56:59] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[19:56:59] [PASSED] NV12 different modifier per-plane
[19:56:59] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[19:56:59] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[19:56:59] [PASSED] NV12 Modifier for inexistent plane
[19:56:59] [PASSED] NV12 Handle for inexistent plane
[19:56:59] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[19:56:59] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[19:56:59] [PASSED] YVU420 Normal sizes
[19:56:59] [PASSED] YVU420 Max sizes
[19:56:59] [PASSED] YVU420 Invalid pitch
[19:56:59] [PASSED] YVU420 Different pitches
[19:56:59] [PASSED] YVU420 Different buffer offsets/pitches
[19:56:59] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[19:56:59] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[19:56:59] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[19:56:59] [PASSED] YVU420 Valid modifier
[19:56:59] [PASSED] YVU420 Different modifiers per plane
[19:56:59] [PASSED] YVU420 Modifier for inexistent plane
[19:56:59] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[19:56:59] [PASSED] X0L2 Normal sizes
[19:56:59] [PASSED] X0L2 Max sizes
[19:56:59] [PASSED] X0L2 Invalid pitch
[19:56:59] [PASSED] X0L2 Pitch greater than minimum required
[19:56:59] [PASSED] X0L2 Handle for inexistent plane
[19:56:59] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[19:56:59] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[19:56:59] [PASSED] X0L2 Valid modifier
[19:56:59] [PASSED] X0L2 Modifier for inexistent plane
[19:56:59] =========== [PASSED] drm_test_framebuffer_create ===========
[19:56:59] [PASSED] drm_test_framebuffer_free
[19:56:59] [PASSED] drm_test_framebuffer_init
[19:56:59] [PASSED] drm_test_framebuffer_init_bad_format
[19:56:59] [PASSED] drm_test_framebuffer_init_dev_mismatch
[19:56:59] [PASSED] drm_test_framebuffer_lookup
[19:56:59] [PASSED] drm_test_framebuffer_lookup_inexistent
[19:56:59] [PASSED] drm_test_framebuffer_modifiers_not_supported
[19:56:59] ================= [PASSED] drm_framebuffer =================
[19:56:59] ================ drm_gem_shmem (8 subtests) ================
[19:56:59] [PASSED] drm_gem_shmem_test_obj_create
[19:56:59] [PASSED] drm_gem_shmem_test_obj_create_private
[19:56:59] [PASSED] drm_gem_shmem_test_pin_pages
[19:56:59] [PASSED] drm_gem_shmem_test_vmap
[19:56:59] [PASSED] drm_gem_shmem_test_get_sg_table
[19:56:59] [PASSED] drm_gem_shmem_test_get_pages_sgt
[19:56:59] [PASSED] drm_gem_shmem_test_madvise
[19:56:59] [PASSED] drm_gem_shmem_test_purge
[19:56:59] ================== [PASSED] drm_gem_shmem ==================
[19:56:59] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[19:56:59] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[19:56:59] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[19:56:59] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[19:56:59] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[19:56:59] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[19:56:59] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[19:56:59] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[19:56:59] [PASSED] Automatic
[19:56:59] [PASSED] Full
[19:56:59] [PASSED] Limited 16:235
[19:56:59] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[19:56:59] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[19:56:59] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[19:56:59] [PASSED] drm_test_check_disable_connector
[19:56:59] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[19:56:59] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[19:56:59] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[19:56:59] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[19:56:59] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[19:56:59] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[19:56:59] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[19:56:59] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[19:56:59] [PASSED] drm_test_check_output_bpc_dvi
[19:56:59] [PASSED] drm_test_check_output_bpc_format_vic_1
[19:56:59] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[19:56:59] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[19:56:59] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[19:56:59] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[19:56:59] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[19:56:59] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[19:56:59] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[19:56:59] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[19:56:59] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[19:56:59] [PASSED] drm_test_check_broadcast_rgb_value
[19:56:59] [PASSED] drm_test_check_bpc_8_value
[19:56:59] [PASSED] drm_test_check_bpc_10_value
[19:56:59] [PASSED] drm_test_check_bpc_12_value
[19:56:59] [PASSED] drm_test_check_format_value
[19:56:59] [PASSED] drm_test_check_tmds_char_value
[19:56:59] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[19:56:59] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[19:56:59] [PASSED] drm_test_check_mode_valid
[19:56:59] [PASSED] drm_test_check_mode_valid_reject
[19:56:59] [PASSED] drm_test_check_mode_valid_reject_rate
[19:56:59] [PASSED] drm_test_check_mode_valid_reject_max_clock
[19:56:59] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[19:56:59] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[19:56:59] [PASSED] drm_test_check_infoframes
[19:56:59] [PASSED] drm_test_check_reject_avi_infoframe
[19:56:59] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[19:56:59] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[19:56:59] [PASSED] drm_test_check_reject_audio_infoframe
[19:56:59] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[19:56:59] ================= drm_managed (2 subtests) =================
[19:56:59] [PASSED] drm_test_managed_release_action
[19:56:59] [PASSED] drm_test_managed_run_action
[19:56:59] =================== [PASSED] drm_managed ===================
[19:56:59] =================== drm_mm (6 subtests) ====================
[19:56:59] [PASSED] drm_test_mm_init
[19:56:59] [PASSED] drm_test_mm_debug
[19:56:59] [PASSED] drm_test_mm_align32
[19:56:59] [PASSED] drm_test_mm_align64
[19:56:59] [PASSED] drm_test_mm_lowest
[19:56:59] [PASSED] drm_test_mm_highest
[19:56:59] ===================== [PASSED] drm_mm ======================
[19:56:59] ============= drm_modes_analog_tv (5 subtests) =============
[19:56:59] [PASSED] drm_test_modes_analog_tv_mono_576i
[19:56:59] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[19:56:59] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[19:56:59] [PASSED] drm_test_modes_analog_tv_pal_576i
[19:56:59] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[19:56:59] =============== [PASSED] drm_modes_analog_tv ===============
[19:56:59] ============== drm_plane_helper (2 subtests) ===============
[19:56:59] =============== drm_test_check_plane_state ================
[19:56:59] [PASSED] clipping_simple
[19:56:59] [PASSED] clipping_rotate_reflect
[19:56:59] [PASSED] positioning_simple
[19:56:59] [PASSED] upscaling
[19:56:59] [PASSED] downscaling
[19:56:59] [PASSED] rounding1
[19:56:59] [PASSED] rounding2
[19:56:59] [PASSED] rounding3
[19:56:59] [PASSED] rounding4
[19:56:59] =========== [PASSED] drm_test_check_plane_state ============
[19:56:59] =========== drm_test_check_invalid_plane_state ============
[19:56:59] [PASSED] positioning_invalid
[19:56:59] [PASSED] upscaling_invalid
[19:56:59] [PASSED] downscaling_invalid
[19:56:59] ======= [PASSED] drm_test_check_invalid_plane_state ========
[19:56:59] ================ [PASSED] drm_plane_helper =================
[19:56:59] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[19:56:59] ====== drm_test_connector_helper_tv_get_modes_check =======
[19:56:59] [PASSED] None
[19:56:59] [PASSED] PAL
[19:56:59] [PASSED] NTSC
[19:56:59] [PASSED] Both, NTSC Default
[19:56:59] [PASSED] Both, PAL Default
[19:56:59] [PASSED] Both, NTSC Default, with PAL on command-line
[19:56:59] [PASSED] Both, PAL Default, with NTSC on command-line
[19:56:59] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[19:56:59] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[19:56:59] ================== drm_rect (9 subtests) ===================
[19:56:59] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[19:56:59] [PASSED] drm_test_rect_clip_scaled_not_clipped
[19:56:59] [PASSED] drm_test_rect_clip_scaled_clipped
[19:56:59] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[19:56:59] ================= drm_test_rect_intersect =================
[19:56:59] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[19:56:59] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[19:56:59] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[19:56:59] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[19:56:59] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[19:56:59] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[19:56:59] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[19:56:59] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[19:56:59] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[19:56:59] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[19:56:59] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[19:56:59] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[19:56:59] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[19:56:59] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[19:56:59] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[19:56:59] ============= [PASSED] drm_test_rect_intersect =============
[19:56:59] ================ drm_test_rect_calc_hscale ================
[19:56:59] [PASSED] normal use
[19:56:59] [PASSED] out of max range
[19:56:59] [PASSED] out of min range
[19:56:59] [PASSED] zero dst
[19:56:59] [PASSED] negative src
[19:56:59] [PASSED] negative dst
[19:56:59] ============ [PASSED] drm_test_rect_calc_hscale ============
[19:56:59] ================ drm_test_rect_calc_vscale ================
[19:56:59] [PASSED] normal use
[19:56:59] [PASSED] out of max range
[19:56:59] [PASSED] out of min range
[19:56:59] [PASSED] zero dst
[19:56:59] [PASSED] negative src
[19:56:59] [PASSED] negative dst
stty: 'standard input': Inappropriate ioctl for device
[19:56:59] ============ [PASSED] drm_test_rect_calc_vscale ============
[19:56:59] ================== drm_test_rect_rotate ===================
[19:56:59] [PASSED] reflect-x
[19:56:59] [PASSED] reflect-y
[19:56:59] [PASSED] rotate-0
[19:56:59] [PASSED] rotate-90
[19:56:59] [PASSED] rotate-180
[19:56:59] [PASSED] rotate-270
[19:56:59] ============== [PASSED] drm_test_rect_rotate ===============
[19:56:59] ================ drm_test_rect_rotate_inv =================
[19:56:59] [PASSED] reflect-x
[19:56:59] [PASSED] reflect-y
[19:56:59] [PASSED] rotate-0
[19:56:59] [PASSED] rotate-90
[19:56:59] [PASSED] rotate-180
[19:56:59] [PASSED] rotate-270
[19:56:59] ============ [PASSED] drm_test_rect_rotate_inv =============
[19:56:59] ==================== [PASSED] drm_rect =====================
[19:56:59] ============ drm_sysfb_modeset_test (1 subtest) ============
[19:56:59] ============ drm_test_sysfb_build_fourcc_list =============
[19:56:59] [PASSED] no native formats
[19:56:59] [PASSED] XRGB8888 as native format
[19:56:59] [PASSED] remove duplicates
[19:56:59] [PASSED] convert alpha formats
[19:56:59] [PASSED] random formats
[19:56:59] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[19:56:59] ============= [PASSED] drm_sysfb_modeset_test ==============
[19:56:59] ================== drm_fixp (2 subtests) ===================
[19:56:59] [PASSED] drm_test_int2fixp
[19:56:59] [PASSED] drm_test_sm2fixp
[19:56:59] ==================== [PASSED] drm_fixp =====================
[19:56:59] ============================================================
[19:56:59] Testing complete. Ran 621 tests: passed: 621
[19:56:59] Elapsed time: 26.026s total, 1.641s configuring, 24.204s building, 0.180s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[19:56:59] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[19:57:01] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[19:57:10] Starting KUnit Kernel (1/1)...
[19:57:10] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[19:57:10] ================= ttm_device (5 subtests) ==================
[19:57:10] [PASSED] ttm_device_init_basic
[19:57:10] [PASSED] ttm_device_init_multiple
[19:57:10] [PASSED] ttm_device_fini_basic
[19:57:10] [PASSED] ttm_device_init_no_vma_man
[19:57:10] ================== ttm_device_init_pools ==================
[19:57:10] [PASSED] No DMA allocations, no DMA32 required
[19:57:10] [PASSED] DMA allocations, DMA32 required
[19:57:10] [PASSED] No DMA allocations, DMA32 required
[19:57:10] [PASSED] DMA allocations, no DMA32 required
[19:57:10] ============== [PASSED] ttm_device_init_pools ==============
[19:57:10] =================== [PASSED] ttm_device ====================
[19:57:10] ================== ttm_pool (8 subtests) ===================
[19:57:10] ================== ttm_pool_alloc_basic ===================
[19:57:10] [PASSED] One page
[19:57:10] [PASSED] More than one page
[19:57:10] [PASSED] Above the allocation limit
[19:57:10] [PASSED] One page, with coherent DMA mappings enabled
[19:57:10] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[19:57:10] ============== [PASSED] ttm_pool_alloc_basic ===============
[19:57:10] ============== ttm_pool_alloc_basic_dma_addr ==============
[19:57:10] [PASSED] One page
[19:57:10] [PASSED] More than one page
[19:57:10] [PASSED] Above the allocation limit
[19:57:10] [PASSED] One page, with coherent DMA mappings enabled
[19:57:10] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[19:57:10] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[19:57:10] [PASSED] ttm_pool_alloc_order_caching_match
[19:57:10] [PASSED] ttm_pool_alloc_caching_mismatch
[19:57:10] [PASSED] ttm_pool_alloc_order_mismatch
[19:57:10] [PASSED] ttm_pool_free_dma_alloc
[19:57:10] [PASSED] ttm_pool_free_no_dma_alloc
[19:57:10] [PASSED] ttm_pool_fini_basic
[19:57:10] ==================== [PASSED] ttm_pool =====================
[19:57:10] ================ ttm_resource (8 subtests) =================
[19:57:10] ================= ttm_resource_init_basic =================
[19:57:10] [PASSED] Init resource in TTM_PL_SYSTEM
[19:57:10] [PASSED] Init resource in TTM_PL_VRAM
[19:57:10] [PASSED] Init resource in a private placement
[19:57:10] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[19:57:10] ============= [PASSED] ttm_resource_init_basic =============
[19:57:10] [PASSED] ttm_resource_init_pinned
[19:57:10] [PASSED] ttm_resource_fini_basic
[19:57:10] [PASSED] ttm_resource_manager_init_basic
[19:57:10] [PASSED] ttm_resource_manager_usage_basic
[19:57:10] [PASSED] ttm_resource_manager_set_used_basic
[19:57:10] [PASSED] ttm_sys_man_alloc_basic
[19:57:10] [PASSED] ttm_sys_man_free_basic
[19:57:10] ================== [PASSED] ttm_resource ===================
[19:57:10] =================== ttm_tt (15 subtests) ===================
[19:57:10] ==================== ttm_tt_init_basic ====================
[19:57:10] [PASSED] Page-aligned size
[19:57:10] [PASSED] Extra pages requested
[19:57:10] ================ [PASSED] ttm_tt_init_basic ================
[19:57:10] [PASSED] ttm_tt_init_misaligned
[19:57:10] [PASSED] ttm_tt_fini_basic
[19:57:10] [PASSED] ttm_tt_fini_sg
[19:57:10] [PASSED] ttm_tt_fini_shmem
[19:57:10] [PASSED] ttm_tt_create_basic
[19:57:10] [PASSED] ttm_tt_create_invalid_bo_type
[19:57:10] [PASSED] ttm_tt_create_ttm_exists
[19:57:10] [PASSED] ttm_tt_create_failed
[19:57:10] [PASSED] ttm_tt_destroy_basic
[19:57:10] [PASSED] ttm_tt_populate_null_ttm
[19:57:10] [PASSED] ttm_tt_populate_populated_ttm
[19:57:10] [PASSED] ttm_tt_unpopulate_basic
[19:57:10] [PASSED] ttm_tt_unpopulate_empty_ttm
[19:57:10] [PASSED] ttm_tt_swapin_basic
[19:57:10] ===================== [PASSED] ttm_tt ======================
[19:57:10] =================== ttm_bo (14 subtests) ===================
[19:57:10] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[19:57:10] [PASSED] Cannot be interrupted and sleeps
[19:57:10] [PASSED] Cannot be interrupted, locks straight away
[19:57:10] [PASSED] Can be interrupted, sleeps
[19:57:10] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[19:57:10] [PASSED] ttm_bo_reserve_locked_no_sleep
[19:57:10] [PASSED] ttm_bo_reserve_no_wait_ticket
[19:57:10] [PASSED] ttm_bo_reserve_double_resv
[19:57:10] [PASSED] ttm_bo_reserve_interrupted
[19:57:10] [PASSED] ttm_bo_reserve_deadlock
[19:57:10] [PASSED] ttm_bo_unreserve_basic
[19:57:10] [PASSED] ttm_bo_unreserve_pinned
[19:57:10] [PASSED] ttm_bo_unreserve_bulk
[19:57:10] [PASSED] ttm_bo_fini_basic
[19:57:10] [PASSED] ttm_bo_fini_shared_resv
[19:57:10] [PASSED] ttm_bo_pin_basic
[19:57:10] [PASSED] ttm_bo_pin_unpin_resource
[19:57:10] [PASSED] ttm_bo_multiple_pin_one_unpin
[19:57:10] ===================== [PASSED] ttm_bo ======================
[19:57:10] ============== ttm_bo_validate (22 subtests) ===============
[19:57:10] ============== ttm_bo_init_reserved_sys_man ===============
[19:57:10] [PASSED] Buffer object for userspace
[19:57:10] [PASSED] Kernel buffer object
[19:57:10] [PASSED] Shared buffer object
[19:57:10] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[19:57:10] ============== ttm_bo_init_reserved_mock_man ==============
[19:57:10] [PASSED] Buffer object for userspace
[19:57:10] [PASSED] Kernel buffer object
[19:57:10] [PASSED] Shared buffer object
[19:57:10] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[19:57:10] [PASSED] ttm_bo_init_reserved_resv
[19:57:10] ================== ttm_bo_validate_basic ==================
[19:57:10] [PASSED] Buffer object for userspace
[19:57:10] [PASSED] Kernel buffer object
[19:57:10] [PASSED] Shared buffer object
[19:57:10] ============== [PASSED] ttm_bo_validate_basic ==============
[19:57:10] [PASSED] ttm_bo_validate_invalid_placement
[19:57:10] ============= ttm_bo_validate_same_placement ==============
[19:57:10] [PASSED] System manager
[19:57:10] [PASSED] VRAM manager
[19:57:10] ========= [PASSED] ttm_bo_validate_same_placement ==========
[19:57:10] [PASSED] ttm_bo_validate_failed_alloc
[19:57:10] [PASSED] ttm_bo_validate_pinned
[19:57:10] [PASSED] ttm_bo_validate_busy_placement
[19:57:10] ================ ttm_bo_validate_multihop =================
[19:57:10] [PASSED] Buffer object for userspace
[19:57:10] [PASSED] Kernel buffer object
[19:57:10] [PASSED] Shared buffer object
[19:57:10] ============ [PASSED] ttm_bo_validate_multihop =============
[19:57:10] ========== ttm_bo_validate_no_placement_signaled ==========
[19:57:10] [PASSED] Buffer object in system domain, no page vector
[19:57:10] [PASSED] Buffer object in system domain with an existing page vector
[19:57:10] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[19:57:10] ======== ttm_bo_validate_no_placement_not_signaled ========
[19:57:10] [PASSED] Buffer object for userspace
[19:57:10] [PASSED] Kernel buffer object
[19:57:10] [PASSED] Shared buffer object
[19:57:10] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[19:57:10] [PASSED] ttm_bo_validate_move_fence_signaled
[19:57:10] ========= ttm_bo_validate_move_fence_not_signaled =========
[19:57:10] [PASSED] Waits for GPU
[19:57:10] [PASSED] Tries to lock straight away
[19:57:10] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[19:57:10] [PASSED] ttm_bo_validate_swapout
[19:57:10] [PASSED] ttm_bo_validate_happy_evict
[19:57:10] [PASSED] ttm_bo_validate_all_pinned_evict
[19:57:10] [PASSED] ttm_bo_validate_allowed_only_evict
[19:57:10] [PASSED] ttm_bo_validate_deleted_evict
[19:57:10] [PASSED] ttm_bo_validate_busy_domain_evict
[19:57:10] [PASSED] ttm_bo_validate_evict_gutting
[19:57:10] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[19:57:10] ================= [PASSED] ttm_bo_validate =================
[19:57:10] ============================================================
[19:57:10] Testing complete. Ran 102 tests: passed: 102
[19:57:10] Elapsed time: 11.398s total, 1.684s configuring, 9.448s building, 0.218s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 15+ messages in thread
* ✓ Xe.CI.BAT: success for drm/xe: Add min and max context TLB invalidation sizes
2026-03-17 19:50 [PATCH] drm/xe: Add min and max context TLB invalidation sizes Stuart Summers
2026-03-17 19:57 ` ✓ CI.KUnit: success for " Patchwork
@ 2026-03-17 21:01 ` Patchwork
2026-03-19 6:52 ` ✓ Xe.CI.FULL: " Patchwork
2 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2026-03-17 21:01 UTC (permalink / raw)
To: Stuart Summers; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 6123 bytes --]
== Series Details ==
Series: drm/xe: Add min and max context TLB invalidation sizes
URL : https://patchwork.freedesktop.org/series/163403/
State : success
== Summary ==
CI Bug Log - changes from xe-4737-6bb9fd4e927009e819a3d1c01a989545fb6ddbaa_BAT -> xe-pw-163403v1_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (13 -> 14)
------------------------------
Additional (1): bat-adlp-7
Known issues
------------
Here are the changes found in xe-pw-163403v1_BAT that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_dsc@dsc-basic:
- bat-adlp-7: NOTRUN -> [SKIP][1] ([Intel XE#2244] / [Intel XE#455])
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/bat-adlp-7/igt@kms_dsc@dsc-basic.html
* igt@kms_flip@basic-flip-vs-dpms:
- bat-adlp-7: NOTRUN -> [DMESG-WARN][2] ([Intel XE#7483]) +12 other tests dmesg-warn
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/bat-adlp-7/igt@kms_flip@basic-flip-vs-dpms.html
* igt@xe_evict@evict-beng-small:
- bat-adlp-7: NOTRUN -> [SKIP][3] ([Intel XE#261] / [Intel XE#5564] / [Intel XE#688]) +9 other tests skip
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/bat-adlp-7/igt@xe_evict@evict-beng-small.html
* igt@xe_evict_ccs@evict-overcommit-parallel-nofree-samefd:
- bat-adlp-7: NOTRUN -> [SKIP][4] ([Intel XE#5563] / [Intel XE#688]) +1 other test skip
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/bat-adlp-7/igt@xe_evict_ccs@evict-overcommit-parallel-nofree-samefd.html
* igt@xe_exec_balancer@twice-cm-virtual-userptr:
- bat-adlp-7: NOTRUN -> [SKIP][5] ([Intel XE#7482]) +17 other tests skip
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/bat-adlp-7/igt@xe_exec_balancer@twice-cm-virtual-userptr.html
* igt@xe_exec_fault_mode@twice-rebind-prefetch:
- bat-adlp-7: NOTRUN -> [SKIP][6] ([Intel XE#288] / [Intel XE#5561]) +32 other tests skip
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/bat-adlp-7/igt@xe_exec_fault_mode@twice-rebind-prefetch.html
* igt@xe_live_ktest@xe_bo:
- bat-adlp-7: NOTRUN -> [SKIP][7] ([Intel XE#2229] / [Intel XE#455]) +2 other tests skip
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/bat-adlp-7/igt@xe_live_ktest@xe_bo.html
* igt@xe_live_ktest@xe_migrate@xe_validate_ccs_kunit:
- bat-adlp-7: NOTRUN -> [SKIP][8] ([Intel XE#2229] / [Intel XE#5488])
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/bat-adlp-7/igt@xe_live_ktest@xe_migrate@xe_validate_ccs_kunit.html
* igt@xe_mmap@vram:
- bat-adlp-7: NOTRUN -> [SKIP][9] ([Intel XE#1008] / [Intel XE#5591])
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/bat-adlp-7/igt@xe_mmap@vram.html
* igt@xe_pat@pat-index-xe2:
- bat-adlp-7: NOTRUN -> [SKIP][10] ([Intel XE#977])
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/bat-adlp-7/igt@xe_pat@pat-index-xe2.html
* igt@xe_pat@pat-index-xehpc:
- bat-adlp-7: NOTRUN -> [SKIP][11] ([Intel XE#2838] / [Intel XE#979])
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/bat-adlp-7/igt@xe_pat@pat-index-xehpc.html
* igt@xe_pat@pat-index-xelpg:
- bat-adlp-7: NOTRUN -> [SKIP][12] ([Intel XE#979])
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/bat-adlp-7/igt@xe_pat@pat-index-xelpg.html
* igt@xe_waitfence@engine:
- bat-dg2-oem2: [PASS][13] -> [FAIL][14] ([Intel XE#6519])
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4737-6bb9fd4e927009e819a3d1c01a989545fb6ddbaa/bat-dg2-oem2/igt@xe_waitfence@engine.html
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/bat-dg2-oem2/igt@xe_waitfence@engine.html
* igt@xe_waitfence@reltime:
- bat-dg2-oem2: [PASS][15] -> [FAIL][16] ([Intel XE#6520])
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4737-6bb9fd4e927009e819a3d1c01a989545fb6ddbaa/bat-dg2-oem2/igt@xe_waitfence@reltime.html
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/bat-dg2-oem2/igt@xe_waitfence@reltime.html
[Intel XE#1008]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1008
[Intel XE#2229]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2229
[Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
[Intel XE#261]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/261
[Intel XE#2838]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2838
[Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
[Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
[Intel XE#5488]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5488
[Intel XE#5561]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5561
[Intel XE#5563]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5563
[Intel XE#5564]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5564
[Intel XE#5591]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5591
[Intel XE#6519]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6519
[Intel XE#6520]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6520
[Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
[Intel XE#7482]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7482
[Intel XE#7483]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7483
[Intel XE#977]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/977
[Intel XE#979]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/979
Build changes
-------------
* Linux: xe-4737-6bb9fd4e927009e819a3d1c01a989545fb6ddbaa -> xe-pw-163403v1
IGT_8807: 7f44d96d705f1583d689f1f8c2275b685b4ca11d @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-4737-6bb9fd4e927009e819a3d1c01a989545fb6ddbaa: 6bb9fd4e927009e819a3d1c01a989545fb6ddbaa
xe-pw-163403v1: 163403v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/index.html
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^ permalink raw reply [flat|nested] 15+ messages in thread
* ✓ Xe.CI.FULL: success for drm/xe: Add min and max context TLB invalidation sizes
2026-03-17 19:50 [PATCH] drm/xe: Add min and max context TLB invalidation sizes Stuart Summers
2026-03-17 19:57 ` ✓ CI.KUnit: success for " Patchwork
2026-03-17 21:01 ` ✓ Xe.CI.BAT: " Patchwork
@ 2026-03-19 6:52 ` Patchwork
2 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2026-03-19 6:52 UTC (permalink / raw)
To: Summers, Stuart; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 25657 bytes --]
== Series Details ==
Series: drm/xe: Add min and max context TLB invalidation sizes
URL : https://patchwork.freedesktop.org/series/163403/
State : success
== Summary ==
CI Bug Log - changes from xe-4737-6bb9fd4e927009e819a3d1c01a989545fb6ddbaa_FULL -> xe-pw-163403v1_FULL
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (2 -> 2)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in xe-pw-163403v1_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_async_flips@alternate-sync-async-flip-atomic:
- shard-bmg: [PASS][1] -> [FAIL][2] ([Intel XE#3718] / [Intel XE#6078])
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4737-6bb9fd4e927009e819a3d1c01a989545fb6ddbaa/shard-bmg-6/igt@kms_async_flips@alternate-sync-async-flip-atomic.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/shard-bmg-9/igt@kms_async_flips@alternate-sync-async-flip-atomic.html
* igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-d-dp-2:
- shard-bmg: [PASS][3] -> [FAIL][4] ([Intel XE#6078])
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4737-6bb9fd4e927009e819a3d1c01a989545fb6ddbaa/shard-bmg-6/igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-d-dp-2.html
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/shard-bmg-9/igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-d-dp-2.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
- shard-bmg: [PASS][5] -> [INCOMPLETE][6] ([Intel XE#6904]) +1 other test incomplete
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4737-6bb9fd4e927009e819a3d1c01a989545fb6ddbaa/shard-bmg-8/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/shard-bmg-3/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
* igt@kms_big_fb@linear-16bpp-rotate-270:
- shard-bmg: NOTRUN -> [SKIP][7] ([Intel XE#2327])
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/shard-bmg-1/igt@kms_big_fb@linear-16bpp-rotate-270.html
* igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-180-hflip:
- shard-bmg: NOTRUN -> [SKIP][8] ([Intel XE#7059] / [Intel XE#7085])
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/shard-bmg-1/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_big_fb@y-tiled-16bpp-rotate-180:
- shard-bmg: NOTRUN -> [SKIP][9] ([Intel XE#1124]) +2 other tests skip
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/shard-bmg-1/igt@kms_big_fb@y-tiled-16bpp-rotate-180.html
* igt@kms_bw@connected-linear-tiling-4-displays-2560x1440p:
- shard-bmg: NOTRUN -> [SKIP][10] ([Intel XE#2314] / [Intel XE#2894] / [Intel XE#7373])
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/shard-bmg-4/igt@kms_bw@connected-linear-tiling-4-displays-2560x1440p.html
* igt@kms_bw@linear-tiling-2-displays-2160x1440p:
- shard-bmg: NOTRUN -> [SKIP][11] ([Intel XE#367] / [Intel XE#7354])
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/shard-bmg-1/igt@kms_bw@linear-tiling-2-displays-2160x1440p.html
* igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs-cc:
- shard-bmg: NOTRUN -> [SKIP][12] ([Intel XE#2887]) +2 other tests skip
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/shard-bmg-1/igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs-cc.html
* igt@kms_chamelium_hpd@hdmi-hpd-for-each-pipe:
- shard-bmg: NOTRUN -> [SKIP][13] ([Intel XE#2252]) +1 other test skip
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/shard-bmg-4/igt@kms_chamelium_hpd@hdmi-hpd-for-each-pipe.html
* igt@kms_cursor_crc@cursor-onscreen-512x512:
- shard-bmg: NOTRUN -> [SKIP][14] ([Intel XE#2321] / [Intel XE#7355])
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/shard-bmg-1/igt@kms_cursor_crc@cursor-onscreen-512x512.html
* igt@kms_cursor_crc@cursor-rapid-movement-128x42:
- shard-bmg: NOTRUN -> [SKIP][15] ([Intel XE#2320])
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/shard-bmg-1/igt@kms_cursor_crc@cursor-rapid-movement-128x42.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-atomic:
- shard-bmg: [PASS][16] -> [SKIP][17] ([Intel XE#2291])
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4737-6bb9fd4e927009e819a3d1c01a989545fb6ddbaa/shard-bmg-2/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic.html
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/shard-bmg-5/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic.html
* igt@kms_cursor_legacy@flip-vs-cursor-legacy:
- shard-bmg: [PASS][18] -> [FAIL][19] ([Intel XE#7571])
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4737-6bb9fd4e927009e819a3d1c01a989545fb6ddbaa/shard-bmg-8/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/shard-bmg-3/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
* igt@kms_display_modes@extended-mode-basic:
- shard-bmg: [PASS][20] -> [SKIP][21] ([Intel XE#4302])
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4737-6bb9fd4e927009e819a3d1c01a989545fb6ddbaa/shard-bmg-2/igt@kms_display_modes@extended-mode-basic.html
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/shard-bmg-5/igt@kms_display_modes@extended-mode-basic.html
* igt@kms_flip@2x-nonexisting-fb:
- shard-bmg: [PASS][22] -> [SKIP][23] ([Intel XE#2316]) +2 other tests skip
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4737-6bb9fd4e927009e819a3d1c01a989545fb6ddbaa/shard-bmg-2/igt@kms_flip@2x-nonexisting-fb.html
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/shard-bmg-5/igt@kms_flip@2x-nonexisting-fb.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
- shard-lnl: [PASS][24] -> [FAIL][25] ([Intel XE#301])
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4737-6bb9fd4e927009e819a3d1c01a989545fb6ddbaa/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling:
- shard-bmg: NOTRUN -> [SKIP][26] ([Intel XE#7178] / [Intel XE#7351]) +1 other test skip
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/shard-bmg-1/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-wc:
- shard-bmg: NOTRUN -> [SKIP][27] ([Intel XE#4141]) +2 other tests skip
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/shard-bmg-1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-blt:
- shard-bmg: NOTRUN -> [SKIP][28] ([Intel XE#2311]) +7 other tests skip
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-blt:
- shard-bmg: NOTRUN -> [SKIP][29] ([Intel XE#2313]) +4 other tests skip
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-argb161616f-draw-blt:
- shard-bmg: NOTRUN -> [SKIP][30] ([Intel XE#7061] / [Intel XE#7356])
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/shard-bmg-1/igt@kms_frontbuffer_tracking@psr-argb161616f-draw-blt.html
* igt@kms_hdr@static-swap:
- shard-bmg: [PASS][31] -> [SKIP][32] ([Intel XE#1503])
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4737-6bb9fd4e927009e819a3d1c01a989545fb6ddbaa/shard-bmg-2/igt@kms_hdr@static-swap.html
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/shard-bmg-5/igt@kms_hdr@static-swap.html
* igt@kms_joiner@invalid-modeset-force-ultra-joiner:
- shard-bmg: NOTRUN -> [SKIP][33] ([Intel XE#6911] / [Intel XE#7466])
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/shard-bmg-4/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html
* igt@kms_plane_multiple@2x-tiling-yf:
- shard-bmg: NOTRUN -> [SKIP][34] ([Intel XE#5021] / [Intel XE#7377])
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/shard-bmg-1/igt@kms_plane_multiple@2x-tiling-yf.html
* igt@kms_pm_dc@dc3co-vpb-simulation:
- shard-bmg: NOTRUN -> [SKIP][35] ([Intel XE#2391] / [Intel XE#6927])
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/shard-bmg-1/igt@kms_pm_dc@dc3co-vpb-simulation.html
* igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-fully-sf:
- shard-bmg: NOTRUN -> [SKIP][36] ([Intel XE#1489]) +1 other test skip
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/shard-bmg-1/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr@psr-suspend:
- shard-bmg: NOTRUN -> [SKIP][37] ([Intel XE#2234] / [Intel XE#2850]) +3 other tests skip
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/shard-bmg-1/igt@kms_psr@psr-suspend.html
* igt@kms_vrr@flip-suspend:
- shard-bmg: NOTRUN -> [SKIP][38] ([Intel XE#1499])
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/shard-bmg-1/igt@kms_vrr@flip-suspend.html
* igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1:
- shard-lnl: [PASS][39] -> [FAIL][40] ([Intel XE#2142]) +1 other test fail
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4737-6bb9fd4e927009e819a3d1c01a989545fb6ddbaa/shard-lnl-5/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/shard-lnl-1/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html
* igt@xe_eudebug@basic-vm-bind-metadata-discovery:
- shard-bmg: NOTRUN -> [SKIP][41] ([Intel XE#4837]) +2 other tests skip
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/shard-bmg-1/igt@xe_eudebug@basic-vm-bind-metadata-discovery.html
* igt@xe_eudebug_online@writes-caching-sram-bb-sram-target-vram:
- shard-bmg: NOTRUN -> [SKIP][42] ([Intel XE#4837] / [Intel XE#6665])
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/shard-bmg-1/igt@xe_eudebug_online@writes-caching-sram-bb-sram-target-vram.html
* igt@xe_evict@evict-mixed-many-threads-small:
- shard-bmg: [PASS][43] -> [INCOMPLETE][44] ([Intel XE#6321])
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4737-6bb9fd4e927009e819a3d1c01a989545fb6ddbaa/shard-bmg-9/igt@xe_evict@evict-mixed-many-threads-small.html
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/shard-bmg-7/igt@xe_evict@evict-mixed-many-threads-small.html
* igt@xe_exec_basic@multigpu-no-exec-basic-defer-bind:
- shard-bmg: NOTRUN -> [SKIP][45] ([Intel XE#2322] / [Intel XE#7372])
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/shard-bmg-1/igt@xe_exec_basic@multigpu-no-exec-basic-defer-bind.html
* igt@xe_exec_multi_queue@two-queues-basic-smem:
- shard-bmg: NOTRUN -> [SKIP][46] ([Intel XE#6874]) +5 other tests skip
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/shard-bmg-1/igt@xe_exec_multi_queue@two-queues-basic-smem.html
* igt@xe_exec_threads@threads-multi-queue-cm-userptr-invalidate-race:
- shard-bmg: NOTRUN -> [SKIP][47] ([Intel XE#7138]) +1 other test skip
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/shard-bmg-1/igt@xe_exec_threads@threads-multi-queue-cm-userptr-invalidate-race.html
* igt@xe_pm_residency@idle-residency@gt0:
- shard-bmg: [PASS][48] -> [FAIL][49] ([Intel XE#7293]) +1 other test fail
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4737-6bb9fd4e927009e819a3d1c01a989545fb6ddbaa/shard-bmg-3/igt@xe_pm_residency@idle-residency@gt0.html
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/shard-bmg-2/igt@xe_pm_residency@idle-residency@gt0.html
* igt@xe_query@multigpu-query-mem-usage:
- shard-bmg: NOTRUN -> [SKIP][50] ([Intel XE#944])
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/shard-bmg-1/igt@xe_query@multigpu-query-mem-usage.html
#### Possible fixes ####
* igt@kms_atomic_transition@modeset-transition-nonblocking:
- shard-bmg: [ABORT][51] ([Intel XE#5545] / [Intel XE#6652]) -> [PASS][52] +1 other test pass
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4737-6bb9fd4e927009e819a3d1c01a989545fb6ddbaa/shard-bmg-2/igt@kms_atomic_transition@modeset-transition-nonblocking.html
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/shard-bmg-1/igt@kms_atomic_transition@modeset-transition-nonblocking.html
* igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy:
- shard-bmg: [SKIP][53] ([Intel XE#2291]) -> [PASS][54] +1 other test pass
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4737-6bb9fd4e927009e819a3d1c01a989545fb6ddbaa/shard-bmg-5/igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy.html
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/shard-bmg-1/igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size:
- shard-bmg: [SKIP][55] ([Intel XE#2291] / [Intel XE#7343]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4737-6bb9fd4e927009e819a3d1c01a989545fb6ddbaa/shard-bmg-5/igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size.html
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/shard-bmg-8/igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size.html
* igt@kms_flip@2x-flip-vs-dpms-on-nop-interruptible:
- shard-bmg: [SKIP][57] ([Intel XE#2316]) -> [PASS][58] +4 other tests pass
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4737-6bb9fd4e927009e819a3d1c01a989545fb6ddbaa/shard-bmg-5/igt@kms_flip@2x-flip-vs-dpms-on-nop-interruptible.html
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/shard-bmg-1/igt@kms_flip@2x-flip-vs-dpms-on-nop-interruptible.html
* igt@kms_flip@flip-vs-expired-vblank@b-edp1:
- shard-lnl: [FAIL][59] ([Intel XE#301]) -> [PASS][60] +2 other tests pass
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4737-6bb9fd4e927009e819a3d1c01a989545fb6ddbaa/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
* igt@kms_hdr@invalid-hdr:
- shard-bmg: [SKIP][61] ([Intel XE#1503]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4737-6bb9fd4e927009e819a3d1c01a989545fb6ddbaa/shard-bmg-6/igt@kms_hdr@invalid-hdr.html
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/shard-bmg-7/igt@kms_hdr@invalid-hdr.html
* igt@kms_setmode@clone-exclusive-crtc:
- shard-bmg: [SKIP][63] ([Intel XE#1435]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4737-6bb9fd4e927009e819a3d1c01a989545fb6ddbaa/shard-bmg-5/igt@kms_setmode@clone-exclusive-crtc.html
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/shard-bmg-8/igt@kms_setmode@clone-exclusive-crtc.html
* igt@kms_vrr@negative-basic:
- shard-bmg: [SKIP][65] ([Intel XE#1499]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4737-6bb9fd4e927009e819a3d1c01a989545fb6ddbaa/shard-bmg-5/igt@kms_vrr@negative-basic.html
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/shard-bmg-8/igt@kms_vrr@negative-basic.html
#### Warnings ####
* igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p:
- shard-bmg: [SKIP][67] ([Intel XE#2314] / [Intel XE#2894] / [Intel XE#7373]) -> [SKIP][68] ([Intel XE#7621])
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4737-6bb9fd4e927009e819a3d1c01a989545fb6ddbaa/shard-bmg-5/igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p.html
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/shard-bmg-8/igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p.html
* igt@kms_content_protection@uevent:
- shard-bmg: [FAIL][69] ([Intel XE#6707] / [Intel XE#7439]) -> [SKIP][70] ([Intel XE#2341])
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4737-6bb9fd4e927009e819a3d1c01a989545fb6ddbaa/shard-bmg-2/igt@kms_content_protection@uevent.html
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/shard-bmg-5/igt@kms_content_protection@uevent.html
* igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-render:
- shard-bmg: [SKIP][71] ([Intel XE#2312]) -> [SKIP][72] ([Intel XE#2311]) +8 other tests skip
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4737-6bb9fd4e927009e819a3d1c01a989545fb6ddbaa/shard-bmg-5/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-render.html
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/shard-bmg-8/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render:
- shard-bmg: [SKIP][73] ([Intel XE#4141]) -> [SKIP][74] ([Intel XE#2312]) +5 other tests skip
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4737-6bb9fd4e927009e819a3d1c01a989545fb6ddbaa/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html
[74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render:
- shard-bmg: [SKIP][75] ([Intel XE#2312]) -> [SKIP][76] ([Intel XE#4141]) +5 other tests skip
[75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4737-6bb9fd4e927009e819a3d1c01a989545fb6ddbaa/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render.html
[76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/shard-bmg-1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-shrfb-plflip-blt:
- shard-bmg: [SKIP][77] ([Intel XE#2311]) -> [SKIP][78] ([Intel XE#2312]) +7 other tests skip
[77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4737-6bb9fd4e927009e819a3d1c01a989545fb6ddbaa/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-shrfb-plflip-blt.html
[78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-shrfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-pgflip-blt:
- shard-bmg: [SKIP][79] ([Intel XE#2313]) -> [SKIP][80] ([Intel XE#2312]) +7 other tests skip
[79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4737-6bb9fd4e927009e819a3d1c01a989545fb6ddbaa/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-pgflip-blt.html
[80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt:
- shard-bmg: [SKIP][81] ([Intel XE#2312]) -> [SKIP][82] ([Intel XE#2313]) +6 other tests skip
[81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4737-6bb9fd4e927009e819a3d1c01a989545fb6ddbaa/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt.html
[82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt.html
* igt@kms_hdr@brightness-with-hdr:
- shard-bmg: [SKIP][83] ([Intel XE#3374] / [Intel XE#3544]) -> [SKIP][84] ([Intel XE#3544])
[83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4737-6bb9fd4e927009e819a3d1c01a989545fb6ddbaa/shard-bmg-3/igt@kms_hdr@brightness-with-hdr.html
[84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/shard-bmg-2/igt@kms_hdr@brightness-with-hdr.html
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
[Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
[Intel XE#2142]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2142
[Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
[Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
[Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
[Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
[Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
[Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
[Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
[Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
[Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
[Intel XE#2391]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2391
[Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
[Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
[Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
[Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
[Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
[Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
[Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
[Intel XE#3718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3718
[Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
[Intel XE#4302]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4302
[Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
[Intel XE#5021]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5021
[Intel XE#5545]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5545
[Intel XE#6078]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6078
[Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
[Intel XE#6652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6652
[Intel XE#6665]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6665
[Intel XE#6707]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6707
[Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
[Intel XE#6904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6904
[Intel XE#6911]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6911
[Intel XE#6927]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6927
[Intel XE#7059]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7059
[Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
[Intel XE#7085]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7085
[Intel XE#7138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7138
[Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
[Intel XE#7293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7293
[Intel XE#7343]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7343
[Intel XE#7351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7351
[Intel XE#7354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7354
[Intel XE#7355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7355
[Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
[Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
[Intel XE#7373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7373
[Intel XE#7377]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7377
[Intel XE#7439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7439
[Intel XE#7466]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7466
[Intel XE#7571]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7571
[Intel XE#7621]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7621
[Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
Build changes
-------------
* Linux: xe-4737-6bb9fd4e927009e819a3d1c01a989545fb6ddbaa -> xe-pw-163403v1
IGT_8807: 7f44d96d705f1583d689f1f8c2275b685b4ca11d @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-4737-6bb9fd4e927009e819a3d1c01a989545fb6ddbaa: 6bb9fd4e927009e819a3d1c01a989545fb6ddbaa
xe-pw-163403v1: 163403v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163403v1/index.html
[-- Attachment #2: Type: text/html, Size: 28964 bytes --]
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH] drm/xe: Add min and max context TLB invalidation sizes
@ 2026-03-19 21:05 Stuart Summers
2026-03-19 21:11 ` Summers, Stuart
2026-03-22 5:56 ` Matthew Brost
0 siblings, 2 replies; 15+ messages in thread
From: Stuart Summers @ 2026-03-19 21:05 UTC (permalink / raw)
Cc: matthew.brost, niranjana.vishwanathapura, intel-xe,
Stuart Summers
Allow platform-defined TLB invalidation min and max lengths.
This gives finer granular control to which invalidations we
decide to send to GuC. The min size is essentially a round
up. The max allows us to switch to a full invalidation.
The expectation here is that GuC will translate the full
invalidation in this instance into a series of per context
invalidaitons. These are then issued with no H2G or G2H
messages and therefore should be quicker than splitting
the invalidations from the KMD in max size chunks and sending
separately.
v2: Add proper defaults for min/max if not set in the device
structures
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
drivers/gpu/drm/xe/xe_device_types.h | 4 ++++
drivers/gpu/drm/xe/xe_guc_tlb_inval.c | 20 +++++++-------------
drivers/gpu/drm/xe/xe_pci.c | 3 +++
drivers/gpu/drm/xe/xe_pci_types.h | 2 ++
4 files changed, 16 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 615218d775b1..0c4168fe2ffb 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -137,6 +137,10 @@ struct xe_device {
u8 vm_max_level;
/** @info.va_bits: Maximum bits of a virtual address */
u8 va_bits;
+ /** @info.min_tlb_inval_size: Minimum size of context based TLB invalidations */
+ u64 min_tlb_inval_size;
+ /** @info.max_tlb_inval_size: Maximum size of context based TLB invalidations */
+ u64 max_tlb_inval_size;
/*
* Keep all flags below alphabetically sorted
diff --git a/drivers/gpu/drm/xe/xe_guc_tlb_inval.c b/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
index eb40528976ca..7512f889a97a 100644
--- a/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
+++ b/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
@@ -133,12 +133,12 @@ static int send_page_reclaim(struct xe_guc *guc, u32 seqno,
static u64 normalize_invalidation_range(struct xe_gt *gt, u64 *start, u64 *end)
{
+ struct xe_device *xe = gt_to_xe(gt);
u64 orig_start = *start;
u64 length = *end - *start;
u64 align;
- if (length < SZ_4K)
- length = SZ_4K;
+ length = max_t(u64, xe->info.min_tlb_inval_size, length);
align = roundup_pow_of_two(length);
*start = ALIGN_DOWN(*start, align);
@@ -163,13 +163,6 @@ static u64 normalize_invalidation_range(struct xe_gt *gt, u64 *start, u64 *end)
return length;
}
-/*
- * Ensure that roundup_pow_of_two(length) doesn't overflow.
- * Note that roundup_pow_of_two() operates on unsigned long,
- * not on u64.
- */
-#define MAX_RANGE_TLB_INVALIDATION_LENGTH (rounddown_pow_of_two(ULONG_MAX))
-
static int send_tlb_inval_ppgtt(struct xe_guc *guc, u32 seqno, u64 start,
u64 end, u32 id, u32 type,
struct drm_suballoc *prl_sa)
@@ -178,9 +171,12 @@ static int send_tlb_inval_ppgtt(struct xe_guc *guc, u32 seqno, u64 start,
struct xe_gt *gt = guc_to_gt(guc);
struct xe_device *xe = guc_to_xe(guc);
u32 action[MAX_TLB_INVALIDATION_LEN];
- u64 length = end - start;
+ u64 normalize_len;
int len = 0, err;
+ normalize_len = normalize_invalidation_range(gt, &start,
+ &end);
+
xe_gt_assert(gt, (type == XE_GUC_TLB_INVAL_PAGE_SELECTIVE &&
!xe->info.has_ctx_tlb_inval) ||
(type == XE_GUC_TLB_INVAL_PAGE_SELECTIVE_CTX &&
@@ -189,11 +185,9 @@ static int send_tlb_inval_ppgtt(struct xe_guc *guc, u32 seqno, u64 start,
action[len++] = XE_GUC_ACTION_TLB_INVALIDATION;
action[len++] = !prl_sa ? seqno : TLB_INVALIDATION_SEQNO_INVALID;
if (!gt_to_xe(gt)->info.has_range_tlb_inval ||
- length > MAX_RANGE_TLB_INVALIDATION_LENGTH) {
+ normalize_len > xe->info.max_tlb_inval_size) {
action[len++] = MAKE_INVAL_OP(XE_GUC_TLB_INVAL_FULL);
} else {
- u64 normalize_len = normalize_invalidation_range(gt, &start,
- &end);
bool need_flush = !prl_sa &&
seqno != TLB_INVALIDATION_SEQNO_INVALID;
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 189e2a1c29f9..5e02f9ab625b 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -743,6 +743,9 @@ static int xe_info_init_early(struct xe_device *xe,
xe->info.vm_max_level = desc->vm_max_level;
xe->info.vram_flags = desc->vram_flags;
+ xe->info.min_tlb_inval_size = desc->min_tlb_inval_size ?: SZ_4K;
+ xe->info.max_tlb_inval_size = desc->max_tlb_inval_size ?: SZ_1G;
+
xe->info.is_dgfx = desc->is_dgfx;
xe->info.has_cached_pt = desc->has_cached_pt;
xe->info.has_fan_control = desc->has_fan_control;
diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
index 8eee4fb1c57c..cd9d3ad96fe0 100644
--- a/drivers/gpu/drm/xe/xe_pci_types.h
+++ b/drivers/gpu/drm/xe/xe_pci_types.h
@@ -34,6 +34,8 @@ struct xe_device_desc {
u8 va_bits;
u8 vm_max_level;
u8 vram_flags;
+ u64 min_tlb_inval_size;
+ u64 max_tlb_inval_size;
u8 require_force_probe:1;
u8 is_dgfx:1;
--
2.43.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH] drm/xe: Add min and max context TLB invalidation sizes
2026-03-19 21:05 [PATCH] " Stuart Summers
@ 2026-03-19 21:11 ` Summers, Stuart
2026-03-19 21:36 ` Cavitt, Jonathan
2026-03-22 5:56 ` Matthew Brost
1 sibling, 1 reply; 15+ messages in thread
From: Summers, Stuart @ 2026-03-19 21:11 UTC (permalink / raw)
To: Summers, Stuart
Cc: intel-xe@lists.freedesktop.org, Brost, Matthew,
Vishwanathapura, Niranjana
On Thu, 2026-03-19 at 21:05 +0000, Stuart Summers wrote:
> Allow platform-defined TLB invalidation min and max lengths.
>
> This gives finer granular control to which invalidations we
> decide to send to GuC. The min size is essentially a round
> up. The max allows us to switch to a full invalidation.
>
> The expectation here is that GuC will translate the full
> invalidation in this instance into a series of per context
> invalidaitons. These are then issued with no H2G or G2H
> messages and therefore should be quicker than splitting
> the invalidations from the KMD in max size chunks and sending
> separately.
>
> v2: Add proper defaults for min/max if not set in the device
> structures
>
> Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> ---
> drivers/gpu/drm/xe/xe_device_types.h | 4 ++++
> drivers/gpu/drm/xe/xe_guc_tlb_inval.c | 20 +++++++-------------
> drivers/gpu/drm/xe/xe_pci.c | 3 +++
> drivers/gpu/drm/xe/xe_pci_types.h | 2 ++
> 4 files changed, 16 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h
> b/drivers/gpu/drm/xe/xe_device_types.h
> index 615218d775b1..0c4168fe2ffb 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -137,6 +137,10 @@ struct xe_device {
> u8 vm_max_level;
> /** @info.va_bits: Maximum bits of a virtual address
> */
> u8 va_bits;
> + /** @info.min_tlb_inval_size: Minimum size of context
> based TLB invalidations */
> + u64 min_tlb_inval_size;
> + /** @info.max_tlb_inval_size: Maximum size of context
> based TLB invalidations */
> + u64 max_tlb_inval_size;
>
> /*
> * Keep all flags below alphabetically sorted
> diff --git a/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
> b/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
> index eb40528976ca..7512f889a97a 100644
> --- a/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
> +++ b/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
> @@ -133,12 +133,12 @@ static int send_page_reclaim(struct xe_guc
> *guc, u32 seqno,
>
> static u64 normalize_invalidation_range(struct xe_gt *gt, u64
> *start, u64 *end)
> {
> + struct xe_device *xe = gt_to_xe(gt);
> u64 orig_start = *start;
> u64 length = *end - *start;
> u64 align;
>
> - if (length < SZ_4K)
> - length = SZ_4K;
> + length = max_t(u64, xe->info.min_tlb_inval_size, length);
>
> align = roundup_pow_of_two(length);
> *start = ALIGN_DOWN(*start, align);
> @@ -163,13 +163,6 @@ static u64 normalize_invalidation_range(struct
> xe_gt *gt, u64 *start, u64 *end)
> return length;
> }
>
> -/*
> - * Ensure that roundup_pow_of_two(length) doesn't overflow.
> - * Note that roundup_pow_of_two() operates on unsigned long,
> - * not on u64.
> - */
> -#define MAX_RANGE_TLB_INVALIDATION_LENGTH
> (rounddown_pow_of_two(ULONG_MAX))
> -
> static int send_tlb_inval_ppgtt(struct xe_guc *guc, u32 seqno, u64
> start,
> u64 end, u32 id, u32 type,
> struct drm_suballoc *prl_sa)
> @@ -178,9 +171,12 @@ static int send_tlb_inval_ppgtt(struct xe_guc
> *guc, u32 seqno, u64 start,
> struct xe_gt *gt = guc_to_gt(guc);
> struct xe_device *xe = guc_to_xe(guc);
> u32 action[MAX_TLB_INVALIDATION_LEN];
> - u64 length = end - start;
> + u64 normalize_len;
> int len = 0, err;
>
> + normalize_len = normalize_invalidation_range(gt, &start,
> + &end);
> +
> xe_gt_assert(gt, (type == XE_GUC_TLB_INVAL_PAGE_SELECTIVE &&
> !xe->info.has_ctx_tlb_inval) ||
> (type == XE_GUC_TLB_INVAL_PAGE_SELECTIVE_CTX &&
> @@ -189,11 +185,9 @@ static int send_tlb_inval_ppgtt(struct xe_guc
> *guc, u32 seqno, u64 start,
> action[len++] = XE_GUC_ACTION_TLB_INVALIDATION;
> action[len++] = !prl_sa ? seqno :
> TLB_INVALIDATION_SEQNO_INVALID;
> if (!gt_to_xe(gt)->info.has_range_tlb_inval ||
> - length > MAX_RANGE_TLB_INVALIDATION_LENGTH) {
> + normalize_len > xe->info.max_tlb_inval_size) {
> action[len++] = MAKE_INVAL_OP(XE_GUC_TLB_INVAL_FULL);
> } else {
> - u64 normalize_len = normalize_invalidation_range(gt,
> &start,
> -
> &end);
> bool need_flush = !prl_sa &&
> seqno != TLB_INVALIDATION_SEQNO_INVALID;
>
> diff --git a/drivers/gpu/drm/xe/xe_pci.c
> b/drivers/gpu/drm/xe/xe_pci.c
> index 189e2a1c29f9..5e02f9ab625b 100644
> --- a/drivers/gpu/drm/xe/xe_pci.c
> +++ b/drivers/gpu/drm/xe/xe_pci.c
> @@ -743,6 +743,9 @@ static int xe_info_init_early(struct xe_device
> *xe,
> xe->info.vm_max_level = desc->vm_max_level;
> xe->info.vram_flags = desc->vram_flags;
>
> + xe->info.min_tlb_inval_size = desc->min_tlb_inval_size ?:
> SZ_4K;
> + xe->info.max_tlb_inval_size = desc->max_tlb_inval_size ?:
> SZ_1G;
Basically I decided to get rid of the pathological case for now. I
figured 1G is a good happy medium for larger VMAs. Let me know if you
have any concerns there though.
Thanks,
Stuart
> +
> xe->info.is_dgfx = desc->is_dgfx;
> xe->info.has_cached_pt = desc->has_cached_pt;
> xe->info.has_fan_control = desc->has_fan_control;
> diff --git a/drivers/gpu/drm/xe/xe_pci_types.h
> b/drivers/gpu/drm/xe/xe_pci_types.h
> index 8eee4fb1c57c..cd9d3ad96fe0 100644
> --- a/drivers/gpu/drm/xe/xe_pci_types.h
> +++ b/drivers/gpu/drm/xe/xe_pci_types.h
> @@ -34,6 +34,8 @@ struct xe_device_desc {
> u8 va_bits;
> u8 vm_max_level;
> u8 vram_flags;
> + u64 min_tlb_inval_size;
> + u64 max_tlb_inval_size;
>
> u8 require_force_probe:1;
> u8 is_dgfx:1;
^ permalink raw reply [flat|nested] 15+ messages in thread
* RE: [PATCH] drm/xe: Add min and max context TLB invalidation sizes
2026-03-19 21:11 ` Summers, Stuart
@ 2026-03-19 21:36 ` Cavitt, Jonathan
2026-03-19 21:51 ` Summers, Stuart
0 siblings, 1 reply; 15+ messages in thread
From: Cavitt, Jonathan @ 2026-03-19 21:36 UTC (permalink / raw)
To: Summers, Stuart, Summers, Stuart
Cc: intel-xe@lists.freedesktop.org, Brost, Matthew,
Vishwanathapura, Niranjana, Cavitt, Jonathan
-----Original Message-----
From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Summers, Stuart
Sent: Thursday, March 19, 2026 2:12 PM
To: Summers, Stuart <stuart.summers@intel.com>
Cc: intel-xe@lists.freedesktop.org; Brost, Matthew <matthew.brost@intel.com>; Vishwanathapura, Niranjana <niranjana.vishwanathapura@intel.com>
Subject: Re: [PATCH] drm/xe: Add min and max context TLB invalidation sizes
>
> On Thu, 2026-03-19 at 21:05 +0000, Stuart Summers wrote:
> > Allow platform-defined TLB invalidation min and max lengths.
> >
> > This gives finer granular control to which invalidations we
> > decide to send to GuC. The min size is essentially a round
> > up. The max allows us to switch to a full invalidation.
> >
> > The expectation here is that GuC will translate the full
> > invalidation in this instance into a series of per context
> > invalidaitons. These are then issued with no H2G or G2H
> > messages and therefore should be quicker than splitting
> > the invalidations from the KMD in max size chunks and sending
> > separately.
> >
> > v2: Add proper defaults for min/max if not set in the device
> > structures
> >
> > Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> > ---
> > drivers/gpu/drm/xe/xe_device_types.h | 4 ++++
> > drivers/gpu/drm/xe/xe_guc_tlb_inval.c | 20 +++++++-------------
> > drivers/gpu/drm/xe/xe_pci.c | 3 +++
> > drivers/gpu/drm/xe/xe_pci_types.h | 2 ++
> > 4 files changed, 16 insertions(+), 13 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/xe/xe_device_types.h
> > b/drivers/gpu/drm/xe/xe_device_types.h
> > index 615218d775b1..0c4168fe2ffb 100644
> > --- a/drivers/gpu/drm/xe/xe_device_types.h
> > +++ b/drivers/gpu/drm/xe/xe_device_types.h
> > @@ -137,6 +137,10 @@ struct xe_device {
> > u8 vm_max_level;
> > /** @info.va_bits: Maximum bits of a virtual address
> > */
> > u8 va_bits;
> > + /** @info.min_tlb_inval_size: Minimum size of context
> > based TLB invalidations */
> > + u64 min_tlb_inval_size;
> > + /** @info.max_tlb_inval_size: Maximum size of context
> > based TLB invalidations */
> > + u64 max_tlb_inval_size;
> >
> > /*
> > * Keep all flags below alphabetically sorted
> > diff --git a/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
> > b/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
> > index eb40528976ca..7512f889a97a 100644
> > --- a/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
> > +++ b/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
> > @@ -133,12 +133,12 @@ static int send_page_reclaim(struct xe_guc
> > *guc, u32 seqno,
> >
> > static u64 normalize_invalidation_range(struct xe_gt *gt, u64
> > *start, u64 *end)
> > {
> > + struct xe_device *xe = gt_to_xe(gt);
> > u64 orig_start = *start;
> > u64 length = *end - *start;
> > u64 align;
> >
> > - if (length < SZ_4K)
> > - length = SZ_4K;
> > + length = max_t(u64, xe->info.min_tlb_inval_size, length);
> >
> > align = roundup_pow_of_two(length);
> > *start = ALIGN_DOWN(*start, align);
> > @@ -163,13 +163,6 @@ static u64 normalize_invalidation_range(struct
> > xe_gt *gt, u64 *start, u64 *end)
> > return length;
> > }
> >
> > -/*
> > - * Ensure that roundup_pow_of_two(length) doesn't overflow.
> > - * Note that roundup_pow_of_two() operates on unsigned long,
> > - * not on u64.
> > - */
> > -#define MAX_RANGE_TLB_INVALIDATION_LENGTH
> > (rounddown_pow_of_two(ULONG_MAX))
> > -
> > static int send_tlb_inval_ppgtt(struct xe_guc *guc, u32 seqno, u64
> > start,
> > u64 end, u32 id, u32 type,
> > struct drm_suballoc *prl_sa)
> > @@ -178,9 +171,12 @@ static int send_tlb_inval_ppgtt(struct xe_guc
> > *guc, u32 seqno, u64 start,
> > struct xe_gt *gt = guc_to_gt(guc);
> > struct xe_device *xe = guc_to_xe(guc);
> > u32 action[MAX_TLB_INVALIDATION_LEN];
> > - u64 length = end - start;
> > + u64 normalize_len;
> > int len = 0, err;
> >
> > + normalize_len = normalize_invalidation_range(gt, &start,
> > + &end);
> > +
> > xe_gt_assert(gt, (type == XE_GUC_TLB_INVAL_PAGE_SELECTIVE &&
> > !xe->info.has_ctx_tlb_inval) ||
> > (type == XE_GUC_TLB_INVAL_PAGE_SELECTIVE_CTX &&
> > @@ -189,11 +185,9 @@ static int send_tlb_inval_ppgtt(struct xe_guc
> > *guc, u32 seqno, u64 start,
> > action[len++] = XE_GUC_ACTION_TLB_INVALIDATION;
> > action[len++] = !prl_sa ? seqno :
> > TLB_INVALIDATION_SEQNO_INVALID;
> > if (!gt_to_xe(gt)->info.has_range_tlb_inval ||
> > - length > MAX_RANGE_TLB_INVALIDATION_LENGTH) {
> > + normalize_len > xe->info.max_tlb_inval_size) {
> > action[len++] = MAKE_INVAL_OP(XE_GUC_TLB_INVAL_FULL);
> > } else {
> > - u64 normalize_len = normalize_invalidation_range(gt,
> > &start,
> > -
> > &end);
> > bool need_flush = !prl_sa &&
> > seqno != TLB_INVALIDATION_SEQNO_INVALID;
> >
> > diff --git a/drivers/gpu/drm/xe/xe_pci.c
> > b/drivers/gpu/drm/xe/xe_pci.c
> > index 189e2a1c29f9..5e02f9ab625b 100644
> > --- a/drivers/gpu/drm/xe/xe_pci.c
> > +++ b/drivers/gpu/drm/xe/xe_pci.c
> > @@ -743,6 +743,9 @@ static int xe_info_init_early(struct xe_device
> > *xe,
> > xe->info.vm_max_level = desc->vm_max_level;
> > xe->info.vram_flags = desc->vram_flags;
> >
> > + xe->info.min_tlb_inval_size = desc->min_tlb_inval_size ?:
> > SZ_4K;
> > + xe->info.max_tlb_inval_size = desc->max_tlb_inval_size ?:
> > SZ_1G;
>
> Basically I decided to get rid of the pathological case for now. I
> figured 1G is a good happy medium for larger VMAs. Let me know if you
> have any concerns there though.
I was going to comment on this once I saw it, but you already considered
this issue. But yeah, SZ_1G seems to be only about 1/2 (or maybe 1/4
depending on how rounddown_pow_of_two operates on ULONG_MAX)
the size of the original MAX_RANGE_TLB_INVALIDATION_LENGTH value,
so I'd say it's probably fine.
This patch doesn't have any other major mechanical differences compared
to before its application, though there are some minor concerns regarding
normalize_invalidation_range:
1. There's an xe_gt_assert(gt, length >= SZ_4K); that was left unchanged in
this patch. We might want to target xe->info.min_tlb_inval_size instead?
2. Using normalize_invalidation_range immediately in send_tlb_inval_ppgtt
instead of initially operating on 'end - start' like before might result in more full
invalidation cases compared to before, as the function seems to return a value
that is more often than not larger than the raw 'end - start' value.
As long as you find these tradeoffs acceptable, I don't see any reason to block
on these concerns. Regardless of if you make changes based on these notes or not:
Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
-Jonathan Cavitt
>
> Thanks,
> Stuart
>
> > +
> > xe->info.is_dgfx = desc->is_dgfx;
> > xe->info.has_cached_pt = desc->has_cached_pt;
> > xe->info.has_fan_control = desc->has_fan_control;
> > diff --git a/drivers/gpu/drm/xe/xe_pci_types.h
> > b/drivers/gpu/drm/xe/xe_pci_types.h
> > index 8eee4fb1c57c..cd9d3ad96fe0 100644
> > --- a/drivers/gpu/drm/xe/xe_pci_types.h
> > +++ b/drivers/gpu/drm/xe/xe_pci_types.h
> > @@ -34,6 +34,8 @@ struct xe_device_desc {
> > u8 va_bits;
> > u8 vm_max_level;
> > u8 vram_flags;
> > + u64 min_tlb_inval_size;
> > + u64 max_tlb_inval_size;
> >
> > u8 require_force_probe:1;
> > u8 is_dgfx:1;
>
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH] drm/xe: Add min and max context TLB invalidation sizes
2026-03-19 21:36 ` Cavitt, Jonathan
@ 2026-03-19 21:51 ` Summers, Stuart
0 siblings, 0 replies; 15+ messages in thread
From: Summers, Stuart @ 2026-03-19 21:51 UTC (permalink / raw)
To: Cavitt, Jonathan
Cc: intel-xe@lists.freedesktop.org, Brost, Matthew,
Vishwanathapura, Niranjana
On Thu, 2026-03-19 at 21:36 +0000, Cavitt, Jonathan wrote:
> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of
> Summers, Stuart
> Sent: Thursday, March 19, 2026 2:12 PM
> To: Summers, Stuart <stuart.summers@intel.com>
> Cc: intel-xe@lists.freedesktop.org; Brost, Matthew
> <matthew.brost@intel.com>; Vishwanathapura, Niranjana
> <niranjana.vishwanathapura@intel.com>
> Subject: Re: [PATCH] drm/xe: Add min and max context TLB invalidation
> sizes
> >
> > On Thu, 2026-03-19 at 21:05 +0000, Stuart Summers wrote:
> > > Allow platform-defined TLB invalidation min and max lengths.
> > >
> > > This gives finer granular control to which invalidations we
> > > decide to send to GuC. The min size is essentially a round
> > > up. The max allows us to switch to a full invalidation.
> > >
> > > The expectation here is that GuC will translate the full
> > > invalidation in this instance into a series of per context
> > > invalidaitons. These are then issued with no H2G or G2H
> > > messages and therefore should be quicker than splitting
> > > the invalidations from the KMD in max size chunks and sending
> > > separately.
> > >
> > > v2: Add proper defaults for min/max if not set in the device
> > > structures
> > >
> > > Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> > > ---
> > > drivers/gpu/drm/xe/xe_device_types.h | 4 ++++
> > > drivers/gpu/drm/xe/xe_guc_tlb_inval.c | 20 +++++++-------------
> > > drivers/gpu/drm/xe/xe_pci.c | 3 +++
> > > drivers/gpu/drm/xe/xe_pci_types.h | 2 ++
> > > 4 files changed, 16 insertions(+), 13 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/xe/xe_device_types.h
> > > b/drivers/gpu/drm/xe/xe_device_types.h
> > > index 615218d775b1..0c4168fe2ffb 100644
> > > --- a/drivers/gpu/drm/xe/xe_device_types.h
> > > +++ b/drivers/gpu/drm/xe/xe_device_types.h
> > > @@ -137,6 +137,10 @@ struct xe_device {
> > > u8 vm_max_level;
> > > /** @info.va_bits: Maximum bits of a virtual
> > > address
> > > */
> > > u8 va_bits;
> > > + /** @info.min_tlb_inval_size: Minimum size of
> > > context
> > > based TLB invalidations */
> > > + u64 min_tlb_inval_size;
> > > + /** @info.max_tlb_inval_size: Maximum size of
> > > context
> > > based TLB invalidations */
> > > + u64 max_tlb_inval_size;
> > >
> > > /*
> > > * Keep all flags below alphabetically sorted
> > > diff --git a/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
> > > b/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
> > > index eb40528976ca..7512f889a97a 100644
> > > --- a/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
> > > +++ b/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
> > > @@ -133,12 +133,12 @@ static int send_page_reclaim(struct xe_guc
> > > *guc, u32 seqno,
> > >
> > > static u64 normalize_invalidation_range(struct xe_gt *gt, u64
> > > *start, u64 *end)
> > > {
> > > + struct xe_device *xe = gt_to_xe(gt);
> > > u64 orig_start = *start;
> > > u64 length = *end - *start;
> > > u64 align;
> > >
> > > - if (length < SZ_4K)
> > > - length = SZ_4K;
> > > + length = max_t(u64, xe->info.min_tlb_inval_size, length);
> > >
> > > align = roundup_pow_of_two(length);
> > > *start = ALIGN_DOWN(*start, align);
> > > @@ -163,13 +163,6 @@ static u64
> > > normalize_invalidation_range(struct
> > > xe_gt *gt, u64 *start, u64 *end)
> > > return length;
> > > }
> > >
> > > -/*
> > > - * Ensure that roundup_pow_of_two(length) doesn't overflow.
> > > - * Note that roundup_pow_of_two() operates on unsigned long,
> > > - * not on u64.
> > > - */
> > > -#define MAX_RANGE_TLB_INVALIDATION_LENGTH
> > > (rounddown_pow_of_two(ULONG_MAX))
> > > -
> > > static int send_tlb_inval_ppgtt(struct xe_guc *guc, u32 seqno,
> > > u64
> > > start,
> > > u64 end, u32 id, u32 type,
> > > struct drm_suballoc *prl_sa)
> > > @@ -178,9 +171,12 @@ static int send_tlb_inval_ppgtt(struct
> > > xe_guc
> > > *guc, u32 seqno, u64 start,
> > > struct xe_gt *gt = guc_to_gt(guc);
> > > struct xe_device *xe = guc_to_xe(guc);
> > > u32 action[MAX_TLB_INVALIDATION_LEN];
> > > - u64 length = end - start;
> > > + u64 normalize_len;
> > > int len = 0, err;
> > >
> > > + normalize_len = normalize_invalidation_range(gt, &start,
> > > + &end);
> > > +
> > > xe_gt_assert(gt, (type == XE_GUC_TLB_INVAL_PAGE_SELECTIVE
> > > &&
> > > !xe->info.has_ctx_tlb_inval) ||
> > > (type == XE_GUC_TLB_INVAL_PAGE_SELECTIVE_CTX
> > > &&
> > > @@ -189,11 +185,9 @@ static int send_tlb_inval_ppgtt(struct
> > > xe_guc
> > > *guc, u32 seqno, u64 start,
> > > action[len++] = XE_GUC_ACTION_TLB_INVALIDATION;
> > > action[len++] = !prl_sa ? seqno :
> > > TLB_INVALIDATION_SEQNO_INVALID;
> > > if (!gt_to_xe(gt)->info.has_range_tlb_inval ||
> > > - length > MAX_RANGE_TLB_INVALIDATION_LENGTH) {
> > > + normalize_len > xe->info.max_tlb_inval_size) {
> > > action[len++] =
> > > MAKE_INVAL_OP(XE_GUC_TLB_INVAL_FULL);
> > > } else {
> > > - u64 normalize_len =
> > > normalize_invalidation_range(gt,
> > > &start,
> > > -
> > > &end);
> > > bool need_flush = !prl_sa &&
> > > seqno != TLB_INVALIDATION_SEQNO_INVALID;
> > >
> > > diff --git a/drivers/gpu/drm/xe/xe_pci.c
> > > b/drivers/gpu/drm/xe/xe_pci.c
> > > index 189e2a1c29f9..5e02f9ab625b 100644
> > > --- a/drivers/gpu/drm/xe/xe_pci.c
> > > +++ b/drivers/gpu/drm/xe/xe_pci.c
> > > @@ -743,6 +743,9 @@ static int xe_info_init_early(struct
> > > xe_device
> > > *xe,
> > > xe->info.vm_max_level = desc->vm_max_level;
> > > xe->info.vram_flags = desc->vram_flags;
> > >
> > > + xe->info.min_tlb_inval_size = desc->min_tlb_inval_size ?:
> > > SZ_4K;
> > > + xe->info.max_tlb_inval_size = desc->max_tlb_inval_size ?:
> > > SZ_1G;
> >
> > Basically I decided to get rid of the pathological case for now. I
> > figured 1G is a good happy medium for larger VMAs. Let me know if
> > you
> > have any concerns there though.
>
> I was going to comment on this once I saw it, but you already
> considered
> this issue. But yeah, SZ_1G seems to be only about 1/2 (or maybe 1/4
> depending on how rounddown_pow_of_two operates on ULONG_MAX)
> the size of the original MAX_RANGE_TLB_INVALIDATION_LENGTH value,
> so I'd say it's probably fine.
>
> This patch doesn't have any other major mechanical differences
> compared
> to before its application, though there are some minor concerns
> regarding
> normalize_invalidation_range:
>
> 1. There's an xe_gt_assert(gt, length >= SZ_4K); that was left
> unchanged in
> this patch. We might want to target xe->info.min_tlb_inval_size
> instead?
Thanks for the review Jonathan!
So my thought here is that from the spec, we need to have 4K aligned
pages here. The interface in xe_pci.c isn't really doing any validation
of the values we are providing through the various per platform
structures, so this is kind of a guarantee that we are at least
following that requirement. The max_t() call is what is being used to
make sure the value is aligned to the min value - which per the assert
should be at least 4K.
> 2. Using normalize_invalidation_range immediately in
> send_tlb_inval_ppgtt
> instead of initially operating on 'end - start' like before might
> result in more full
> invalidation cases compared to before, as the function seems to
> return a value
> that is more often than not larger than the raw 'end - start' value.
Yeah that's true. I think there's going to be some tradeoff here of
doing a full invalidation vs a series of smaller range invalidations if
the size is large enough. From the hardware perspective, we might get
more performance out of just invalidating everything. We already have
code to do this in the context invalidation sequence, and this takes a
similar approach.
>
> As long as you find these tradeoffs acceptable, I don't see any
> reason to block
> on these concerns. Regardless of if you make changes based on these
> notes or not:
>
> Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
Thanks!
Stuart
> -Jonathan Cavitt
>
> >
> > Thanks,
> > Stuart
> >
> > > +
> > > xe->info.is_dgfx = desc->is_dgfx;
> > > xe->info.has_cached_pt = desc->has_cached_pt;
> > > xe->info.has_fan_control = desc->has_fan_control;
> > > diff --git a/drivers/gpu/drm/xe/xe_pci_types.h
> > > b/drivers/gpu/drm/xe/xe_pci_types.h
> > > index 8eee4fb1c57c..cd9d3ad96fe0 100644
> > > --- a/drivers/gpu/drm/xe/xe_pci_types.h
> > > +++ b/drivers/gpu/drm/xe/xe_pci_types.h
> > > @@ -34,6 +34,8 @@ struct xe_device_desc {
> > > u8 va_bits;
> > > u8 vm_max_level;
> > > u8 vram_flags;
> > > + u64 min_tlb_inval_size;
> > > + u64 max_tlb_inval_size;
> > >
> > > u8 require_force_probe:1;
> > > u8 is_dgfx:1;
> >
> >
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH] drm/xe: Add min and max context TLB invalidation sizes
@ 2026-03-20 20:46 Stuart Summers
2026-03-20 20:49 ` Summers, Stuart
2026-03-23 17:23 ` Matthew Brost
0 siblings, 2 replies; 15+ messages in thread
From: Stuart Summers @ 2026-03-20 20:46 UTC (permalink / raw)
Cc: intel-xe, matthew.brost, niranjana.vishwanathapura,
jonathan.cavitt, Stuart Summers
Allow platform-defined TLB invalidation min and max lengths.
This gives finer granular control to which invalidations we
decide to send to GuC. The min size is essentially a round
up. The max allows us to switch to a full invalidation.
The expectation here is that GuC will translate the full
invalidation in this instance into a series of per context
invalidaitons. These are then issued with no H2G or G2H
messages and therefore should be quicker than splitting
the invalidations from the KMD in max size chunks and sending
separately.
v2: Add proper defaults for min/max if not set in the device
structures
v3: Add coverage for pow-of-2 out of bounds cases
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
---
drivers/gpu/drm/xe/xe_device_types.h | 4 +++
drivers/gpu/drm/xe/xe_guc_tlb_inval.c | 39 +++++++++++++++++----------
drivers/gpu/drm/xe/xe_pci.c | 3 +++
drivers/gpu/drm/xe/xe_pci_types.h | 2 ++
4 files changed, 34 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 615218d775b1..0c4168fe2ffb 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -137,6 +137,10 @@ struct xe_device {
u8 vm_max_level;
/** @info.va_bits: Maximum bits of a virtual address */
u8 va_bits;
+ /** @info.min_tlb_inval_size: Minimum size of context based TLB invalidations */
+ u64 min_tlb_inval_size;
+ /** @info.max_tlb_inval_size: Maximum size of context based TLB invalidations */
+ u64 max_tlb_inval_size;
/*
* Keep all flags below alphabetically sorted
diff --git a/drivers/gpu/drm/xe/xe_guc_tlb_inval.c b/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
index ced58f46f846..e9e0be94ceef 100644
--- a/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
+++ b/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
@@ -115,14 +115,23 @@ static int send_page_reclaim(struct xe_guc *guc, u32 seqno,
G2H_LEN_DW_PAGE_RECLAMATION, 1);
}
+/*
+ * Ensure that roundup_pow_of_two(length) doesn't overflow.
+ * Note that roundup_pow_of_two() operates on unsigned long,
+ * not on u64.
+ */
+#define MAX_RANGE_TLB_INVALIDATION_LENGTH (rounddown_pow_of_two(ULONG_MAX))
+
static u64 normalize_invalidation_range(struct xe_gt *gt, u64 *start, u64 *end)
{
+ struct xe_device *xe = gt_to_xe(gt);
u64 orig_start = *start;
u64 length = *end - *start;
u64 align;
- if (length < SZ_4K)
- length = SZ_4K;
+ xe_gt_assert(gt, length <= MAX_RANGE_TLB_INVALIDATION_LENGTH);
+
+ length = max_t(u64, xe->info.min_tlb_inval_size, length);
align = roundup_pow_of_two(length);
*start = ALIGN_DOWN(*start, align);
@@ -147,13 +156,6 @@ static u64 normalize_invalidation_range(struct xe_gt *gt, u64 *start, u64 *end)
return length;
}
-/*
- * Ensure that roundup_pow_of_two(length) doesn't overflow.
- * Note that roundup_pow_of_two() operates on unsigned long,
- * not on u64.
- */
-#define MAX_RANGE_TLB_INVALIDATION_LENGTH (rounddown_pow_of_two(ULONG_MAX))
-
static int send_tlb_inval_ppgtt(struct xe_guc *guc, u32 seqno, u64 start,
u64 end, u32 id, u32 type,
struct drm_suballoc *prl_sa)
@@ -162,8 +164,20 @@ static int send_tlb_inval_ppgtt(struct xe_guc *guc, u32 seqno, u64 start,
struct xe_gt *gt = guc_to_gt(guc);
struct xe_device *xe = guc_to_xe(guc);
u32 action[MAX_TLB_INVALIDATION_LEN];
- u64 length = end - start;
+ u64 normalize_len, length = end - start;
int len = 0, err;
+ bool do_full_inval = false;
+
+ if (!xe->info.has_range_tlb_inval ||
+ length > MAX_RANGE_TLB_INVALIDATION_LENGTH) {
+ do_full_inval = true;
+ } else {
+ normalize_len = normalize_invalidation_range(gt, &start,
+ &end);
+
+ if (normalize_len > xe->info.max_tlb_inval_size)
+ do_full_inval = true;
+ }
xe_gt_assert(gt, (type == XE_GUC_TLB_INVAL_PAGE_SELECTIVE &&
!xe->info.has_ctx_tlb_inval) ||
@@ -172,12 +186,9 @@ static int send_tlb_inval_ppgtt(struct xe_guc *guc, u32 seqno, u64 start,
action[len++] = XE_GUC_ACTION_TLB_INVALIDATION;
action[len++] = !prl_sa ? seqno : TLB_INVALIDATION_SEQNO_INVALID;
- if (!gt_to_xe(gt)->info.has_range_tlb_inval ||
- length > MAX_RANGE_TLB_INVALIDATION_LENGTH) {
+ if (do_full_inval) {
action[len++] = MAKE_INVAL_OP(XE_GUC_TLB_INVAL_FULL);
} else {
- u64 normalize_len = normalize_invalidation_range(gt, &start,
- &end);
bool need_flush = !prl_sa &&
seqno != TLB_INVALIDATION_SEQNO_INVALID;
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 189e2a1c29f9..5e02f9ab625b 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -743,6 +743,9 @@ static int xe_info_init_early(struct xe_device *xe,
xe->info.vm_max_level = desc->vm_max_level;
xe->info.vram_flags = desc->vram_flags;
+ xe->info.min_tlb_inval_size = desc->min_tlb_inval_size ?: SZ_4K;
+ xe->info.max_tlb_inval_size = desc->max_tlb_inval_size ?: SZ_1G;
+
xe->info.is_dgfx = desc->is_dgfx;
xe->info.has_cached_pt = desc->has_cached_pt;
xe->info.has_fan_control = desc->has_fan_control;
diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
index 8eee4fb1c57c..cd9d3ad96fe0 100644
--- a/drivers/gpu/drm/xe/xe_pci_types.h
+++ b/drivers/gpu/drm/xe/xe_pci_types.h
@@ -34,6 +34,8 @@ struct xe_device_desc {
u8 va_bits;
u8 vm_max_level;
u8 vram_flags;
+ u64 min_tlb_inval_size;
+ u64 max_tlb_inval_size;
u8 require_force_probe:1;
u8 is_dgfx:1;
--
2.43.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH] drm/xe: Add min and max context TLB invalidation sizes
2026-03-20 20:46 Stuart Summers
@ 2026-03-20 20:49 ` Summers, Stuart
2026-03-20 20:59 ` Cavitt, Jonathan
2026-03-23 17:23 ` Matthew Brost
1 sibling, 1 reply; 15+ messages in thread
From: Summers, Stuart @ 2026-03-20 20:49 UTC (permalink / raw)
To: Summers, Stuart
Cc: intel-xe@lists.freedesktop.org, Brost, Matthew,
Vishwanathapura, Niranjana, Cavitt, Jonathan
On Fri, 2026-03-20 at 20:46 +0000, Stuart Summers wrote:
> Allow platform-defined TLB invalidation min and max lengths.
>
> This gives finer granular control to which invalidations we
> decide to send to GuC. The min size is essentially a round
> up. The max allows us to switch to a full invalidation.
>
> The expectation here is that GuC will translate the full
> invalidation in this instance into a series of per context
> invalidaitons. These are then issued with no H2G or G2H
> messages and therefore should be quicker than splitting
> the invalidations from the KMD in max size chunks and sending
> separately.
>
> v2: Add proper defaults for min/max if not set in the device
> structures
> v3: Add coverage for pow-of-2 out of bounds cases
>
> Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
Jonathan, I left your R-B on here with these latest changes since
they're mostly covering a corner case on top of what I had. But let me
know if you'd like any changes here and I'm happy to address.
Thanks,
Stuart
> ---
> drivers/gpu/drm/xe/xe_device_types.h | 4 +++
> drivers/gpu/drm/xe/xe_guc_tlb_inval.c | 39 +++++++++++++++++--------
> --
> drivers/gpu/drm/xe/xe_pci.c | 3 +++
> drivers/gpu/drm/xe/xe_pci_types.h | 2 ++
> 4 files changed, 34 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h
> b/drivers/gpu/drm/xe/xe_device_types.h
> index 615218d775b1..0c4168fe2ffb 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -137,6 +137,10 @@ struct xe_device {
> u8 vm_max_level;
> /** @info.va_bits: Maximum bits of a virtual address
> */
> u8 va_bits;
> + /** @info.min_tlb_inval_size: Minimum size of context
> based TLB invalidations */
> + u64 min_tlb_inval_size;
> + /** @info.max_tlb_inval_size: Maximum size of context
> based TLB invalidations */
> + u64 max_tlb_inval_size;
>
> /*
> * Keep all flags below alphabetically sorted
> diff --git a/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
> b/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
> index ced58f46f846..e9e0be94ceef 100644
> --- a/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
> +++ b/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
> @@ -115,14 +115,23 @@ static int send_page_reclaim(struct xe_guc
> *guc, u32 seqno,
> G2H_LEN_DW_PAGE_RECLAMATION, 1);
> }
>
> +/*
> + * Ensure that roundup_pow_of_two(length) doesn't overflow.
> + * Note that roundup_pow_of_two() operates on unsigned long,
> + * not on u64.
> + */
> +#define MAX_RANGE_TLB_INVALIDATION_LENGTH
> (rounddown_pow_of_two(ULONG_MAX))
> +
> static u64 normalize_invalidation_range(struct xe_gt *gt, u64
> *start, u64 *end)
> {
> + struct xe_device *xe = gt_to_xe(gt);
> u64 orig_start = *start;
> u64 length = *end - *start;
> u64 align;
>
> - if (length < SZ_4K)
> - length = SZ_4K;
> + xe_gt_assert(gt, length <=
> MAX_RANGE_TLB_INVALIDATION_LENGTH);
> +
> + length = max_t(u64, xe->info.min_tlb_inval_size, length);
>
> align = roundup_pow_of_two(length);
> *start = ALIGN_DOWN(*start, align);
> @@ -147,13 +156,6 @@ static u64 normalize_invalidation_range(struct
> xe_gt *gt, u64 *start, u64 *end)
> return length;
> }
>
> -/*
> - * Ensure that roundup_pow_of_two(length) doesn't overflow.
> - * Note that roundup_pow_of_two() operates on unsigned long,
> - * not on u64.
> - */
> -#define MAX_RANGE_TLB_INVALIDATION_LENGTH
> (rounddown_pow_of_two(ULONG_MAX))
> -
> static int send_tlb_inval_ppgtt(struct xe_guc *guc, u32 seqno, u64
> start,
> u64 end, u32 id, u32 type,
> struct drm_suballoc *prl_sa)
> @@ -162,8 +164,20 @@ static int send_tlb_inval_ppgtt(struct xe_guc
> *guc, u32 seqno, u64 start,
> struct xe_gt *gt = guc_to_gt(guc);
> struct xe_device *xe = guc_to_xe(guc);
> u32 action[MAX_TLB_INVALIDATION_LEN];
> - u64 length = end - start;
> + u64 normalize_len, length = end - start;
> int len = 0, err;
> + bool do_full_inval = false;
> +
> + if (!xe->info.has_range_tlb_inval ||
> + length > MAX_RANGE_TLB_INVALIDATION_LENGTH) {
> + do_full_inval = true;
> + } else {
> + normalize_len = normalize_invalidation_range(gt,
> &start,
> + &end);
> +
> + if (normalize_len > xe->info.max_tlb_inval_size)
> + do_full_inval = true;
> + }
>
> xe_gt_assert(gt, (type == XE_GUC_TLB_INVAL_PAGE_SELECTIVE &&
> !xe->info.has_ctx_tlb_inval) ||
> @@ -172,12 +186,9 @@ static int send_tlb_inval_ppgtt(struct xe_guc
> *guc, u32 seqno, u64 start,
>
> action[len++] = XE_GUC_ACTION_TLB_INVALIDATION;
> action[len++] = !prl_sa ? seqno :
> TLB_INVALIDATION_SEQNO_INVALID;
> - if (!gt_to_xe(gt)->info.has_range_tlb_inval ||
> - length > MAX_RANGE_TLB_INVALIDATION_LENGTH) {
> + if (do_full_inval) {
> action[len++] = MAKE_INVAL_OP(XE_GUC_TLB_INVAL_FULL);
> } else {
> - u64 normalize_len = normalize_invalidation_range(gt,
> &start,
> -
> &end);
> bool need_flush = !prl_sa &&
> seqno != TLB_INVALIDATION_SEQNO_INVALID;
>
> diff --git a/drivers/gpu/drm/xe/xe_pci.c
> b/drivers/gpu/drm/xe/xe_pci.c
> index 189e2a1c29f9..5e02f9ab625b 100644
> --- a/drivers/gpu/drm/xe/xe_pci.c
> +++ b/drivers/gpu/drm/xe/xe_pci.c
> @@ -743,6 +743,9 @@ static int xe_info_init_early(struct xe_device
> *xe,
> xe->info.vm_max_level = desc->vm_max_level;
> xe->info.vram_flags = desc->vram_flags;
>
> + xe->info.min_tlb_inval_size = desc->min_tlb_inval_size ?:
> SZ_4K;
> + xe->info.max_tlb_inval_size = desc->max_tlb_inval_size ?:
> SZ_1G;
> +
> xe->info.is_dgfx = desc->is_dgfx;
> xe->info.has_cached_pt = desc->has_cached_pt;
> xe->info.has_fan_control = desc->has_fan_control;
> diff --git a/drivers/gpu/drm/xe/xe_pci_types.h
> b/drivers/gpu/drm/xe/xe_pci_types.h
> index 8eee4fb1c57c..cd9d3ad96fe0 100644
> --- a/drivers/gpu/drm/xe/xe_pci_types.h
> +++ b/drivers/gpu/drm/xe/xe_pci_types.h
> @@ -34,6 +34,8 @@ struct xe_device_desc {
> u8 va_bits;
> u8 vm_max_level;
> u8 vram_flags;
> + u64 min_tlb_inval_size;
> + u64 max_tlb_inval_size;
>
> u8 require_force_probe:1;
> u8 is_dgfx:1;
^ permalink raw reply [flat|nested] 15+ messages in thread
* RE: [PATCH] drm/xe: Add min and max context TLB invalidation sizes
2026-03-20 20:49 ` Summers, Stuart
@ 2026-03-20 20:59 ` Cavitt, Jonathan
0 siblings, 0 replies; 15+ messages in thread
From: Cavitt, Jonathan @ 2026-03-20 20:59 UTC (permalink / raw)
To: Summers, Stuart
Cc: intel-xe@lists.freedesktop.org, Brost, Matthew,
Vishwanathapura, Niranjana, Cavitt, Jonathan
-----Original Message-----
From: Summers, Stuart <stuart.summers@intel.com>
Sent: Friday, March 20, 2026 1:50 PM
To: Summers, Stuart <stuart.summers@intel.com>
Cc: intel-xe@lists.freedesktop.org; Brost, Matthew <matthew.brost@intel.com>; Vishwanathapura, Niranjana <niranjana.vishwanathapura@intel.com>; Cavitt, Jonathan <jonathan.cavitt@intel.com>
Subject: Re: [PATCH] drm/xe: Add min and max context TLB invalidation sizes
>
> On Fri, 2026-03-20 at 20:46 +0000, Stuart Summers wrote:
> > Allow platform-defined TLB invalidation min and max lengths.
> >
> > This gives finer granular control to which invalidations we
> > decide to send to GuC. The min size is essentially a round
> > up. The max allows us to switch to a full invalidation.
> >
> > The expectation here is that GuC will translate the full
> > invalidation in this instance into a series of per context
> > invalidaitons. These are then issued with no H2G or G2H
> > messages and therefore should be quicker than splitting
> > the invalidations from the KMD in max size chunks and sending
> > separately.
> >
> > v2: Add proper defaults for min/max if not set in the device
> > structures
> > v3: Add coverage for pow-of-2 out of bounds cases
> >
> > Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> > Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
>
> Jonathan, I left your R-B on here with these latest changes since
> they're mostly covering a corner case on top of what I had. But let me
> know if you'd like any changes here and I'm happy to address.
>
> Thanks,
> Stuart
>
> > ---
> > drivers/gpu/drm/xe/xe_device_types.h | 4 +++
> > drivers/gpu/drm/xe/xe_guc_tlb_inval.c | 39 +++++++++++++++++--------
> > --
> > drivers/gpu/drm/xe/xe_pci.c | 3 +++
> > drivers/gpu/drm/xe/xe_pci_types.h | 2 ++
> > 4 files changed, 34 insertions(+), 14 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/xe/xe_device_types.h
> > b/drivers/gpu/drm/xe/xe_device_types.h
> > index 615218d775b1..0c4168fe2ffb 100644
> > --- a/drivers/gpu/drm/xe/xe_device_types.h
> > +++ b/drivers/gpu/drm/xe/xe_device_types.h
> > @@ -137,6 +137,10 @@ struct xe_device {
> > u8 vm_max_level;
> > /** @info.va_bits: Maximum bits of a virtual address
> > */
> > u8 va_bits;
> > + /** @info.min_tlb_inval_size: Minimum size of context
> > based TLB invalidations */
> > + u64 min_tlb_inval_size;
> > + /** @info.max_tlb_inval_size: Maximum size of context
> > based TLB invalidations */
> > + u64 max_tlb_inval_size;
> >
> > /*
> > * Keep all flags below alphabetically sorted
> > diff --git a/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
> > b/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
> > index ced58f46f846..e9e0be94ceef 100644
> > --- a/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
> > +++ b/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
> > @@ -115,14 +115,23 @@ static int send_page_reclaim(struct xe_guc
> > *guc, u32 seqno,
> > G2H_LEN_DW_PAGE_RECLAMATION, 1);
> > }
> >
> > +/*
> > + * Ensure that roundup_pow_of_two(length) doesn't overflow.
> > + * Note that roundup_pow_of_two() operates on unsigned long,
> > + * not on u64.
> > + */
> > +#define MAX_RANGE_TLB_INVALIDATION_LENGTH
> > (rounddown_pow_of_two(ULONG_MAX))
> > +
> > static u64 normalize_invalidation_range(struct xe_gt *gt, u64
> > *start, u64 *end)
> > {
> > + struct xe_device *xe = gt_to_xe(gt);
> > u64 orig_start = *start;
> > u64 length = *end - *start;
> > u64 align;
> >
> > - if (length < SZ_4K)
> > - length = SZ_4K;
> > + xe_gt_assert(gt, length <=
> > MAX_RANGE_TLB_INVALIDATION_LENGTH);
I think it might make more sense to use max_tlb_inval_size from
xe->info here, but I take it we're more concerned here about a
possible type overflow than we are about us exceeding the TLB
invalidation size limit at this point in execution.
My RB still stands.
-Jonathan Cavitt
> > +
> > + length = max_t(u64, xe->info.min_tlb_inval_size, length);
> >
> > align = roundup_pow_of_two(length);
> > *start = ALIGN_DOWN(*start, align);
> > @@ -147,13 +156,6 @@ static u64 normalize_invalidation_range(struct
> > xe_gt *gt, u64 *start, u64 *end)
> > return length;
> > }
> >
> > -/*
> > - * Ensure that roundup_pow_of_two(length) doesn't overflow.
> > - * Note that roundup_pow_of_two() operates on unsigned long,
> > - * not on u64.
> > - */
> > -#define MAX_RANGE_TLB_INVALIDATION_LENGTH
> > (rounddown_pow_of_two(ULONG_MAX))
> > -
> > static int send_tlb_inval_ppgtt(struct xe_guc *guc, u32 seqno, u64
> > start,
> > u64 end, u32 id, u32 type,
> > struct drm_suballoc *prl_sa)
> > @@ -162,8 +164,20 @@ static int send_tlb_inval_ppgtt(struct xe_guc
> > *guc, u32 seqno, u64 start,
> > struct xe_gt *gt = guc_to_gt(guc);
> > struct xe_device *xe = guc_to_xe(guc);
> > u32 action[MAX_TLB_INVALIDATION_LEN];
> > - u64 length = end - start;
> > + u64 normalize_len, length = end - start;
> > int len = 0, err;
> > + bool do_full_inval = false;
> > +
> > + if (!xe->info.has_range_tlb_inval ||
> > + length > MAX_RANGE_TLB_INVALIDATION_LENGTH) {
> > + do_full_inval = true;
> > + } else {
> > + normalize_len = normalize_invalidation_range(gt,
> > &start,
> > + &end);
> > +
> > + if (normalize_len > xe->info.max_tlb_inval_size)
> > + do_full_inval = true;
> > + }
> >
> > xe_gt_assert(gt, (type == XE_GUC_TLB_INVAL_PAGE_SELECTIVE &&
> > !xe->info.has_ctx_tlb_inval) ||
> > @@ -172,12 +186,9 @@ static int send_tlb_inval_ppgtt(struct xe_guc
> > *guc, u32 seqno, u64 start,
> >
> > action[len++] = XE_GUC_ACTION_TLB_INVALIDATION;
> > action[len++] = !prl_sa ? seqno :
> > TLB_INVALIDATION_SEQNO_INVALID;
> > - if (!gt_to_xe(gt)->info.has_range_tlb_inval ||
> > - length > MAX_RANGE_TLB_INVALIDATION_LENGTH) {
> > + if (do_full_inval) {
> > action[len++] = MAKE_INVAL_OP(XE_GUC_TLB_INVAL_FULL);
> > } else {
> > - u64 normalize_len = normalize_invalidation_range(gt,
> > &start,
> > -
> > &end);
> > bool need_flush = !prl_sa &&
> > seqno != TLB_INVALIDATION_SEQNO_INVALID;
> >
> > diff --git a/drivers/gpu/drm/xe/xe_pci.c
> > b/drivers/gpu/drm/xe/xe_pci.c
> > index 189e2a1c29f9..5e02f9ab625b 100644
> > --- a/drivers/gpu/drm/xe/xe_pci.c
> > +++ b/drivers/gpu/drm/xe/xe_pci.c
> > @@ -743,6 +743,9 @@ static int xe_info_init_early(struct xe_device
> > *xe,
> > xe->info.vm_max_level = desc->vm_max_level;
> > xe->info.vram_flags = desc->vram_flags;
> >
> > + xe->info.min_tlb_inval_size = desc->min_tlb_inval_size ?:
> > SZ_4K;
> > + xe->info.max_tlb_inval_size = desc->max_tlb_inval_size ?:
> > SZ_1G;
> > +
> > xe->info.is_dgfx = desc->is_dgfx;
> > xe->info.has_cached_pt = desc->has_cached_pt;
> > xe->info.has_fan_control = desc->has_fan_control;
> > diff --git a/drivers/gpu/drm/xe/xe_pci_types.h
> > b/drivers/gpu/drm/xe/xe_pci_types.h
> > index 8eee4fb1c57c..cd9d3ad96fe0 100644
> > --- a/drivers/gpu/drm/xe/xe_pci_types.h
> > +++ b/drivers/gpu/drm/xe/xe_pci_types.h
> > @@ -34,6 +34,8 @@ struct xe_device_desc {
> > u8 va_bits;
> > u8 vm_max_level;
> > u8 vram_flags;
> > + u64 min_tlb_inval_size;
> > + u64 max_tlb_inval_size;
> >
> > u8 require_force_probe:1;
> > u8 is_dgfx:1;
>
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH] drm/xe: Add min and max context TLB invalidation sizes
2026-03-19 21:05 [PATCH] " Stuart Summers
2026-03-19 21:11 ` Summers, Stuart
@ 2026-03-22 5:56 ` Matthew Brost
2026-03-23 19:22 ` Summers, Stuart
1 sibling, 1 reply; 15+ messages in thread
From: Matthew Brost @ 2026-03-22 5:56 UTC (permalink / raw)
To: Stuart Summers; +Cc: niranjana.vishwanathapura, intel-xe
On Thu, Mar 19, 2026 at 09:05:32PM +0000, Stuart Summers wrote:
> Allow platform-defined TLB invalidation min and max lengths.
>
> This gives finer granular control to which invalidations we
> decide to send to GuC. The min size is essentially a round
> up. The max allows us to switch to a full invalidation.
>
> The expectation here is that GuC will translate the full
> invalidation in this instance into a series of per context
> invalidaitons. These are then issued with no H2G or G2H
> messages and therefore should be quicker than splitting
> the invalidations from the KMD in max size chunks and sending
> separately.
>
> v2: Add proper defaults for min/max if not set in the device
> structures
>
> Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> ---
> drivers/gpu/drm/xe/xe_device_types.h | 4 ++++
> drivers/gpu/drm/xe/xe_guc_tlb_inval.c | 20 +++++++-------------
> drivers/gpu/drm/xe/xe_pci.c | 3 +++
> drivers/gpu/drm/xe/xe_pci_types.h | 2 ++
> 4 files changed, 16 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index 615218d775b1..0c4168fe2ffb 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -137,6 +137,10 @@ struct xe_device {
> u8 vm_max_level;
> /** @info.va_bits: Maximum bits of a virtual address */
> u8 va_bits;
> + /** @info.min_tlb_inval_size: Minimum size of context based TLB invalidations */
> + u64 min_tlb_inval_size;
> + /** @info.max_tlb_inval_size: Maximum size of context based TLB invalidations */
> + u64 max_tlb_inval_size;
>
> /*
> * Keep all flags below alphabetically sorted
> diff --git a/drivers/gpu/drm/xe/xe_guc_tlb_inval.c b/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
> index eb40528976ca..7512f889a97a 100644
> --- a/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
> +++ b/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
> @@ -133,12 +133,12 @@ static int send_page_reclaim(struct xe_guc *guc, u32 seqno,
>
> static u64 normalize_invalidation_range(struct xe_gt *gt, u64 *start, u64 *end)
> {
> + struct xe_device *xe = gt_to_xe(gt);
> u64 orig_start = *start;
> u64 length = *end - *start;
> u64 align;
>
> - if (length < SZ_4K)
> - length = SZ_4K;
> + length = max_t(u64, xe->info.min_tlb_inval_size, length);
>
> align = roundup_pow_of_two(length);
> *start = ALIGN_DOWN(*start, align);
> @@ -163,13 +163,6 @@ static u64 normalize_invalidation_range(struct xe_gt *gt, u64 *start, u64 *end)
> return length;
> }
>
> -/*
> - * Ensure that roundup_pow_of_two(length) doesn't overflow.
> - * Note that roundup_pow_of_two() operates on unsigned long,
> - * not on u64.
> - */
> -#define MAX_RANGE_TLB_INVALIDATION_LENGTH (rounddown_pow_of_two(ULONG_MAX))
> -
> static int send_tlb_inval_ppgtt(struct xe_guc *guc, u32 seqno, u64 start,
> u64 end, u32 id, u32 type,
> struct drm_suballoc *prl_sa)
> @@ -178,9 +171,12 @@ static int send_tlb_inval_ppgtt(struct xe_guc *guc, u32 seqno, u64 start,
> struct xe_gt *gt = guc_to_gt(guc);
> struct xe_device *xe = guc_to_xe(guc);
> u32 action[MAX_TLB_INVALIDATION_LEN];
> - u64 length = end - start;
> + u64 normalize_len;
> int len = 0, err;
>
> + normalize_len = normalize_invalidation_range(gt, &start,
> + &end);
> +
Maybe not related, but is there any way we can pull
normalize_invalidation_range() out of send_tlb_inval_ppgtt()?
Context-based TLB invalidations call send_tlb_inval_ppgtt() multiple
times, but the normalization step only needs to happen once. I’d include
this as a “since we’re here” request.
> xe_gt_assert(gt, (type == XE_GUC_TLB_INVAL_PAGE_SELECTIVE &&
> !xe->info.has_ctx_tlb_inval) ||
> (type == XE_GUC_TLB_INVAL_PAGE_SELECTIVE_CTX &&
> @@ -189,11 +185,9 @@ static int send_tlb_inval_ppgtt(struct xe_guc *guc, u32 seqno, u64 start,
> action[len++] = XE_GUC_ACTION_TLB_INVALIDATION;
> action[len++] = !prl_sa ? seqno : TLB_INVALIDATION_SEQNO_INVALID;
> if (!gt_to_xe(gt)->info.has_range_tlb_inval ||
> - length > MAX_RANGE_TLB_INVALIDATION_LENGTH) {
> + normalize_len > xe->info.max_tlb_inval_size) {
> action[len++] = MAKE_INVAL_OP(XE_GUC_TLB_INVAL_FULL);
> } else {
> - u64 normalize_len = normalize_invalidation_range(gt, &start,
> - &end);
> bool need_flush = !prl_sa &&
> seqno != TLB_INVALIDATION_SEQNO_INVALID;
>
> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> index 189e2a1c29f9..5e02f9ab625b 100644
> --- a/drivers/gpu/drm/xe/xe_pci.c
> +++ b/drivers/gpu/drm/xe/xe_pci.c
> @@ -743,6 +743,9 @@ static int xe_info_init_early(struct xe_device *xe,
> xe->info.vm_max_level = desc->vm_max_level;
> xe->info.vram_flags = desc->vram_flags;
>
> + xe->info.min_tlb_inval_size = desc->min_tlb_inval_size ?: SZ_4K;
> + xe->info.max_tlb_inval_size = desc->max_tlb_inval_size ?: SZ_1G;
How did you arrive at SZ_1G? Previously this was
rounddown_pow_of_two(ULONG_MAX), which was entirely meant to prevent a
software infinite loop, not because of a hardware restriction.
> +
> xe->info.is_dgfx = desc->is_dgfx;
> xe->info.has_cached_pt = desc->has_cached_pt;
> xe->info.has_fan_control = desc->has_fan_control;
> diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
> index 8eee4fb1c57c..cd9d3ad96fe0 100644
> --- a/drivers/gpu/drm/xe/xe_pci_types.h
> +++ b/drivers/gpu/drm/xe/xe_pci_types.h
> @@ -34,6 +34,8 @@ struct xe_device_desc {
> u8 va_bits;
> u8 vm_max_level;
> u8 vram_flags;
> + u64 min_tlb_inval_size;
> + u64 max_tlb_inval_size;
+1 on these bounds - this looks right and needed.
Mztt
>
> u8 require_force_probe:1;
> u8 is_dgfx:1;
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH] drm/xe: Add min and max context TLB invalidation sizes
2026-03-20 20:46 Stuart Summers
2026-03-20 20:49 ` Summers, Stuart
@ 2026-03-23 17:23 ` Matthew Brost
2026-03-23 19:18 ` Summers, Stuart
1 sibling, 1 reply; 15+ messages in thread
From: Matthew Brost @ 2026-03-23 17:23 UTC (permalink / raw)
To: Stuart Summers; +Cc: intel-xe, niranjana.vishwanathapura, jonathan.cavitt
On Fri, Mar 20, 2026 at 08:46:30PM +0000, Stuart Summers wrote:
> Allow platform-defined TLB invalidation min and max lengths.
>
> This gives finer granular control to which invalidations we
> decide to send to GuC. The min size is essentially a round
> up. The max allows us to switch to a full invalidation.
>
> The expectation here is that GuC will translate the full
> invalidation in this instance into a series of per context
> invalidaitons. These are then issued with no H2G or G2H
> messages and therefore should be quicker than splitting
> the invalidations from the KMD in max size chunks and sending
> separately.
>
> v2: Add proper defaults for min/max if not set in the device
> structures
> v3: Add coverage for pow-of-2 out of bounds cases
>
> Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
> ---
> drivers/gpu/drm/xe/xe_device_types.h | 4 +++
> drivers/gpu/drm/xe/xe_guc_tlb_inval.c | 39 +++++++++++++++++----------
> drivers/gpu/drm/xe/xe_pci.c | 3 +++
> drivers/gpu/drm/xe/xe_pci_types.h | 2 ++
> 4 files changed, 34 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index 615218d775b1..0c4168fe2ffb 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -137,6 +137,10 @@ struct xe_device {
> u8 vm_max_level;
> /** @info.va_bits: Maximum bits of a virtual address */
> u8 va_bits;
> + /** @info.min_tlb_inval_size: Minimum size of context based TLB invalidations */
> + u64 min_tlb_inval_size;
> + /** @info.max_tlb_inval_size: Maximum size of context based TLB invalidations */
> + u64 max_tlb_inval_size;
>
> /*
> * Keep all flags below alphabetically sorted
> diff --git a/drivers/gpu/drm/xe/xe_guc_tlb_inval.c b/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
> index ced58f46f846..e9e0be94ceef 100644
> --- a/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
> +++ b/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
> @@ -115,14 +115,23 @@ static int send_page_reclaim(struct xe_guc *guc, u32 seqno,
> G2H_LEN_DW_PAGE_RECLAMATION, 1);
> }
>
> +/*
> + * Ensure that roundup_pow_of_two(length) doesn't overflow.
> + * Note that roundup_pow_of_two() operates on unsigned long,
> + * not on u64.
> + */
> +#define MAX_RANGE_TLB_INVALIDATION_LENGTH (rounddown_pow_of_two(ULONG_MAX))
> +
> static u64 normalize_invalidation_range(struct xe_gt *gt, u64 *start, u64 *end)
> {
> + struct xe_device *xe = gt_to_xe(gt);
> u64 orig_start = *start;
> u64 length = *end - *start;
> u64 align;
>
> - if (length < SZ_4K)
> - length = SZ_4K;
> + xe_gt_assert(gt, length <= MAX_RANGE_TLB_INVALIDATION_LENGTH);
> +
> + length = max_t(u64, xe->info.min_tlb_inval_size, length);
>
> align = roundup_pow_of_two(length);
> *start = ALIGN_DOWN(*start, align);
> @@ -147,13 +156,6 @@ static u64 normalize_invalidation_range(struct xe_gt *gt, u64 *start, u64 *end)
> return length;
> }
>
> -/*
> - * Ensure that roundup_pow_of_two(length) doesn't overflow.
> - * Note that roundup_pow_of_two() operates on unsigned long,
> - * not on u64.
> - */
> -#define MAX_RANGE_TLB_INVALIDATION_LENGTH (rounddown_pow_of_two(ULONG_MAX))
> -
> static int send_tlb_inval_ppgtt(struct xe_guc *guc, u32 seqno, u64 start,
> u64 end, u32 id, u32 type,
> struct drm_suballoc *prl_sa)
> @@ -162,8 +164,20 @@ static int send_tlb_inval_ppgtt(struct xe_guc *guc, u32 seqno, u64 start,
> struct xe_gt *gt = guc_to_gt(guc);
> struct xe_device *xe = guc_to_xe(guc);
> u32 action[MAX_TLB_INVALIDATION_LEN];
> - u64 length = end - start;
> + u64 normalize_len, length = end - start;
> int len = 0, err;
> + bool do_full_inval = false;
> +
> + if (!xe->info.has_range_tlb_inval ||
> + length > MAX_RANGE_TLB_INVALIDATION_LENGTH) {
> + do_full_inval = true;
> + } else {
> + normalize_len = normalize_invalidation_range(gt, &start,
> + &end);
> +
> + if (normalize_len > xe->info.max_tlb_inval_size)
> + do_full_inval = true;
> + }
I suggested this is the last rev, can this logic be moved to
send_tlb_inval_asid_ppgtt / send_tlb_inval_ctx_ppgtt?
For send_tlb_inval_asid_ppgtt it doesn't really matter as
send_tlb_inval_ppgtt is called once.
But consider send_tlb_inval_ctx_ppgtt where send_tlb_inval_ppgtt is
called multiple times and each call fails the
normalize_invalidation_range step (i.e., we set do_full_inval). We only
need to issue one full invalidation, not multiple.
So likely want to hook in early in existing if statement in
send_tlb_inval_ctx_ppgtt.
244 #define EXEC_QUEUE_COUNT_FULL_THRESHOLD 8
245 if (vm->exec_queues.count[id] >= EXEC_QUEUE_COUNT_FULL_THRESHOLD) {
246 u32 action[] = {
247 XE_GUC_ACTION_TLB_INVALIDATION,
248 seqno,
249 MAKE_INVAL_OP(XE_GUC_TLB_INVAL_FULL),
250 };
251
252 err = send_tlb_inval(guc, action, ARRAY_SIZE(action));
253 goto err_unlock;
254 }
255 #undef EXEC_QUEUE_COUNT_FULL_THRESHOLD
Matt
>
> xe_gt_assert(gt, (type == XE_GUC_TLB_INVAL_PAGE_SELECTIVE &&
> !xe->info.has_ctx_tlb_inval) ||
> @@ -172,12 +186,9 @@ static int send_tlb_inval_ppgtt(struct xe_guc *guc, u32 seqno, u64 start,
>
> action[len++] = XE_GUC_ACTION_TLB_INVALIDATION;
> action[len++] = !prl_sa ? seqno : TLB_INVALIDATION_SEQNO_INVALID;
> - if (!gt_to_xe(gt)->info.has_range_tlb_inval ||
> - length > MAX_RANGE_TLB_INVALIDATION_LENGTH) {
> + if (do_full_inval) {
> action[len++] = MAKE_INVAL_OP(XE_GUC_TLB_INVAL_FULL);
> } else {
> - u64 normalize_len = normalize_invalidation_range(gt, &start,
> - &end);
> bool need_flush = !prl_sa &&
> seqno != TLB_INVALIDATION_SEQNO_INVALID;
>
> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> index 189e2a1c29f9..5e02f9ab625b 100644
> --- a/drivers/gpu/drm/xe/xe_pci.c
> +++ b/drivers/gpu/drm/xe/xe_pci.c
> @@ -743,6 +743,9 @@ static int xe_info_init_early(struct xe_device *xe,
> xe->info.vm_max_level = desc->vm_max_level;
> xe->info.vram_flags = desc->vram_flags;
>
> + xe->info.min_tlb_inval_size = desc->min_tlb_inval_size ?: SZ_4K;
> + xe->info.max_tlb_inval_size = desc->max_tlb_inval_size ?: SZ_1G;
> +
> xe->info.is_dgfx = desc->is_dgfx;
> xe->info.has_cached_pt = desc->has_cached_pt;
> xe->info.has_fan_control = desc->has_fan_control;
> diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
> index 8eee4fb1c57c..cd9d3ad96fe0 100644
> --- a/drivers/gpu/drm/xe/xe_pci_types.h
> +++ b/drivers/gpu/drm/xe/xe_pci_types.h
> @@ -34,6 +34,8 @@ struct xe_device_desc {
> u8 va_bits;
> u8 vm_max_level;
> u8 vram_flags;
> + u64 min_tlb_inval_size;
> + u64 max_tlb_inval_size;
>
> u8 require_force_probe:1;
> u8 is_dgfx:1;
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH] drm/xe: Add min and max context TLB invalidation sizes
2026-03-23 17:23 ` Matthew Brost
@ 2026-03-23 19:18 ` Summers, Stuart
0 siblings, 0 replies; 15+ messages in thread
From: Summers, Stuart @ 2026-03-23 19:18 UTC (permalink / raw)
To: Brost, Matthew
Cc: intel-xe@lists.freedesktop.org, Vishwanathapura, Niranjana,
Cavitt, Jonathan
On Mon, 2026-03-23 at 10:23 -0700, Matthew Brost wrote:
> On Fri, Mar 20, 2026 at 08:46:30PM +0000, Stuart Summers wrote:
> > Allow platform-defined TLB invalidation min and max lengths.
> >
> > This gives finer granular control to which invalidations we
> > decide to send to GuC. The min size is essentially a round
> > up. The max allows us to switch to a full invalidation.
> >
> > The expectation here is that GuC will translate the full
> > invalidation in this instance into a series of per context
> > invalidaitons. These are then issued with no H2G or G2H
> > messages and therefore should be quicker than splitting
> > the invalidations from the KMD in max size chunks and sending
> > separately.
> >
> > v2: Add proper defaults for min/max if not set in the device
> > structures
> > v3: Add coverage for pow-of-2 out of bounds cases
> >
> > Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> > Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
> > ---
> > drivers/gpu/drm/xe/xe_device_types.h | 4 +++
> > drivers/gpu/drm/xe/xe_guc_tlb_inval.c | 39 +++++++++++++++++------
> > ----
> > drivers/gpu/drm/xe/xe_pci.c | 3 +++
> > drivers/gpu/drm/xe/xe_pci_types.h | 2 ++
> > 4 files changed, 34 insertions(+), 14 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/xe/xe_device_types.h
> > b/drivers/gpu/drm/xe/xe_device_types.h
> > index 615218d775b1..0c4168fe2ffb 100644
> > --- a/drivers/gpu/drm/xe/xe_device_types.h
> > +++ b/drivers/gpu/drm/xe/xe_device_types.h
> > @@ -137,6 +137,10 @@ struct xe_device {
> > u8 vm_max_level;
> > /** @info.va_bits: Maximum bits of a virtual
> > address */
> > u8 va_bits;
> > + /** @info.min_tlb_inval_size: Minimum size of
> > context based TLB invalidations */
> > + u64 min_tlb_inval_size;
> > + /** @info.max_tlb_inval_size: Maximum size of
> > context based TLB invalidations */
> > + u64 max_tlb_inval_size;
> >
> > /*
> > * Keep all flags below alphabetically sorted
> > diff --git a/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
> > b/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
> > index ced58f46f846..e9e0be94ceef 100644
> > --- a/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
> > +++ b/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
> > @@ -115,14 +115,23 @@ static int send_page_reclaim(struct xe_guc
> > *guc, u32 seqno,
> > G2H_LEN_DW_PAGE_RECLAMATION, 1);
> > }
> >
> > +/*
> > + * Ensure that roundup_pow_of_two(length) doesn't overflow.
> > + * Note that roundup_pow_of_two() operates on unsigned long,
> > + * not on u64.
> > + */
> > +#define MAX_RANGE_TLB_INVALIDATION_LENGTH
> > (rounddown_pow_of_two(ULONG_MAX))
> > +
> > static u64 normalize_invalidation_range(struct xe_gt *gt, u64
> > *start, u64 *end)
> > {
> > + struct xe_device *xe = gt_to_xe(gt);
> > u64 orig_start = *start;
> > u64 length = *end - *start;
> > u64 align;
> >
> > - if (length < SZ_4K)
> > - length = SZ_4K;
> > + xe_gt_assert(gt, length <=
> > MAX_RANGE_TLB_INVALIDATION_LENGTH);
> > +
> > + length = max_t(u64, xe->info.min_tlb_inval_size, length);
> >
> > align = roundup_pow_of_two(length);
> > *start = ALIGN_DOWN(*start, align);
> > @@ -147,13 +156,6 @@ static u64 normalize_invalidation_range(struct
> > xe_gt *gt, u64 *start, u64 *end)
> > return length;
> > }
> >
> > -/*
> > - * Ensure that roundup_pow_of_two(length) doesn't overflow.
> > - * Note that roundup_pow_of_two() operates on unsigned long,
> > - * not on u64.
> > - */
> > -#define MAX_RANGE_TLB_INVALIDATION_LENGTH
> > (rounddown_pow_of_two(ULONG_MAX))
> > -
> > static int send_tlb_inval_ppgtt(struct xe_guc *guc, u32 seqno, u64
> > start,
> > u64 end, u32 id, u32 type,
> > struct drm_suballoc *prl_sa)
> > @@ -162,8 +164,20 @@ static int send_tlb_inval_ppgtt(struct xe_guc
> > *guc, u32 seqno, u64 start,
> > struct xe_gt *gt = guc_to_gt(guc);
> > struct xe_device *xe = guc_to_xe(guc);
> > u32 action[MAX_TLB_INVALIDATION_LEN];
> > - u64 length = end - start;
> > + u64 normalize_len, length = end - start;
> > int len = 0, err;
> > + bool do_full_inval = false;
> > +
> > + if (!xe->info.has_range_tlb_inval ||
> > + length > MAX_RANGE_TLB_INVALIDATION_LENGTH) {
> > + do_full_inval = true;
> > + } else {
> > + normalize_len = normalize_invalidation_range(gt,
> > &start,
> > + &end);
> > +
> > + if (normalize_len > xe->info.max_tlb_inval_size)
> > + do_full_inval = true;
> > + }
>
> I suggested this is the last rev, can this logic be moved to
> send_tlb_inval_asid_ppgtt / send_tlb_inval_ctx_ppgtt?
>
> For send_tlb_inval_asid_ppgtt it doesn't really matter as
> send_tlb_inval_ppgtt is called once.
>
> But consider send_tlb_inval_ctx_ppgtt where send_tlb_inval_ppgtt is
> called multiple times and each call fails the
> normalize_invalidation_range step (i.e., we set do_full_inval). We
> only
> need to issue one full invalidation, not multiple.
Yeah it's a good suggestion. I'll split this out in the next rev.
And I'll repond to those other comments in the earlier rev.
Thanks,
Stuart
>
> So likely want to hook in early in existing if statement in
> send_tlb_inval_ctx_ppgtt.
>
> 244 #define EXEC_QUEUE_COUNT_FULL_THRESHOLD 8
> 245 if (vm->exec_queues.count[id] >=
> EXEC_QUEUE_COUNT_FULL_THRESHOLD) {
> 246 u32 action[] = {
> 247 XE_GUC_ACTION_TLB_INVALIDATION,
> 248 seqno,
> 249 MAKE_INVAL_OP(XE_GUC_TLB_INVAL_FULL),
> 250 };
> 251
> 252 err = send_tlb_inval(guc, action,
> ARRAY_SIZE(action));
> 253 goto err_unlock;
> 254 }
> 255 #undef EXEC_QUEUE_COUNT_FULL_THRESHOLD
>
> Matt
>
> >
> > xe_gt_assert(gt, (type == XE_GUC_TLB_INVAL_PAGE_SELECTIVE
> > &&
> > !xe->info.has_ctx_tlb_inval) ||
> > @@ -172,12 +186,9 @@ static int send_tlb_inval_ppgtt(struct xe_guc
> > *guc, u32 seqno, u64 start,
> >
> > action[len++] = XE_GUC_ACTION_TLB_INVALIDATION;
> > action[len++] = !prl_sa ? seqno :
> > TLB_INVALIDATION_SEQNO_INVALID;
> > - if (!gt_to_xe(gt)->info.has_range_tlb_inval ||
> > - length > MAX_RANGE_TLB_INVALIDATION_LENGTH) {
> > + if (do_full_inval) {
> > action[len++] =
> > MAKE_INVAL_OP(XE_GUC_TLB_INVAL_FULL);
> > } else {
> > - u64 normalize_len =
> > normalize_invalidation_range(gt, &start,
> > -
> > &end);
> > bool need_flush = !prl_sa &&
> > seqno != TLB_INVALIDATION_SEQNO_INVALID;
> >
> > diff --git a/drivers/gpu/drm/xe/xe_pci.c
> > b/drivers/gpu/drm/xe/xe_pci.c
> > index 189e2a1c29f9..5e02f9ab625b 100644
> > --- a/drivers/gpu/drm/xe/xe_pci.c
> > +++ b/drivers/gpu/drm/xe/xe_pci.c
> > @@ -743,6 +743,9 @@ static int xe_info_init_early(struct xe_device
> > *xe,
> > xe->info.vm_max_level = desc->vm_max_level;
> > xe->info.vram_flags = desc->vram_flags;
> >
> > + xe->info.min_tlb_inval_size = desc->min_tlb_inval_size ?:
> > SZ_4K;
> > + xe->info.max_tlb_inval_size = desc->max_tlb_inval_size ?:
> > SZ_1G;
> > +
> > xe->info.is_dgfx = desc->is_dgfx;
> > xe->info.has_cached_pt = desc->has_cached_pt;
> > xe->info.has_fan_control = desc->has_fan_control;
> > diff --git a/drivers/gpu/drm/xe/xe_pci_types.h
> > b/drivers/gpu/drm/xe/xe_pci_types.h
> > index 8eee4fb1c57c..cd9d3ad96fe0 100644
> > --- a/drivers/gpu/drm/xe/xe_pci_types.h
> > +++ b/drivers/gpu/drm/xe/xe_pci_types.h
> > @@ -34,6 +34,8 @@ struct xe_device_desc {
> > u8 va_bits;
> > u8 vm_max_level;
> > u8 vram_flags;
> > + u64 min_tlb_inval_size;
> > + u64 max_tlb_inval_size;
> >
> > u8 require_force_probe:1;
> > u8 is_dgfx:1;
> > --
> > 2.43.0
> >
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH] drm/xe: Add min and max context TLB invalidation sizes
2026-03-22 5:56 ` Matthew Brost
@ 2026-03-23 19:22 ` Summers, Stuart
0 siblings, 0 replies; 15+ messages in thread
From: Summers, Stuart @ 2026-03-23 19:22 UTC (permalink / raw)
To: Brost, Matthew; +Cc: intel-xe@lists.freedesktop.org, Vishwanathapura, Niranjana
On Sat, 2026-03-21 at 22:56 -0700, Matthew Brost wrote:
> On Thu, Mar 19, 2026 at 09:05:32PM +0000, Stuart Summers wrote:
> > Allow platform-defined TLB invalidation min and max lengths.
> >
> > This gives finer granular control to which invalidations we
> > decide to send to GuC. The min size is essentially a round
> > up. The max allows us to switch to a full invalidation.
> >
> > The expectation here is that GuC will translate the full
> > invalidation in this instance into a series of per context
> > invalidaitons. These are then issued with no H2G or G2H
> > messages and therefore should be quicker than splitting
> > the invalidations from the KMD in max size chunks and sending
> > separately.
> >
> > v2: Add proper defaults for min/max if not set in the device
> > structures
> >
> > Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> > ---
> > drivers/gpu/drm/xe/xe_device_types.h | 4 ++++
> > drivers/gpu/drm/xe/xe_guc_tlb_inval.c | 20 +++++++-------------
> > drivers/gpu/drm/xe/xe_pci.c | 3 +++
> > drivers/gpu/drm/xe/xe_pci_types.h | 2 ++
> > 4 files changed, 16 insertions(+), 13 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/xe/xe_device_types.h
> > b/drivers/gpu/drm/xe/xe_device_types.h
> > index 615218d775b1..0c4168fe2ffb 100644
> > --- a/drivers/gpu/drm/xe/xe_device_types.h
> > +++ b/drivers/gpu/drm/xe/xe_device_types.h
> > @@ -137,6 +137,10 @@ struct xe_device {
> > u8 vm_max_level;
> > /** @info.va_bits: Maximum bits of a virtual
> > address */
> > u8 va_bits;
> > + /** @info.min_tlb_inval_size: Minimum size of
> > context based TLB invalidations */
> > + u64 min_tlb_inval_size;
> > + /** @info.max_tlb_inval_size: Maximum size of
> > context based TLB invalidations */
> > + u64 max_tlb_inval_size;
> >
> > /*
> > * Keep all flags below alphabetically sorted
> > diff --git a/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
> > b/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
> > index eb40528976ca..7512f889a97a 100644
> > --- a/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
> > +++ b/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
> > @@ -133,12 +133,12 @@ static int send_page_reclaim(struct xe_guc
> > *guc, u32 seqno,
> >
> > static u64 normalize_invalidation_range(struct xe_gt *gt, u64
> > *start, u64 *end)
> > {
> > + struct xe_device *xe = gt_to_xe(gt);
> > u64 orig_start = *start;
> > u64 length = *end - *start;
> > u64 align;
> >
> > - if (length < SZ_4K)
> > - length = SZ_4K;
> > + length = max_t(u64, xe->info.min_tlb_inval_size, length);
> >
> > align = roundup_pow_of_two(length);
> > *start = ALIGN_DOWN(*start, align);
> > @@ -163,13 +163,6 @@ static u64 normalize_invalidation_range(struct
> > xe_gt *gt, u64 *start, u64 *end)
> > return length;
> > }
> >
> > -/*
> > - * Ensure that roundup_pow_of_two(length) doesn't overflow.
> > - * Note that roundup_pow_of_two() operates on unsigned long,
> > - * not on u64.
> > - */
> > -#define MAX_RANGE_TLB_INVALIDATION_LENGTH
> > (rounddown_pow_of_two(ULONG_MAX))
> > -
> > static int send_tlb_inval_ppgtt(struct xe_guc *guc, u32 seqno, u64
> > start,
> > u64 end, u32 id, u32 type,
> > struct drm_suballoc *prl_sa)
> > @@ -178,9 +171,12 @@ static int send_tlb_inval_ppgtt(struct xe_guc
> > *guc, u32 seqno, u64 start,
> > struct xe_gt *gt = guc_to_gt(guc);
> > struct xe_device *xe = guc_to_xe(guc);
> > u32 action[MAX_TLB_INVALIDATION_LEN];
> > - u64 length = end - start;
> > + u64 normalize_len;
> > int len = 0, err;
> >
> > + normalize_len = normalize_invalidation_range(gt, &start,
> > + &end);
> > +
>
> Maybe not related, but is there any way we can pull
> normalize_invalidation_range() out of send_tlb_inval_ppgtt()?
> Context-based TLB invalidations call send_tlb_inval_ppgtt() multiple
> times, but the normalization step only needs to happen once. I’d
> include
> this as a “since we’re here” request.
Yeah seems like a good change to make. Let me add that in the next rev.
>
> > xe_gt_assert(gt, (type == XE_GUC_TLB_INVAL_PAGE_SELECTIVE
> > &&
> > !xe->info.has_ctx_tlb_inval) ||
> > (type == XE_GUC_TLB_INVAL_PAGE_SELECTIVE_CTX
> > &&
> > @@ -189,11 +185,9 @@ static int send_tlb_inval_ppgtt(struct xe_guc
> > *guc, u32 seqno, u64 start,
> > action[len++] = XE_GUC_ACTION_TLB_INVALIDATION;
> > action[len++] = !prl_sa ? seqno :
> > TLB_INVALIDATION_SEQNO_INVALID;
> > if (!gt_to_xe(gt)->info.has_range_tlb_inval ||
> > - length > MAX_RANGE_TLB_INVALIDATION_LENGTH) {
> > + normalize_len > xe->info.max_tlb_inval_size) {
> > action[len++] =
> > MAKE_INVAL_OP(XE_GUC_TLB_INVAL_FULL);
> > } else {
> > - u64 normalize_len =
> > normalize_invalidation_range(gt, &start,
> > -
> > &end);
> > bool need_flush = !prl_sa &&
> > seqno != TLB_INVALIDATION_SEQNO_INVALID;
> >
> > diff --git a/drivers/gpu/drm/xe/xe_pci.c
> > b/drivers/gpu/drm/xe/xe_pci.c
> > index 189e2a1c29f9..5e02f9ab625b 100644
> > --- a/drivers/gpu/drm/xe/xe_pci.c
> > +++ b/drivers/gpu/drm/xe/xe_pci.c
> > @@ -743,6 +743,9 @@ static int xe_info_init_early(struct xe_device
> > *xe,
> > xe->info.vm_max_level = desc->vm_max_level;
> > xe->info.vram_flags = desc->vram_flags;
> >
> > + xe->info.min_tlb_inval_size = desc->min_tlb_inval_size ?:
> > SZ_4K;
> > + xe->info.max_tlb_inval_size = desc->max_tlb_inval_size ?:
> > SZ_1G;
>
> How did you arrive at SZ_1G? Previously this was
> rounddown_pow_of_two(ULONG_MAX), which was entirely meant to prevent
> a
> software infinite loop, not because of a hardware restriction.
Not a hardware requirement I agree. This was just a middle ground value
I had chosen. I think on initial bind we're invaliding all 0xf's
basically.. so it would hit that upper case. We could set the default
to that? I was thinking if we go much beyond 1G, I don't know that
we're really gaining much doing a range based invalidation at that
point. Maybe we should at least account for the possibility of 1G page
sizes though and bump that to something like 4 or 8G?
>
> > +
> > xe->info.is_dgfx = desc->is_dgfx;
> > xe->info.has_cached_pt = desc->has_cached_pt;
> > xe->info.has_fan_control = desc->has_fan_control;
> > diff --git a/drivers/gpu/drm/xe/xe_pci_types.h
> > b/drivers/gpu/drm/xe/xe_pci_types.h
> > index 8eee4fb1c57c..cd9d3ad96fe0 100644
> > --- a/drivers/gpu/drm/xe/xe_pci_types.h
> > +++ b/drivers/gpu/drm/xe/xe_pci_types.h
> > @@ -34,6 +34,8 @@ struct xe_device_desc {
> > u8 va_bits;
> > u8 vm_max_level;
> > u8 vram_flags;
> > + u64 min_tlb_inval_size;
> > + u64 max_tlb_inval_size;
>
> +1 on these bounds - this looks right and needed.
Thanks!
Stuart
>
> Mztt
>
> >
> > u8 require_force_probe:1;
> > u8 is_dgfx:1;
> > --
> > 2.43.0
> >
^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2026-03-23 19:23 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz follow: Atom feed
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2026-03-17 19:50 [PATCH] drm/xe: Add min and max context TLB invalidation sizes Stuart Summers
2026-03-17 19:57 ` ✓ CI.KUnit: success for " Patchwork
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2026-03-19 21:05 [PATCH] " Stuart Summers
2026-03-19 21:11 ` Summers, Stuart
2026-03-19 21:36 ` Cavitt, Jonathan
2026-03-19 21:51 ` Summers, Stuart
2026-03-22 5:56 ` Matthew Brost
2026-03-23 19:22 ` Summers, Stuart
2026-03-20 20:46 Stuart Summers
2026-03-20 20:49 ` Summers, Stuart
2026-03-20 20:59 ` Cavitt, Jonathan
2026-03-23 17:23 ` Matthew Brost
2026-03-23 19:18 ` Summers, Stuart
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