public inbox for intel-xe@lists.freedesktop.org
 help / color / mirror / Atom feed
* [PATCH] [RFC]: drm/i915/display: Fix vblank timestamps for fixed RR on VRR-TG-always platforms when userspace set vrr_enable=FALSE
@ 2026-04-17 13:06 Vidya Srinivas
  2026-04-20 17:24 ` ✓ CI.KUnit: success for : " Patchwork
                   ` (2 more replies)
  0 siblings, 3 replies; 4+ messages in thread
From: Vidya Srinivas @ 2026-04-17 13:06 UTC (permalink / raw)
  To: intel-gfx
  Cc: intel-xe, uma.shankar, ankit.k.nautiyal, seanpaul, navaremanasi,
	shawn.c.lee, Vidya Srinivas

On LNL+ VRR timing generator is always active.
For panels like this

"2880x1800": 120 709633 2880 2888 2920 3080 1800 1880 1896 1920 0x48 0xa
"2880x1800": 60 709633 2880 2888 2920 3080 1800 3800 3816 3840 0x40 0xa

that use the same pixel clock with a stretched vtotal have a large front
porch. For this case 2880x1800 panel:
120Hz: vtotal=1920 (120 lines of front porch)
60Hz: vtotal=3840 (2000 lines of front porch)

When at lower RR (60Hz) and "vrr_enable = FALSE"
the intel_crtc_active_timings() function is not adjusting
crtc_vblank_start leaving it at the raw mode value of 1800 (vactive end).

This caused Android SurfaceFlinger to miscalculate frame deadlines --
it received fence signals ~8ms into the 16.67ms frame and concluded
frames were being presented late, leading to dropped frames during
heavy workloads like video playback at 60Hz.

Fix by adjusting crtc_vblank_start, crtc_vblank_end, and crtc_vtotal
to match the VRR timing generator values when
intel_vrr_always_use_vrr_tg() is true, even when vrr_enable is false.

Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vblank.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
index 0726a2abed38..3667e1a7c0ad 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -527,13 +527,15 @@ static void intel_crtc_active_timings(struct drm_display_mode *mode,
 	drm_mode_init(mode, &crtc_state->hw.adjusted_mode);
 	*vmax_vblank_start = 0;
 
-	if (!vrr_enable)
+	if (!vrr_enable && !intel_vrr_always_use_vrr_tg(to_intel_display(crtc_state)))
 		return;
 
 	mode->crtc_vtotal = intel_vrr_vmax_vtotal(crtc_state);
 	mode->crtc_vblank_end = intel_vrr_vmax_vtotal(crtc_state);
 	mode->crtc_vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
-	*vmax_vblank_start = intel_vrr_vmax_vblank_start(crtc_state);
+
+	if (vrr_enable)
+		*vmax_vblank_start = intel_vrr_vmax_vblank_start(crtc_state);
 }
 
 void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state,
-- 
2.45.2


^ permalink raw reply related	[flat|nested] 4+ messages in thread
end of thread, other threads:[~2026-04-20 21:00 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-04-17 13:06 [PATCH] [RFC]: drm/i915/display: Fix vblank timestamps for fixed RR on VRR-TG-always platforms when userspace set vrr_enable=FALSE Vidya Srinivas
2026-04-20 17:24 ` ✓ CI.KUnit: success for : " Patchwork
2026-04-20 18:11 ` ✓ Xe.CI.BAT: " Patchwork
2026-04-20 21:00 ` ✗ Xe.CI.FULL: failure " Patchwork

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox