* [PATCH 01/24] drm/xe/eudebug: Introduce eudebug interface
2026-04-30 10:50 [PATCH 00/24] Intel Xe GPU Debug Support (eudebug) v8 Mika Kuoppala
@ 2026-04-30 10:50 ` Mika Kuoppala
2026-04-30 10:50 ` [PATCH 02/24] drm/xe/eudebug: Add documentation Mika Kuoppala
` (26 subsequent siblings)
27 siblings, 0 replies; 32+ messages in thread
From: Mika Kuoppala @ 2026-04-30 10:50 UTC (permalink / raw)
To: intel-xe
Cc: simona.vetter, matthew.brost, christian.koenig, thomas.hellstrom,
joonas.lahtinen, gustavo.sousa, jan.maslak,
dominik.karol.piatkowski, rodrigo.vivi, andrzej.hajda,
matthew.auld, maciej.patelczyk, gwan-gyeong.mun, Mika Kuoppala,
Maarten Lankhorst, Lucas De Marchi, Dominik Grzegorzek,
Andi Shyti, Matt Roper, Zbigniew Kempczyński,
Jonathan Cavitt, Christoph Manszewski
This patch adds the eudebug interface to the Xe driver, enabling
user-space debuggers (e.g., GDB) to track and interact with GPU resources
of a DRM client. Debuggers can inspect or modify these resources,
for example, to locate ISA/ELF sections and install breakpoints in a
shader's instruction stream.
A debugger opens a connection to the Xe driver via a DRM ioctl, specifying
the target DRM client's file descriptor. This returns an anonymous file
descriptor for the connection, which can be used to listen for resource
creation/destruction events. The same file descriptor can also be used to
receive hardware state change events and control execution flow by
interrupting EU threads on the GPU (in follow-up patches).
This patch introduces the eudebug connection and event queuing,
adding client create/destroy and VM create/destroy events as a baseline.
Additional events and hardware control for full debugger operation are
needed and will be introduced in follow-up patches.
The resource tracking components are inspired by Maciej Patelczyk's work on
resource handling for i915. Chris Wilson suggested a two-way mapping
approach, which simplifies using the resource map as definitive
bookkeeping forresources relayed to the debugger during the discovery
phase (in a follow-up patch).
v2: - Kconfig support (Matthew)
- ptraced access control (Lucas)
- pass expected event length to user (Zbigniew)
- only track long running VMs
- checkpatch (Tilak)
- include order (Andrzej)
- 32bit fixes (Andrzej)
- cleaner get_task_struct
- remove xa_array and use clients.list for tracking (Mika)
v3: - adapt to removal of clients.lock (Mika)
- create_event cleanup (Christoph)
v4: - add proper header guards (Christoph)
- better read_event fault handling (Christoph, Mika)
- simplify attach (Mika)
- connect using target file descriptors
- avoid event->seqno after queue as it is can UAF (Mika)
- use drmm for eudebug_fini (Maciej)
- squash dynamic enable
v6: - drm->authenticated is overzealous for render (Mika)
v7: - struct member documentation (Mika)
- enforce seqno mbz (Mika)
v8 - head->seqno fix (Mika)
- resource alloc and removal cleanup (Mika)
- s/wait_interruptible_timeout/wait_timeout (Mika)
- use fd_install in connect (Mika)
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Andi Shyti <andi.shyti@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Andrzej Hajda <andrzej.hajda@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Maciej Patelczyk <maciej.patelczyk@intel.com>
Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
Signed-off-by: Christoph Manszewski <christoph.manszewski@intel.com>
fix
dont use NOTCON on resource add remove
---
drivers/gpu/drm/xe/Kconfig | 10 +
drivers/gpu/drm/xe/Makefile | 3 +
drivers/gpu/drm/xe/xe_device.c | 14 +
drivers/gpu/drm/xe/xe_device_types.h | 32 +
drivers/gpu/drm/xe/xe_eudebug.c | 1040 +++++++++++++++++++++++++
drivers/gpu/drm/xe/xe_eudebug.h | 65 ++
drivers/gpu/drm/xe/xe_eudebug_types.h | 121 +++
drivers/gpu/drm/xe/xe_vm.c | 7 +-
include/uapi/drm/xe_drm.h | 29 +
include/uapi/drm/xe_drm_eudebug.h | 80 ++
10 files changed, 1400 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/xe/xe_eudebug.c
create mode 100644 drivers/gpu/drm/xe/xe_eudebug.h
create mode 100644 drivers/gpu/drm/xe/xe_eudebug_types.h
create mode 100644 include/uapi/drm/xe_drm_eudebug.h
diff --git a/drivers/gpu/drm/xe/Kconfig b/drivers/gpu/drm/xe/Kconfig
index 4d7dcaff2b91..78d4673665b4 100644
--- a/drivers/gpu/drm/xe/Kconfig
+++ b/drivers/gpu/drm/xe/Kconfig
@@ -129,6 +129,16 @@ config DRM_XE_FORCE_PROBE
Use "!*" to block the probe of the driver for all known devices.
+config DRM_XE_EUDEBUG
+ bool "Enable gdb debugger support (eudebug)"
+ depends on DRM_XE
+ default y
+ help
+ Choose this option if you want to add support for debugger (gdb) to
+ attach into process using Xe and debug the gpu/gpgpu programs.
+ With debugger support, Xe will provide interface for a debugger to
+ process to track, inspect and modify resources.
+
menu "drm/Xe Debugging"
depends on DRM_XE
depends on EXPERT
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 09661f079d03..7212ceb339ab 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -156,6 +156,9 @@ xe-$(CONFIG_I2C) += xe_i2c.o
xe-$(CONFIG_DRM_XE_GPUSVM) += xe_svm.o
xe-$(CONFIG_DRM_GPUSVM) += xe_userptr.o
+# debugging shaders with gdb (eudebug) support
+xe-$(CONFIG_DRM_XE_EUDEBUG) += xe_eudebug.o
+
# graphics hardware monitoring (HWMON) support
xe-$(CONFIG_HWMON) += xe_hwmon.o
diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index 4b45b617a039..4e6773cf806f 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -34,6 +34,7 @@
#include "xe_dma_buf.h"
#include "xe_drm_client.h"
#include "xe_drv.h"
+#include "xe_eudebug.h"
#include "xe_exec.h"
#include "xe_exec_queue.h"
#include "xe_force_wake.h"
@@ -110,6 +111,11 @@ static int xe_file_open(struct drm_device *dev, struct drm_file *file)
mutex_init(&xef->exec_queue.lock);
xa_init_flags(&xef->exec_queue.xa, XA_FLAGS_ALLOC1);
+#if IS_ENABLED(CONFIG_DRM_XE_EUDEBUG)
+ mutex_init(&xef->eudebug.lock);
+ INIT_LIST_HEAD(&xef->eudebug.target_link);
+#endif
+
file->driver_priv = xef;
kref_init(&xef->refcount);
@@ -132,6 +138,9 @@ static void xe_file_destroy(struct kref *ref)
xa_destroy(&xef->vm.xa);
mutex_destroy(&xef->vm.lock);
+#if IS_ENABLED(CONFIG_DRM_XE_EUDEBUG)
+ mutex_destroy(&xef->eudebug.lock);
+#endif
xe_drm_client_put(xef->client);
kfree(xef->process_name);
kfree(xef);
@@ -173,6 +182,8 @@ static void xe_file_close(struct drm_device *dev, struct drm_file *file)
guard(xe_pm_runtime)(xe);
+ xe_eudebug_file_close(xef);
+
/*
* No need for exec_queue.lock here as there is no contention for it
* when FD is closing as IOCTLs presumably can't be modifying the
@@ -216,6 +227,7 @@ static const struct drm_ioctl_desc xe_ioctls[] = {
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(XE_VM_GET_PROPERTY, xe_vm_get_property_ioctl,
DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(XE_EUDEBUG_CONNECT, xe_eudebug_connect_ioctl, DRM_RENDER_ALLOW),
};
static long xe_drm_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
@@ -1071,6 +1083,8 @@ int xe_device_probe(struct xe_device *xe)
if (err)
goto err_unregister_display;
+ xe_eudebug_init(xe);
+
detect_preproduction_hw(xe);
err = drmm_add_action_or_reset(&xe->drm, xe_device_wedged_fini, xe);
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 89437de3001a..733f4ab391bd 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -14,6 +14,7 @@
#include "xe_devcoredump_types.h"
#include "xe_drm_ras_types.h"
+#include "xe_eudebug_types.h"
#include "xe_heci_gsc.h"
#include "xe_late_bind_fw_types.h"
#include "xe_oa_types.h"
@@ -568,6 +569,23 @@ struct xe_device {
spinlock_t lock;
} uncore;
#endif
+
+#if IS_ENABLED(CONFIG_DRM_XE_EUDEBUG)
+ /** @debugger connection list and globals for device */
+ struct {
+ /** @eudebug.session_count: session counter to track connections */
+ u64 session_count;
+
+ /** @eudebug.available: is the debugging functionality available */
+ enum xe_eudebug_state state;
+
+ /** @eudebug.targets: this is list for xe_files for each target */
+ struct list_head targets;
+
+ /** @eudebug.lock: protects state and targets */
+ struct mutex lock;
+ } eudebug;
+#endif
};
/**
@@ -629,6 +647,20 @@ struct xe_file {
/** @refcount: ref count of this xe file */
struct kref refcount;
+
+#if IS_ENABLED(CONFIG_DRM_XE_EUDEBUG)
+ /** @eudebug: struct to hold eudebug connection specifics */
+ struct {
+ /** @eudebug.debugger: the debugger connection into this xe_file */
+ struct xe_eudebug *debugger;
+
+ /** @eudebug.lock: protecting debugger */
+ struct mutex lock;
+
+ /** @target_link: link into xe_device.eudebug.targets */
+ struct list_head target_link;
+ } eudebug;
+#endif
};
#endif
diff --git a/drivers/gpu/drm/xe/xe_eudebug.c b/drivers/gpu/drm/xe/xe_eudebug.c
new file mode 100644
index 000000000000..02ecdbca46ff
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_eudebug.c
@@ -0,0 +1,1040 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2023-2025 Intel Corporation
+ */
+
+#include <linux/anon_inodes.h>
+#include <linux/delay.h>
+#include <linux/poll.h>
+#include <linux/uaccess.h>
+
+#include <drm/drm_managed.h>
+#include <uapi/drm/xe_drm.h>
+
+#include "xe_assert.h"
+#include "xe_device.h"
+#include "xe_eudebug.h"
+#include "xe_eudebug_types.h"
+#include "xe_macros.h"
+#include "xe_vm.h"
+
+/*
+ * If there is no detected event read by userspace, during this period, assume
+ * userspace problem and disconnect debugger to allow forward progress.
+ */
+#define XE_EUDEBUG_NO_READ_DETECTED_TIMEOUT_MS (25 * 1000)
+
+#define cast_event(T, event) container_of((event), typeof(*(T)), base)
+
+static struct drm_xe_eudebug_event *
+event_fifo_pending(struct xe_eudebug *d)
+{
+ struct drm_xe_eudebug_event *event;
+
+ if (kfifo_peek(&d->events.fifo, &event))
+ return event;
+
+ return NULL;
+}
+
+/*
+ * This is racy as we dont take the lock for read but all the
+ * callsites can handle the race so we can live without lock.
+ */
+__no_kcsan
+static unsigned int
+event_fifo_num_events_peek(const struct xe_eudebug * const d)
+{
+ return kfifo_len(&d->events.fifo);
+}
+
+static bool
+xe_eudebug_detached(struct xe_eudebug *d)
+{
+ return READ_ONCE(d->target.xef) == NULL;
+}
+
+static unsigned int
+event_fifo_has_events(struct xe_eudebug *d)
+{
+ /* Allow all waiters to proceed to check their state */
+ if (xe_eudebug_detached(d))
+ return 1;
+
+ return event_fifo_num_events_peek(d);
+}
+
+static const struct rhashtable_params rhash_res = {
+ .head_offset = offsetof(struct xe_eudebug_handle, rh_head),
+ .key_len = sizeof_field(struct xe_eudebug_handle, key),
+ .key_offset = offsetof(struct xe_eudebug_handle, key),
+ .automatic_shrinking = true,
+};
+
+static struct xe_eudebug_resource *
+resource_from_type(struct xe_eudebug *d, int t)
+{
+ return &d->target.res[t];
+}
+
+static int
+xe_eudebug_resources_init(struct xe_eudebug *d)
+{
+ int ret;
+ int i;
+
+ ret = 0;
+ for (i = 0; i < XE_EUDEBUG_RES_TYPE_COUNT; i++) {
+ struct xe_eudebug_resource *r = resource_from_type(d, i);
+
+ xa_init_flags(&r->xa, XA_FLAGS_ALLOC1);
+ ret = rhashtable_init(&r->rh, &rhash_res);
+
+ if (ret) {
+ xa_destroy(&r->xa);
+ break;
+ }
+ }
+
+ if (!ret)
+ return 0;
+
+ while (i--) {
+ struct xe_eudebug_resource *r = resource_from_type(d, i);
+
+ xa_destroy(&r->xa);
+ rhashtable_destroy(&r->rh);
+ }
+
+ return ret;
+}
+
+static void
+xe_eudebug_resources_destroy(struct xe_eudebug *d)
+{
+ unsigned long j;
+ int err;
+ int i;
+
+ mutex_lock(&d->target.lock);
+ for (i = 0; i < XE_EUDEBUG_RES_TYPE_COUNT; i++) {
+ struct xe_eudebug_resource *r = resource_from_type(d, i);
+ struct xe_eudebug_handle *h;
+
+ xa_for_each(&r->xa, j, h) {
+ struct xe_eudebug_handle *t;
+
+ err = rhashtable_remove_fast(&r->rh,
+ &h->rh_head,
+ rhash_res);
+ xe_eudebug_assert(d, !err);
+ t = xa_erase(&r->xa, h->id);
+ if (XE_WARN_ON(!t))
+ continue;
+
+ xe_eudebug_assert(d, t == h);
+ kfree(t);
+ }
+ }
+ mutex_unlock(&d->target.lock);
+
+ for (i = 0; i < XE_EUDEBUG_RES_TYPE_COUNT; i++) {
+ struct xe_eudebug_resource *r = resource_from_type(d, i);
+
+ rhashtable_destroy(&r->rh);
+ xe_eudebug_assert(d, xa_empty(&r->xa));
+ xa_destroy(&r->xa);
+ }
+}
+
+static void xe_eudebug_free(struct kref *ref)
+{
+ struct xe_eudebug *d = container_of(ref, typeof(*d), ref);
+ struct drm_xe_eudebug_event *event;
+
+ xe_assert(d->xe, xe_eudebug_detached(d));
+
+ while (kfifo_get(&d->events.fifo, &event))
+ kfree(event);
+
+ xe_eudebug_resources_destroy(d);
+ mutex_destroy(&d->target.lock);
+ XE_WARN_ON(d->target.xef);
+
+ xe_eudebug_assert(d, !kfifo_len(&d->events.fifo));
+
+ kfree(d);
+}
+
+static void xe_eudebug_put(struct xe_eudebug *d)
+{
+ kref_put(&d->ref, xe_eudebug_free);
+}
+
+static void remove_debugger(struct xe_file *xef)
+{
+ struct xe_eudebug *d;
+
+ if (XE_WARN_ON(!xef))
+ return;
+
+ mutex_lock(&xef->eudebug.lock);
+ d = xef->eudebug.debugger;
+ if (d)
+ xef->eudebug.debugger = NULL;
+ mutex_unlock(&xef->eudebug.lock);
+
+ if (d) {
+ struct xe_device *xe = d->xe;
+
+ mutex_lock(&xe->eudebug.lock);
+ list_del_init(&xef->eudebug.target_link);
+ mutex_unlock(&xe->eudebug.lock);
+
+ eu_dbg(d, "debugger removed");
+
+ xe_eudebug_put(d);
+ }
+}
+
+static bool xe_eudebug_detach(struct xe_device *xe,
+ struct xe_eudebug *d,
+ const int err)
+{
+ struct xe_file *target = NULL;
+
+ XE_WARN_ON(err > 0);
+
+ mutex_lock(&d->target.lock);
+ if (d->target.xef) {
+ target = d->target.xef;
+ d->target.err = err;
+ WRITE_ONCE(d->target.xef, NULL);
+ }
+ mutex_unlock(&d->target.lock);
+
+ if (!target)
+ return false;
+
+ eu_dbg(d, "session %lld detached with %d", d->session, err);
+
+ remove_debugger(target);
+ xe_file_put(target);
+
+ return true;
+}
+
+static int _xe_eudebug_disconnect(struct xe_eudebug *d,
+ const int err)
+{
+ wake_up_all(&d->events.write_done);
+ wake_up_all(&d->events.read_done);
+
+ return xe_eudebug_detach(d->xe, d, err);
+}
+
+#define xe_eudebug_disconnect(_d, _err) ({ \
+ if (_xe_eudebug_disconnect((_d), (_err))) { \
+ if ((_err) == 0 || (_err) == -ETIMEDOUT) \
+ eu_dbg((_d), "Session closed (%d)", (_err)); \
+ else \
+ eu_err((_d), "Session disconnected, err = %d (%s:%d)", \
+ (_err), __func__, __LINE__); \
+ } \
+})
+
+static struct xe_eudebug *
+xe_eudebug_get(struct xe_file *xef)
+{
+ struct xe_eudebug *d;
+
+ mutex_lock(&xef->eudebug.lock);
+ d = xef->eudebug.debugger;
+ if (d && !kref_get_unless_zero(&d->ref))
+ d = NULL;
+ mutex_unlock(&xef->eudebug.lock);
+
+ if (!d)
+ return NULL;
+
+ if (xe_eudebug_detached(d)) {
+ xe_eudebug_put(d);
+ return NULL;
+ }
+
+ return d;
+}
+
+static int xe_eudebug_queue_event(struct xe_eudebug *d,
+ struct drm_xe_eudebug_event *event)
+{
+ const u64 wait_jiffies = msecs_to_jiffies(1000);
+ u64 last_read_detected_ts, last_head_seqno, start_ts;
+ const u64 event_seqno = event->seqno;
+
+ xe_eudebug_assert(d, event->len > sizeof(struct drm_xe_eudebug_event));
+ xe_eudebug_assert(d, event->type);
+ xe_eudebug_assert(d, event->type != DRM_XE_EUDEBUG_EVENT_READ);
+
+ start_ts = ktime_get();
+ last_read_detected_ts = start_ts;
+ last_head_seqno = 0;
+
+ do {
+ struct drm_xe_eudebug_event *head;
+ u64 head_seqno;
+ bool was_queued;
+
+ if (xe_eudebug_detached(d))
+ break;
+
+ spin_lock(&d->events.lock);
+ head = event_fifo_pending(d);
+ if (head)
+ head_seqno = head->seqno;
+ else
+ head_seqno = 0;
+
+ was_queued = kfifo_in(&d->events.fifo, &event, 1);
+ spin_unlock(&d->events.lock);
+
+ wake_up_all(&d->events.write_done);
+
+ if (was_queued) {
+ eu_dbg(d, "queued event with seqno %lld (head %lld)\n",
+ event_seqno, head_seqno);
+ event = NULL;
+ break;
+ }
+
+ XE_WARN_ON(!head_seqno);
+
+ /* If we detect progress, restart timeout */
+ if (last_head_seqno != head_seqno)
+ last_read_detected_ts = ktime_get();
+
+ last_head_seqno = head_seqno;
+
+ wait_event_timeout(d->events.read_done,
+ !kfifo_is_full(&d->events.fifo) ||
+ xe_eudebug_detached(d),
+ wait_jiffies);
+
+ } while (ktime_ms_delta(ktime_get(), last_read_detected_ts) <
+ XE_EUDEBUG_NO_READ_DETECTED_TIMEOUT_MS);
+
+ if (event) {
+ eu_dbg(d,
+ "event %llu queue failed (blocked %lld ms, avail %d)",
+ event->seqno,
+ ktime_ms_delta(ktime_get(), start_ts),
+ kfifo_avail(&d->events.fifo));
+
+ kfree(event);
+
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+static struct xe_eudebug_handle *
+alloc_handle(const int type, const u64 key)
+{
+ struct xe_eudebug_handle *h;
+
+ h = kzalloc_obj(*h, GFP_KERNEL);
+ if (!h)
+ return NULL;
+
+ h->key = key;
+
+ return h;
+}
+
+static struct xe_eudebug_handle *
+__find_handle(struct xe_eudebug_resource *r,
+ const u64 key)
+{
+ struct xe_eudebug_handle *h;
+
+ h = rhashtable_lookup_fast(&r->rh,
+ &key,
+ rhash_res);
+ return h;
+}
+
+static int _xe_eudebug_add_handle(struct xe_eudebug *d,
+ int type,
+ void *p,
+ u64 *seqno,
+ int *handle)
+{
+ const u64 key = (uintptr_t)p;
+ struct xe_eudebug_resource *r;
+ struct xe_eudebug_handle *h, *o;
+ int err;
+
+ if (XE_WARN_ON(!p))
+ return -EINVAL;
+
+ h = alloc_handle(type, key);
+ if (!h)
+ return -ENOMEM;
+
+ r = resource_from_type(d, type);
+
+ mutex_lock(&d->target.lock);
+ o = __find_handle(r, key);
+ if (o) {
+ err = -EEXIST;
+ } else {
+ err = xa_alloc(&r->xa, &h->id, h, xa_limit_31b, GFP_KERNEL);
+ if (!err) {
+ err = rhashtable_insert_fast(&r->rh,
+ &h->rh_head,
+ rhash_res);
+ if (err)
+ xa_erase(&r->xa, h->id);
+ else if (seqno)
+ *seqno = atomic_long_inc_return(&d->events.seqno);
+ }
+ }
+ mutex_unlock(&d->target.lock);
+
+ if (err) {
+ kfree(h);
+ XE_WARN_ON(err > 0);
+ return err;
+ }
+
+ if (handle)
+ *handle = h->id;
+
+ xe_eudebug_assert(d, h->id);
+
+ return h->id;
+}
+
+static int xe_eudebug_add_handle(struct xe_eudebug *d,
+ int type,
+ void *p,
+ u64 *seqno)
+{
+ int ret;
+
+ ret = _xe_eudebug_add_handle(d, type, p, seqno, NULL);
+
+ eu_dbg(d, "handle type %d handle %p added: %d\n", type, p, ret);
+
+ return ret;
+}
+
+static int _xe_eudebug_remove_handle(struct xe_eudebug *d, int type, void *p,
+ u64 *seqno)
+{
+ const u64 key = (uintptr_t)p;
+ struct xe_eudebug_resource *r;
+ struct xe_eudebug_handle *h, *xa_h;
+ int ret;
+
+ if (XE_WARN_ON(!key))
+ return -EINVAL;
+
+ r = resource_from_type(d, type);
+
+ mutex_lock(&d->target.lock);
+ h = __find_handle(r, key);
+ if (!h) {
+ ret = -ENOENT;
+ goto out;
+ }
+
+ xa_h = xa_load(&r->xa, h->id);
+ if (XE_WARN_ON(!xa_h || xa_h != h)) {
+ ret = -EIO;
+ goto out;
+ }
+
+ ret = rhashtable_remove_fast(&r->rh,
+ &h->rh_head,
+ rhash_res);
+ if (XE_WARN_ON(ret)) {
+ ret = -EIO;
+ goto out;
+ }
+
+ xa_h = xa_erase(&r->xa, h->id);
+ if (XE_WARN_ON(xa_h != h)) {
+ ret = -EIO;
+ goto out;
+ }
+
+ ret = h->id;
+ if (seqno)
+ *seqno = atomic_long_inc_return(&d->events.seqno);
+
+ kfree(h);
+out:
+ mutex_unlock(&d->target.lock);
+
+ return ret;
+}
+
+static int xe_eudebug_remove_handle(struct xe_eudebug *d, int type, void *p,
+ u64 *seqno)
+{
+ int ret;
+
+ ret = _xe_eudebug_remove_handle(d, type, p, seqno);
+
+ eu_dbg(d, "handle type %d handle %p removed: %d\n", type, p, ret);
+
+ return ret;
+}
+
+static struct drm_xe_eudebug_event *
+xe_eudebug_create_event(struct xe_eudebug *d, u16 type, u64 seqno, u16 flags,
+ u32 len)
+{
+ const u16 known_flags =
+ DRM_XE_EUDEBUG_EVENT_CREATE |
+ DRM_XE_EUDEBUG_EVENT_DESTROY |
+ DRM_XE_EUDEBUG_EVENT_STATE_CHANGE |
+ DRM_XE_EUDEBUG_EVENT_NEED_ACK;
+ struct drm_xe_eudebug_event *event;
+
+ BUILD_BUG_ON(type > XE_EUDEBUG_MAX_EVENT_TYPE);
+
+ xe_eudebug_assert(d, type <= XE_EUDEBUG_MAX_EVENT_TYPE);
+ xe_eudebug_assert(d, !(~known_flags & flags));
+ xe_eudebug_assert(d, len > sizeof(*event));
+
+ event = kzalloc(len, GFP_KERNEL);
+ if (!event)
+ return NULL;
+
+ event->len = len;
+ event->type = type;
+ event->flags = flags;
+ event->seqno = seqno;
+
+ return event;
+}
+
+static int send_vm_event(struct xe_eudebug *d, u32 flags,
+ const u64 vm_handle,
+ const u64 seqno)
+{
+ struct drm_xe_eudebug_event *event;
+ struct drm_xe_eudebug_event_vm *e;
+
+ event = xe_eudebug_create_event(d, DRM_XE_EUDEBUG_EVENT_VM,
+ seqno, flags, sizeof(*e));
+ if (!event)
+ return -ENOMEM;
+
+ e = cast_event(e, event);
+
+ e->vm_handle = vm_handle;
+
+ return xe_eudebug_queue_event(d, event);
+}
+
+static int vm_create_event(struct xe_eudebug *d,
+ struct xe_file *xef, struct xe_vm *vm)
+{
+ int vm_id;
+ u64 seqno;
+ int ret;
+
+ if (!xe_vm_in_lr_mode(vm))
+ return 0;
+
+ vm_id = xe_eudebug_add_handle(d, XE_EUDEBUG_RES_TYPE_VM, vm, &seqno);
+ if (vm_id < 0)
+ return vm_id;
+
+ ret = send_vm_event(d, DRM_XE_EUDEBUG_EVENT_CREATE, vm_id, seqno);
+ if (ret)
+ eu_dbg(d, "send_vm_event create error %d\n", ret);
+
+ return ret;
+}
+
+static int vm_destroy_event(struct xe_eudebug *d,
+ struct xe_file *xef, struct xe_vm *vm)
+{
+ int vm_id;
+ u64 seqno;
+ int ret;
+
+ if (!xe_vm_in_lr_mode(vm))
+ return 0;
+
+ vm_id = xe_eudebug_remove_handle(d, XE_EUDEBUG_RES_TYPE_VM, vm, &seqno);
+ if (vm_id < 0)
+ return vm_id;
+
+ ret = send_vm_event(d, DRM_XE_EUDEBUG_EVENT_DESTROY, vm_id, seqno);
+ if (ret)
+ eu_dbg(d, "send_vm_event destroy error %d\n", ret);
+
+ return ret;
+}
+
+#define xe_eudebug_event_put(_d, _err) ({ \
+ if ((_err)) \
+ xe_eudebug_disconnect((_d), (_err)); \
+ xe_eudebug_put((_d)); \
+ })
+
+void xe_eudebug_vm_create(struct xe_file *xef, struct xe_vm *vm)
+{
+ struct xe_eudebug *d;
+
+ if (!xe_vm_in_lr_mode(vm))
+ return;
+
+ d = xe_eudebug_get(xef);
+ if (!d)
+ return;
+
+ xe_eudebug_event_put(d, vm_create_event(d, xef, vm));
+}
+
+void xe_eudebug_vm_destroy(struct xe_file *xef, struct xe_vm *vm)
+{
+ struct xe_eudebug *d;
+
+ if (!xe_vm_in_lr_mode(vm))
+ return;
+
+ d = xe_eudebug_get(xef);
+ if (!d)
+ return;
+
+ xe_eudebug_event_put(d, vm_destroy_event(d, xef, vm));
+}
+
+static int add_debugger(struct xe_device *xe, struct xe_eudebug *d,
+ struct drm_file *target)
+{
+ struct xe_file *xef = target->driver_priv;
+ int ret = -EBUSY;
+
+ mutex_lock(&xef->eudebug.lock);
+ if (!xef->eudebug.debugger) {
+ d->target.xef = xe_file_get(xef);
+ d->target.pid = xef->pid;
+ kref_get(&d->ref);
+ xef->eudebug.debugger = d;
+ ret = 0;
+ }
+ mutex_unlock(&xef->eudebug.lock);
+
+ if (ret)
+ return ret;
+
+ mutex_lock(&xe->eudebug.lock);
+ XE_WARN_ON(!list_empty(&xef->eudebug.target_link));
+
+ d->session = ++xe->eudebug.session_count;
+ if (!d->session)
+ d->session = ++xe->eudebug.session_count;
+
+ list_add_tail(&xef->eudebug.target_link, &xef->xe->eudebug.targets);
+ mutex_unlock(&xe->eudebug.lock);
+
+ return 0;
+}
+
+static int
+xe_eudebug_attach(struct xe_device *xe, struct drm_file *parent_file,
+ struct xe_eudebug *d, u64 target_pidfd)
+{
+ struct file *file __free(fput) = NULL;
+ struct drm_file *drm_file;
+ struct xe_file *target_xef;
+ int ret;
+
+ file = fget(target_pidfd);
+ if (XE_IOCTL_DBG(xe, !file))
+ return -EBADFD;
+
+ drm_file = file->private_data;
+ if (XE_IOCTL_DBG(xe, !drm_file))
+ return -EINVAL;
+
+ if (XE_IOCTL_DBG(xe, parent_file->filp->f_op != file->f_op))
+ return -EINVAL;
+
+ target_xef = drm_file->driver_priv;
+ if (XE_IOCTL_DBG(xe, !target_xef))
+ return -EINVAL;
+
+ if (XE_IOCTL_DBG(xe, xe != target_xef->xe))
+ return -EINVAL;
+
+ ret = add_debugger(xe, d, drm_file);
+ if (XE_IOCTL_DBG(xe, ret))
+ return ret;
+
+ d->xe = xe;
+
+ eu_dbg(d, "session %lld attached to %s", d->session,
+ parent_file == drm_file ? "self" : "remote");
+
+ return 0;
+}
+
+static int xe_eudebug_release(struct inode *inode, struct file *file)
+{
+ struct xe_eudebug *d = file->private_data;
+
+ xe_eudebug_disconnect(d, 0);
+ xe_eudebug_put(d);
+
+ return 0;
+}
+
+static __poll_t xe_eudebug_poll(struct file *file, poll_table *wait)
+{
+ struct xe_eudebug * const d = file->private_data;
+ __poll_t ret = 0;
+
+ poll_wait(file, &d->events.write_done, wait);
+
+ if (xe_eudebug_detached(d)) {
+ ret |= EPOLLHUP;
+ if (d->target.err)
+ ret |= EPOLLERR;
+ }
+
+ if (event_fifo_num_events_peek(d))
+ ret |= EPOLLIN;
+
+ return ret;
+}
+
+static ssize_t xe_eudebug_read(struct file *file,
+ char __user *buf,
+ size_t count,
+ loff_t *ppos)
+{
+ return -EINVAL;
+}
+
+static long xe_eudebug_read_event(struct xe_eudebug *d,
+ const u64 arg,
+ const bool wait)
+{
+ struct xe_device *xe = d->xe;
+ struct drm_xe_eudebug_event __user * const user_orig =
+ u64_to_user_ptr(arg);
+ struct drm_xe_eudebug_event user_event;
+ struct drm_xe_eudebug_event *pending, *event_out;
+ long ret = 0;
+
+ if (XE_IOCTL_DBG(xe, copy_from_user(&user_event, user_orig, sizeof(user_event))))
+ return -EFAULT;
+
+ if (XE_IOCTL_DBG(xe, user_event.type != DRM_XE_EUDEBUG_EVENT_READ))
+ return -EINVAL;
+
+ if (XE_IOCTL_DBG(xe, user_event.len < sizeof(*user_orig)))
+ return -EINVAL;
+
+ if (XE_IOCTL_DBG(xe, user_event.flags))
+ return -EINVAL;
+
+ if (XE_IOCTL_DBG(xe, user_event.seqno))
+ return -EINVAL;
+
+ if (XE_IOCTL_DBG(xe, user_event.reserved))
+ return -EINVAL;
+
+ /* XXX: define wait time in connect arguments ? */
+ if (wait) {
+ ret = wait_event_interruptible_timeout(d->events.write_done,
+ event_fifo_has_events(d),
+ msecs_to_jiffies(5 * 1000));
+
+ if (XE_IOCTL_DBG(xe, ret < 0))
+ return ret;
+ }
+
+ if (XE_IOCTL_DBG(xe, xe_eudebug_detached(d)))
+ return -ENOTCONN;
+
+ event_out = NULL;
+ spin_lock(&d->events.lock);
+ pending = event_fifo_pending(d);
+ if (!pending)
+ ret = wait ? -ETIMEDOUT : -EAGAIN;
+ else if (user_event.len < pending->len)
+ ret = -EMSGSIZE;
+ else if (access_ok(user_orig, pending->len))
+ ret = kfifo_out(&d->events.fifo, &event_out, 1) == 1 ? 0 : -EIO;
+ else
+ ret = -EFAULT;
+
+ wake_up_all(&d->events.read_done);
+ spin_unlock(&d->events.lock);
+
+ if (!pending)
+ return ret;
+
+ if (ret == -EMSGSIZE) {
+ if (XE_IOCTL_DBG(xe, put_user(pending->len, &user_orig->len)))
+ return -EFAULT;
+
+ return -EMSGSIZE;
+ }
+
+ if (XE_IOCTL_DBG(xe, ret)) {
+ xe_eudebug_disconnect(d, (int)ret);
+ return ret;
+ }
+
+ XE_WARN_ON(pending != event_out);
+
+ if (__copy_to_user(user_orig, event_out, event_out->len)) {
+ ret = -EFAULT;
+ /* We can't rollback anymore, disconnect */
+ xe_eudebug_disconnect(d, -EFAULT);
+ }
+
+ eu_dbg(d, "event read=%ld: type=%u, flags=0x%x, seqno=%llu", ret,
+ event_out->type, event_out->flags, event_out->seqno);
+
+ kfree(event_out);
+
+ return ret;
+}
+
+static long xe_eudebug_ioctl(struct file *file,
+ unsigned int cmd,
+ unsigned long arg)
+{
+ struct xe_eudebug * const d = file->private_data;
+ long ret;
+
+ switch (cmd) {
+ case DRM_XE_EUDEBUG_IOCTL_READ_EVENT:
+ ret = xe_eudebug_read_event(d, arg,
+ !(file->f_flags & O_NONBLOCK));
+ break;
+
+ default:
+ ret = -EINVAL;
+ }
+
+ return ret;
+}
+
+static const struct file_operations fops = {
+ .owner = THIS_MODULE,
+ .release = xe_eudebug_release,
+ .poll = xe_eudebug_poll,
+ .read = xe_eudebug_read,
+ .unlocked_ioctl = xe_eudebug_ioctl,
+};
+
+static int
+xe_eudebug_connect(struct xe_device *xe,
+ struct drm_file *drm_file,
+ struct drm_xe_eudebug_connect *param)
+{
+ const u64 known_open_flags = 0;
+ unsigned long f_flags = 0;
+ struct xe_eudebug *d;
+ struct file *file;
+ int fd, err;
+
+ if (XE_IOCTL_DBG(xe, param->extensions))
+ return -EINVAL;
+
+ if (XE_IOCTL_DBG(xe, !param->fd))
+ return -EINVAL;
+
+ if (XE_IOCTL_DBG(xe, param->flags & ~known_open_flags))
+ return -EINVAL;
+
+ if (XE_IOCTL_DBG(xe, param->version &&
+ param->version != DRM_XE_EUDEBUG_VERSION))
+ return -EINVAL;
+
+ param->version = DRM_XE_EUDEBUG_VERSION;
+
+ mutex_lock(&xe->eudebug.lock);
+ err = xe_eudebug_is_enabled(xe) ? 0 : -EOPNOTSUPP;
+ mutex_unlock(&xe->eudebug.lock);
+
+ if (XE_IOCTL_DBG(xe, err))
+ return err;
+
+ d = kzalloc_obj(*d, GFP_KERNEL);
+ if (XE_IOCTL_DBG(xe, !d))
+ return -ENOMEM;
+
+ kref_init(&d->ref);
+ mutex_init(&d->target.lock);
+ init_waitqueue_head(&d->events.write_done);
+ init_waitqueue_head(&d->events.read_done);
+
+ spin_lock_init(&d->events.lock);
+ INIT_KFIFO(d->events.fifo);
+
+ err = xe_eudebug_resources_init(d);
+ if (XE_IOCTL_DBG(xe, err))
+ goto err_free;
+
+ err = xe_eudebug_attach(xe, drm_file, d, param->fd);
+ if (XE_IOCTL_DBG(xe, err))
+ goto err_free_res;
+
+ fd = get_unused_fd_flags(f_flags);
+ if (fd < 0) {
+ err = fd;
+ goto err_detach;
+ }
+
+ file = anon_inode_getfile("[xe_eudebug]", &fops, d, f_flags);
+ if (IS_ERR(file)) {
+ err = PTR_ERR(file);
+ goto err_fd;
+ }
+
+ eu_dbg(d, "connected session %lld", d->session);
+
+ fd_install(fd, file);
+
+ return fd;
+
+err_fd:
+ put_unused_fd(fd);
+err_detach:
+ xe_eudebug_detach(xe, d, err);
+err_free_res:
+ xe_eudebug_resources_destroy(d);
+err_free:
+ mutex_destroy(&d->target.lock);
+ kfree(d);
+
+ return err;
+}
+
+void xe_eudebug_file_close(struct xe_file *xef)
+{
+ remove_debugger(xef);
+}
+
+bool xe_eudebug_is_enabled(struct xe_device *xe)
+{
+ return READ_ONCE(xe->eudebug.state) == XE_EUDEBUG_ENABLED;
+}
+
+int xe_eudebug_enable(struct xe_device *xe, bool enable)
+{
+ mutex_lock(&xe->eudebug.lock);
+
+ if (xe->eudebug.state == XE_EUDEBUG_NOT_SUPPORTED) {
+ mutex_unlock(&xe->eudebug.lock);
+ return -EPERM;
+ }
+
+ if (!enable && !list_empty(&xe->eudebug.targets)) {
+ mutex_unlock(&xe->eudebug.lock);
+ return -EBUSY;
+ }
+
+ if (enable == xe_eudebug_is_enabled(xe)) {
+ mutex_unlock(&xe->eudebug.lock);
+ return 0;
+ }
+
+ xe->eudebug.state = enable ?
+ XE_EUDEBUG_ENABLED : XE_EUDEBUG_DISABLED;
+ mutex_unlock(&xe->eudebug.lock);
+
+ return 0;
+}
+
+static ssize_t enable_eudebug_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct xe_device *xe = pdev_to_xe_device(to_pci_dev(dev));
+
+ return sysfs_emit(buf, "%u\n", xe_eudebug_is_enabled(xe));
+}
+
+static ssize_t enable_eudebug_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct xe_device *xe = pdev_to_xe_device(to_pci_dev(dev));
+ bool enable;
+ int ret;
+
+ ret = kstrtobool(buf, &enable);
+ if (ret)
+ return ret;
+
+ ret = xe_eudebug_enable(xe, enable);
+ if (ret)
+ return ret;
+
+ return count;
+}
+
+static DEVICE_ATTR_RW(enable_eudebug);
+
+static void xe_eudebug_sysfs_fini(void *arg)
+{
+ struct xe_device *xe = arg;
+ struct drm_device *dev = &xe->drm;
+
+ sysfs_remove_file(&dev->dev->kobj,
+ &dev_attr_enable_eudebug.attr);
+}
+
+void xe_eudebug_init(struct xe_device *xe)
+{
+ struct drm_device *dev = &xe->drm;
+ int err;
+
+ INIT_LIST_HEAD(&xe->eudebug.targets);
+
+ xe->eudebug.state = XE_EUDEBUG_NOT_SUPPORTED;
+
+ err = drmm_mutex_init(dev, &xe->eudebug.lock);
+ if (err)
+ goto out_err;
+
+ err = sysfs_create_file(&dev->dev->kobj,
+ &dev_attr_enable_eudebug.attr);
+ if (err)
+ goto out_err;
+
+ err = devm_add_action_or_reset(dev->dev, xe_eudebug_sysfs_fini, xe);
+ if (err)
+ goto out_err;
+
+ xe->eudebug.state = XE_EUDEBUG_DISABLED;
+
+ return;
+
+out_err:
+ drm_warn(&xe->drm, "eudebug disabled, init fail: %d\n", err);
+}
+
+int xe_eudebug_connect_ioctl(struct drm_device *dev,
+ void *data,
+ struct drm_file *file)
+{
+ struct xe_device *xe = to_xe_device(dev);
+ struct drm_xe_eudebug_connect * const param = data;
+
+ return xe_eudebug_connect(xe, file, param);
+}
diff --git a/drivers/gpu/drm/xe/xe_eudebug.h b/drivers/gpu/drm/xe/xe_eudebug.h
new file mode 100644
index 000000000000..22fbb2ff24da
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_eudebug.h
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023-2025 Intel Corporation
+ */
+
+#ifndef _XE_EUDEBUG_H_
+#define _XE_EUDEBUG_H_
+
+#include <linux/types.h>
+
+struct drm_device;
+struct drm_file;
+struct xe_device;
+struct xe_file;
+struct xe_vm;
+
+#if IS_ENABLED(CONFIG_DRM_XE_EUDEBUG)
+
+#define XE_EUDEBUG_DBG_STR "eudbg: %lld:%lu:%s (%d/%d) -> (%d): "
+#define XE_EUDEBUG_DBG_ARGS(d) (d)->session, \
+ atomic_long_read(&(d)->events.seqno), \
+ !READ_ONCE(d->target.xef) ? "disconnected" : "", \
+ current->pid, \
+ task_tgid_nr(current), \
+ READ_ONCE(d->target.xef) ? d->target.xef->pid : -1
+
+#define eu_err(d, fmt, ...) drm_err(&(d)->xe->drm, XE_EUDEBUG_DBG_STR # fmt, \
+ XE_EUDEBUG_DBG_ARGS(d), ##__VA_ARGS__)
+#define eu_warn(d, fmt, ...) drm_warn(&(d)->xe->drm, XE_EUDEBUG_DBG_STR # fmt, \
+ XE_EUDEBUG_DBG_ARGS(d), ##__VA_ARGS__)
+#define eu_dbg(d, fmt, ...) drm_dbg(&(d)->xe->drm, XE_EUDEBUG_DBG_STR # fmt, \
+ XE_EUDEBUG_DBG_ARGS(d), ##__VA_ARGS__)
+
+#define xe_eudebug_assert(d, ...) xe_assert((d)->xe, ##__VA_ARGS__)
+
+int xe_eudebug_connect_ioctl(struct drm_device *dev,
+ void *data,
+ struct drm_file *file);
+
+void xe_eudebug_init(struct xe_device *xe);
+bool xe_eudebug_is_enabled(struct xe_device *xe);
+
+void xe_eudebug_file_close(struct xe_file *xef);
+
+void xe_eudebug_vm_create(struct xe_file *xef, struct xe_vm *vm);
+void xe_eudebug_vm_destroy(struct xe_file *xef, struct xe_vm *vm);
+int xe_eudebug_enable(struct xe_device *xe, bool enable);
+
+#else
+
+static inline int xe_eudebug_connect_ioctl(struct drm_device *dev,
+ void *data,
+ struct drm_file *file) { return 0; }
+
+static inline void xe_eudebug_init(struct xe_device *xe) { }
+static inline bool xe_eudebug_is_enabled(struct xe_device *xe) { return false; }
+
+static inline void xe_eudebug_file_close(struct xe_file *xef) { }
+
+static inline void xe_eudebug_vm_create(struct xe_file *xef, struct xe_vm *vm) { }
+static inline void xe_eudebug_vm_destroy(struct xe_file *xef, struct xe_vm *vm) { }
+
+#endif /* CONFIG_DRM_XE_EUDEBUG */
+
+#endif /* _XE_EUDEBUG_H_ */
diff --git a/drivers/gpu/drm/xe/xe_eudebug_types.h b/drivers/gpu/drm/xe/xe_eudebug_types.h
new file mode 100644
index 000000000000..a73eb6c98b02
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_eudebug_types.h
@@ -0,0 +1,121 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023-2025 Intel Corporation
+ */
+
+#ifndef _XE_EUDEBUG_TYPES_H_
+#define _XE_EUDEBUG_TYPES_H_
+
+#include <linux/completion.h>
+#include <linux/kfifo.h>
+#include <linux/kref.h>
+#include <linux/mutex.h>
+#include <linux/rbtree.h>
+#include <linux/rhashtable.h>
+#include <linux/wait.h>
+#include <linux/xarray.h>
+
+struct xe_device;
+struct task_struct;
+
+/**
+ * enum xe_eudebug_state - eudebug capability state
+ *
+ * @XE_EUDEBUG_NOT_SUPPORTED: eudebug feature support off
+ * @XE_EUDEBUG_DISABLED: eudebug feature supported but disabled
+ * @XE_EUDEBUG_ENABLED: eudebug enabled
+ */
+enum xe_eudebug_state {
+ XE_EUDEBUG_NOT_SUPPORTED = 0,
+ XE_EUDEBUG_DISABLED,
+ XE_EUDEBUG_ENABLED,
+};
+
+#define CONFIG_DRM_XE_DEBUGGER_EVENT_QUEUE_SIZE 64
+#define XE_EUDEBUG_MAX_EVENT_TYPE DRM_XE_EUDEBUG_EVENT_VM
+
+/**
+ * struct xe_eudebug_handle - eudebug resource handle
+ */
+struct xe_eudebug_handle {
+ /** @key: key value in rhashtable <key:id> */
+ u64 key;
+
+ /** @id: opaque handle id for xarray <id:key> */
+ int id;
+
+ /** @rh_head: rhashtable head */
+ struct rhash_head rh_head;
+};
+
+/**
+ * struct xe_eudebug_resource - Resource map for one resource
+ */
+struct xe_eudebug_resource {
+ /** @xa: xarrays for <id->key> */
+ struct xarray xa;
+
+ /** @rh: rhashtable for <key->id> */
+ struct rhashtable rh;
+};
+
+#define XE_EUDEBUG_RES_TYPE_VM 0
+#define XE_EUDEBUG_RES_TYPE_COUNT (XE_EUDEBUG_RES_TYPE_VM + 1)
+
+/**
+ * struct xe_eudebug - Top level struct for eudebug: the connection
+ */
+struct xe_eudebug {
+ /** @ref: kref counter for this struct */
+ struct kref ref;
+
+ /** @target: debug target specifics */
+ struct {
+ /** @xef: the target xe_file that we are debugging */
+ struct xe_file *xef;
+
+ /** @pid: pid of target */
+ pid_t pid;
+
+ /** @err: error code on disconnect */
+ int err;
+
+ /** @lock: guards access to xef and err */
+ struct mutex lock;
+
+ /** @rt: resource maps for all types */
+ struct xe_eudebug_resource res[XE_EUDEBUG_RES_TYPE_COUNT];
+ } target;
+
+ /** @xe: the parent device we are serving */
+ struct xe_device *xe;
+
+ /** @res: the resource maps we track for target_task */
+ struct xe_eudebug_resources *res;
+
+ /** @session: session number for this connection (for logs) */
+ u64 session;
+
+ /** @events: kfifo queue of to-be-delivered events */
+ struct {
+ /** @lock: guards access to fifo */
+ spinlock_t lock;
+
+ /** @fifo: queue of events pending */
+ DECLARE_KFIFO(fifo,
+ struct drm_xe_eudebug_event *,
+ CONFIG_DRM_XE_DEBUGGER_EVENT_QUEUE_SIZE);
+
+ /** @write_done: waitqueue for signalling write to fifo */
+ wait_queue_head_t write_done;
+
+ /** @read_done: waitqueue for signalling read from fifo */
+ wait_queue_head_t read_done;
+
+ /** @event_seqno: seqno counter to stamp events for fifo */
+ atomic_long_t seqno;
+ } events;
+
+};
+
+#endif /* _XE_EUDEBUG_TYPES_H_ */
diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
index c3836f6eab35..456ee3bc4073 100644
--- a/drivers/gpu/drm/xe/xe_vm.c
+++ b/drivers/gpu/drm/xe/xe_vm.c
@@ -26,6 +26,7 @@
#include "xe_bo.h"
#include "xe_device.h"
#include "xe_drm_client.h"
+#include "xe_eudebug.h"
#include "xe_exec_queue.h"
#include "xe_gt.h"
#include "xe_migrate.h"
@@ -2104,6 +2105,8 @@ int xe_vm_create_ioctl(struct drm_device *dev, void *data,
args->vm_id = id;
+ xe_eudebug_vm_create(xef, vm);
+
return 0;
err_close_and_put:
@@ -2135,8 +2138,10 @@ int xe_vm_destroy_ioctl(struct drm_device *dev, void *data,
xa_erase(&xef->vm.xa, args->vm_id);
mutex_unlock(&xef->vm.lock);
- if (!err)
+ if (!err) {
+ xe_eudebug_vm_destroy(xef, vm);
xe_vm_close_and_put(vm);
+ }
return err;
}
diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
index 48e9f1fdb78d..acacd9e7e1e0 100644
--- a/include/uapi/drm/xe_drm.h
+++ b/include/uapi/drm/xe_drm.h
@@ -110,6 +110,7 @@ extern "C" {
#define DRM_XE_VM_QUERY_MEM_RANGE_ATTRS 0x0d
#define DRM_XE_EXEC_QUEUE_SET_PROPERTY 0x0e
#define DRM_XE_VM_GET_PROPERTY 0x0f
+#define DRM_XE_EUDEBUG_CONNECT 0x10
/* Must be kept compact -- no holes */
@@ -129,6 +130,7 @@ extern "C" {
#define DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_VM_QUERY_MEM_RANGE_ATTRS, struct drm_xe_vm_query_mem_range_attr)
#define DRM_IOCTL_XE_EXEC_QUEUE_SET_PROPERTY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_SET_PROPERTY, struct drm_xe_exec_queue_set_property)
#define DRM_IOCTL_XE_VM_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_VM_GET_PROPERTY, struct drm_xe_vm_get_property)
+#define DRM_IOCTL_XE_EUDEBUG_CONNECT DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EUDEBUG_CONNECT, struct drm_xe_eudebug_connect)
/**
* DOC: Xe IOCTL Extensions
@@ -2609,6 +2611,33 @@ enum drm_xe_ras_error_component {
[DRM_XE_RAS_ERR_COMP_SOC_INTERNAL] = "soc-internal" \
}
+/*
+ * struct drm_xe_eudebug_connect - Input of &DRM_IOCTL_XE_EUDEBUG_CONNECT
+ *
+ * This structure is used to connect to an eudebug interface of target drm file.
+ */
+struct drm_xe_eudebug_connect {
+ /** @extensions: Pointer to the first extension struct, if any */
+ __u64 extensions;
+
+ /** @fd: Debug target DRM client fd */
+ __u64 fd;
+
+ /** @flags: Flags (MBZ) */
+ __u32 flags;
+
+ /**
+ * @version: Current ABI (ioctl / events) version.
+ *
+ * If zero, current version supported in return.
+ * If non zero, the version requested.
+ */
+ __u32 version;
+#define DRM_XE_EUDEBUG_VERSION 1
+};
+
+#include "xe_drm_eudebug.h"
+
#if defined(__cplusplus)
}
#endif
diff --git a/include/uapi/drm/xe_drm_eudebug.h b/include/uapi/drm/xe_drm_eudebug.h
new file mode 100644
index 000000000000..cdb4e4af4879
--- /dev/null
+++ b/include/uapi/drm/xe_drm_eudebug.h
@@ -0,0 +1,80 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#ifndef _UAPI_XE_DRM_EUDEBUG_H_
+#define _UAPI_XE_DRM_EUDEBUG_H_
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define DRM_XE_EUDEBUG_IOCTL_READ_EVENT _IO('j', 0x0)
+
+/**
+ * struct drm_xe_eudebug_event - Base type of event delivered by xe_eudebug.
+ *
+ * Base event for xe_eudebug interface.
+ *
+ * For receiving events :c:member:`drm_xe_eudebug_event.type` has to
+ * be DRM_XE_EUDEBUG_EVENT_READ. On return, this is set to the type
+ * of event received. :c:member:`drm_xe_eudebug_event.len` has to be
+ * set to maximum size that can be received. On return, len will be set
+ * to the event size. If the pending event was larger than this size,
+ * -EMSGSIZE is returned instead of 0 and the caller should retry with a larger
+ * allocated receive length.
+ *
+ * :c:member:`drm_xe_eudebug_event.seqno` can be used to form a timeline
+ * as event delivery order does not guarantee event creation
+ * order. Must be set to zero.
+ *
+ * :c:member:`drm_xe_eudebug_event.flags` will indicate if a resource was
+ * created, destroyed, or if its state changed. Must be set to zero.
+ *
+ * If DRM_XE_EUDEBUG_EVENT_NEED_ACK is set, xe_eudebug
+ * will hold the said resource until it is acked by userspace
+ * using the acking ioctl with the seqno of the said event.
+ */
+struct drm_xe_eudebug_event {
+ /** @len: Length */
+ __u32 len;
+
+ /** @type: Type */
+ __u16 type;
+#define DRM_XE_EUDEBUG_EVENT_NONE 0
+#define DRM_XE_EUDEBUG_EVENT_READ 1
+#define DRM_XE_EUDEBUG_EVENT_VM 2
+
+ /** @flags: Flags */
+ __u16 flags;
+#define DRM_XE_EUDEBUG_EVENT_CREATE (1 << 0)
+#define DRM_XE_EUDEBUG_EVENT_DESTROY (1 << 1)
+#define DRM_XE_EUDEBUG_EVENT_STATE_CHANGE (1 << 2)
+#define DRM_XE_EUDEBUG_EVENT_NEED_ACK (1 << 3)
+
+ /** @seqno: Sequence number to form a timeline */
+ __u64 seqno;
+
+ /** @reserved: Reserved field, must be zero. */
+ __u64 reserved;
+};
+
+/**
+ * struct drm_xe_eudebug_event_vm - VM event
+ *
+ * VM event is delivered when vm is created or destroyed.
+ */
+struct drm_xe_eudebug_event_vm {
+ /** @base: base event */
+ struct drm_xe_eudebug_event base;
+
+ /** @vm_handle: unique handle for vm */
+ __u64 vm_handle;
+};
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* _UAPI_XE_DRM_EUDEBUG_H_ */
--
2.43.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 02/24] drm/xe/eudebug: Add documentation
2026-04-30 10:50 [PATCH 00/24] Intel Xe GPU Debug Support (eudebug) v8 Mika Kuoppala
2026-04-30 10:50 ` [PATCH 01/24] drm/xe/eudebug: Introduce eudebug interface Mika Kuoppala
@ 2026-04-30 10:50 ` Mika Kuoppala
2026-04-30 10:50 ` [PATCH 03/24] drm/xe/eudebug: Add connection establishment documentation Mika Kuoppala
` (25 subsequent siblings)
27 siblings, 0 replies; 32+ messages in thread
From: Mika Kuoppala @ 2026-04-30 10:50 UTC (permalink / raw)
To: intel-xe
Cc: simona.vetter, matthew.brost, christian.koenig, thomas.hellstrom,
joonas.lahtinen, gustavo.sousa, jan.maslak,
dominik.karol.piatkowski, rodrigo.vivi, andrzej.hajda,
matthew.auld, maciej.patelczyk, gwan-gyeong.mun, Mika Kuoppala
Add a core documentation for connection setup and events.
Followup patches can then incrementally add their workings.
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
Documentation/gpu/xe/index.rst | 1 +
Documentation/gpu/xe/xe_eudebug.rst | 45 +++++++++++++++++++++++++++++
drivers/gpu/drm/xe/xe_eudebug.c | 41 ++++++++++++++++++++++++++
3 files changed, 87 insertions(+)
create mode 100644 Documentation/gpu/xe/xe_eudebug.rst
diff --git a/Documentation/gpu/xe/index.rst b/Documentation/gpu/xe/index.rst
index 874ffcb6da3a..3055b3ede093 100644
--- a/Documentation/gpu/xe/index.rst
+++ b/Documentation/gpu/xe/index.rst
@@ -30,3 +30,4 @@ DG2, etc is provided to prototype the driver.
xe-drm-usage-stats.rst
xe_configfs
xe_gt_stats
+ xe_eudebug
diff --git a/Documentation/gpu/xe/xe_eudebug.rst b/Documentation/gpu/xe/xe_eudebug.rst
new file mode 100644
index 000000000000..ff7fbc403ebb
--- /dev/null
+++ b/Documentation/gpu/xe/xe_eudebug.rst
@@ -0,0 +1,45 @@
+.. SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+===================================
+Xe EU Debug (eudebug)
+===================================
+
+Overview
+========
+
+The EU Debug (eudebug) subsystem provides an interface for debugging
+Execution Unit (EU) workloads on Intel Xe GPUs, independently from
+CPU process debugging. This enables tools like GDB (via gdbserver-intelgt)
+to debug GPU compute workloads through the Level-Zero Debug API.
+In practice, this means that SYCL/DPC++ workloads submitted by the
+compute-runtime can be debugged interactively at this time.
+
+
+Connection Establishment
+========================
+
+.. kernel-doc:: drivers/gpu/drm/xe/xe_eudebug.c
+ :doc: Connection Establishment
+
+Events
+======
+
+.. kernel-doc:: drivers/gpu/drm/xe/xe_eudebug.c
+ :doc: Events
+
+
+Base Event Header
+-----------------
+
+The debugger receives events by reading from the eudebug file descriptor
+using an read_event ioctl. Every event has :c:type:`drm_xe_eudebug_event`
+as a header
+
+.. kernel-doc:: include/uapi/drm/xe_drm_eudebug.h
+ :identifiers: drm_xe_eudebug_event
+
+Resource Event Types
+--------------------
+
+.. kernel-doc:: include/uapi/drm/xe_drm_eudebug.h
+ :identifiers: drm_xe_eudebug_event_vm
diff --git a/drivers/gpu/drm/xe/xe_eudebug.c b/drivers/gpu/drm/xe/xe_eudebug.c
index 02ecdbca46ff..f1d17f03054e 100644
--- a/drivers/gpu/drm/xe/xe_eudebug.c
+++ b/drivers/gpu/drm/xe/xe_eudebug.c
@@ -18,6 +18,25 @@
#include "xe_macros.h"
#include "xe_vm.h"
+/**
+ * DOC: Connection Establishment
+ *
+ * To debug a target DRM client, the debugger must first establish
+ * a connection using :c:type:`drm_xe_eudebug_connect`.
+ *
+ */
+
+/**
+ * DOC: Events
+ *
+ * Resource creation/destruction and hardware state changes are
+ * delivered as events for debugger.
+ *
+ * To read an event, ioctl DRM_XE_EUDEBUG_IOCTL_READ_EVENT command
+ * can be issued with prefilled :c:type:`drm_xe_eudebug_event` as argument.
+ *
+ */
+
/*
* If there is no detected event read by userspace, during this period, assume
* userspace problem and disconnect debugger to allow forward progress.
@@ -813,6 +832,17 @@ static long xe_eudebug_read_event(struct xe_eudebug *d,
return ret;
}
+/**
+ * xe_eudebug_ioctl - Issue a command to eudebug interface
+ *
+ * @file : eudebug file (returned from connect)
+ * @cmd : cmd
+ * @arg : arguments depending on cmd
+ *
+ * Issue a eudebug command
+ *
+ * Return: 0 on success, negative error code on failure.
+ */
static long xe_eudebug_ioctl(struct file *file,
unsigned int cmd,
unsigned long arg)
@@ -1029,6 +1059,17 @@ void xe_eudebug_init(struct xe_device *xe)
drm_warn(&xe->drm, "eudebug disabled, init fail: %d\n", err);
}
+/**
+ * xe_eudebug_connect_ioctl - Connect to eudebug interface
+ * @dev : DRM device
+ * @data : ioctl data, (struct drm_xe_eudebug_connect)
+ * @file : DRM file
+ *
+ * Connect to the eudebug interface.
+ *
+ * Return: eudebug filedesriptor on success, negative error code on failure.
+ *
+ */
int xe_eudebug_connect_ioctl(struct drm_device *dev,
void *data,
struct drm_file *file)
--
2.43.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 03/24] drm/xe/eudebug: Add connection establishment documentation
2026-04-30 10:50 [PATCH 00/24] Intel Xe GPU Debug Support (eudebug) v8 Mika Kuoppala
2026-04-30 10:50 ` [PATCH 01/24] drm/xe/eudebug: Introduce eudebug interface Mika Kuoppala
2026-04-30 10:50 ` [PATCH 02/24] drm/xe/eudebug: Add documentation Mika Kuoppala
@ 2026-04-30 10:50 ` Mika Kuoppala
2026-04-30 10:51 ` [PATCH 04/24] drm/xe/eudebug: Introduce discovery for resources Mika Kuoppala
` (24 subsequent siblings)
27 siblings, 0 replies; 32+ messages in thread
From: Mika Kuoppala @ 2026-04-30 10:50 UTC (permalink / raw)
To: intel-xe
Cc: simona.vetter, matthew.brost, christian.koenig, thomas.hellstrom,
joonas.lahtinen, gustavo.sousa, jan.maslak,
dominik.karol.piatkowski, rodrigo.vivi, andrzej.hajda,
matthew.auld, maciej.patelczyk, gwan-gyeong.mun, Mika Kuoppala
Add documentation for connecting to a target DRM Xe client
for debugging.
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
Documentation/gpu/xe/xe_eudebug.rst | 11 +++++
drivers/gpu/drm/xe/xe_eudebug.c | 70 +++++++++++++++++++++++++++++
2 files changed, 81 insertions(+)
diff --git a/Documentation/gpu/xe/xe_eudebug.rst b/Documentation/gpu/xe/xe_eudebug.rst
index ff7fbc403ebb..c21fa7c47ab8 100644
--- a/Documentation/gpu/xe/xe_eudebug.rst
+++ b/Documentation/gpu/xe/xe_eudebug.rst
@@ -21,6 +21,17 @@ Connection Establishment
.. kernel-doc:: drivers/gpu/drm/xe/xe_eudebug.c
:doc: Connection Establishment
+File Descriptor Acquisition Methods
+-----------------------------------
+
+.. kernel-doc:: drivers/gpu/drm/xe/xe_eudebug.c
+ :doc: File Descriptor Acquisition Methods
+
+Security Model
+--------------
+.. kernel-doc:: drivers/gpu/drm/xe/xe_eudebug.c
+ :doc: Security Model
+
Events
======
diff --git a/drivers/gpu/drm/xe/xe_eudebug.c b/drivers/gpu/drm/xe/xe_eudebug.c
index f1d17f03054e..f661b3ae9c9a 100644
--- a/drivers/gpu/drm/xe/xe_eudebug.c
+++ b/drivers/gpu/drm/xe/xe_eudebug.c
@@ -24,6 +24,76 @@
* To debug a target DRM client, the debugger must first establish
* a connection using :c:type:`drm_xe_eudebug_connect`.
*
+ * The debug target's DRM client file descriptor is passed into the
+ * connect ioctl via :c:member:`drm_xe_eudebug_connect.fd`.
+ * This is the fd that the target process obtained from open('/dev/dri/cardX').
+ *
+ * This file descriptor must be a valid DRM client fd in the debugger's
+ * (calling) process context. For debugging an Xe DRM client in
+ * another process, pidfd_getfd() can be used to acquire a duplicate
+ * of the file descriptor from the target process. See
+ * :ref:`File Descriptor Acquisition Methods <fd_acquisition_methods>` for
+ * details on how to obtain the target's fd.
+ *
+ */
+
+/**
+ * DOC: Security Model
+ *
+ * If you are inside the same process, you can connect to your own DRM client
+ * by simply passing its fd to drm_xe_eudebug_connect.
+ *
+ * The security model for connecting to a remote process uses
+ * file descriptor access via pidfd_getfd(). The kernel enforces
+ * credentials with ptrace_may_access(). So in order to connect to a
+ * remote DRM client, the same ptrace_may_access() checks apply
+ * as in CPU process debugging with gdb.
+ *
+ */
+
+/**
+ * DOC: File Descriptor Acquisition Methods
+ * .. _fd_acquisition_methods:
+ *
+ * There are multiple ways to get the target DRM client fd for
+ * another process:
+ *
+ * Unix domain socket
+ * The debugger can receive the DRM client fd from the target via a Unix
+ * domain socket using SCM_RIGHTS ancillary data. This is the standard
+ * mechanism for passing file descriptors between processes, but requires
+ * coordination to establish the socket connection.
+ *
+ * Pipe
+ * The debugger can acquire the DRM client fd through a pipe from the target.
+ * This requires coordination between the processes to establish
+ * a pipe to deliver the fd.
+ *
+ * Fork
+ * If the debugger spawns the target process, the DRM client fd can be
+ * inherited across fork(). The debugger opens the DRM device before
+ * forking, and the child process inherits the fd. This is useful
+ * when the debugger launches the target, similar to how gdb launches
+ * programs for debugging.
+ *
+ * Ptrace
+ * The debugger can attach to the target process using ptrace. It can
+ * intercept the return value of the target's open() or drmOpen() call
+ * by inspecting registers at syscall exit to catch the fd when it is
+ * created. Alternatively, if the target has already opened the device,
+ * the debugger can read the target's memory using PTRACE_PEEKDATA to
+ * locate the stored fd value in a known variable or data structure.
+ * Once the fd number is known, pidfd_getfd() can be used to acquire a
+ * duplicate in the debugger's process context.
+ *
+ * Procfs
+ * The debugger can look through /proc/<targetpid>/fd for file descriptors
+ * and inspect /proc/<targetpid>/fdinfo to see which of those
+ * are for an Xe DRM client.
+ *
+ * Brute force
+ * The debugger can traverse /proc/<targetpid>/fd descriptors
+ * and try to connect to each to see if it succeeds.
*/
/**
--
2.43.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 04/24] drm/xe/eudebug: Introduce discovery for resources
2026-04-30 10:50 [PATCH 00/24] Intel Xe GPU Debug Support (eudebug) v8 Mika Kuoppala
` (2 preceding siblings ...)
2026-04-30 10:50 ` [PATCH 03/24] drm/xe/eudebug: Add connection establishment documentation Mika Kuoppala
@ 2026-04-30 10:51 ` Mika Kuoppala
2026-04-30 10:51 ` [PATCH 05/24] drm/xe/eudebug: Introduce exec_queue events Mika Kuoppala
` (23 subsequent siblings)
27 siblings, 0 replies; 32+ messages in thread
From: Mika Kuoppala @ 2026-04-30 10:51 UTC (permalink / raw)
To: intel-xe
Cc: simona.vetter, matthew.brost, christian.koenig, thomas.hellstrom,
joonas.lahtinen, gustavo.sousa, jan.maslak,
dominik.karol.piatkowski, rodrigo.vivi, andrzej.hajda,
matthew.auld, maciej.patelczyk, gwan-gyeong.mun, Mika Kuoppala,
Dominik Grzegorzek
A debugger connection can occur after a client has created
and destroyed an arbitrary number of resources. To support
this, we need to relay all currently existing resources to
the debugger. The client is held on selected ioctls until
this discovery process, executed by a workqueue, is complete.
This patch is based on discovery work by Maciej Patelczyk
for the i915 driver.
v2: - use rw_semaphore to block DRM ioctls during discovery (Matthew)
- only lock according to ioctl at play (Dominik)
v4: - s/discovery_lock/ioctl_lock
- change lock to be per xe_file as is connections
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Co-developed-by: Maciej Patelczyk <maciej.patelczyk@intel.com>
Signed-off-by: Maciej Patelczyk <maciej.patelczyk@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Acked-by: Matthew Brost <matthew.brost@intel.com> #locking
---
drivers/gpu/drm/xe/xe_device.c | 13 +++-
drivers/gpu/drm/xe/xe_device.h | 42 +++++++++++
drivers/gpu/drm/xe/xe_device_types.h | 6 ++
drivers/gpu/drm/xe/xe_eudebug.c | 104 +++++++++++++++++++++++++-
drivers/gpu/drm/xe/xe_eudebug_types.h | 7 ++
5 files changed, 166 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index 4e6773cf806f..7f04951188d9 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -114,6 +114,7 @@ static int xe_file_open(struct drm_device *dev, struct drm_file *file)
#if IS_ENABLED(CONFIG_DRM_XE_EUDEBUG)
mutex_init(&xef->eudebug.lock);
INIT_LIST_HEAD(&xef->eudebug.target_link);
+ init_rwsem(&xef->eudebug.ioctl_lock);
#endif
file->driver_priv = xef;
@@ -241,8 +242,12 @@ static long xe_drm_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
ACQUIRE(xe_pm_runtime_ioctl, pm)(xe);
ret = ACQUIRE_ERR(xe_pm_runtime_ioctl, &pm);
- if (ret >= 0)
+ if (ret >= 0) {
+ bool lock = xe_eudebug_discovery_lock(file, cmd);
ret = drm_ioctl(file, cmd, arg);
+ if (lock)
+ xe_eudebug_discovery_unlock(file, cmd);
+ }
return ret;
}
@@ -259,8 +264,12 @@ static long xe_drm_compat_ioctl(struct file *file, unsigned int cmd, unsigned lo
ACQUIRE(xe_pm_runtime_ioctl, pm)(xe);
ret = ACQUIRE_ERR(xe_pm_runtime_ioctl, &pm);
- if (ret >= 0)
+ if (ret >= 0) {
+ bool lock = xe_eudebug_discovery_lock(file, cmd);
ret = drm_compat_ioctl(file, cmd, arg);
+ if (lock)
+ xe_eudebug_discovery_unlock(file, cmd);
+ }
return ret;
}
diff --git a/drivers/gpu/drm/xe/xe_device.h b/drivers/gpu/drm/xe/xe_device.h
index 355d69dc8f54..5a56050bf403 100644
--- a/drivers/gpu/drm/xe/xe_device.h
+++ b/drivers/gpu/drm/xe/xe_device.h
@@ -7,6 +7,7 @@
#define _XE_DEVICE_H_
#include <drm/drm_util.h>
+#include <drm/drm_ioctl.h>
#include "xe_device_types.h"
#include "xe_gt_types.h"
@@ -234,4 +235,45 @@ static inline bool xe_device_is_admin_only(const struct xe_device *xe)
#define LNL_FLUSH_WORK(wrk__) \
flush_work(wrk__)
+#if IS_ENABLED(CONFIG_DRM_XE_EUDEBUG)
+static inline int xe_eudebug_needs_ioctl_lock(const unsigned int cmd)
+{
+ const unsigned int xe_cmd = DRM_IOCTL_NR(cmd) - DRM_COMMAND_BASE;
+
+ switch (xe_cmd) {
+ case DRM_XE_VM_CREATE:
+ case DRM_XE_VM_DESTROY:
+ case DRM_XE_VM_BIND:
+ case DRM_XE_EXEC_QUEUE_CREATE:
+ case DRM_XE_EXEC_QUEUE_DESTROY:
+ return 1;
+ }
+
+ return 0;
+}
+
+static inline bool xe_eudebug_discovery_lock(struct file *file, unsigned int cmd)
+{
+ struct drm_file *file_priv = file->private_data;
+ struct xe_file *xef = file_priv->driver_priv;
+
+ if (!xe_eudebug_needs_ioctl_lock(cmd))
+ return false;
+
+ down_read(&xef->eudebug.ioctl_lock);
+ return true;
+}
+
+static inline void xe_eudebug_discovery_unlock(struct file *file, unsigned int cmd)
+{
+ struct drm_file *file_priv = file->private_data;
+ struct xe_file *xef = file_priv->driver_priv;
+
+ up_read(&xef->eudebug.ioctl_lock);
+}
+#else
+static inline bool xe_eudebug_discovery_lock(struct file *file, unsigned int cmd) { return false; }
+static inline void xe_eudebug_discovery_unlock(struct file *file, unsigned int cmd) { }
+#endif /* CONFIG_DRM_XE_EUDEBUG */
+
#endif
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 733f4ab391bd..b72edf776f93 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -584,6 +584,9 @@ struct xe_device {
/** @eudebug.lock: protects state and targets */
struct mutex lock;
+
+ /** @wq: used for client discovery */
+ struct workqueue_struct *wq;
} eudebug;
#endif
};
@@ -659,6 +662,9 @@ struct xe_file {
/** @target_link: link into xe_device.eudebug.targets */
struct list_head target_link;
+
+ /** @eudebug.ioctl_lock syncing ioctl access */
+ struct rw_semaphore ioctl_lock;
} eudebug;
#endif
};
diff --git a/drivers/gpu/drm/xe/xe_eudebug.c b/drivers/gpu/drm/xe/xe_eudebug.c
index f661b3ae9c9a..360273d25d51 100644
--- a/drivers/gpu/drm/xe/xe_eudebug.c
+++ b/drivers/gpu/drm/xe/xe_eudebug.c
@@ -35,6 +35,10 @@
* :ref:`File Descriptor Acquisition Methods <fd_acquisition_methods>` for
* details on how to obtain the target's fd.
*
+ * After a successful connection, all existing resources that the target Xe DRM
+ * client already has are sent as events, as if they had been
+ * created right after the connection. This is referred to as discovery.
+ *
*/
/**
@@ -241,6 +245,8 @@ static void xe_eudebug_free(struct kref *ref)
struct xe_eudebug *d = container_of(ref, typeof(*d), ref);
struct drm_xe_eudebug_event *event;
+ WARN_ON(work_pending(&d->discovery_work));
+
xe_assert(d->xe, xe_eudebug_detached(d));
while (kfifo_get(&d->events.fifo, &event))
@@ -302,6 +308,8 @@ static bool xe_eudebug_detach(struct xe_device *xe,
}
mutex_unlock(&d->target.lock);
+ flush_work(&d->discovery_work);
+
if (!target)
return false;
@@ -333,7 +341,7 @@ static int _xe_eudebug_disconnect(struct xe_eudebug *d,
})
static struct xe_eudebug *
-xe_eudebug_get(struct xe_file *xef)
+xe_eudebug_get_nolock(struct xe_file *xef)
{
struct xe_eudebug *d;
@@ -346,7 +354,8 @@ xe_eudebug_get(struct xe_file *xef)
if (!d)
return NULL;
- if (xe_eudebug_detached(d)) {
+ if (xe_eudebug_detached(d) ||
+ !completion_done(&d->discovery)) {
xe_eudebug_put(d);
return NULL;
}
@@ -354,6 +363,14 @@ xe_eudebug_get(struct xe_file *xef)
return d;
}
+static struct xe_eudebug *
+xe_eudebug_get(struct xe_file *xef)
+{
+ lockdep_assert_held(&xef->eudebug.ioctl_lock);
+
+ return xe_eudebug_get_nolock(xef);
+}
+
static int xe_eudebug_queue_event(struct xe_eudebug *d,
struct drm_xe_eudebug_event *event)
{
@@ -575,6 +592,8 @@ static int xe_eudebug_remove_handle(struct xe_eudebug *d, int type, void *p,
{
int ret;
+ XE_WARN_ON(!completion_done(&d->discovery));
+
ret = _xe_eudebug_remove_handle(d, type, p, seqno);
eu_dbg(d, "handle type %d handle %p removed: %d\n", type, p, ret);
@@ -706,6 +725,66 @@ void xe_eudebug_vm_destroy(struct xe_file *xef, struct xe_vm *vm)
xe_eudebug_event_put(d, vm_destroy_event(d, xef, vm));
}
+static struct xe_file *xe_eudebug_target_get(struct xe_eudebug *d)
+{
+ struct xe_file *xef = NULL;
+
+ mutex_lock(&d->target.lock);
+ if (d->target.xef)
+ xef = xe_file_get(d->target.xef);
+ mutex_unlock(&d->target.lock);
+
+ return xef;
+}
+
+static void discover_client(struct xe_eudebug *d)
+{
+ struct xe_file *xef;
+ struct xe_vm *vm;
+ unsigned long i;
+ unsigned int vm_count = 0;
+ int err = 0;
+
+ xef = xe_eudebug_target_get(d);
+ if (!xef)
+ return;
+
+ down_write(&xef->eudebug.ioctl_lock);
+
+ eu_dbg(d, "Discovery start for %lld", d->session);
+
+ xa_for_each(&xef->vm.xa, i, vm) {
+ err = vm_create_event(d, xef, vm);
+ if (err)
+ break;
+ vm_count++;
+ }
+
+ complete_all(&d->discovery);
+
+ eu_dbg(d, "Discovery end for %lld: %d", d->session, err);
+
+ up_write(&xef->eudebug.ioctl_lock);
+
+ if (vm_count)
+ eu_dbg(d, "Discovery found %u vms", vm_count);
+
+ xe_file_put(xef);
+}
+
+static void discovery_work_fn(struct work_struct *work)
+{
+ struct xe_eudebug *d = container_of(work, typeof(*d),
+ discovery_work);
+
+ if (xe_eudebug_detached(d))
+ complete_all(&d->discovery);
+ else
+ discover_client(d);
+
+ xe_eudebug_put(d);
+}
+
static int add_debugger(struct xe_device *xe, struct xe_eudebug *d,
struct drm_file *target)
{
@@ -920,6 +999,10 @@ static long xe_eudebug_ioctl(struct file *file,
struct xe_eudebug * const d = file->private_data;
long ret;
+ if (cmd != DRM_XE_EUDEBUG_IOCTL_READ_EVENT &&
+ !completion_done(&d->discovery))
+ return -EBUSY;
+
switch (cmd) {
case DRM_XE_EUDEBUG_IOCTL_READ_EVENT:
ret = xe_eudebug_read_event(d, arg,
@@ -982,9 +1065,11 @@ xe_eudebug_connect(struct xe_device *xe,
mutex_init(&d->target.lock);
init_waitqueue_head(&d->events.write_done);
init_waitqueue_head(&d->events.read_done);
+ init_completion(&d->discovery);
spin_lock_init(&d->events.lock);
INIT_KFIFO(d->events.fifo);
+ INIT_WORK(&d->discovery_work, discovery_work_fn);
err = xe_eudebug_resources_init(d);
if (XE_IOCTL_DBG(xe, err))
@@ -1006,10 +1091,13 @@ xe_eudebug_connect(struct xe_device *xe,
goto err_fd;
}
- eu_dbg(d, "connected session %lld", d->session);
-
fd_install(fd, file);
+ kref_get(&d->ref); /* for discovery */
+ queue_work(xe->eudebug.wq, &d->discovery_work);
+
+ eu_dbg(d, "connected session %lld", d->session);
+
return fd;
err_fd:
@@ -1102,6 +1190,7 @@ static void xe_eudebug_sysfs_fini(void *arg)
void xe_eudebug_init(struct xe_device *xe)
{
struct drm_device *dev = &xe->drm;
+ struct workqueue_struct *wq;
int err;
INIT_LIST_HEAD(&xe->eudebug.targets);
@@ -1112,6 +1201,13 @@ void xe_eudebug_init(struct xe_device *xe)
if (err)
goto out_err;
+ wq = drmm_alloc_ordered_workqueue(dev, "xe-eudebug", 0);
+ if (IS_ERR(wq)) {
+ err = PTR_ERR(wq);
+ goto out_err;
+ }
+ xe->eudebug.wq = wq;
+
err = sysfs_create_file(&dev->dev->kobj,
&dev_attr_enable_eudebug.attr);
if (err)
diff --git a/drivers/gpu/drm/xe/xe_eudebug_types.h b/drivers/gpu/drm/xe/xe_eudebug_types.h
index a73eb6c98b02..d7625e55d711 100644
--- a/drivers/gpu/drm/xe/xe_eudebug_types.h
+++ b/drivers/gpu/drm/xe/xe_eudebug_types.h
@@ -17,6 +17,7 @@
struct xe_device;
struct task_struct;
+struct workqueue_struct;
/**
* enum xe_eudebug_state - eudebug capability state
@@ -96,6 +97,12 @@ struct xe_eudebug {
/** @session: session number for this connection (for logs) */
u64 session;
+ /** @discovery: completion to wait for discovery */
+ struct completion discovery;
+
+ /** @discovery_work: worker to discover resources for target_task */
+ struct work_struct discovery_work;
+
/** @events: kfifo queue of to-be-delivered events */
struct {
/** @lock: guards access to fifo */
--
2.43.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 05/24] drm/xe/eudebug: Introduce exec_queue events
2026-04-30 10:50 [PATCH 00/24] Intel Xe GPU Debug Support (eudebug) v8 Mika Kuoppala
` (3 preceding siblings ...)
2026-04-30 10:51 ` [PATCH 04/24] drm/xe/eudebug: Introduce discovery for resources Mika Kuoppala
@ 2026-04-30 10:51 ` Mika Kuoppala
2026-04-30 10:51 ` [PATCH 06/24] drm/xe: Add EUDEBUG_ENABLE exec queue property Mika Kuoppala
` (22 subsequent siblings)
27 siblings, 0 replies; 32+ messages in thread
From: Mika Kuoppala @ 2026-04-30 10:51 UTC (permalink / raw)
To: intel-xe
Cc: simona.vetter, matthew.brost, christian.koenig, thomas.hellstrom,
joonas.lahtinen, gustavo.sousa, jan.maslak,
dominik.karol.piatkowski, rodrigo.vivi, andrzej.hajda,
matthew.auld, maciej.patelczyk, gwan-gyeong.mun,
Dominik Grzegorzek, Mika Kuoppala
From: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Add events to inform the debugger about the creation and destruction of
exec_queues. Use user engine class types instead of the internal
xe_engine_class enum in exec_queue events. During discovery, only advertise
exec_queues with render or compute class,excluding others.
v2: - Only track long running queues
- Checkpatch (Tilak)
v3: __counted_by added
v4: - use helpers for filtering engines (Mika)
v5: - fix lrc handles memcpy size bug (Mika)
Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Signed-off-by: Maciej Patelczyk <maciej.patelczyk@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
Documentation/gpu/xe/xe_eudebug.rst | 3 +
drivers/gpu/drm/xe/xe_eudebug.c | 216 +++++++++++++++++++++++++-
drivers/gpu/drm/xe/xe_eudebug.h | 7 +
drivers/gpu/drm/xe/xe_eudebug_types.h | 7 +-
drivers/gpu/drm/xe/xe_exec_queue.c | 5 +
drivers/gpu/drm/xe/xe_hw_engine.h | 14 ++
include/uapi/drm/xe_drm_eudebug.h | 26 ++++
7 files changed, 273 insertions(+), 5 deletions(-)
diff --git a/Documentation/gpu/xe/xe_eudebug.rst b/Documentation/gpu/xe/xe_eudebug.rst
index c21fa7c47ab8..e191e2c8ded4 100644
--- a/Documentation/gpu/xe/xe_eudebug.rst
+++ b/Documentation/gpu/xe/xe_eudebug.rst
@@ -54,3 +54,6 @@ Resource Event Types
.. kernel-doc:: include/uapi/drm/xe_drm_eudebug.h
:identifiers: drm_xe_eudebug_event_vm
+
+.. kernel-doc:: include/uapi/drm/xe_drm_eudebug.h
+ :identifiers: drm_xe_eudebug_event_exec_queue
diff --git a/drivers/gpu/drm/xe/xe_eudebug.c b/drivers/gpu/drm/xe/xe_eudebug.c
index 360273d25d51..64ac465725c5 100644
--- a/drivers/gpu/drm/xe/xe_eudebug.c
+++ b/drivers/gpu/drm/xe/xe_eudebug.c
@@ -15,6 +15,8 @@
#include "xe_device.h"
#include "xe_eudebug.h"
#include "xe_eudebug_types.h"
+#include "xe_exec_queue.h"
+#include "xe_hw_engine.h"
#include "xe_macros.h"
#include "xe_vm.h"
@@ -470,6 +472,28 @@ __find_handle(struct xe_eudebug_resource *r,
return h;
}
+static int find_handle(struct xe_eudebug *d,
+ const int type,
+ const void *p)
+{
+ const u64 key = (uintptr_t)p;
+ struct xe_eudebug_resource *r;
+ struct xe_eudebug_handle *h;
+ int id;
+
+ if (XE_WARN_ON(!key))
+ return -EINVAL;
+
+ r = resource_from_type(d, type);
+
+ mutex_lock(&d->target.lock);
+ h = __find_handle(r, key);
+ id = h ? h->id : -ENOENT;
+ mutex_unlock(&d->target.lock);
+
+ return id;
+}
+
static int _xe_eudebug_add_handle(struct xe_eudebug *d,
int type,
void *p,
@@ -725,6 +749,181 @@ void xe_eudebug_vm_destroy(struct xe_file *xef, struct xe_vm *vm)
xe_eudebug_event_put(d, vm_destroy_event(d, xef, vm));
}
+static const u16 xe_to_user_engine_class[] = {
+ [XE_ENGINE_CLASS_RENDER] = DRM_XE_ENGINE_CLASS_RENDER,
+ [XE_ENGINE_CLASS_COPY] = DRM_XE_ENGINE_CLASS_COPY,
+ [XE_ENGINE_CLASS_VIDEO_DECODE] = DRM_XE_ENGINE_CLASS_VIDEO_DECODE,
+ [XE_ENGINE_CLASS_VIDEO_ENHANCE] = DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE,
+ [XE_ENGINE_CLASS_COMPUTE] = DRM_XE_ENGINE_CLASS_COMPUTE,
+};
+
+static int send_exec_queue_event(struct xe_eudebug *d, u32 flags,
+ u64 vm_handle, u64 exec_queue_handle,
+ enum xe_engine_class class,
+ u32 width, u64 *lrc_handles, u64 seqno)
+{
+ struct drm_xe_eudebug_event *event;
+ struct drm_xe_eudebug_event_exec_queue *e;
+ const u32 sz = struct_size(e, lrc_handle, width);
+ const u32 xe_engine_class = xe_to_user_engine_class[class];
+
+ if (!xe_engine_supports_eudebug(class))
+ return -EINVAL;
+
+ event = xe_eudebug_create_event(d, DRM_XE_EUDEBUG_EVENT_EXEC_QUEUE,
+ seqno, flags, sz);
+ if (!event)
+ return -ENOMEM;
+
+ e = cast_event(e, event);
+
+ e->vm_handle = vm_handle;
+ e->exec_queue_handle = exec_queue_handle;
+ e->engine_class = xe_engine_class;
+ e->width = width;
+
+ memcpy(e->lrc_handle, lrc_handles, width * sizeof(u64));
+
+ return xe_eudebug_queue_event(d, event);
+}
+
+static int exec_queue_create_event(struct xe_eudebug *d,
+ struct xe_file *xef, struct xe_exec_queue *q)
+{
+ int h_vm, h_queue;
+ u64 h_lrc[XE_HW_ENGINE_MAX_INSTANCE], seqno;
+ int i;
+ int ret;
+
+ if (!xe_exec_queue_is_lr(q))
+ return 0;
+
+ h_vm = find_handle(d, XE_EUDEBUG_RES_TYPE_VM, q->vm);
+ if (h_vm < 0)
+ return h_vm;
+
+ if (XE_WARN_ON(q->width >= XE_HW_ENGINE_MAX_INSTANCE))
+ return -EINVAL;
+
+ for (i = 0; i < q->width; i++) {
+ int h, ret;
+
+ ret = _xe_eudebug_add_handle(d,
+ XE_EUDEBUG_RES_TYPE_LRC,
+ q->lrc[i],
+ NULL,
+ &h);
+
+ if (ret < 0 && ret != -EEXIST)
+ return ret;
+
+ XE_WARN_ON(!h);
+
+ h_lrc[i] = h;
+ }
+
+ h_queue = xe_eudebug_add_handle(d, XE_EUDEBUG_RES_TYPE_EXEC_QUEUE, q, &seqno);
+ if (h_queue <= 0)
+ return h_queue;
+
+ /* No need to cleanup for added handles on error as if we fail
+ * we disconnect
+ */
+
+ ret = send_exec_queue_event(d, DRM_XE_EUDEBUG_EVENT_CREATE,
+ h_vm, h_queue, q->class,
+ q->width, h_lrc, seqno);
+
+ if (ret)
+ eu_dbg(d, "send_exec_queue_event create error %d", ret);
+
+ return ret;
+}
+
+static int exec_queue_destroy_event(struct xe_eudebug *d,
+ struct xe_file *xef,
+ struct xe_exec_queue *q)
+{
+ int h_vm, h_queue;
+ u64 h_lrc[XE_HW_ENGINE_MAX_INSTANCE], seqno;
+ int i;
+ int ret, err = 0;
+
+ if (!xe_exec_queue_is_lr(q))
+ return 0;
+
+ h_vm = find_handle(d, XE_EUDEBUG_RES_TYPE_VM, q->vm);
+ if (h_vm < 0)
+ return h_vm;
+
+ if (XE_WARN_ON(q->width >= XE_HW_ENGINE_MAX_INSTANCE))
+ return -EINVAL;
+
+ for (i = 0; i < q->width; i++) {
+ ret = _xe_eudebug_remove_handle(d,
+ XE_EUDEBUG_RES_TYPE_LRC,
+ q->lrc[i],
+ NULL);
+ if (ret < 0) {
+ XE_WARN_ON(ret != -ENOENT);
+ if (!err)
+ err = ret;
+ h_lrc[i] = 0;
+ continue;
+ }
+
+ XE_WARN_ON(!ret);
+ h_lrc[i] = ret;
+ }
+
+ if (err)
+ return err;
+
+ h_queue = xe_eudebug_remove_handle(d,
+ XE_EUDEBUG_RES_TYPE_EXEC_QUEUE,
+ q,
+ &seqno);
+ if (h_queue <= 0)
+ return h_queue;
+
+ ret = send_exec_queue_event(d, DRM_XE_EUDEBUG_EVENT_DESTROY,
+ h_vm, h_queue, q->class,
+ q->width, h_lrc, seqno);
+
+ if (ret)
+ eu_dbg(d, "send_exec_queue_event destroy error %d\n", ret);
+
+ return ret;
+}
+
+void xe_eudebug_exec_queue_create(struct xe_file *xef, struct xe_exec_queue *q)
+{
+ struct xe_eudebug *d;
+
+ if (!xe_engine_supports_eudebug(q->class))
+ return;
+
+ d = xe_eudebug_get(xef);
+ if (!d)
+ return;
+
+ xe_eudebug_event_put(d, exec_queue_create_event(d, xef, q));
+}
+
+void xe_eudebug_exec_queue_destroy(struct xe_file *xef, struct xe_exec_queue *q)
+{
+ struct xe_eudebug *d;
+
+ if (!xe_engine_supports_eudebug(q->class))
+ return;
+
+ d = xe_eudebug_get(xef);
+ if (!d)
+ return;
+
+ xe_eudebug_event_put(d, exec_queue_destroy_event(d, xef, q));
+}
+
static struct xe_file *xe_eudebug_target_get(struct xe_eudebug *d)
{
struct xe_file *xef = NULL;
@@ -740,9 +939,10 @@ static struct xe_file *xe_eudebug_target_get(struct xe_eudebug *d)
static void discover_client(struct xe_eudebug *d)
{
struct xe_file *xef;
+ struct xe_exec_queue *q;
struct xe_vm *vm;
unsigned long i;
- unsigned int vm_count = 0;
+ unsigned int vm_count = 0, eq_count = 0;
int err = 0;
xef = xe_eudebug_target_get(d);
@@ -760,14 +960,24 @@ static void discover_client(struct xe_eudebug *d)
vm_count++;
}
+ xa_for_each(&xef->exec_queue.xa, i, q) {
+ if (!xe_engine_supports_eudebug(q->class))
+ continue;
+
+ err = exec_queue_create_event(d, xef, q);
+ if (err)
+ break;
+ }
+
complete_all(&d->discovery);
eu_dbg(d, "Discovery end for %lld: %d", d->session, err);
up_write(&xef->eudebug.ioctl_lock);
- if (vm_count)
- eu_dbg(d, "Discovery found %u vms", vm_count);
+ if (vm_count || eq_count)
+ eu_dbg(d, "Discovery found %u vms, %u exec_queues",
+ vm_count, eq_count);
xe_file_put(xef);
}
diff --git a/drivers/gpu/drm/xe/xe_eudebug.h b/drivers/gpu/drm/xe/xe_eudebug.h
index 22fbb2ff24da..10480a226fac 100644
--- a/drivers/gpu/drm/xe/xe_eudebug.h
+++ b/drivers/gpu/drm/xe/xe_eudebug.h
@@ -13,6 +13,7 @@ struct drm_file;
struct xe_device;
struct xe_file;
struct xe_vm;
+struct xe_exec_queue;
#if IS_ENABLED(CONFIG_DRM_XE_EUDEBUG)
@@ -46,6 +47,9 @@ void xe_eudebug_vm_create(struct xe_file *xef, struct xe_vm *vm);
void xe_eudebug_vm_destroy(struct xe_file *xef, struct xe_vm *vm);
int xe_eudebug_enable(struct xe_device *xe, bool enable);
+void xe_eudebug_exec_queue_create(struct xe_file *xef, struct xe_exec_queue *q);
+void xe_eudebug_exec_queue_destroy(struct xe_file *xef, struct xe_exec_queue *q);
+
#else
static inline int xe_eudebug_connect_ioctl(struct drm_device *dev,
@@ -60,6 +64,9 @@ static inline void xe_eudebug_file_close(struct xe_file *xef) { }
static inline void xe_eudebug_vm_create(struct xe_file *xef, struct xe_vm *vm) { }
static inline void xe_eudebug_vm_destroy(struct xe_file *xef, struct xe_vm *vm) { }
+static inline void xe_eudebug_exec_queue_create(struct xe_file *xef, struct xe_exec_queue *q) { }
+static inline void xe_eudebug_exec_queue_destroy(struct xe_file *xef, struct xe_exec_queue *q) { }
+
#endif /* CONFIG_DRM_XE_EUDEBUG */
#endif /* _XE_EUDEBUG_H_ */
diff --git a/drivers/gpu/drm/xe/xe_eudebug_types.h b/drivers/gpu/drm/xe/xe_eudebug_types.h
index d7625e55d711..9c111c483778 100644
--- a/drivers/gpu/drm/xe/xe_eudebug_types.h
+++ b/drivers/gpu/drm/xe/xe_eudebug_types.h
@@ -33,7 +33,7 @@ enum xe_eudebug_state {
};
#define CONFIG_DRM_XE_DEBUGGER_EVENT_QUEUE_SIZE 64
-#define XE_EUDEBUG_MAX_EVENT_TYPE DRM_XE_EUDEBUG_EVENT_VM
+#define XE_EUDEBUG_MAX_EVENT_TYPE DRM_XE_EUDEBUG_EVENT_EXEC_QUEUE
/**
* struct xe_eudebug_handle - eudebug resource handle
@@ -61,7 +61,9 @@ struct xe_eudebug_resource {
};
#define XE_EUDEBUG_RES_TYPE_VM 0
-#define XE_EUDEBUG_RES_TYPE_COUNT (XE_EUDEBUG_RES_TYPE_VM + 1)
+#define XE_EUDEBUG_RES_TYPE_EXEC_QUEUE 1
+#define XE_EUDEBUG_RES_TYPE_LRC 2
+#define XE_EUDEBUG_RES_TYPE_COUNT (XE_EUDEBUG_RES_TYPE_LRC + 1)
/**
* struct xe_eudebug - Top level struct for eudebug: the connection
@@ -126,3 +128,4 @@ struct xe_eudebug {
};
#endif /* _XE_EUDEBUG_TYPES_H_ */
+
diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c b/drivers/gpu/drm/xe/xe_exec_queue.c
index 071b8c41df43..2e01a4e67578 100644
--- a/drivers/gpu/drm/xe/xe_exec_queue.c
+++ b/drivers/gpu/drm/xe/xe_exec_queue.c
@@ -29,6 +29,7 @@
#include "xe_trace.h"
#include "xe_vm.h"
#include "xe_pxp.h"
+#include "xe_eudebug.h"
/**
* DOC: Execution Queue
@@ -1420,6 +1421,8 @@ int xe_exec_queue_create_ioctl(struct drm_device *dev, void *data,
args->exec_queue_id = id;
+ xe_eudebug_exec_queue_create(xef, q);
+
return 0;
del_hw_engine_group:
@@ -1617,6 +1620,8 @@ int xe_exec_queue_destroy_ioctl(struct drm_device *dev, void *data,
if (q->vm && q->hwe->hw_engine_group)
xe_hw_engine_group_del_exec_queue(q->hwe->hw_engine_group, q);
+ xe_eudebug_exec_queue_destroy(xef, q);
+
xe_exec_queue_kill(q);
trace_xe_exec_queue_close(q);
diff --git a/drivers/gpu/drm/xe/xe_hw_engine.h b/drivers/gpu/drm/xe/xe_hw_engine.h
index ee9218773b51..61a9e4622084 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.h
+++ b/drivers/gpu/drm/xe/xe_hw_engine.h
@@ -78,4 +78,18 @@ enum xe_force_wake_domains xe_hw_engine_to_fw_domain(struct xe_hw_engine *hwe);
u32 xe_hw_engine_mmio_read32(struct xe_hw_engine *hwe, struct xe_reg reg);
+static inline bool xe_engine_supports_eudebug(const enum xe_engine_class ec)
+{
+ if (ec == XE_ENGINE_CLASS_COMPUTE ||
+ ec == XE_ENGINE_CLASS_RENDER)
+ return true;
+
+ return false;
+}
+
+static inline bool xe_hw_engine_has_eudebug(const struct xe_hw_engine *hwe)
+{
+ return xe_engine_supports_eudebug(hwe->class);
+}
+
#endif
diff --git a/include/uapi/drm/xe_drm_eudebug.h b/include/uapi/drm/xe_drm_eudebug.h
index cdb4e4af4879..c9f21283ffdf 100644
--- a/include/uapi/drm/xe_drm_eudebug.h
+++ b/include/uapi/drm/xe_drm_eudebug.h
@@ -45,6 +45,7 @@ struct drm_xe_eudebug_event {
#define DRM_XE_EUDEBUG_EVENT_NONE 0
#define DRM_XE_EUDEBUG_EVENT_READ 1
#define DRM_XE_EUDEBUG_EVENT_VM 2
+#define DRM_XE_EUDEBUG_EVENT_EXEC_QUEUE 3
/** @flags: Flags */
__u16 flags;
@@ -73,6 +74,31 @@ struct drm_xe_eudebug_event_vm {
__u64 vm_handle;
};
+/**
+ * struct drm_xe_eudebug_event_exec_queue - Exec Queue resource event
+ *
+ * Resource creation/destruction event for an Exec Queue
+ */
+struct drm_xe_eudebug_event_exec_queue {
+ /** @base: base event */
+ struct drm_xe_eudebug_event base;
+
+ /** @vm_handle: the vm handle this exec queue belongs to */
+ __u64 vm_handle;
+
+ /** @exec_queue_handle: unique handle for this exec queue */
+ __u64 exec_queue_handle;
+
+ /** @engine_class: engine class for the exec queue */
+ __u32 engine_class;
+
+ /** @width: width of exec queue, how many lrcs (handles) it has */
+ __u32 width;
+
+ /** @lrc_handle: array of lrc handles */
+ __u64 lrc_handle[];
+};
+
#if defined(__cplusplus)
}
#endif
--
2.43.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 06/24] drm/xe: Add EUDEBUG_ENABLE exec queue property
2026-04-30 10:50 [PATCH 00/24] Intel Xe GPU Debug Support (eudebug) v8 Mika Kuoppala
` (4 preceding siblings ...)
2026-04-30 10:51 ` [PATCH 05/24] drm/xe/eudebug: Introduce exec_queue events Mika Kuoppala
@ 2026-04-30 10:51 ` Mika Kuoppala
2026-04-30 10:51 ` [PATCH 07/24] drm/xe/eudebug: Mark guc contexts as debuggable Mika Kuoppala
` (21 subsequent siblings)
27 siblings, 0 replies; 32+ messages in thread
From: Mika Kuoppala @ 2026-04-30 10:51 UTC (permalink / raw)
To: intel-xe
Cc: simona.vetter, matthew.brost, christian.koenig, thomas.hellstrom,
joonas.lahtinen, gustavo.sousa, jan.maslak,
dominik.karol.piatkowski, rodrigo.vivi, andrzej.hajda,
matthew.auld, maciej.patelczyk, gwan-gyeong.mun,
Dominik Grzegorzek, Mika Kuoppala
From: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
This patch introduces an immutable eudebug property for exec_queues,
using a flags value to enable eudebug-specific features. For now, the
engine LRC uses this flag to enable the runalone hardware feature.
Runalone ensures that only one hardware engine in a group
[rcs0, ccs0-3] is active on a tile.
v2: - check CONFIG_DRM_XE_EUDEBUG and LR mode (Matthew)
- disable preempt (Dominik)
- lrc_create remove from engine init
Cc: Matthew Brost <matthew.brost@intel.com>
Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/xe/xe_eudebug.c | 4 +--
drivers/gpu/drm/xe/xe_exec_queue.c | 46 +++++++++++++++++++++++-
drivers/gpu/drm/xe/xe_exec_queue.h | 2 ++
drivers/gpu/drm/xe/xe_exec_queue_types.h | 7 ++++
drivers/gpu/drm/xe/xe_lrc.c | 10 ++++++
include/uapi/drm/xe_drm.h | 2 ++
6 files changed, 68 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_eudebug.c b/drivers/gpu/drm/xe/xe_eudebug.c
index 64ac465725c5..7c553881a617 100644
--- a/drivers/gpu/drm/xe/xe_eudebug.c
+++ b/drivers/gpu/drm/xe/xe_eudebug.c
@@ -795,7 +795,7 @@ static int exec_queue_create_event(struct xe_eudebug *d,
int i;
int ret;
- if (!xe_exec_queue_is_lr(q))
+ if (!xe_exec_queue_is_debuggable(q))
return 0;
h_vm = find_handle(d, XE_EUDEBUG_RES_TYPE_VM, q->vm);
@@ -849,7 +849,7 @@ static int exec_queue_destroy_event(struct xe_eudebug *d,
int i;
int ret, err = 0;
- if (!xe_exec_queue_is_lr(q))
+ if (!xe_exec_queue_is_debuggable(q))
return 0;
h_vm = find_handle(d, XE_EUDEBUG_RES_TYPE_VM, q->vm);
diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c b/drivers/gpu/drm/xe/xe_exec_queue.c
index 2e01a4e67578..d2b6203aef11 100644
--- a/drivers/gpu/drm/xe/xe_exec_queue.c
+++ b/drivers/gpu/drm/xe/xe_exec_queue.c
@@ -357,6 +357,9 @@ static int __xe_exec_queue_init(struct xe_exec_queue *q, u32 exec_queue_flags)
if (q->flags & EXEC_QUEUE_FLAG_DISABLE_STATE_CACHE_PERF_FIX)
flags |= XE_LRC_DISABLE_STATE_CACHE_PERF_FIX;
+ if (q->eudebug_flags & EXEC_QUEUE_EUDEBUG_FLAG_ENABLE)
+ flags |= XE_LRC_CREATE_RUNALONE;
+
err = q->ops->init(q);
if (err)
return err;
@@ -993,6 +996,45 @@ static int exec_queue_set_state_cache_perf_fix(struct xe_device *xe, struct xe_e
return 0;
}
+static int exec_queue_set_eudebug(struct xe_device *xe, struct xe_exec_queue *q,
+ u64 value)
+{
+ const u64 known_flags = DRM_XE_EXEC_QUEUE_EUDEBUG_FLAG_ENABLE;
+
+ if (XE_IOCTL_DBG(xe, (q->class != XE_ENGINE_CLASS_RENDER &&
+ q->class != XE_ENGINE_CLASS_COMPUTE)))
+ return -EINVAL;
+
+ if (XE_IOCTL_DBG(xe, (value & ~known_flags)))
+ return -EINVAL;
+
+ if (XE_IOCTL_DBG(xe, !IS_ENABLED(CONFIG_DRM_XE_EUDEBUG)))
+ return -EOPNOTSUPP;
+
+ if (XE_IOCTL_DBG(xe, !xe_exec_queue_is_lr(q)))
+ return -EINVAL;
+ /*
+ * We want to explicitly set the global feature if
+ * property is set.
+ */
+ if (XE_IOCTL_DBG(xe,
+ !(value & DRM_XE_EXEC_QUEUE_EUDEBUG_FLAG_ENABLE)))
+ return -EINVAL;
+
+ if (XE_IOCTL_DBG(xe, !xe_eudebug_is_enabled(xe)))
+ return -EPERM;
+
+ q->eudebug_flags = EXEC_QUEUE_EUDEBUG_FLAG_ENABLE;
+ q->sched_props.preempt_timeout_us = 0;
+
+ return 0;
+}
+
+int xe_exec_queue_is_debuggable(struct xe_exec_queue *q)
+{
+ return q->eudebug_flags & EXEC_QUEUE_EUDEBUG_FLAG_ENABLE;
+}
+
typedef int (*xe_exec_queue_set_property_fn)(struct xe_device *xe,
struct xe_exec_queue *q,
u64 value);
@@ -1007,6 +1049,7 @@ static const xe_exec_queue_set_property_fn exec_queue_set_property_funcs[] = {
exec_queue_set_multi_queue_priority,
[DRM_XE_EXEC_QUEUE_SET_DISABLE_STATE_CACHE_PERF_FIX] =
exec_queue_set_state_cache_perf_fix,
+ [DRM_XE_EXEC_QUEUE_SET_PROPERTY_EUDEBUG] = exec_queue_set_eudebug,
};
/**
@@ -1103,7 +1146,8 @@ static int exec_queue_user_ext_set_property(struct xe_device *xe,
ext.property != DRM_XE_EXEC_QUEUE_SET_HANG_REPLAY_STATE &&
ext.property != DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP &&
ext.property != DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY &&
- ext.property != DRM_XE_EXEC_QUEUE_SET_DISABLE_STATE_CACHE_PERF_FIX))
+ ext.property != DRM_XE_EXEC_QUEUE_SET_DISABLE_STATE_CACHE_PERF_FIX &&
+ ext.property != DRM_XE_EXEC_QUEUE_SET_PROPERTY_EUDEBUG))
return -EINVAL;
idx = array_index_nospec(ext.property, ARRAY_SIZE(exec_queue_set_property_funcs));
diff --git a/drivers/gpu/drm/xe/xe_exec_queue.h b/drivers/gpu/drm/xe/xe_exec_queue.h
index a82d99bd77bc..f7babd1e2940 100644
--- a/drivers/gpu/drm/xe/xe_exec_queue.h
+++ b/drivers/gpu/drm/xe/xe_exec_queue.h
@@ -179,4 +179,6 @@ static inline bool xe_exec_queue_idle_skip_suspend(struct xe_exec_queue *q)
return !xe_exec_queue_is_parallel(q) && xe_exec_queue_is_idle(q);
}
+int xe_exec_queue_is_debuggable(struct xe_exec_queue *q);
+
#endif
diff --git a/drivers/gpu/drm/xe/xe_exec_queue_types.h b/drivers/gpu/drm/xe/xe_exec_queue_types.h
index 2f5ccf294675..10be00a3a7af 100644
--- a/drivers/gpu/drm/xe/xe_exec_queue_types.h
+++ b/drivers/gpu/drm/xe/xe_exec_queue_types.h
@@ -143,6 +143,13 @@ struct xe_exec_queue {
*/
unsigned long flags;
+ /**
+ * @eudebug_flags: immutable eudebug flags for this exec queue.
+ * Set up with DRM_XE_EXEC_QUEUE_SET_PROPERTY_EUDEBUG.
+ */
+#define EXEC_QUEUE_EUDEBUG_FLAG_ENABLE BIT(0)
+ unsigned long eudebug_flags;
+
union {
/** @multi_gt_list: list head for VM bind engines if multi-GT */
struct list_head multi_gt_list;
diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
index 9db914584347..8675897ff071 100644
--- a/drivers/gpu/drm/xe/xe_lrc.c
+++ b/drivers/gpu/drm/xe/xe_lrc.c
@@ -1636,6 +1636,16 @@ static int xe_lrc_init(struct xe_lrc *lrc, struct xe_hw_engine *hwe, struct xe_v
if (vm && vm->xef)
xe_drm_client_add_bo(vm->xef->client, lrc->bo);
+ if (init_flags & XE_LRC_CREATE_RUNALONE) {
+ u32 ctx_control = xe_lrc_read_ctx_reg(lrc, CTX_CONTEXT_CONTROL);
+
+ drm_dbg(&xe->drm, "read CTX_CONTEXT_CONTROL: 0x%x\n", ctx_control);
+ ctx_control |= REG_MASKED_FIELD_ENABLE(CTX_CTRL_RUN_ALONE);
+ drm_dbg(&xe->drm, "written CTX_CONTEXT_CONTROL: 0x%x\n", ctx_control);
+
+ xe_lrc_write_ctx_reg(lrc, CTX_CONTEXT_CONTROL, ctx_control);
+ }
+
return 0;
err_lrc_finish:
diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
index acacd9e7e1e0..ed53a56ad71b 100644
--- a/include/uapi/drm/xe_drm.h
+++ b/include/uapi/drm/xe_drm.h
@@ -1442,6 +1442,8 @@ struct drm_xe_exec_queue_create {
#define DRM_XE_MULTI_GROUP_CREATE (1ull << 63)
#define DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY 5
#define DRM_XE_EXEC_QUEUE_SET_DISABLE_STATE_CACHE_PERF_FIX 6
+#define DRM_XE_EXEC_QUEUE_SET_PROPERTY_EUDEBUG 7
+#define DRM_XE_EXEC_QUEUE_EUDEBUG_FLAG_ENABLE (1 << 0)
/** @extensions: Pointer to the first extension struct, if any */
__u64 extensions;
--
2.43.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 07/24] drm/xe/eudebug: Mark guc contexts as debuggable
2026-04-30 10:50 [PATCH 00/24] Intel Xe GPU Debug Support (eudebug) v8 Mika Kuoppala
` (5 preceding siblings ...)
2026-04-30 10:51 ` [PATCH 06/24] drm/xe: Add EUDEBUG_ENABLE exec queue property Mika Kuoppala
@ 2026-04-30 10:51 ` Mika Kuoppala
2026-04-30 10:51 ` [PATCH 08/24] drm/xe: Introduce ADD_DEBUG_DATA and REMOVE_DEBUG_DATA vm bind ops Mika Kuoppala
` (20 subsequent siblings)
27 siblings, 0 replies; 32+ messages in thread
From: Mika Kuoppala @ 2026-04-30 10:51 UTC (permalink / raw)
To: intel-xe
Cc: simona.vetter, matthew.brost, christian.koenig, thomas.hellstrom,
joonas.lahtinen, gustavo.sousa, jan.maslak,
dominik.karol.piatkowski, rodrigo.vivi, andrzej.hajda,
matthew.auld, maciej.patelczyk, gwan-gyeong.mun, Mika Kuoppala,
Lucas De Marchi, Daniele Ceraolo Spurio, Jan Sokolowski,
Dominik Grzegorzek
We need to inform to guc which contexts are debuggable
as their handling is different from ordinary contexts.
v2: void return, use xe_gt_dbg, no need for lrc (Matt)
v3: add the workaround enabling (Daniele)
v4: version needed to 70.49.4
v5: bail out early before registering eq (Daniele)
v6: export the guc action for future (Mika)
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Jan Sokolowski <jan.sokolowski@intel.com>
Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Signed-off-by: Maciej Patelczyk <maciej.patelczyk@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/xe/abi/guc_actions_abi.h | 5 ++++
drivers/gpu/drm/xe/abi/guc_klvs_abi.h | 1 +
drivers/gpu/drm/xe/xe_exec_queue.c | 5 ++++
drivers/gpu/drm/xe/xe_guc.c | 17 ++++++++++++
drivers/gpu/drm/xe/xe_guc.h | 3 +++
drivers/gpu/drm/xe/xe_guc_ads.c | 17 ++++++++++++
drivers/gpu/drm/xe/xe_guc_submit.c | 34 ++++++++++++++++++++++++
drivers/gpu/drm/xe/xe_guc_submit.h | 1 +
drivers/gpu/drm/xe/xe_wa_oob.rules | 3 ++-
9 files changed, 85 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xe/abi/guc_actions_abi.h b/drivers/gpu/drm/xe/abi/guc_actions_abi.h
index 83a6e7794982..918247d1f526 100644
--- a/drivers/gpu/drm/xe/abi/guc_actions_abi.h
+++ b/drivers/gpu/drm/xe/abi/guc_actions_abi.h
@@ -161,6 +161,7 @@ enum xe_guc_action {
XE_GUC_ACTION_NOTIFY_FLUSH_LOG_BUFFER_TO_FILE = 0x8003,
XE_GUC_ACTION_NOTIFY_CRASH_DUMP_POSTED = 0x8004,
XE_GUC_ACTION_NOTIFY_EXCEPTION = 0x8005,
+ XE_GUC_ACTION_EU_KERNEL_DEBUG = 0x8006,
XE_GUC_ACTION_TEST_G2G_SEND = 0xF001,
XE_GUC_ACTION_TEST_G2G_RECV = 0xF002,
XE_GUC_ACTION_LIMIT
@@ -284,4 +285,8 @@ enum xe_guc_g2g_type {
/* invalid type for XE_GUC_ACTION_NOTIFY_MEMORY_CAT_ERROR */
#define XE_GUC_CAT_ERR_TYPE_INVALID 0xdeadbeef
+enum xe_guc_eu_kernel_debug_request_type {
+ XE_GUC_EU_KERNEL_DEBUG_ENABLE = 0x3,
+};
+
#endif
diff --git a/drivers/gpu/drm/xe/abi/guc_klvs_abi.h b/drivers/gpu/drm/xe/abi/guc_klvs_abi.h
index 644f5a4226d7..4cca653e37a1 100644
--- a/drivers/gpu/drm/xe/abi/guc_klvs_abi.h
+++ b/drivers/gpu/drm/xe/abi/guc_klvs_abi.h
@@ -504,6 +504,7 @@ enum xe_guc_klv_ids {
GUC_WA_KLV_RESET_BB_STACK_PTR_ON_VF_SWITCH = 0x900b,
GUC_WA_KLV_RESTORE_UNSAVED_MEDIA_CONTROL_REG = 0x900c,
GUC_WA_KLV_CLR_CS_INDIRECT_RING_STATE_IF_IDLE_AT_CTX_REG = 0x900e,
+ GUC_WA_KLV_RESET_DEP_ENGINES_ON_DEBUG_CTX_SWITCH = 0x900d,
};
#endif
diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c b/drivers/gpu/drm/xe/xe_exec_queue.c
index d2b6203aef11..d0164fb795ad 100644
--- a/drivers/gpu/drm/xe/xe_exec_queue.c
+++ b/drivers/gpu/drm/xe/xe_exec_queue.c
@@ -19,6 +19,7 @@
#include "xe_gt.h"
#include "xe_gt_sriov_pf.h"
#include "xe_gt_sriov_vf.h"
+#include "xe_guc.h"
#include "xe_hw_engine_class_sysfs.h"
#include "xe_hw_engine_group.h"
#include "xe_irq.h"
@@ -1000,6 +1001,7 @@ static int exec_queue_set_eudebug(struct xe_device *xe, struct xe_exec_queue *q,
u64 value)
{
const u64 known_flags = DRM_XE_EXEC_QUEUE_EUDEBUG_FLAG_ENABLE;
+ struct xe_guc *guc = &q->gt->uc.guc;
if (XE_IOCTL_DBG(xe, (q->class != XE_ENGINE_CLASS_RENDER &&
q->class != XE_ENGINE_CLASS_COMPUTE)))
@@ -1011,6 +1013,9 @@ static int exec_queue_set_eudebug(struct xe_device *xe, struct xe_exec_queue *q,
if (XE_IOCTL_DBG(xe, !IS_ENABLED(CONFIG_DRM_XE_EUDEBUG)))
return -EOPNOTSUPP;
+ if (XE_IOCTL_DBG(xe, !xe_guc_has_debug_contexts(guc)))
+ return -EOPNOTSUPP;
+
if (XE_IOCTL_DBG(xe, !xe_exec_queue_is_lr(q)))
return -EINVAL;
/*
diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index e468b638271b..8fae93d5755e 100644
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -1846,6 +1846,23 @@ bool xe_guc_using_main_gamctrl_queues(struct xe_guc *guc)
return GT_VER(gt) >= 35;
}
+bool xe_guc_has_debug_contexts(struct xe_guc *guc)
+{
+ const struct xe_uc_fw_version required = XE_UC_FW_VERSION_DEBUG_CONTEXTS;
+ struct xe_uc_fw_version *version = &guc->fw.versions.found[XE_UC_FW_VER_RELEASE];
+ struct xe_gt *gt = guc_to_gt(guc);
+
+ if (MAKE_GUC_VER_STRUCT(*version) < MAKE_GUC_VER_STRUCT(required)) {
+ xe_gt_info(gt,
+ "debug context unsupported in GuC interface v%u.%u.%u, need v%u.%u.%u or higher\n",
+ version->major, version->minor, version->patch, required.major,
+ required.minor, required.patch);
+ return false;
+ }
+
+ return true;
+}
+
#if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)
#include "tests/xe_guc_g2g_test.c"
#endif
diff --git a/drivers/gpu/drm/xe/xe_guc.h b/drivers/gpu/drm/xe/xe_guc.h
index 02514914f404..9c6b3845d0bc 100644
--- a/drivers/gpu/drm/xe/xe_guc.h
+++ b/drivers/gpu/drm/xe/xe_guc.h
@@ -29,6 +29,8 @@
#define GUC_FIRMWARE_VER_AT_LEAST(guc, ver...) \
xe_guc_fw_version_at_least((guc), MAKE_GUC_VER_ARGS(ver))
+#define XE_UC_FW_VERSION_DEBUG_CONTEXTS { .major = 70, .minor = 49, .patch = 4 }
+
struct drm_printer;
void xe_guc_comm_init_early(struct xe_guc *guc);
@@ -62,6 +64,7 @@ void xe_guc_stop(struct xe_guc *guc);
int xe_guc_start(struct xe_guc *guc);
void xe_guc_declare_wedged(struct xe_guc *guc);
bool xe_guc_using_main_gamctrl_queues(struct xe_guc *guc);
+bool xe_guc_has_debug_contexts(struct xe_guc *guc);
#if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)
int xe_guc_g2g_test_notification(struct xe_guc *guc, u32 *payload, u32 len);
diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
index ce651da6f318..9574d0567701 100644
--- a/drivers/gpu/drm/xe/xe_guc_ads.c
+++ b/drivers/gpu/drm/xe/xe_guc_ads.c
@@ -364,6 +364,23 @@ static void guc_waklv_init(struct xe_guc_ads *ads)
guc_waklv_enable(ads, NULL, 0, &offset, &remain,
GUC_WA_KLV_CLR_CS_INDIRECT_RING_STATE_IF_IDLE_AT_CTX_REG);
+#if IS_ENABLED(CONFIG_DRM_XE_EUDEBUG)
+ if (XE_GT_WA(gt, 14022766366)) {
+ if (xe_guc_has_debug_contexts(>->uc.guc)) {
+ guc_waklv_enable(ads, NULL, 0, &offset, &remain,
+ GUC_WA_KLV_RESET_DEP_ENGINES_ON_DEBUG_CTX_SWITCH);
+ } else {
+ const struct xe_uc_fw_version required =
+ XE_UC_FW_VERSION_DEBUG_CONTEXTS;
+
+ xe_gt_info(gt, "eudebug needs GuC version %u.%u.%u or greater\n",
+ required.major,
+ required.minor,
+ required.patch);
+ }
+ }
+#endif
+
size = guc_ads_waklv_size(ads) - remain;
if (!size)
return;
diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c
index b1222b42174c..69973eb6e978 100644
--- a/drivers/gpu/drm/xe/xe_guc_submit.c
+++ b/drivers/gpu/drm/xe/xe_guc_submit.c
@@ -979,6 +979,37 @@ static void __register_exec_queue(struct xe_guc *guc,
xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action), 0, 0);
}
+int xe_guc_action_eu_kernel_debug(struct xe_guc *guc, u32 id, u32 cmd)
+{
+ const u32 action[] = {
+ XE_GUC_ACTION_EU_KERNEL_DEBUG,
+ id,
+ cmd,
+ 0, /* reserved */
+ };
+
+ return xe_guc_ct_send(&guc->ct, action,
+ ARRAY_SIZE(action), 0, 0);
+}
+
+static void set_eu_kernel_debug(struct xe_exec_queue *q)
+{
+ struct xe_guc *guc = exec_queue_to_guc(q);
+ struct xe_gt *gt = guc_to_gt(guc);
+ int ret;
+
+ ret = xe_guc_action_eu_kernel_debug(guc, q->guc->id,
+ XE_GUC_EU_KERNEL_DEBUG_ENABLE);
+
+ if (ret)
+ xe_gt_warn(gt,
+ "GuC ctx=%u debug enabling failed with %d",
+ q->guc->id, ret);
+ else
+ xe_gt_dbg(gt,
+ "GuC ctx=%u enabled for debug", q->guc->id);
+}
+
static void register_exec_queue(struct xe_exec_queue *q, int ctx_type)
{
struct xe_guc *guc = exec_queue_to_guc(q);
@@ -1039,6 +1070,9 @@ static void register_exec_queue(struct xe_exec_queue *q, int ctx_type)
if (xe_exec_queue_is_multi_queue_secondary(q))
xe_guc_exec_queue_group_add(guc, q);
+
+ if (xe_exec_queue_is_debuggable(q))
+ set_eu_kernel_debug(q);
}
static u32 wq_space_until_wrap(struct xe_exec_queue *q)
diff --git a/drivers/gpu/drm/xe/xe_guc_submit.h b/drivers/gpu/drm/xe/xe_guc_submit.h
index b3839a90c142..d296e30f9e39 100644
--- a/drivers/gpu/drm/xe/xe_guc_submit.h
+++ b/drivers/gpu/drm/xe/xe_guc_submit.h
@@ -55,5 +55,6 @@ void xe_guc_register_vf_exec_queue(struct xe_exec_queue *q, int ctx_type);
bool xe_guc_has_registered_mlrc_queues(struct xe_guc *guc);
int xe_guc_contexts_hwsp_rebase(struct xe_guc *guc, void *scratch);
+int xe_guc_action_eu_kernel_debug(struct xe_guc *guc, u32 id, u32 cmd);
#endif
diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
index f8a185103b80..445ba0d19051 100644
--- a/drivers/gpu/drm/xe/xe_wa_oob.rules
+++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
@@ -62,6 +62,7 @@
15015404425_disable PLATFORM(PANTHERLAKE), MEDIA_STEP(B0, FOREVER)
16026007364 MEDIA_VERSION(3000)
14020316580 MEDIA_VERSION(1301)
-
14025883347 MEDIA_VERSION_RANGE(1301, 3503)
GRAPHICS_VERSION_RANGE(2004, 3005)
+14022766366 GRAPHICS_VERSION_RANGE(2001, 2004)
+ GRAPHICS_VERSION_RANGE(3000, 3005)
--
2.43.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 08/24] drm/xe: Introduce ADD_DEBUG_DATA and REMOVE_DEBUG_DATA vm bind ops
2026-04-30 10:50 [PATCH 00/24] Intel Xe GPU Debug Support (eudebug) v8 Mika Kuoppala
` (6 preceding siblings ...)
2026-04-30 10:51 ` [PATCH 07/24] drm/xe/eudebug: Mark guc contexts as debuggable Mika Kuoppala
@ 2026-04-30 10:51 ` Mika Kuoppala
2026-04-30 10:51 ` [PATCH 09/24] drm/xe/eudebug: Introduce vm bind and vm bind debug data events Mika Kuoppala
` (19 subsequent siblings)
27 siblings, 0 replies; 32+ messages in thread
From: Mika Kuoppala @ 2026-04-30 10:51 UTC (permalink / raw)
To: intel-xe
Cc: simona.vetter, matthew.brost, christian.koenig, thomas.hellstrom,
joonas.lahtinen, gustavo.sousa, jan.maslak,
dominik.karol.piatkowski, rodrigo.vivi, andrzej.hajda,
matthew.auld, maciej.patelczyk, gwan-gyeong.mun,
Christoph Manszewski, Mika Kuoppala
From: Christoph Manszewski <christoph.manszewski@intel.com>
Make it possible to add and remove per vm debug data, which can be used
to annotate vm ranges (using pseudopaths) or to associate them with
a file which can carry arbitrary debug data (e.g. binary instruction to
code line mapping). The debug data is kept separe from the vmas. Each
address can be associated with only one debug data entry i.e. debug data
entries cannot overlap. Each entry is atomic so to remove it the
creation address and range has to be passed for removal.
For debug data manipulation only the 'op' and 'extensions' field from
'struct drm_xe_vm_bind_op' is used. All required parameters are passed
through 'struct drm_xe_vm_bind_op_ext_debug_data' and a valid instance
should be present in the extension chain pointed by the 'extensions'
field.
Debug data will be accessible through the eudebug event interface,
introduced in the following patch. An alternative way to access debug data
using debugfs, without relying on eudebug, will be proposed as a follow-up
to the eudebug series.
v2: enforce empty path on unmap (Joonas, Mika)
Signed-off-by: Christoph Manszewski <christoph.manszewski@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/xe/Makefile | 1 +
drivers/gpu/drm/xe/xe_debug_data.c | 314 +++++++++++++++++++++++
drivers/gpu/drm/xe/xe_debug_data.h | 22 ++
drivers/gpu/drm/xe/xe_debug_data_types.h | 25 ++
drivers/gpu/drm/xe/xe_vm.c | 157 +++++++++++-
drivers/gpu/drm/xe/xe_vm_types.h | 19 ++
include/uapi/drm/xe_drm.h | 64 +++++
7 files changed, 596 insertions(+), 6 deletions(-)
create mode 100644 drivers/gpu/drm/xe/xe_debug_data.c
create mode 100644 drivers/gpu/drm/xe/xe_debug_data.h
create mode 100644 drivers/gpu/drm/xe/xe_debug_data_types.h
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 7212ceb339ab..97c721cd32aa 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -35,6 +35,7 @@ $(obj)/generated/%_device_wa_oob.c $(obj)/generated/%_device_wa_oob.h: $(obj)/xe
xe-y += xe_bb.o \
xe_bo.o \
xe_bo_evict.o \
+ xe_debug_data.o \
xe_dep_scheduler.o \
xe_devcoredump.o \
xe_device.o \
diff --git a/drivers/gpu/drm/xe/xe_debug_data.c b/drivers/gpu/drm/xe/xe_debug_data.c
new file mode 100644
index 000000000000..3c39b2457d6e
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_debug_data.c
@@ -0,0 +1,314 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#include "xe_debug_data.h"
+#include "xe_debug_data_types.h"
+#include "xe_vm.h"
+
+const char *xe_debug_data_pseudo_path_to_string(u64 pseudopath)
+{
+ switch (pseudopath) {
+ case DRM_XE_VM_BIND_DEBUG_DATA_PSEUDO_MODULE_AREA:
+ return "[module_area]";
+ case DRM_XE_VM_BIND_DEBUG_DATA_PSEUDO_SBA_AREA:
+ return "[sba_area]";
+ case DRM_XE_VM_BIND_DEBUG_DATA_PSEUDO_SIP_AREA:
+ return "[sip_area]";
+ default:
+ return "[unknown]";
+ }
+}
+
+static bool
+debug_data_overlaps(const struct drm_xe_vm_bind_op_ext_debug_data *a,
+ const struct xe_debug_data *b)
+{
+ const u64 s1 = a->addr;
+ const u64 e1 = a->addr + a->range;
+ const u64 s2 = b->addr;
+ const u64 e2 = b->addr + b->range;
+
+ return (s1 < e2) && (s2 < e1);
+}
+
+static bool
+debug_data_matches(const struct drm_xe_vm_bind_op_ext_debug_data *a,
+ const struct xe_debug_data *b)
+{
+ return (a->addr == b->addr) && (a->range == b->range);
+}
+
+static bool
+debug_data_is_empty(const struct drm_xe_vm_bind_op_ext_debug_data *dd)
+{
+ int i;
+
+ if (dd->flags)
+ return false;
+
+ if (dd->offset)
+ return false;
+
+ for (i = 0; i < PATH_MAX; i++)
+ if (dd->pathname[i])
+ return false;
+
+ return true;
+}
+
+static int xe_debug_data_check_add(struct xe_vm *vm,
+ const struct drm_xe_vm_bind_op_ext_debug_data *ext)
+{
+ struct xe_device *xe = vm->xe;
+ struct xe_debug_data *i;
+
+ mutex_lock(&vm->debug_data.lock);
+ list_for_each_entry(i, &vm->debug_data.list, link) {
+ if (XE_IOCTL_DBG(xe, debug_data_overlaps(ext, i))) {
+ mutex_unlock(&vm->debug_data.lock);
+ return -EINVAL;
+ }
+ }
+ mutex_unlock(&vm->debug_data.lock);
+
+ return 0;
+}
+
+static int xe_debug_data_check_remove(struct xe_vm *vm,
+ const struct drm_xe_vm_bind_op_ext_debug_data *ext)
+{
+ struct xe_device *xe = vm->xe;
+ struct xe_debug_data *i;
+ bool found = false;
+
+ if (XE_IOCTL_DBG(xe, !debug_data_is_empty(ext)))
+ return -EINVAL;
+
+ mutex_lock(&vm->debug_data.lock);
+ list_for_each_entry(i, &vm->debug_data.list, link) {
+ found = debug_data_matches(ext, i);
+ if (found)
+ break;
+ }
+ mutex_unlock(&vm->debug_data.lock);
+
+ if (XE_IOCTL_DBG(xe, !found)) {
+ drm_dbg(&xe->drm, "Debug data to remove not found for addr 0x%llx, range 0x%llx\n",
+ ext->addr, ext->range);
+ return -ENOENT;
+ }
+
+ return 0;
+}
+
+int xe_debug_data_check_extension(struct xe_vm *vm, u32 operation, u64 extension)
+{
+ const u64 __user * const address = u64_to_user_ptr(extension);
+ struct drm_xe_vm_bind_op_ext_debug_data *ext;
+ struct xe_device *xe = vm->xe;
+ int ret;
+
+ if (XE_IOCTL_DBG(xe, operation != DRM_XE_VM_BIND_OP_ADD_DEBUG_DATA &&
+ operation != DRM_XE_VM_BIND_OP_REMOVE_DEBUG_DATA))
+ return -EINVAL;
+
+ ext = kzalloc_obj(*ext, GFP_KERNEL);
+ if (!ext)
+ return -ENOMEM;
+
+ if (copy_from_user(ext, address, sizeof(*ext))) {
+ kfree(ext);
+ return -EFAULT;
+ }
+
+ if (XE_IOCTL_DBG(xe, ext->flags & ~DRM_XE_VM_BIND_DEBUG_DATA_FLAG_PSEUDO) ||
+ XE_IOCTL_DBG(xe, ext->flags & DRM_XE_VM_BIND_DEBUG_DATA_FLAG_PSEUDO &&
+ ext->offset != 0) ||
+ XE_IOCTL_DBG(xe, ext->flags & DRM_XE_VM_BIND_DEBUG_DATA_FLAG_PSEUDO &&
+ (ext->pseudopath < DRM_XE_VM_BIND_DEBUG_DATA_PSEUDO_MODULE_AREA ||
+ ext->pseudopath > DRM_XE_VM_BIND_DEBUG_DATA_PSEUDO_SIP_AREA)) ||
+ XE_IOCTL_DBG(xe, !(ext->flags & DRM_XE_VM_BIND_DEBUG_DATA_FLAG_PSEUDO) &&
+ strnlen(ext->pathname, PATH_MAX) >= PATH_MAX)) {
+ kfree(ext);
+ return -EINVAL;
+ }
+
+ ret = operation == DRM_XE_VM_BIND_OP_ADD_DEBUG_DATA ?
+ xe_debug_data_check_add(vm, ext) :
+ xe_debug_data_check_remove(vm, ext);
+
+ kfree(ext);
+ return ret;
+}
+
+static int xe_debug_data_add(struct xe_vm *vm, struct xe_vma_op *vma_op,
+ struct drm_xe_vm_bind_op_ext_debug_data *ext)
+{
+ struct xe_debug_data *dd;
+
+ vm_dbg(&vm->xe->drm,
+ "ADD_DEBUG_DATA: addr=0x%016llx, range=0x%016llx, offset=0x%08x, flags=0x%016llx, path=%s\n",
+ ext->addr, ext->range, ext->offset, ext->flags,
+ (ext->flags & DRM_XE_VM_BIND_DEBUG_DATA_FLAG_PSEUDO) ?
+ xe_debug_data_pseudo_path_to_string(ext->pseudopath) : ext->pathname);
+
+ dd = kzalloc_obj(*dd, GFP_KERNEL);
+ if (!dd)
+ return -ENOMEM;
+
+ dd->addr = ext->addr;
+ dd->range = ext->range;
+ dd->flags = ext->flags;
+ dd->offset = ext->offset;
+
+ if (ext->flags & DRM_XE_VM_BIND_DEBUG_DATA_FLAG_PSEUDO) {
+ dd->pseudopath = ext->pseudopath;
+ } else if (strscpy(dd->pathname, ext->pathname, PATH_MAX) < 0) {
+ kfree(dd);
+ return -EINVAL;
+ }
+
+ mutex_lock(&vm->debug_data.lock);
+ list_add_tail(&dd->link, &vm->debug_data.list);
+ mutex_unlock(&vm->debug_data.lock);
+
+ memcpy(&vma_op->modify_debug_data.debug_data, dd, sizeof(*dd));
+
+ return 0;
+}
+
+static int xe_debug_data_remove(struct xe_vm *vm, struct xe_vma_op *vma_op,
+ struct drm_xe_vm_bind_op_ext_debug_data *ext)
+{
+ struct xe_debug_data *dd;
+
+ vm_dbg(&vm->xe->drm,
+ "REMOVE_DEBUG_DATA: addr=0x%016llx, range=0x%016llx, offset=0x%08x, flags=0x%016llx, path=%s\n",
+ ext->addr, ext->range, ext->offset, ext->flags,
+ (ext->flags & DRM_XE_VM_BIND_DEBUG_DATA_FLAG_PSEUDO) ?
+ xe_debug_data_pseudo_path_to_string(ext->pseudopath) : ext->pathname);
+
+ mutex_lock(&vm->debug_data.lock);
+ list_for_each_entry(dd, &vm->debug_data.list, link) {
+ if (dd->addr == ext->addr && dd->range == ext->range) {
+ list_del(&dd->link);
+ memcpy(&vma_op->modify_debug_data.debug_data, dd, sizeof(*dd));
+ kfree(dd);
+ break;
+ }
+ }
+ mutex_unlock(&vm->debug_data.lock);
+
+ return 0;
+}
+
+int xe_debug_data_process_extension(struct xe_vm *vm, struct drm_gpuva_ops *ops, u32 operation,
+ u64 extension)
+{
+ const u64 __user * const address = u64_to_user_ptr(extension);
+ struct drm_xe_vm_bind_op_ext_debug_data *ext;
+ struct xe_vma_op *vma_op;
+ struct drm_gpuva_op *op;
+ int ret;
+
+ ext = kzalloc_obj(*ext, GFP_KERNEL);
+ if (!ext)
+ return -ENOMEM;
+
+ if (copy_from_user(ext, address, sizeof(*ext))) {
+ kfree(ext);
+ return -EFAULT;
+ }
+
+ /* We expect only a single op for debug data */
+ op = drm_gpuva_first_op(ops);
+ if (op != drm_gpuva_last_op(ops))
+ drm_warn(&vm->xe->drm, "NOT POSSIBLE");
+
+ vma_op = gpuva_op_to_vma_op(op);
+
+ if (vma_op->subop == XE_VMA_SUBOP_ADD_DEBUG_DATA)
+ ret = xe_debug_data_add(vm, vma_op, ext);
+ else
+ ret = xe_debug_data_remove(vm, vma_op, ext);
+
+ kfree(ext);
+ return ret;
+}
+
+static int xe_debug_data_op_unwind_add(struct xe_vm *vm, struct xe_vma_op *vma_op)
+{
+ const struct xe_debug_data *op_data = &vma_op->modify_debug_data.debug_data;
+ struct xe_debug_data *dd;
+
+ vm_dbg(&vm->xe->drm,
+ "Reverting debug data add: addr=0x%016llx, range=0x%016llx, offset=0x%08x, flags=0x%016llx, path=%s\n",
+ op_data->addr, op_data->range, op_data->offset, op_data->flags,
+ (op_data->flags & DRM_XE_VM_BIND_DEBUG_DATA_FLAG_PSEUDO) ?
+ xe_debug_data_pseudo_path_to_string(op_data->pseudopath) : op_data->pathname);
+
+ mutex_lock(&vm->debug_data.lock);
+ list_for_each_entry(dd, &vm->debug_data.list, link) {
+ if (dd->addr == op_data->addr && dd->range == op_data->range) {
+ list_del(&dd->link);
+ kfree(dd);
+ break;
+ }
+ }
+ mutex_unlock(&vm->debug_data.lock);
+
+ return 0;
+}
+
+static int xe_debug_data_op_unwind_remove(struct xe_vm *vm, struct xe_vma_op *vma_op)
+{
+ const struct xe_debug_data *op_data = &vma_op->modify_debug_data.debug_data;
+ struct xe_debug_data *dd;
+
+ vm_dbg(&vm->xe->drm,
+ "Reverting debug data remove: addr=0x%016llx, range=0x%016llx, offset=0x%08x, flags=0x%016llx, path=%s\n",
+ op_data->addr, op_data->range, op_data->offset, op_data->flags,
+ (op_data->flags & DRM_XE_VM_BIND_DEBUG_DATA_FLAG_PSEUDO) ?
+ xe_debug_data_pseudo_path_to_string(op_data->pseudopath) : op_data->pathname);
+
+ dd = kzalloc_obj(*dd, GFP_KERNEL);
+ if (!dd)
+ return -ENOMEM;
+
+ memcpy(dd, op_data, sizeof(*dd));
+
+ mutex_lock(&vm->debug_data.lock);
+ list_add_tail(&dd->link, &vm->debug_data.list);
+ mutex_unlock(&vm->debug_data.lock);
+
+ return 0;
+}
+
+int xe_debug_data_op_unwind(struct xe_vm *vm, struct xe_vma_op *vma_op)
+{
+ switch (vma_op->subop) {
+ case XE_VMA_SUBOP_ADD_DEBUG_DATA:
+ return xe_debug_data_op_unwind_add(vm, vma_op);
+ case XE_VMA_SUBOP_REMOVE_DEBUG_DATA:
+ return xe_debug_data_op_unwind_remove(vm, vma_op);
+ default:
+ drm_err(&vm->xe->drm, "Invalid debug data subop %d\n", vma_op->subop);
+ return -EINVAL;
+ }
+}
+
+int xe_debug_data_destroy(struct xe_vm *vm)
+{
+ struct xe_debug_data *dd, *tmp;
+
+ mutex_lock(&vm->debug_data.lock);
+ list_for_each_entry_safe(dd, tmp, &vm->debug_data.list, link) {
+ list_del(&dd->link);
+ kfree(dd);
+ }
+ mutex_unlock(&vm->debug_data.lock);
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/xe/xe_debug_data.h b/drivers/gpu/drm/xe/xe_debug_data.h
new file mode 100644
index 000000000000..3436a7023920
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_debug_data.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef _XE_DEBUG_DATA_H_
+#define _XE_DEBUG_DATA_H_
+
+#include <linux/types.h>
+
+struct drm_gpuva_ops;
+struct xe_vm;
+struct xe_vma_op;
+
+const char *xe_debug_data_pseudo_path_to_string(u64 pseudopath);
+int xe_debug_data_check_extension(struct xe_vm *vm, u32 operation, u64 extension);
+int xe_debug_data_process_extension(struct xe_vm *vm, struct drm_gpuva_ops *ops, u32 operation,
+ u64 extension);
+int xe_debug_data_op_unwind(struct xe_vm *vm, struct xe_vma_op *vma_op);
+int xe_debug_data_destroy(struct xe_vm *vm);
+
+#endif /* _XE_DEBUG_DATA_H_ */
diff --git a/drivers/gpu/drm/xe/xe_debug_data_types.h b/drivers/gpu/drm/xe/xe_debug_data_types.h
new file mode 100644
index 000000000000..a8b430af2275
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_debug_data_types.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef _XE_DEBUG_DATA_TYPES_H_
+#define _XE_DEBUG_DATA_TYPES_H_
+
+#include <linux/limits.h>
+#include <linux/list.h>
+#include <linux/types.h>
+
+struct xe_debug_data {
+ struct list_head link;
+ u64 addr;
+ u64 range;
+ u64 flags;
+ u32 offset;
+ union {
+ u64 pseudopath;
+ char pathname[PATH_MAX];
+ };
+};
+
+#endif /* _XE_DEBUG_DATA_TYPES_H_ */
diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
index 456ee3bc4073..9a3980e8422a 100644
--- a/drivers/gpu/drm/xe/xe_vm.c
+++ b/drivers/gpu/drm/xe/xe_vm.c
@@ -24,6 +24,7 @@
#include "regs/xe_gtt_defs.h"
#include "xe_assert.h"
#include "xe_bo.h"
+#include "xe_debug_data.h"
#include "xe_device.h"
#include "xe_drm_client.h"
#include "xe_eudebug.h"
@@ -1649,6 +1650,9 @@ struct xe_vm *xe_vm_create(struct xe_device *xe, u32 flags, struct xe_file *xef)
for_each_tile(tile, xe, id)
xe_range_fence_tree_init(&vm->rftree[id]);
+ INIT_LIST_HEAD(&vm->debug_data.list);
+ mutex_init(&vm->debug_data.lock);
+
vm->pt_ops = &xelp_pt_ops;
/*
@@ -1952,6 +1956,8 @@ void xe_vm_close_and_put(struct xe_vm *vm)
for_each_tile(tile, xe, id)
xe_range_fence_tree_fini(&vm->rftree[id]);
+ xe_debug_data_destroy(vm);
+
xe_vm_put(vm);
}
@@ -2301,6 +2307,7 @@ static void prep_vma_destroy(struct xe_vm *vm, struct xe_vma *vma,
#if IS_ENABLED(CONFIG_DRM_XE_DEBUG_VM)
static void print_op(struct xe_device *xe, struct drm_gpuva_op *op)
{
+ struct xe_vma_op *vma_op;
struct xe_vma *vma;
switch (op->op) {
@@ -2335,6 +2342,12 @@ static void print_op(struct xe_device *xe, struct drm_gpuva_op *op)
vm_dbg(&xe->drm, "PREFETCH: addr=0x%016llx, range=0x%016llx",
(ULL)xe_vma_start(vma), (ULL)xe_vma_size(vma));
break;
+ case DRM_GPUVA_OP_DRIVER:
+ vma_op = gpuva_op_to_vma_op(op);
+ if (vma_op->subop != XE_VMA_SUBOP_ADD_DEBUG_DATA &&
+ vma_op->subop != XE_VMA_SUBOP_REMOVE_DEBUG_DATA)
+ drm_warn(&xe->drm, "Unexpected vma sub op: %d", vma_op->subop);
+ break;
default:
drm_warn(&xe->drm, "NOT POSSIBLE\n");
}
@@ -2379,12 +2392,13 @@ vm_bind_ioctl_ops_create(struct xe_vm *vm, struct xe_vma_ops *vops,
struct xe_bo *bo, u64 bo_offset_or_userptr,
u64 addr, u64 range,
u32 operation, u32 flags,
- u32 prefetch_region, u16 pat_index)
+ u32 prefetch_region, u16 pat_index, u64 extensions)
{
struct drm_gem_object *obj = bo ? &bo->ttm.base : NULL;
struct drm_gpuva_ops *ops;
struct drm_gpuva_op *__op;
struct drm_gpuvm_bo *vm_bo;
+ struct xe_vma_op *vma_op;
u64 range_start = addr;
u64 range_end = addr + range;
int err;
@@ -2438,6 +2452,24 @@ vm_bind_ioctl_ops_create(struct xe_vm *vm, struct xe_vma_ops *vops,
drm_gpuvm_bo_put(vm_bo);
xe_bo_unlock(bo);
break;
+ case DRM_XE_VM_BIND_OP_ADD_DEBUG_DATA:
+ case DRM_XE_VM_BIND_OP_REMOVE_DEBUG_DATA:
+ ops = kzalloc(sizeof(*ops), GFP_KERNEL);
+ if (!ops)
+ return ERR_PTR(-ENOMEM);
+
+ INIT_LIST_HEAD(&ops->list);
+ vma_op = kzalloc_obj(*vma_op, GFP_KERNEL);
+ if (!vma_op) {
+ kfree(ops);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ vma_op->base.op = DRM_GPUVA_OP_DRIVER;
+ vma_op->subop = operation == DRM_XE_VM_BIND_OP_ADD_DEBUG_DATA ?
+ XE_VMA_SUBOP_ADD_DEBUG_DATA : XE_VMA_SUBOP_REMOVE_DEBUG_DATA;
+ list_add_tail(&vma_op->base.entry, &ops->list);
+ break;
default:
drm_warn(&vm->xe->drm, "NOT POSSIBLE\n");
ops = ERR_PTR(-EINVAL);
@@ -2712,6 +2744,11 @@ static int xe_vma_op_commit(struct xe_vm *vm, struct xe_vma_op *op)
case DRM_GPUVA_OP_PREFETCH:
op->flags |= XE_VMA_OP_COMMITTED;
break;
+ case DRM_GPUVA_OP_DRIVER:
+ if (op->subop != XE_VMA_SUBOP_ADD_DEBUG_DATA &&
+ op->subop != XE_VMA_SUBOP_REMOVE_DEBUG_DATA)
+ drm_warn(&vm->xe->drm, "Unexpected vma sub op: %d", op->subop);
+ break;
default:
drm_warn(&vm->xe->drm, "NOT POSSIBLE\n");
}
@@ -2914,6 +2951,11 @@ static int vm_bind_ioctl_ops_parse(struct xe_vm *vm, struct drm_gpuva_ops *ops,
xe_vma_ops_incr_pt_update_ops(vops, op->tile_mask, 1);
break;
+ case DRM_GPUVA_OP_DRIVER:
+ if (op->subop != XE_VMA_SUBOP_ADD_DEBUG_DATA &&
+ op->subop != XE_VMA_SUBOP_REMOVE_DEBUG_DATA)
+ drm_warn(&vm->xe->drm, "Unexpected vma sub op: %d", op->subop);
+ break;
default:
drm_warn(&vm->xe->drm, "NOT POSSIBLE\n");
}
@@ -2987,6 +3029,13 @@ static void xe_vma_op_unwind(struct xe_vm *vm, struct xe_vma_op *op,
case DRM_GPUVA_OP_PREFETCH:
/* Nothing to do */
break;
+ case DRM_GPUVA_OP_DRIVER:
+ if (op->subop == XE_VMA_SUBOP_ADD_DEBUG_DATA ||
+ op->subop == XE_VMA_SUBOP_REMOVE_DEBUG_DATA)
+ xe_debug_data_op_unwind(vm, op);
+ else
+ drm_warn(&vm->xe->drm, "Unexpected vma sub op: %d", op->subop);
+ break;
default:
drm_warn(&vm->xe->drm, "NOT POSSIBLE\n");
}
@@ -3235,6 +3284,11 @@ static int op_lock_and_prep(struct drm_exec *exec, struct xe_vm *vm,
exec);
break;
}
+ case DRM_GPUVA_OP_DRIVER:
+ if (op->subop != XE_VMA_SUBOP_ADD_DEBUG_DATA &&
+ op->subop != XE_VMA_SUBOP_REMOVE_DEBUG_DATA)
+ drm_warn(&vm->xe->drm, "Unexpected vma sub op: %d", op->subop);
+ break;
default:
drm_warn(&vm->xe->drm, "NOT POSSIBLE\n");
}
@@ -3474,6 +3528,11 @@ static void op_add_ufence(struct xe_vm *vm, struct xe_vma_op *op,
case DRM_GPUVA_OP_PREFETCH:
vma_add_ufence(gpuva_to_vma(op->base.prefetch.va), ufence);
break;
+ case DRM_GPUVA_OP_DRIVER:
+ if (op->subop != XE_VMA_SUBOP_ADD_DEBUG_DATA &&
+ op->subop != XE_VMA_SUBOP_REMOVE_DEBUG_DATA)
+ drm_warn(&vm->xe->drm, "Unexpected vma sub op: %d", op->subop);
+ break;
default:
drm_warn(&vm->xe->drm, "NOT POSSIBLE\n");
}
@@ -3561,6 +3620,79 @@ ALLOW_ERROR_INJECTION(vm_bind_ioctl_ops_execute, ERRNO);
#define XE_64K_PAGE_MASK 0xffffull
#define ALL_DRM_XE_SYNCS_FLAGS (DRM_XE_SYNCS_FLAG_WAIT_FOR_OP)
+#define MAX_USER_EXTENSIONS 16
+
+typedef int (*xe_vm_bind_user_extension_check_fn)(struct xe_vm *vm, u32 operation, u64 extension);
+
+typedef int (*xe_vm_bind_user_extension_process_fn)(struct xe_vm *vm, struct drm_gpuva_ops *ops,
+ u32 operation, u64 extension);
+
+static const xe_vm_bind_user_extension_check_fn vm_bind_extension_check_funcs[] = {
+ [XE_VM_BIND_OP_EXTENSIONS_DEBUG_DATA] = xe_debug_data_check_extension,
+};
+
+static const xe_vm_bind_user_extension_process_fn vm_bind_extension_process_funcs[] = {
+ [XE_VM_BIND_OP_EXTENSIONS_DEBUG_DATA] = xe_debug_data_process_extension,
+};
+
+#define MAX_USER_EXTENSIONS 16
+static int __vm_bind_op_user_extensions(struct xe_vm *vm, struct drm_gpuva_ops *ops,
+ u32 operation, u64 extensions)
+{
+ struct xe_device *xe = vm->xe;
+ int debug_data_count = 0;
+ int ext_count = 0;
+ int err = -1;
+
+ struct drm_xe_user_extension ext;
+
+ while (extensions) {
+ u64 __user *address = u64_to_user_ptr(extensions);
+
+ if (XE_IOCTL_DBG(xe, ++ext_count >= MAX_USER_EXTENSIONS))
+ return -E2BIG;
+
+ err = copy_from_user(&ext, address, sizeof(ext));
+ if (XE_IOCTL_DBG(xe, err))
+ return -EFAULT;
+
+ if (XE_IOCTL_DBG(xe, operation != DRM_XE_VM_BIND_OP_ADD_DEBUG_DATA &&
+ operation != DRM_XE_VM_BIND_OP_REMOVE_DEBUG_DATA &&
+ ext.name == XE_VM_BIND_OP_EXTENSIONS_DEBUG_DATA) ||
+ XE_IOCTL_DBG(xe, ext.name == XE_VM_BIND_OP_EXTENSIONS_DEBUG_DATA &&
+ ++debug_data_count > 1))
+ return -EINVAL;
+
+ if (XE_IOCTL_DBG(xe, ext.pad) ||
+ XE_IOCTL_DBG(xe, ext.name > XE_VM_BIND_OP_EXTENSIONS_DEBUG_DATA))
+ return -EINVAL;
+
+ if (!ops)
+ err = vm_bind_extension_check_funcs[ext.name](vm, operation, extensions);
+ else
+ err = vm_bind_extension_process_funcs[ext.name](vm, ops, operation,
+ extensions);
+
+ if (XE_IOCTL_DBG(xe, err))
+ return err;
+
+ extensions = ext.next_extension;
+ }
+
+ return 0;
+}
+
+static int vm_bind_ioctl_check_user_extensions(struct xe_vm *vm, u32 operation, u64 extensions)
+{
+ return __vm_bind_op_user_extensions(vm, NULL, operation, extensions);
+}
+
+static int vm_bind_ioctl_process_user_extensions(struct xe_vm *vm, struct drm_gpuva_ops *ops,
+ u32 operation, u64 extensions)
+{
+ return __vm_bind_op_user_extensions(vm, ops, operation, extensions);
+}
+
static int vm_bind_ioctl_check_args(struct xe_device *xe, struct xe_vm *vm,
struct drm_xe_vm_bind *args,
struct drm_xe_vm_bind_op **bind_ops)
@@ -3612,6 +3744,7 @@ static int vm_bind_ioctl_check_args(struct xe_device *xe, struct xe_vm *vm,
DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR;
bool is_decompress = flags & DRM_XE_VM_BIND_FLAG_DECOMPRESS;
u16 pat_index = (*bind_ops)[i].pat_index;
+ u64 extensions = (*bind_ops)[i].extensions;
u16 coh_mode;
bool comp_en;
@@ -3641,7 +3774,7 @@ static int vm_bind_ioctl_check_args(struct xe_device *xe, struct xe_vm *vm,
goto free_bind_ops;
}
- if (XE_IOCTL_DBG(xe, op > DRM_XE_VM_BIND_OP_PREFETCH) ||
+ if (XE_IOCTL_DBG(xe, op > DRM_XE_VM_BIND_OP_REMOVE_DEBUG_DATA) ||
XE_IOCTL_DBG(xe, flags & ~SUPPORTED_FLAGS) ||
XE_IOCTL_DBG(xe, obj && (is_null || is_cpu_addr_mirror)) ||
XE_IOCTL_DBG(xe, obj_offset && (is_null ||
@@ -3693,7 +3826,9 @@ static int vm_bind_ioctl_check_args(struct xe_device *xe, struct xe_vm *vm,
XE_IOCTL_DBG(xe, addr & ~PAGE_MASK) ||
XE_IOCTL_DBG(xe, range & ~PAGE_MASK) ||
XE_IOCTL_DBG(xe, !range &&
- op != DRM_XE_VM_BIND_OP_UNMAP_ALL)) {
+ op != DRM_XE_VM_BIND_OP_UNMAP_ALL &&
+ op != DRM_XE_VM_BIND_OP_ADD_DEBUG_DATA &&
+ op != DRM_XE_VM_BIND_OP_REMOVE_DEBUG_DATA)) {
err = -EINVAL;
goto free_bind_ops;
}
@@ -3704,6 +3839,10 @@ static int vm_bind_ioctl_check_args(struct xe_device *xe, struct xe_vm *vm,
err = -EOPNOTSUPP;
goto free_bind_ops;
}
+
+ err = vm_bind_ioctl_check_user_extensions(vm, op, extensions);
+ if (err)
+ goto free_bind_ops;
}
return 0;
@@ -3981,11 +4120,17 @@ int xe_vm_bind_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
u64 obj_offset = bind_ops[i].obj_offset;
u32 prefetch_region = bind_ops[i].prefetch_mem_region_instance;
u16 pat_index = bind_ops[i].pat_index;
+ u64 extensions = bind_ops[i].extensions;
ops[i] = vm_bind_ioctl_ops_create(vm, &vops, bos[i], obj_offset,
addr, range, op, flags,
- prefetch_region, pat_index);
- if (IS_ERR(ops[i])) {
+ prefetch_region, pat_index, extensions);
+
+ if (!IS_ERR(ops[i]) && extensions) {
+ err = vm_bind_ioctl_process_user_extensions(vm, ops[i], op, extensions);
+ if (err)
+ goto unwind_ops;
+ } else if (IS_ERR(ops[i])) {
err = PTR_ERR(ops[i]);
ops[i] = NULL;
goto unwind_ops;
@@ -4211,7 +4356,7 @@ struct dma_fence *xe_vm_bind_kernel_bo(struct xe_vm *vm, struct xe_bo *bo,
ops = vm_bind_ioctl_ops_create(vm, &vops, bo, 0, addr, xe_bo_size(bo),
DRM_XE_VM_BIND_OP_MAP, 0, 0,
- xe_cache_pat_idx(vm->xe, cache_lvl));
+ xe_cache_pat_idx(vm->xe, cache_lvl), 0);
if (IS_ERR(ops)) {
err = PTR_ERR(ops);
goto release_vm_lock;
diff --git a/drivers/gpu/drm/xe/xe_vm_types.h b/drivers/gpu/drm/xe/xe_vm_types.h
index 635ed29b9a69..d24e594e7c33 100644
--- a/drivers/gpu/drm/xe/xe_vm_types.h
+++ b/drivers/gpu/drm/xe/xe_vm_types.h
@@ -15,6 +15,7 @@
#include <linux/mmu_notifier.h>
#include <linux/scatterlist.h>
+#include "xe_debug_data_types.h"
#include "xe_device_types.h"
#include "xe_pt_types.h"
#include "xe_range_fence.h"
@@ -406,6 +407,12 @@ struct xe_vm {
bool batch_invalidate_tlb;
/** @xef: Xe file handle for tracking this VM's drm client */
struct xe_file *xef;
+
+ /** @debug_data: track debug_data mapped to vm */
+ struct {
+ struct list_head list;
+ struct mutex lock;
+ } debug_data;
};
/** struct xe_vma_op_map - VMA map operation */
@@ -479,6 +486,12 @@ struct xe_vma_op_prefetch_range {
struct drm_pagemap *dpagemap;
};
+/** struct xe_vma_op_debug_data - debug data altering operation */
+struct xe_vma_op_modify_debug_data {
+ /** @debug_data: debug data associated with that operation */
+ struct xe_debug_data debug_data;
+};
+
/** enum xe_vma_op_flags - flags for VMA operation */
enum xe_vma_op_flags {
/** @XE_VMA_OP_COMMITTED: VMA operation committed */
@@ -495,6 +508,10 @@ enum xe_vma_subop {
XE_VMA_SUBOP_MAP_RANGE,
/** @XE_VMA_SUBOP_UNMAP_RANGE: Unmap range */
XE_VMA_SUBOP_UNMAP_RANGE,
+ /** @XE_VMA_SUBOP_ADD_DEBUG_DATA: Add debug data to vm */
+ XE_VMA_SUBOP_ADD_DEBUG_DATA,
+ /** @XE_VMA_SUBOP_REMOVE_DEBUG_DATA: Remove debug data from vm */
+ XE_VMA_SUBOP_REMOVE_DEBUG_DATA,
};
/** struct xe_vma_op - VMA operation */
@@ -523,6 +540,8 @@ struct xe_vma_op {
struct xe_vma_op_unmap_range unmap_range;
/** @prefetch_range: VMA prefetch range operation specific data */
struct xe_vma_op_prefetch_range prefetch_range;
+ /** @debug_data: debug_data operation specific data */
+ struct xe_vma_op_modify_debug_data modify_debug_data;
};
};
diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
index ed53a56ad71b..2d90402d4e4e 100644
--- a/include/uapi/drm/xe_drm.h
+++ b/include/uapi/drm/xe_drm.h
@@ -6,6 +6,8 @@
#ifndef _UAPI_XE_DRM_H_
#define _UAPI_XE_DRM_H_
+#include <linux/limits.h>
+
#include "drm.h"
#if defined(__cplusplus)
@@ -1020,6 +1022,63 @@ struct drm_xe_vm_destroy {
__u64 reserved[2];
};
+/**
+ * struct drm_xe_vm_bind_op_ext_debug_data - debug data extension struct for
+ * :c:type:`drm_xe_vm_bind_op`
+ *
+ * The GPU VM can be annotated by issuing a bind operation with the
+ * :c:member:`drm_xe_vm_bind_op.op` set to %DRM_XE_VM_BIND_OP_ADD_DEBUG_DATA or
+ * %DRM_XE_VM_BIND_OP_REMOVE_DEBUG_DATA. Each such operation has to provide a
+ * :c:type:`drm_xe_vm_bind_op_ext_debug_data` extension, which describes the
+ * debug data to add or remove.
+ *
+ * This extension can either point to a file that contains relevant debug data
+ * or annotate the VM range with a pseudopath by setting the
+ * %DRM_XE_VM_BIND_DEBUG_DATA_FLAG_PSEUDO flag and providing one of the supported
+ * pseudopath values:
+ * - %DRM_XE_VM_BIND_DEBUG_DATA_PSEUDO_MODULE_AREA
+ * - %DRM_XE_VM_BIND_DEBUG_DATA_PSEUDO_SBA_AREA
+ * - %DRM_XE_VM_BIND_DEBUG_DATA_PSEUDO_SIP_AREA
+ *
+ */
+struct drm_xe_vm_bind_op_ext_debug_data {
+ /** @base: Base user extension */
+ struct drm_xe_user_extension base;
+
+ /** @addr: Address of the debug data mapping */
+ __u64 addr;
+
+ /** @range: Range of the debug data mapping */
+ __u64 range;
+
+#define DRM_XE_VM_BIND_DEBUG_DATA_FLAG_PSEUDO (1 << 0)
+ /** @flags: Debug data flags */
+ __u64 flags;
+
+ /**
+ * @offset: Offset into the debug data file, MBZ when
+ * %DRM_XE_VM_BIND_DEBUG_DATA_FLAG_PSEUDO is set
+ */
+ __u32 offset;
+
+ /** @reserved: Reserved */
+ __u32 reserved;
+
+ union {
+#define DRM_XE_VM_BIND_DEBUG_DATA_PSEUDO_MODULE_AREA 0x1
+#define DRM_XE_VM_BIND_DEBUG_DATA_PSEUDO_SBA_AREA 0x2
+#define DRM_XE_VM_BIND_DEBUG_DATA_PSEUDO_SIP_AREA 0x3
+ /**
+ * @pseudopath: Pseudopath used when
+ * %DRM_XE_VM_BIND_DEBUG_DATA_FLAG_PSEUDO is set
+ */
+ __u64 pseudopath;
+
+ /** @pathname: Path to the debug data file */
+ char pathname[PATH_MAX];
+ };
+};
+
/**
* struct drm_xe_vm_bind_op - run bind operations
*
@@ -1029,6 +1088,8 @@ struct drm_xe_vm_destroy {
* - %DRM_XE_VM_BIND_OP_MAP_USERPTR
* - %DRM_XE_VM_BIND_OP_UNMAP_ALL
* - %DRM_XE_VM_BIND_OP_PREFETCH
+ * - %DRM_XE_VM_BIND_OP_ADD_DEBUG_DATA
+ * - %DRM_XE_VM_BIND_OP_REMOVE_DEBUG_DATA
*
* and the @flags can be:
* - %DRM_XE_VM_BIND_FLAG_READONLY - Setup the page tables as read-only
@@ -1080,6 +1141,7 @@ struct drm_xe_vm_destroy {
* the memory region advised by madvise.
*/
struct drm_xe_vm_bind_op {
+#define XE_VM_BIND_OP_EXTENSIONS_DEBUG_DATA 0
/** @extensions: Pointer to the first extension struct, if any */
__u64 extensions;
@@ -1173,6 +1235,8 @@ struct drm_xe_vm_bind_op {
#define DRM_XE_VM_BIND_OP_MAP_USERPTR 0x2
#define DRM_XE_VM_BIND_OP_UNMAP_ALL 0x3
#define DRM_XE_VM_BIND_OP_PREFETCH 0x4
+#define DRM_XE_VM_BIND_OP_ADD_DEBUG_DATA 0x5
+#define DRM_XE_VM_BIND_OP_REMOVE_DEBUG_DATA 0x6
/** @op: Bind operation to perform */
__u32 op;
--
2.43.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 09/24] drm/xe/eudebug: Introduce vm bind and vm bind debug data events
2026-04-30 10:50 [PATCH 00/24] Intel Xe GPU Debug Support (eudebug) v8 Mika Kuoppala
` (7 preceding siblings ...)
2026-04-30 10:51 ` [PATCH 08/24] drm/xe: Introduce ADD_DEBUG_DATA and REMOVE_DEBUG_DATA vm bind ops Mika Kuoppala
@ 2026-04-30 10:51 ` Mika Kuoppala
2026-04-30 10:51 ` [PATCH 10/24] drm/xe/eudebug: Add ufence events with acks Mika Kuoppala
` (18 subsequent siblings)
27 siblings, 0 replies; 32+ messages in thread
From: Mika Kuoppala @ 2026-04-30 10:51 UTC (permalink / raw)
To: intel-xe
Cc: simona.vetter, matthew.brost, christian.koenig, thomas.hellstrom,
joonas.lahtinen, gustavo.sousa, jan.maslak,
dominik.karol.piatkowski, rodrigo.vivi, andrzej.hajda,
matthew.auld, maciej.patelczyk, gwan-gyeong.mun,
Christoph Manszewski, Mika Kuoppala
From: Christoph Manszewski <christoph.manszewski@intel.com>
This patch adds events to track the bind ioctl and associated debug data add
and remove operations. As a single bind can involve multiple operations and
may fail mid-process.
Add bind event to signal to debugger when bind operation is executed.
Further add debug data add and remove operations so debugger
can keep track of regions where they reside. The bind event is
important as we will want to include ufence event further
in the series and tie it to this bind.
Only deliver bind+operations to the debugger if the vm bind
op execution chain succeeds.
v2: - avoid sending bind if there is no operations (Mika)
- documentation (Christoph, Mika)
Signed-off-by: Christoph Manszewski <christoph.manszewski@intel.com>
Co-developed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
Documentation/gpu/xe/xe_eudebug.rst | 6 +
drivers/gpu/drm/xe/xe_eudebug.c | 226 +++++++++++++++++++++++++-
drivers/gpu/drm/xe/xe_eudebug.h | 7 +
drivers/gpu/drm/xe/xe_eudebug_types.h | 2 +-
drivers/gpu/drm/xe/xe_vm.c | 4 +
include/uapi/drm/xe_drm_eudebug.h | 85 ++++++++++
6 files changed, 325 insertions(+), 5 deletions(-)
diff --git a/Documentation/gpu/xe/xe_eudebug.rst b/Documentation/gpu/xe/xe_eudebug.rst
index e191e2c8ded4..1f743f1d6f2a 100644
--- a/Documentation/gpu/xe/xe_eudebug.rst
+++ b/Documentation/gpu/xe/xe_eudebug.rst
@@ -57,3 +57,9 @@ Resource Event Types
.. kernel-doc:: include/uapi/drm/xe_drm_eudebug.h
:identifiers: drm_xe_eudebug_event_exec_queue
+
+.. kernel-doc:: include/uapi/drm/xe_drm_eudebug.h
+ :identifiers: drm_xe_eudebug_event_vm_bind
+
+.. kernel-doc:: include/uapi/drm/xe_drm_eudebug.h
+ :identifiers: drm_xe_eudebug_event_vm_bind_op_debug_data
diff --git a/drivers/gpu/drm/xe/xe_eudebug.c b/drivers/gpu/drm/xe/xe_eudebug.c
index 7c553881a617..b66b834c0575 100644
--- a/drivers/gpu/drm/xe/xe_eudebug.c
+++ b/drivers/gpu/drm/xe/xe_eudebug.c
@@ -12,6 +12,7 @@
#include <uapi/drm/xe_drm.h>
#include "xe_assert.h"
+#include "xe_debug_data_types.h"
#include "xe_device.h"
#include "xe_eudebug.h"
#include "xe_eudebug_types.h"
@@ -924,6 +925,167 @@ void xe_eudebug_exec_queue_destroy(struct xe_file *xef, struct xe_exec_queue *q)
xe_eudebug_event_put(d, exec_queue_destroy_event(d, xef, q));
}
+static int send_vm_bind_event(struct xe_eudebug *d,
+ struct xe_vm *vm,
+ u64 vm_handle,
+ u32 bind_flags,
+ u32 num_ops, u64 *seqno)
+{
+ struct drm_xe_eudebug_event_vm_bind *e;
+ struct drm_xe_eudebug_event *event;
+ const u32 sz = sizeof(*e);
+ const u32 base_flags = DRM_XE_EUDEBUG_EVENT_STATE_CHANGE;
+
+ *seqno = atomic_long_inc_return(&d->events.seqno);
+
+ event = xe_eudebug_create_event(d, DRM_XE_EUDEBUG_EVENT_VM_BIND,
+ *seqno, base_flags, sz);
+ if (!event)
+ return -ENOMEM;
+
+ e = cast_event(e, event);
+
+ e->vm_handle = vm_handle;
+ e->flags = bind_flags;
+ e->num_bind_ops = num_ops;
+
+ return xe_eudebug_queue_event(d, event);
+}
+
+static int vm_bind_event(struct xe_eudebug *d,
+ struct xe_vm *vm,
+ u32 flags,
+ u32 num_ops,
+ u64 *seqno)
+{
+ int h_vm;
+
+ h_vm = find_handle(d, XE_EUDEBUG_RES_TYPE_VM, vm);
+ if (h_vm < 0)
+ return h_vm;
+
+ return send_vm_bind_event(d, vm, h_vm, flags,
+ num_ops, seqno);
+}
+
+static int vm_bind_op_event(struct xe_eudebug *d,
+ struct xe_vm *vm,
+ const u32 flags,
+ const u64 bind_ref_seqno,
+ const u64 num_extensions,
+ struct xe_debug_data *debug_data,
+ u64 *op_seqno)
+{
+ struct drm_xe_eudebug_event_vm_bind_op_debug_data *e;
+ struct drm_xe_eudebug_event *event;
+ const u32 sz = sizeof(*e);
+
+ *op_seqno = atomic_long_inc_return(&d->events.seqno);
+
+ event = xe_eudebug_create_event(d, DRM_XE_EUDEBUG_EVENT_VM_BIND_OP_DEBUG_DATA,
+ *op_seqno, flags, sz);
+ if (!event)
+ return -ENOMEM;
+
+ e = cast_event(e, event);
+
+ e->vm_bind_ref_seqno = bind_ref_seqno;
+ e->num_extensions = num_extensions;
+ e->addr = debug_data->addr;
+ e->range = debug_data->range;
+ e->flags = debug_data->flags;
+ e->offset = debug_data->offset;
+
+ if (debug_data->flags & DRM_XE_VM_BIND_DEBUG_DATA_FLAG_PSEUDO)
+ e->pseudopath = debug_data->pseudopath;
+ else
+ strscpy(e->pathname, debug_data->pathname, PATH_MAX);
+
+ return xe_eudebug_queue_event(d, event);
+}
+
+static int vm_bind_op(struct xe_eudebug *d, struct xe_vm *vm,
+ const u32 flags, const u64 bind_ref_seqno,
+ struct xe_debug_data *debug_data)
+{
+ u64 op_seqno = 0;
+ u64 num_extensions = 0;
+ int ret;
+
+ ret = vm_bind_op_event(d, vm, flags, bind_ref_seqno, num_extensions,
+ debug_data, &op_seqno);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+void xe_eudebug_vm_bind_execute(struct xe_vm *vm,
+ struct xe_vma_ops *ops)
+{
+ struct xe_eudebug *d;
+ struct xe_vma_op *op;
+ u64 bind_seqno = 0;
+ u32 num_ops;
+ int err;
+
+ if (!xe_vm_in_lr_mode(vm))
+ return;
+
+ d = xe_eudebug_get(vm->xef);
+ if (!d)
+ return;
+
+ num_ops = 0;
+ list_for_each_entry(op, &ops->list, link) {
+ if (op->base.op != DRM_GPUVA_OP_DRIVER)
+ continue;
+
+ if (op->subop == XE_VMA_SUBOP_ADD_DEBUG_DATA ||
+ op->subop == XE_VMA_SUBOP_REMOVE_DEBUG_DATA)
+ num_ops++;
+ }
+
+ lockdep_assert_held_write(&vm->lock);
+
+ if (!num_ops) {
+ xe_eudebug_put(d);
+ return;
+ }
+
+ err = vm_bind_event(d, vm, 0,
+ num_ops, &bind_seqno);
+ if (err)
+ goto out_err;
+
+ list_for_each_entry(op, &ops->list, link) {
+ u32 flags = 0;
+
+ if (op->base.op != DRM_GPUVA_OP_DRIVER)
+ continue;
+
+ if (op->subop == XE_VMA_SUBOP_ADD_DEBUG_DATA)
+ flags = DRM_XE_EUDEBUG_EVENT_CREATE;
+
+ if (op->subop == XE_VMA_SUBOP_REMOVE_DEBUG_DATA)
+ flags = DRM_XE_EUDEBUG_EVENT_DESTROY;
+
+ if (!flags)
+ continue;
+
+ err = vm_bind_op(d, vm, flags, bind_seqno,
+ &op->modify_debug_data.debug_data);
+ if (err)
+ goto out_err;
+ }
+
+out_err:
+ if (err)
+ xe_eudebug_disconnect(d, err);
+
+ xe_eudebug_put(d);
+}
+
static struct xe_file *xe_eudebug_target_get(struct xe_eudebug *d)
{
struct xe_file *xef = NULL;
@@ -936,19 +1098,67 @@ static struct xe_file *xe_eudebug_target_get(struct xe_eudebug *d)
return xef;
}
+static int vm_discover_binds(struct xe_eudebug *d, struct xe_vm *vm)
+{
+ struct xe_debug_data *dd;
+ struct list_head *pos;
+ unsigned int ops, count;
+ u64 ref_seqno;
+ int err;
+
+ if (list_empty(&vm->debug_data.list))
+ return 0;
+
+ count = 0;
+ list_for_each(pos, &vm->debug_data.list)
+ count++;
+
+ ops = count;
+ ref_seqno = 0;
+ err = vm_bind_event(d, vm, 0, ops, &ref_seqno);
+ if (err) {
+ eu_dbg(d, "vm_bind_event error %d\n", err);
+ return err;
+ }
+
+ list_for_each_entry(dd, &vm->debug_data.list, link) {
+ err = vm_bind_op(d, vm, DRM_XE_EUDEBUG_EVENT_CREATE, ref_seqno, dd);
+ if (err) {
+ eu_dbg(d, "vm_bind_op error %d\n", err);
+ return err;
+ }
+
+ ops--;
+ }
+
+ XE_WARN_ON(ops);
+
+ return ops ? -EIO : count;
+}
+
static void discover_client(struct xe_eudebug *d)
{
struct xe_file *xef;
struct xe_exec_queue *q;
struct xe_vm *vm;
unsigned long i;
- unsigned int vm_count = 0, eq_count = 0;
+ unsigned int vm_count = 0, eq_count = 0, ops_count = 0;
int err = 0;
xef = xe_eudebug_target_get(d);
if (!xef)
return;
+ /*
+ * xe_eudebug ref is taken for discovery worker. It will
+ * hold target xe_file ref and xe_file holds vm and exec_queue
+ * refs.
+ *
+ * The relevant ioctls through xe_file are through
+ * down_read(&xef->eudebug.lock). That means we can peek inside
+ * the resources without taking their respective locks by
+ * taking write lock.
+ */
down_write(&xef->eudebug.ioctl_lock);
eu_dbg(d, "Discovery start for %lld", d->session);
@@ -958,6 +1168,12 @@ static void discover_client(struct xe_eudebug *d)
if (err)
break;
vm_count++;
+
+ err = vm_discover_binds(d, vm);
+ if (err < 0)
+ break;
+
+ ops_count += err;
}
xa_for_each(&xef->exec_queue.xa, i, q) {
@@ -967,6 +1183,8 @@ static void discover_client(struct xe_eudebug *d)
err = exec_queue_create_event(d, xef, q);
if (err)
break;
+
+ eq_count++;
}
complete_all(&d->discovery);
@@ -975,9 +1193,9 @@ static void discover_client(struct xe_eudebug *d)
up_write(&xef->eudebug.ioctl_lock);
- if (vm_count || eq_count)
- eu_dbg(d, "Discovery found %u vms, %u exec_queues",
- vm_count, eq_count);
+ if (vm_count || eq_count || ops_count)
+ eu_dbg(d, "Discovery found %u vms, %u exec_queues, %u bind_ops",
+ vm_count, eq_count, ops_count);
xe_file_put(xef);
}
diff --git a/drivers/gpu/drm/xe/xe_eudebug.h b/drivers/gpu/drm/xe/xe_eudebug.h
index 10480a226fac..9c622362c0f7 100644
--- a/drivers/gpu/drm/xe/xe_eudebug.h
+++ b/drivers/gpu/drm/xe/xe_eudebug.h
@@ -10,10 +10,14 @@
struct drm_device;
struct drm_file;
+struct xe_debug_data;
struct xe_device;
struct xe_file;
struct xe_vm;
+struct xe_vma;
+struct xe_vma_ops;
struct xe_exec_queue;
+struct xe_user_fence;
#if IS_ENABLED(CONFIG_DRM_XE_EUDEBUG)
@@ -50,6 +54,8 @@ int xe_eudebug_enable(struct xe_device *xe, bool enable);
void xe_eudebug_exec_queue_create(struct xe_file *xef, struct xe_exec_queue *q);
void xe_eudebug_exec_queue_destroy(struct xe_file *xef, struct xe_exec_queue *q);
+void xe_eudebug_vm_bind_execute(struct xe_vm *vm, struct xe_vma_ops *ops);
+
#else
static inline int xe_eudebug_connect_ioctl(struct drm_device *dev,
@@ -67,6 +73,7 @@ static inline void xe_eudebug_vm_destroy(struct xe_file *xef, struct xe_vm *vm)
static inline void xe_eudebug_exec_queue_create(struct xe_file *xef, struct xe_exec_queue *q) { }
static inline void xe_eudebug_exec_queue_destroy(struct xe_file *xef, struct xe_exec_queue *q) { }
+static inline void xe_eudebug_vm_bind_execute(struct xe_vm *vm, struct xe_vma_ops *ops) { }
#endif /* CONFIG_DRM_XE_EUDEBUG */
#endif /* _XE_EUDEBUG_H_ */
diff --git a/drivers/gpu/drm/xe/xe_eudebug_types.h b/drivers/gpu/drm/xe/xe_eudebug_types.h
index 9c111c483778..1bd6eb2aa102 100644
--- a/drivers/gpu/drm/xe/xe_eudebug_types.h
+++ b/drivers/gpu/drm/xe/xe_eudebug_types.h
@@ -33,7 +33,7 @@ enum xe_eudebug_state {
};
#define CONFIG_DRM_XE_DEBUGGER_EVENT_QUEUE_SIZE 64
-#define XE_EUDEBUG_MAX_EVENT_TYPE DRM_XE_EUDEBUG_EVENT_EXEC_QUEUE
+#define XE_EUDEBUG_MAX_EVENT_TYPE DRM_XE_EUDEBUG_EVENT_VM_BIND_OP_DEBUG_DATA
/**
* struct xe_eudebug_handle - eudebug resource handle
diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
index 9a3980e8422a..f00bd5801b0c 100644
--- a/drivers/gpu/drm/xe/xe_vm.c
+++ b/drivers/gpu/drm/xe/xe_vm.c
@@ -3588,6 +3588,10 @@ static struct dma_fence *vm_bind_ioctl_ops_execute(struct xe_vm *vm,
xe_vm_set_validation_exec(vm, &exec);
fence = ops_execute(vm, vops);
xe_vm_set_validation_exec(vm, NULL);
+
+ if (!IS_ERR(fence) || PTR_ERR(fence) == -ENODATA)
+ xe_eudebug_vm_bind_execute(vm, vops);
+
if (IS_ERR(fence)) {
if (PTR_ERR(fence) == -ENODATA)
vm_bind_ioctl_ops_fini(vm, vops, NULL);
diff --git a/include/uapi/drm/xe_drm_eudebug.h b/include/uapi/drm/xe_drm_eudebug.h
index c9f21283ffdf..230c8cdcbd21 100644
--- a/include/uapi/drm/xe_drm_eudebug.h
+++ b/include/uapi/drm/xe_drm_eudebug.h
@@ -46,6 +46,8 @@ struct drm_xe_eudebug_event {
#define DRM_XE_EUDEBUG_EVENT_READ 1
#define DRM_XE_EUDEBUG_EVENT_VM 2
#define DRM_XE_EUDEBUG_EVENT_EXEC_QUEUE 3
+#define DRM_XE_EUDEBUG_EVENT_VM_BIND 4
+#define DRM_XE_EUDEBUG_EVENT_VM_BIND_OP_DEBUG_DATA 5
/** @flags: Flags */
__u16 flags;
@@ -99,6 +101,89 @@ struct drm_xe_eudebug_event_exec_queue {
__u64 lrc_handle[];
};
+/**
+ * struct drm_xe_eudebug_event_vm_bind - VM Bind Event
+ *
+ * When the client (debuggee) calls the vm_bind_ioctl with the
+ * DRM_XE_VM_BIND_OP_[ADD|REMOVE]_DEBUG_DATA operation, the following event
+ * sequence will be created (for the debugger)::
+ *
+ * ┌───────────────────────┐
+ * │ EVENT_VM_BIND ├──────────────────┬─┬┄┐
+ * └───────────────────────┘ │ │ ┊
+ * ┌──────────────────────────────────┐ │ │ ┊
+ * │ EVENT_VM_BIND_OP_DEBUG_DATA #1 ├───┘ │ ┊
+ * └──────────────────────────────────┘ │ ┊
+ * ... │ ┊
+ * ┌──────────────────────────────────┐ │ ┊
+ * │ EVENT_VM_BIND_OP_DEBUG_DATA #n ├─────┘ ┊
+ * └──────────────────────────────────┘ ┊
+ * ┊
+ * ┌┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┐ ┊
+ * ┊ EVENT_UFENCE ├┄┄┄┄┄┄┄┘
+ * └┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┘
+ *
+ * All the events below VM_BIND will reference the VM_BIND
+ * they associate with, by field .vm_bind_ref_seqno.
+ */
+struct drm_xe_eudebug_event_vm_bind {
+ /** @base: Base event */
+ struct drm_xe_eudebug_event base;
+
+ /** @vm_handle: VM handle for this bind */
+ __u64 vm_handle;
+
+ /** @flags: Bind specific flags */
+ __u32 flags;
+
+ /** @num_bind_ops: How many [ADD|REMOVE]_DEBUG_DATA operations this bind has */
+ __u32 num_bind_ops;
+};
+
+/**
+ * struct drm_xe_eudebug_event_vm_bind_op_debug_data - VM Bind Op Debug Data Event
+ *
+ * When the target drm client issues a vm bind, each operation of type
+ * %DRM_XE_VM_BIND_OP_ADD_DEBUG_DATA or %DRM_XE_VM_BIND_OP_REMOVE_DEBUG_DATA
+ * will generate an event of this type. For reference see
+ * :c:type:`drm_xe_vm_bind_op_ext_debug_data`.
+ */
+struct drm_xe_eudebug_event_vm_bind_op_debug_data {
+ /** @base: Base event */
+ struct drm_xe_eudebug_event base;
+
+ /** @vm_bind_ref_seqno: Parent :c:member:`drm_xe_eudebug_event_vm_bind.base.seqno` */
+ __u64 vm_bind_ref_seqno;
+
+ /** @num_extensions: Extension count for this op */
+ __u64 num_extensions;
+
+ /** @addr: Address of the debug data mapping */
+ __u64 addr;
+
+ /** @range: Range of the debug data mapping */
+ __u64 range;
+
+ /** @flags: Debug data flags */
+ __u64 flags;
+
+ /** @offset: Offset into the debug data file */
+ __u32 offset;
+
+ /** @reserved: Reserved, must be zero */
+ __u32 reserved;
+ union {
+ /**
+ * @pseudopath: Pseudopath if
+ * %DRM_XE_VM_BIND_DEBUG_DATA_FLAG_PSEUDO was set
+ */
+ __u64 pseudopath;
+
+ /** @pathname: Path to the debug data file */
+ char pathname[PATH_MAX];
+ };
+};
+
#if defined(__cplusplus)
}
#endif
--
2.43.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 10/24] drm/xe/eudebug: Add ufence events with acks
2026-04-30 10:50 [PATCH 00/24] Intel Xe GPU Debug Support (eudebug) v8 Mika Kuoppala
` (8 preceding siblings ...)
2026-04-30 10:51 ` [PATCH 09/24] drm/xe/eudebug: Introduce vm bind and vm bind debug data events Mika Kuoppala
@ 2026-04-30 10:51 ` Mika Kuoppala
2026-04-30 10:51 ` [PATCH 11/24] drm/xe/eudebug: vm open/pread/pwrite Mika Kuoppala
` (17 subsequent siblings)
27 siblings, 0 replies; 32+ messages in thread
From: Mika Kuoppala @ 2026-04-30 10:51 UTC (permalink / raw)
To: intel-xe
Cc: simona.vetter, matthew.brost, christian.koenig, thomas.hellstrom,
joonas.lahtinen, gustavo.sousa, jan.maslak,
dominik.karol.piatkowski, rodrigo.vivi, andrzej.hajda,
matthew.auld, maciej.patelczyk, gwan-gyeong.mun, Mika Kuoppala
When vma is in place, debugger needs to intercept before
userspace proceeds with the workload. For example to install
a breakpoint in an eu shader.
If ufence is part of bind sequence,aAttach debugger in
xe_user_fence. When ufence signal is about to be delivered,
check if this ufence needs to be tracked by debugger.
If so, stall the delivery of the ufence signal up until
debugger has acked the ufence (event), with the ack ioctl.
v2: - return err instead of 0 to guarantee signalling (Dominik)
- checkpatch (Tilak)
- Kconfig (Mika, Andrzej)
- use lock instead of cmpxchg (Mika)
v4: - improve ref handling and no ufences nodebug binds
v5: - remove overzealous warn_on on bind_ref_seqno (Christoph)
- remove superfluous signalled (Mika)
- fix double free on bind sequence (Mika)
- Dont fill op fields if no debugger (Maciej)
v6: - rework to align with xe_eudebug_bind_execute()
v7: - fix setting signalled before debugger acks (Jan)
v8: - explicit debugger set and clears (Mika)
- take reference for for tracking check (Mika)
- fix leak of ref in handle_ack (Mika)
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
Documentation/gpu/xe/xe_eudebug.rst | 3 +
drivers/gpu/drm/xe/xe_eudebug.c | 314 +++++++++++++++++++++++++-
drivers/gpu/drm/xe/xe_eudebug.h | 9 +
drivers/gpu/drm/xe/xe_eudebug_types.h | 10 +-
drivers/gpu/drm/xe/xe_sync.c | 43 ++--
drivers/gpu/drm/xe/xe_sync.h | 7 +-
drivers/gpu/drm/xe/xe_sync_types.h | 28 ++-
include/uapi/drm/xe_drm_eudebug.h | 58 +++++
8 files changed, 444 insertions(+), 28 deletions(-)
diff --git a/Documentation/gpu/xe/xe_eudebug.rst b/Documentation/gpu/xe/xe_eudebug.rst
index 1f743f1d6f2a..db52945714f3 100644
--- a/Documentation/gpu/xe/xe_eudebug.rst
+++ b/Documentation/gpu/xe/xe_eudebug.rst
@@ -63,3 +63,6 @@ Resource Event Types
.. kernel-doc:: include/uapi/drm/xe_drm_eudebug.h
:identifiers: drm_xe_eudebug_event_vm_bind_op_debug_data
+
+.. kernel-doc:: include/uapi/drm/xe_drm_eudebug.h
+ :identifiers: drm_xe_eudebug_event_vm_bind_ufence
diff --git a/drivers/gpu/drm/xe/xe_eudebug.c b/drivers/gpu/drm/xe/xe_eudebug.c
index b66b834c0575..14be97b5b4eb 100644
--- a/drivers/gpu/drm/xe/xe_eudebug.c
+++ b/drivers/gpu/drm/xe/xe_eudebug.c
@@ -19,6 +19,7 @@
#include "xe_exec_queue.h"
#include "xe_hw_engine.h"
#include "xe_macros.h"
+#include "xe_sync.h"
#include "xe_vm.h"
/**
@@ -295,6 +296,120 @@ static void remove_debugger(struct xe_file *xef)
}
}
+struct xe_eudebug_ack {
+ struct rb_node rb_node;
+ u64 seqno;
+ u64 ts_insert;
+ struct xe_user_fence *ufence;
+};
+
+#define fetch_ack(x) rb_entry(x, struct xe_eudebug_ack, rb_node)
+
+static int compare_ack(const u64 a, const u64 b)
+{
+ if (a < b)
+ return -1;
+ else if (a > b)
+ return 1;
+
+ return 0;
+}
+
+static int ack_insert_cmp(struct rb_node * const node,
+ const struct rb_node * const p)
+{
+ return compare_ack(fetch_ack(node)->seqno,
+ fetch_ack(p)->seqno);
+}
+
+static int ack_lookup_cmp(const void * const key,
+ const struct rb_node * const node)
+{
+ return compare_ack(*(const u64 *)key,
+ fetch_ack(node)->seqno);
+}
+
+static struct xe_eudebug_ack *remove_ack(struct xe_eudebug *d, u64 seqno)
+{
+ struct rb_root * const root = &d->acks.tree;
+ struct rb_node *node;
+
+ spin_lock(&d->acks.lock);
+ node = rb_find(&seqno, root, ack_lookup_cmp);
+ if (node)
+ rb_erase(node, root);
+ spin_unlock(&d->acks.lock);
+
+ if (!node)
+ return NULL;
+
+ return rb_entry_safe(node, struct xe_eudebug_ack, rb_node);
+}
+
+static void ufence_signal_worker(struct work_struct *w)
+{
+ struct xe_user_fence * const ufence =
+ container_of(w, struct xe_user_fence, eudebug.worker);
+
+ xe_sync_ufence_signal(ufence);
+
+ xe_sync_ufence_put(ufence);
+}
+
+static void kick_ufence_worker(struct xe_user_fence *f)
+{
+ queue_work(f->xe->eudebug.wq, &f->eudebug.worker);
+}
+
+static void handle_ack(struct xe_eudebug *d, struct xe_eudebug_ack *ack,
+ bool on_disconnect)
+{
+ struct xe_user_fence *f = ack->ufence;
+ struct xe_eudebug *debugger = NULL;
+ u64 signalled_by;
+ bool signal = false;
+
+ spin_lock(&f->eudebug.lock);
+ if (!f->eudebug.signalled_seqno) {
+ f->eudebug.signalled_seqno = ack->seqno;
+ f->eudebug.bind_ref_seqno = 0;
+ debugger = f->eudebug.debugger;
+ f->eudebug.debugger = NULL;
+ signal = true;
+ }
+ signalled_by = f->eudebug.signalled_seqno;
+ spin_unlock(&f->eudebug.lock);
+
+ if (signal)
+ kick_ufence_worker(f);
+ else
+ xe_sync_ufence_put(f);
+
+ eu_dbg(d, "ACK: seqno=%llu: signalled by %llu (%s) (held %lluus)",
+ ack->seqno, signalled_by,
+ on_disconnect ? "disconnect" : "debugger",
+ ktime_us_delta(ktime_get(), ack->ts_insert));
+
+ kfree(ack);
+
+ if (debugger)
+ xe_eudebug_put(debugger);
+}
+
+static void release_acks(struct xe_eudebug *d)
+{
+ struct xe_eudebug_ack *ack, *n;
+ struct rb_root root;
+
+ spin_lock(&d->acks.lock);
+ root = d->acks.tree;
+ d->acks.tree = RB_ROOT;
+ spin_unlock(&d->acks.lock);
+
+ rbtree_postorder_for_each_entry_safe(ack, n, &root, rb_node)
+ handle_ack(d, ack, true);
+}
+
static bool xe_eudebug_detach(struct xe_device *xe,
struct xe_eudebug *d,
const int err)
@@ -318,6 +433,8 @@ static bool xe_eudebug_detach(struct xe_device *xe,
eu_dbg(d, "session %lld detached with %d", d->session, err);
+ release_acks(d);
+
remove_debugger(target);
xe_file_put(target);
@@ -1020,11 +1137,142 @@ static int vm_bind_op(struct xe_eudebug *d, struct xe_vm *vm,
return 0;
}
+void xe_eudebug_ufence_init(struct xe_user_fence *ufence)
+{
+ spin_lock_init(&ufence->eudebug.lock);
+ ufence->eudebug.debugger = NULL;
+ ufence->eudebug.bind_ref_seqno = 0;
+ ufence->eudebug.signalled_seqno = 0;
+ INIT_WORK(&ufence->eudebug.worker, ufence_signal_worker);
+}
+
+void xe_eudebug_ufence_fini(struct xe_user_fence *ufence)
+{
+ struct xe_eudebug *d = ufence->eudebug.debugger;
+
+ XE_WARN_ON(READ_ONCE(ufence->eudebug.bind_ref_seqno));
+
+ if (!d)
+ return;
+
+ ufence->eudebug.debugger = NULL;
+ xe_eudebug_put(d);
+}
+
+static int xe_eudebug_track_ufence(struct xe_eudebug *d,
+ struct xe_user_fence *f,
+ u64 seqno)
+{
+ struct xe_eudebug_ack *ack;
+ struct rb_node *old;
+
+ ack = kzalloc_obj(*ack, GFP_KERNEL);
+ if (!ack)
+ return -ENOMEM;
+
+ ack->seqno = seqno;
+ ack->ts_insert = ktime_get();
+
+ __xe_sync_ufence_get(f);
+
+ spin_lock(&d->acks.lock);
+ old = rb_find_add(&ack->rb_node,
+ &d->acks.tree, ack_insert_cmp);
+ if (!old)
+ ack->ufence = f;
+ spin_unlock(&d->acks.lock);
+
+ if (ack->ufence)
+ return 0;
+
+ xe_sync_ufence_put(f);
+ kfree(ack);
+
+ return -EEXIST;
+}
+
+static int track_ufence(struct xe_eudebug *d,
+ struct xe_user_fence *ufence)
+{
+ struct drm_xe_eudebug_event *event;
+ struct drm_xe_eudebug_event_vm_bind_ufence *e;
+ const u32 sz = sizeof(*e);
+ const u32 flags = DRM_XE_EUDEBUG_EVENT_CREATE |
+ DRM_XE_EUDEBUG_EVENT_NEED_ACK;
+ u64 seqno;
+ int ret;
+
+ if (XE_WARN_ON(!ufence->eudebug.bind_ref_seqno))
+ return -EINVAL;
+
+ seqno = atomic_long_inc_return(&d->events.seqno);
+
+ event = xe_eudebug_create_event(d, DRM_XE_EUDEBUG_EVENT_VM_BIND_UFENCE,
+ seqno, flags, sz);
+ if (!event)
+ return -ENOMEM;
+
+ e = cast_event(e, event);
+ e->vm_bind_ref_seqno = ufence->eudebug.bind_ref_seqno;
+
+ ret = xe_eudebug_track_ufence(d, ufence, seqno);
+ if (ret) {
+ kfree(event);
+
+ eu_dbg(d, "tracking of ufence %llu failed with %d\n", seqno, ret);
+
+ return ret;
+ }
+
+ return xe_eudebug_queue_event(d, event);
+}
+
+/**
+ * xe_eudebug_ufence_track - Track the ufence for eudebug
+ * @ufence : user fence that might be applicaple to tracking
+ *
+ * If this user fence was part of bind sequence, we need
+ * to track it so that we can hold the client signalling on behalf
+ * of debugger and thus deliver event to debugger.
+ *
+ * Return: true debugger will track, false debugger not interested
+ *
+ */
+bool xe_eudebug_ufence_track(struct xe_user_fence *ufence)
+{
+ struct xe_eudebug *d;
+ int ret;
+
+ spin_lock(&ufence->eudebug.lock);
+ d = ufence->eudebug.debugger;
+ if (d && !kref_get_unless_zero(&d->ref))
+ d = NULL;
+ spin_unlock(&ufence->eudebug.lock);
+
+ if (!d)
+ return false;
+
+ if (xe_eudebug_detached(d)) {
+ xe_eudebug_put(d);
+ return false;
+ }
+
+ ret = track_ufence(d, ufence);
+ if (ret)
+ xe_eudebug_disconnect(d, ret);
+
+ xe_eudebug_put(d);
+
+ return ret == 0;
+}
+
void xe_eudebug_vm_bind_execute(struct xe_vm *vm,
struct xe_vma_ops *ops)
{
+ struct xe_user_fence *ufence = NULL;
struct xe_eudebug *d;
struct xe_vma_op *op;
+ unsigned int i;
u64 bind_seqno = 0;
u32 num_ops;
int err;
@@ -1036,6 +1284,15 @@ void xe_eudebug_vm_bind_execute(struct xe_vm *vm,
if (!d)
return;
+ for (i = 0; i < ops->num_syncs; i++) {
+ struct xe_sync_entry *se = &ops->syncs[i];
+
+ if (xe_sync_is_ufence(se)) {
+ xe_assert(vm->xe, ufence == NULL);
+ ufence = se->ufence;
+ }
+ }
+
num_ops = 0;
list_for_each_entry(op, &ops->list, link) {
if (op->base.op != DRM_GPUVA_OP_DRIVER)
@@ -1053,7 +1310,8 @@ void xe_eudebug_vm_bind_execute(struct xe_vm *vm,
return;
}
- err = vm_bind_event(d, vm, 0,
+ err = vm_bind_event(d, vm,
+ ufence ? DRM_XE_EUDEBUG_EVENT_VM_BIND_FLAG_UFENCE : 0,
num_ops, &bind_seqno);
if (err)
goto out_err;
@@ -1079,6 +1337,14 @@ void xe_eudebug_vm_bind_execute(struct xe_vm *vm,
goto out_err;
}
+ if (ufence) {
+ spin_lock(&ufence->eudebug.lock);
+ kref_get(&d->ref);
+ ufence->eudebug.debugger = d;
+ ufence->eudebug.bind_ref_seqno = bind_seqno;
+ spin_unlock(&ufence->eudebug.lock);
+ }
+
out_err:
if (err)
xe_eudebug_disconnect(d, err);
@@ -1409,6 +1675,44 @@ static long xe_eudebug_read_event(struct xe_eudebug *d,
return ret;
}
+static long
+xe_eudebug_ack_event_ioctl(struct xe_eudebug *d,
+ const unsigned int cmd,
+ const u64 arg)
+{
+ struct drm_xe_eudebug_ack_event __user * const user_ptr =
+ u64_to_user_ptr(arg);
+ struct drm_xe_eudebug_ack user_arg;
+ struct xe_eudebug_ack *ack;
+ struct xe_device *xe = d->xe;
+
+ if (XE_IOCTL_DBG(xe, _IOC_SIZE(cmd) < sizeof(user_arg)))
+ return -EINVAL;
+
+ /* Userland write */
+ if (XE_IOCTL_DBG(xe, !(_IOC_DIR(cmd) & _IOC_WRITE)))
+ return -EINVAL;
+
+ if (XE_IOCTL_DBG(xe, copy_from_user(&user_arg,
+ user_ptr,
+ sizeof(user_arg))))
+ return -EFAULT;
+
+ if (XE_IOCTL_DBG(xe, user_arg.flags))
+ return -EINVAL;
+
+ if (XE_IOCTL_DBG(xe, xe_eudebug_detached(d)))
+ return -ENOTCONN;
+
+ ack = remove_ack(d, user_arg.seqno);
+ if (XE_IOCTL_DBG(xe, !ack))
+ return -EINVAL;
+
+ handle_ack(d, ack, false);
+
+ return 0;
+}
+
/**
* xe_eudebug_ioctl - Issue a command to eudebug interface
*
@@ -1436,7 +1740,10 @@ static long xe_eudebug_ioctl(struct file *file,
ret = xe_eudebug_read_event(d, arg,
!(file->f_flags & O_NONBLOCK));
break;
-
+ case DRM_XE_EUDEBUG_IOCTL_ACK_EVENT:
+ ret = xe_eudebug_ack_event_ioctl(d, cmd, arg);
+ eu_dbg(d, "ioctl cmd=EVENT_ACK ret=%ld\n", ret);
+ break;
default:
ret = -EINVAL;
}
@@ -1499,6 +1806,9 @@ xe_eudebug_connect(struct xe_device *xe,
INIT_KFIFO(d->events.fifo);
INIT_WORK(&d->discovery_work, discovery_work_fn);
+ spin_lock_init(&d->acks.lock);
+ d->acks.tree = RB_ROOT;
+
err = xe_eudebug_resources_init(d);
if (XE_IOCTL_DBG(xe, err))
goto err_free;
diff --git a/drivers/gpu/drm/xe/xe_eudebug.h b/drivers/gpu/drm/xe/xe_eudebug.h
index 9c622362c0f7..d0f1b51564dc 100644
--- a/drivers/gpu/drm/xe/xe_eudebug.h
+++ b/drivers/gpu/drm/xe/xe_eudebug.h
@@ -56,6 +56,10 @@ void xe_eudebug_exec_queue_destroy(struct xe_file *xef, struct xe_exec_queue *q)
void xe_eudebug_vm_bind_execute(struct xe_vm *vm, struct xe_vma_ops *ops);
+void xe_eudebug_ufence_init(struct xe_user_fence *ufence);
+void xe_eudebug_ufence_fini(struct xe_user_fence *ufence);
+bool xe_eudebug_ufence_track(struct xe_user_fence *ufence);
+
#else
static inline int xe_eudebug_connect_ioctl(struct drm_device *dev,
@@ -74,6 +78,11 @@ static inline void xe_eudebug_exec_queue_create(struct xe_file *xef, struct xe_e
static inline void xe_eudebug_exec_queue_destroy(struct xe_file *xef, struct xe_exec_queue *q) { }
static inline void xe_eudebug_vm_bind_execute(struct xe_vm *vm, struct xe_vma_ops *ops) { }
+
+static inline void xe_eudebug_ufence_init(struct xe_user_fence *ufence) { }
+static inline void xe_eudebug_ufence_fini(struct xe_user_fence *ufence) { }
+static inline bool xe_eudebug_ufence_track(struct xe_user_fence *ufence) { return false; }
+
#endif /* CONFIG_DRM_XE_EUDEBUG */
#endif /* _XE_EUDEBUG_H_ */
diff --git a/drivers/gpu/drm/xe/xe_eudebug_types.h b/drivers/gpu/drm/xe/xe_eudebug_types.h
index 1bd6eb2aa102..0f18667a5ab8 100644
--- a/drivers/gpu/drm/xe/xe_eudebug_types.h
+++ b/drivers/gpu/drm/xe/xe_eudebug_types.h
@@ -33,7 +33,7 @@ enum xe_eudebug_state {
};
#define CONFIG_DRM_XE_DEBUGGER_EVENT_QUEUE_SIZE 64
-#define XE_EUDEBUG_MAX_EVENT_TYPE DRM_XE_EUDEBUG_EVENT_VM_BIND_OP_DEBUG_DATA
+#define XE_EUDEBUG_MAX_EVENT_TYPE DRM_XE_EUDEBUG_EVENT_VM_BIND_UFENCE
/**
* struct xe_eudebug_handle - eudebug resource handle
@@ -125,6 +125,14 @@ struct xe_eudebug {
atomic_long_t seqno;
} events;
+ /** @acks: user fence acks tracked by this debugger */
+ struct {
+ /** @lock: guards access to tree */
+ spinlock_t lock;
+
+ /** @tree: pending acks by seqnos */
+ struct rb_root tree;
+ } acks;
};
#endif /* _XE_EUDEBUG_TYPES_H_ */
diff --git a/drivers/gpu/drm/xe/xe_sync.c b/drivers/gpu/drm/xe/xe_sync.c
index 24d6d9af20d6..70f94517e6cc 100644
--- a/drivers/gpu/drm/xe/xe_sync.c
+++ b/drivers/gpu/drm/xe/xe_sync.c
@@ -15,27 +15,20 @@
#include <uapi/drm/xe_drm.h>
#include "xe_device.h"
+#include "xe_eudebug.h"
#include "xe_exec_queue.h"
#include "xe_macros.h"
#include "xe_sched_job_types.h"
-struct xe_user_fence {
- struct xe_device *xe;
- struct kref refcount;
- struct dma_fence_cb cb;
- struct work_struct worker;
- struct mm_struct *mm;
- u64 __user *addr;
- u64 value;
- int signalled;
-};
-
static void user_fence_destroy(struct kref *kref)
{
struct xe_user_fence *ufence = container_of(kref, struct xe_user_fence,
refcount);
mmdrop(ufence->mm);
+
+ xe_eudebug_ufence_fini(ufence);
+
kfree(ufence);
}
@@ -49,7 +42,8 @@ static void user_fence_put(struct xe_user_fence *ufence)
kref_put(&ufence->refcount, user_fence_destroy);
}
-static struct xe_user_fence *user_fence_create(struct xe_device *xe, u64 addr,
+static struct xe_user_fence *user_fence_create(struct xe_device *xe,
+ u64 addr,
u64 value)
{
struct xe_user_fence *ufence;
@@ -70,14 +64,19 @@ static struct xe_user_fence *user_fence_create(struct xe_device *xe, u64 addr,
ufence->mm = current->mm;
mmgrab(ufence->mm);
+ xe_eudebug_ufence_init(ufence);
+
return ufence;
}
-static void user_fence_worker(struct work_struct *w)
+void xe_sync_ufence_signal(struct xe_user_fence *ufence)
{
- struct xe_user_fence *ufence = container_of(w, struct xe_user_fence, worker);
-
+ /*
+ * Wake up waiters only after updating the ufence state, allowing the UMD
+ * to safely reuse the same ufence without encountering -EBUSY errors.
+ */
WRITE_ONCE(ufence->signalled, 1);
+
if (mmget_not_zero(ufence->mm)) {
kthread_use_mm(ufence->mm);
if (copy_to_user(ufence->addr, &ufence->value, sizeof(ufence->value)))
@@ -88,11 +87,17 @@ static void user_fence_worker(struct work_struct *w)
drm_dbg(&ufence->xe->drm, "mmget_not_zero() failed, ufence wasn't signaled\n");
}
- /*
- * Wake up waiters only after updating the ufence state, allowing the UMD
- * to safely reuse the same ufence without encountering -EBUSY errors.
- */
wake_up_all(&ufence->xe->ufence_wq);
+}
+
+static void user_fence_worker(struct work_struct *w)
+{
+ struct xe_user_fence *ufence = container_of(w, struct xe_user_fence, worker);
+
+ /* Lets see if debugger wants to track this */
+ if (!xe_eudebug_ufence_track(ufence))
+ xe_sync_ufence_signal(ufence);
+
user_fence_put(ufence);
}
diff --git a/drivers/gpu/drm/xe/xe_sync.h b/drivers/gpu/drm/xe/xe_sync.h
index 6b949194acff..768c0517f104 100644
--- a/drivers/gpu/drm/xe/xe_sync.h
+++ b/drivers/gpu/drm/xe/xe_sync.h
@@ -10,8 +10,12 @@
struct drm_syncobj;
struct xe_device;
-struct xe_exec_queue;
struct xe_file;
+struct xe_exec_queue;
+struct drm_syncobj;
+struct dma_fence;
+struct dma_fence_chain;
+struct drm_xe_sync;
struct xe_sched_job;
struct xe_vm;
@@ -45,5 +49,6 @@ struct xe_user_fence *__xe_sync_ufence_get(struct xe_user_fence *ufence);
struct xe_user_fence *xe_sync_ufence_get(struct xe_sync_entry *sync);
void xe_sync_ufence_put(struct xe_user_fence *ufence);
int xe_sync_ufence_get_status(struct xe_user_fence *ufence);
+void xe_sync_ufence_signal(struct xe_user_fence *ufence);
#endif
diff --git a/drivers/gpu/drm/xe/xe_sync_types.h b/drivers/gpu/drm/xe/xe_sync_types.h
index b88f1833e28c..33a93a0faa72 100644
--- a/drivers/gpu/drm/xe/xe_sync_types.h
+++ b/drivers/gpu/drm/xe/xe_sync_types.h
@@ -6,13 +6,31 @@
#ifndef _XE_SYNC_TYPES_H_
#define _XE_SYNC_TYPES_H_
+#include <linux/dma-fence-array.h>
+#include <linux/kref.h>
+#include <linux/spinlock.h>
#include <linux/types.h>
-struct drm_syncobj;
-struct dma_fence;
-struct dma_fence_chain;
-struct drm_xe_sync;
-struct user_fence;
+struct xe_user_fence {
+ struct xe_device *xe;
+ struct kref refcount;
+ struct dma_fence_cb cb;
+ struct work_struct worker;
+ struct mm_struct *mm;
+ u64 __user *addr;
+ u64 value;
+ int signalled;
+
+#if IS_ENABLED(CONFIG_DRM_XE_EUDEBUG)
+ struct {
+ spinlock_t lock;
+ struct xe_eudebug *debugger;
+ u64 bind_ref_seqno;
+ u64 signalled_seqno;
+ struct work_struct worker;
+ } eudebug;
+#endif
+};
struct xe_sync_entry {
struct drm_syncobj *syncobj;
diff --git a/include/uapi/drm/xe_drm_eudebug.h b/include/uapi/drm/xe_drm_eudebug.h
index 230c8cdcbd21..fb53174869ef 100644
--- a/include/uapi/drm/xe_drm_eudebug.h
+++ b/include/uapi/drm/xe_drm_eudebug.h
@@ -11,6 +11,7 @@ extern "C" {
#endif
#define DRM_XE_EUDEBUG_IOCTL_READ_EVENT _IO('j', 0x0)
+#define DRM_XE_EUDEBUG_IOCTL_ACK_EVENT _IOW('j', 0x1, struct drm_xe_eudebug_ack)
/**
* struct drm_xe_eudebug_event - Base type of event delivered by xe_eudebug.
@@ -48,6 +49,7 @@ struct drm_xe_eudebug_event {
#define DRM_XE_EUDEBUG_EVENT_EXEC_QUEUE 3
#define DRM_XE_EUDEBUG_EVENT_VM_BIND 4
#define DRM_XE_EUDEBUG_EVENT_VM_BIND_OP_DEBUG_DATA 5
+#define DRM_XE_EUDEBUG_EVENT_VM_BIND_UFENCE 6
/** @flags: Flags */
__u16 flags;
@@ -125,6 +127,24 @@ struct drm_xe_eudebug_event_exec_queue {
*
* All the events below VM_BIND will reference the VM_BIND
* they associate with, by field .vm_bind_ref_seqno.
+ * EVENT_UFENCE will only be included if the client did
+ * attach sync of type UFENCE into its vm_bind_ioctl().
+ *
+ * When EVENT_UFENCE is sent by the driver, all the OPs of
+ * the original VM_BIND are completed and the [addr,range]
+ * contained in them are present and modifiable through the
+ * vm accessors. Accessing [addr, range] before related ufence
+ * event will lead to undefined results as the actual bind
+ * operations are async and the backing storage might not
+ * be there on a moment of receiving the event.
+ *
+ * Client's UFENCE sync will be held by the driver: client's
+ * drm_xe_wait_ufence will not complete and the value of the ufence
+ * won't appear until ufence is acked by the debugger process calling
+ * DRM_XE_EUDEBUG_IOCTL_ACK_EVENT with the event_ufence.base.seqno.
+ * This will signal the fence, .value will update and the wait will
+ * complete allowing the client to continue.
+ *
*/
struct drm_xe_eudebug_event_vm_bind {
/** @base: Base event */
@@ -135,6 +155,7 @@ struct drm_xe_eudebug_event_vm_bind {
/** @flags: Bind specific flags */
__u32 flags;
+#define DRM_XE_EUDEBUG_EVENT_VM_BIND_FLAG_UFENCE (1 << 0)
/** @num_bind_ops: How many [ADD|REMOVE]_DEBUG_DATA operations this bind has */
__u32 num_bind_ops;
@@ -184,6 +205,43 @@ struct drm_xe_eudebug_event_vm_bind_op_debug_data {
};
};
+/**
+ * struct drm_xe_eudebug_event_vm_bind_ufence - User Fence Event
+ *
+ * When target drm client does vm bind with associated user fence,
+ * this event will be delivered. This event will have
+ * DRM_XE_EUDEBUG_EVENT_NEED_ACK set in :c:member:`drm_xe_eudebug_event.flags`
+ * and upon receiving this event you need to ack it with
+ * DRM_XE_EUDEBUG_IOCTL_ACK_EVENT.
+ *
+ */
+struct drm_xe_eudebug_event_vm_bind_ufence {
+ /** @base: Base event */
+ struct drm_xe_eudebug_event base;
+
+ /** @vm_bind_ref_seqno: Parent :c:member:`drm_xe_eudebug_event_vm_bind.base.seqno` */
+ __u64 vm_bind_ref_seqno;
+};
+
+/**
+ * struct drm_xe_eudebug_ack - Deliver ack for an event
+ *
+ * If event base.flags has DRM_XE_EUDEBUG_EVENT_NEED_ACK set,
+ * then the associated resource processing is held for client and
+ * thus held for the debugger. In order to release the client,
+ * ack needs to be delivered with DRM_XE_EUDEBUG_IOCTL_ACK_EVENT.
+ */
+struct drm_xe_eudebug_ack {
+ /** @type: Type, must be zero */
+ __u32 type;
+
+ /** @flags: Flags, must be zero */
+ __u32 flags;
+
+ /** @seqno: Seqno of event that is to be acked */
+ __u64 seqno;
+};
+
#if defined(__cplusplus)
}
#endif
--
2.43.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 11/24] drm/xe/eudebug: vm open/pread/pwrite
2026-04-30 10:50 [PATCH 00/24] Intel Xe GPU Debug Support (eudebug) v8 Mika Kuoppala
` (9 preceding siblings ...)
2026-04-30 10:51 ` [PATCH 10/24] drm/xe/eudebug: Add ufence events with acks Mika Kuoppala
@ 2026-04-30 10:51 ` Mika Kuoppala
2026-04-30 10:51 ` [PATCH 12/24] drm/xe/eudebug: userptr vm pread/pwrite Mika Kuoppala
` (16 subsequent siblings)
27 siblings, 0 replies; 32+ messages in thread
From: Mika Kuoppala @ 2026-04-30 10:51 UTC (permalink / raw)
To: intel-xe
Cc: simona.vetter, matthew.brost, christian.koenig, thomas.hellstrom,
joonas.lahtinen, gustavo.sousa, jan.maslak,
dominik.karol.piatkowski, rodrigo.vivi, andrzej.hajda,
matthew.auld, maciej.patelczyk, gwan-gyeong.mun, Mika Kuoppala
Debugger needs access to the client's vm to read and write. For
example inspecting ISA/ELF and setting up breakpoints.
Add ioctl to open target vm with debugger client and vm_handle
and hook up pread/pwrite possibility.
Open will take timeout argument so that standard fsync
can be used for explicit flushing between cpu/gpu for
the target vm.
Implement this for bo backed storage. userptr will
be done in following patch.
v2: - checkpatch (Maciej)
- 32bit fixes (Andrzej)
- bo_vmap (Mika)
- fix vm leak if can't allocate k_buffer (Mika)
- assert vm write held for vma (Matthew)
v3: - fw ref, ttm_bo_access
- timeout boundary check (Dominik)
- dont try to copy to user on zero bytes (Mika)
v4: - offset as unsigned long (Thomas)
- check XE_VMA_DESTROYED
v5: - drm_dev_put before releasing debugger (Mika)
v6: - stop flushing on first error (Mika)
Cc: Matthew Brost <matthew.brost@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
Documentation/gpu/xe/xe_eudebug.rst | 6 +
drivers/gpu/drm/xe/Makefile | 2 +-
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 24 ++
drivers/gpu/drm/xe/xe_eudebug.c | 40 ++-
drivers/gpu/drm/xe/xe_eudebug.h | 12 +
drivers/gpu/drm/xe/xe_eudebug_types.h | 6 +
drivers/gpu/drm/xe/xe_eudebug_vm.c | 420 ++++++++++++++++++++++++++
drivers/gpu/drm/xe/xe_eudebug_vm.h | 8 +
include/uapi/drm/xe_drm_eudebug.h | 29 ++
9 files changed, 543 insertions(+), 4 deletions(-)
create mode 100644 drivers/gpu/drm/xe/xe_eudebug_vm.c
create mode 100644 drivers/gpu/drm/xe/xe_eudebug_vm.h
diff --git a/Documentation/gpu/xe/xe_eudebug.rst b/Documentation/gpu/xe/xe_eudebug.rst
index db52945714f3..466d366c1e83 100644
--- a/Documentation/gpu/xe/xe_eudebug.rst
+++ b/Documentation/gpu/xe/xe_eudebug.rst
@@ -66,3 +66,9 @@ Resource Event Types
.. kernel-doc:: include/uapi/drm/xe_drm_eudebug.h
:identifiers: drm_xe_eudebug_event_vm_bind_ufence
+
+VM Access
+=========
+
+.. kernel-doc:: include/uapi/drm/xe_drm_eudebug.h
+ :identifiers: drm_xe_eudebug_vm_open
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 97c721cd32aa..83e88d75c3e0 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -158,7 +158,7 @@ xe-$(CONFIG_DRM_XE_GPUSVM) += xe_svm.o
xe-$(CONFIG_DRM_GPUSVM) += xe_userptr.o
# debugging shaders with gdb (eudebug) support
-xe-$(CONFIG_DRM_XE_EUDEBUG) += xe_eudebug.o
+xe-$(CONFIG_DRM_XE_EUDEBUG) += xe_eudebug.o xe_eudebug_vm.o
# graphics hardware monitoring (HWMON) support
xe-$(CONFIG_HWMON) += xe_hwmon.o
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 16c87ce3f614..1787f4906775 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -614,6 +614,30 @@
#define CCS_MODE_CSLICE(cslice, ccs) \
((ccs) << ((cslice) * CCS_MODE_CSLICE_WIDTH))
+#define RCU_ASYNC_FLUSH XE_REG(0x149fc)
+#define RCU_ASYNC_FLUSH_IN_PROGRESS REG_BIT(31)
+#define RCU_ASYNC_FLUSH_ENGINE_ID_SHIFT 28
+#define RCU_ASYNC_FLUSH_ENGINE_ID_DECODE1 REG_BIT(26)
+#define RCU_ASYNC_FLUSH_AMFS REG_BIT(8)
+#define RCU_ASYNC_FLUSH_PREFETCH REG_BIT(7)
+#define RCU_ASYNC_FLUSH_DATA_PORT REG_BIT(6)
+#define RCU_ASYNC_FLUSH_DATA_CACHE REG_BIT(5)
+#define RCU_ASYNC_FLUSH_HDC_PIPELINE REG_BIT(4)
+#define RCU_ASYNC_INVALIDATE_HDC_PIPELINE REG_BIT(3)
+#define RCU_ASYNC_INVALIDATE_CONSTANT_CACHE REG_BIT(2)
+#define RCU_ASYNC_INVALIDATE_TEXTURE_CACHE REG_BIT(1)
+#define RCU_ASYNC_INVALIDATE_INSTRUCTION_CACHE REG_BIT(0)
+#define RCU_ASYNC_FLUSH_AND_INVALIDATE_ALL ( \
+ RCU_ASYNC_FLUSH_AMFS | \
+ RCU_ASYNC_FLUSH_PREFETCH | \
+ RCU_ASYNC_FLUSH_DATA_PORT | \
+ RCU_ASYNC_FLUSH_DATA_CACHE | \
+ RCU_ASYNC_FLUSH_HDC_PIPELINE | \
+ RCU_ASYNC_INVALIDATE_HDC_PIPELINE | \
+ RCU_ASYNC_INVALIDATE_CONSTANT_CACHE | \
+ RCU_ASYNC_INVALIDATE_TEXTURE_CACHE | \
+ RCU_ASYNC_INVALIDATE_INSTRUCTION_CACHE)
+
#define FORCEWAKE_ACK_GT XE_REG(0x130044)
/* Applicable for all FORCEWAKE_DOMAIN and FORCEWAKE_ACK_DOMAIN regs */
diff --git a/drivers/gpu/drm/xe/xe_eudebug.c b/drivers/gpu/drm/xe/xe_eudebug.c
index 14be97b5b4eb..0027dea2c396 100644
--- a/drivers/gpu/drm/xe/xe_eudebug.c
+++ b/drivers/gpu/drm/xe/xe_eudebug.c
@@ -16,6 +16,7 @@
#include "xe_device.h"
#include "xe_eudebug.h"
#include "xe_eudebug_types.h"
+#include "xe_eudebug_vm.h"
#include "xe_exec_queue.h"
#include "xe_hw_engine.h"
#include "xe_macros.h"
@@ -145,8 +146,7 @@ event_fifo_num_events_peek(const struct xe_eudebug * const d)
return kfifo_len(&d->events.fifo);
}
-static bool
-xe_eudebug_detached(struct xe_eudebug *d)
+bool xe_eudebug_detached(struct xe_eudebug *d)
{
return READ_ONCE(d->target.xef) == NULL;
}
@@ -265,7 +265,7 @@ static void xe_eudebug_free(struct kref *ref)
kfree(d);
}
-static void xe_eudebug_put(struct xe_eudebug *d)
+void xe_eudebug_put(struct xe_eudebug *d)
{
kref_put(&d->ref, xe_eudebug_free);
}
@@ -743,6 +743,34 @@ static int xe_eudebug_remove_handle(struct xe_eudebug *d, int type, void *p,
return ret;
}
+static void *find_resource__unlocked(struct xe_eudebug *d,
+ int type,
+ u32 id)
+{
+
+ struct xe_eudebug_resource *r;
+ struct xe_eudebug_handle *h;
+
+ r = resource_from_type(d, type);
+ h = xa_load(&r->xa, id);
+
+ return h ? (void *)(uintptr_t)h->key : NULL;
+}
+
+struct xe_vm *xe_eudebug_vm_get(struct xe_eudebug *d, u32 id)
+{
+ struct xe_vm *vm;
+
+ mutex_lock(&d->target.lock);
+ vm = find_resource__unlocked(d, XE_EUDEBUG_RES_TYPE_VM, id);
+ if (vm)
+ xe_vm_get(vm);
+ mutex_unlock(&d->target.lock);
+
+ return vm;
+}
+
+
static struct drm_xe_eudebug_event *
xe_eudebug_create_event(struct xe_eudebug *d, u16 type, u64 seqno, u16 flags,
u32 len)
@@ -1744,6 +1772,10 @@ static long xe_eudebug_ioctl(struct file *file,
ret = xe_eudebug_ack_event_ioctl(d, cmd, arg);
eu_dbg(d, "ioctl cmd=EVENT_ACK ret=%ld\n", ret);
break;
+ case DRM_XE_EUDEBUG_IOCTL_VM_OPEN:
+ ret = xe_eudebug_vm_open_ioctl(d, arg);
+ eu_dbg(d, "ioctl cmd=VM_OPEN ret=%ld\n", ret);
+ break;
default:
ret = -EINVAL;
}
@@ -1809,6 +1841,8 @@ xe_eudebug_connect(struct xe_device *xe,
spin_lock_init(&d->acks.lock);
d->acks.tree = RB_ROOT;
+ mutex_init(&d->hw.lock);
+
err = xe_eudebug_resources_init(d);
if (XE_IOCTL_DBG(xe, err))
goto err_free;
diff --git a/drivers/gpu/drm/xe/xe_eudebug.h b/drivers/gpu/drm/xe/xe_eudebug.h
index d0f1b51564dc..74171cc81fe1 100644
--- a/drivers/gpu/drm/xe/xe_eudebug.h
+++ b/drivers/gpu/drm/xe/xe_eudebug.h
@@ -18,6 +18,7 @@ struct xe_vma;
struct xe_vma_ops;
struct xe_exec_queue;
struct xe_user_fence;
+struct xe_eudebug;
#if IS_ENABLED(CONFIG_DRM_XE_EUDEBUG)
@@ -38,6 +39,10 @@ struct xe_user_fence;
#define xe_eudebug_assert(d, ...) xe_assert((d)->xe, ##__VA_ARGS__)
+#define xe_eudebug_for_each_hw_engine(__hwe, __gt, __id) \
+ for_each_hw_engine(__hwe, __gt, __id) \
+ if (xe_hw_engine_has_eudebug(__hwe))
+
int xe_eudebug_connect_ioctl(struct drm_device *dev,
void *data,
struct drm_file *file);
@@ -47,10 +52,15 @@ bool xe_eudebug_is_enabled(struct xe_device *xe);
void xe_eudebug_file_close(struct xe_file *xef);
+bool xe_eudebug_detached(struct xe_eudebug *d);
+
void xe_eudebug_vm_create(struct xe_file *xef, struct xe_vm *vm);
void xe_eudebug_vm_destroy(struct xe_file *xef, struct xe_vm *vm);
+
int xe_eudebug_enable(struct xe_device *xe, bool enable);
+struct xe_vm *xe_eudebug_vm_get(struct xe_eudebug *d, u32 vm_id);
+
void xe_eudebug_exec_queue_create(struct xe_file *xef, struct xe_exec_queue *q);
void xe_eudebug_exec_queue_destroy(struct xe_file *xef, struct xe_exec_queue *q);
@@ -60,6 +70,8 @@ void xe_eudebug_ufence_init(struct xe_user_fence *ufence);
void xe_eudebug_ufence_fini(struct xe_user_fence *ufence);
bool xe_eudebug_ufence_track(struct xe_user_fence *ufence);
+void xe_eudebug_put(struct xe_eudebug *d);
+
#else
static inline int xe_eudebug_connect_ioctl(struct drm_device *dev,
diff --git a/drivers/gpu/drm/xe/xe_eudebug_types.h b/drivers/gpu/drm/xe/xe_eudebug_types.h
index 0f18667a5ab8..10d19a43ba6b 100644
--- a/drivers/gpu/drm/xe/xe_eudebug_types.h
+++ b/drivers/gpu/drm/xe/xe_eudebug_types.h
@@ -133,6 +133,12 @@ struct xe_eudebug {
/** @tree: pending acks by seqnos */
struct rb_root tree;
} acks;
+
+ /** @hw: hw access */
+ struct {
+ /** @lock: guards access to hw state */
+ struct mutex lock;
+ } hw;
};
#endif /* _XE_EUDEBUG_TYPES_H_ */
diff --git a/drivers/gpu/drm/xe/xe_eudebug_vm.c b/drivers/gpu/drm/xe/xe_eudebug_vm.c
new file mode 100644
index 000000000000..dd75227555ee
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_eudebug_vm.c
@@ -0,0 +1,420 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2023-2025 Intel Corporation
+ */
+
+#include "xe_eudebug_vm.h"
+
+#include <linux/anon_inodes.h>
+#include <linux/fs.h>
+#include <linux/vmalloc.h>
+
+#include <drm/drm_drv.h>
+
+#include "xe_bo.h"
+#include "xe_device.h"
+#include "xe_eudebug.h"
+#include "xe_eudebug_types.h"
+#include "xe_force_wake.h"
+#include "xe_gt.h"
+#include "xe_mmio.h"
+#include "xe_vm.h"
+
+#include "regs/xe_gt_regs.h"
+#include "regs/xe_engine_regs.h"
+
+static int xe_eudebug_vma_access(struct xe_vma *vma,
+ unsigned long offset_in_vma,
+ void *buf, unsigned long len, bool write)
+{
+ struct xe_bo *bo;
+ u64 bytes;
+
+ lockdep_assert_held_write(&xe_vma_vm(vma)->lock);
+
+ if (XE_WARN_ON(offset_in_vma >= xe_vma_size(vma)))
+ return -EINVAL;
+
+ if (vma->gpuva.flags & XE_VMA_DESTROYED)
+ return -EINVAL;
+
+ bytes = min_t(u64, len, xe_vma_size(vma) - offset_in_vma);
+ if (!bytes)
+ return 0;
+
+ bo = xe_bo_get(xe_vma_bo(vma));
+ if (bo) {
+ int ret;
+
+ ret = ttm_bo_access(&bo->ttm, offset_in_vma, buf, bytes, write);
+
+ xe_bo_put(bo);
+
+ return ret;
+ }
+
+ return -EINVAL;
+}
+
+static int xe_eudebug_vm_access(struct xe_vm *vm, unsigned long offset,
+ void *buf, unsigned long len, bool write)
+{
+ struct xe_vma *vma;
+ int ret;
+
+ down_write(&vm->lock);
+
+ vma = xe_vm_find_overlapping_vma(vm, offset, len);
+ if (vma) {
+ /* XXX: why find overlapping returns below start? */
+ if (offset < xe_vma_start(vma) ||
+ offset >= (xe_vma_start(vma) + xe_vma_size(vma))) {
+ ret = -EINVAL;
+ goto out;
+ }
+
+ /* Offset into vma */
+ offset -= xe_vma_start(vma);
+ ret = xe_eudebug_vma_access(vma, offset, buf, len, write);
+ } else {
+ ret = -EINVAL;
+ }
+
+out:
+ up_write(&vm->lock);
+
+ return ret;
+}
+
+struct vm_file {
+ struct xe_eudebug *debugger;
+ struct xe_vm *vm;
+ u64 flags;
+ u64 vm_handle;
+ unsigned int timeout_us;
+};
+
+static ssize_t __vm_read_write(struct xe_vm *vm,
+ void *bb,
+ char __user *r_buffer,
+ const char __user *w_buffer,
+ unsigned long offset,
+ unsigned long len,
+ const bool write)
+{
+ ssize_t ret;
+
+ if (!len)
+ return 0;
+
+ if (write) {
+ ret = copy_from_user(bb, w_buffer, len);
+ if (ret)
+ return -EFAULT;
+
+ ret = xe_eudebug_vm_access(vm, offset, bb, len, true);
+ if (ret <= 0)
+ return ret;
+
+ len = ret;
+ } else {
+ ret = xe_eudebug_vm_access(vm, offset, bb, len, false);
+ if (ret <= 0)
+ return ret;
+
+ len = ret;
+
+ ret = copy_to_user(r_buffer, bb, len);
+ if (ret)
+ return -EFAULT;
+ }
+
+ return len;
+}
+
+static ssize_t __xe_eudebug_vm_access(struct file *file,
+ char __user *r_buffer,
+ const char __user *w_buffer,
+ size_t count, loff_t *__pos)
+{
+ struct vm_file *vmf = file->private_data;
+ struct xe_eudebug * const d = vmf->debugger;
+ struct xe_device * const xe = d->xe;
+ const bool write = !!w_buffer;
+ struct xe_vm *vm;
+ ssize_t copied = 0;
+ ssize_t bytes_left = count;
+ ssize_t ret;
+ unsigned long alloc_len;
+ loff_t pos = *__pos;
+ void *k_buffer;
+
+ if (XE_IOCTL_DBG(xe, write && r_buffer))
+ return -EINVAL;
+
+ vm = xe_eudebug_vm_get(d, vmf->vm_handle);
+ if (XE_IOCTL_DBG(xe, !vm))
+ return -EINVAL;
+
+ if (XE_IOCTL_DBG(xe, vm != vmf->vm)) {
+ eu_warn(d, "vm_access(%s): vm handle mismatch vm_handle=%llu, flags=0x%llx, pos=%llu, count=%zu\n",
+ write ? "write" : "read",
+ vmf->vm_handle, vmf->flags, pos, count);
+ xe_vm_put(vm);
+ return -EINVAL;
+ }
+
+ if (!count) {
+ xe_vm_put(vm);
+ return 0;
+ }
+
+ alloc_len = min_t(unsigned long, ALIGN(count, PAGE_SIZE), 64 * SZ_1M);
+ do {
+ k_buffer = vmalloc(alloc_len);
+ if (k_buffer)
+ break;
+
+ alloc_len >>= 1;
+ } while (alloc_len > PAGE_SIZE);
+
+ if (XE_IOCTL_DBG(xe, !k_buffer)) {
+ xe_vm_put(vm);
+ return -ENOMEM;
+ }
+
+ do {
+ const ssize_t len = min_t(ssize_t, bytes_left, alloc_len);
+
+ ret = __vm_read_write(vm, k_buffer,
+ write ? NULL : r_buffer + copied,
+ write ? w_buffer + copied : NULL,
+ pos + copied,
+ len,
+ write);
+ if (ret <= 0)
+ break;
+
+ bytes_left -= ret;
+ copied += ret;
+ } while (bytes_left > 0);
+
+ vfree(k_buffer);
+ xe_vm_put(vm);
+
+ if (XE_WARN_ON(copied < 0))
+ copied = 0;
+
+ *__pos += copied;
+
+ return copied ?: ret;
+}
+
+static ssize_t xe_eudebug_vm_read(struct file *file,
+ char __user *buffer,
+ size_t count, loff_t *pos)
+{
+ return __xe_eudebug_vm_access(file, buffer, NULL, count, pos);
+}
+
+static ssize_t xe_eudebug_vm_write(struct file *file,
+ const char __user *buffer,
+ size_t count, loff_t *pos)
+{
+ return __xe_eudebug_vm_access(file, NULL, buffer, count, pos);
+}
+
+static int engine_rcu_flush(struct xe_eudebug *d,
+ struct xe_hw_engine *hwe,
+ unsigned int timeout_us)
+{
+ const struct xe_reg psmi_addr = RING_PSMI_CTL(hwe->mmio_base);
+ struct xe_gt *gt = hwe->gt;
+ unsigned int fw_ref;
+ u32 mask = RCU_ASYNC_FLUSH_AND_INVALIDATE_ALL;
+ u32 psmi_ctrl;
+ u32 id;
+ int ret;
+
+ if (hwe->class == XE_ENGINE_CLASS_RENDER)
+ id = 0;
+ else if (hwe->class == XE_ENGINE_CLASS_COMPUTE)
+ id = hwe->instance + 1;
+ else
+ return -EINVAL;
+
+ if (id < 8)
+ mask |= id << RCU_ASYNC_FLUSH_ENGINE_ID_SHIFT;
+ else
+ mask |= (id - 8) << RCU_ASYNC_FLUSH_ENGINE_ID_SHIFT |
+ RCU_ASYNC_FLUSH_ENGINE_ID_DECODE1;
+
+ fw_ref = xe_force_wake_get(gt_to_fw(gt), hwe->domain);
+ if (!fw_ref)
+ return -ETIMEDOUT;
+
+ /* Prevent concurrent flushes */
+ mutex_lock(&d->hw.lock);
+ psmi_ctrl = xe_mmio_read32(>->mmio, psmi_addr);
+ if (!(psmi_ctrl & IDLE_MSG_DISABLE))
+ xe_mmio_write32(>->mmio, psmi_addr,
+ REG_MASKED_FIELD_ENABLE(IDLE_MSG_DISABLE));
+
+ /* XXX: Timeout is per operation but in here we flush previous */
+ ret = xe_mmio_wait32(>->mmio, RCU_ASYNC_FLUSH,
+ RCU_ASYNC_FLUSH_IN_PROGRESS, 0,
+ timeout_us, NULL, false);
+ if (ret)
+ goto out;
+
+ xe_mmio_write32(>->mmio, RCU_ASYNC_FLUSH, mask);
+
+ ret = xe_mmio_wait32(>->mmio, RCU_ASYNC_FLUSH,
+ RCU_ASYNC_FLUSH_IN_PROGRESS, 0,
+ timeout_us, NULL, false);
+out:
+ if (!(psmi_ctrl & IDLE_MSG_DISABLE))
+ xe_mmio_write32(>->mmio, psmi_addr,
+ REG_MASKED_FIELD_DISABLE(IDLE_MSG_DISABLE));
+
+ mutex_unlock(&d->hw.lock);
+ xe_force_wake_put(gt_to_fw(gt), fw_ref);
+
+ return ret;
+}
+
+static int xe_eudebug_vm_fsync(struct file *file, loff_t start, loff_t end, int datasync)
+{
+ struct vm_file *vmf = file->private_data;
+ struct xe_eudebug *d = vmf->debugger;
+ struct xe_gt *gt;
+ int gt_id;
+ int ret = -EINVAL;
+
+ eu_dbg(d, "vm_fsync: vm_handle=%llu, flags=0x%llx, start=%llu, end=%llu datasync=%d\n",
+ vmf->vm_handle, vmf->flags, start, end, datasync);
+
+ for_each_gt(gt, d->xe, gt_id) {
+ struct xe_hw_engine *hwe;
+ enum xe_hw_engine_id id;
+
+ /* XXX: vm open per engine? */
+ xe_eudebug_for_each_hw_engine(hwe, gt, id) {
+ ret = engine_rcu_flush(d, hwe, vmf->timeout_us);
+ if (ret)
+ goto out;
+ }
+ }
+out:
+ return ret;
+}
+
+static int xe_eudebug_vm_release(struct inode *inode, struct file *file)
+{
+ struct vm_file *vmf = file->private_data;
+ struct xe_eudebug *d = vmf->debugger;
+
+ eu_dbg(d, "vm_release: vm_handle=%llu, flags=0x%llx",
+ vmf->vm_handle, vmf->flags);
+
+ xe_vm_put(vmf->vm);
+ drm_dev_put(&d->xe->drm);
+ xe_eudebug_put(d);
+
+ kfree(vmf);
+
+ return 0;
+}
+
+static const struct file_operations vm_fops = {
+ .owner = THIS_MODULE,
+ .llseek = generic_file_llseek,
+ .read = xe_eudebug_vm_read,
+ .write = xe_eudebug_vm_write,
+ .fsync = xe_eudebug_vm_fsync,
+ .mmap = NULL,
+ .release = xe_eudebug_vm_release,
+};
+
+long xe_eudebug_vm_open_ioctl(struct xe_eudebug *d, unsigned long arg)
+{
+ struct drm_xe_eudebug_vm_open param;
+ struct xe_device * const xe = d->xe;
+ struct vm_file *vmf = NULL;
+ struct xe_vm *vm;
+ struct file *file;
+ long ret = 0;
+ int fd;
+
+ if (XE_IOCTL_DBG(xe, _IOC_SIZE(DRM_XE_EUDEBUG_IOCTL_VM_OPEN) != sizeof(param)))
+ return -EINVAL;
+
+ if (XE_IOCTL_DBG(xe, !(_IOC_DIR(DRM_XE_EUDEBUG_IOCTL_VM_OPEN) & _IOC_WRITE)))
+ return -EINVAL;
+
+ if (XE_IOCTL_DBG(xe, copy_from_user(¶m, (void __user *)arg, sizeof(param))))
+ return -EFAULT;
+
+ if (XE_IOCTL_DBG(xe, param.flags))
+ return -EINVAL;
+
+ if (XE_IOCTL_DBG(xe, xe_eudebug_detached(d)))
+ return -ENOTCONN;
+
+ vm = xe_eudebug_vm_get(d, param.vm_handle);
+ if (XE_IOCTL_DBG(xe, !vm))
+ return -EINVAL;
+
+ vmf = kzalloc_obj(*vmf, GFP_KERNEL);
+ if (XE_IOCTL_DBG(xe, !vmf)) {
+ ret = -ENOMEM;
+ goto out_vm_put;
+ }
+
+ fd = get_unused_fd_flags(O_CLOEXEC);
+ if (XE_IOCTL_DBG(xe, fd < 0)) {
+ ret = fd;
+ goto out_free;
+ }
+
+ kref_get(&d->ref);
+ vmf->debugger = d;
+ vmf->vm = vm;
+ vmf->flags = param.flags;
+ vmf->vm_handle = param.vm_handle;
+ vmf->timeout_us = div64_u64(param.timeout_ns, 1000ull);
+
+ file = anon_inode_getfile("[xe_eudebug.vm]", &vm_fops, vmf, O_RDWR);
+ if (IS_ERR(file)) {
+ ret = PTR_ERR(file);
+ XE_IOCTL_DBG(xe, ret);
+ file = NULL;
+ goto out_fd_put;
+ }
+
+ drm_dev_get(&xe->drm);
+
+ file->f_mode |= FMODE_PREAD | FMODE_PWRITE |
+ FMODE_READ | FMODE_WRITE | FMODE_LSEEK;
+
+ fd_install(fd, file);
+
+ eu_dbg(d, "vm_open: handle=%llu, flags=0x%llx, fd=%d",
+ vmf->vm_handle, vmf->flags, fd);
+
+ XE_WARN_ON(ret);
+
+ return fd;
+
+out_fd_put:
+ put_unused_fd(fd);
+ xe_eudebug_put(d);
+out_free:
+ kfree(vmf);
+out_vm_put:
+ xe_vm_put(vm);
+
+ XE_WARN_ON(ret >= 0);
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/xe/xe_eudebug_vm.h b/drivers/gpu/drm/xe/xe_eudebug_vm.h
new file mode 100644
index 000000000000..b3dc5618a5e6
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_eudebug_vm.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023-2025 Intel Corporation
+ */
+
+struct xe_eudebug;
+
+long xe_eudebug_vm_open_ioctl(struct xe_eudebug *d, unsigned long arg);
diff --git a/include/uapi/drm/xe_drm_eudebug.h b/include/uapi/drm/xe_drm_eudebug.h
index fb53174869ef..029a51340777 100644
--- a/include/uapi/drm/xe_drm_eudebug.h
+++ b/include/uapi/drm/xe_drm_eudebug.h
@@ -12,6 +12,7 @@ extern "C" {
#define DRM_XE_EUDEBUG_IOCTL_READ_EVENT _IO('j', 0x0)
#define DRM_XE_EUDEBUG_IOCTL_ACK_EVENT _IOW('j', 0x1, struct drm_xe_eudebug_ack)
+#define DRM_XE_EUDEBUG_IOCTL_VM_OPEN _IOW('j', 0x2, struct drm_xe_eudebug_vm_open)
/**
* struct drm_xe_eudebug_event - Base type of event delivered by xe_eudebug.
@@ -242,6 +243,34 @@ struct drm_xe_eudebug_ack {
__u64 seqno;
};
+/**
+ * struct drm_xe_eudebug_vm_open - Open a target vm
+ *
+ * Open target VM for reading and writing with DRM_XE_EUDEBUG_IOCTL_VM_OPEN.
+ *
+ * File descriptor is returned which can be used with pread and pwrite
+ * to inspect and modify the target VM.
+ *
+ * Multiple operations can be synced with calling fsync(fd). If
+ * timeout_ns was specified, the fsync will timeout if the
+ * VM can't be guaranteed to be in sync. Caller should re-read the
+ * state with pread again.
+ *
+ */
+struct drm_xe_eudebug_vm_open {
+ /** @extensions: Pointer to the first extension struct, if any */
+ __u64 extensions;
+
+ /** @vm_handle: handle of vm to be accessed */
+ __u64 vm_handle;
+
+ /** @flags: flags, must be zero */
+ __u64 flags;
+
+ /** @timeout_ns: Timeout value in nanoseconds */
+ __u64 timeout_ns;
+};
+
#if defined(__cplusplus)
}
#endif
--
2.43.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 12/24] drm/xe/eudebug: userptr vm pread/pwrite
2026-04-30 10:50 [PATCH 00/24] Intel Xe GPU Debug Support (eudebug) v8 Mika Kuoppala
` (10 preceding siblings ...)
2026-04-30 10:51 ` [PATCH 11/24] drm/xe/eudebug: vm open/pread/pwrite Mika Kuoppala
@ 2026-04-30 10:51 ` Mika Kuoppala
2026-04-30 10:51 ` [PATCH 13/24] drm/xe/eudebug: hw enablement for eudebug Mika Kuoppala
` (15 subsequent siblings)
27 siblings, 0 replies; 32+ messages in thread
From: Mika Kuoppala @ 2026-04-30 10:51 UTC (permalink / raw)
To: intel-xe
Cc: simona.vetter, matthew.brost, christian.koenig, thomas.hellstrom,
joonas.lahtinen, gustavo.sousa, jan.maslak,
dominik.karol.piatkowski, rodrigo.vivi, andrzej.hajda,
matthew.auld, maciej.patelczyk, gwan-gyeong.mun, Mika Kuoppala,
Simona Vetter, Dominik Grzegorzek
Implement debugger vm access for userptrs.
When bind is done, take ref to current task so that
we know from which vm the address was bound. Then during
debugger pread/pwrite we use this target task as
parameter to access the debuggee vm with access_process_vm().
This is based on suggestions from Simona, Thomas and Joonas.
v2: need to add offset into vma (Dominik)
v3: move code into xe_userptr.c (Mika)
Cc: Simona Vetter <simona@ffwll.ch>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Andrzej Hajda <andrzej.hajda@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Christian König <christian.koenig@amd.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/xe/xe_eudebug_vm.c | 16 +++++++++++++++
drivers/gpu/drm/xe/xe_userptr.c | 4 ++++
drivers/gpu/drm/xe/xe_userptr.h | 32 ++++++++++++++++++++++++++++++
3 files changed, 52 insertions(+)
diff --git a/drivers/gpu/drm/xe/xe_eudebug_vm.c b/drivers/gpu/drm/xe/xe_eudebug_vm.c
index dd75227555ee..8485397cf9c6 100644
--- a/drivers/gpu/drm/xe/xe_eudebug_vm.c
+++ b/drivers/gpu/drm/xe/xe_eudebug_vm.c
@@ -51,6 +51,22 @@ static int xe_eudebug_vma_access(struct xe_vma *vma,
xe_bo_put(bo);
return ret;
+ } else if (xe_vma_is_userptr(vma)) {
+ struct xe_userptr *userptr = &to_userptr_vma(vma)->userptr;
+
+ if (XE_WARN_ON(!userptr->eudebug.task))
+ return -EINVAL;
+
+ /*
+ * access_remote_vm() would fit as userptr notifier has
+ * mm ref so we would not need to carry task ref at all.
+ * But access_remote_vm is not exported. access_process_vm()
+ * is exported so use it instead.
+ */
+ return access_process_vm(userptr->eudebug.task,
+ xe_vma_userptr(vma) + offset_in_vma,
+ buf, bytes,
+ write ? FOLL_WRITE : 0);
}
return -EINVAL;
diff --git a/drivers/gpu/drm/xe/xe_userptr.c b/drivers/gpu/drm/xe/xe_userptr.c
index 6761005c0b90..ce7f30d2ccee 100644
--- a/drivers/gpu/drm/xe/xe_userptr.c
+++ b/drivers/gpu/drm/xe/xe_userptr.c
@@ -403,6 +403,8 @@ int xe_userptr_setup(struct xe_userptr_vma *uvma, unsigned long start,
userptr->pages.notifier_seq = LONG_MAX;
+ xe_eudebug_track_userptr_task(userptr);
+
return 0;
}
@@ -411,6 +413,8 @@ void xe_userptr_remove(struct xe_userptr_vma *uvma)
struct xe_vm *vm = xe_vma_vm(&uvma->vma);
struct xe_userptr *userptr = &uvma->userptr;
+ xe_eudebug_untrack_userptr_task(userptr);
+
drm_gpusvm_free_pages(&vm->svm.gpusvm, &uvma->userptr.pages,
xe_vma_size(&uvma->vma) >> PAGE_SHIFT);
diff --git a/drivers/gpu/drm/xe/xe_userptr.h b/drivers/gpu/drm/xe/xe_userptr.h
index 2a3cd1b5efbb..b0781618b3f4 100644
--- a/drivers/gpu/drm/xe/xe_userptr.h
+++ b/drivers/gpu/drm/xe/xe_userptr.h
@@ -95,6 +95,12 @@ struct xe_userptr {
#if IS_ENABLED(CONFIG_DRM_XE_USERPTR_INVAL_INJECT)
u32 divisor;
#endif
+
+#if IS_ENABLED(CONFIG_DRM_XE_EUDEBUG)
+ struct {
+ struct task_struct *task;
+ } eudebug;
+#endif
};
#if IS_ENABLED(CONFIG_DRM_GPUSVM)
@@ -133,4 +139,30 @@ static inline void xe_vma_userptr_force_invalidate(struct xe_userptr_vma *uvma)
{
}
#endif
+
+#if IS_ENABLED(CONFIG_DRM_XE_EUDEBUG)
+static inline void xe_eudebug_track_userptr_task(struct xe_userptr *userptr)
+{
+ /*
+ * We could use the mm which is on notifier. But
+ * the access_remote_vm() is not exported. Thus
+ * we get reference to task for access_process_vm()
+ */
+ userptr->eudebug.task = get_task_struct(current);
+}
+
+static inline void xe_eudebug_untrack_userptr_task(struct xe_userptr *userptr)
+{
+ put_task_struct(userptr->eudebug.task);
+}
+#else
+static inline void xe_eudebug_track_userptr_task(struct xe_userptr *userptr)
+{
+}
+
+static inline void xe_eudebug_untrack_userptr_task(struct xe_userptr *userptr)
+{
+}
+#endif /* CONFIG_DRM_XE_EUDEBUG */
+
#endif
--
2.43.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 13/24] drm/xe/eudebug: hw enablement for eudebug
2026-04-30 10:50 [PATCH 00/24] Intel Xe GPU Debug Support (eudebug) v8 Mika Kuoppala
` (11 preceding siblings ...)
2026-04-30 10:51 ` [PATCH 12/24] drm/xe/eudebug: userptr vm pread/pwrite Mika Kuoppala
@ 2026-04-30 10:51 ` Mika Kuoppala
2026-04-30 10:51 ` [PATCH 14/24] drm/xe/eudebug: Introduce EU control interface Mika Kuoppala
` (14 subsequent siblings)
27 siblings, 0 replies; 32+ messages in thread
From: Mika Kuoppala @ 2026-04-30 10:51 UTC (permalink / raw)
To: intel-xe
Cc: simona.vetter, matthew.brost, christian.koenig, thomas.hellstrom,
joonas.lahtinen, gustavo.sousa, jan.maslak,
dominik.karol.piatkowski, rodrigo.vivi, andrzej.hajda,
matthew.auld, maciej.patelczyk, gwan-gyeong.mun,
Dominik Grzegorzek, Mika Kuoppala
From: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
In order to turn on debug capabilities, (i.e. breakpoints), TD_CTL
and some other registers needs to be programmed. Implement eudebug
mode enabling including eudebug related workarounds.
v2: Move workarounds to xe_wa_oob. Use reg_sr directly instead of
xe_rtp as it suits better for dynamic manipulation of those register we
do later in the series.
v3: get rid of undefining XE_MCR_REG (Mika)
Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/xe/Makefile | 2 +-
drivers/gpu/drm/xe/regs/xe_engine_regs.h | 4 +
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 19 +++
drivers/gpu/drm/xe/xe_eudebug.c | 5 +-
drivers/gpu/drm/xe/xe_eudebug_hw.c | 72 +++++++++
drivers/gpu/drm/xe/xe_eudebug_hw.h | 25 ++++
drivers/gpu/drm/xe/xe_gt_debug.c | 179 +++++++++++++++++++++++
drivers/gpu/drm/xe/xe_gt_debug.h | 32 ++++
drivers/gpu/drm/xe/xe_reg_sr.c | 21 ++-
drivers/gpu/drm/xe/xe_reg_sr.h | 4 +-
drivers/gpu/drm/xe/xe_reg_whitelist.c | 2 +-
drivers/gpu/drm/xe/xe_rtp.c | 2 +-
drivers/gpu/drm/xe/xe_wa_oob.rules | 2 +
13 files changed, 357 insertions(+), 12 deletions(-)
create mode 100644 drivers/gpu/drm/xe/xe_eudebug_hw.c
create mode 100644 drivers/gpu/drm/xe/xe_eudebug_hw.h
create mode 100644 drivers/gpu/drm/xe/xe_gt_debug.c
create mode 100644 drivers/gpu/drm/xe/xe_gt_debug.h
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 83e88d75c3e0..1531ea9b3a93 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -158,7 +158,7 @@ xe-$(CONFIG_DRM_XE_GPUSVM) += xe_svm.o
xe-$(CONFIG_DRM_GPUSVM) += xe_userptr.o
# debugging shaders with gdb (eudebug) support
-xe-$(CONFIG_DRM_XE_EUDEBUG) += xe_eudebug.o xe_eudebug_vm.o
+xe-$(CONFIG_DRM_XE_EUDEBUG) += xe_eudebug.o xe_eudebug_vm.o xe_eudebug_hw.o xe_gt_debug.o
# graphics hardware monitoring (HWMON) support
xe-$(CONFIG_HWMON) += xe_hwmon.o
diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
index c4c879a9e555..9764a3359aad 100644
--- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
@@ -129,6 +129,10 @@
#define INDIRECT_RING_STATE(base) XE_REG((base) + 0x108)
+#define CS_DEBUG_MODE2(base) XE_REG((base) + 0xd8, XE_REG_OPTION_MASKED)
+#define INST_STATE_CACHE_INVALIDATE REG_BIT(6)
+#define GLOBAL_DEBUG_ENABLE REG_BIT(5)
+
#define RING_BBADDR(base) XE_REG((base) + 0x140)
#define RING_BBADDR_UDW(base) XE_REG((base) + 0x168)
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 1787f4906775..72a4697f56f7 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -513,10 +513,20 @@
#define DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA REG_BIT(15)
#define CLEAR_OPTIMIZATION_DISABLE REG_BIT(6)
+#define TD_CTL XE_REG_MCR(0xe400)
+#define TD_CTL_FEH_AND_FEE_ENABLE REG_BIT(7) /* forced halt and exception */
+#define TD_CTL_FORCE_EXTERNAL_HALT REG_BIT(6)
+#define TD_CTL_FORCE_THREAD_BREAKPOINT_ENABLE REG_BIT(4)
+#define TD_CTL_FORCE_EXCEPTION REG_BIT(3)
+#define TD_CTL_BREAKPOINT_ENABLE REG_BIT(2)
+#define TD_CTL_GLOBAL_DEBUG_ENABLE REG_BIT(0) /* XeHP */
+
#define CACHE_MODE_SS XE_REG_MCR(0xe420, XE_REG_OPTION_MASKED)
#define DISABLE_ECC REG_BIT(5)
#define ENABLE_PREFETCH_INTO_IC REG_BIT(3)
+#define EU_ATT(reg, row) XE_REG_MCR((reg ? 0xe478 : 0xe470) + (row) * 4)
+
#define ROW_CHICKEN4 XE_REG_MCR(0xe48c, XE_REG_OPTION_MASKED)
#define DISABLE_GRF_CLEAR REG_BIT(13)
#define XEHP_DIS_BBL_SYSPIPE REG_BIT(11)
@@ -526,6 +536,8 @@
#define THREAD_EX_ARB_MODE REG_GENMASK(3, 2)
#define THREAD_EX_ARB_MODE_RR_AFTER_DEP REG_FIELD_PREP(THREAD_EX_ARB_MODE, 0x2)
+#define EU_ATT_CLR(reg, row) XE_REG_MCR((reg ? 0xe698 : 0xe490) + (row) * 4)
+
#define ROW_CHICKEN3 XE_REG_MCR(0xe49c, XE_REG_OPTION_MASKED)
#define XE2_EUPEND_CHK_FLUSH_DIS REG_BIT(14)
#define DIS_EU_GRF_POISON_TO_LSC REG_BIT(13)
@@ -544,11 +556,13 @@
#define MDQ_ARBITRATION_MODE REG_BIT(12)
#define STALL_DOP_GATING_DISABLE REG_BIT(5)
#define EARLY_EOT_DIS REG_BIT(1)
+#define STALL_DOP_GATING_DISABLE REG_BIT(5)
#define ROW_CHICKEN2 XE_REG_MCR(0xe4f4, XE_REG_OPTION_MASKED)
#define DISABLE_READ_SUPPRESSION REG_BIT(15)
#define DISABLE_EARLY_READ REG_BIT(14)
#define ENABLE_LARGE_GRF_MODE REG_BIT(12)
+#define XEHPC_DISABLE_BTB REG_BIT(11)
#define PUSH_CONST_DEREF_HOLD_DIS REG_BIT(8)
#define DISABLE_TDL_SVHS_GATING REG_BIT(1)
#define DISABLE_DOP_GATING REG_BIT(0)
@@ -614,6 +628,11 @@
#define CCS_MODE_CSLICE(cslice, ccs) \
((ccs) << ((cslice) * CCS_MODE_CSLICE_WIDTH))
+#define RCU_DEBUG_1 XE_REG(0x14a00)
+#define RCU_DEBUG_1_ENGINE_STATUS REG_GENMASK(2, 0)
+#define RCU_DEBUG_1_RUNALONE_ACTIVE REG_BIT(2)
+#define RCU_DEBUG_1_CONTEXT_ACTIVE REG_BIT(0)
+
#define RCU_ASYNC_FLUSH XE_REG(0x149fc)
#define RCU_ASYNC_FLUSH_IN_PROGRESS REG_BIT(31)
#define RCU_ASYNC_FLUSH_ENGINE_ID_SHIFT 28
diff --git a/drivers/gpu/drm/xe/xe_eudebug.c b/drivers/gpu/drm/xe/xe_eudebug.c
index 0027dea2c396..0124efb37fde 100644
--- a/drivers/gpu/drm/xe/xe_eudebug.c
+++ b/drivers/gpu/drm/xe/xe_eudebug.c
@@ -257,6 +257,7 @@ static void xe_eudebug_free(struct kref *ref)
kfree(event);
xe_eudebug_resources_destroy(d);
+ mutex_destroy(&d->hw.lock);
mutex_destroy(&d->target.lock);
XE_WARN_ON(d->target.xef);
@@ -1830,6 +1831,7 @@ xe_eudebug_connect(struct xe_device *xe,
kref_init(&d->ref);
mutex_init(&d->target.lock);
+ mutex_init(&d->hw.lock);
init_waitqueue_head(&d->events.write_done);
init_waitqueue_head(&d->events.read_done);
init_completion(&d->discovery);
@@ -1841,8 +1843,6 @@ xe_eudebug_connect(struct xe_device *xe,
spin_lock_init(&d->acks.lock);
d->acks.tree = RB_ROOT;
- mutex_init(&d->hw.lock);
-
err = xe_eudebug_resources_init(d);
if (XE_IOCTL_DBG(xe, err))
goto err_free;
@@ -1879,6 +1879,7 @@ xe_eudebug_connect(struct xe_device *xe,
err_free_res:
xe_eudebug_resources_destroy(d);
err_free:
+ mutex_destroy(&d->hw.lock);
mutex_destroy(&d->target.lock);
kfree(d);
diff --git a/drivers/gpu/drm/xe/xe_eudebug_hw.c b/drivers/gpu/drm/xe/xe_eudebug_hw.c
new file mode 100644
index 000000000000..aa31b4c91713
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_eudebug_hw.c
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2023-2025 Intel Corporation
+ */
+
+#include "xe_eudebug_hw.h"
+
+#include <linux/delay.h>
+#include <linux/pm_runtime.h>
+#include <generated/xe_wa_oob.h>
+
+#include "regs/xe_gt_regs.h"
+#include "regs/xe_engine_regs.h"
+
+#include "xe_eudebug.h"
+#include "xe_eudebug_types.h"
+#include "xe_exec_queue.h"
+#include "xe_exec_queue_types.h"
+#include "xe_force_wake.h"
+#include "xe_gt.h"
+#include "xe_gt_debug.h"
+#include "xe_gt_mcr.h"
+#include "xe_hw_engine.h"
+#include "xe_lrc.h"
+#include "xe_macros.h"
+#include "xe_mmio.h"
+#include "xe_reg_sr.h"
+#include "xe_rtp.h"
+#include "xe_wa.h"
+
+static void add_sr_entry(struct xe_hw_engine *hwe,
+ struct xe_reg_mcr mcr_reg,
+ u32 mask, bool enable)
+{
+ const struct xe_reg_sr_entry sr_entry = {
+ .reg = mcr_reg.__reg,
+ .clr_bits = mask,
+ .set_bits = enable ? mask : 0,
+ .read_mask = mask,
+ };
+
+ xe_reg_sr_add(&hwe->reg_sr, &sr_entry, hwe->gt, true);
+}
+
+void xe_eudebug_init_hw_engine(struct xe_hw_engine *hwe, bool enable)
+{
+ struct xe_gt *gt = hwe->gt;
+ struct xe_device *xe = gt_to_xe(gt);
+
+ if (!xe_rtp_match_first_render_or_compute(xe, gt, hwe))
+ return;
+
+ if (XE_GT_WA(gt, 18022722726))
+ add_sr_entry(hwe, ROW_CHICKEN,
+ STALL_DOP_GATING_DISABLE, enable);
+
+ if (XE_GT_WA(gt, 14015474168))
+ add_sr_entry(hwe, ROW_CHICKEN2,
+ XEHPC_DISABLE_BTB,
+ enable);
+
+ if (xe->info.graphics_verx100 >= 1200)
+ add_sr_entry(hwe, TD_CTL,
+ TD_CTL_BREAKPOINT_ENABLE |
+ TD_CTL_FORCE_THREAD_BREAKPOINT_ENABLE |
+ TD_CTL_FEH_AND_FEE_ENABLE,
+ enable);
+
+ if (xe->info.graphics_verx100 >= 1250)
+ add_sr_entry(hwe, TD_CTL,
+ TD_CTL_GLOBAL_DEBUG_ENABLE, enable);
+}
diff --git a/drivers/gpu/drm/xe/xe_eudebug_hw.h b/drivers/gpu/drm/xe/xe_eudebug_hw.h
new file mode 100644
index 000000000000..7362ed9bde68
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_eudebug_hw.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023-2025 Intel Corporation
+ */
+
+#include <linux/types.h>
+
+#ifndef _XE_EUDEBUG_HW_H_
+#define _XE_EUDEBUG_HW_H_
+
+#include <linux/types.h>
+
+struct xe_eudebug;
+struct xe_hw_engine;
+struct xe_gt;
+
+#if IS_ENABLED(CONFIG_DRM_XE_EUDEBUG)
+
+void xe_eudebug_init_hw_engine(struct xe_hw_engine *hwe, bool enable);
+
+#else /* CONFIG_DRM_XE_EUDEBUG */
+
+#endif /* CONFIG_DRM_XE_EUDEBUG */
+
+#endif /* _XE_EUDEBUG_HW_H_ */
diff --git a/drivers/gpu/drm/xe/xe_gt_debug.c b/drivers/gpu/drm/xe/xe_gt_debug.c
new file mode 100644
index 000000000000..314eef6734c3
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_gt_debug.c
@@ -0,0 +1,179 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#include "regs/xe_gt_regs.h"
+#include "xe_device.h"
+#include "xe_force_wake.h"
+#include "xe_gt.h"
+#include "xe_gt_topology.h"
+#include "xe_gt_debug.h"
+#include "xe_gt_mcr.h"
+#include "xe_pm.h"
+#include "xe_macros.h"
+
+unsigned int xe_gt_eu_att_regs(struct xe_gt *gt)
+{
+ return (GRAPHICS_VERx100(gt_to_xe(gt)) >= 3000) ? 2u : 1u;
+}
+
+int xe_gt_foreach_dss_group_instance(struct xe_gt *gt,
+ int (*fn)(struct xe_gt *gt,
+ void *data,
+ u16 group,
+ u16 instance,
+ bool present),
+ void *data)
+{
+ const enum xe_force_wake_domains fw_domains = XE_FW_GT;
+ xe_dss_mask_t dss_mask;
+ unsigned int dss, fw_ref;
+ u16 group, instance;
+ int ret = 0;
+
+ fw_ref = xe_force_wake_get(gt_to_fw(gt), fw_domains);
+ if (!fw_ref)
+ return -ETIMEDOUT;
+
+ bitmap_or(dss_mask, gt->fuse_topo.g_dss_mask, gt->fuse_topo.c_dss_mask,
+ XE_MAX_DSS_FUSE_BITS);
+
+ /*
+ * Note: This removes terminating zeros when last dss is fused out!
+ * In order bitmask to be exactly the same as on with i915 we would
+ * need to figure out max dss for given platform, most probably by
+ * querying hwconfig
+ */
+
+ for (dss = 0;
+ dss <= find_last_bit(dss_mask, XE_MAX_DSS_FUSE_BITS);
+ dss++) {
+ xe_gt_mcr_get_dss_steering(gt, dss, &group, &instance);
+
+ ret = fn(gt, data, group, instance, test_bit(dss, dss_mask));
+ if (ret)
+ break;
+ }
+
+ xe_force_wake_put(gt_to_fw(gt), fw_ref);
+
+ return ret;
+}
+
+static int read_first_attention_mcr(struct xe_gt *gt, void *data,
+ u16 group, u16 instance, bool present)
+{
+ unsigned int reg, row;
+
+ if (!present)
+ return 0;
+
+ for (reg = 0; reg < xe_gt_eu_att_regs(gt); reg++) {
+ for (row = 0; row < XE_GT_EU_ATT_ROWS; row++) {
+ u32 val;
+
+ val = xe_gt_mcr_unicast_read(gt, EU_ATT(reg, row), group, instance);
+
+ if (val)
+ return 1;
+ }
+ }
+
+ return 0;
+}
+
+#define MAX_EUS_PER_ROW 4u
+#define MAX_THREADS 8u
+
+/**
+ * xe_gt_eu_attention_bitmap_size - query size of the attention bitmask
+ *
+ * @gt: pointer to struct xe_gt
+ *
+ * Return: size in bytes.
+ */
+int xe_gt_eu_attention_bitmap_size(struct xe_gt *gt)
+{
+ xe_dss_mask_t dss_mask;
+
+ bitmap_or(dss_mask, gt->fuse_topo.c_dss_mask,
+ gt->fuse_topo.g_dss_mask, XE_MAX_DSS_FUSE_BITS);
+
+ return (find_last_bit(dss_mask, XE_MAX_DSS_FUSE_BITS) + 1) *
+ XE_GT_EU_ATT_ROWS * xe_gt_eu_att_regs(gt) * MAX_THREADS *
+ MAX_EUS_PER_ROW / 8;
+}
+
+struct attn_read_iter {
+ struct xe_gt *gt;
+ unsigned int i;
+ unsigned int size;
+ u8 *bits;
+};
+
+static int read_eu_attentions_mcr(struct xe_gt *gt, void *data,
+ u16 group, u16 instance, bool present)
+{
+ struct attn_read_iter * const iter = data;
+ unsigned int reg, row;
+
+ for (reg = 0; reg < xe_gt_eu_att_regs(gt); reg++) {
+ for (row = 0; row < XE_GT_EU_ATT_ROWS; row++) {
+ u32 val;
+
+ if (iter->i >= iter->size)
+ return 0;
+
+ XE_WARN_ON(iter->i + sizeof(val) > xe_gt_eu_attention_bitmap_size(gt));
+
+ if (present)
+ val = xe_gt_mcr_unicast_read(gt, EU_ATT(reg, row), group, instance);
+ else
+ val = 0;
+
+ memcpy(&iter->bits[iter->i], &val, sizeof(val));
+ iter->i += sizeof(val);
+ }
+ }
+
+ return 0;
+}
+
+/**
+ * xe_gt_eu_attention_bitmap - query host attention
+ *
+ * @gt: pointer to struct xe_gt
+ *
+ * Return: 0 on success, negative otherwise.
+ */
+int xe_gt_eu_attention_bitmap(struct xe_gt *gt, u8 *bits,
+ unsigned int bitmap_size)
+{
+ struct attn_read_iter iter = {
+ .gt = gt,
+ .i = 0,
+ .size = bitmap_size,
+ .bits = bits
+ };
+
+ return xe_gt_foreach_dss_group_instance(gt, read_eu_attentions_mcr, &iter);
+}
+
+/**
+ * xe_gt_eu_threads_needing_attention - Query host attention
+ *
+ * @gt: pointer to struct xe_gt
+ *
+ * Return: 1 if threads waiting host attention, 0 otherwise.
+ */
+int xe_gt_eu_threads_needing_attention(struct xe_gt *gt)
+{
+ int err;
+
+ err = xe_gt_foreach_dss_group_instance(gt, read_first_attention_mcr, NULL);
+
+ XE_WARN_ON(err < 0);
+
+ return err < 0 ? 0 : err;
+}
diff --git a/drivers/gpu/drm/xe/xe_gt_debug.h b/drivers/gpu/drm/xe/xe_gt_debug.h
new file mode 100644
index 000000000000..9dabe9cc1d25
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_gt_debug.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#ifndef __XE_GT_DEBUG_
+#define __XE_GT_DEBUG_
+
+#include <linux/bits.h>
+#include <linux/math.h>
+
+struct xe_gt;
+
+#define XE_GT_ATTENTION_TIMEOUT_MS 100
+#define XE_GT_EU_ATT_ROWS 2u
+
+unsigned int xe_gt_eu_att_regs(struct xe_gt *gt);
+
+int xe_gt_eu_threads_needing_attention(struct xe_gt *gt);
+int xe_gt_foreach_dss_group_instance(struct xe_gt *gt,
+ int (*fn)(struct xe_gt *gt,
+ void *data,
+ u16 group,
+ u16 instance,
+ bool present),
+ void *data);
+
+int xe_gt_eu_attention_bitmap_size(struct xe_gt *gt);
+int xe_gt_eu_attention_bitmap(struct xe_gt *gt, u8 *bits,
+ unsigned int bitmap_size);
+
+#endif
diff --git a/drivers/gpu/drm/xe/xe_reg_sr.c b/drivers/gpu/drm/xe/xe_reg_sr.c
index 2df0277efb2f..2adda788deab 100644
--- a/drivers/gpu/drm/xe/xe_reg_sr.c
+++ b/drivers/gpu/drm/xe/xe_reg_sr.c
@@ -72,22 +72,31 @@ static void reg_sr_inc_error(struct xe_reg_sr *sr)
int xe_reg_sr_add(struct xe_reg_sr *sr,
const struct xe_reg_sr_entry *e,
- struct xe_gt *gt)
+ struct xe_gt *gt,
+ bool overwrite)
{
unsigned long idx = e->reg.addr;
struct xe_reg_sr_entry *pentry = xa_load(&sr->xa, idx);
int ret;
if (pentry) {
- if (!compatible_entries(pentry, e)) {
+ if (overwrite && e->set_bits) {
+ pentry->clr_bits |= e->clr_bits;
+ pentry->set_bits |= e->set_bits;
+ pentry->read_mask |= e->read_mask;
+ } else if (overwrite && !e->set_bits) {
+ pentry->clr_bits |= e->clr_bits;
+ pentry->set_bits &= ~e->clr_bits;
+ pentry->read_mask |= e->read_mask;
+ } else if (!compatible_entries(pentry, e)) {
ret = -EINVAL;
goto fail;
+ } else {
+ pentry->clr_bits |= e->clr_bits;
+ pentry->set_bits |= e->set_bits;
+ pentry->read_mask |= e->read_mask;
}
- pentry->clr_bits |= e->clr_bits;
- pentry->set_bits |= e->set_bits;
- pentry->read_mask |= e->read_mask;
-
return 0;
}
diff --git a/drivers/gpu/drm/xe/xe_reg_sr.h b/drivers/gpu/drm/xe/xe_reg_sr.h
index d26cf4713383..8231640edb0f 100644
--- a/drivers/gpu/drm/xe/xe_reg_sr.h
+++ b/drivers/gpu/drm/xe/xe_reg_sr.h
@@ -6,6 +6,8 @@
#ifndef _XE_REG_SR_H_
#define _XE_REG_SR_H_
+#include <linux/types.h>
+
/*
* Reg save/restore bookkeeping
*/
@@ -28,7 +30,7 @@ void xe_reg_sr_lrc_check(struct xe_reg_sr *sr,
struct drm_printer *p);
int xe_reg_sr_add(struct xe_reg_sr *sr, const struct xe_reg_sr_entry *e,
- struct xe_gt *gt);
+ struct xe_gt *gt, bool overwrite);
void xe_reg_sr_apply_mmio(struct xe_reg_sr *sr, struct xe_gt *gt);
void xe_reg_sr_apply_whitelist(struct xe_hw_engine *hwe);
diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
index 8cc313182968..95c0970d27a1 100644
--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
+++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
@@ -170,7 +170,7 @@ static void whitelist_apply_to_hwe(struct xe_hw_engine *hwe)
}
xe_reg_whitelist_print_entry(&p, 0, reg, entry);
- xe_reg_sr_add(&hwe->reg_sr, &hwe_entry, hwe->gt);
+ xe_reg_sr_add(&hwe->reg_sr, &hwe_entry, hwe->gt, false);
slot++;
}
diff --git a/drivers/gpu/drm/xe/xe_rtp.c b/drivers/gpu/drm/xe/xe_rtp.c
index 1a4dcbbbc176..32d089961cc7 100644
--- a/drivers/gpu/drm/xe/xe_rtp.c
+++ b/drivers/gpu/drm/xe/xe_rtp.c
@@ -185,7 +185,7 @@ static void rtp_add_sr_entry(const struct xe_rtp_action *action,
};
sr_entry.reg.addr += mmio_base;
- xe_reg_sr_add(sr, &sr_entry, gt);
+ xe_reg_sr_add(sr, &sr_entry, gt, false);
}
static bool rtp_process_one_sr(const struct xe_rtp_entry_sr *entry,
diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
index 445ba0d19051..1eef9b082fa3 100644
--- a/drivers/gpu/drm/xe/xe_wa_oob.rules
+++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
@@ -66,3 +66,5 @@
GRAPHICS_VERSION_RANGE(2004, 3005)
14022766366 GRAPHICS_VERSION_RANGE(2001, 2004)
GRAPHICS_VERSION_RANGE(3000, 3005)
+18022722726 GRAPHICS_VERSION_RANGE(1250, 1274)
+14015474168 PLATFORM(PVC)
--
2.43.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 14/24] drm/xe/eudebug: Introduce EU control interface
2026-04-30 10:50 [PATCH 00/24] Intel Xe GPU Debug Support (eudebug) v8 Mika Kuoppala
` (12 preceding siblings ...)
2026-04-30 10:51 ` [PATCH 13/24] drm/xe/eudebug: hw enablement for eudebug Mika Kuoppala
@ 2026-04-30 10:51 ` Mika Kuoppala
2026-04-30 10:51 ` [PATCH 15/24] drm/xe/eudebug: Introduce per device attention scan worker Mika Kuoppala
` (13 subsequent siblings)
27 siblings, 0 replies; 32+ messages in thread
From: Mika Kuoppala @ 2026-04-30 10:51 UTC (permalink / raw)
To: intel-xe
Cc: simona.vetter, matthew.brost, christian.koenig, thomas.hellstrom,
joonas.lahtinen, gustavo.sousa, jan.maslak,
dominik.karol.piatkowski, rodrigo.vivi, andrzej.hajda,
matthew.auld, maciej.patelczyk, gwan-gyeong.mun,
Dominik Grzegorzek, Mika Kuoppala, Christoph Manszewski
From: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Introduce EU control functionality, which allows EU debugger
to interrupt, resume, and inform about the current state of
EU threads during execution. Provide an abstraction layer,
so in the future guc will only need to provide appropriate callbacks.
Based on implementation created by authors and other folks within
i915 driver.
v2: - checkpatch (Maciej)
- lrc index off by one fix (Mika)
- checkpatch (Tilak)
- 32bit fixes (Andrzej, Mika)
- find_resource_get for client (Mika)
v3: - fw ref (Mika)
- attention register naming
v4: - fused off handling (Dominik)
- squash xe3 parts and ptl attentions (Mika)
v5: - s/ioctl_lock/exec_queue.lock to avoid wrong lock order (Mika)
v6: - require seqno MBZ (Mika)
v7: - error return consistency (Mika)
v8: - consolidate boilerplate and lrc sanity check (Mika)
Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Signed-off-by: Maciej Patelczyk <maciej.patelczyk@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Christoph Manszewski <christoph.manszewski@intel.com>
---
Documentation/gpu/xe/xe_eudebug.rst | 6 +
drivers/gpu/drm/xe/regs/xe_engine_regs.h | 1 +
drivers/gpu/drm/xe/xe_eudebug.c | 52 ++
drivers/gpu/drm/xe/xe_eudebug.h | 2 +
drivers/gpu/drm/xe/xe_eudebug_hw.c | 640 +++++++++++++++++++++++
drivers/gpu/drm/xe/xe_eudebug_hw.h | 7 +
drivers/gpu/drm/xe/xe_eudebug_types.h | 25 +
include/uapi/drm/xe_drm_eudebug.h | 58 ++
8 files changed, 791 insertions(+)
diff --git a/Documentation/gpu/xe/xe_eudebug.rst b/Documentation/gpu/xe/xe_eudebug.rst
index 466d366c1e83..76f255c7da73 100644
--- a/Documentation/gpu/xe/xe_eudebug.rst
+++ b/Documentation/gpu/xe/xe_eudebug.rst
@@ -72,3 +72,9 @@ VM Access
.. kernel-doc:: include/uapi/drm/xe_drm_eudebug.h
:identifiers: drm_xe_eudebug_vm_open
+
+EU/HW Control
+=============
+
+.. kernel-doc:: include/uapi/drm/xe_drm_eudebug.h
+ :identifiers: drm_xe_eudebug_eu_control
diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
index 9764a3359aad..e264bde909bc 100644
--- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
@@ -160,6 +160,7 @@
#define IDLE_DELAY REG_GENMASK(20, 0)
#define RING_CURRENT_LRCA(base) XE_REG((base) + 0x240)
+#define CURRENT_LRCA_VALID REG_BIT(0)
#define RING_CONTEXT_CONTROL(base) XE_REG((base) + 0x244, XE_REG_OPTION_MASKED)
#define CTX_CTRL_PXP_ENABLE REG_BIT(10)
diff --git a/drivers/gpu/drm/xe/xe_eudebug.c b/drivers/gpu/drm/xe/xe_eudebug.c
index 0124efb37fde..321012d2f6e8 100644
--- a/drivers/gpu/drm/xe/xe_eudebug.c
+++ b/drivers/gpu/drm/xe/xe_eudebug.c
@@ -15,11 +15,14 @@
#include "xe_debug_data_types.h"
#include "xe_device.h"
#include "xe_eudebug.h"
+#include "xe_eudebug_hw.h"
#include "xe_eudebug_types.h"
#include "xe_eudebug_vm.h"
#include "xe_exec_queue.h"
+#include "xe_gt.h"
#include "xe_hw_engine.h"
#include "xe_macros.h"
+#include "xe_pm.h"
#include "xe_sync.h"
#include "xe_vm.h"
@@ -771,6 +774,29 @@ struct xe_vm *xe_eudebug_vm_get(struct xe_eudebug *d, u32 id)
return vm;
}
+struct xe_exec_queue *xe_eudebug_exec_queue_get(struct xe_eudebug *d, u32 id)
+{
+ struct xe_exec_queue *q;
+
+ mutex_lock(&d->target.lock);
+ q = find_resource__unlocked(d, XE_EUDEBUG_RES_TYPE_EXEC_QUEUE, id);
+ if (q)
+ xe_exec_queue_get(q);
+ mutex_unlock(&d->target.lock);
+
+ return q;
+}
+
+struct xe_lrc *xe_eudebug_find_lrc(struct xe_eudebug *d, u32 id)
+{
+ struct xe_lrc *lrc;
+
+ mutex_lock(&d->target.lock);
+ lrc = find_resource__unlocked(d, XE_EUDEBUG_RES_TYPE_LRC, id);
+ mutex_unlock(&d->target.lock);
+
+ return lrc;
+}
static struct drm_xe_eudebug_event *
xe_eudebug_create_event(struct xe_eudebug *d, u16 type, u64 seqno, u16 flags,
@@ -1777,6 +1803,10 @@ static long xe_eudebug_ioctl(struct file *file,
ret = xe_eudebug_vm_open_ioctl(d, arg);
eu_dbg(d, "ioctl cmd=VM_OPEN ret=%ld\n", ret);
break;
+ case DRM_XE_EUDEBUG_IOCTL_EU_CONTROL:
+ ret = xe_eudebug_eu_control(d, arg);
+ eu_dbg(d, "ioctl cmd=EU_CONTROL ret=%ld\n", ret);
+ break;
default:
ret = -EINVAL;
}
@@ -1863,6 +1893,8 @@ xe_eudebug_connect(struct xe_device *xe,
goto err_fd;
}
+ xe_eudebug_hw_init(d);
+
fd_install(fd, file);
kref_get(&d->ref); /* for discovery */
@@ -1898,6 +1930,10 @@ bool xe_eudebug_is_enabled(struct xe_device *xe)
int xe_eudebug_enable(struct xe_device *xe, bool enable)
{
+ struct xe_gt *gt;
+ int i;
+ u8 id;
+
mutex_lock(&xe->eudebug.lock);
if (xe->eudebug.state == XE_EUDEBUG_NOT_SUPPORTED) {
@@ -1915,6 +1951,22 @@ int xe_eudebug_enable(struct xe_device *xe, bool enable)
return 0;
}
+ xe_pm_runtime_get(xe);
+
+ for_each_gt(gt, xe, id) {
+ for (i = 0; i < ARRAY_SIZE(gt->hw_engines); i++) {
+ if (!(gt->info.engine_mask & BIT(i)))
+ continue;
+
+ xe_eudebug_init_hw_engine(>->hw_engines[i], enable);
+ }
+
+ xe_gt_reset_async(gt);
+ flush_work(>->reset.worker);
+ }
+
+ xe_pm_runtime_put(xe);
+
xe->eudebug.state = enable ?
XE_EUDEBUG_ENABLED : XE_EUDEBUG_DISABLED;
mutex_unlock(&xe->eudebug.lock);
diff --git a/drivers/gpu/drm/xe/xe_eudebug.h b/drivers/gpu/drm/xe/xe_eudebug.h
index 74171cc81fe1..bd9fd7bf454f 100644
--- a/drivers/gpu/drm/xe/xe_eudebug.h
+++ b/drivers/gpu/drm/xe/xe_eudebug.h
@@ -63,6 +63,8 @@ struct xe_vm *xe_eudebug_vm_get(struct xe_eudebug *d, u32 vm_id);
void xe_eudebug_exec_queue_create(struct xe_file *xef, struct xe_exec_queue *q);
void xe_eudebug_exec_queue_destroy(struct xe_file *xef, struct xe_exec_queue *q);
+struct xe_exec_queue *xe_eudebug_exec_queue_get(struct xe_eudebug *d, u32 id);
+struct xe_lrc *xe_eudebug_find_lrc(struct xe_eudebug *d, u32 id);
void xe_eudebug_vm_bind_execute(struct xe_vm *vm, struct xe_vma_ops *ops);
diff --git a/drivers/gpu/drm/xe/xe_eudebug_hw.c b/drivers/gpu/drm/xe/xe_eudebug_hw.c
index aa31b4c91713..e6510e7b51a9 100644
--- a/drivers/gpu/drm/xe/xe_eudebug_hw.c
+++ b/drivers/gpu/drm/xe/xe_eudebug_hw.c
@@ -70,3 +70,643 @@ void xe_eudebug_init_hw_engine(struct xe_hw_engine *hwe, bool enable)
add_sr_entry(hwe, TD_CTL,
TD_CTL_GLOBAL_DEBUG_ENABLE, enable);
}
+
+static int read_hw_lrca_fw(struct xe_hw_engine *hwe, u32 *lrc_hw)
+{
+ u32 lrc_reg;
+
+ lrc_reg = xe_hw_engine_mmio_read32(hwe, RING_CURRENT_LRCA(0));
+
+ if (!(lrc_reg & CURRENT_LRCA_VALID))
+ return -ENOENT;
+
+ *lrc_hw = lrc_reg & GENMASK(31, 12);
+
+ return 0;
+}
+
+static int read_hw_lrca(struct xe_hw_engine *hwe, u32 *lrc_hw)
+{
+ unsigned int fw_ref;
+ int ret;
+
+ fw_ref = xe_force_wake_get(gt_to_fw(hwe->gt), hwe->domain);
+ if (!fw_ref)
+ return -ETIMEDOUT;
+
+ ret = read_hw_lrca_fw(hwe, lrc_hw);
+
+ xe_force_wake_put(gt_to_fw(hwe->gt), fw_ref);
+
+ return ret;
+}
+
+static bool lrca_equals(u32 a, u32 b)
+{
+ return (a & GENMASK(31, 12)) == (b & GENMASK(31, 12));
+}
+
+static int match_exec_queue_lrca(struct xe_exec_queue *q, u32 lrc_hw)
+{
+ int i;
+
+ for (i = 0; i < q->width; i++)
+ if (lrca_equals(lower_32_bits(xe_lrc_descriptor(q->lrc[i])), lrc_hw))
+ return i;
+
+ return -1;
+}
+
+static int rcu_debug1_engine_index(const struct xe_hw_engine * const hwe)
+{
+ if (hwe->class == XE_ENGINE_CLASS_RENDER) {
+ XE_WARN_ON(hwe->instance);
+ return 0;
+ }
+
+ XE_WARN_ON(hwe->instance > 3);
+
+ return hwe->instance + 1;
+}
+
+static u32 engine_status_xe1(const struct xe_hw_engine * const hwe,
+ u32 rcu_debug1)
+{
+ const unsigned int first = 7;
+ const unsigned int incr = 3;
+ const unsigned int i = rcu_debug1_engine_index(hwe);
+ const unsigned int shift = first + (i * incr);
+
+ return (rcu_debug1 >> shift) & RCU_DEBUG_1_ENGINE_STATUS;
+}
+
+static u32 engine_status_xe2(const struct xe_hw_engine * const hwe,
+ u32 rcu_debug1)
+{
+ const unsigned int first = 7;
+ const unsigned int incr = 4;
+ const unsigned int i = rcu_debug1_engine_index(hwe);
+ const unsigned int shift = first + (i * incr);
+
+ return (rcu_debug1 >> shift) & RCU_DEBUG_1_ENGINE_STATUS;
+}
+
+static u32 engine_status_xe3(const struct xe_hw_engine * const hwe,
+ u32 rcu_debug1)
+{
+ const unsigned int first = 6;
+ const unsigned int incr = 4;
+ const unsigned int i = rcu_debug1_engine_index(hwe);
+ const unsigned int shift = first + (i * incr);
+
+ return (rcu_debug1 >> shift) & RCU_DEBUG_1_ENGINE_STATUS;
+}
+
+static u32 engine_status(const struct xe_hw_engine * const hwe,
+ u32 rcu_debug1)
+{
+ u32 status = 0;
+
+ if (GRAPHICS_VER(gt_to_xe(hwe->gt)) < 20)
+ status = engine_status_xe1(hwe, rcu_debug1);
+ else if (GRAPHICS_VER(gt_to_xe(hwe->gt)) < 30)
+ status = engine_status_xe2(hwe, rcu_debug1);
+ else if (GRAPHICS_VER(gt_to_xe(hwe->gt)) < 35)
+ status = engine_status_xe3(hwe, rcu_debug1);
+ else
+ XE_WARN_ON(GRAPHICS_VER(gt_to_xe(hwe->gt)));
+
+ return status;
+}
+
+static bool engine_has_runalone_set(const struct xe_hw_engine * const hwe,
+ u32 rcu_debug1)
+{
+ return engine_status(hwe, rcu_debug1) & RCU_DEBUG_1_RUNALONE_ACTIVE;
+}
+
+static bool engine_has_context_set(const struct xe_hw_engine * const hwe,
+ u32 rcu_debug1)
+{
+ return engine_status(hwe, rcu_debug1) & RCU_DEBUG_1_CONTEXT_ACTIVE;
+}
+
+static struct xe_hw_engine *get_runalone_active_hw_engine(struct xe_gt *gt)
+{
+ struct xe_hw_engine *hwe, *first = NULL;
+ unsigned int num_active, id, fw_ref;
+ u32 val;
+
+ fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);
+ if (!fw_ref) {
+ drm_dbg(>_to_xe(gt)->drm, "eudbg: runalone failed to get force wake\n");
+ return ERR_PTR(-ETIMEDOUT);
+ }
+
+ val = xe_mmio_read32(>->mmio, RCU_DEBUG_1);
+ xe_force_wake_put(gt_to_fw(gt), fw_ref);
+
+ drm_dbg(>_to_xe(gt)->drm, "eudbg: runalone RCU_DEBUG_1 = 0x%08x\n", val);
+
+ num_active = 0;
+ xe_eudebug_for_each_hw_engine(hwe, gt, id) {
+ bool runalone, ctx;
+
+ runalone = engine_has_runalone_set(hwe, val);
+ ctx = engine_has_context_set(hwe, val);
+
+ drm_dbg(>_to_xe(gt)->drm, "eudbg: engine %s: runalone=%s, context=%s",
+ hwe->name, runalone ? "active" : "inactive",
+ ctx ? "active" : "inactive");
+
+ /*
+ * On earlier gen12 the context status seems to be idle when
+ * it has raised attention. We have to omit the active bit.
+ */
+ if (IS_DGFX(gt_to_xe(gt)))
+ ctx = true;
+
+ if (runalone && ctx) {
+ num_active++;
+
+ drm_dbg(>_to_xe(gt)->drm, "eudbg: runalone engine %s %s",
+ hwe->name, first ? "selected" : "found");
+ if (!first)
+ first = hwe;
+ }
+ }
+
+ if (num_active > 1)
+ drm_err(>_to_xe(gt)->drm, "eudbg: %d runalone engines active!",
+ num_active);
+
+ if (!first)
+ return ERR_PTR(-ENOENT);
+
+ return first;
+}
+
+static struct xe_exec_queue *active_hwe_to_exec_queue(struct xe_hw_engine *hwe,
+ int *lrc_idx)
+{
+ struct xe_device *xe = gt_to_xe(hwe->gt);
+ struct xe_gt *gt = hwe->gt;
+ struct xe_exec_queue *q, *found = NULL;
+ struct xe_file *xef;
+ unsigned long i;
+ int idx, err;
+ u32 lrc_hw;
+
+ err = read_hw_lrca(hwe, &lrc_hw);
+ if (err)
+ return ERR_PTR(err);
+
+ mutex_lock(&xe->eudebug.lock);
+ list_for_each_entry(xef, &xe->eudebug.targets, eudebug.target_link) {
+ mutex_lock(&xef->exec_queue.lock);
+ xa_for_each(&xef->exec_queue.xa, i, q) {
+ if (q->gt != gt)
+ continue;
+
+ if (q->class != hwe->class)
+ continue;
+
+ if (xe_exec_queue_is_idle(q))
+ continue;
+
+ idx = match_exec_queue_lrca(q, lrc_hw);
+ if (idx < 0)
+ continue;
+
+ found = xe_exec_queue_get(q);
+
+ if (lrc_idx)
+ *lrc_idx = idx;
+
+ break;
+ }
+ mutex_unlock(&xef->exec_queue.lock);
+
+ if (found)
+ break;
+ }
+ mutex_unlock(&xe->eudebug.lock);
+
+ if (!found)
+ return ERR_PTR(-ENOENT);
+
+ if (XE_WARN_ON(read_hw_lrca(hwe, &lrc_hw))) {
+ xe_exec_queue_put(found);
+ return ERR_PTR(-ENOENT);
+ }
+
+ if (XE_WARN_ON(match_exec_queue_lrca(found, lrc_hw) < 0)) {
+ xe_exec_queue_put(found);
+ return ERR_PTR(-ENOENT);
+ }
+
+ return found;
+}
+
+struct xe_exec_queue *
+xe_gt_runalone_active_queue_get(struct xe_gt *gt, int *lrc_idx)
+{
+ struct xe_hw_engine *active;
+
+ active = get_runalone_active_hw_engine(gt);
+ if (IS_ERR(active))
+ return ERR_CAST(active);
+
+ return active_hwe_to_exec_queue(active, lrc_idx);
+}
+
+static int check_lrc_sanity(const struct xe_exec_queue *q,
+ const struct xe_lrc *lrc,
+ const int lrc_idx)
+{
+ if (lrc_idx >= q->width)
+ return -EINVAL;
+
+ if (q->lrc[lrc_idx] != lrc)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int do_eu_control(struct xe_eudebug *d,
+ const struct drm_xe_eudebug_eu_control * const arg,
+ struct drm_xe_eudebug_eu_control __user * const user_ptr)
+{
+ void __user * const bitmask_ptr = u64_to_user_ptr(arg->bitmask_ptr);
+ struct xe_device *xe = d->xe;
+ struct xe_exec_queue *q, *active;
+ struct xe_lrc *lrc;
+ unsigned int hw_attn_size, attn_size;
+ u8 *bits = NULL;
+ u64 seqno;
+ int lrc_idx;
+ int ret;
+
+ if (xe_eudebug_detached(d))
+ return -ENOTCONN;
+
+ /* Accept only hardware reg granularity mask */
+ if (XE_IOCTL_DBG(xe, !IS_ALIGNED(arg->bitmask_size, sizeof(u32))))
+ return -EINVAL;
+
+ if (XE_IOCTL_DBG(xe, arg->seqno))
+ return -EINVAL;
+
+ q = xe_eudebug_exec_queue_get(d, arg->exec_queue_handle);
+ if (XE_IOCTL_DBG(xe, !q))
+ return -EINVAL;
+
+ if (XE_IOCTL_DBG(xe, !xe_exec_queue_is_debuggable(q))) {
+ ret = -EINVAL;
+ goto queue_put;
+ }
+
+ lrc = xe_eudebug_find_lrc(d, arg->lrc_handle);
+ if (XE_IOCTL_DBG(xe, !lrc)) {
+ ret = -EINVAL;
+ goto queue_put;
+ }
+
+ active = xe_gt_runalone_active_queue_get(q->gt, &lrc_idx);
+ if (XE_IOCTL_DBG(xe, IS_ERR(active))) {
+ ret = PTR_ERR(active);
+ goto queue_put;
+ }
+
+ ret = check_lrc_sanity(q, lrc, lrc_idx);
+ if (XE_IOCTL_DBG(xe, ret))
+ goto active_put;
+
+ if (XE_IOCTL_DBG(xe, q != active)) {
+ ret = -EBUSY;
+ goto active_put;
+ }
+
+ hw_attn_size = xe_gt_eu_attention_bitmap_size(q->gt);
+ attn_size = arg->bitmask_size;
+
+ if (attn_size > hw_attn_size)
+ attn_size = hw_attn_size;
+
+ if (attn_size > 0) {
+ bits = kmalloc(attn_size, GFP_KERNEL);
+ if (!bits) {
+ ret = -ENOMEM;
+ goto active_put;
+ }
+
+ if (copy_from_user(bits, bitmask_ptr, attn_size)) {
+ ret = -EFAULT;
+ goto out_free;
+ }
+ }
+
+ if (!pm_runtime_active(xe->drm.dev)) {
+ ret = -EIO;
+ goto out_free;
+ }
+
+ ret = -EINVAL;
+ mutex_lock(&d->hw.lock);
+
+ switch (arg->cmd) {
+ case DRM_XE_EUDEBUG_EU_CONTROL_CMD_INTERRUPT_ALL:
+ /* Make sure we dont promise anything but interrupting all */
+ if (!attn_size)
+ ret = d->ops->interrupt_all(d, active, lrc);
+ else
+ ret = -EINVAL;
+ break;
+ case DRM_XE_EUDEBUG_EU_CONTROL_CMD_STOPPED:
+ ret = d->ops->stopped(d, active, lrc, bits, attn_size);
+ break;
+ case DRM_XE_EUDEBUG_EU_CONTROL_CMD_RESUME:
+ ret = d->ops->resume(d, active, lrc, bits, attn_size);
+ break;
+ default:
+ break;
+ }
+
+ if (ret == 0)
+ seqno = atomic_long_inc_return(&d->events.seqno);
+
+ mutex_unlock(&d->hw.lock);
+
+ if (ret)
+ goto out_free;
+
+ if (put_user(seqno, &user_ptr->seqno)) {
+ ret = -EFAULT;
+ goto out_free;
+ }
+
+ if (copy_to_user(bitmask_ptr, bits, attn_size)) {
+ ret = -EFAULT;
+ goto out_free;
+ }
+
+ if (hw_attn_size != arg->bitmask_size)
+ if (put_user(hw_attn_size, &user_ptr->bitmask_size))
+ ret = -EFAULT;
+
+out_free:
+ kfree(bits);
+active_put:
+ xe_exec_queue_put(active);
+queue_put:
+ xe_exec_queue_put(q);
+
+ return ret;
+}
+
+static int xe_eu_control_interrupt_all(struct xe_eudebug *d,
+ struct xe_exec_queue *active,
+ struct xe_lrc *lrc)
+{
+ unsigned int fw_ref = 0;
+ u32 lrc_hw, lrc_hw_post;
+ u32 td_ctl;
+ int err = -EINVAL;
+
+ fw_ref = xe_force_wake_get(gt_to_fw(active->gt), active->hwe->domain);
+ if (!fw_ref) {
+ err = -ETIMEDOUT;
+ goto out;
+ }
+
+ /* Additional check just before issuing MMIO writes */
+ err = read_hw_lrca_fw(active->hwe, &lrc_hw);
+ if (err)
+ goto out;
+
+ if (!lrca_equals(lower_32_bits(xe_lrc_descriptor(lrc)), lrc_hw)) {
+ err = -EBUSY;
+ goto out;
+ }
+
+ td_ctl = xe_gt_mcr_unicast_read_any(active->gt, TD_CTL);
+
+ /* Halt on next thread dispatch */
+ if (!(td_ctl & TD_CTL_FORCE_EXTERNAL_HALT))
+ xe_gt_mcr_multicast_write(active->gt, TD_CTL,
+ td_ctl | TD_CTL_FORCE_EXTERNAL_HALT);
+ else
+ eu_warn(d, "TD_CTL force external halt bit already set!\n");
+
+ /*
+ * The sleep is needed because some interrupts are ignored
+ * by the HW, hence we allow the HW some time to acknowledge
+ * that.
+ */
+ usleep_range(100, 110);
+
+ /* Halt regardless of thread dependencies */
+ if (!(td_ctl & TD_CTL_FORCE_EXCEPTION))
+ xe_gt_mcr_multicast_write(active->gt, TD_CTL,
+ td_ctl | TD_CTL_FORCE_EXCEPTION);
+ else
+ eu_warn(d, "TD_CTL force exception bit already set!\n");
+
+ usleep_range(100, 110);
+
+ xe_gt_mcr_multicast_write(active->gt, TD_CTL, td_ctl &
+ ~(TD_CTL_FORCE_EXTERNAL_HALT | TD_CTL_FORCE_EXCEPTION));
+
+ /*
+ * In case of stopping wrong ctx emit warning.
+ * Nothing else we can do for now.
+ */
+ if (read_hw_lrca_fw(active->hwe, &lrc_hw_post) ||
+ !lrca_equals(lrc_hw, lrc_hw_post))
+ eu_warn(d, "xe_eudebug: interrupted wrong context 0x%08x, wanted 0x%08x",
+ lrc_hw_post, lrc_hw);
+
+out:
+ if (fw_ref)
+ xe_force_wake_put(gt_to_fw(active->gt), fw_ref);
+
+ return err;
+}
+
+struct ss_iter {
+ struct xe_eudebug *debugger;
+ unsigned int i;
+
+ unsigned int size;
+ u8 *bits;
+};
+
+static int check_attn_mcr(struct xe_gt *gt, void *data,
+ u16 group, u16 instance, bool present)
+{
+ struct ss_iter *iter = data;
+ struct xe_eudebug *d = iter->debugger;
+ unsigned int reg, row;
+
+ for (reg = 0; reg < xe_gt_eu_att_regs(gt); reg++) {
+ for (row = 0; row < XE_GT_EU_ATT_ROWS; row++) {
+ u32 val, cur = 0;
+
+ if (iter->i >= iter->size)
+ return 0;
+
+ if (XE_WARN_ON((iter->i + sizeof(val)) >
+ (xe_gt_eu_attention_bitmap_size(gt))))
+ return -EIO;
+
+ memcpy(&val, &iter->bits[iter->i], sizeof(val));
+ iter->i += sizeof(val);
+
+ if (present)
+ cur = xe_gt_mcr_unicast_read(gt, EU_ATT(reg, row), group, instance);
+
+ if ((val | cur) != cur) {
+ eu_dbg(d,
+ "WRONG CLEAR (%u:%u:%u:%u) EU_ATT_CLR: 0x%08x; EU_ATT: 0x%08x\n",
+ group, instance, reg, row, val, cur);
+ return -EINVAL;
+ }
+ }
+ }
+
+ return 0;
+}
+
+static int clear_attn_mcr(struct xe_gt *gt, void *data,
+ u16 group, u16 instance, bool present)
+{
+ struct ss_iter *iter = data;
+ struct xe_eudebug *d = iter->debugger;
+ unsigned int reg, row;
+
+ for (reg = 0; reg < xe_gt_eu_att_regs(gt); reg++) {
+ for (row = 0; row < XE_GT_EU_ATT_ROWS; row++) {
+ u32 val;
+
+ if (iter->i >= iter->size)
+ return 0;
+
+ if (XE_WARN_ON((iter->i + sizeof(val)) >
+ (xe_gt_eu_attention_bitmap_size(gt))))
+ return -EIO;
+
+ memcpy(&val, &iter->bits[iter->i], sizeof(val));
+ iter->i += sizeof(val);
+
+ if (!val)
+ continue;
+
+ if (present) {
+ xe_gt_mcr_unicast_write(gt, EU_ATT_CLR(reg, row), val,
+ group, instance);
+
+ eu_dbg(d,
+ "EU_ATT_CLR: (%u:%u:%u:%u): 0x%08x\n",
+ group, instance, reg, row, val);
+ } else {
+ eu_warn(d,
+ "EU_ATT_CLR: (%u:%u:%u:%u): 0x%08x to fused off dss\n",
+ group, instance, reg, row, val);
+ }
+ }
+ }
+
+ return 0;
+}
+
+static int xe_eu_control_resume(struct xe_eudebug *d,
+ struct xe_exec_queue *active,
+ struct xe_lrc *lrc,
+ u8 *bits, unsigned int bitmask_size)
+{
+ struct ss_iter iter = {
+ .debugger = d,
+ .i = 0,
+ .size = bitmask_size,
+ .bits = bits
+ };
+
+ /*
+ * hsdes: 18021122357
+ * We need to avoid clearing attention bits that are not set
+ * in order to avoid the EOT hang on PVC.
+ */
+ if (GRAPHICS_VERx100(d->xe) == 1260) {
+ int err;
+
+ err = xe_gt_foreach_dss_group_instance(active->gt, check_attn_mcr, &iter);
+ if (err)
+ return err;
+
+ iter.i = 0;
+ }
+
+ return xe_gt_foreach_dss_group_instance(active->gt, clear_attn_mcr, &iter);
+}
+
+static int xe_eu_control_stopped(struct xe_eudebug *d,
+ struct xe_exec_queue *active,
+ struct xe_lrc *lrc,
+ u8 *bits, unsigned int bitmask_size)
+{
+ return xe_gt_eu_attention_bitmap(active->gt, bits, bitmask_size);
+}
+
+static struct xe_eudebug_eu_control_ops eu_control = {
+ .interrupt_all = xe_eu_control_interrupt_all,
+ .stopped = xe_eu_control_stopped,
+ .resume = xe_eu_control_resume,
+};
+
+void xe_eudebug_hw_init(struct xe_eudebug *d)
+{
+ d->ops = &eu_control;
+}
+
+long xe_eudebug_eu_control(struct xe_eudebug *d, const u64 arg)
+{
+ struct drm_xe_eudebug_eu_control __user * const user_ptr =
+ u64_to_user_ptr(arg);
+ struct drm_xe_eudebug_eu_control user_arg;
+ struct xe_device *xe = d->xe;
+ int ret;
+
+ if (XE_IOCTL_DBG(xe, !(_IOC_DIR(DRM_XE_EUDEBUG_IOCTL_EU_CONTROL) & _IOC_WRITE)))
+ return -EINVAL;
+
+ if (XE_IOCTL_DBG(xe, !(_IOC_DIR(DRM_XE_EUDEBUG_IOCTL_EU_CONTROL) & _IOC_READ)))
+ return -EINVAL;
+
+ if (XE_IOCTL_DBG(xe, _IOC_SIZE(DRM_XE_EUDEBUG_IOCTL_EU_CONTROL) != sizeof(user_arg)))
+ return -EINVAL;
+
+ if (copy_from_user(&user_arg,
+ user_ptr,
+ sizeof(user_arg)))
+ return -EFAULT;
+
+ if (XE_IOCTL_DBG(xe, user_arg.flags))
+ return -EINVAL;
+
+ if (!access_ok(u64_to_user_ptr(user_arg.bitmask_ptr), user_arg.bitmask_size))
+ return -EFAULT;
+
+ eu_dbg(d,
+ "eu_control: cmd=%u, flags=0x%x, exec_queue_handle=%llu, bitmask_size=%u\n",
+ user_arg.cmd, user_arg.flags, user_arg.exec_queue_handle,
+ user_arg.bitmask_size);
+
+ ret = do_eu_control(d, &user_arg, user_ptr);
+
+ eu_dbg(d,
+ "eu_control: cmd=%u, flags=0x%x, exec_queue_handle=%llu, bitmask_size=%u ret=%d\n",
+ user_arg.cmd, user_arg.flags, user_arg.exec_queue_handle,
+ user_arg.bitmask_size, ret);
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/xe/xe_eudebug_hw.h b/drivers/gpu/drm/xe/xe_eudebug_hw.h
index 7362ed9bde68..8f59ec574e4e 100644
--- a/drivers/gpu/drm/xe/xe_eudebug_hw.h
+++ b/drivers/gpu/drm/xe/xe_eudebug_hw.h
@@ -16,10 +16,17 @@ struct xe_gt;
#if IS_ENABLED(CONFIG_DRM_XE_EUDEBUG)
+void xe_eudebug_hw_init(struct xe_eudebug *d);
void xe_eudebug_init_hw_engine(struct xe_hw_engine *hwe, bool enable);
+long xe_eudebug_eu_control(struct xe_eudebug *d, const u64 arg);
+
+struct xe_exec_queue *xe_gt_runalone_active_queue_get(struct xe_gt *gt, int *lrc_idx);
+
#else /* CONFIG_DRM_XE_EUDEBUG */
+static inline void xe_eudebug_init_hw_engine(struct xe_hw_engine *hwe, bool enable) { }
+
#endif /* CONFIG_DRM_XE_EUDEBUG */
#endif /* _XE_EUDEBUG_HW_H_ */
diff --git a/drivers/gpu/drm/xe/xe_eudebug_types.h b/drivers/gpu/drm/xe/xe_eudebug_types.h
index 10d19a43ba6b..57bd82a02ecb 100644
--- a/drivers/gpu/drm/xe/xe_eudebug_types.h
+++ b/drivers/gpu/drm/xe/xe_eudebug_types.h
@@ -17,7 +17,11 @@
struct xe_device;
struct task_struct;
+struct xe_eudebug;
+struct xe_hw_engine;
struct workqueue_struct;
+struct xe_exec_queue;
+struct xe_lrc;
/**
* enum xe_eudebug_state - eudebug capability state
@@ -65,6 +69,24 @@ struct xe_eudebug_resource {
#define XE_EUDEBUG_RES_TYPE_LRC 2
#define XE_EUDEBUG_RES_TYPE_COUNT (XE_EUDEBUG_RES_TYPE_LRC + 1)
+/**
+ * struct xe_eudebug_eu_control_ops - interface for eu thread
+ * state control backend
+ */
+struct xe_eudebug_eu_control_ops {
+ /** @interrupt_all: interrupts workload active on given hwe */
+ int (*interrupt_all)(struct xe_eudebug *e, struct xe_exec_queue *q,
+ struct xe_lrc *lrc);
+
+ /** @resume: resumes threads reflected by bitmask active on given hwe */
+ int (*resume)(struct xe_eudebug *e, struct xe_exec_queue *q,
+ struct xe_lrc *lrc, u8 *bitmap, unsigned int bitmap_size);
+
+ /** @stopped: returns bitmap reflecting threads which signal attention */
+ int (*stopped)(struct xe_eudebug *e, struct xe_exec_queue *q,
+ struct xe_lrc *lrc, u8 *bitmap, unsigned int bitmap_size);
+};
+
/**
* struct xe_eudebug - Top level struct for eudebug: the connection
*/
@@ -139,6 +161,9 @@ struct xe_eudebug {
/** @lock: guards access to hw state */
struct mutex lock;
} hw;
+
+ /** @ops: operations for eu_control */
+ struct xe_eudebug_eu_control_ops *ops;
};
#endif /* _XE_EUDEBUG_TYPES_H_ */
diff --git a/include/uapi/drm/xe_drm_eudebug.h b/include/uapi/drm/xe_drm_eudebug.h
index 029a51340777..6d69e100c965 100644
--- a/include/uapi/drm/xe_drm_eudebug.h
+++ b/include/uapi/drm/xe_drm_eudebug.h
@@ -13,6 +13,7 @@ extern "C" {
#define DRM_XE_EUDEBUG_IOCTL_READ_EVENT _IO('j', 0x0)
#define DRM_XE_EUDEBUG_IOCTL_ACK_EVENT _IOW('j', 0x1, struct drm_xe_eudebug_ack)
#define DRM_XE_EUDEBUG_IOCTL_VM_OPEN _IOW('j', 0x2, struct drm_xe_eudebug_vm_open)
+#define DRM_XE_EUDEBUG_IOCTL_EU_CONTROL _IOWR('j', 0x3, struct drm_xe_eudebug_eu_control)
/**
* struct drm_xe_eudebug_event - Base type of event delivered by xe_eudebug.
@@ -271,6 +272,63 @@ struct drm_xe_eudebug_vm_open {
__u64 timeout_ns;
};
+/**
+ * struct drm_xe_eudebug_eu_control - Control EU states
+ *
+ * Issue commands to execution units in hardware.
+ *
+ * With DRM_XE_EUDEBUG_IOCTL_EU_CONTROL debugger can
+ * interrupt all threads on execution units, query thread
+ * state and resume execution.
+ *
+ * :c:member:`drm_xe_eudebug_eu_control.seqno`
+ * will be updated to the timeline point when
+ * the command was issued.
+ *
+ * :c:member:`drm_xe_eudebug_eu_control.cmd` can
+ * be following:
+ *
+ * *DRM_XE_EUDEBUG_EU_CONTROL_CMD_INTERRUPT_ALL*
+ * will instruct hardware to stop all threads on EUs
+ * for exec_queue:lrc
+ *
+ * *DRM_XE_EUDEBUG_EU_CONTROL_CMD_STOPPED*
+ * returns the bitmask for threads that are
+ * in so called attention state.
+ *
+ * *DRM_XE_EUDEBUG_EU_CONTROL_CMD_RESUME* resumes the
+ * threads that the bitmask is set.
+ *
+ */
+struct drm_xe_eudebug_eu_control {
+ /** @cmd: Command for execution units */
+#define DRM_XE_EUDEBUG_EU_CONTROL_CMD_INTERRUPT_ALL 0
+#define DRM_XE_EUDEBUG_EU_CONTROL_CMD_STOPPED 1
+#define DRM_XE_EUDEBUG_EU_CONTROL_CMD_RESUME 2
+ __u32 cmd;
+
+ /** @flags: Flags, must be set to zero */
+ __u32 flags;
+
+ /** @seqno: Seqno, must be set to zero */
+ __u64 seqno;
+
+ /** @exec_queue_handle: Exec queue handle for the command */
+ __u64 exec_queue_handle;
+
+ /** @lrc_handle: LRC handle for the command */
+ __u64 lrc_handle;
+
+ /** @reserved: Reserved field, must be set to zero */
+ __u32 reserved;
+
+ /** @bitmask_size: Bitmask size in bytes */
+ __u32 bitmask_size;
+
+ /** @bitmask_ptr: Bitmask pointer, each bit is one thread */
+ __u64 bitmask_ptr;
+};
+
#if defined(__cplusplus)
}
#endif
--
2.43.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 15/24] drm/xe/eudebug: Introduce per device attention scan worker
2026-04-30 10:50 [PATCH 00/24] Intel Xe GPU Debug Support (eudebug) v8 Mika Kuoppala
` (13 preceding siblings ...)
2026-04-30 10:51 ` [PATCH 14/24] drm/xe/eudebug: Introduce EU control interface Mika Kuoppala
@ 2026-04-30 10:51 ` Mika Kuoppala
2026-04-30 10:51 ` [PATCH 16/24] drm/xe/eudebug_test: Introduce xe_eudebug wa kunit test Mika Kuoppala
` (12 subsequent siblings)
27 siblings, 0 replies; 32+ messages in thread
From: Mika Kuoppala @ 2026-04-30 10:51 UTC (permalink / raw)
To: intel-xe
Cc: simona.vetter, matthew.brost, christian.koenig, thomas.hellstrom,
joonas.lahtinen, gustavo.sousa, jan.maslak,
dominik.karol.piatkowski, rodrigo.vivi, andrzej.hajda,
matthew.auld, maciej.patelczyk, gwan-gyeong.mun,
Dominik Grzegorzek, Christoph Manszewski, Mika Kuoppala
From: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Scan for EU debugging attention bits periodically to detect if some EU
thread has entered the system routine (SIP) due to EU thread exception.
Make the scanning interval 10 times slower when there is no debugger
connection open. Send attention event whenever we see attention with
debugger presence. If there is no debugger connection active - reset.
Based on work by authors and other folks who were part of attentions in
i915.
v2: - use xa_array for files
- null ptr deref fix for non-debugged context (Dominik)
- checkpatch (Tilak)
- use discovery_lock during list traversal
v3: - engine status per gen improvements, force_wake ref
- __counted_by (Mika)
v4: - attention register naming (Dominik)
v5: - free event on error (Mika)
v6: - annotata data race on extending the poll interval (Mika)
Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Signed-off-by: Christoph Manszewski <christoph.manszewski@intel.com>
Signed-off-by: Maciej Patelczyk <maciej.patelczyk@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
Documentation/gpu/xe/xe_eudebug.rst | 3 +
drivers/gpu/drm/xe/xe_device_types.h | 3 +
drivers/gpu/drm/xe/xe_eudebug.c | 172 ++++++++++++++++++++++++++
drivers/gpu/drm/xe/xe_eudebug_types.h | 3 +-
include/uapi/drm/xe_drm_eudebug.h | 29 +++++
5 files changed, 208 insertions(+), 2 deletions(-)
diff --git a/Documentation/gpu/xe/xe_eudebug.rst b/Documentation/gpu/xe/xe_eudebug.rst
index 76f255c7da73..29f70b023326 100644
--- a/Documentation/gpu/xe/xe_eudebug.rst
+++ b/Documentation/gpu/xe/xe_eudebug.rst
@@ -67,6 +67,9 @@ Resource Event Types
.. kernel-doc:: include/uapi/drm/xe_drm_eudebug.h
:identifiers: drm_xe_eudebug_event_vm_bind_ufence
+.. kernel-doc:: include/uapi/drm/xe_drm_eudebug.h
+ :identifiers: drm_xe_eudebug_event_eu_attention
+
VM Access
=========
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index b72edf776f93..5d9569d5fd1a 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -587,6 +587,9 @@ struct xe_device {
/** @wq: used for client discovery */
struct workqueue_struct *wq;
+
+ /** @attention_poll: attention poll work */
+ struct delayed_work attention_dwork;
} eudebug;
#endif
};
diff --git a/drivers/gpu/drm/xe/xe_eudebug.c b/drivers/gpu/drm/xe/xe_eudebug.c
index 321012d2f6e8..2566b55f9c47 100644
--- a/drivers/gpu/drm/xe/xe_eudebug.c
+++ b/drivers/gpu/drm/xe/xe_eudebug.c
@@ -20,6 +20,7 @@
#include "xe_eudebug_vm.h"
#include "xe_exec_queue.h"
#include "xe_gt.h"
+#include "xe_gt_debug.h"
#include "xe_hw_engine.h"
#include "xe_macros.h"
#include "xe_pm.h"
@@ -1822,6 +1823,157 @@ static const struct file_operations fops = {
.unlocked_ioctl = xe_eudebug_ioctl,
};
+static int send_attention_event(struct xe_eudebug *d, struct xe_exec_queue *q, int lrc_idx)
+{
+ struct drm_xe_eudebug_event_eu_attention *e;
+ struct drm_xe_eudebug_event *event;
+ const u32 size = xe_gt_eu_attention_bitmap_size(q->gt);
+ const u32 sz = struct_size(e, bitmask, size);
+ int h_queue, h_lrc;
+ int ret;
+
+ XE_WARN_ON(lrc_idx < 0 || lrc_idx >= q->width);
+
+ XE_WARN_ON(!xe_exec_queue_is_debuggable(q));
+
+ h_queue = find_handle(d, XE_EUDEBUG_RES_TYPE_EXEC_QUEUE, q);
+ if (h_queue < 0)
+ return h_queue;
+
+ h_lrc = find_handle(d, XE_EUDEBUG_RES_TYPE_LRC, q->lrc[lrc_idx]);
+ if (h_lrc < 0)
+ return h_lrc;
+
+ event = xe_eudebug_create_event(d, DRM_XE_EUDEBUG_EVENT_EU_ATTENTION, 0,
+ DRM_XE_EUDEBUG_EVENT_STATE_CHANGE, sz);
+
+ if (!event)
+ return -ENOSPC;
+
+ e = cast_event(e, event);
+ e->exec_queue_handle = h_queue;
+ e->lrc_handle = h_lrc;
+ e->bitmask_size = size;
+
+ mutex_lock(&d->hw.lock);
+ event->seqno = atomic_long_inc_return(&d->events.seqno);
+ ret = xe_gt_eu_attention_bitmap(q->gt, &e->bitmask[0], e->bitmask_size);
+ mutex_unlock(&d->hw.lock);
+
+ if (ret) {
+ kfree(event);
+ return ret;
+ }
+
+ return xe_eudebug_queue_event(d, event);
+}
+
+static int xe_send_gt_attention(struct xe_gt *gt)
+{
+ struct xe_eudebug *d;
+ struct xe_exec_queue *q;
+ int ret, lrc_idx;
+
+ q = xe_gt_runalone_active_queue_get(gt, &lrc_idx);
+ if (IS_ERR(q))
+ return PTR_ERR(q);
+
+ if (!xe_exec_queue_is_debuggable(q)) {
+ ret = -EPERM;
+ goto err_exec_queue_put;
+ }
+
+ d = xe_eudebug_get_nolock(q->vm->xef);
+ if (!d) {
+ ret = -ENOTCONN;
+ goto err_exec_queue_put;
+ }
+
+ if (!completion_done(&d->discovery)) {
+ eu_dbg(d, "discovery not yet done\n");
+ ret = -EBUSY;
+ goto err_eudebug_put;
+ }
+
+ ret = send_attention_event(d, q, lrc_idx);
+ if (ret)
+ xe_eudebug_disconnect(d, ret);
+
+err_eudebug_put:
+ xe_eudebug_put(d);
+err_exec_queue_put:
+ xe_exec_queue_put(q);
+
+ return ret;
+}
+
+static int xe_eudebug_handle_gt_attention(struct xe_gt *gt)
+{
+ int ret;
+
+ ret = xe_gt_eu_threads_needing_attention(gt);
+ if (ret <= 0)
+ return ret;
+
+ ret = xe_send_gt_attention(gt);
+
+ /* Discovery in progress, fake it */
+ if (ret == -EBUSY)
+ return 0;
+
+ return ret;
+}
+
+static void attention_poll_work(struct work_struct *work)
+{
+ struct xe_device *xe = container_of(work, typeof(*xe),
+ eudebug.attention_dwork.work);
+ const unsigned int poll_interval_ms = 100;
+ long delay = msecs_to_jiffies(poll_interval_ms);
+ struct xe_gt *gt;
+ u8 gt_id;
+
+ /* Non critical if we get it wrong, just longer delay on race */
+ if (data_race(list_empty(&xe->eudebug.targets)))
+ delay *= 11;
+
+ if (delay >= HZ)
+ delay = round_jiffies_up_relative(delay);
+
+ if (xe_pm_runtime_get_if_active(xe)) {
+ for_each_gt(gt, xe, gt_id) {
+ int ret;
+
+ if (gt->info.type != XE_GT_TYPE_MAIN)
+ continue;
+
+ ret = xe_eudebug_handle_gt_attention(gt);
+ if (ret) {
+ /* TODO: error capture */
+ drm_info(>_to_xe(gt)->drm,
+ "gt:%d unable to handle eu attention ret=%d\n",
+ gt_id, ret);
+
+ xe_gt_reset_async(gt);
+ }
+ }
+
+ xe_pm_runtime_put(xe);
+ }
+
+ schedule_delayed_work(&xe->eudebug.attention_dwork, delay);
+}
+
+static void attention_poll_stop(struct xe_device *xe)
+{
+ cancel_delayed_work_sync(&xe->eudebug.attention_dwork);
+}
+
+static void attention_poll_start(struct xe_device *xe)
+{
+ mod_delayed_work(system_wq, &xe->eudebug.attention_dwork, 0);
+}
+
static int
xe_eudebug_connect(struct xe_device *xe,
struct drm_file *drm_file,
@@ -1899,6 +2051,7 @@ xe_eudebug_connect(struct xe_device *xe,
kref_get(&d->ref); /* for discovery */
queue_work(xe->eudebug.wq, &d->discovery_work);
+ attention_poll_start(xe);
eu_dbg(d, "connected session %lld", d->session);
@@ -1971,6 +2124,11 @@ int xe_eudebug_enable(struct xe_device *xe, bool enable)
XE_EUDEBUG_ENABLED : XE_EUDEBUG_DISABLED;
mutex_unlock(&xe->eudebug.lock);
+ if (enable)
+ attention_poll_start(xe);
+ else
+ attention_poll_stop(xe);
+
return 0;
}
@@ -2012,6 +2170,15 @@ static void xe_eudebug_sysfs_fini(void *arg)
&dev_attr_enable_eudebug.attr);
}
+static void xe_eudebug_fini(struct drm_device *dev, void *__unused)
+{
+ struct xe_device *xe = to_xe_device(dev);
+
+ xe_assert(xe, list_empty(&xe->eudebug.targets));
+
+ attention_poll_stop(xe);
+}
+
void xe_eudebug_init(struct xe_device *xe)
{
struct drm_device *dev = &xe->drm;
@@ -2019,6 +2186,7 @@ void xe_eudebug_init(struct xe_device *xe)
int err;
INIT_LIST_HEAD(&xe->eudebug.targets);
+ INIT_DELAYED_WORK(&xe->eudebug.attention_dwork, attention_poll_work);
xe->eudebug.state = XE_EUDEBUG_NOT_SUPPORTED;
@@ -2033,6 +2201,10 @@ void xe_eudebug_init(struct xe_device *xe)
}
xe->eudebug.wq = wq;
+ err = drmm_add_action_or_reset(&xe->drm, xe_eudebug_fini, NULL);
+ if (err)
+ goto out_err;
+
err = sysfs_create_file(&dev->dev->kobj,
&dev_attr_enable_eudebug.attr);
if (err)
diff --git a/drivers/gpu/drm/xe/xe_eudebug_types.h b/drivers/gpu/drm/xe/xe_eudebug_types.h
index 57bd82a02ecb..386b5c78ecff 100644
--- a/drivers/gpu/drm/xe/xe_eudebug_types.h
+++ b/drivers/gpu/drm/xe/xe_eudebug_types.h
@@ -37,7 +37,7 @@ enum xe_eudebug_state {
};
#define CONFIG_DRM_XE_DEBUGGER_EVENT_QUEUE_SIZE 64
-#define XE_EUDEBUG_MAX_EVENT_TYPE DRM_XE_EUDEBUG_EVENT_VM_BIND_UFENCE
+#define XE_EUDEBUG_MAX_EVENT_TYPE DRM_XE_EUDEBUG_EVENT_EU_ATTENTION
/**
* struct xe_eudebug_handle - eudebug resource handle
@@ -167,4 +167,3 @@ struct xe_eudebug {
};
#endif /* _XE_EUDEBUG_TYPES_H_ */
-
diff --git a/include/uapi/drm/xe_drm_eudebug.h b/include/uapi/drm/xe_drm_eudebug.h
index 6d69e100c965..54394a7e12ab 100644
--- a/include/uapi/drm/xe_drm_eudebug.h
+++ b/include/uapi/drm/xe_drm_eudebug.h
@@ -52,6 +52,7 @@ struct drm_xe_eudebug_event {
#define DRM_XE_EUDEBUG_EVENT_VM_BIND 4
#define DRM_XE_EUDEBUG_EVENT_VM_BIND_OP_DEBUG_DATA 5
#define DRM_XE_EUDEBUG_EVENT_VM_BIND_UFENCE 6
+#define DRM_XE_EUDEBUG_EVENT_EU_ATTENTION 7
/** @flags: Flags */
__u16 flags;
@@ -329,6 +330,34 @@ struct drm_xe_eudebug_eu_control {
__u64 bitmask_ptr;
};
+/**
+ * struct drm_xe_eudebug_event_eu_attention - EU Attention Event
+ *
+ * Whenever there is any thread in halted/attentions state, this
+ * event will be delivered. The event will be delivered periodically
+ * until there are no attentions detected.
+ *
+ */
+struct drm_xe_eudebug_event_eu_attention {
+ /** @base: base event */
+ struct drm_xe_eudebug_event base;
+
+ /** @exec_queue_handle: Exec queue handle for the attentions */
+ __u64 exec_queue_handle;
+
+ /** @lrc_handle: LRC handle for the attentions */
+ __u64 lrc_handle;
+
+ /** @flags: Flags */
+ __u32 flags;
+
+ /** @bitmask_size: Bitmask size in bytes for bitmask[] */
+ __u32 bitmask_size;
+
+ /** @bitmask: Attention bits, one per thread */
+ __u8 bitmask[];
+};
+
#if defined(__cplusplus)
}
#endif
--
2.43.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 16/24] drm/xe/eudebug_test: Introduce xe_eudebug wa kunit test
2026-04-30 10:50 [PATCH 00/24] Intel Xe GPU Debug Support (eudebug) v8 Mika Kuoppala
` (14 preceding siblings ...)
2026-04-30 10:51 ` [PATCH 15/24] drm/xe/eudebug: Introduce per device attention scan worker Mika Kuoppala
@ 2026-04-30 10:51 ` Mika Kuoppala
2026-04-30 14:16 ` Michal Wajdeczko
2026-04-30 10:51 ` [PATCH 17/24] drm/xe: Implement SR-IOV and eudebug exclusivity Mika Kuoppala
` (11 subsequent siblings)
27 siblings, 1 reply; 32+ messages in thread
From: Mika Kuoppala @ 2026-04-30 10:51 UTC (permalink / raw)
To: intel-xe
Cc: simona.vetter, matthew.brost, christian.koenig, thomas.hellstrom,
joonas.lahtinen, gustavo.sousa, jan.maslak,
dominik.karol.piatkowski, rodrigo.vivi, andrzej.hajda,
matthew.auld, maciej.patelczyk, gwan-gyeong.mun,
Christoph Manszewski, Mika Kuoppala
From: Christoph Manszewski <christoph.manszewski@intel.com>
Introduce kunit test for eudebug. For now it checks the dynamic
application of WAs.
v2: adapt to removal of call_for_each_device (Mika)
v3: s/FW_RENDER/FORCEWAKE_ALL (Mika)
Signed-off-by: Christoph Manszewski <christoph.manszewski@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/xe/tests/xe_eudebug.c | 183 ++++++++++++++++++++
drivers/gpu/drm/xe/tests/xe_live_test_mod.c | 5 +
drivers/gpu/drm/xe/xe_eudebug.c | 4 +
3 files changed, 192 insertions(+)
create mode 100644 drivers/gpu/drm/xe/tests/xe_eudebug.c
diff --git a/drivers/gpu/drm/xe/tests/xe_eudebug.c b/drivers/gpu/drm/xe/tests/xe_eudebug.c
new file mode 100644
index 000000000000..f839fb292b9b
--- /dev/null
+++ b/drivers/gpu/drm/xe/tests/xe_eudebug.c
@@ -0,0 +1,183 @@
+// SPDX-License-Identifier: GPL-2.0 AND MIT
+/*
+ * Copyright © 2024 Intel Corporation
+ */
+
+#include <kunit/visibility.h>
+
+#include "regs/xe_gt_regs.h"
+#include "regs/xe_engine_regs.h"
+
+#include "xe_force_wake.h"
+#include "xe_gt_mcr.h"
+#include "xe_mmio.h"
+
+#include "tests/xe_kunit_helpers.h"
+#include "tests/xe_pci_test.h"
+#include "tests/xe_test.h"
+
+#undef XE_REG_MCR
+#define XE_REG_MCR(r_, ...) ((const struct xe_reg_mcr){ \
+ .__reg = XE_REG_INITIALIZER(r_, ##__VA_ARGS__, .mcr = 1) \
+ })
+
+static const char *reg_to_str(struct xe_reg reg)
+{
+ if (reg.raw == TD_CTL.__reg.raw)
+ return "TD_CTL";
+ else if (reg.raw == CS_DEBUG_MODE2(RENDER_RING_BASE).raw)
+ return "CS_DEBUG_MODE2";
+ else if (reg.raw == ROW_CHICKEN.__reg.raw)
+ return "ROW_CHICKEN";
+ else if (reg.raw == ROW_CHICKEN2.__reg.raw)
+ return "ROW_CHICKEN2";
+ else if (reg.raw == ROW_CHICKEN3.__reg.raw)
+ return "ROW_CHICKEN3";
+ else
+ return "UNKNOWN REG";
+}
+
+static u32 get_reg_mask(struct xe_device *xe, struct xe_reg reg)
+{
+ struct kunit *test = kunit_get_current_test();
+ u32 val = 0;
+
+ if (reg.raw == TD_CTL.__reg.raw) {
+ val = TD_CTL_BREAKPOINT_ENABLE |
+ TD_CTL_FORCE_THREAD_BREAKPOINT_ENABLE |
+ TD_CTL_FEH_AND_FEE_ENABLE;
+
+ if (GRAPHICS_VERx100(xe) >= 1250)
+ val |= TD_CTL_GLOBAL_DEBUG_ENABLE;
+
+ } else if (reg.raw == CS_DEBUG_MODE2(RENDER_RING_BASE).raw) {
+ val = GLOBAL_DEBUG_ENABLE;
+ } else if (reg.raw == ROW_CHICKEN.__reg.raw) {
+ val = STALL_DOP_GATING_DISABLE;
+ } else if (reg.raw == ROW_CHICKEN2.__reg.raw) {
+ val = XEHPC_DISABLE_BTB;
+ } else if (reg.raw == ROW_CHICKEN3.__reg.raw) {
+ val = XE2_EUPEND_CHK_FLUSH_DIS;
+ } else {
+ kunit_warn(test, "Invalid register selection: %u\n", reg.raw);
+ }
+
+ return val;
+}
+
+static u32 get_reg_expected(struct xe_device *xe, struct xe_reg reg, bool enable_eudebug)
+{
+ u32 reg_mask = get_reg_mask(xe, reg);
+ u32 reg_bits = 0;
+
+ if (enable_eudebug || reg.raw == ROW_CHICKEN3.__reg.raw)
+ reg_bits = reg_mask;
+ else
+ reg_bits = 0;
+
+ return reg_bits;
+}
+
+static void check_reg(struct xe_gt *gt, bool enable_eudebug, struct xe_reg reg)
+{
+ struct kunit *test = kunit_get_current_test();
+ struct xe_device *xe = gt_to_xe(gt);
+ u32 reg_bits_expected = get_reg_expected(xe, reg, enable_eudebug);
+ u32 reg_mask = get_reg_mask(xe, reg);
+ u32 reg_bits = 0;
+
+ if (reg.mcr)
+ reg_bits = xe_gt_mcr_unicast_read_any(gt, (struct xe_reg_mcr){.__reg = reg});
+ else
+ reg_bits = xe_mmio_read32(>->mmio, reg);
+
+ reg_bits &= reg_mask;
+
+ kunit_printk(KERN_DEBUG, test, "%s bits: expected == 0x%x; actual == 0x%x\n",
+ reg_to_str(reg), reg_bits_expected, reg_bits);
+ KUNIT_EXPECT_EQ_MSG(test, reg_bits_expected, reg_bits,
+ "Invalid bits set for %s\n", reg_to_str(reg));
+}
+
+static void __check_regs(struct xe_gt *gt, bool enable_eudebug)
+{
+ struct xe_device *xe = gt_to_xe(gt);
+
+ if (GRAPHICS_VERx100(xe) >= 1200)
+ check_reg(gt, enable_eudebug, TD_CTL.__reg);
+
+ if (GRAPHICS_VERx100(xe) >= 1250 && GRAPHICS_VERx100(xe) <= 1274)
+ check_reg(gt, enable_eudebug, ROW_CHICKEN.__reg);
+
+ if (xe->info.platform == XE_PVC)
+ check_reg(gt, enable_eudebug, ROW_CHICKEN2.__reg);
+
+ if (GRAPHICS_VERx100(xe) >= 2000 && GRAPHICS_VERx100(xe) <= 2004)
+ check_reg(gt, enable_eudebug, ROW_CHICKEN3.__reg);
+}
+
+static void check_regs(struct xe_device *xe, bool enable_eudebug)
+{
+ struct kunit *test = kunit_get_current_test();
+ struct xe_gt *gt;
+ unsigned int fw_ref;
+ u8 id;
+
+ kunit_printk(KERN_DEBUG, test, "Check regs for eudebug %s\n",
+ enable_eudebug ? "enabled" : "disabled");
+
+ xe_pm_runtime_get(xe);
+ for_each_gt(gt, xe, id) {
+ if (xe_gt_is_media_type(gt))
+ continue;
+
+ /* XXX: Figure out per platform proper domain */
+ fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL);
+ KUNIT_ASSERT_TRUE_MSG(test, fw_ref, "Forcewake failed.\n");
+
+ __check_regs(gt, enable_eudebug);
+
+ xe_force_wake_put(gt_to_fw(gt), fw_ref);
+ }
+ xe_pm_runtime_put(xe);
+}
+
+static int toggle_reg_value(struct xe_device *xe)
+{
+ struct kunit *test = kunit_get_current_test();
+ bool enable_eudebug = xe_eudebug_is_enabled(xe);
+
+ kunit_printk(KERN_DEBUG, test, "Test eudebug WAs for graphics version: %u\n",
+ GRAPHICS_VERx100(xe));
+
+ check_regs(xe, enable_eudebug);
+
+ xe_eudebug_enable(xe, !enable_eudebug);
+ check_regs(xe, !enable_eudebug);
+
+ xe_eudebug_enable(xe, enable_eudebug);
+ check_regs(xe, enable_eudebug);
+
+ return 0;
+}
+
+static void xe_eudebug_toggle_reg_kunit(struct kunit *test)
+{
+ struct xe_device *xe = test->priv;
+
+ toggle_reg_value(xe);
+}
+
+static struct kunit_case xe_eudebug_tests[] = {
+ KUNIT_CASE_PARAM(xe_eudebug_toggle_reg_kunit,
+ xe_pci_live_device_gen_param),
+ {}
+};
+
+VISIBLE_IF_KUNIT
+struct kunit_suite xe_eudebug_test_suite = {
+ .name = "xe_eudebug",
+ .test_cases = xe_eudebug_tests,
+ .init = xe_kunit_helper_xe_device_live_test_init,
+};
+EXPORT_SYMBOL_IF_KUNIT(xe_eudebug_test_suite);
diff --git a/drivers/gpu/drm/xe/tests/xe_live_test_mod.c b/drivers/gpu/drm/xe/tests/xe_live_test_mod.c
index c55e46f1ae92..dc83bb6a892d 100644
--- a/drivers/gpu/drm/xe/tests/xe_live_test_mod.c
+++ b/drivers/gpu/drm/xe/tests/xe_live_test_mod.c
@@ -19,6 +19,11 @@ kunit_test_suite(xe_migrate_test_suite);
kunit_test_suite(xe_mocs_test_suite);
kunit_test_suite(xe_guc_g2g_test_suite);
+#if IS_ENABLED(CONFIG_DRM_XE_EUDEBUG)
+extern struct kunit_suite xe_eudebug_test_suite;
+kunit_test_suite(xe_eudebug_test_suite);
+#endif
+
MODULE_AUTHOR("Intel Corporation");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("xe live kunit tests");
diff --git a/drivers/gpu/drm/xe/xe_eudebug.c b/drivers/gpu/drm/xe/xe_eudebug.c
index 2566b55f9c47..f5547c756b31 100644
--- a/drivers/gpu/drm/xe/xe_eudebug.c
+++ b/drivers/gpu/drm/xe/xe_eudebug.c
@@ -2242,3 +2242,7 @@ int xe_eudebug_connect_ioctl(struct drm_device *dev,
return xe_eudebug_connect(xe, file, param);
}
+
+#if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)
+#include "tests/xe_eudebug.c"
+#endif
--
2.43.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* Re: [PATCH 16/24] drm/xe/eudebug_test: Introduce xe_eudebug wa kunit test
2026-04-30 10:51 ` [PATCH 16/24] drm/xe/eudebug_test: Introduce xe_eudebug wa kunit test Mika Kuoppala
@ 2026-04-30 14:16 ` Michal Wajdeczko
0 siblings, 0 replies; 32+ messages in thread
From: Michal Wajdeczko @ 2026-04-30 14:16 UTC (permalink / raw)
To: Mika Kuoppala, intel-xe
Cc: simona.vetter, matthew.brost, christian.koenig, thomas.hellstrom,
joonas.lahtinen, gustavo.sousa, jan.maslak,
dominik.karol.piatkowski, rodrigo.vivi, andrzej.hajda,
matthew.auld, maciej.patelczyk, gwan-gyeong.mun,
Christoph Manszewski
Hi Mika,
few nits below...
nit: maybe title should be:
drm/xe/tests: Introduce eudebug live tests
On 4/30/2026 12:51 PM, Mika Kuoppala wrote:
> From: Christoph Manszewski <christoph.manszewski@intel.com>
>
> Introduce kunit test for eudebug. For now it checks the dynamic
> application of WAs.
>
> v2: adapt to removal of call_for_each_device (Mika)
> v3: s/FW_RENDER/FORCEWAKE_ALL (Mika)
>
> Signed-off-by: Christoph Manszewski <christoph.manszewski@intel.com>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/xe/tests/xe_eudebug.c | 183 ++++++++++++++++++++
nit: while we are still inconsistent in file naming,
maybe we should follow some rules and
- use _kunit file suffix for pure KUnit tests
- use _test file suffix for our live tests (not strictly kunit)
see https://docs.kernel.org/dev-tools/kunit/style.html#test-file-and-module-names
> drivers/gpu/drm/xe/tests/xe_live_test_mod.c | 5 +
> drivers/gpu/drm/xe/xe_eudebug.c | 4 +
> 3 files changed, 192 insertions(+)
> create mode 100644 drivers/gpu/drm/xe/tests/xe_eudebug.c
>
> diff --git a/drivers/gpu/drm/xe/tests/xe_eudebug.c b/drivers/gpu/drm/xe/tests/xe_eudebug.c
> new file mode 100644
> index 000000000000..f839fb292b9b
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/tests/xe_eudebug.c
> @@ -0,0 +1,183 @@
> +// SPDX-License-Identifier: GPL-2.0 AND MIT
> +/*
> + * Copyright © 2024 Intel Corporation
nit: 2026
> + */
> +
> +#include <kunit/visibility.h>
> +
> +#include "regs/xe_gt_regs.h"
> +#include "regs/xe_engine_regs.h"
> +
> +#include "xe_force_wake.h"
> +#include "xe_gt_mcr.h"
> +#include "xe_mmio.h"
> +
> +#include "tests/xe_kunit_helpers.h"
> +#include "tests/xe_pci_test.h"
> +#include "tests/xe_test.h"
> +
> +#undef XE_REG_MCR
> +#define XE_REG_MCR(r_, ...) ((const struct xe_reg_mcr){ \
> + .__reg = XE_REG_INITIALIZER(r_, ##__VA_ARGS__, .mcr = 1) \
> + })
> +
> +static const char *reg_to_str(struct xe_reg reg)
> +{
> + if (reg.raw == TD_CTL.__reg.raw)
> + return "TD_CTL";
> + else if (reg.raw == CS_DEBUG_MODE2(RENDER_RING_BASE).raw)
> + return "CS_DEBUG_MODE2";
> + else if (reg.raw == ROW_CHICKEN.__reg.raw)
> + return "ROW_CHICKEN";
> + else if (reg.raw == ROW_CHICKEN2.__reg.raw)
> + return "ROW_CHICKEN2";
> + else if (reg.raw == ROW_CHICKEN3.__reg.raw)
> + return "ROW_CHICKEN3";
> + else
> + return "UNKNOWN REG";
> +}
> +
> +static u32 get_reg_mask(struct xe_device *xe, struct xe_reg reg)
> +{
> + struct kunit *test = kunit_get_current_test();
> + u32 val = 0;
> +
> + if (reg.raw == TD_CTL.__reg.raw) {
> + val = TD_CTL_BREAKPOINT_ENABLE |
> + TD_CTL_FORCE_THREAD_BREAKPOINT_ENABLE |
> + TD_CTL_FEH_AND_FEE_ENABLE;
> +
> + if (GRAPHICS_VERx100(xe) >= 1250)
> + val |= TD_CTL_GLOBAL_DEBUG_ENABLE;
> +
> + } else if (reg.raw == CS_DEBUG_MODE2(RENDER_RING_BASE).raw) {
> + val = GLOBAL_DEBUG_ENABLE;
> + } else if (reg.raw == ROW_CHICKEN.__reg.raw) {
> + val = STALL_DOP_GATING_DISABLE;
> + } else if (reg.raw == ROW_CHICKEN2.__reg.raw) {
> + val = XEHPC_DISABLE_BTB;
> + } else if (reg.raw == ROW_CHICKEN3.__reg.raw) {
> + val = XE2_EUPEND_CHK_FLUSH_DIS;
> + } else {
> + kunit_warn(test, "Invalid register selection: %u\n", reg.raw);
nit: use KUNIT_FAIL(kunit_get_current_test(), "...");
> + }
> +
> + return val;
> +}
> +
> +static u32 get_reg_expected(struct xe_device *xe, struct xe_reg reg, bool enable_eudebug)
> +{
> + u32 reg_mask = get_reg_mask(xe, reg);
> + u32 reg_bits = 0;
> +
> + if (enable_eudebug || reg.raw == ROW_CHICKEN3.__reg.raw)
> + reg_bits = reg_mask;
> + else
> + reg_bits = 0;
> +
> + return reg_bits;
> +}
> +
> +static void check_reg(struct xe_gt *gt, bool enable_eudebug, struct xe_reg reg)
> +{
> + struct kunit *test = kunit_get_current_test();
nit: as this testcase function, why not pass test as a param?
> + struct xe_device *xe = gt_to_xe(gt);
> + u32 reg_bits_expected = get_reg_expected(xe, reg, enable_eudebug);
> + u32 reg_mask = get_reg_mask(xe, reg);
> + u32 reg_bits = 0;
> +
> + if (reg.mcr)
> + reg_bits = xe_gt_mcr_unicast_read_any(gt, (struct xe_reg_mcr){.__reg = reg});
> + else
> + reg_bits = xe_mmio_read32(>->mmio, reg);
> +
> + reg_bits &= reg_mask;
> +
> + kunit_printk(KERN_DEBUG, test, "%s bits: expected == 0x%x; actual == 0x%x\n",
> + reg_to_str(reg), reg_bits_expected, reg_bits);
nit: is this message really useful?
if bits are different then below EXPECT macro will print them anyway
> + KUNIT_EXPECT_EQ_MSG(test, reg_bits_expected, reg_bits,
> + "Invalid bits set for %s\n", reg_to_str(reg));
> +}
> +
> +static void __check_regs(struct xe_gt *gt, bool enable_eudebug)
nit: maybe this function should be split into two:
- first that returns register
- second that runs tests on it?
> +{
> + struct xe_device *xe = gt_to_xe(gt);
> +
> + if (GRAPHICS_VERx100(xe) >= 1200)
> + check_reg(gt, enable_eudebug, TD_CTL.__reg);
> +
> + if (GRAPHICS_VERx100(xe) >= 1250 && GRAPHICS_VERx100(xe) <= 1274)
> + check_reg(gt, enable_eudebug, ROW_CHICKEN.__reg);
> +
> + if (xe->info.platform == XE_PVC)
> + check_reg(gt, enable_eudebug, ROW_CHICKEN2.__reg);
> +
> + if (GRAPHICS_VERx100(xe) >= 2000 && GRAPHICS_VERx100(xe) <= 2004)
> + check_reg(gt, enable_eudebug, ROW_CHICKEN3.__reg);
> +}
> +
> +static void check_regs(struct xe_device *xe, bool enable_eudebug)
> +{
> + struct kunit *test = kunit_get_current_test();
> + struct xe_gt *gt;
> + unsigned int fw_ref;
> + u8 id;
> +
> + kunit_printk(KERN_DEBUG, test, "Check regs for eudebug %s\n",
> + enable_eudebug ? "enabled" : "disabled");
> +
> + xe_pm_runtime_get(xe);
nit: no need to take extra rpm, our live test helper takes care of it
> + for_each_gt(gt, xe, id) {
> + if (xe_gt_is_media_type(gt))
> + continue;
> +
> + /* XXX: Figure out per platform proper domain */
> + fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL);
> + KUNIT_ASSERT_TRUE_MSG(test, fw_ref, "Forcewake failed.\n");
> +
> + __check_regs(gt, enable_eudebug);
> +
> + xe_force_wake_put(gt_to_fw(gt), fw_ref);
> + }
> + xe_pm_runtime_put(xe);
> +}
> +
> +static int toggle_reg_value(struct xe_device *xe)
> +{
> + struct kunit *test = kunit_get_current_test();
> + bool enable_eudebug = xe_eudebug_is_enabled(xe);
> +
> + kunit_printk(KERN_DEBUG, test, "Test eudebug WAs for graphics version: %u\n",
> + GRAPHICS_VERx100(xe));
nit: if GFX version is so important for EUDEBUG then maybe this
message should be part of the custom test_init()?
static int xe_eudebug_test_init(test)
{
struct xe_device *xe;
xe_kunit_helper_xe_device_live_test_init(test);
xe = test->priv;
kunit_info(test, "running on graphics version: %u", GRAPHICS_VERx100(xe));
return 0;
}
> +
> + check_regs(xe, enable_eudebug);
> +
> + xe_eudebug_enable(xe, !enable_eudebug);
> + check_regs(xe, !enable_eudebug);
> +
> + xe_eudebug_enable(xe, enable_eudebug);
> + check_regs(xe, enable_eudebug);
> +
> + return 0;
> +}
> +
> +static void xe_eudebug_toggle_reg_kunit(struct kunit *test)
nit: no need to add 'xe_eudebug' prefix as this test case is
already in 'xe_eudebug' suite
nit: this '_kunit' suffix seems unnecessary
see https://docs.kernel.org/dev-tools/kunit/style.html#test-cases
> +{
> + struct xe_device *xe = test->priv;
> +
> + toggle_reg_value(xe);
> +}
> +
> +static struct kunit_case xe_eudebug_tests[] = {
> + KUNIT_CASE_PARAM(xe_eudebug_toggle_reg_kunit,
> + xe_pci_live_device_gen_param),
> + {}
> +};
> +
> +VISIBLE_IF_KUNIT
> +struct kunit_suite xe_eudebug_test_suite = {
> + .name = "xe_eudebug",
> + .test_cases = xe_eudebug_tests,
> + .init = xe_kunit_helper_xe_device_live_test_init,
> +};
> +EXPORT_SYMBOL_IF_KUNIT(xe_eudebug_test_suite);
> diff --git a/drivers/gpu/drm/xe/tests/xe_live_test_mod.c b/drivers/gpu/drm/xe/tests/xe_live_test_mod.c
> index c55e46f1ae92..dc83bb6a892d 100644
> --- a/drivers/gpu/drm/xe/tests/xe_live_test_mod.c
> +++ b/drivers/gpu/drm/xe/tests/xe_live_test_mod.c
> @@ -19,6 +19,11 @@ kunit_test_suite(xe_migrate_test_suite);
> kunit_test_suite(xe_mocs_test_suite);
> kunit_test_suite(xe_guc_g2g_test_suite);
>
> +#if IS_ENABLED(CONFIG_DRM_XE_EUDEBUG)
> +extern struct kunit_suite xe_eudebug_test_suite;
> +kunit_test_suite(xe_eudebug_test_suite);
> +#endif
> +
> MODULE_AUTHOR("Intel Corporation");
> MODULE_LICENSE("GPL");
> MODULE_DESCRIPTION("xe live kunit tests");
> diff --git a/drivers/gpu/drm/xe/xe_eudebug.c b/drivers/gpu/drm/xe/xe_eudebug.c
> index 2566b55f9c47..f5547c756b31 100644
> --- a/drivers/gpu/drm/xe/xe_eudebug.c
> +++ b/drivers/gpu/drm/xe/xe_eudebug.c
> @@ -2242,3 +2242,7 @@ int xe_eudebug_connect_ioctl(struct drm_device *dev,
>
> return xe_eudebug_connect(xe, file, param);
> }
> +
> +#if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)
> +#include "tests/xe_eudebug.c"
> +#endif
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 17/24] drm/xe: Implement SR-IOV and eudebug exclusivity
2026-04-30 10:50 [PATCH 00/24] Intel Xe GPU Debug Support (eudebug) v8 Mika Kuoppala
` (15 preceding siblings ...)
2026-04-30 10:51 ` [PATCH 16/24] drm/xe/eudebug_test: Introduce xe_eudebug wa kunit test Mika Kuoppala
@ 2026-04-30 10:51 ` Mika Kuoppala
2026-04-30 10:51 ` [PATCH 18/24] drm/xe: Add xe_client_debugfs and introduce debug_data file Mika Kuoppala
` (10 subsequent siblings)
27 siblings, 0 replies; 32+ messages in thread
From: Mika Kuoppala @ 2026-04-30 10:51 UTC (permalink / raw)
To: intel-xe
Cc: simona.vetter, matthew.brost, christian.koenig, thomas.hellstrom,
joonas.lahtinen, gustavo.sousa, jan.maslak,
dominik.karol.piatkowski, rodrigo.vivi, andrzej.hajda,
matthew.auld, maciej.patelczyk, gwan-gyeong.mun,
Christoph Manszewski, Mika Kuoppala
From: Christoph Manszewski <christoph.manszewski@intel.com>
EU debug functionality relies on access to specific mmio registers.
Since VFs don't have access to those registers and in order to avoid
interference with VFs, make SR-IOV and eudebug functionality exclusive.
I.e. don't allow to enable eudebug in VF mode and don't allow to enable
eudebug when any VFs are provisioned. Likewise, don't allow to provision
VFs when eudebug is enabled.
Signed-off-by: Christoph Manszewski <christoph.manszewski@intel.com>
Signed-off-by: Maciej Patelczyk <maciej.patelczyk@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/xe/tests/xe_eudebug.c | 10 ++++++++++
drivers/gpu/drm/xe/xe_eudebug.c | 23 +++++++++++++++++++++--
2 files changed, 31 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/xe/tests/xe_eudebug.c b/drivers/gpu/drm/xe/tests/xe_eudebug.c
index f839fb292b9b..601725c642bd 100644
--- a/drivers/gpu/drm/xe/tests/xe_eudebug.c
+++ b/drivers/gpu/drm/xe/tests/xe_eudebug.c
@@ -8,9 +8,13 @@
#include "regs/xe_gt_regs.h"
#include "regs/xe_engine_regs.h"
+#include "xe_device.h"
+#include "xe_eudebug.h"
#include "xe_force_wake.h"
+#include "xe_gt.h"
#include "xe_gt_mcr.h"
#include "xe_mmio.h"
+#include "xe_pm.h"
#include "tests/xe_kunit_helpers.h"
#include "tests/xe_pci_test.h"
@@ -147,6 +151,12 @@ static int toggle_reg_value(struct xe_device *xe)
struct kunit *test = kunit_get_current_test();
bool enable_eudebug = xe_eudebug_is_enabled(xe);
+ if (IS_SRIOV_VF(xe))
+ kunit_skip(test, "eudebug not available in SR-IOV VF mode\n");
+
+ if (xe->eudebug.state == XE_EUDEBUG_NOT_SUPPORTED)
+ kunit_skip(test, "eudebug not supported\n");
+
kunit_printk(KERN_DEBUG, test, "Test eudebug WAs for graphics version: %u\n",
GRAPHICS_VERx100(xe));
diff --git a/drivers/gpu/drm/xe/xe_eudebug.c b/drivers/gpu/drm/xe/xe_eudebug.c
index f5547c756b31..4e9977d33612 100644
--- a/drivers/gpu/drm/xe/xe_eudebug.c
+++ b/drivers/gpu/drm/xe/xe_eudebug.c
@@ -24,6 +24,7 @@
#include "xe_hw_engine.h"
#include "xe_macros.h"
#include "xe_pm.h"
+#include "xe_sriov_pf.h"
#include "xe_sync.h"
#include "xe_vm.h"
@@ -2084,6 +2085,7 @@ bool xe_eudebug_is_enabled(struct xe_device *xe)
int xe_eudebug_enable(struct xe_device *xe, bool enable)
{
struct xe_gt *gt;
+ int ret;
int i;
u8 id;
@@ -2104,6 +2106,14 @@ int xe_eudebug_enable(struct xe_device *xe, bool enable)
return 0;
}
+ if (enable && IS_SRIOV_PF(xe)) {
+ ret = xe_sriov_pf_lockdown(xe);
+ if (ret) {
+ mutex_unlock(&xe->eudebug.lock);
+ return ret;
+ }
+ }
+
xe_pm_runtime_get(xe);
for_each_gt(gt, xe, id) {
@@ -2124,11 +2134,15 @@ int xe_eudebug_enable(struct xe_device *xe, bool enable)
XE_EUDEBUG_ENABLED : XE_EUDEBUG_DISABLED;
mutex_unlock(&xe->eudebug.lock);
- if (enable)
+ if (enable) {
attention_poll_start(xe);
- else
+ } else {
attention_poll_stop(xe);
+ if (IS_SRIOV_PF(xe))
+ xe_sriov_pf_end_lockdown(xe);
+ }
+
return 0;
}
@@ -2190,6 +2204,11 @@ void xe_eudebug_init(struct xe_device *xe)
xe->eudebug.state = XE_EUDEBUG_NOT_SUPPORTED;
+ if (IS_SRIOV_VF(xe)) {
+ drm_info(&xe->drm, "eudebug not available in SR-IOV VF mode\n");
+ return;
+ }
+
err = drmm_mutex_init(dev, &xe->eudebug.lock);
if (err)
goto out_err;
--
2.43.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 18/24] drm/xe: Add xe_client_debugfs and introduce debug_data file
2026-04-30 10:50 [PATCH 00/24] Intel Xe GPU Debug Support (eudebug) v8 Mika Kuoppala
` (16 preceding siblings ...)
2026-04-30 10:51 ` [PATCH 17/24] drm/xe: Implement SR-IOV and eudebug exclusivity Mika Kuoppala
@ 2026-04-30 10:51 ` Mika Kuoppala
2026-04-30 10:51 ` [PATCH 19/24] drm/xe/eudebug: Allow getting eudebug instance during discovery Mika Kuoppala
` (9 subsequent siblings)
27 siblings, 0 replies; 32+ messages in thread
From: Mika Kuoppala @ 2026-04-30 10:51 UTC (permalink / raw)
To: intel-xe
Cc: simona.vetter, matthew.brost, christian.koenig, thomas.hellstrom,
joonas.lahtinen, gustavo.sousa, jan.maslak,
dominik.karol.piatkowski, rodrigo.vivi, andrzej.hajda,
matthew.auld, maciej.patelczyk, gwan-gyeong.mun,
Christoph Manszewski, Sunil Khatri, Mika Kuoppala
From: Christoph Manszewski <christoph.manszewski@intel.com>
Create a debug_data file for each xe file/client which is supposed to
list all mapped debug data and attempts to mimic '/proc/pid/maps'.
Each line represents a single mapping and has the following format:
<vm id> <begin>-<end> <flags> <offset> <pathname>
Cc: Sunil Khatri <sunil.khatri@amd.com>
Signed-off-by: Christoph Manszewski <christoph.manszewski@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/xe/Makefile | 3 +-
drivers/gpu/drm/xe/xe_client_debugfs.c | 118 +++++++++++++++++++++++++
drivers/gpu/drm/xe/xe_client_debugfs.h | 19 ++++
drivers/gpu/drm/xe/xe_device.c | 3 +
4 files changed, 142 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/xe/xe_client_debugfs.c
create mode 100644 drivers/gpu/drm/xe/xe_client_debugfs.h
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 1531ea9b3a93..e43d89a45d39 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -354,7 +354,8 @@ ifeq ($(CONFIG_DRM_FBDEV_EMULATION),y)
endif
ifeq ($(CONFIG_DEBUG_FS),y)
- xe-y += xe_debugfs.o \
+ xe-y += xe_client_debugfs.o \
+ xe_debugfs.o \
xe_gt_debugfs.o \
xe_gt_sriov_vf_debugfs.o \
xe_gt_stats.o \
diff --git a/drivers/gpu/drm/xe/xe_client_debugfs.c b/drivers/gpu/drm/xe/xe_client_debugfs.c
new file mode 100644
index 000000000000..0b952038e698
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_client_debugfs.c
@@ -0,0 +1,118 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#include "xe_client_debugfs.h"
+
+#include <linux/debugfs.h>
+
+#include "xe_debug_data.h"
+#include "xe_debug_data_types.h"
+#include "xe_device_types.h"
+#include "xe_vm_types.h"
+
+#define MAX_LINE_LEN (64 + PATH_MAX)
+
+static ssize_t debug_data_read(struct file *file, char __user *buf, size_t count,
+ loff_t *ppos)
+{
+ struct xe_debug_data *dd;
+ unsigned long vm_index;
+ const char *path;
+ char *kbuf;
+ struct xe_vm *vm;
+
+ struct xe_file *xef = file->private_data;
+ ssize_t total = 0;
+ loff_t pos = 0;
+
+ if (!xef || !buf)
+ return -EINVAL;
+
+ kbuf = kmalloc(MAX_LINE_LEN, GFP_KERNEL);
+ if (!kbuf)
+ return -ENOMEM;
+
+ mutex_lock(&xef->vm.lock);
+
+ xa_for_each(&xef->vm.xa, vm_index, vm) {
+ mutex_lock(&vm->debug_data.lock);
+ list_for_each_entry(dd, &vm->debug_data.list, link) {
+ int len;
+
+ path = dd->flags & DRM_XE_VM_BIND_DEBUG_DATA_FLAG_PSEUDO ?
+ xe_debug_data_pseudo_path_to_string(dd->pseudopath) :
+ dd->pathname;
+
+ /* Format: <vm id> <begin>-<end> <flags> <offset> <pathname> */
+ len = snprintf(kbuf, MAX_LINE_LEN, "%lu 0x%llx-0x%llx 0x%llx 0x%x\t%s\n",
+ vm_index,
+ dd->addr,
+ dd->addr + dd->range,
+ dd->flags,
+ dd->offset,
+ path);
+
+ if (pos + len <= *ppos) {
+ pos += len;
+ continue;
+ }
+
+ if (pos < *ppos) {
+ const int skip = *ppos - pos;
+
+ len -= skip;
+ memmove(kbuf, kbuf + skip, len);
+ pos = *ppos;
+ }
+
+ if (total + len > count)
+ len = count - total;
+
+ if (copy_to_user(buf + total, kbuf, len)) {
+ mutex_unlock(&vm->debug_data.lock);
+ mutex_unlock(&xef->vm.lock);
+ kfree(kbuf);
+ return -EFAULT;
+ }
+
+ total += len;
+ pos += len;
+
+ if (total >= count) {
+ mutex_unlock(&vm->debug_data.lock);
+ mutex_unlock(&xef->vm.lock);
+ kfree(kbuf);
+ *ppos = pos;
+ return total;
+ }
+ }
+ mutex_unlock(&vm->debug_data.lock);
+ }
+
+ mutex_unlock(&xef->vm.lock);
+ kfree(kbuf);
+ *ppos = pos;
+ return total;
+}
+
+static int debug_data_open(struct inode *inode, struct file *file)
+{
+ struct xe_file *xef = inode->i_private;
+
+ file->private_data = xef;
+ return 0;
+}
+
+static const struct file_operations maps_fops = {
+ .owner = THIS_MODULE,
+ .open = debug_data_open,
+ .read = debug_data_read,
+ .llseek = default_llseek,
+};
+
+void xe_client_debugfs_register(struct xe_file *xef)
+{
+ debugfs_create_file("debug_data", 0444, xef->drm->debugfs_client, xef, &maps_fops);
+}
diff --git a/drivers/gpu/drm/xe/xe_client_debugfs.h b/drivers/gpu/drm/xe/xe_client_debugfs.h
new file mode 100644
index 000000000000..9eace15c0a49
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_client_debugfs.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef _XE_CLIENT_DEBUGFS_H_
+#define _XE_CLIENT_DEBUGFS_H_
+
+#include <linux/debugfs.h>
+
+struct xe_file;
+
+#ifdef CONFIG_DEBUG_FS
+void xe_client_debugfs_register(struct xe_file *xef);
+#else
+static inline void xe_client_debugfs_register(struct xe_file *xef) { }
+#endif
+
+#endif // _XE_CLIENT_DEBUGFS_H_
diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index 7f04951188d9..136c7d3f12c0 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -26,6 +26,7 @@
#include "regs/xe_regs.h"
#include "xe_bo.h"
#include "xe_bo_evict.h"
+#include "xe_client_debugfs.h"
#include "xe_configfs.h"
#include "xe_debugfs.h"
#include "xe_defaults.h"
@@ -127,6 +128,8 @@ static int xe_file_open(struct drm_device *dev, struct drm_file *file)
put_task_struct(task);
}
+ xe_client_debugfs_register(xef);
+
return 0;
}
--
2.43.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 19/24] drm/xe/eudebug: Allow getting eudebug instance during discovery
2026-04-30 10:50 [PATCH 00/24] Intel Xe GPU Debug Support (eudebug) v8 Mika Kuoppala
` (17 preceding siblings ...)
2026-04-30 10:51 ` [PATCH 18/24] drm/xe: Add xe_client_debugfs and introduce debug_data file Mika Kuoppala
@ 2026-04-30 10:51 ` Mika Kuoppala
2026-04-30 10:51 ` [PATCH 20/24] drm/xe/eudebug: Add read/count/compare helper for eu attention Mika Kuoppala
` (8 subsequent siblings)
27 siblings, 0 replies; 32+ messages in thread
From: Mika Kuoppala @ 2026-04-30 10:51 UTC (permalink / raw)
To: intel-xe
Cc: simona.vetter, matthew.brost, christian.koenig, thomas.hellstrom,
joonas.lahtinen, gustavo.sousa, jan.maslak,
dominik.karol.piatkowski, rodrigo.vivi, andrzej.hajda,
matthew.auld, maciej.patelczyk, gwan-gyeong.mun, Mika Kuoppala
From: Maciej Patelczyk <maciej.patelczyk@intel.com>
Allow to get eudebug instance even if discovery has not yet finished.
This is needed for internal queuing pagefault events if discovery is
running.
Signed-off-by: Maciej Patelczyk <maciej.patelczyk@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/xe/xe_eudebug.c | 35 +++++++++++++++++++++++++++++----
drivers/gpu/drm/xe/xe_eudebug.h | 2 ++
2 files changed, 33 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_eudebug.c b/drivers/gpu/drm/xe/xe_eudebug.c
index 4e9977d33612..3f22924a1275 100644
--- a/drivers/gpu/drm/xe/xe_eudebug.c
+++ b/drivers/gpu/drm/xe/xe_eudebug.c
@@ -467,7 +467,7 @@ static int _xe_eudebug_disconnect(struct xe_eudebug *d,
})
static struct xe_eudebug *
-xe_eudebug_get_nolock(struct xe_file *xef)
+__xe_eudebug_get(struct xe_file *xef)
{
struct xe_eudebug *d;
@@ -480,8 +480,22 @@ xe_eudebug_get_nolock(struct xe_file *xef)
if (!d)
return NULL;
- if (xe_eudebug_detached(d) ||
- !completion_done(&d->discovery)) {
+ if (xe_eudebug_detached(d)) {
+ xe_eudebug_put(d);
+ return NULL;
+ }
+
+ return d;
+}
+
+static struct xe_eudebug *
+_xe_eudebug_get(struct xe_file *xef)
+{
+ struct xe_eudebug *d;
+
+ d = __xe_eudebug_get(xef);
+
+ if (d && !completion_done(&d->discovery)) {
xe_eudebug_put(d);
return NULL;
}
@@ -494,7 +508,20 @@ xe_eudebug_get(struct xe_file *xef)
{
lockdep_assert_held(&xef->eudebug.ioctl_lock);
- return xe_eudebug_get_nolock(xef);
+ return _xe_eudebug_get(xef);
+}
+
+struct xe_eudebug *
+xe_eudebug_get_nolock(struct xe_file *xef)
+{
+ return _xe_eudebug_get(xef);
+}
+
+/* Returns eudebug instance even if discovery is running */
+struct xe_eudebug *
+xe_eudebug_get_nolock_with_discovery(struct xe_file *xef)
+{
+ return __xe_eudebug_get(xef);
}
static int xe_eudebug_queue_event(struct xe_eudebug *d,
diff --git a/drivers/gpu/drm/xe/xe_eudebug.h b/drivers/gpu/drm/xe/xe_eudebug.h
index bd9fd7bf454f..b1f8a5fcc890 100644
--- a/drivers/gpu/drm/xe/xe_eudebug.h
+++ b/drivers/gpu/drm/xe/xe_eudebug.h
@@ -72,6 +72,8 @@ void xe_eudebug_ufence_init(struct xe_user_fence *ufence);
void xe_eudebug_ufence_fini(struct xe_user_fence *ufence);
bool xe_eudebug_ufence_track(struct xe_user_fence *ufence);
+struct xe_eudebug *xe_eudebug_get_nolock(struct xe_file *xef);
+struct xe_eudebug *xe_eudebug_get_nolock_with_discovery(struct xe_file *xef);
void xe_eudebug_put(struct xe_eudebug *d);
#else
--
2.43.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 20/24] drm/xe/eudebug: Add read/count/compare helper for eu attention
2026-04-30 10:50 [PATCH 00/24] Intel Xe GPU Debug Support (eudebug) v8 Mika Kuoppala
` (18 preceding siblings ...)
2026-04-30 10:51 ` [PATCH 19/24] drm/xe/eudebug: Allow getting eudebug instance during discovery Mika Kuoppala
@ 2026-04-30 10:51 ` Mika Kuoppala
2026-04-30 10:51 ` [PATCH 21/24] drm/xe/vm: Support for adding null page VMA to VM on request Mika Kuoppala
` (7 subsequent siblings)
27 siblings, 0 replies; 32+ messages in thread
From: Mika Kuoppala @ 2026-04-30 10:51 UTC (permalink / raw)
To: intel-xe
Cc: simona.vetter, matthew.brost, christian.koenig, thomas.hellstrom,
joonas.lahtinen, gustavo.sousa, jan.maslak,
dominik.karol.piatkowski, rodrigo.vivi, andrzej.hajda,
matthew.auld, maciej.patelczyk, gwan-gyeong.mun, Mika Kuoppala
From: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Add xe_eu_attentions structure to capture and store eu attention bits.
Add a function to count the number of eu threads that have turned on from
eu attentions, and add a function to count the number of eu threads that
have changed on a state between eu attentions.
v2: fix array size calculation (Christoph)
v3: remote timestamp (Maciej)
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: Maciej Patelczyk <maciej.patelczyk@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/xe/xe_gt_debug.c | 63 ++++++++++++++++++++++++++
drivers/gpu/drm/xe/xe_gt_debug.h | 9 +++-
drivers/gpu/drm/xe/xe_gt_debug_types.h | 22 +++++++++
3 files changed, 93 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/xe/xe_gt_debug_types.h
diff --git a/drivers/gpu/drm/xe/xe_gt_debug.c b/drivers/gpu/drm/xe/xe_gt_debug.c
index 314eef6734c3..9265506da05f 100644
--- a/drivers/gpu/drm/xe/xe_gt_debug.c
+++ b/drivers/gpu/drm/xe/xe_gt_debug.c
@@ -3,12 +3,14 @@
* Copyright © 2023 Intel Corporation
*/
+#include <linux/delay.h>
#include "regs/xe_gt_regs.h"
#include "xe_device.h"
#include "xe_force_wake.h"
#include "xe_gt.h"
#include "xe_gt_topology.h"
#include "xe_gt_debug.h"
+#include "xe_gt_debug_types.h"
#include "xe_gt_mcr.h"
#include "xe_pm.h"
#include "xe_macros.h"
@@ -177,3 +179,64 @@ int xe_gt_eu_threads_needing_attention(struct xe_gt *gt)
return err < 0 ? 0 : err;
}
+
+static inline unsigned int
+xe_eu_attentions_count(const struct xe_eu_attentions *a)
+{
+ return bitmap_weight((void *)a->att, a->size * BITS_PER_BYTE);
+}
+
+void xe_gt_eu_attentions_read(struct xe_gt *gt,
+ struct xe_eu_attentions *a,
+ const unsigned int settle_time_ms)
+{
+ unsigned int attn, prev = 0;
+ ktime_t end, now;
+
+ now = ktime_get_raw();
+ /* Initially wait longer for attentions to appear */
+ end = ktime_add_ms(now, settle_time_ms * 10);
+
+ a->size = min_t(int,
+ xe_gt_eu_attention_bitmap_size(gt),
+ sizeof(a->att));
+
+ do {
+ if (xe_gt_eu_attention_bitmap(gt, a->att, a->size) < 0)
+ return;
+
+ attn = xe_eu_attentions_count(a);
+
+ now = ktime_get_raw();
+
+ if (attn > prev) {
+ prev = attn;
+ end = ktime_add_ms(now, settle_time_ms);
+ }
+
+ if (settle_time_ms)
+ udelay(5);
+
+ /*
+ * XXX We are gathering data for production SIP to find
+ * the upper limit of settle time. For now, we wait full
+ * timeout value regardless.
+ */
+ } while ((attn < a->size * 8) && ktime_before(now, end));
+}
+
+unsigned int xe_eu_attentions_xor_count(const struct xe_eu_attentions *a,
+ const struct xe_eu_attentions *b)
+{
+ unsigned int count = 0;
+ unsigned int i;
+
+ if (XE_WARN_ON(a->size != b->size))
+ return -EINVAL;
+
+ for (i = 0; i < a->size; i++)
+ if (a->att[i] ^ b->att[i])
+ count++;
+
+ return count;
+}
diff --git a/drivers/gpu/drm/xe/xe_gt_debug.h b/drivers/gpu/drm/xe/xe_gt_debug.h
index 9dabe9cc1d25..a1103ecf1b4e 100644
--- a/drivers/gpu/drm/xe/xe_gt_debug.h
+++ b/drivers/gpu/drm/xe/xe_gt_debug.h
@@ -9,9 +9,10 @@
#include <linux/bits.h>
#include <linux/math.h>
+struct xe_eu_attentions;
struct xe_gt;
-#define XE_GT_ATTENTION_TIMEOUT_MS 100
+#define XE_GT_ATTENTION_TIMEOUT_MS 150
#define XE_GT_EU_ATT_ROWS 2u
unsigned int xe_gt_eu_att_regs(struct xe_gt *gt);
@@ -29,4 +30,10 @@ int xe_gt_eu_attention_bitmap_size(struct xe_gt *gt);
int xe_gt_eu_attention_bitmap(struct xe_gt *gt, u8 *bits,
unsigned int bitmap_size);
+void xe_gt_eu_attentions_read(struct xe_gt *gt,
+ struct xe_eu_attentions *a,
+ const unsigned int settle_time_ms);
+
+unsigned int xe_eu_attentions_xor_count(const struct xe_eu_attentions *a,
+ const struct xe_eu_attentions *b);
#endif
diff --git a/drivers/gpu/drm/xe/xe_gt_debug_types.h b/drivers/gpu/drm/xe/xe_gt_debug_types.h
new file mode 100644
index 000000000000..f24eed15cf7c
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_gt_debug_types.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef __XE_GT_DEBUG_TYPES_
+#define __XE_GT_DEBUG_TYPES_
+
+#include <linux/types.h>
+
+#define XE_GT_EU_ATT_ROWS 2u
+#define XE_GT_EU_ATT_MAX_THREADS 16
+#define XE_GT_EU_MAX_NUM 1024
+
+struct xe_eu_attentions {
+ u8 att[XE_GT_EU_MAX_NUM *
+ XE_GT_EU_ATT_ROWS *
+ XE_GT_EU_ATT_MAX_THREADS/8];
+ unsigned int size;
+};
+
+#endif
--
2.43.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 21/24] drm/xe/vm: Support for adding null page VMA to VM on request
2026-04-30 10:50 [PATCH 00/24] Intel Xe GPU Debug Support (eudebug) v8 Mika Kuoppala
` (19 preceding siblings ...)
2026-04-30 10:51 ` [PATCH 20/24] drm/xe/eudebug: Add read/count/compare helper for eu attention Mika Kuoppala
@ 2026-04-30 10:51 ` Mika Kuoppala
2026-04-30 10:51 ` [PATCH 22/24] drm/xe/eudebug: Introduce EU pagefault handling interface Mika Kuoppala
` (6 subsequent siblings)
27 siblings, 0 replies; 32+ messages in thread
From: Mika Kuoppala @ 2026-04-30 10:51 UTC (permalink / raw)
To: intel-xe
Cc: simona.vetter, matthew.brost, christian.koenig, thomas.hellstrom,
joonas.lahtinen, gustavo.sousa, jan.maslak,
dominik.karol.piatkowski, rodrigo.vivi, andrzej.hajda,
matthew.auld, maciej.patelczyk, gwan-gyeong.mun, Oak Zeng,
Niranjana Vishwanathapura, Stuart Summers, Bruce Chang,
Mika Kuoppala
From: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
The XE2 (and PVC) HW has a limitation that the pagefault due to invalid
access will halt the corresponding EUs. So, in order to activate the
debugger, kmd needs to install the temporal page to unhalt the EUs.
Plan to be used for pagefault handling when the EU debugger is running.
The idea is to install a null page vma if the pagefault is from an invalid
access. After installing null page pte, the user debugger can continue to
run/inspect without causing a fatal failure or reset and stop.
Based on Bruce's implementation [1].
[1] https://lore.kernel.org/intel-xe/20230829231648.4438-1-yu.bruce.chang@intel.com/
v2: s/NULL_VMA/DRM_GPUVA_SPARSE (Mika)
v3: use ERR_CAST as we dont return null (Mika)
Cc: Oak Zeng <oak.zeng@intel.com>
Cc: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Cc: Stuart Summers <stuart.summers@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Co-developed-by: Bruce Chang <yu.bruce.chang@intel.com>
Signed-off-by: Bruce Chang <yu.bruce.chang@intel.com>
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/xe/xe_vm.c | 33 +++++++++++++++++++++++++++++++++
drivers/gpu/drm/xe/xe_vm.h | 3 +++
2 files changed, 36 insertions(+)
diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
index f00bd5801b0c..20acf5b63214 100644
--- a/drivers/gpu/drm/xe/xe_vm.c
+++ b/drivers/gpu/drm/xe/xe_vm.c
@@ -5083,3 +5083,36 @@ void xe_vm_remove_exec_queue(struct xe_vm *vm, struct xe_exec_queue *q)
}
up_write(&vm->exec_queues.lock);
}
+
+struct xe_vma *xe_vm_create_null_vma(struct xe_vm *vm, u64 addr)
+{
+ struct xe_vma_mem_attr default_attr = {
+ .preferred_loc = {
+ .devmem_fd = DRM_XE_PREFERRED_LOC_DEFAULT_DEVICE,
+ .migration_policy = DRM_XE_MIGRATE_ALL_PAGES,
+ },
+ .atomic_access = DRM_XE_ATOMIC_UNDEFINED,
+ .default_pat_index = vm->xe->pat.idx[XE_CACHE_NONE],
+ .pat_index = vm->xe->pat.idx[XE_CACHE_NONE],
+ };
+ struct xe_vma *vma;
+ u32 page_size;
+ int err;
+
+ if (xe_vm_is_closed_or_banned(vm))
+ return ERR_PTR(-ENOENT);
+
+ page_size = vm->flags & XE_VM_FLAG_64K ? SZ_64K : SZ_4K;
+ vma = xe_vma_create(vm, NULL, 0, addr, addr + page_size - 1,
+ &default_attr, DRM_GPUVA_SPARSE);
+ if (IS_ERR(vma))
+ return ERR_CAST(vma);
+
+ err = xe_vm_insert_vma(vm, vma);
+ if (err) {
+ xe_vma_destroy_late(vma);
+ return ERR_PTR(err);
+ }
+
+ return vma;
+}
diff --git a/drivers/gpu/drm/xe/xe_vm.h b/drivers/gpu/drm/xe/xe_vm.h
index c5b900f38ded..63821e11c81a 100644
--- a/drivers/gpu/drm/xe/xe_vm.h
+++ b/drivers/gpu/drm/xe/xe_vm.h
@@ -436,4 +436,7 @@ static inline struct drm_exec *xe_vm_validation_exec(struct xe_vm *vm)
((READ_ONCE(tile_present) & ~READ_ONCE(tile_invalidated)) & BIT((tile)->id))
void xe_vma_mem_attr_copy(struct xe_vma_mem_attr *to, struct xe_vma_mem_attr *from);
+
+struct xe_vma *xe_vm_create_null_vma(struct xe_vm *vm, u64 addr);
+
#endif
--
2.43.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 22/24] drm/xe/eudebug: Introduce EU pagefault handling interface
2026-04-30 10:50 [PATCH 00/24] Intel Xe GPU Debug Support (eudebug) v8 Mika Kuoppala
` (20 preceding siblings ...)
2026-04-30 10:51 ` [PATCH 21/24] drm/xe/vm: Support for adding null page VMA to VM on request Mika Kuoppala
@ 2026-04-30 10:51 ` Mika Kuoppala
2026-04-30 19:50 ` Gwan-gyeong Mun
2026-04-30 10:51 ` [PATCH 23/24] drm/xe/eudebug: Enable EU pagefault handling Mika Kuoppala
` (5 subsequent siblings)
27 siblings, 1 reply; 32+ messages in thread
From: Mika Kuoppala @ 2026-04-30 10:51 UTC (permalink / raw)
To: intel-xe
Cc: simona.vetter, matthew.brost, christian.koenig, thomas.hellstrom,
joonas.lahtinen, gustavo.sousa, jan.maslak,
dominik.karol.piatkowski, rodrigo.vivi, andrzej.hajda,
matthew.auld, maciej.patelczyk, gwan-gyeong.mun, Mika Kuoppala
From: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
The XE2 (and PVC) HW has a limitation that the pagefault due to invalid
access will halt the corresponding EUs. To solve this problem, introduce
EU pagefault handling functionality, which allows to unhalt pagefaulted
eu threads and to EU debugger to get inform about the eu attentions state
of EU threads during execution.
If a pagefault occurs, send the DRM_XE_EUDEBUG_EVENT_PAGEFAULT event
after handling the pagefault. The pagefault eudebug event follows
the newly added drm_xe_eudebug_event_pagefault type.
When a pagefault occurs, it prevents to send the
DRM_XE_EUDEBUG_EVENT_EU_ATTENTION event to the client during pagefault
handling.
The page fault event delivery follows the below policy.
(1) If EU Debugger discovery has completed and pagefaulted eu threads turn
on attention bit then pagefault handler delivers pagefault event
directly.
(2) If a pagefault occurs during eu debugger discovery process, pagefault
handler queues a pagefault event and sends the queued event when
discovery has completed and pagefaulted eu threads turn on attention
bit.
(3) If the pagefaulted eu thread struggles to turn on the attention bit
within the specified time, the attention scan worker sends a pagefault
event when it detects that the attention bit is turned on.
If multiple eu threads are running and a pagefault occurs due to accessing
the same invalid address, send a single pagefault event
(DRM_XE_EUDEBUG_EVENT_PAGEFAULT type) to the user debugger instead of a
pagefault event for each of the multiple eu threads.
If eu threads (other than the one that caused the page fault before) access
the new invalid addresses, send a new pagefault event.
As the attention scan worker send the eu attention event whenever the
attention bit is turned on, user debugger receives attenion event
immediately after pagefault event.
In this case, the page-fault event always precedes the attention event.
When the user debugger receives an attention event after a pagefault event,
it can detect whether additional breakpoints or interrupts occur in
addition to the existing pagefault by comparing the eu threads where the
pagefault occurred with the eu threads where the attention bit is newly
enabled.
v2: use only force exception (Joonas, Mika)
v3: rebased on v4 (Mika)
v4: streamline uapi, cleanups (Mika)
v5: struct member documentation (Mika)
v6: fault to fault_type (Mika)
v7: pagefault rework (Maciej)
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: Jan Maślak <jan.maslak@intel.com>
Signed-off-by: Maciej Patelczyk <maciej.patelczyk@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/xe/Makefile | 2 +-
drivers/gpu/drm/xe/xe_eudebug.c | 104 +++++-
drivers/gpu/drm/xe/xe_eudebug.h | 8 +
drivers/gpu/drm/xe/xe_eudebug_hw.c | 15 +-
drivers/gpu/drm/xe/xe_eudebug_pagefault.c | 412 ++++++++++++++++++++++
drivers/gpu/drm/xe/xe_eudebug_pagefault.h | 63 ++++
drivers/gpu/drm/xe/xe_eudebug_types.h | 61 +++-
drivers/gpu/drm/xe/xe_guc_pagefault.c | 3 +-
drivers/gpu/drm/xe/xe_pagefault_types.h | 1 +
include/uapi/drm/xe_drm_eudebug.h | 12 +
10 files changed, 658 insertions(+), 23 deletions(-)
create mode 100644 drivers/gpu/drm/xe/xe_eudebug_pagefault.c
create mode 100644 drivers/gpu/drm/xe/xe_eudebug_pagefault.h
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index e43d89a45d39..53302104d05c 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -158,7 +158,7 @@ xe-$(CONFIG_DRM_XE_GPUSVM) += xe_svm.o
xe-$(CONFIG_DRM_GPUSVM) += xe_userptr.o
# debugging shaders with gdb (eudebug) support
-xe-$(CONFIG_DRM_XE_EUDEBUG) += xe_eudebug.o xe_eudebug_vm.o xe_eudebug_hw.o xe_gt_debug.o
+xe-$(CONFIG_DRM_XE_EUDEBUG) += xe_eudebug.o xe_eudebug_vm.o xe_eudebug_hw.o xe_eudebug_pagefault.o xe_gt_debug.o
# graphics hardware monitoring (HWMON) support
xe-$(CONFIG_HWMON) += xe_hwmon.o
diff --git a/drivers/gpu/drm/xe/xe_eudebug.c b/drivers/gpu/drm/xe/xe_eudebug.c
index 3f22924a1275..06cbb3de57f4 100644
--- a/drivers/gpu/drm/xe/xe_eudebug.c
+++ b/drivers/gpu/drm/xe/xe_eudebug.c
@@ -17,11 +17,15 @@
#include "xe_eudebug.h"
#include "xe_eudebug_hw.h"
#include "xe_eudebug_types.h"
+#include "xe_eudebug_pagefault.h"
#include "xe_eudebug_vm.h"
#include "xe_exec_queue.h"
+#include "xe_force_wake.h"
#include "xe_gt.h"
#include "xe_gt_debug.h"
+#include "xe_gt_mcr.h"
#include "xe_hw_engine.h"
+#include "regs/xe_gt_regs.h"
#include "xe_macros.h"
#include "xe_pm.h"
#include "xe_sriov_pf.h"
@@ -261,9 +265,12 @@ static void xe_eudebug_free(struct kref *ref)
while (kfifo_get(&d->events.fifo, &event))
kfree(event);
+ xe_eudebug_pagefault_fini(d);
xe_eudebug_resources_destroy(d);
+ mutex_destroy(&d->pf_lock);
mutex_destroy(&d->hw.lock);
mutex_destroy(&d->target.lock);
+
XE_WARN_ON(d->target.xef);
xe_eudebug_assert(d, !kfifo_len(&d->events.fifo));
@@ -440,7 +447,7 @@ static bool xe_eudebug_detach(struct xe_device *xe,
eu_dbg(d, "session %lld detached with %d", d->session, err);
release_acks(d);
-
+ xe_eudebug_pagefault_signal(target);
remove_debugger(target);
xe_file_put(target);
@@ -1939,10 +1946,6 @@ static int xe_eudebug_handle_gt_attention(struct xe_gt *gt)
{
int ret;
- ret = xe_gt_eu_threads_needing_attention(gt);
- if (ret <= 0)
- return ret;
-
ret = xe_send_gt_attention(gt);
/* Discovery in progress, fake it */
@@ -1952,6 +1955,65 @@ static int xe_eudebug_handle_gt_attention(struct xe_gt *gt)
return ret;
}
+int xe_eudebug_send_pagefault_event(struct xe_eudebug *d,
+ struct xe_eudebug_pagefault *pf)
+{
+ struct drm_xe_eudebug_event_pagefault *ep;
+ struct drm_xe_eudebug_event *event;
+ int h_queue, h_lrc;
+ u32 size = xe_gt_eu_attention_bitmap_size(pf->q->gt) * 3;
+ u32 sz = struct_size(ep, bitmask, size);
+ int ret;
+
+ XE_WARN_ON(pf->lrc_idx < 0 || pf->lrc_idx >= pf->q->width);
+
+ XE_WARN_ON(!xe_exec_queue_is_debuggable(pf->q));
+
+ h_queue = find_handle(d, XE_EUDEBUG_RES_TYPE_EXEC_QUEUE, pf->q);
+ if (h_queue < 0)
+ return h_queue;
+
+ h_lrc = find_handle(d, XE_EUDEBUG_RES_TYPE_LRC, pf->q->lrc[pf->lrc_idx]);
+ if (h_lrc < 0)
+ return h_lrc;
+
+ event = xe_eudebug_create_event(d, DRM_XE_EUDEBUG_EVENT_PAGEFAULT, 0,
+ DRM_XE_EUDEBUG_EVENT_STATE_CHANGE, sz);
+
+ if (!event)
+ return -ENOSPC;
+
+ ep = cast_event(ep, event);
+ ep->exec_queue_handle = h_queue;
+ ep->lrc_handle = h_lrc;
+ ep->bitmask_size = size;
+ ep->pagefault_address = pf->fault.addr;
+
+ memcpy(ep->bitmask, pf->attentions.before.att, pf->attentions.before.size);
+ memcpy(ep->bitmask + pf->attentions.before.size,
+ pf->attentions.after.att, pf->attentions.after.size);
+ memcpy(ep->bitmask + pf->attentions.before.size + pf->attentions.after.size,
+ pf->attentions.resolved.att, pf->attentions.resolved.size);
+
+ event->seqno = atomic_long_inc_return(&d->events.seqno);
+
+ ret = xe_eudebug_queue_event(d, event);
+ if (ret)
+ xe_eudebug_disconnect(d, ret);
+
+ return ret;
+}
+
+static void handle_attention_fail(struct xe_gt *gt, int gt_id, int ret)
+{
+ /* TODO: error capture */
+ drm_info(>_to_xe(gt)->drm,
+ "gt:%d unable to handle eu attention ret = %d\n",
+ gt_id, ret);
+
+ xe_gt_reset_async(gt);
+}
+
static void attention_poll_work(struct work_struct *work)
{
struct xe_device *xe = container_of(work, typeof(*xe),
@@ -1975,15 +2037,15 @@ static void attention_poll_work(struct work_struct *work)
if (gt->info.type != XE_GT_TYPE_MAIN)
continue;
- ret = xe_eudebug_handle_gt_attention(gt);
- if (ret) {
- /* TODO: error capture */
- drm_info(>_to_xe(gt)->drm,
- "gt:%d unable to handle eu attention ret=%d\n",
- gt_id, ret);
+ if (!xe_gt_eu_threads_needing_attention(gt))
+ continue;
+
+ ret = xe_eudebug_handle_pagefaults(gt);
+ if (!ret)
+ ret = xe_eudebug_handle_gt_attention(gt);
- xe_gt_reset_async(gt);
- }
+ if (ret)
+ handle_attention_fail(gt, gt_id, ret);
}
xe_pm_runtime_put(xe);
@@ -1992,12 +2054,12 @@ static void attention_poll_work(struct work_struct *work)
schedule_delayed_work(&xe->eudebug.attention_dwork, delay);
}
-static void attention_poll_stop(struct xe_device *xe)
+void xe_eudebug_attention_poll_stop(struct xe_device *xe)
{
cancel_delayed_work_sync(&xe->eudebug.attention_dwork);
}
-static void attention_poll_start(struct xe_device *xe)
+void xe_eudebug_attention_poll_start(struct xe_device *xe)
{
mod_delayed_work(system_wq, &xe->eudebug.attention_dwork, 0);
}
@@ -2042,6 +2104,8 @@ xe_eudebug_connect(struct xe_device *xe,
kref_init(&d->ref);
mutex_init(&d->target.lock);
mutex_init(&d->hw.lock);
+ mutex_init(&d->pf_lock);
+ INIT_LIST_HEAD(&d->pagefaults);
init_waitqueue_head(&d->events.write_done);
init_waitqueue_head(&d->events.read_done);
init_completion(&d->discovery);
@@ -2079,7 +2143,7 @@ xe_eudebug_connect(struct xe_device *xe,
kref_get(&d->ref); /* for discovery */
queue_work(xe->eudebug.wq, &d->discovery_work);
- attention_poll_start(xe);
+ xe_eudebug_attention_poll_start(xe);
eu_dbg(d, "connected session %lld", d->session);
@@ -2092,6 +2156,7 @@ xe_eudebug_connect(struct xe_device *xe,
err_free_res:
xe_eudebug_resources_destroy(d);
err_free:
+ mutex_destroy(&d->pf_lock);
mutex_destroy(&d->hw.lock);
mutex_destroy(&d->target.lock);
kfree(d);
@@ -2101,6 +2166,7 @@ xe_eudebug_connect(struct xe_device *xe,
void xe_eudebug_file_close(struct xe_file *xef)
{
+ xe_eudebug_pagefault_signal(xef);
remove_debugger(xef);
}
@@ -2162,9 +2228,9 @@ int xe_eudebug_enable(struct xe_device *xe, bool enable)
mutex_unlock(&xe->eudebug.lock);
if (enable) {
- attention_poll_start(xe);
+ xe_eudebug_attention_poll_start(xe);
} else {
- attention_poll_stop(xe);
+ xe_eudebug_attention_poll_stop(xe);
if (IS_SRIOV_PF(xe))
xe_sriov_pf_end_lockdown(xe);
@@ -2217,7 +2283,7 @@ static void xe_eudebug_fini(struct drm_device *dev, void *__unused)
xe_assert(xe, list_empty(&xe->eudebug.targets));
- attention_poll_stop(xe);
+ xe_eudebug_attention_poll_stop(xe);
}
void xe_eudebug_init(struct xe_device *xe)
diff --git a/drivers/gpu/drm/xe/xe_eudebug.h b/drivers/gpu/drm/xe/xe_eudebug.h
index b1f8a5fcc890..826b63c4ba09 100644
--- a/drivers/gpu/drm/xe/xe_eudebug.h
+++ b/drivers/gpu/drm/xe/xe_eudebug.h
@@ -13,12 +13,14 @@ struct drm_file;
struct xe_debug_data;
struct xe_device;
struct xe_file;
+struct xe_gt;
struct xe_vm;
struct xe_vma;
struct xe_vma_ops;
struct xe_exec_queue;
struct xe_user_fence;
struct xe_eudebug;
+struct xe_eudebug_pagefault;
#if IS_ENABLED(CONFIG_DRM_XE_EUDEBUG)
@@ -76,6 +78,12 @@ struct xe_eudebug *xe_eudebug_get_nolock(struct xe_file *xef);
struct xe_eudebug *xe_eudebug_get_nolock_with_discovery(struct xe_file *xef);
void xe_eudebug_put(struct xe_eudebug *d);
+int xe_eudebug_send_pagefault_event(struct xe_eudebug *d,
+ struct xe_eudebug_pagefault *pf);
+
+void xe_eudebug_attention_poll_stop(struct xe_device *xe);
+void xe_eudebug_attention_poll_start(struct xe_device *xe);
+
#else
static inline int xe_eudebug_connect_ioctl(struct drm_device *dev,
diff --git a/drivers/gpu/drm/xe/xe_eudebug_hw.c b/drivers/gpu/drm/xe/xe_eudebug_hw.c
index e6510e7b51a9..d67530ace186 100644
--- a/drivers/gpu/drm/xe/xe_eudebug_hw.c
+++ b/drivers/gpu/drm/xe/xe_eudebug_hw.c
@@ -340,6 +340,7 @@ static int do_eu_control(struct xe_eudebug *d,
void __user * const bitmask_ptr = u64_to_user_ptr(arg->bitmask_ptr);
struct xe_device *xe = d->xe;
struct xe_exec_queue *q, *active;
+ struct dma_fence *pf_fence;
struct xe_lrc *lrc;
unsigned int hw_attn_size, attn_size;
u8 *bits = NULL;
@@ -411,8 +412,20 @@ static int do_eu_control(struct xe_eudebug *d,
goto out_free;
}
- ret = -EINVAL;
mutex_lock(&d->hw.lock);
+ do {
+ pf_fence = dma_fence_get(d->pf_fence);
+ if (pf_fence) {
+ mutex_unlock(&d->hw.lock);
+ ret = dma_fence_wait(pf_fence, true);
+ dma_fence_put(pf_fence);
+ if (ret)
+ goto out_free;
+ mutex_lock(&d->hw.lock);
+ }
+ } while (pf_fence);
+
+ ret = -EINVAL;
switch (arg->cmd) {
case DRM_XE_EUDEBUG_EU_CONTROL_CMD_INTERRUPT_ALL:
diff --git a/drivers/gpu/drm/xe/xe_eudebug_pagefault.c b/drivers/gpu/drm/xe/xe_eudebug_pagefault.c
new file mode 100644
index 000000000000..15389fcd042f
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_eudebug_pagefault.c
@@ -0,0 +1,412 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2023-2025 Intel Corporation
+ */
+
+#include "xe_eudebug_pagefault.h"
+
+#include <linux/delay.h>
+
+#include "xe_exec_queue.h"
+#include "xe_eudebug.h"
+#include "xe_eudebug_hw.h"
+#include "xe_force_wake.h"
+#include "xe_gt_debug.h"
+#include "xe_gt_mcr.h"
+#include "regs/xe_gt_regs.h"
+#include "xe_vm.h"
+
+static struct xe_gt *
+epf_to_gt(struct xe_eudebug_pagefault *epf)
+{
+ return epf->q->gt;
+}
+
+static void destroy_pagefault(struct xe_eudebug_pagefault *epf)
+{
+ xe_exec_queue_put(epf->q);
+ kfree(epf);
+}
+
+static void queue_pagefault(struct xe_eudebug *d,
+ struct xe_eudebug_pagefault *epf)
+{
+ mutex_lock(&d->pf_lock);
+ list_add_tail(&epf->link, &d->pagefaults);
+ mutex_unlock(&d->pf_lock);
+}
+
+static const char *
+pagefault_get_driver_name(struct dma_fence *dma_fence)
+{
+ return "xe";
+}
+
+static const char *
+pagefault_fence_get_timeline_name(struct dma_fence *dma_fence)
+{
+ return "eudebug_pagefault_fence";
+}
+
+static const struct dma_fence_ops pagefault_fence_ops = {
+ .get_driver_name = pagefault_get_driver_name,
+ .get_timeline_name = pagefault_fence_get_timeline_name,
+};
+
+struct pagefault_fence {
+ struct dma_fence base;
+ spinlock_t lock;
+};
+
+static struct pagefault_fence *pagefault_fence_create(void)
+{
+ struct pagefault_fence *fence;
+
+ fence = kzalloc_obj(*fence, GFP_KERNEL);
+ if (fence == NULL)
+ return NULL;
+
+ spin_lock_init(&fence->lock);
+ dma_fence_init(&fence->base, &pagefault_fence_ops, &fence->lock,
+ dma_fence_context_alloc(1), 1);
+
+ return fence;
+}
+
+static void xe_eudebug_pagefault_set_private(struct xe_pagefault *pf,
+ struct xe_eudebug_pagefault *epf)
+{
+ u64 private = (u64)pf->producer.private;
+
+ XE_WARN_ON(private & XE_EUDEBUG_PAGEFAULT_PRIVATE_EUDEBUG);
+
+ epf->private = pf->producer.private;
+ private = (u64)epf | XE_EUDEBUG_PAGEFAULT_PRIVATE_EUDEBUG;
+ pf->producer.private = (void *)private;
+}
+
+void *xe_eudebug_pagefault_get_private(void *private)
+{
+ if ((u64)private & XE_EUDEBUG_PAGEFAULT_PRIVATE_EUDEBUG) {
+ struct xe_eudebug_pagefault *epf = (void *)((u64)private &
+ ~XE_EUDEBUG_PAGEFAULT_PRIVATE_EUDEBUG);
+ return epf->private;
+ }
+ return private;
+}
+
+int
+xe_eudebug_pagefault_create(struct xe_vm *vm, struct xe_pagefault *pf)
+{
+ struct pagefault_fence *pf_fence;
+ struct xe_eudebug_pagefault *epf;
+ struct xe_gt *gt = pf->gt;
+ struct xe_exec_queue *q;
+ struct dma_fence *fence;
+ struct xe_eudebug *d;
+ unsigned int fw_ref;
+ int lrc_idx;
+ u32 td_ctl;
+
+ d = xe_eudebug_get_nolock_with_discovery(vm->xef);
+ if (!d)
+ return -ENOENT;
+
+ q = xe_gt_runalone_active_queue_get(gt, &lrc_idx);
+ if (IS_ERR(q))
+ goto err_put_eudebug;
+
+ if (XE_WARN_ON(q->vm != vm))
+ goto err_put_exec_queue;
+
+ if (!xe_exec_queue_is_debuggable(q))
+ goto err_put_exec_queue;
+
+ fw_ref = xe_force_wake_get(gt_to_fw(gt), q->hwe->domain);
+ if (!fw_ref)
+ goto err_put_exec_queue;
+
+ /*
+ * If there is no debug functionality (TD_CTL_GLOBAL_DEBUG_ENABLE, etc.),
+ * don't proceed pagefault routine for eu debugger.
+ */
+ td_ctl = xe_gt_mcr_unicast_read_any(gt, TD_CTL);
+ if (!td_ctl)
+ goto err_put_fw;
+
+ epf = kzalloc_obj(*epf, GFP_KERNEL);
+ if (!epf)
+ goto err_put_fw;
+
+ xe_eudebug_attention_poll_stop(gt_to_xe(gt));
+
+ mutex_lock(&d->hw.lock);
+ fence = dma_fence_get(d->pf_fence);
+
+ if (fence) {
+ /*
+ * Unless there are parallel PF routines this should
+ * not happen.
+ */
+ dma_fence_put(fence);
+ goto err_unlock_hw_lock;
+ }
+
+ pf_fence = pagefault_fence_create();
+ if (!pf_fence)
+ goto err_unlock_hw_lock;
+
+ d->pf_fence = &pf_fence->base;
+
+ INIT_LIST_HEAD(&epf->link);
+
+ xe_gt_eu_attentions_read(gt, &epf->attentions.before, 0);
+
+ if (td_ctl & TD_CTL_FORCE_EXCEPTION)
+ eu_warn(d, "force exception already set!");
+
+ /* Halt regardless of thread dependencies */
+ while (!(td_ctl & TD_CTL_FORCE_EXCEPTION)) {
+ xe_gt_mcr_multicast_write(gt, TD_CTL,
+ td_ctl | TD_CTL_FORCE_EXCEPTION);
+ udelay(200);
+ td_ctl = xe_gt_mcr_unicast_read_any(gt, TD_CTL);
+ }
+
+ xe_gt_eu_attentions_read(gt, &epf->attentions.after,
+ XE_GT_ATTENTION_TIMEOUT_MS);
+
+ mutex_unlock(&d->hw.lock);
+
+ /*
+ * xe_exec_queue_put() will be called from destroy_pagefault()
+ * or handle_pagefault()
+ */
+ epf->q = q;
+ epf->lrc_idx = lrc_idx;
+ epf->fault.addr = pf->consumer.page_addr;
+ epf->fault.type_level = pf->consumer.fault_type_level;
+ epf->fault.access_type = pf->consumer.access_type;
+
+ xe_force_wake_put(gt_to_fw(gt), fw_ref);
+ xe_eudebug_put(d);
+
+ xe_eudebug_pagefault_set_private(pf, epf);
+
+ return 0;
+
+err_unlock_hw_lock:
+ mutex_unlock(&d->hw.lock);
+ xe_eudebug_attention_poll_start(gt_to_xe(gt));
+ kfree(epf);
+err_put_fw:
+ xe_force_wake_put(gt_to_fw(gt), fw_ref);
+err_put_exec_queue:
+ xe_exec_queue_put(q);
+err_put_eudebug:
+ xe_eudebug_put(d);
+
+ return -EINVAL;
+}
+
+static struct xe_eudebug_pagefault *xe_debubug_get_epf(struct xe_pagefault *pf)
+{
+ u64 private = (u64)pf->producer.private;
+
+ if (private & XE_EUDEBUG_PAGEFAULT_PRIVATE_EUDEBUG)
+ return (void *)(private & ~XE_EUDEBUG_PAGEFAULT_PRIVATE_EUDEBUG);
+
+ return NULL;
+}
+
+struct xe_vma *xe_eudebug_create_vma(struct xe_vm *vm, struct xe_pagefault *pf)
+{
+ struct xe_vma *vma = NULL;
+ struct xe_eudebug_pagefault *epf = xe_debubug_get_epf(pf);
+
+ if (!epf)
+ return NULL;
+
+ vma = xe_vm_create_null_vma(vm, pf->consumer.page_addr);
+ if (IS_ERR(vma))
+ return vma;
+
+ return vma;
+}
+
+static void
+xe_eudebug_pagefault_process(struct xe_eudebug_pagefault *epf)
+{
+ struct xe_gt *gt = epf_to_gt(epf);
+
+ xe_gt_eu_attentions_read(gt, &epf->attentions.resolved,
+ XE_GT_ATTENTION_TIMEOUT_MS);
+}
+
+static int send_queued_pagefaults_locked(struct xe_eudebug *d)
+{
+ struct xe_eudebug_pagefault *epf, *epf_temp;
+ int ret = 0;
+
+ list_for_each_entry_safe(epf, epf_temp, &d->pagefaults, link) {
+ ret = xe_eudebug_send_pagefault_event(d, epf);
+
+ list_del(&epf->link);
+
+ destroy_pagefault(epf);
+
+ if (ret)
+ break;
+ }
+ return ret;
+}
+
+static int send_queued_pagefaults(struct xe_eudebug *d)
+{
+ int ret = 0;
+
+ mutex_lock(&d->pf_lock);
+ ret = send_queued_pagefaults_locked(d);
+ mutex_unlock(&d->pf_lock);
+
+ return ret;
+}
+
+static void
+_xe_eudebug_pagefault_destroy(struct xe_eudebug_pagefault *epf, int err)
+{
+ struct xe_gt *gt = epf_to_gt(epf);
+ struct xe_vm *vm = epf->q->vm;
+ struct xe_eudebug *d;
+ struct dma_fence *f;
+ unsigned int fw_ref;
+ bool queued = false;
+ u32 td_ctl, ret = 0;
+
+ fw_ref = xe_force_wake_get(gt_to_fw(gt), epf->q->hwe->domain);
+ if (!fw_ref) {
+ struct xe_device *xe = gt_to_xe(gt);
+
+ drm_warn(&xe->drm, "Forcewake fail: Can not recover TD_CTL");
+ } else {
+ td_ctl = xe_gt_mcr_unicast_read_any(gt, TD_CTL);
+ xe_gt_mcr_multicast_write(gt, TD_CTL, td_ctl &
+ ~(TD_CTL_FORCE_EXCEPTION));
+ xe_force_wake_put(gt_to_fw(gt), fw_ref);
+ }
+
+ d = xe_eudebug_get_nolock_with_discovery(vm->xef);
+ if (!d)
+ goto epf_free;
+
+ if (!err) {
+ if (completion_done(&d->discovery)) {
+ /* Just in case there was a discovery */
+ ret = send_queued_pagefaults_locked(d);
+ if (!ret)
+ ret = xe_eudebug_send_pagefault_event(d, epf);
+ } else {
+ queue_pagefault(d, epf);
+ queued = true;
+ }
+ }
+
+ mutex_lock(&d->hw.lock);
+ f = d->pf_fence;
+ d->pf_fence = NULL;
+ mutex_unlock(&d->hw.lock);
+
+ if (f) {
+ dma_fence_signal(f);
+ dma_fence_put(f);
+ }
+
+ xe_eudebug_put(d);
+
+ epf_free:
+ if (!queued || ret)
+ destroy_pagefault(epf);
+
+ xe_eudebug_attention_poll_start(gt_to_xe(gt));
+}
+
+int xe_eudebug_handle_pagefaults(struct xe_gt *gt)
+{
+ struct xe_exec_queue *q;
+ struct xe_eudebug *d;
+ int ret, lrc_idx;
+
+ q = xe_gt_runalone_active_queue_get(gt, &lrc_idx);
+ if (IS_ERR(q))
+ return PTR_ERR(q);
+
+ if (!xe_exec_queue_is_debuggable(q)) {
+ ret = -EPERM;
+ goto out_exec_queue_put;
+ }
+
+ d = xe_eudebug_get_nolock(q->vm->xef);
+ if (!d) {
+ ret = -ENOTCONN;
+ goto out_exec_queue_put;
+ }
+
+ ret = send_queued_pagefaults(d);
+
+ xe_eudebug_put(d);
+
+out_exec_queue_put:
+ xe_exec_queue_put(q);
+
+ return ret;
+}
+
+void xe_eudebug_pagefault_service(struct xe_pagefault *pf, int err)
+{
+ struct xe_eudebug_pagefault *epf = xe_debubug_get_epf(pf);
+
+ if (!epf)
+ return;
+
+ if (!err)
+ xe_eudebug_pagefault_process(epf);
+
+ _xe_eudebug_pagefault_destroy(epf, err);
+}
+
+void xe_eudebug_pagefault_fini(struct xe_eudebug *d)
+{
+ struct xe_eudebug_pagefault *epf, *epf_temp;
+
+ /* Since it's the last reference no race here */
+
+ list_for_each_entry_safe(epf, epf_temp, &d->pagefaults, link) {
+ list_del(&epf->link);
+ destroy_pagefault(epf);
+ }
+
+ XE_WARN_ON(d->pf_fence);
+}
+
+void xe_eudebug_pagefault_signal(struct xe_file *xef)
+{
+ struct xe_eudebug *d;
+ struct dma_fence *f;
+
+ mutex_lock(&xef->eudebug.lock);
+ d = xef->eudebug.debugger;
+ mutex_unlock(&xef->eudebug.lock);
+
+ if (!d)
+ return;
+
+ mutex_lock(&d->hw.lock);
+ f = d->pf_fence;
+ d->pf_fence = NULL;
+ mutex_unlock(&d->hw.lock);
+
+ if (f) {
+ dma_fence_signal(f);
+ dma_fence_put(f);
+ }
+}
diff --git a/drivers/gpu/drm/xe/xe_eudebug_pagefault.h b/drivers/gpu/drm/xe/xe_eudebug_pagefault.h
new file mode 100644
index 000000000000..c7434e1c3bd3
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_eudebug_pagefault.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023-2025 Intel Corporation
+ */
+
+#ifndef _XE_EUDEBUG_PAGEFAULT_H_
+#define _XE_EUDEBUG_PAGEFAULT_H_
+
+#include <linux/types.h>
+
+struct xe_eudebug;
+struct xe_gt;
+struct xe_pagefault;
+struct xe_eudebug_pagefault;
+struct xe_vm;
+struct xe_file;
+
+void xe_eudebug_pagefault_fini(struct xe_eudebug *d);
+int xe_eudebug_handle_pagefaults(struct xe_gt *gt);
+
+#if IS_ENABLED(CONFIG_DRM_XE_EUDEBUG)
+int xe_eudebug_pagefault_create(struct xe_vm *vm, struct xe_pagefault *pf);
+struct xe_vma *xe_eudebug_create_vma(struct xe_vm *vm, struct xe_pagefault *pf);
+void xe_eudebug_pagefault_service(struct xe_pagefault *pf, int err);
+/*
+ * The (struct xe_pagefault *)->producer.private is a pointer which, for now,
+ * stores the pointer guc.
+ * EU Debug intercepts this pointer to store struct xe_eudebug_pagefault.
+ * Original pointer can be obtained via eudebug function below called with
+ * mentioned producer's private field.
+ */
+#define XE_EUDEBUG_PAGEFAULT_PRIVATE_EUDEBUG 0x1
+void *xe_eudebug_pagefault_get_private(void *private);
+
+void xe_eudebug_pagefault_signal(struct xe_file *xef);
+#else
+
+static inline int
+xe_eudebug_pagefault_create(struct xe_vm *vm, struct xe_pagefault *pf)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline struct xe_vma *xe_eudebug_create_vma(struct xe_vm *vm, struct xe_pagefault *pf)
+{
+ return NULL;
+}
+
+static inline void xe_eudebug_pagefault_service(struct xe_pagefault *pf, int err)
+{
+}
+
+static inline void *xe_eudebug_pagefault_get_private(void *private)
+{
+ return private;
+}
+
+static inline void xe_eudebug_pagefault_signal(struct xe_file *xef)
+{
+}
+#endif
+
+#endif /* _XE_EUDEBUG_PAGEFAULT_H_ */
diff --git a/drivers/gpu/drm/xe/xe_eudebug_types.h b/drivers/gpu/drm/xe/xe_eudebug_types.h
index 386b5c78ecff..46dac32fabf6 100644
--- a/drivers/gpu/drm/xe/xe_eudebug_types.h
+++ b/drivers/gpu/drm/xe/xe_eudebug_types.h
@@ -15,6 +15,8 @@
#include <linux/wait.h>
#include <linux/xarray.h>
+#include "xe_gt_debug_types.h"
+
struct xe_device;
struct task_struct;
struct xe_eudebug;
@@ -37,7 +39,7 @@ enum xe_eudebug_state {
};
#define CONFIG_DRM_XE_DEBUGGER_EVENT_QUEUE_SIZE 64
-#define XE_EUDEBUG_MAX_EVENT_TYPE DRM_XE_EUDEBUG_EVENT_EU_ATTENTION
+#define XE_EUDEBUG_MAX_EVENT_TYPE DRM_XE_EUDEBUG_EVENT_PAGEFAULT
/**
* struct xe_eudebug_handle - eudebug resource handle
@@ -164,6 +166,63 @@ struct xe_eudebug {
/** @ops: operations for eu_control */
struct xe_eudebug_eu_control_ops *ops;
+
+ /** @pf_lock: guards access to pagefaults list*/
+ struct mutex pf_lock;
+ /** @pagefaults: xe_eudebug_pagefault list for pagefault event queuing */
+ struct list_head pagefaults;
+ /**
+ * @pf_fence: fence on operations of eus (eu thread control and attention)
+ * when page faults are being handled, protected by @eu_lock.
+ */
+ struct dma_fence *pf_fence;
+};
+
+/**
+ * struct xe_eudebug_pagefault - eudebug structure for queuing pagefault
+ */
+struct xe_eudebug_pagefault {
+ /** @link: link into the xe_eudebug.pagefaults */
+ struct list_head link;
+ /** @q: exec_queue which raised pagefault */
+ struct xe_exec_queue *q;
+ /** @lrc_idx: lrc index of the workload which raised pagefault */
+ int lrc_idx;
+
+ /** @fault: pagefault raw partial data passed from guc */
+ struct {
+ /** @addr: ppgtt address where the pagefault occurred */
+ u64 addr;
+ u8 type_level;
+ u8 access_type;
+ } fault;
+
+ /** @attentions: attention states in different phases of fault */
+ struct {
+ /** @before: state of attention bits before page fault WA processing*/
+ struct xe_eu_attentions before;
+ /**
+ * @after: status of attention bits during page fault WA processing.
+ * It includes eu threads where attention bits are turned on for
+ * reasons other than page fault WA (breakpoint, interrupt, etc.).
+ */
+ struct xe_eu_attentions after;
+ /**
+ * @resolved: state of the attention bits after page fault WA.
+ * It includes the eu thread that caused the page fault.
+ * To determine the eu thread that caused the page fault,
+ * do XOR attentions.after and attentions.resolved.
+ */
+ struct xe_eu_attentions resolved;
+ } attentions;
+
+ /**
+ * @private: copied the (struct xe_pagefault *)->producer.private filed.
+ * EU Debugger masks private field in the struct xe_pagefault.
+ * The xe_eudebug_pagefault_get_private() function to extracts original
+ * private field regardless if it was shadowed or not.
+ */
+ void *private;
};
#endif /* _XE_EUDEBUG_TYPES_H_ */
diff --git a/drivers/gpu/drm/xe/xe_guc_pagefault.c b/drivers/gpu/drm/xe/xe_guc_pagefault.c
index 607e32392f46..038688ab63b4 100644
--- a/drivers/gpu/drm/xe/xe_guc_pagefault.c
+++ b/drivers/gpu/drm/xe/xe_guc_pagefault.c
@@ -4,6 +4,7 @@
*/
#include "abi/guc_actions_abi.h"
+#include "xe_eudebug_pagefault.h"
#include "xe_guc.h"
#include "xe_guc_ct.h"
#include "xe_guc_pagefault.h"
@@ -35,7 +36,7 @@ static void guc_ack_fault(struct xe_pagefault *pf, int err)
FIELD_PREP(PFR_ENG_CLASS, engine_class) |
FIELD_PREP(PFR_PDATA, pdata),
};
- struct xe_guc *guc = pf->producer.private;
+ struct xe_guc *guc = xe_eudebug_pagefault_get_private(pf->producer.private);
xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action), 0, 0);
}
diff --git a/drivers/gpu/drm/xe/xe_pagefault_types.h b/drivers/gpu/drm/xe/xe_pagefault_types.h
index c4ee625b93dd..ab38e135f23d 100644
--- a/drivers/gpu/drm/xe/xe_pagefault_types.h
+++ b/drivers/gpu/drm/xe/xe_pagefault_types.h
@@ -10,6 +10,7 @@
struct xe_gt;
struct xe_pagefault;
+struct xe_eudebug_pagefault;
/** enum xe_pagefault_access_type - Xe page fault access type */
enum xe_pagefault_access_type {
diff --git a/include/uapi/drm/xe_drm_eudebug.h b/include/uapi/drm/xe_drm_eudebug.h
index 54394a7e12ab..f7d035532be2 100644
--- a/include/uapi/drm/xe_drm_eudebug.h
+++ b/include/uapi/drm/xe_drm_eudebug.h
@@ -53,6 +53,7 @@ struct drm_xe_eudebug_event {
#define DRM_XE_EUDEBUG_EVENT_VM_BIND_OP_DEBUG_DATA 5
#define DRM_XE_EUDEBUG_EVENT_VM_BIND_UFENCE 6
#define DRM_XE_EUDEBUG_EVENT_EU_ATTENTION 7
+#define DRM_XE_EUDEBUG_EVENT_PAGEFAULT 8
/** @flags: Flags */
__u16 flags;
@@ -358,6 +359,17 @@ struct drm_xe_eudebug_event_eu_attention {
__u8 bitmask[];
};
+struct drm_xe_eudebug_event_pagefault {
+ struct drm_xe_eudebug_event base;
+
+ __u64 exec_queue_handle;
+ __u64 lrc_handle;
+ __u32 flags;
+ __u32 bitmask_size;
+ __u64 pagefault_address;
+ __u8 bitmask[];
+};
+
#if defined(__cplusplus)
}
#endif
--
2.43.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* Re: [PATCH 22/24] drm/xe/eudebug: Introduce EU pagefault handling interface
2026-04-30 10:51 ` [PATCH 22/24] drm/xe/eudebug: Introduce EU pagefault handling interface Mika Kuoppala
@ 2026-04-30 19:50 ` Gwan-gyeong Mun
0 siblings, 0 replies; 32+ messages in thread
From: Gwan-gyeong Mun @ 2026-04-30 19:50 UTC (permalink / raw)
To: Mika Kuoppala, intel-xe
Cc: simona.vetter, matthew.brost, christian.koenig, thomas.hellstrom,
joonas.lahtinen, gustavo.sousa, jan.maslak,
dominik.karol.piatkowski, rodrigo.vivi, andrzej.hajda,
matthew.auld, maciej.patelczyk
On 4/30/26 3:51 AM, Mika Kuoppala wrote:
> From: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
>
> The XE2 (and PVC) HW has a limitation that the pagefault due to invalid
> access will halt the corresponding EUs. To solve this problem, introduce
> EU pagefault handling functionality, which allows to unhalt pagefaulted
> eu threads and to EU debugger to get inform about the eu attentions state
> of EU threads during execution.
>
> If a pagefault occurs, send the DRM_XE_EUDEBUG_EVENT_PAGEFAULT event
> after handling the pagefault. The pagefault eudebug event follows
> the newly added drm_xe_eudebug_event_pagefault type.
> When a pagefault occurs, it prevents to send the
> DRM_XE_EUDEBUG_EVENT_EU_ATTENTION event to the client during pagefault
> handling.
>
> The page fault event delivery follows the below policy.
> (1) If EU Debugger discovery has completed and pagefaulted eu threads turn
> on attention bit then pagefault handler delivers pagefault event
> directly.
> (2) If a pagefault occurs during eu debugger discovery process, pagefault
> handler queues a pagefault event and sends the queued event when
> discovery has completed and pagefaulted eu threads turn on attention
> bit.
> (3) If the pagefaulted eu thread struggles to turn on the attention bit
> within the specified time, the attention scan worker sends a pagefault
> event when it detects that the attention bit is turned on.
>
> If multiple eu threads are running and a pagefault occurs due to accessing
> the same invalid address, send a single pagefault event
> (DRM_XE_EUDEBUG_EVENT_PAGEFAULT type) to the user debugger instead of a
> pagefault event for each of the multiple eu threads.
> If eu threads (other than the one that caused the page fault before) access
> the new invalid addresses, send a new pagefault event.
>
> As the attention scan worker send the eu attention event whenever the
> attention bit is turned on, user debugger receives attenion event
> immediately after pagefault event.
> In this case, the page-fault event always precedes the attention event.
>
> When the user debugger receives an attention event after a pagefault event,
> it can detect whether additional breakpoints or interrupts occur in
> addition to the existing pagefault by comparing the eu threads where the
> pagefault occurred with the eu threads where the attention bit is newly
> enabled.
>
> v2: use only force exception (Joonas, Mika)
> v3: rebased on v4 (Mika)
> v4: streamline uapi, cleanups (Mika)
> v5: struct member documentation (Mika)
> v6: fault to fault_type (Mika)
> v7: pagefault rework (Maciej)
>
> Cc: Matthew Brost <matthew.brost@intel.com>
> Cc: Gustavo Sousa <gustavo.sousa@intel.com>
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Signed-off-by: Jan Maślak <jan.maslak@intel.com>
> Signed-off-by: Maciej Patelczyk <maciej.patelczyk@intel.com>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/xe/Makefile | 2 +-
> drivers/gpu/drm/xe/xe_eudebug.c | 104 +++++-
> drivers/gpu/drm/xe/xe_eudebug.h | 8 +
> drivers/gpu/drm/xe/xe_eudebug_hw.c | 15 +-
> drivers/gpu/drm/xe/xe_eudebug_pagefault.c | 412 ++++++++++++++++++++++
> drivers/gpu/drm/xe/xe_eudebug_pagefault.h | 63 ++++
> drivers/gpu/drm/xe/xe_eudebug_types.h | 61 +++-
> drivers/gpu/drm/xe/xe_guc_pagefault.c | 3 +-
> drivers/gpu/drm/xe/xe_pagefault_types.h | 1 +
> include/uapi/drm/xe_drm_eudebug.h | 12 +
> 10 files changed, 658 insertions(+), 23 deletions(-)
> create mode 100644 drivers/gpu/drm/xe/xe_eudebug_pagefault.c
> create mode 100644 drivers/gpu/drm/xe/xe_eudebug_pagefault.h
>
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> index e43d89a45d39..53302104d05c 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -158,7 +158,7 @@ xe-$(CONFIG_DRM_XE_GPUSVM) += xe_svm.o
> xe-$(CONFIG_DRM_GPUSVM) += xe_userptr.o
>
> # debugging shaders with gdb (eudebug) support
> -xe-$(CONFIG_DRM_XE_EUDEBUG) += xe_eudebug.o xe_eudebug_vm.o xe_eudebug_hw.o xe_gt_debug.o
> +xe-$(CONFIG_DRM_XE_EUDEBUG) += xe_eudebug.o xe_eudebug_vm.o xe_eudebug_hw.o xe_eudebug_pagefault.o xe_gt_debug.o
>
> # graphics hardware monitoring (HWMON) support
> xe-$(CONFIG_HWMON) += xe_hwmon.o
> diff --git a/drivers/gpu/drm/xe/xe_eudebug.c b/drivers/gpu/drm/xe/xe_eudebug.c
> index 3f22924a1275..06cbb3de57f4 100644
> --- a/drivers/gpu/drm/xe/xe_eudebug.c
> +++ b/drivers/gpu/drm/xe/xe_eudebug.c
> @@ -17,11 +17,15 @@
> #include "xe_eudebug.h"
> #include "xe_eudebug_hw.h"
> #include "xe_eudebug_types.h"
> +#include "xe_eudebug_pagefault.h"
> #include "xe_eudebug_vm.h"
> #include "xe_exec_queue.h"
> +#include "xe_force_wake.h"
> #include "xe_gt.h"
> #include "xe_gt_debug.h"
> +#include "xe_gt_mcr.h"
> #include "xe_hw_engine.h"
> +#include "regs/xe_gt_regs.h"
> #include "xe_macros.h"
> #include "xe_pm.h"
> #include "xe_sriov_pf.h"
> @@ -261,9 +265,12 @@ static void xe_eudebug_free(struct kref *ref)
> while (kfifo_get(&d->events.fifo, &event))
> kfree(event);
>
> + xe_eudebug_pagefault_fini(d);
> xe_eudebug_resources_destroy(d);
> + mutex_destroy(&d->pf_lock);
> mutex_destroy(&d->hw.lock);
> mutex_destroy(&d->target.lock);
> +
> XE_WARN_ON(d->target.xef);
>
> xe_eudebug_assert(d, !kfifo_len(&d->events.fifo));
> @@ -440,7 +447,7 @@ static bool xe_eudebug_detach(struct xe_device *xe,
> eu_dbg(d, "session %lld detached with %d", d->session, err);
>
> release_acks(d);
> -
> + xe_eudebug_pagefault_signal(target);
> remove_debugger(target);
> xe_file_put(target);
>
> @@ -1939,10 +1946,6 @@ static int xe_eudebug_handle_gt_attention(struct xe_gt *gt)
> {
> int ret;
>
> - ret = xe_gt_eu_threads_needing_attention(gt);
> - if (ret <= 0)
> - return ret;
> -
> ret = xe_send_gt_attention(gt);
>
> /* Discovery in progress, fake it */
> @@ -1952,6 +1955,65 @@ static int xe_eudebug_handle_gt_attention(struct xe_gt *gt)
> return ret;
> }
>
> +int xe_eudebug_send_pagefault_event(struct xe_eudebug *d,
> + struct xe_eudebug_pagefault *pf)
> +{
> + struct drm_xe_eudebug_event_pagefault *ep;
> + struct drm_xe_eudebug_event *event;
> + int h_queue, h_lrc;
> + u32 size = xe_gt_eu_attention_bitmap_size(pf->q->gt) * 3;
> + u32 sz = struct_size(ep, bitmask, size);
> + int ret;
> +
> + XE_WARN_ON(pf->lrc_idx < 0 || pf->lrc_idx >= pf->q->width);
> +
> + XE_WARN_ON(!xe_exec_queue_is_debuggable(pf->q));
> +
> + h_queue = find_handle(d, XE_EUDEBUG_RES_TYPE_EXEC_QUEUE, pf->q);
> + if (h_queue < 0)
> + return h_queue;
> +
> + h_lrc = find_handle(d, XE_EUDEBUG_RES_TYPE_LRC, pf->q->lrc[pf->lrc_idx]);
> + if (h_lrc < 0)
> + return h_lrc;
> +
> + event = xe_eudebug_create_event(d, DRM_XE_EUDEBUG_EVENT_PAGEFAULT, 0,
> + DRM_XE_EUDEBUG_EVENT_STATE_CHANGE, sz);
> +
> + if (!event)
> + return -ENOSPC;
> +
> + ep = cast_event(ep, event);
> + ep->exec_queue_handle = h_queue;
> + ep->lrc_handle = h_lrc;
> + ep->bitmask_size = size;
> + ep->pagefault_address = pf->fault.addr;
> +
> + memcpy(ep->bitmask, pf->attentions.before.att, pf->attentions.before.size);
> + memcpy(ep->bitmask + pf->attentions.before.size,
> + pf->attentions.after.att, pf->attentions.after.size);
> + memcpy(ep->bitmask + pf->attentions.before.size + pf->attentions.after.size,
> + pf->attentions.resolved.att, pf->attentions.resolved.size);
> +
> + event->seqno = atomic_long_inc_return(&d->events.seqno);
> +
> + ret = xe_eudebug_queue_event(d, event);
> + if (ret)
> + xe_eudebug_disconnect(d, ret);
> +
> + return ret;
> +}
> +
> +static void handle_attention_fail(struct xe_gt *gt, int gt_id, int ret)
> +{
> + /* TODO: error capture */
> + drm_info(>_to_xe(gt)->drm,
> + "gt:%d unable to handle eu attention ret = %d\n",
> + gt_id, ret);
> +
> + xe_gt_reset_async(gt);
> +}
> +
> static void attention_poll_work(struct work_struct *work)
> {
> struct xe_device *xe = container_of(work, typeof(*xe),
> @@ -1975,15 +2037,15 @@ static void attention_poll_work(struct work_struct *work)
> if (gt->info.type != XE_GT_TYPE_MAIN)
> continue;
>
> - ret = xe_eudebug_handle_gt_attention(gt);
> - if (ret) {
> - /* TODO: error capture */
> - drm_info(>_to_xe(gt)->drm,
> - "gt:%d unable to handle eu attention ret=%d\n",
> - gt_id, ret);
> + if (!xe_gt_eu_threads_needing_attention(gt))
> + continue;
> +
> + ret = xe_eudebug_handle_pagefaults(gt);
> + if (!ret)
> + ret = xe_eudebug_handle_gt_attention(gt);
>
> - xe_gt_reset_async(gt);
> - }
> + if (ret)
> + handle_attention_fail(gt, gt_id, ret);
> }
>
> xe_pm_runtime_put(xe);
> @@ -1992,12 +2054,12 @@ static void attention_poll_work(struct work_struct *work)
> schedule_delayed_work(&xe->eudebug.attention_dwork, delay);
> }
>
> -static void attention_poll_stop(struct xe_device *xe)
> +void xe_eudebug_attention_poll_stop(struct xe_device *xe)
> {
> cancel_delayed_work_sync(&xe->eudebug.attention_dwork);
> }
>
> -static void attention_poll_start(struct xe_device *xe)
> +void xe_eudebug_attention_poll_start(struct xe_device *xe)
> {
> mod_delayed_work(system_wq, &xe->eudebug.attention_dwork, 0);
> }
> @@ -2042,6 +2104,8 @@ xe_eudebug_connect(struct xe_device *xe,
> kref_init(&d->ref);
> mutex_init(&d->target.lock);
> mutex_init(&d->hw.lock);
> + mutex_init(&d->pf_lock);
> + INIT_LIST_HEAD(&d->pagefaults);
> init_waitqueue_head(&d->events.write_done);
> init_waitqueue_head(&d->events.read_done);
> init_completion(&d->discovery);
> @@ -2079,7 +2143,7 @@ xe_eudebug_connect(struct xe_device *xe,
>
> kref_get(&d->ref); /* for discovery */
> queue_work(xe->eudebug.wq, &d->discovery_work);
> - attention_poll_start(xe);
> + xe_eudebug_attention_poll_start(xe);
>
> eu_dbg(d, "connected session %lld", d->session);
>
> @@ -2092,6 +2156,7 @@ xe_eudebug_connect(struct xe_device *xe,
> err_free_res:
> xe_eudebug_resources_destroy(d);
> err_free:
> + mutex_destroy(&d->pf_lock);
> mutex_destroy(&d->hw.lock);
> mutex_destroy(&d->target.lock);
> kfree(d);
> @@ -2101,6 +2166,7 @@ xe_eudebug_connect(struct xe_device *xe,
>
> void xe_eudebug_file_close(struct xe_file *xef)
> {
> + xe_eudebug_pagefault_signal(xef);
> remove_debugger(xef);
> }
>
> @@ -2162,9 +2228,9 @@ int xe_eudebug_enable(struct xe_device *xe, bool enable)
> mutex_unlock(&xe->eudebug.lock);
>
> if (enable) {
> - attention_poll_start(xe);
> + xe_eudebug_attention_poll_start(xe);
> } else {
> - attention_poll_stop(xe);
> + xe_eudebug_attention_poll_stop(xe);
>
> if (IS_SRIOV_PF(xe))
> xe_sriov_pf_end_lockdown(xe);
> @@ -2217,7 +2283,7 @@ static void xe_eudebug_fini(struct drm_device *dev, void *__unused)
>
> xe_assert(xe, list_empty(&xe->eudebug.targets));
>
> - attention_poll_stop(xe);
> + xe_eudebug_attention_poll_stop(xe);
> }
>
> void xe_eudebug_init(struct xe_device *xe)
> diff --git a/drivers/gpu/drm/xe/xe_eudebug.h b/drivers/gpu/drm/xe/xe_eudebug.h
> index b1f8a5fcc890..826b63c4ba09 100644
> --- a/drivers/gpu/drm/xe/xe_eudebug.h
> +++ b/drivers/gpu/drm/xe/xe_eudebug.h
> @@ -13,12 +13,14 @@ struct drm_file;
> struct xe_debug_data;
> struct xe_device;
> struct xe_file;
> +struct xe_gt;
> struct xe_vm;
> struct xe_vma;
> struct xe_vma_ops;
> struct xe_exec_queue;
> struct xe_user_fence;
> struct xe_eudebug;
> +struct xe_eudebug_pagefault;
>
> #if IS_ENABLED(CONFIG_DRM_XE_EUDEBUG)
>
> @@ -76,6 +78,12 @@ struct xe_eudebug *xe_eudebug_get_nolock(struct xe_file *xef);
> struct xe_eudebug *xe_eudebug_get_nolock_with_discovery(struct xe_file *xef);
> void xe_eudebug_put(struct xe_eudebug *d);
>
> +int xe_eudebug_send_pagefault_event(struct xe_eudebug *d,
> + struct xe_eudebug_pagefault *pf);
> +
> +void xe_eudebug_attention_poll_stop(struct xe_device *xe);
> +void xe_eudebug_attention_poll_start(struct xe_device *xe);
> +
> #else
>
> static inline int xe_eudebug_connect_ioctl(struct drm_device *dev,
> diff --git a/drivers/gpu/drm/xe/xe_eudebug_hw.c b/drivers/gpu/drm/xe/xe_eudebug_hw.c
> index e6510e7b51a9..d67530ace186 100644
> --- a/drivers/gpu/drm/xe/xe_eudebug_hw.c
> +++ b/drivers/gpu/drm/xe/xe_eudebug_hw.c
> @@ -340,6 +340,7 @@ static int do_eu_control(struct xe_eudebug *d,
> void __user * const bitmask_ptr = u64_to_user_ptr(arg->bitmask_ptr);
> struct xe_device *xe = d->xe;
> struct xe_exec_queue *q, *active;
> + struct dma_fence *pf_fence;
> struct xe_lrc *lrc;
> unsigned int hw_attn_size, attn_size;
> u8 *bits = NULL;
> @@ -411,8 +412,20 @@ static int do_eu_control(struct xe_eudebug *d,
> goto out_free;
> }
>
> - ret = -EINVAL;
> mutex_lock(&d->hw.lock);
> + do {
> + pf_fence = dma_fence_get(d->pf_fence);
> + if (pf_fence) {
> + mutex_unlock(&d->hw.lock);
> + ret = dma_fence_wait(pf_fence, true);
> + dma_fence_put(pf_fence);
> + if (ret)
> + goto out_free;
> + mutex_lock(&d->hw.lock);
> + }
> + } while (pf_fence);
> +
> + ret = -EINVAL;
>
> switch (arg->cmd) {
> case DRM_XE_EUDEBUG_EU_CONTROL_CMD_INTERRUPT_ALL:
> diff --git a/drivers/gpu/drm/xe/xe_eudebug_pagefault.c b/drivers/gpu/drm/xe/xe_eudebug_pagefault.c
> new file mode 100644
> index 000000000000..15389fcd042f
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_eudebug_pagefault.c
> @@ -0,0 +1,412 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2023-2025 Intel Corporation
> + */
> +
> +#include "xe_eudebug_pagefault.h"
> +
> +#include <linux/delay.h>
> +
> +#include "xe_exec_queue.h"
> +#include "xe_eudebug.h"
> +#include "xe_eudebug_hw.h"
> +#include "xe_force_wake.h"
> +#include "xe_gt_debug.h"
> +#include "xe_gt_mcr.h"
> +#include "regs/xe_gt_regs.h"
> +#include "xe_vm.h"
> +
> +static struct xe_gt *
> +epf_to_gt(struct xe_eudebug_pagefault *epf)
> +{
> + return epf->q->gt;
> +}
> +
> +static void destroy_pagefault(struct xe_eudebug_pagefault *epf)
> +{
> + xe_exec_queue_put(epf->q);
> + kfree(epf);
> +}
> +
> +static void queue_pagefault(struct xe_eudebug *d,
> + struct xe_eudebug_pagefault *epf)
> +{
> + mutex_lock(&d->pf_lock);
> + list_add_tail(&epf->link, &d->pagefaults);
> + mutex_unlock(&d->pf_lock);
> +}
> +
> +static const char *
> +pagefault_get_driver_name(struct dma_fence *dma_fence)
> +{
> + return "xe";
> +}
> +
> +static const char *
> +pagefault_fence_get_timeline_name(struct dma_fence *dma_fence)
> +{
> + return "eudebug_pagefault_fence";
> +}
> +
> +static const struct dma_fence_ops pagefault_fence_ops = {
> + .get_driver_name = pagefault_get_driver_name,
> + .get_timeline_name = pagefault_fence_get_timeline_name,
> +};
> +
> +struct pagefault_fence {
> + struct dma_fence base;
> + spinlock_t lock;
> +};
> +
> +static struct pagefault_fence *pagefault_fence_create(void)
> +{
> + struct pagefault_fence *fence;
> +
> + fence = kzalloc_obj(*fence, GFP_KERNEL);
> + if (fence == NULL)
> + return NULL;
> +
> + spin_lock_init(&fence->lock);
> + dma_fence_init(&fence->base, &pagefault_fence_ops, &fence->lock,
> + dma_fence_context_alloc(1), 1);
> +
> + return fence;
> +}
> +
> +static void xe_eudebug_pagefault_set_private(struct xe_pagefault *pf,
> + struct xe_eudebug_pagefault *epf)
> +{
> + u64 private = (u64)pf->producer.private;
> +
> + XE_WARN_ON(private & XE_EUDEBUG_PAGEFAULT_PRIVATE_EUDEBUG);
> +
> + epf->private = pf->producer.private;
> + private = (u64)epf | XE_EUDEBUG_PAGEFAULT_PRIVATE_EUDEBUG;
> + pf->producer.private = (void *)private;
> +}
> +
> +void *xe_eudebug_pagefault_get_private(void *private)
> +{
> + if ((u64)private & XE_EUDEBUG_PAGEFAULT_PRIVATE_EUDEBUG) {
> + struct xe_eudebug_pagefault *epf = (void *)((u64)private &
> + ~XE_EUDEBUG_PAGEFAULT_PRIVATE_EUDEBUG);
> + return epf->private;
> + }
> + return private;
> +}
> +
> +int
> +xe_eudebug_pagefault_create(struct xe_vm *vm, struct xe_pagefault *pf)
> +{
> + struct pagefault_fence *pf_fence;
> + struct xe_eudebug_pagefault *epf;
> + struct xe_gt *gt = pf->gt;
> + struct xe_exec_queue *q;
> + struct dma_fence *fence;
> + struct xe_eudebug *d;
> + unsigned int fw_ref;
> + int lrc_idx;
> + u32 td_ctl;
> +
> + d = xe_eudebug_get_nolock_with_discovery(vm->xef);
> + if (!d)
> + return -ENOENT;
> +
> + q = xe_gt_runalone_active_queue_get(gt, &lrc_idx);
> + if (IS_ERR(q))
> + goto err_put_eudebug;
> +
> + if (XE_WARN_ON(q->vm != vm))
> + goto err_put_exec_queue;
> +
> + if (!xe_exec_queue_is_debuggable(q))
> + goto err_put_exec_queue;
> +
> + fw_ref = xe_force_wake_get(gt_to_fw(gt), q->hwe->domain);
> + if (!fw_ref)
> + goto err_put_exec_queue;
> +
> + /*
> + * If there is no debug functionality (TD_CTL_GLOBAL_DEBUG_ENABLE, etc.),
> + * don't proceed pagefault routine for eu debugger.
> + */
> + td_ctl = xe_gt_mcr_unicast_read_any(gt, TD_CTL);
> + if (!td_ctl)
> + goto err_put_fw;
> +
> + epf = kzalloc_obj(*epf, GFP_KERNEL);
> + if (!epf)
> + goto err_put_fw;
> +
> + xe_eudebug_attention_poll_stop(gt_to_xe(gt));
> +
> + mutex_lock(&d->hw.lock);
> + fence = dma_fence_get(d->pf_fence);
> +
> + if (fence) {
> + /*
> + * Unless there are parallel PF routines this should
> + * not happen.
> + */
> + dma_fence_put(fence);
> + goto err_unlock_hw_lock;
> + }
> +
> + pf_fence = pagefault_fence_create();
> + if (!pf_fence)
> + goto err_unlock_hw_lock;
> +
> + d->pf_fence = &pf_fence->base;
> +
> + INIT_LIST_HEAD(&epf->link);
> +
> + xe_gt_eu_attentions_read(gt, &epf->attentions.before, 0);
> +
> + if (td_ctl & TD_CTL_FORCE_EXCEPTION)
> + eu_warn(d, "force exception already set!");
> +
> + /* Halt regardless of thread dependencies */
> + while (!(td_ctl & TD_CTL_FORCE_EXCEPTION)) {
> + xe_gt_mcr_multicast_write(gt, TD_CTL,
> + td_ctl | TD_CTL_FORCE_EXCEPTION);
> + udelay(200);
> + td_ctl = xe_gt_mcr_unicast_read_any(gt, TD_CTL);
> + }
> +
> + xe_gt_eu_attentions_read(gt, &epf->attentions.after,
> + XE_GT_ATTENTION_TIMEOUT_MS);
> +
> + mutex_unlock(&d->hw.lock);
> +
> + /*
> + * xe_exec_queue_put() will be called from destroy_pagefault()
> + * or handle_pagefault()
> + */
> + epf->q = q;
> + epf->lrc_idx = lrc_idx;
> + epf->fault.addr = pf->consumer.page_addr;
> + epf->fault.type_level = pf->consumer.fault_type_level;
> + epf->fault.access_type = pf->consumer.access_type;
> +
> + xe_force_wake_put(gt_to_fw(gt), fw_ref);
> + xe_eudebug_put(d);
> +
> + xe_eudebug_pagefault_set_private(pf, epf);
> +
> + return 0;
> +
> +err_unlock_hw_lock:
> + mutex_unlock(&d->hw.lock);
> + xe_eudebug_attention_poll_start(gt_to_xe(gt));
> + kfree(epf);
> +err_put_fw:
> + xe_force_wake_put(gt_to_fw(gt), fw_ref);
> +err_put_exec_queue:
> + xe_exec_queue_put(q);
> +err_put_eudebug:
> + xe_eudebug_put(d);
> +
> + return -EINVAL;
> +}
> +
> +static struct xe_eudebug_pagefault *xe_debubug_get_epf(struct xe_pagefault *pf)
> +{
> + u64 private = (u64)pf->producer.private;
> +
> + if (private & XE_EUDEBUG_PAGEFAULT_PRIVATE_EUDEBUG)
> + return (void *)(private & ~XE_EUDEBUG_PAGEFAULT_PRIVATE_EUDEBUG);
> +
> + return NULL;
> +}
> +
> +struct xe_vma *xe_eudebug_create_vma(struct xe_vm *vm, struct xe_pagefault *pf)
> +{
> + struct xe_vma *vma = NULL;
> + struct xe_eudebug_pagefault *epf = xe_debubug_get_epf(pf);
> +
> + if (!epf)
> + return NULL;
> +
> + vma = xe_vm_create_null_vma(vm, pf->consumer.page_addr);
> + if (IS_ERR(vma))
> + return vma;
> +
> + return vma;
> +}
> +
> +static void
> +xe_eudebug_pagefault_process(struct xe_eudebug_pagefault *epf)
> +{
> + struct xe_gt *gt = epf_to_gt(epf);
> +
> + xe_gt_eu_attentions_read(gt, &epf->attentions.resolved,
> + XE_GT_ATTENTION_TIMEOUT_MS);
> +}
> +
> +static int send_queued_pagefaults_locked(struct xe_eudebug *d)
> +{
> + struct xe_eudebug_pagefault *epf, *epf_temp;
> + int ret = 0;
> +
> + list_for_each_entry_safe(epf, epf_temp, &d->pagefaults, link) {
> + ret = xe_eudebug_send_pagefault_event(d, epf);
> +
> + list_del(&epf->link);
> +
> + destroy_pagefault(epf);
> +
> + if (ret)
> + break;
> + }
> + return ret;
> +}
> +
> +static int send_queued_pagefaults(struct xe_eudebug *d)
> +{
> + int ret = 0;
> +
> + mutex_lock(&d->pf_lock);
> + ret = send_queued_pagefaults_locked(d);
> + mutex_unlock(&d->pf_lock);
> +
> + return ret;
> +}
> +
> +static void
> +_xe_eudebug_pagefault_destroy(struct xe_eudebug_pagefault *epf, int err)
> +{
> + struct xe_gt *gt = epf_to_gt(epf);
> + struct xe_vm *vm = epf->q->vm;
> + struct xe_eudebug *d;
> + struct dma_fence *f;
> + unsigned int fw_ref;
> + bool queued = false;
> + u32 td_ctl, ret = 0;
> +
> + fw_ref = xe_force_wake_get(gt_to_fw(gt), epf->q->hwe->domain);
> + if (!fw_ref) {
> + struct xe_device *xe = gt_to_xe(gt);
> +
> + drm_warn(&xe->drm, "Forcewake fail: Can not recover TD_CTL");
> + } else {
> + td_ctl = xe_gt_mcr_unicast_read_any(gt, TD_CTL);
> + xe_gt_mcr_multicast_write(gt, TD_CTL, td_ctl &
> + ~(TD_CTL_FORCE_EXCEPTION));
> + xe_force_wake_put(gt_to_fw(gt), fw_ref);
> + }
> +
> + d = xe_eudebug_get_nolock_with_discovery(vm->xef);
> + if (!d)
> + goto epf_free;
> +
> + if (!err) {
> + if (completion_done(&d->discovery)) {
> + /* Just in case there was a discovery */
> + ret = send_queued_pagefaults_locked(d);
> + if (!ret)
> + ret = xe_eudebug_send_pagefault_event(d, epf);
> + } else {
> + queue_pagefault(d, epf);
> + queued = true;
> + }
> + }
> +
> + mutex_lock(&d->hw.lock);
> + f = d->pf_fence;
> + d->pf_fence = NULL;
> + mutex_unlock(&d->hw.lock);
> +
> + if (f) {
> + dma_fence_signal(f);
> + dma_fence_put(f);
> + }
> +
> + xe_eudebug_put(d);
> +
> + epf_free:
> + if (!queued || ret)
> + destroy_pagefault(epf);
> +
> + xe_eudebug_attention_poll_start(gt_to_xe(gt));
> +}
> +
> +int xe_eudebug_handle_pagefaults(struct xe_gt *gt)
> +{
> + struct xe_exec_queue *q;
> + struct xe_eudebug *d;
> + int ret, lrc_idx;
> +
> + q = xe_gt_runalone_active_queue_get(gt, &lrc_idx);
> + if (IS_ERR(q))
> + return PTR_ERR(q);
> +
> + if (!xe_exec_queue_is_debuggable(q)) {
> + ret = -EPERM;
> + goto out_exec_queue_put;
> + }
> +
> + d = xe_eudebug_get_nolock(q->vm->xef);
> + if (!d) {
> + ret = -ENOTCONN;
> + goto out_exec_queue_put;
> + }
> +
> + ret = send_queued_pagefaults(d);
> +
> + xe_eudebug_put(d);
> +
> +out_exec_queue_put:
> + xe_exec_queue_put(q);
> +
> + return ret;
> +}
> +
> +void xe_eudebug_pagefault_service(struct xe_pagefault *pf, int err)
> +{
> + struct xe_eudebug_pagefault *epf = xe_debubug_get_epf(pf);
> +
> + if (!epf)
> + return;
> +
> + if (!err)
> + xe_eudebug_pagefault_process(epf);
> +
> + _xe_eudebug_pagefault_destroy(epf, err);
> +}
> +
> +void xe_eudebug_pagefault_fini(struct xe_eudebug *d)
> +{
> + struct xe_eudebug_pagefault *epf, *epf_temp;
> +
> + /* Since it's the last reference no race here */
> +
> + list_for_each_entry_safe(epf, epf_temp, &d->pagefaults, link) {
> + list_del(&epf->link);
> + destroy_pagefault(epf);
> + }
> +
> + XE_WARN_ON(d->pf_fence);
> +}
> +
> +void xe_eudebug_pagefault_signal(struct xe_file *xef)
> +{
> + struct xe_eudebug *d;
> + struct dma_fence *f;
> +
> + mutex_lock(&xef->eudebug.lock);
> + d = xef->eudebug.debugger;
> + mutex_unlock(&xef->eudebug.lock);
> +
> + if (!d)
> + return;
> +
> + mutex_lock(&d->hw.lock);
> + f = d->pf_fence;
> + d->pf_fence = NULL;
> + mutex_unlock(&d->hw.lock);
> +
> + if (f) {
> + dma_fence_signal(f);
> + dma_fence_put(f);
> + }
> +}
> diff --git a/drivers/gpu/drm/xe/xe_eudebug_pagefault.h b/drivers/gpu/drm/xe/xe_eudebug_pagefault.h
> new file mode 100644
> index 000000000000..c7434e1c3bd3
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_eudebug_pagefault.h
> @@ -0,0 +1,63 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2023-2025 Intel Corporation
> + */
> +
> +#ifndef _XE_EUDEBUG_PAGEFAULT_H_
> +#define _XE_EUDEBUG_PAGEFAULT_H_
> +
> +#include <linux/types.h>
> +
> +struct xe_eudebug;
> +struct xe_gt;
> +struct xe_pagefault;
> +struct xe_eudebug_pagefault;
> +struct xe_vm;
> +struct xe_file;
> +
> +void xe_eudebug_pagefault_fini(struct xe_eudebug *d);
> +int xe_eudebug_handle_pagefaults(struct xe_gt *gt);
> +
> +#if IS_ENABLED(CONFIG_DRM_XE_EUDEBUG)
> +int xe_eudebug_pagefault_create(struct xe_vm *vm, struct xe_pagefault *pf);
> +struct xe_vma *xe_eudebug_create_vma(struct xe_vm *vm, struct xe_pagefault *pf);
> +void xe_eudebug_pagefault_service(struct xe_pagefault *pf, int err);
> +/*
> + * The (struct xe_pagefault *)->producer.private is a pointer which, for now,
> + * stores the pointer guc.
> + * EU Debug intercepts this pointer to store struct xe_eudebug_pagefault.
> + * Original pointer can be obtained via eudebug function below called with
> + * mentioned producer's private field.
> + */
> +#define XE_EUDEBUG_PAGEFAULT_PRIVATE_EUDEBUG 0x1
> +void *xe_eudebug_pagefault_get_private(void *private);
> +
> +void xe_eudebug_pagefault_signal(struct xe_file *xef);
> +#else
> +
in order to use EOPNOTSUPP, it should include `#include <linux/errno.h>`.
this version missed it.
G.G.> +static inline int
> +xe_eudebug_pagefault_create(struct xe_vm *vm, struct xe_pagefault *pf)
> +{
> + return -EOPNOTSUPP;
> +}
> +
> +static inline struct xe_vma *xe_eudebug_create_vma(struct xe_vm *vm, struct xe_pagefault *pf)
> +{
> + return NULL;
> +}
> +
> +static inline void xe_eudebug_pagefault_service(struct xe_pagefault *pf, int err)
> +{
> +}
> +
> +static inline void *xe_eudebug_pagefault_get_private(void *private)
> +{
> + return private;
> +}
> +
> +static inline void xe_eudebug_pagefault_signal(struct xe_file *xef)
> +{
> +}
> +#endif
> +
> +#endif /* _XE_EUDEBUG_PAGEFAULT_H_ */
> diff --git a/drivers/gpu/drm/xe/xe_eudebug_types.h b/drivers/gpu/drm/xe/xe_eudebug_types.h
> index 386b5c78ecff..46dac32fabf6 100644
> --- a/drivers/gpu/drm/xe/xe_eudebug_types.h
> +++ b/drivers/gpu/drm/xe/xe_eudebug_types.h
> @@ -15,6 +15,8 @@
> #include <linux/wait.h>
> #include <linux/xarray.h>
>
> +#include "xe_gt_debug_types.h"
> +
> struct xe_device;
> struct task_struct;
> struct xe_eudebug;
> @@ -37,7 +39,7 @@ enum xe_eudebug_state {
> };
>
> #define CONFIG_DRM_XE_DEBUGGER_EVENT_QUEUE_SIZE 64
> -#define XE_EUDEBUG_MAX_EVENT_TYPE DRM_XE_EUDEBUG_EVENT_EU_ATTENTION
> +#define XE_EUDEBUG_MAX_EVENT_TYPE DRM_XE_EUDEBUG_EVENT_PAGEFAULT
>
> /**
> * struct xe_eudebug_handle - eudebug resource handle
> @@ -164,6 +166,63 @@ struct xe_eudebug {
>
> /** @ops: operations for eu_control */
> struct xe_eudebug_eu_control_ops *ops;
> +
> + /** @pf_lock: guards access to pagefaults list*/
> + struct mutex pf_lock;
> + /** @pagefaults: xe_eudebug_pagefault list for pagefault event queuing */
> + struct list_head pagefaults;
> + /**
> + * @pf_fence: fence on operations of eus (eu thread control and attention)
> + * when page faults are being handled, protected by @eu_lock.
> + */
> + struct dma_fence *pf_fence;
> +};
> +
> +/**
> + * struct xe_eudebug_pagefault - eudebug structure for queuing pagefault
> + */
> +struct xe_eudebug_pagefault {
> + /** @link: link into the xe_eudebug.pagefaults */
> + struct list_head link;
> + /** @q: exec_queue which raised pagefault */
> + struct xe_exec_queue *q;
> + /** @lrc_idx: lrc index of the workload which raised pagefault */
> + int lrc_idx;
> +
> + /** @fault: pagefault raw partial data passed from guc */
> + struct {
> + /** @addr: ppgtt address where the pagefault occurred */
> + u64 addr;
> + u8 type_level;
> + u8 access_type;
> + } fault;
> +
> + /** @attentions: attention states in different phases of fault */
> + struct {
> + /** @before: state of attention bits before page fault WA processing*/
> + struct xe_eu_attentions before;
> + /**
> + * @after: status of attention bits during page fault WA processing.
> + * It includes eu threads where attention bits are turned on for
> + * reasons other than page fault WA (breakpoint, interrupt, etc.).
> + */
> + struct xe_eu_attentions after;
> + /**
> + * @resolved: state of the attention bits after page fault WA.
> + * It includes the eu thread that caused the page fault.
> + * To determine the eu thread that caused the page fault,
> + * do XOR attentions.after and attentions.resolved.
> + */
> + struct xe_eu_attentions resolved;
> + } attentions;
> +
> + /**
> + * @private: copied the (struct xe_pagefault *)->producer.private filed.
> + * EU Debugger masks private field in the struct xe_pagefault.
> + * The xe_eudebug_pagefault_get_private() function to extracts original
> + * private field regardless if it was shadowed or not.
> + */
> + void *private;
> };
>
> #endif /* _XE_EUDEBUG_TYPES_H_ */
> diff --git a/drivers/gpu/drm/xe/xe_guc_pagefault.c b/drivers/gpu/drm/xe/xe_guc_pagefault.c
> index 607e32392f46..038688ab63b4 100644
> --- a/drivers/gpu/drm/xe/xe_guc_pagefault.c
> +++ b/drivers/gpu/drm/xe/xe_guc_pagefault.c
> @@ -4,6 +4,7 @@
> */
>
> #include "abi/guc_actions_abi.h"
> +#include "xe_eudebug_pagefault.h"
> #include "xe_guc.h"
> #include "xe_guc_ct.h"
> #include "xe_guc_pagefault.h"
> @@ -35,7 +36,7 @@ static void guc_ack_fault(struct xe_pagefault *pf, int err)
> FIELD_PREP(PFR_ENG_CLASS, engine_class) |
> FIELD_PREP(PFR_PDATA, pdata),
> };
> - struct xe_guc *guc = pf->producer.private;
> + struct xe_guc *guc = xe_eudebug_pagefault_get_private(pf->producer.private);
>
> xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action), 0, 0);
> }
> diff --git a/drivers/gpu/drm/xe/xe_pagefault_types.h b/drivers/gpu/drm/xe/xe_pagefault_types.h
> index c4ee625b93dd..ab38e135f23d 100644
> --- a/drivers/gpu/drm/xe/xe_pagefault_types.h
> +++ b/drivers/gpu/drm/xe/xe_pagefault_types.h
> @@ -10,6 +10,7 @@
>
> struct xe_gt;
> struct xe_pagefault;
> +struct xe_eudebug_pagefault;
>
> /** enum xe_pagefault_access_type - Xe page fault access type */
> enum xe_pagefault_access_type {
> diff --git a/include/uapi/drm/xe_drm_eudebug.h b/include/uapi/drm/xe_drm_eudebug.h
> index 54394a7e12ab..f7d035532be2 100644
> --- a/include/uapi/drm/xe_drm_eudebug.h
> +++ b/include/uapi/drm/xe_drm_eudebug.h
> @@ -53,6 +53,7 @@ struct drm_xe_eudebug_event {
> #define DRM_XE_EUDEBUG_EVENT_VM_BIND_OP_DEBUG_DATA 5
> #define DRM_XE_EUDEBUG_EVENT_VM_BIND_UFENCE 6
> #define DRM_XE_EUDEBUG_EVENT_EU_ATTENTION 7
> +#define DRM_XE_EUDEBUG_EVENT_PAGEFAULT 8
>
> /** @flags: Flags */
> __u16 flags;
> @@ -358,6 +359,17 @@ struct drm_xe_eudebug_event_eu_attention {
> __u8 bitmask[];
> };
>
> +struct drm_xe_eudebug_event_pagefault {
> + struct drm_xe_eudebug_event base;
> +
> + __u64 exec_queue_handle;
> + __u64 lrc_handle;
> + __u32 flags;
> + __u32 bitmask_size;
> + __u64 pagefault_address;
> + __u8 bitmask[];
> +};
> +
> #if defined(__cplusplus)
> }
> #endif
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 23/24] drm/xe/eudebug: Enable EU pagefault handling
2026-04-30 10:50 [PATCH 00/24] Intel Xe GPU Debug Support (eudebug) v8 Mika Kuoppala
` (21 preceding siblings ...)
2026-04-30 10:51 ` [PATCH 22/24] drm/xe/eudebug: Introduce EU pagefault handling interface Mika Kuoppala
@ 2026-04-30 10:51 ` Mika Kuoppala
2026-04-30 10:51 ` [PATCH 24/24] drm/xe/eudebug: Disable SVM in Xe for Eudebug Mika Kuoppala
` (4 subsequent siblings)
27 siblings, 0 replies; 32+ messages in thread
From: Mika Kuoppala @ 2026-04-30 10:51 UTC (permalink / raw)
To: intel-xe
Cc: simona.vetter, matthew.brost, christian.koenig, thomas.hellstrom,
joonas.lahtinen, gustavo.sousa, jan.maslak,
dominik.karol.piatkowski, rodrigo.vivi, andrzej.hajda,
matthew.auld, maciej.patelczyk, gwan-gyeong.mun, Mika Kuoppala
From: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
The XE2 (and PVC) HW has a limitation that the pagefault due to invalid
access will halt the corresponding EUs. To solve this problem, enable
EU pagefault handling functionality, which allows to unhalt pagefaulted
eu threads and to EU debugger to get inform about the eu attentions state
of EU threads during execution.
If a pagefault occurs, send the DRM_XE_EUDEBUG_EVENT_PAGEFAULT event
after handling the pagefault.
The pagefault handling is a mechanism that allows a stalled EU thread to
enter SIP mode by installing a temporal null page to the page table entry
where the pagefault happened.
A brief description of the page fault handling mechanism flow between KMD
and the eu thread is as follows
(1) eu thread accesses unallocated address
(2) pagefault happens and eu thread stalls
(3) XE kmd set an force eu thread exception to allow the running eu thread
to enter SIP mode (kmd set ForceException / ForceExternalHalt bit of
TD_CTL register)
Not stalled (none-pagefaulted) eu threads enter SIP mode
(4) XE kmd installs temporal null page to the pagetable entry of the
address where pagefault happened.
(5) XE kmd replies pagefault successful message to GUC
(6) stalled eu thread resumes as per pagefault condition has resolved
(7) resumed eu thread enters SIP mode due to force exception set by (3)
(8) adapted to consumer/produced pagefaults
As designed this feature to only work when eudbug is enabled, it should
have no impact to regular recoverable pagefault code path.
v2: - pf->q holds the vm ref so drop it (Mika)
- streamline uapi (Mika)
- cleanup the pagefault through producer if (Mika)
v3: - pagefault rework (Maciej)
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: Maciej Patelczyk <maciej.patelczyk@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/xe/xe_device_types.h | 8 +++
drivers/gpu/drm/xe/xe_eudebug_pagefault.c | 5 ++
drivers/gpu/drm/xe/xe_eudebug_pagefault.h | 14 +++++
drivers/gpu/drm/xe/xe_guc_pagefault.c | 7 +++
drivers/gpu/drm/xe/xe_pagefault.c | 77 ++++++++++++++++++++---
drivers/gpu/drm/xe/xe_pagefault_types.h | 9 +++
6 files changed, 113 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 5d9569d5fd1a..826132dcab22 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -305,12 +305,20 @@ struct xe_device {
struct rw_semaphore lock;
/** @usm.pf_wq: page fault work queue, unbound, high priority */
struct workqueue_struct *pf_wq;
+#if IS_ENABLED(CONFIG_DRM_XE_EUDEBUG)
+ /*
+ * For EU Debug Pagefault workaround we need single queue
+ * to properly handle/ack incoming pagefaults.
+ */
+#define XE_PAGEFAULT_QUEUE_COUNT 1
+#else
/*
* We pick 4 here because, in the current implementation, it
* yields the best bandwidth utilization of the kernel paging
* engine.
*/
#define XE_PAGEFAULT_QUEUE_COUNT 4
+#endif
/** @usm.pf_queue: Page fault queues */
struct xe_pagefault_queue pf_queue[XE_PAGEFAULT_QUEUE_COUNT];
#if IS_ENABLED(CONFIG_DRM_XE_PAGEMAP)
diff --git a/drivers/gpu/drm/xe/xe_eudebug_pagefault.c b/drivers/gpu/drm/xe/xe_eudebug_pagefault.c
index 15389fcd042f..2c812b32c543 100644
--- a/drivers/gpu/drm/xe/xe_eudebug_pagefault.c
+++ b/drivers/gpu/drm/xe/xe_eudebug_pagefault.c
@@ -95,6 +95,11 @@ void *xe_eudebug_pagefault_get_private(void *private)
return private;
}
+bool xe_eudebug_pagefault_owned(struct xe_pagefault *pf)
+{
+ return !!((u64)pf->producer.private & XE_EUDEBUG_PAGEFAULT_PRIVATE_EUDEBUG);
+}
+
int
xe_eudebug_pagefault_create(struct xe_vm *vm, struct xe_pagefault *pf)
{
diff --git a/drivers/gpu/drm/xe/xe_eudebug_pagefault.h b/drivers/gpu/drm/xe/xe_eudebug_pagefault.h
index c7434e1c3bd3..b05e6d074346 100644
--- a/drivers/gpu/drm/xe/xe_eudebug_pagefault.h
+++ b/drivers/gpu/drm/xe/xe_eudebug_pagefault.h
@@ -32,7 +32,12 @@ void xe_eudebug_pagefault_service(struct xe_pagefault *pf, int err);
#define XE_EUDEBUG_PAGEFAULT_PRIVATE_EUDEBUG 0x1
void *xe_eudebug_pagefault_get_private(void *private);
+bool xe_eudebug_pagefault_owned(struct xe_pagefault *pf);
+
void xe_eudebug_pagefault_signal(struct xe_file *xef);
+
+#define xe_eudebug_pagefault_vm_lock(vm) down_write(&(vm)->lock)
+#define xe_eudebug_pagefault_vm_unlock(vm) up_write(&(vm)->lock)
#else
static inline int
@@ -41,6 +46,11 @@ xe_eudebug_pagefault_create(struct xe_vm *vm, struct xe_pagefault *pf)
return -EOPNOTSUPP;
}
+static inline bool xe_eudebug_pagefault_owned(struct xe_pagefault *pf)
+{
+ return false;
+}
+
static inline struct xe_vma *xe_eudebug_create_vma(struct xe_vm *vm, struct xe_pagefault *pf)
{
return NULL;
@@ -58,6 +68,10 @@ static inline void *xe_eudebug_pagefault_get_private(void *private)
static inline void xe_eudebug_pagefault_signal(struct xe_file *xef)
{
}
+
+#define xe_eudebug_pagefault_vm_lock(vm) down_read(&(vm)->lock)
+#define xe_eudebug_pagefault_vm_unlock(vm) up_read(&(vm)->lock)
+
#endif
#endif /* _XE_EUDEBUG_PAGEFAULT_H_ */
diff --git a/drivers/gpu/drm/xe/xe_guc_pagefault.c b/drivers/gpu/drm/xe/xe_guc_pagefault.c
index 038688ab63b4..9c00f3662e35 100644
--- a/drivers/gpu/drm/xe/xe_guc_pagefault.c
+++ b/drivers/gpu/drm/xe/xe_guc_pagefault.c
@@ -10,6 +10,7 @@
#include "xe_guc_pagefault.h"
#include "xe_pagefault.h"
#include "xe_pagefault_types.h"
+#include "xe_eudebug_pagefault.h"
static void guc_ack_fault(struct xe_pagefault *pf, int err)
{
@@ -41,8 +42,14 @@ static void guc_ack_fault(struct xe_pagefault *pf, int err)
xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action), 0, 0);
}
+static void guc_cleanup_fault(struct xe_pagefault *pf, int err)
+{
+ xe_eudebug_pagefault_service(pf, err);
+}
+
static const struct xe_pagefault_ops guc_pagefault_ops = {
.ack_fault = guc_ack_fault,
+ .cleanup_fault = guc_cleanup_fault,
};
/**
diff --git a/drivers/gpu/drm/xe/xe_pagefault.c b/drivers/gpu/drm/xe/xe_pagefault.c
index dd3c068e1a39..265fbff85c07 100644
--- a/drivers/gpu/drm/xe/xe_pagefault.c
+++ b/drivers/gpu/drm/xe/xe_pagefault.c
@@ -10,6 +10,7 @@
#include "xe_bo.h"
#include "xe_device.h"
+#include "xe_eudebug_pagefault.h"
#include "xe_gt_printk.h"
#include "xe_gt_types.h"
#include "xe_gt_stats.h"
@@ -184,10 +185,7 @@ static int xe_pagefault_service(struct xe_pagefault *pf)
if (IS_ERR(vm))
return PTR_ERR(vm);
- /*
- * TODO: Change to read lock? Using write lock for simplicity.
- */
- down_write(&vm->lock);
+ xe_eudebug_pagefault_vm_lock(vm);
if (xe_vm_is_closed(vm)) {
err = -ENOENT;
@@ -197,7 +195,15 @@ static int xe_pagefault_service(struct xe_pagefault *pf)
vma = xe_vm_find_vma_by_addr(vm, pf->consumer.page_addr);
if (!vma) {
err = -EINVAL;
- goto unlock_vm;
+ if (!xe_eudebug_pagefault_create(vm, pf)) {
+ vma = xe_eudebug_create_vma(vm, pf);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ vma = NULL;
+ }
+ }
+ if (!vma)
+ goto unlock_vm;
}
if (xe_vma_read_only(vma) &&
@@ -217,7 +223,7 @@ static int xe_pagefault_service(struct xe_pagefault *pf)
unlock_vm:
if (!err)
vm->usm.last_fault_vma = vma;
- up_write(&vm->lock);
+ xe_eudebug_pagefault_vm_unlock(vm);
xe_vm_put(vm);
return err;
@@ -240,6 +246,49 @@ static bool xe_pagefault_queue_pop(struct xe_pagefault_queue *pf_queue,
return found_fault;
}
+static bool pagefault_match(struct xe_pagefault *pf,
+ struct xe_pagefault *pf_to_match)
+{
+ if (pf_to_match->consumer.asid == pf->consumer.asid)
+ return true;
+ return false;
+}
+
+static bool xe_pagefault_queue_pop_if_match(struct xe_pagefault_queue *pf_queue,
+ struct xe_pagefault *pf,
+ struct xe_pagefault *pf_to_match)
+{
+ bool found_fault = false;
+ u32 ltail;
+
+ spin_lock_irq(&pf_queue->lock);
+ ltail = pf_queue->tail;
+ while (ltail != pf_queue->head && !found_fault) {
+ memcpy(pf, pf_queue->data + ltail, sizeof(*pf));
+
+ /* This will reorder the queue. */
+ if (pagefault_match(pf, pf_to_match)) {
+ if (ltail != pf_queue->tail) {
+ memcpy(pf_queue->data + ltail,
+ pf_queue->data + pf_queue->tail,
+ sizeof(*pf));
+ }
+ found_fault = true;
+ } else {
+ ltail = (ltail + xe_pagefault_entry_size()) %
+ pf_queue->size;
+ }
+ }
+
+ if (found_fault)
+ pf_queue->tail = (pf_queue->tail + xe_pagefault_entry_size()) %
+ pf_queue->size;
+
+ spin_unlock_irq(&pf_queue->lock);
+
+ return found_fault;
+}
+
static void xe_pagefault_print(struct xe_pagefault *pf)
{
xe_gt_info(pf->gt, "\n\tASID: %d\n"
@@ -292,7 +341,7 @@ static void xe_pagefault_queue_work(struct work_struct *w)
{
struct xe_pagefault_queue *pf_queue =
container_of(w, typeof(*pf_queue), worker);
- struct xe_pagefault pf;
+ struct xe_pagefault pf, pf_next;
unsigned long threshold;
#define USM_QUEUE_MAX_RUNTIME_MS 20
@@ -320,6 +369,20 @@ static void xe_pagefault_queue_work(struct work_struct *w)
pf.producer.ops->ack_fault(&pf, err);
+ /*
+ * EU Debugger: pagefault workaround needs to ACK all PFs
+ * for a given VM to have proper status. Otherwise
+ * the attention readout will be inacurate and any update
+ * will be visible in attention worker later on.
+ * For PF workaround EU Debugger runs in runalone mode.
+ */
+ if (!err && xe_eudebug_pagefault_owned(&pf)) {
+ while (xe_pagefault_queue_pop_if_match(pf_queue, &pf_next, &pf))
+ pf.producer.ops->ack_fault(&pf_next, err);
+ }
+ if (pf.producer.ops->cleanup_fault)
+ pf.producer.ops->cleanup_fault(&pf, err);
+
if (time_after(jiffies, threshold)) {
queue_work(gt_to_xe(pf.gt)->usm.pf_wq, w);
break;
diff --git a/drivers/gpu/drm/xe/xe_pagefault_types.h b/drivers/gpu/drm/xe/xe_pagefault_types.h
index ab38e135f23d..149e5989024e 100644
--- a/drivers/gpu/drm/xe/xe_pagefault_types.h
+++ b/drivers/gpu/drm/xe/xe_pagefault_types.h
@@ -43,6 +43,15 @@ struct xe_pagefault_ops {
* sends the result to the HW/FW interface.
*/
void (*ack_fault)(struct xe_pagefault *pf, int err);
+
+ /**
+ * @cleanup_fault: Cleanup for producer, if any
+ * @pf: Page fault
+ * @err: Error state of fault
+ *
+ * Page fault producer received cleanup request from consumer
+ */
+ void (*cleanup_fault)(struct xe_pagefault *pf, int err);
};
/**
--
2.43.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 24/24] drm/xe/eudebug: Disable SVM in Xe for Eudebug
2026-04-30 10:50 [PATCH 00/24] Intel Xe GPU Debug Support (eudebug) v8 Mika Kuoppala
` (22 preceding siblings ...)
2026-04-30 10:51 ` [PATCH 23/24] drm/xe/eudebug: Enable EU pagefault handling Mika Kuoppala
@ 2026-04-30 10:51 ` Mika Kuoppala
2026-04-30 19:22 ` Matthew Brost
2026-04-30 11:09 ` ✗ CI.checkpatch: warning for Intel Xe GPU Debug Support (eudebug) v8 Patchwork
` (3 subsequent siblings)
27 siblings, 1 reply; 32+ messages in thread
From: Mika Kuoppala @ 2026-04-30 10:51 UTC (permalink / raw)
To: intel-xe
Cc: simona.vetter, matthew.brost, christian.koenig, thomas.hellstrom,
joonas.lahtinen, gustavo.sousa, jan.maslak,
dominik.karol.piatkowski, rodrigo.vivi, andrzej.hajda,
matthew.auld, maciej.patelczyk, gwan-gyeong.mun, Mika Kuoppala
From: Maciej Patelczyk <maciej.patelczyk@intel.com>
Missing SVM pagefault intergration. Temporary exclude SVM in Xe until
there is SVM support in EU Debugger.
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Maciej Patelczyk <maciej.patelczyk@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/xe/Kconfig | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xe/Kconfig b/drivers/gpu/drm/xe/Kconfig
index 78d4673665b4..542198a60ed9 100644
--- a/drivers/gpu/drm/xe/Kconfig
+++ b/drivers/gpu/drm/xe/Kconfig
@@ -81,7 +81,7 @@ config DRM_XE_GPUSVM
depends on DRM_XE
depends on !UML
depends on ZONE_DEVICE
- default y
+ default n
select DEVICE_PRIVATE
select DRM_GPUSVM
help
@@ -132,6 +132,7 @@ config DRM_XE_FORCE_PROBE
config DRM_XE_EUDEBUG
bool "Enable gdb debugger support (eudebug)"
depends on DRM_XE
+ depends on !DRM_XE_GPUSVM
default y
help
Choose this option if you want to add support for debugger (gdb) to
@@ -139,6 +140,9 @@ config DRM_XE_EUDEBUG
With debugger support, Xe will provide interface for a debugger to
process to track, inspect and modify resources.
+comment "Gdb debugger support (eudebug) disabled for CPU to GPU address mirroring"
+ depends on DRM_XE_GPUSVM
+
menu "drm/Xe Debugging"
depends on DRM_XE
depends on EXPERT
--
2.43.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* Re: [PATCH 24/24] drm/xe/eudebug: Disable SVM in Xe for Eudebug
2026-04-30 10:51 ` [PATCH 24/24] drm/xe/eudebug: Disable SVM in Xe for Eudebug Mika Kuoppala
@ 2026-04-30 19:22 ` Matthew Brost
0 siblings, 0 replies; 32+ messages in thread
From: Matthew Brost @ 2026-04-30 19:22 UTC (permalink / raw)
To: Mika Kuoppala
Cc: intel-xe, simona.vetter, christian.koenig, thomas.hellstrom,
joonas.lahtinen, gustavo.sousa, jan.maslak,
dominik.karol.piatkowski, rodrigo.vivi, andrzej.hajda,
matthew.auld, maciej.patelczyk, gwan-gyeong.mun
On Thu, Apr 30, 2026 at 01:51:20PM +0300, Mika Kuoppala wrote:
> From: Maciej Patelczyk <maciej.patelczyk@intel.com>
>
> Missing SVM pagefault intergration. Temporary exclude SVM in Xe until
> there is SVM support in EU Debugger.
>
> Cc: Matthew Brost <matthew.brost@intel.com>
> Cc: Gustavo Sousa <gustavo.sousa@intel.com>
> Signed-off-by: Maciej Patelczyk <maciej.patelczyk@intel.com>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/xe/Kconfig | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/xe/Kconfig b/drivers/gpu/drm/xe/Kconfig
> index 78d4673665b4..542198a60ed9 100644
> --- a/drivers/gpu/drm/xe/Kconfig
> +++ b/drivers/gpu/drm/xe/Kconfig
> @@ -81,7 +81,7 @@ config DRM_XE_GPUSVM
> depends on DRM_XE
> depends on !UML
> depends on ZONE_DEVICE
> - default y
> + default n
If EU debugger and SVM are mutual exclusive, you will need to do the
inverse of this - default DRM_XE_EUDEBUG to false. I don't think a new
feature can turn off an existing one.
Perhaps this will be non-issue by the time of merging though as the SVM
interaction will be fixed.
Matt
> select DEVICE_PRIVATE
> select DRM_GPUSVM
> help
> @@ -132,6 +132,7 @@ config DRM_XE_FORCE_PROBE
> config DRM_XE_EUDEBUG
> bool "Enable gdb debugger support (eudebug)"
> depends on DRM_XE
> + depends on !DRM_XE_GPUSVM
> default y
> help
> Choose this option if you want to add support for debugger (gdb) to
> @@ -139,6 +140,9 @@ config DRM_XE_EUDEBUG
> With debugger support, Xe will provide interface for a debugger to
> process to track, inspect and modify resources.
>
> +comment "Gdb debugger support (eudebug) disabled for CPU to GPU address mirroring"
> + depends on DRM_XE_GPUSVM
> +
> menu "drm/Xe Debugging"
> depends on DRM_XE
> depends on EXPERT
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* ✗ CI.checkpatch: warning for Intel Xe GPU Debug Support (eudebug) v8
2026-04-30 10:50 [PATCH 00/24] Intel Xe GPU Debug Support (eudebug) v8 Mika Kuoppala
` (23 preceding siblings ...)
2026-04-30 10:51 ` [PATCH 24/24] drm/xe/eudebug: Disable SVM in Xe for Eudebug Mika Kuoppala
@ 2026-04-30 11:09 ` Patchwork
2026-04-30 11:10 ` ✓ CI.KUnit: success " Patchwork
` (2 subsequent siblings)
27 siblings, 0 replies; 32+ messages in thread
From: Patchwork @ 2026-04-30 11:09 UTC (permalink / raw)
To: Mika Kuoppala; +Cc: intel-xe
== Series Details ==
Series: Intel Xe GPU Debug Support (eudebug) v8
URL : https://patchwork.freedesktop.org/series/165777/
State : warning
== Summary ==
+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
c8c12e558adaef7a4d125d83b6e1f8824bc13b82
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 9e920ee42bc0dcf88381b7e41fb18d758a03835a
Author: Maciej Patelczyk <maciej.patelczyk@intel.com>
Date: Thu Apr 30 13:51:20 2026 +0300
drm/xe/eudebug: Disable SVM in Xe for Eudebug
Missing SVM pagefault intergration. Temporary exclude SVM in Xe until
there is SVM support in EU Debugger.
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Maciej Patelczyk <maciej.patelczyk@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
+ /mt/dim checkpatch 3ac514cf64f272cc4d5143f4cc28fb18a8aba76d drm-intel
ecfd14ef7c80 drm/xe/eudebug: Introduce eudebug interface
-:235: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#235:
new file mode 100644
-:293: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "!READ_ONCE"
#293: FILE: drivers/gpu/drm/xe/xe_eudebug.c:54:
+ return READ_ONCE(d->target.xef) == NULL;
-:475: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_d' - possible side-effects?
#475: FILE: drivers/gpu/drm/xe/xe_eudebug.c:236:
+#define xe_eudebug_disconnect(_d, _err) ({ \
+ if (_xe_eudebug_disconnect((_d), (_err))) { \
+ if ((_err) == 0 || (_err) == -ETIMEDOUT) \
+ eu_dbg((_d), "Session closed (%d)", (_err)); \
+ else \
+ eu_err((_d), "Session disconnected, err = %d (%s:%d)", \
+ (_err), __func__, __LINE__); \
+ } \
+})
-:475: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_err' - possible side-effects?
#475: FILE: drivers/gpu/drm/xe/xe_eudebug.c:236:
+#define xe_eudebug_disconnect(_d, _err) ({ \
+ if (_xe_eudebug_disconnect((_d), (_err))) { \
+ if ((_err) == 0 || (_err) == -ETIMEDOUT) \
+ eu_dbg((_d), "Session closed (%d)", (_err)); \
+ else \
+ eu_err((_d), "Session disconnected, err = %d (%s:%d)", \
+ (_err), __func__, __LINE__); \
+ } \
+})
-:825: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_d' - possible side-effects?
#825: FILE: drivers/gpu/drm/xe/xe_eudebug.c:586:
+#define xe_eudebug_event_put(_d, _err) ({ \
+ if ((_err)) \
+ xe_eudebug_disconnect((_d), (_err)); \
+ xe_eudebug_put((_d)); \
+ })
-:825: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_err' - possible side-effects?
#825: FILE: drivers/gpu/drm/xe/xe_eudebug.c:586:
+#define xe_eudebug_event_put(_d, _err) ({ \
+ if ((_err)) \
+ xe_eudebug_disconnect((_d), (_err)); \
+ xe_eudebug_put((_d)); \
+ })
-:1305: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1305: FILE: drivers/gpu/drm/xe/xe_eudebug.h:20:
+#define XE_EUDEBUG_DBG_ARGS(d) (d)->session, \
+ atomic_long_read(&(d)->events.seqno), \
+ !READ_ONCE(d->target.xef) ? "disconnected" : "", \
+ current->pid, \
+ task_tgid_nr(current), \
+ READ_ONCE(d->target.xef) ? d->target.xef->pid : -1
BUT SEE:
do {} while (0) advice is over-stated in a few situations:
The more obvious case is macros, like MODULE_PARM_DESC, invoked at
file-scope, where C disallows code (it must be in functions). See
$exceptions if you have one to add by name.
More troublesome is declarative macros used at top of new scope,
like DECLARE_PER_CPU. These might just compile with a do-while-0
wrapper, but would be incorrect. Most of these are handled by
detecting struct,union,etc declaration primitives in $exceptions.
Theres also macros called inside an if (block), which "return" an
expression. These cannot do-while, and need a ({}) wrapper.
Enjoy this qualification while we work to improve our heuristics.
-:1305: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'd' - possible side-effects?
#1305: FILE: drivers/gpu/drm/xe/xe_eudebug.h:20:
+#define XE_EUDEBUG_DBG_ARGS(d) (d)->session, \
+ atomic_long_read(&(d)->events.seqno), \
+ !READ_ONCE(d->target.xef) ? "disconnected" : "", \
+ current->pid, \
+ task_tgid_nr(current), \
+ READ_ONCE(d->target.xef) ? d->target.xef->pid : -1
-:1312: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'd' - possible side-effects?
#1312: FILE: drivers/gpu/drm/xe/xe_eudebug.h:27:
+#define eu_err(d, fmt, ...) drm_err(&(d)->xe->drm, XE_EUDEBUG_DBG_STR # fmt, \
+ XE_EUDEBUG_DBG_ARGS(d), ##__VA_ARGS__)
-:1314: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'd' - possible side-effects?
#1314: FILE: drivers/gpu/drm/xe/xe_eudebug.h:29:
+#define eu_warn(d, fmt, ...) drm_warn(&(d)->xe->drm, XE_EUDEBUG_DBG_STR # fmt, \
+ XE_EUDEBUG_DBG_ARGS(d), ##__VA_ARGS__)
-:1316: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'd' - possible side-effects?
#1316: FILE: drivers/gpu/drm/xe/xe_eudebug.h:31:
+#define eu_dbg(d, fmt, ...) drm_dbg(&(d)->xe->drm, XE_EUDEBUG_DBG_STR # fmt, \
+ XE_EUDEBUG_DBG_ARGS(d), ##__VA_ARGS__)
-:1527: WARNING:LONG_LINE: line length of 130 exceeds 100 columns
#1527: FILE: include/uapi/drm/xe_drm.h:133:
+#define DRM_IOCTL_XE_EUDEBUG_CONNECT DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EUDEBUG_CONNECT, struct drm_xe_eudebug_connect)
total: 1 errors, 2 warnings, 9 checks, 1504 lines checked
20d2e2ea5f54 drm/xe/eudebug: Add documentation
-:21: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#21:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 108 lines checked
230ca6426623 drm/xe/eudebug: Add connection establishment documentation
cab635633925 drm/xe/eudebug: Introduce discovery for resources
ea14318160fc drm/xe/eudebug: Introduce exec_queue events
1cf709641970 drm/xe: Add EUDEBUG_ENABLE exec queue property
0aa3d7adea74 drm/xe/eudebug: Mark guc contexts as debuggable
c24e8c5b4140 drm/xe: Introduce ADD_DEBUG_DATA and REMOVE_DEBUG_DATA vm bind ops
-:44: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#44:
new file mode 100644
-:617: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#617: FILE: drivers/gpu/drm/xe/xe_vm.c:3660:
+ if (XE_IOCTL_DBG(xe, operation != DRM_XE_VM_BIND_OP_ADD_DEBUG_DATA &&
+ operation != DRM_XE_VM_BIND_OP_REMOVE_DEBUG_DATA &&
-:620: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#620: FILE: drivers/gpu/drm/xe/xe_vm.c:3663:
+ XE_IOCTL_DBG(xe, ext.name == XE_VM_BIND_OP_EXTENSIONS_DEBUG_DATA &&
+ ++debug_data_count > 1))
-:744: CHECK:UNCOMMENTED_DEFINITION: struct mutex definition without comment
#744: FILE: drivers/gpu/drm/xe/xe_vm_types.h:414:
+ struct mutex lock;
total: 0 errors, 1 warnings, 3 checks, 790 lines checked
bf304b06145b drm/xe/eudebug: Introduce vm bind and vm bind debug data events
-:7: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line (possible unwrapped commit description?)
#7:
This patch adds events to track the bind ioctl and associated debug data add
-:414: WARNING:LONG_LINE_COMMENT: line length of 102 exceeds 100 columns
#414: FILE: include/uapi/drm/xe_drm_eudebug.h:112:
+ * │ EVENT_VM_BIND ├──────────────────┬─┬┄┐
-:415: WARNING:LONG_LINE_COMMENT: line length of 108 exceeds 100 columns
#415: FILE: include/uapi/drm/xe_drm_eudebug.h:113:
+ * └───────────────────────┘ │ │ ┊
-:416: WARNING:LONG_LINE_COMMENT: line length of 130 exceeds 100 columns
#416: FILE: include/uapi/drm/xe_drm_eudebug.h:114:
+ * ┌──────────────────────────────────┐ │ │ ┊
-:418: WARNING:LONG_LINE_COMMENT: line length of 128 exceeds 100 columns
#418: FILE: include/uapi/drm/xe_drm_eudebug.h:116:
+ * └──────────────────────────────────┘ │ ┊
-:420: WARNING:LONG_LINE_COMMENT: line length of 128 exceeds 100 columns
#420: FILE: include/uapi/drm/xe_drm_eudebug.h:118:
+ * ┌──────────────────────────────────┐ │ ┊
-:422: WARNING:LONG_LINE_COMMENT: line length of 126 exceeds 100 columns
#422: FILE: include/uapi/drm/xe_drm_eudebug.h:120:
+ * └──────────────────────────────────┘ ┊
-:424: WARNING:LONG_LINE_COMMENT: line length of 126 exceeds 100 columns
#424: FILE: include/uapi/drm/xe_drm_eudebug.h:122:
+ * ┌┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┐ ┊
-:426: WARNING:LONG_LINE_COMMENT: line length of 116 exceeds 100 columns
#426: FILE: include/uapi/drm/xe_drm_eudebug.h:124:
+ * └┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┄┘
total: 0 errors, 9 warnings, 0 checks, 427 lines checked
ec17ff396a7b drm/xe/eudebug: Add ufence events with acks
-:28: WARNING:REPEATED_WORD: Possible repeated word: 'for'
#28:
- take reference for for tracking check (Mika)
-:337: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "!ufence"
#337: FILE: drivers/gpu/drm/xe/xe_eudebug.c:1291:
+ xe_assert(vm->xe, ufence == NULL);
-:638: CHECK:UNCOMMENTED_DEFINITION: spinlock_t definition without comment
#638: FILE: drivers/gpu/drm/xe/xe_sync_types.h:26:
+ spinlock_t lock;
total: 0 errors, 1 warnings, 2 checks, 654 lines checked
29637a08d924 drm/xe/eudebug: vm open/pread/pwrite
-:139: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#139: FILE: drivers/gpu/drm/xe/xe_eudebug.c:750:
+{
+
-:162: CHECK:LINE_SPACING: Please don't use multiple blank lines
#162: FILE: drivers/gpu/drm/xe/xe_eudebug.c:773:
+
+
-:202: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#202: FILE: drivers/gpu/drm/xe/xe_eudebug.h:42:
+#define xe_eudebug_for_each_hw_engine(__hwe, __gt, __id) \
+ for_each_hw_engine(__hwe, __gt, __id) \
+ if (xe_hw_engine_has_eudebug(__hwe))
BUT SEE:
do {} while (0) advice is over-stated in a few situations:
The more obvious case is macros, like MODULE_PARM_DESC, invoked at
file-scope, where C disallows code (it must be in functions). See
$exceptions if you have one to add by name.
More troublesome is declarative macros used at top of new scope,
like DECLARE_PER_CPU. These might just compile with a do-while-0
wrapper, but would be incorrect. Most of these are handled by
detecting struct,union,etc declaration primitives in $exceptions.
Theres also macros called inside an if (block), which "return" an
expression. These cannot do-while, and need a ({}) wrapper.
Enjoy this qualification while we work to improve our heuristics.
-:202: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__hwe' - possible side-effects?
#202: FILE: drivers/gpu/drm/xe/xe_eudebug.h:42:
+#define xe_eudebug_for_each_hw_engine(__hwe, __gt, __id) \
+ for_each_hw_engine(__hwe, __gt, __id) \
+ if (xe_hw_engine_has_eudebug(__hwe))
-:252: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#252:
new file mode 100644
total: 1 errors, 1 warnings, 3 checks, 644 lines checked
2dc1635f8b5b drm/xe/eudebug: userptr vm pread/pwrite
f20439c2fa6b drm/xe/eudebug: hw enablement for eudebug
-:144: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#144:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 481 lines checked
dba3233dca8a drm/xe/eudebug: Introduce EU control interface
-:295: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#295: FILE: drivers/gpu/drm/xe/xe_eudebug_hw.c:183:
+static bool engine_has_runalone_set(const struct xe_hw_engine * const hwe,
+ u32 rcu_debug1)
-:301: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#301: FILE: drivers/gpu/drm/xe/xe_eudebug_hw.c:189:
+static bool engine_has_context_set(const struct xe_hw_engine * const hwe,
+ u32 rcu_debug1)
total: 0 errors, 0 warnings, 2 checks, 891 lines checked
d29bbbc620bc drm/xe/eudebug: Introduce per device attention scan worker
5bd603e4f848 drm/xe/eudebug_test: Introduce xe_eudebug wa kunit test
-:16: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#16:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 201 lines checked
f7030e98051e drm/xe: Implement SR-IOV and eudebug exclusivity
0eef827a8570 drm/xe: Add xe_client_debugfs and introduce debug_data file
-:31: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
-:85: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#85: FILE: drivers/gpu/drm/xe/xe_client_debugfs.c:50:
+ len = snprintf(kbuf, MAX_LINE_LEN, "%lu 0x%llx-0x%llx 0x%llx 0x%x\t%s\n",
+ vm_index,
total: 0 errors, 1 warnings, 1 checks, 161 lines checked
aa4b22466196 drm/xe/eudebug: Allow getting eudebug instance during discovery
c365fcd48a10 drm/xe/eudebug: Add read/count/compare helper for eu attention
-:131: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#131:
new file mode 100644
-:153: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#153: FILE: drivers/gpu/drm/xe/xe_gt_debug_types.h:18:
+ XE_GT_EU_ATT_MAX_THREADS/8];
^
total: 0 errors, 1 warnings, 1 checks, 121 lines checked
855e12416e46 drm/xe/vm: Support for adding null page VMA to VM on request
-:15: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line (possible unwrapped commit description?)
#15:
[1] https://lore.kernel.org/intel-xe/20230829231648.4438-1-yu.bruce.chang@intel.com/
total: 0 errors, 1 warnings, 0 checks, 43 lines checked
394b3b021487 drm/xe/eudebug: Introduce EU pagefault handling interface
-:359: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#359:
new file mode 100644
-:421: CHECK:UNCOMMENTED_DEFINITION: spinlock_t definition without comment
#421: FILE: drivers/gpu/drm/xe/xe_eudebug_pagefault.c:58:
+ spinlock_t lock;
-:429: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "!fence"
#429: FILE: drivers/gpu/drm/xe/xe_eudebug_pagefault.c:66:
+ if (fence == NULL)
-:535: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see function description of usleep_range() and udelay().
#535: FILE: drivers/gpu/drm/xe/xe_eudebug_pagefault.c:172:
+ udelay(200);
total: 0 errors, 1 warnings, 3 checks, 858 lines checked
d789723aad4e drm/xe/eudebug: Enable EU pagefault handling
9e920ee42bc0 drm/xe/eudebug: Disable SVM in Xe for Eudebug
^ permalink raw reply [flat|nested] 32+ messages in thread* ✓ CI.KUnit: success for Intel Xe GPU Debug Support (eudebug) v8
2026-04-30 10:50 [PATCH 00/24] Intel Xe GPU Debug Support (eudebug) v8 Mika Kuoppala
` (24 preceding siblings ...)
2026-04-30 11:09 ` ✗ CI.checkpatch: warning for Intel Xe GPU Debug Support (eudebug) v8 Patchwork
@ 2026-04-30 11:10 ` Patchwork
2026-04-30 12:06 ` ✓ Xe.CI.BAT: " Patchwork
2026-04-30 22:41 ` ✗ Xe.CI.FULL: failure " Patchwork
27 siblings, 0 replies; 32+ messages in thread
From: Patchwork @ 2026-04-30 11:10 UTC (permalink / raw)
To: Mika Kuoppala; +Cc: intel-xe
== Series Details ==
Series: Intel Xe GPU Debug Support (eudebug) v8
URL : https://patchwork.freedesktop.org/series/165777/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[11:09:36] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[11:09:41] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[11:10:12] Starting KUnit Kernel (1/1)...
[11:10:12] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[11:10:12] ================== guc_buf (11 subtests) ===================
[11:10:12] [PASSED] test_smallest
[11:10:12] [PASSED] test_largest
[11:10:12] [PASSED] test_granular
[11:10:12] [PASSED] test_unique
[11:10:12] [PASSED] test_overlap
[11:10:12] [PASSED] test_reusable
[11:10:12] [PASSED] test_too_big
[11:10:12] [PASSED] test_flush
[11:10:12] [PASSED] test_lookup
[11:10:12] [PASSED] test_data
[11:10:12] [PASSED] test_class
[11:10:12] ===================== [PASSED] guc_buf =====================
[11:10:12] =================== guc_dbm (7 subtests) ===================
[11:10:12] [PASSED] test_empty
[11:10:12] [PASSED] test_default
[11:10:12] ======================== test_size ========================
[11:10:12] [PASSED] 4
[11:10:12] [PASSED] 8
[11:10:12] [PASSED] 32
[11:10:12] [PASSED] 256
[11:10:12] ==================== [PASSED] test_size ====================
[11:10:12] ======================= test_reuse ========================
[11:10:12] [PASSED] 4
[11:10:12] [PASSED] 8
[11:10:12] [PASSED] 32
[11:10:12] [PASSED] 256
[11:10:12] =================== [PASSED] test_reuse ====================
[11:10:12] =================== test_range_overlap ====================
[11:10:12] [PASSED] 4
[11:10:12] [PASSED] 8
[11:10:12] [PASSED] 32
[11:10:12] [PASSED] 256
[11:10:12] =============== [PASSED] test_range_overlap ================
[11:10:12] =================== test_range_compact ====================
[11:10:12] [PASSED] 4
[11:10:12] [PASSED] 8
[11:10:12] [PASSED] 32
[11:10:12] [PASSED] 256
[11:10:12] =============== [PASSED] test_range_compact ================
[11:10:12] ==================== test_range_spare =====================
[11:10:12] [PASSED] 4
[11:10:12] [PASSED] 8
[11:10:12] [PASSED] 32
[11:10:12] [PASSED] 256
[11:10:12] ================ [PASSED] test_range_spare =================
[11:10:12] ===================== [PASSED] guc_dbm =====================
[11:10:12] =================== guc_idm (6 subtests) ===================
[11:10:12] [PASSED] bad_init
[11:10:12] [PASSED] no_init
[11:10:12] [PASSED] init_fini
[11:10:12] [PASSED] check_used
[11:10:12] [PASSED] check_quota
[11:10:12] [PASSED] check_all
[11:10:12] ===================== [PASSED] guc_idm =====================
[11:10:12] ================== no_relay (3 subtests) ===================
[11:10:12] [PASSED] xe_drops_guc2pf_if_not_ready
[11:10:12] [PASSED] xe_drops_guc2vf_if_not_ready
[11:10:12] [PASSED] xe_rejects_send_if_not_ready
[11:10:12] ==================== [PASSED] no_relay =====================
[11:10:12] ================== pf_relay (14 subtests) ==================
[11:10:12] [PASSED] pf_rejects_guc2pf_too_short
[11:10:12] [PASSED] pf_rejects_guc2pf_too_long
[11:10:12] [PASSED] pf_rejects_guc2pf_no_payload
[11:10:12] [PASSED] pf_fails_no_payload
[11:10:12] [PASSED] pf_fails_bad_origin
[11:10:12] [PASSED] pf_fails_bad_type
[11:10:12] [PASSED] pf_txn_reports_error
[11:10:12] [PASSED] pf_txn_sends_pf2guc
[11:10:12] [PASSED] pf_sends_pf2guc
[11:10:12] [SKIPPED] pf_loopback_nop
[11:10:12] [SKIPPED] pf_loopback_echo
[11:10:12] [SKIPPED] pf_loopback_fail
[11:10:12] [SKIPPED] pf_loopback_busy
[11:10:12] [SKIPPED] pf_loopback_retry
[11:10:12] ==================== [PASSED] pf_relay =====================
[11:10:12] ================== vf_relay (3 subtests) ===================
[11:10:12] [PASSED] vf_rejects_guc2vf_too_short
[11:10:12] [PASSED] vf_rejects_guc2vf_too_long
[11:10:12] [PASSED] vf_rejects_guc2vf_no_payload
[11:10:12] ==================== [PASSED] vf_relay =====================
[11:10:12] ================ pf_gt_config (9 subtests) =================
[11:10:13] [PASSED] fair_contexts_1vf
[11:10:13] [PASSED] fair_doorbells_1vf
[11:10:13] [PASSED] fair_ggtt_1vf
[11:10:13] ====================== fair_vram_1vf ======================
[11:10:13] [PASSED] 3.50 GiB
[11:10:13] [PASSED] 11.5 GiB
[11:10:13] [PASSED] 15.5 GiB
[11:10:13] [PASSED] 31.5 GiB
[11:10:13] [PASSED] 63.5 GiB
[11:10:13] [PASSED] 1.91 GiB
[11:10:13] ================== [PASSED] fair_vram_1vf ==================
[11:10:13] ================ fair_vram_1vf_admin_only =================
[11:10:13] [PASSED] 3.50 GiB
[11:10:13] [PASSED] 11.5 GiB
[11:10:13] [PASSED] 15.5 GiB
[11:10:13] [PASSED] 31.5 GiB
[11:10:13] [PASSED] 63.5 GiB
[11:10:13] [PASSED] 1.91 GiB
[11:10:13] ============ [PASSED] fair_vram_1vf_admin_only =============
[11:10:13] ====================== fair_contexts ======================
[11:10:13] [PASSED] 1 VF
[11:10:13] [PASSED] 2 VFs
[11:10:13] [PASSED] 3 VFs
[11:10:13] [PASSED] 4 VFs
[11:10:13] [PASSED] 5 VFs
[11:10:13] [PASSED] 6 VFs
[11:10:13] [PASSED] 7 VFs
[11:10:13] [PASSED] 8 VFs
[11:10:13] [PASSED] 9 VFs
[11:10:13] [PASSED] 10 VFs
[11:10:13] [PASSED] 11 VFs
[11:10:13] [PASSED] 12 VFs
[11:10:13] [PASSED] 13 VFs
[11:10:13] [PASSED] 14 VFs
[11:10:13] [PASSED] 15 VFs
[11:10:13] [PASSED] 16 VFs
[11:10:13] [PASSED] 17 VFs
[11:10:13] [PASSED] 18 VFs
[11:10:13] [PASSED] 19 VFs
[11:10:13] [PASSED] 20 VFs
[11:10:13] [PASSED] 21 VFs
[11:10:13] [PASSED] 22 VFs
[11:10:13] [PASSED] 23 VFs
[11:10:13] [PASSED] 24 VFs
[11:10:13] [PASSED] 25 VFs
[11:10:13] [PASSED] 26 VFs
[11:10:13] [PASSED] 27 VFs
[11:10:13] [PASSED] 28 VFs
[11:10:13] [PASSED] 29 VFs
[11:10:13] [PASSED] 30 VFs
[11:10:13] [PASSED] 31 VFs
[11:10:13] [PASSED] 32 VFs
[11:10:13] [PASSED] 33 VFs
[11:10:13] [PASSED] 34 VFs
[11:10:13] [PASSED] 35 VFs
[11:10:13] [PASSED] 36 VFs
[11:10:13] [PASSED] 37 VFs
[11:10:13] [PASSED] 38 VFs
[11:10:13] [PASSED] 39 VFs
[11:10:13] [PASSED] 40 VFs
[11:10:13] [PASSED] 41 VFs
[11:10:13] [PASSED] 42 VFs
[11:10:13] [PASSED] 43 VFs
[11:10:13] [PASSED] 44 VFs
[11:10:13] [PASSED] 45 VFs
[11:10:13] [PASSED] 46 VFs
[11:10:13] [PASSED] 47 VFs
[11:10:13] [PASSED] 48 VFs
[11:10:13] [PASSED] 49 VFs
[11:10:13] [PASSED] 50 VFs
[11:10:13] [PASSED] 51 VFs
[11:10:13] [PASSED] 52 VFs
[11:10:13] [PASSED] 53 VFs
[11:10:13] [PASSED] 54 VFs
[11:10:13] [PASSED] 55 VFs
[11:10:13] [PASSED] 56 VFs
[11:10:13] [PASSED] 57 VFs
[11:10:13] [PASSED] 58 VFs
[11:10:13] [PASSED] 59 VFs
[11:10:13] [PASSED] 60 VFs
[11:10:13] [PASSED] 61 VFs
[11:10:13] [PASSED] 62 VFs
[11:10:13] [PASSED] 63 VFs
[11:10:13] ================== [PASSED] fair_contexts ==================
[11:10:13] ===================== fair_doorbells ======================
[11:10:13] [PASSED] 1 VF
[11:10:13] [PASSED] 2 VFs
[11:10:13] [PASSED] 3 VFs
[11:10:13] [PASSED] 4 VFs
[11:10:13] [PASSED] 5 VFs
[11:10:13] [PASSED] 6 VFs
[11:10:13] [PASSED] 7 VFs
[11:10:13] [PASSED] 8 VFs
[11:10:13] [PASSED] 9 VFs
[11:10:13] [PASSED] 10 VFs
[11:10:13] [PASSED] 11 VFs
[11:10:13] [PASSED] 12 VFs
[11:10:13] [PASSED] 13 VFs
[11:10:13] [PASSED] 14 VFs
[11:10:13] [PASSED] 15 VFs
[11:10:13] [PASSED] 16 VFs
[11:10:13] [PASSED] 17 VFs
[11:10:13] [PASSED] 18 VFs
[11:10:13] [PASSED] 19 VFs
[11:10:13] [PASSED] 20 VFs
[11:10:13] [PASSED] 21 VFs
[11:10:13] [PASSED] 22 VFs
[11:10:13] [PASSED] 23 VFs
[11:10:13] [PASSED] 24 VFs
[11:10:13] [PASSED] 25 VFs
[11:10:13] [PASSED] 26 VFs
[11:10:13] [PASSED] 27 VFs
[11:10:13] [PASSED] 28 VFs
[11:10:13] [PASSED] 29 VFs
[11:10:13] [PASSED] 30 VFs
[11:10:13] [PASSED] 31 VFs
[11:10:13] [PASSED] 32 VFs
[11:10:13] [PASSED] 33 VFs
[11:10:13] [PASSED] 34 VFs
[11:10:13] [PASSED] 35 VFs
[11:10:13] [PASSED] 36 VFs
[11:10:13] [PASSED] 37 VFs
[11:10:13] [PASSED] 38 VFs
[11:10:13] [PASSED] 39 VFs
[11:10:13] [PASSED] 40 VFs
[11:10:13] [PASSED] 41 VFs
[11:10:13] [PASSED] 42 VFs
[11:10:13] [PASSED] 43 VFs
[11:10:13] [PASSED] 44 VFs
[11:10:13] [PASSED] 45 VFs
[11:10:13] [PASSED] 46 VFs
[11:10:13] [PASSED] 47 VFs
[11:10:13] [PASSED] 48 VFs
[11:10:13] [PASSED] 49 VFs
[11:10:13] [PASSED] 50 VFs
[11:10:13] [PASSED] 51 VFs
[11:10:13] [PASSED] 52 VFs
[11:10:13] [PASSED] 53 VFs
[11:10:13] [PASSED] 54 VFs
[11:10:13] [PASSED] 55 VFs
[11:10:13] [PASSED] 56 VFs
[11:10:13] [PASSED] 57 VFs
[11:10:13] [PASSED] 58 VFs
[11:10:13] [PASSED] 59 VFs
[11:10:13] [PASSED] 60 VFs
[11:10:13] [PASSED] 61 VFs
[11:10:13] [PASSED] 62 VFs
[11:10:13] [PASSED] 63 VFs
[11:10:13] ================= [PASSED] fair_doorbells ==================
[11:10:13] ======================== fair_ggtt ========================
[11:10:13] [PASSED] 1 VF
[11:10:13] [PASSED] 2 VFs
[11:10:13] [PASSED] 3 VFs
[11:10:13] [PASSED] 4 VFs
[11:10:13] [PASSED] 5 VFs
[11:10:13] [PASSED] 6 VFs
[11:10:13] [PASSED] 7 VFs
[11:10:13] [PASSED] 8 VFs
[11:10:13] [PASSED] 9 VFs
[11:10:13] [PASSED] 10 VFs
[11:10:13] [PASSED] 11 VFs
[11:10:13] [PASSED] 12 VFs
[11:10:13] [PASSED] 13 VFs
[11:10:13] [PASSED] 14 VFs
[11:10:13] [PASSED] 15 VFs
[11:10:13] [PASSED] 16 VFs
[11:10:13] [PASSED] 17 VFs
[11:10:13] [PASSED] 18 VFs
[11:10:13] [PASSED] 19 VFs
[11:10:13] [PASSED] 20 VFs
[11:10:13] [PASSED] 21 VFs
[11:10:13] [PASSED] 22 VFs
[11:10:13] [PASSED] 23 VFs
[11:10:13] [PASSED] 24 VFs
[11:10:13] [PASSED] 25 VFs
[11:10:13] [PASSED] 26 VFs
[11:10:13] [PASSED] 27 VFs
[11:10:13] [PASSED] 28 VFs
[11:10:13] [PASSED] 29 VFs
[11:10:13] [PASSED] 30 VFs
[11:10:13] [PASSED] 31 VFs
[11:10:13] [PASSED] 32 VFs
[11:10:13] [PASSED] 33 VFs
[11:10:13] [PASSED] 34 VFs
[11:10:13] [PASSED] 35 VFs
[11:10:13] [PASSED] 36 VFs
[11:10:13] [PASSED] 37 VFs
[11:10:13] [PASSED] 38 VFs
[11:10:13] [PASSED] 39 VFs
[11:10:13] [PASSED] 40 VFs
[11:10:13] [PASSED] 41 VFs
[11:10:13] [PASSED] 42 VFs
[11:10:13] [PASSED] 43 VFs
[11:10:13] [PASSED] 44 VFs
[11:10:13] [PASSED] 45 VFs
[11:10:13] [PASSED] 46 VFs
[11:10:13] [PASSED] 47 VFs
[11:10:13] [PASSED] 48 VFs
[11:10:13] [PASSED] 49 VFs
[11:10:13] [PASSED] 50 VFs
[11:10:13] [PASSED] 51 VFs
[11:10:13] [PASSED] 52 VFs
[11:10:13] [PASSED] 53 VFs
[11:10:13] [PASSED] 54 VFs
[11:10:13] [PASSED] 55 VFs
[11:10:13] [PASSED] 56 VFs
[11:10:13] [PASSED] 57 VFs
[11:10:13] [PASSED] 58 VFs
[11:10:13] [PASSED] 59 VFs
[11:10:13] [PASSED] 60 VFs
[11:10:13] [PASSED] 61 VFs
[11:10:13] [PASSED] 62 VFs
[11:10:13] [PASSED] 63 VFs
[11:10:13] ==================== [PASSED] fair_ggtt ====================
[11:10:13] ======================== fair_vram ========================
[11:10:13] [PASSED] 1 VF
[11:10:13] [PASSED] 2 VFs
[11:10:13] [PASSED] 3 VFs
[11:10:13] [PASSED] 4 VFs
[11:10:13] [PASSED] 5 VFs
[11:10:13] [PASSED] 6 VFs
[11:10:13] [PASSED] 7 VFs
[11:10:13] [PASSED] 8 VFs
[11:10:13] [PASSED] 9 VFs
[11:10:13] [PASSED] 10 VFs
[11:10:13] [PASSED] 11 VFs
[11:10:13] [PASSED] 12 VFs
[11:10:13] [PASSED] 13 VFs
[11:10:13] [PASSED] 14 VFs
[11:10:13] [PASSED] 15 VFs
[11:10:13] [PASSED] 16 VFs
[11:10:13] [PASSED] 17 VFs
[11:10:13] [PASSED] 18 VFs
[11:10:13] [PASSED] 19 VFs
[11:10:13] [PASSED] 20 VFs
[11:10:13] [PASSED] 21 VFs
[11:10:13] [PASSED] 22 VFs
[11:10:13] [PASSED] 23 VFs
[11:10:13] [PASSED] 24 VFs
[11:10:13] [PASSED] 25 VFs
[11:10:13] [PASSED] 26 VFs
[11:10:13] [PASSED] 27 VFs
[11:10:13] [PASSED] 28 VFs
[11:10:13] [PASSED] 29 VFs
[11:10:13] [PASSED] 30 VFs
[11:10:13] [PASSED] 31 VFs
[11:10:13] [PASSED] 32 VFs
[11:10:13] [PASSED] 33 VFs
[11:10:13] [PASSED] 34 VFs
[11:10:13] [PASSED] 35 VFs
[11:10:13] [PASSED] 36 VFs
[11:10:13] [PASSED] 37 VFs
[11:10:13] [PASSED] 38 VFs
[11:10:13] [PASSED] 39 VFs
[11:10:13] [PASSED] 40 VFs
[11:10:13] [PASSED] 41 VFs
[11:10:13] [PASSED] 42 VFs
[11:10:13] [PASSED] 43 VFs
[11:10:13] [PASSED] 44 VFs
[11:10:13] [PASSED] 45 VFs
[11:10:13] [PASSED] 46 VFs
[11:10:13] [PASSED] 47 VFs
[11:10:13] [PASSED] 48 VFs
[11:10:13] [PASSED] 49 VFs
[11:10:13] [PASSED] 50 VFs
[11:10:13] [PASSED] 51 VFs
[11:10:13] [PASSED] 52 VFs
[11:10:13] [PASSED] 53 VFs
[11:10:13] [PASSED] 54 VFs
[11:10:13] [PASSED] 55 VFs
[11:10:13] [PASSED] 56 VFs
[11:10:13] [PASSED] 57 VFs
[11:10:13] [PASSED] 58 VFs
[11:10:13] [PASSED] 59 VFs
[11:10:13] [PASSED] 60 VFs
[11:10:13] [PASSED] 61 VFs
[11:10:13] [PASSED] 62 VFs
[11:10:13] [PASSED] 63 VFs
[11:10:13] ==================== [PASSED] fair_vram ====================
[11:10:13] ================== [PASSED] pf_gt_config ===================
[11:10:13] ===================== lmtt (1 subtest) =====================
[11:10:13] ======================== test_ops =========================
[11:10:13] [PASSED] 2-level
[11:10:13] [PASSED] multi-level
[11:10:13] ==================== [PASSED] test_ops =====================
[11:10:13] ====================== [PASSED] lmtt =======================
[11:10:13] ================= pf_service (11 subtests) =================
[11:10:13] [PASSED] pf_negotiate_any
[11:10:13] [PASSED] pf_negotiate_base_match
[11:10:13] [PASSED] pf_negotiate_base_newer
[11:10:13] [PASSED] pf_negotiate_base_next
[11:10:13] [SKIPPED] pf_negotiate_base_older
[11:10:13] [PASSED] pf_negotiate_base_prev
[11:10:13] [PASSED] pf_negotiate_latest_match
[11:10:13] [PASSED] pf_negotiate_latest_newer
[11:10:13] [PASSED] pf_negotiate_latest_next
[11:10:13] [SKIPPED] pf_negotiate_latest_older
[11:10:13] [SKIPPED] pf_negotiate_latest_prev
[11:10:13] =================== [PASSED] pf_service ====================
[11:10:13] ================== xe_eudebug (1 subtest) ==================
[11:10:13] =============== xe_eudebug_toggle_reg_kunit ===============
[11:10:13] ========== [SKIPPED] xe_eudebug_toggle_reg_kunit ===========
[11:10:13] =================== [SKIPPED] xe_eudebug ===================
[11:10:13] ================= xe_guc_g2g (2 subtests) ==================
[11:10:13] ============== xe_live_guc_g2g_kunit_default ==============
[11:10:13] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[11:10:13] ============== xe_live_guc_g2g_kunit_allmem ===============
[11:10:13] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[11:10:13] =================== [SKIPPED] xe_guc_g2g ===================
[11:10:13] =================== xe_mocs (2 subtests) ===================
[11:10:13] ================ xe_live_mocs_kernel_kunit ================
[11:10:13] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[11:10:13] ================ xe_live_mocs_reset_kunit =================
[11:10:13] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[11:10:13] ==================== [SKIPPED] xe_mocs =====================
[11:10:13] ================= xe_migrate (2 subtests) ==================
[11:10:13] ================= xe_migrate_sanity_kunit =================
[11:10:13] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[11:10:13] ================== xe_validate_ccs_kunit ==================
[11:10:13] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[11:10:13] =================== [SKIPPED] xe_migrate ===================
[11:10:13] ================== xe_dma_buf (1 subtest) ==================
[11:10:13] ==================== xe_dma_buf_kunit =====================
[11:10:13] ================ [SKIPPED] xe_dma_buf_kunit ================
[11:10:13] =================== [SKIPPED] xe_dma_buf ===================
[11:10:13] ================= xe_bo_shrink (1 subtest) =================
[11:10:13] =================== xe_bo_shrink_kunit ====================
[11:10:13] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[11:10:13] ================== [SKIPPED] xe_bo_shrink ==================
[11:10:13] ==================== xe_bo (2 subtests) ====================
[11:10:13] ================== xe_ccs_migrate_kunit ===================
[11:10:13] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[11:10:13] ==================== xe_bo_evict_kunit ====================
[11:10:13] =============== [SKIPPED] xe_bo_evict_kunit ================
[11:10:13] ===================== [SKIPPED] xe_bo ======================
[11:10:13] ==================== args (13 subtests) ====================
[11:10:13] [PASSED] count_args_test
[11:10:13] [PASSED] call_args_example
[11:10:13] [PASSED] call_args_test
[11:10:13] [PASSED] drop_first_arg_example
[11:10:13] [PASSED] drop_first_arg_test
[11:10:13] [PASSED] first_arg_example
[11:10:13] [PASSED] first_arg_test
[11:10:13] [PASSED] last_arg_example
[11:10:13] [PASSED] last_arg_test
[11:10:13] [PASSED] pick_arg_example
[11:10:13] [PASSED] if_args_example
[11:10:13] [PASSED] if_args_test
[11:10:13] [PASSED] sep_comma_example
[11:10:13] ====================== [PASSED] args =======================
[11:10:13] =================== xe_pci (3 subtests) ====================
[11:10:13] ==================== check_graphics_ip ====================
[11:10:13] [PASSED] 12.00 Xe_LP
[11:10:13] [PASSED] 12.10 Xe_LP+
[11:10:13] [PASSED] 12.55 Xe_HPG
[11:10:13] [PASSED] 12.60 Xe_HPC
[11:10:13] [PASSED] 12.70 Xe_LPG
[11:10:13] [PASSED] 12.71 Xe_LPG
[11:10:13] [PASSED] 12.74 Xe_LPG+
[11:10:13] [PASSED] 20.01 Xe2_HPG
[11:10:13] [PASSED] 20.02 Xe2_HPG
[11:10:13] [PASSED] 20.04 Xe2_LPG
[11:10:13] [PASSED] 30.00 Xe3_LPG
[11:10:13] [PASSED] 30.01 Xe3_LPG
[11:10:13] [PASSED] 30.03 Xe3_LPG
[11:10:13] [PASSED] 30.04 Xe3_LPG
[11:10:13] [PASSED] 30.05 Xe3_LPG
[11:10:13] [PASSED] 35.10 Xe3p_LPG
[11:10:13] [PASSED] 35.11 Xe3p_XPC
[11:10:13] ================ [PASSED] check_graphics_ip ================
[11:10:13] ===================== check_media_ip ======================
[11:10:13] [PASSED] 12.00 Xe_M
[11:10:13] [PASSED] 12.55 Xe_HPM
[11:10:13] [PASSED] 13.00 Xe_LPM+
[11:10:13] [PASSED] 13.01 Xe2_HPM
[11:10:13] [PASSED] 20.00 Xe2_LPM
[11:10:13] [PASSED] 30.00 Xe3_LPM
[11:10:13] [PASSED] 30.02 Xe3_LPM
[11:10:13] [PASSED] 35.00 Xe3p_LPM
[11:10:13] [PASSED] 35.03 Xe3p_HPM
[11:10:13] ================= [PASSED] check_media_ip ==================
[11:10:13] =================== check_platform_desc ===================
[11:10:13] [PASSED] 0x9A60 (TIGERLAKE)
[11:10:13] [PASSED] 0x9A68 (TIGERLAKE)
[11:10:13] [PASSED] 0x9A70 (TIGERLAKE)
[11:10:13] [PASSED] 0x9A40 (TIGERLAKE)
[11:10:13] [PASSED] 0x9A49 (TIGERLAKE)
[11:10:13] [PASSED] 0x9A59 (TIGERLAKE)
[11:10:13] [PASSED] 0x9A78 (TIGERLAKE)
[11:10:13] [PASSED] 0x9AC0 (TIGERLAKE)
[11:10:13] [PASSED] 0x9AC9 (TIGERLAKE)
[11:10:13] [PASSED] 0x9AD9 (TIGERLAKE)
[11:10:13] [PASSED] 0x9AF8 (TIGERLAKE)
[11:10:13] [PASSED] 0x4C80 (ROCKETLAKE)
[11:10:13] [PASSED] 0x4C8A (ROCKETLAKE)
[11:10:13] [PASSED] 0x4C8B (ROCKETLAKE)
[11:10:13] [PASSED] 0x4C8C (ROCKETLAKE)
[11:10:13] [PASSED] 0x4C90 (ROCKETLAKE)
[11:10:13] [PASSED] 0x4C9A (ROCKETLAKE)
[11:10:13] [PASSED] 0x4680 (ALDERLAKE_S)
[11:10:13] [PASSED] 0x4682 (ALDERLAKE_S)
[11:10:13] [PASSED] 0x4688 (ALDERLAKE_S)
[11:10:13] [PASSED] 0x468A (ALDERLAKE_S)
[11:10:13] [PASSED] 0x468B (ALDERLAKE_S)
[11:10:13] [PASSED] 0x4690 (ALDERLAKE_S)
[11:10:13] [PASSED] 0x4692 (ALDERLAKE_S)
[11:10:13] [PASSED] 0x4693 (ALDERLAKE_S)
[11:10:13] [PASSED] 0x46A0 (ALDERLAKE_P)
[11:10:13] [PASSED] 0x46A1 (ALDERLAKE_P)
[11:10:13] [PASSED] 0x46A2 (ALDERLAKE_P)
[11:10:13] [PASSED] 0x46A3 (ALDERLAKE_P)
[11:10:13] [PASSED] 0x46A6 (ALDERLAKE_P)
[11:10:13] [PASSED] 0x46A8 (ALDERLAKE_P)
[11:10:13] [PASSED] 0x46AA (ALDERLAKE_P)
[11:10:13] [PASSED] 0x462A (ALDERLAKE_P)
[11:10:13] [PASSED] 0x4626 (ALDERLAKE_P)
[11:10:13] [PASSED] 0x4628 (ALDERLAKE_P)
[11:10:13] [PASSED] 0x46B0 (ALDERLAKE_P)
[11:10:13] [PASSED] 0x46B1 (ALDERLAKE_P)
[11:10:13] [PASSED] 0x46B2 (ALDERLAKE_P)
[11:10:13] [PASSED] 0x46B3 (ALDERLAKE_P)
[11:10:13] [PASSED] 0x46C0 (ALDERLAKE_P)
[11:10:13] [PASSED] 0x46C1 (ALDERLAKE_P)
[11:10:13] [PASSED] 0x46C2 (ALDERLAKE_P)
[11:10:13] [PASSED] 0x46C3 (ALDERLAKE_P)
[11:10:13] [PASSED] 0x46D0 (ALDERLAKE_N)
[11:10:13] [PASSED] 0x46D1 (ALDERLAKE_N)
[11:10:13] [PASSED] 0x46D2 (ALDERLAKE_N)
[11:10:13] [PASSED] 0x46D3 (ALDERLAKE_N)
[11:10:13] [PASSED] 0x46D4 (ALDERLAKE_N)
[11:10:13] [PASSED] 0xA721 (ALDERLAKE_P)
[11:10:13] [PASSED] 0xA7A1 (ALDERLAKE_P)
[11:10:13] [PASSED] 0xA7A9 (ALDERLAKE_P)
[11:10:13] [PASSED] 0xA7AC (ALDERLAKE_P)
[11:10:13] [PASSED] 0xA7AD (ALDERLAKE_P)
[11:10:13] [PASSED] 0xA720 (ALDERLAKE_P)
[11:10:13] [PASSED] 0xA7A0 (ALDERLAKE_P)
[11:10:13] [PASSED] 0xA7A8 (ALDERLAKE_P)
[11:10:13] [PASSED] 0xA7AA (ALDERLAKE_P)
[11:10:13] [PASSED] 0xA7AB (ALDERLAKE_P)
[11:10:13] [PASSED] 0xA780 (ALDERLAKE_S)
[11:10:13] [PASSED] 0xA781 (ALDERLAKE_S)
[11:10:13] [PASSED] 0xA782 (ALDERLAKE_S)
[11:10:13] [PASSED] 0xA783 (ALDERLAKE_S)
[11:10:13] [PASSED] 0xA788 (ALDERLAKE_S)
[11:10:13] [PASSED] 0xA789 (ALDERLAKE_S)
[11:10:13] [PASSED] 0xA78A (ALDERLAKE_S)
[11:10:13] [PASSED] 0xA78B (ALDERLAKE_S)
[11:10:13] [PASSED] 0x4905 (DG1)
[11:10:13] [PASSED] 0x4906 (DG1)
[11:10:13] [PASSED] 0x4907 (DG1)
[11:10:13] [PASSED] 0x4908 (DG1)
[11:10:13] [PASSED] 0x4909 (DG1)
[11:10:13] [PASSED] 0x56C0 (DG2)
[11:10:13] [PASSED] 0x56C2 (DG2)
[11:10:13] [PASSED] 0x56C1 (DG2)
[11:10:13] [PASSED] 0x7D51 (METEORLAKE)
[11:10:13] [PASSED] 0x7DD1 (METEORLAKE)
[11:10:13] [PASSED] 0x7D41 (METEORLAKE)
[11:10:13] [PASSED] 0x7D67 (METEORLAKE)
[11:10:13] [PASSED] 0xB640 (METEORLAKE)
[11:10:13] [PASSED] 0x56A0 (DG2)
[11:10:13] [PASSED] 0x56A1 (DG2)
[11:10:13] [PASSED] 0x56A2 (DG2)
[11:10:13] [PASSED] 0x56BE (DG2)
[11:10:13] [PASSED] 0x56BF (DG2)
[11:10:13] [PASSED] 0x5690 (DG2)
[11:10:13] [PASSED] 0x5691 (DG2)
[11:10:13] [PASSED] 0x5692 (DG2)
[11:10:13] [PASSED] 0x56A5 (DG2)
[11:10:13] [PASSED] 0x56A6 (DG2)
[11:10:13] [PASSED] 0x56B0 (DG2)
[11:10:13] [PASSED] 0x56B1 (DG2)
[11:10:13] [PASSED] 0x56BA (DG2)
[11:10:13] [PASSED] 0x56BB (DG2)
[11:10:13] [PASSED] 0x56BC (DG2)
[11:10:13] [PASSED] 0x56BD (DG2)
[11:10:13] [PASSED] 0x5693 (DG2)
[11:10:13] [PASSED] 0x5694 (DG2)
[11:10:13] [PASSED] 0x5695 (DG2)
[11:10:13] [PASSED] 0x56A3 (DG2)
[11:10:13] [PASSED] 0x56A4 (DG2)
[11:10:13] [PASSED] 0x56B2 (DG2)
[11:10:13] [PASSED] 0x56B3 (DG2)
[11:10:13] [PASSED] 0x5696 (DG2)
[11:10:13] [PASSED] 0x5697 (DG2)
[11:10:13] [PASSED] 0xB69 (PVC)
[11:10:13] [PASSED] 0xB6E (PVC)
[11:10:13] [PASSED] 0xBD4 (PVC)
[11:10:13] [PASSED] 0xBD5 (PVC)
[11:10:13] [PASSED] 0xBD6 (PVC)
[11:10:13] [PASSED] 0xBD7 (PVC)
[11:10:13] [PASSED] 0xBD8 (PVC)
[11:10:13] [PASSED] 0xBD9 (PVC)
[11:10:13] [PASSED] 0xBDA (PVC)
[11:10:13] [PASSED] 0xBDB (PVC)
[11:10:13] [PASSED] 0xBE0 (PVC)
[11:10:13] [PASSED] 0xBE1 (PVC)
[11:10:13] [PASSED] 0xBE5 (PVC)
[11:10:13] [PASSED] 0x7D40 (METEORLAKE)
[11:10:13] [PASSED] 0x7D45 (METEORLAKE)
[11:10:13] [PASSED] 0x7D55 (METEORLAKE)
[11:10:13] [PASSED] 0x7D60 (METEORLAKE)
[11:10:13] [PASSED] 0x7DD5 (METEORLAKE)
[11:10:13] [PASSED] 0x6420 (LUNARLAKE)
[11:10:13] [PASSED] 0x64A0 (LUNARLAKE)
[11:10:13] [PASSED] 0x64B0 (LUNARLAKE)
[11:10:13] [PASSED] 0xE202 (BATTLEMAGE)
[11:10:13] [PASSED] 0xE209 (BATTLEMAGE)
[11:10:13] [PASSED] 0xE20B (BATTLEMAGE)
[11:10:13] [PASSED] 0xE20C (BATTLEMAGE)
[11:10:13] [PASSED] 0xE20D (BATTLEMAGE)
[11:10:13] [PASSED] 0xE210 (BATTLEMAGE)
[11:10:13] [PASSED] 0xE211 (BATTLEMAGE)
[11:10:13] [PASSED] 0xE212 (BATTLEMAGE)
[11:10:13] [PASSED] 0xE216 (BATTLEMAGE)
[11:10:13] [PASSED] 0xE220 (BATTLEMAGE)
[11:10:13] [PASSED] 0xE221 (BATTLEMAGE)
[11:10:13] [PASSED] 0xE222 (BATTLEMAGE)
[11:10:13] [PASSED] 0xE223 (BATTLEMAGE)
[11:10:13] [PASSED] 0xB080 (PANTHERLAKE)
[11:10:13] [PASSED] 0xB081 (PANTHERLAKE)
[11:10:13] [PASSED] 0xB082 (PANTHERLAKE)
[11:10:13] [PASSED] 0xB083 (PANTHERLAKE)
[11:10:13] [PASSED] 0xB084 (PANTHERLAKE)
[11:10:13] [PASSED] 0xB085 (PANTHERLAKE)
[11:10:13] [PASSED] 0xB086 (PANTHERLAKE)
[11:10:13] [PASSED] 0xB087 (PANTHERLAKE)
[11:10:13] [PASSED] 0xB08F (PANTHERLAKE)
[11:10:13] [PASSED] 0xB090 (PANTHERLAKE)
[11:10:13] [PASSED] 0xB0A0 (PANTHERLAKE)
[11:10:13] [PASSED] 0xB0B0 (PANTHERLAKE)
[11:10:13] [PASSED] 0xFD80 (PANTHERLAKE)
[11:10:13] [PASSED] 0xFD81 (PANTHERLAKE)
[11:10:13] [PASSED] 0xD740 (NOVALAKE_S)
[11:10:13] [PASSED] 0xD741 (NOVALAKE_S)
[11:10:13] [PASSED] 0xD742 (NOVALAKE_S)
[11:10:13] [PASSED] 0xD743 (NOVALAKE_S)
[11:10:13] [PASSED] 0xD744 (NOVALAKE_S)
[11:10:13] [PASSED] 0xD745 (NOVALAKE_S)
[11:10:13] [PASSED] 0x674C (CRESCENTISLAND)
[11:10:13] [PASSED] 0xD750 (NOVALAKE_P)
[11:10:13] [PASSED] 0xD751 (NOVALAKE_P)
[11:10:13] [PASSED] 0xD752 (NOVALAKE_P)
[11:10:13] [PASSED] 0xD753 (NOVALAKE_P)
[11:10:13] [PASSED] 0xD754 (NOVALAKE_P)
[11:10:13] [PASSED] 0xD755 (NOVALAKE_P)
[11:10:13] [PASSED] 0xD756 (NOVALAKE_P)
[11:10:13] [PASSED] 0xD757 (NOVALAKE_P)
[11:10:13] [PASSED] 0xD75F (NOVALAKE_P)
[11:10:13] =============== [PASSED] check_platform_desc ===============
[11:10:13] ===================== [PASSED] xe_pci ======================
[11:10:13] =================== xe_rtp (2 subtests) ====================
[11:10:13] =============== xe_rtp_process_to_sr_tests ================
[11:10:13] [PASSED] coalesce-same-reg
[11:10:13] [PASSED] no-match-no-add
[11:10:13] [PASSED] match-or
[11:10:13] [PASSED] match-or-xfail
[11:10:13] [PASSED] no-match-no-add-multiple-rules
[11:10:13] [PASSED] two-regs-two-entries
[11:10:13] [PASSED] clr-one-set-other
[11:10:13] [PASSED] set-field
[11:10:13] [PASSED] conflict-duplicate
[11:10:13] [PASSED] conflict-not-disjoint
[11:10:13] [PASSED] conflict-reg-type
[11:10:13] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[11:10:13] ================== xe_rtp_process_tests ===================
[11:10:13] [PASSED] active1
[11:10:13] [PASSED] active2
[11:10:13] [PASSED] active-inactive
[11:10:13] [PASSED] inactive-active
[11:10:13] [PASSED] inactive-1st_or_active-inactive
[11:10:13] [PASSED] inactive-2nd_or_active-inactive
[11:10:13] [PASSED] inactive-last_or_active-inactive
[11:10:13] [PASSED] inactive-no_or_active-inactive
[11:10:13] ============== [PASSED] xe_rtp_process_tests ===============
[11:10:13] ===================== [PASSED] xe_rtp ======================
[11:10:13] ==================== xe_wa (1 subtest) =====================
[11:10:13] ======================== xe_wa_gt =========================
[11:10:13] [PASSED] TIGERLAKE B0
[11:10:13] [PASSED] DG1 A0
[11:10:13] [PASSED] DG1 B0
[11:10:13] [PASSED] ALDERLAKE_S A0
[11:10:13] [PASSED] ALDERLAKE_S B0
[11:10:13] [PASSED] ALDERLAKE_S C0
[11:10:13] [PASSED] ALDERLAKE_S D0
[11:10:13] [PASSED] ALDERLAKE_P A0
[11:10:13] [PASSED] ALDERLAKE_P B0
[11:10:13] [PASSED] ALDERLAKE_P C0
[11:10:13] [PASSED] ALDERLAKE_S RPLS D0
[11:10:13] [PASSED] ALDERLAKE_P RPLU E0
[11:10:13] [PASSED] DG2 G10 C0
[11:10:13] [PASSED] DG2 G11 B1
[11:10:13] [PASSED] DG2 G12 A1
[11:10:13] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[11:10:13] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[11:10:13] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[11:10:13] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[11:10:13] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[11:10:13] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[11:10:13] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[11:10:13] ==================== [PASSED] xe_wa_gt =====================
[11:10:13] ====================== [PASSED] xe_wa ======================
[11:10:13] ============================================================
[11:10:13] Testing complete. Ran 598 tests: passed: 579, skipped: 19
[11:10:13] Elapsed time: 36.340s total, 4.220s configuring, 31.504s building, 0.609s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[11:10:13] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[11:10:15] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[11:10:39] Starting KUnit Kernel (1/1)...
[11:10:39] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[11:10:39] ============ drm_test_pick_cmdline (2 subtests) ============
[11:10:39] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[11:10:39] =============== drm_test_pick_cmdline_named ===============
[11:10:39] [PASSED] NTSC
[11:10:39] [PASSED] NTSC-J
[11:10:39] [PASSED] PAL
[11:10:39] [PASSED] PAL-M
[11:10:39] =========== [PASSED] drm_test_pick_cmdline_named ===========
[11:10:39] ============== [PASSED] drm_test_pick_cmdline ==============
[11:10:39] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[11:10:39] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[11:10:39] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[11:10:39] =========== drm_validate_clone_mode (2 subtests) ===========
[11:10:39] ============== drm_test_check_in_clone_mode ===============
[11:10:39] [PASSED] in_clone_mode
[11:10:39] [PASSED] not_in_clone_mode
[11:10:39] ========== [PASSED] drm_test_check_in_clone_mode ===========
[11:10:39] =============== drm_test_check_valid_clones ===============
[11:10:39] [PASSED] not_in_clone_mode
[11:10:39] [PASSED] valid_clone
[11:10:39] [PASSED] invalid_clone
[11:10:39] =========== [PASSED] drm_test_check_valid_clones ===========
[11:10:39] ============= [PASSED] drm_validate_clone_mode =============
[11:10:39] ============= drm_validate_modeset (1 subtest) =============
[11:10:39] [PASSED] drm_test_check_connector_changed_modeset
[11:10:39] ============== [PASSED] drm_validate_modeset ===============
[11:10:39] ====== drm_test_bridge_get_current_state (2 subtests) ======
[11:10:39] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[11:10:39] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[11:10:39] ======== [PASSED] drm_test_bridge_get_current_state ========
[11:10:39] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[11:10:39] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[11:10:39] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[11:10:39] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[11:10:39] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[11:10:39] ============== drm_bridge_alloc (2 subtests) ===============
[11:10:39] [PASSED] drm_test_drm_bridge_alloc_basic
[11:10:39] [PASSED] drm_test_drm_bridge_alloc_get_put
[11:10:39] ================ [PASSED] drm_bridge_alloc =================
[11:10:39] ============= drm_cmdline_parser (40 subtests) =============
[11:10:39] [PASSED] drm_test_cmdline_force_d_only
[11:10:39] [PASSED] drm_test_cmdline_force_D_only_dvi
[11:10:39] [PASSED] drm_test_cmdline_force_D_only_hdmi
[11:10:39] [PASSED] drm_test_cmdline_force_D_only_not_digital
[11:10:39] [PASSED] drm_test_cmdline_force_e_only
[11:10:39] [PASSED] drm_test_cmdline_res
[11:10:39] [PASSED] drm_test_cmdline_res_vesa
[11:10:39] [PASSED] drm_test_cmdline_res_vesa_rblank
[11:10:39] [PASSED] drm_test_cmdline_res_rblank
[11:10:39] [PASSED] drm_test_cmdline_res_bpp
[11:10:39] [PASSED] drm_test_cmdline_res_refresh
[11:10:39] [PASSED] drm_test_cmdline_res_bpp_refresh
[11:10:39] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[11:10:39] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[11:10:39] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[11:10:39] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[11:10:39] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[11:10:39] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[11:10:39] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[11:10:39] [PASSED] drm_test_cmdline_res_margins_force_on
[11:10:39] [PASSED] drm_test_cmdline_res_vesa_margins
[11:10:39] [PASSED] drm_test_cmdline_name
[11:10:39] [PASSED] drm_test_cmdline_name_bpp
[11:10:39] [PASSED] drm_test_cmdline_name_option
[11:10:39] [PASSED] drm_test_cmdline_name_bpp_option
[11:10:39] [PASSED] drm_test_cmdline_rotate_0
[11:10:39] [PASSED] drm_test_cmdline_rotate_90
[11:10:39] [PASSED] drm_test_cmdline_rotate_180
[11:10:39] [PASSED] drm_test_cmdline_rotate_270
[11:10:39] [PASSED] drm_test_cmdline_hmirror
[11:10:39] [PASSED] drm_test_cmdline_vmirror
[11:10:39] [PASSED] drm_test_cmdline_margin_options
[11:10:39] [PASSED] drm_test_cmdline_multiple_options
[11:10:39] [PASSED] drm_test_cmdline_bpp_extra_and_option
[11:10:39] [PASSED] drm_test_cmdline_extra_and_option
[11:10:39] [PASSED] drm_test_cmdline_freestanding_options
[11:10:39] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[11:10:39] [PASSED] drm_test_cmdline_panel_orientation
[11:10:39] ================ drm_test_cmdline_invalid =================
[11:10:39] [PASSED] margin_only
[11:10:39] [PASSED] interlace_only
[11:10:39] [PASSED] res_missing_x
[11:10:39] [PASSED] res_missing_y
[11:10:39] [PASSED] res_bad_y
[11:10:39] [PASSED] res_missing_y_bpp
[11:10:39] [PASSED] res_bad_bpp
[11:10:39] [PASSED] res_bad_refresh
[11:10:39] [PASSED] res_bpp_refresh_force_on_off
[11:10:39] [PASSED] res_invalid_mode
[11:10:39] [PASSED] res_bpp_wrong_place_mode
[11:10:39] [PASSED] name_bpp_refresh
[11:10:39] [PASSED] name_refresh
[11:10:39] [PASSED] name_refresh_wrong_mode
[11:10:39] [PASSED] name_refresh_invalid_mode
[11:10:39] [PASSED] rotate_multiple
[11:10:39] [PASSED] rotate_invalid_val
[11:10:39] [PASSED] rotate_truncated
[11:10:39] [PASSED] invalid_option
[11:10:39] [PASSED] invalid_tv_option
[11:10:39] [PASSED] truncated_tv_option
[11:10:39] ============ [PASSED] drm_test_cmdline_invalid =============
[11:10:39] =============== drm_test_cmdline_tv_options ===============
[11:10:39] [PASSED] NTSC
[11:10:39] [PASSED] NTSC_443
[11:10:39] [PASSED] NTSC_J
[11:10:39] [PASSED] PAL
[11:10:39] [PASSED] PAL_M
[11:10:39] [PASSED] PAL_N
[11:10:39] [PASSED] SECAM
[11:10:39] [PASSED] MONO_525
[11:10:39] [PASSED] MONO_625
[11:10:39] =========== [PASSED] drm_test_cmdline_tv_options ===========
[11:10:39] =============== [PASSED] drm_cmdline_parser ================
[11:10:39] ========== drmm_connector_hdmi_init (20 subtests) ==========
[11:10:39] [PASSED] drm_test_connector_hdmi_init_valid
[11:10:39] [PASSED] drm_test_connector_hdmi_init_bpc_8
[11:10:39] [PASSED] drm_test_connector_hdmi_init_bpc_10
[11:10:39] [PASSED] drm_test_connector_hdmi_init_bpc_12
[11:10:39] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[11:10:39] [PASSED] drm_test_connector_hdmi_init_bpc_null
[11:10:39] [PASSED] drm_test_connector_hdmi_init_formats_empty
[11:10:39] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[11:10:39] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[11:10:39] [PASSED] supported_formats=0x9 yuv420_allowed=1
[11:10:39] [PASSED] supported_formats=0x9 yuv420_allowed=0
[11:10:39] [PASSED] supported_formats=0x5 yuv420_allowed=1
[11:10:39] [PASSED] supported_formats=0x5 yuv420_allowed=0
[11:10:39] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[11:10:39] [PASSED] drm_test_connector_hdmi_init_null_ddc
[11:10:39] [PASSED] drm_test_connector_hdmi_init_null_product
[11:10:39] [PASSED] drm_test_connector_hdmi_init_null_vendor
[11:10:39] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[11:10:39] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[11:10:39] [PASSED] drm_test_connector_hdmi_init_product_valid
[11:10:39] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[11:10:39] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[11:10:39] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[11:10:39] ========= drm_test_connector_hdmi_init_type_valid =========
[11:10:39] [PASSED] HDMI-A
[11:10:39] [PASSED] HDMI-B
[11:10:39] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[11:10:39] ======== drm_test_connector_hdmi_init_type_invalid ========
[11:10:39] [PASSED] Unknown
[11:10:39] [PASSED] VGA
[11:10:39] [PASSED] DVI-I
[11:10:39] [PASSED] DVI-D
[11:10:39] [PASSED] DVI-A
[11:10:39] [PASSED] Composite
[11:10:39] [PASSED] SVIDEO
[11:10:39] [PASSED] LVDS
[11:10:39] [PASSED] Component
[11:10:39] [PASSED] DIN
[11:10:39] [PASSED] DP
[11:10:39] [PASSED] TV
[11:10:39] [PASSED] eDP
[11:10:39] [PASSED] Virtual
[11:10:39] [PASSED] DSI
[11:10:39] [PASSED] DPI
[11:10:39] [PASSED] Writeback
[11:10:39] [PASSED] SPI
[11:10:39] [PASSED] USB
[11:10:39] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[11:10:39] ============ [PASSED] drmm_connector_hdmi_init =============
[11:10:39] ============= drmm_connector_init (3 subtests) =============
[11:10:39] [PASSED] drm_test_drmm_connector_init
[11:10:39] [PASSED] drm_test_drmm_connector_init_null_ddc
[11:10:39] ========= drm_test_drmm_connector_init_type_valid =========
[11:10:39] [PASSED] Unknown
[11:10:39] [PASSED] VGA
[11:10:39] [PASSED] DVI-I
[11:10:39] [PASSED] DVI-D
[11:10:39] [PASSED] DVI-A
[11:10:39] [PASSED] Composite
[11:10:39] [PASSED] SVIDEO
[11:10:39] [PASSED] LVDS
[11:10:39] [PASSED] Component
[11:10:39] [PASSED] DIN
[11:10:39] [PASSED] DP
[11:10:39] [PASSED] HDMI-A
[11:10:39] [PASSED] HDMI-B
[11:10:39] [PASSED] TV
[11:10:39] [PASSED] eDP
[11:10:39] [PASSED] Virtual
[11:10:39] [PASSED] DSI
[11:10:39] [PASSED] DPI
[11:10:39] [PASSED] Writeback
[11:10:39] [PASSED] SPI
[11:10:39] [PASSED] USB
[11:10:39] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[11:10:39] =============== [PASSED] drmm_connector_init ===============
[11:10:39] ========= drm_connector_dynamic_init (6 subtests) ==========
[11:10:39] [PASSED] drm_test_drm_connector_dynamic_init
[11:10:39] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[11:10:39] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[11:10:39] [PASSED] drm_test_drm_connector_dynamic_init_properties
[11:10:39] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[11:10:39] [PASSED] Unknown
[11:10:39] [PASSED] VGA
[11:10:39] [PASSED] DVI-I
[11:10:39] [PASSED] DVI-D
[11:10:39] [PASSED] DVI-A
[11:10:39] [PASSED] Composite
[11:10:39] [PASSED] SVIDEO
[11:10:39] [PASSED] LVDS
[11:10:39] [PASSED] Component
[11:10:39] [PASSED] DIN
[11:10:39] [PASSED] DP
[11:10:39] [PASSED] HDMI-A
[11:10:39] [PASSED] HDMI-B
[11:10:39] [PASSED] TV
[11:10:39] [PASSED] eDP
[11:10:39] [PASSED] Virtual
[11:10:39] [PASSED] DSI
[11:10:39] [PASSED] DPI
[11:10:39] [PASSED] Writeback
[11:10:39] [PASSED] SPI
[11:10:39] [PASSED] USB
[11:10:39] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[11:10:39] ======== drm_test_drm_connector_dynamic_init_name =========
[11:10:39] [PASSED] Unknown
[11:10:39] [PASSED] VGA
[11:10:39] [PASSED] DVI-I
[11:10:39] [PASSED] DVI-D
[11:10:39] [PASSED] DVI-A
[11:10:39] [PASSED] Composite
[11:10:39] [PASSED] SVIDEO
[11:10:39] [PASSED] LVDS
[11:10:39] [PASSED] Component
[11:10:39] [PASSED] DIN
[11:10:39] [PASSED] DP
[11:10:39] [PASSED] HDMI-A
[11:10:39] [PASSED] HDMI-B
[11:10:39] [PASSED] TV
[11:10:39] [PASSED] eDP
[11:10:39] [PASSED] Virtual
[11:10:39] [PASSED] DSI
[11:10:39] [PASSED] DPI
[11:10:39] [PASSED] Writeback
[11:10:39] [PASSED] SPI
[11:10:39] [PASSED] USB
[11:10:39] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[11:10:39] =========== [PASSED] drm_connector_dynamic_init ============
[11:10:39] ==== drm_connector_dynamic_register_early (4 subtests) =====
[11:10:39] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[11:10:39] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[11:10:39] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[11:10:39] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[11:10:39] ====== [PASSED] drm_connector_dynamic_register_early =======
[11:10:39] ======= drm_connector_dynamic_register (7 subtests) ========
[11:10:39] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[11:10:39] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[11:10:39] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[11:10:39] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[11:10:39] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[11:10:39] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[11:10:39] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[11:10:39] ========= [PASSED] drm_connector_dynamic_register ==========
[11:10:39] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[11:10:39] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[11:10:39] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[11:10:39] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[11:10:39] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[11:10:39] ========== drm_test_get_tv_mode_from_name_valid ===========
[11:10:39] [PASSED] NTSC
[11:10:39] [PASSED] NTSC-443
[11:10:39] [PASSED] NTSC-J
[11:10:39] [PASSED] PAL
[11:10:39] [PASSED] PAL-M
[11:10:39] [PASSED] PAL-N
[11:10:39] [PASSED] SECAM
[11:10:39] [PASSED] Mono
[11:10:39] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[11:10:39] [PASSED] drm_test_get_tv_mode_from_name_truncated
[11:10:39] ============ [PASSED] drm_get_tv_mode_from_name ============
[11:10:39] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[11:10:39] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[11:10:39] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[11:10:39] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[11:10:39] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[11:10:39] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[11:10:39] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[11:10:39] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[11:10:39] [PASSED] VIC 96
[11:10:39] [PASSED] VIC 97
[11:10:39] [PASSED] VIC 101
[11:10:39] [PASSED] VIC 102
[11:10:39] [PASSED] VIC 106
[11:10:39] [PASSED] VIC 107
[11:10:39] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[11:10:39] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[11:10:39] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[11:10:39] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[11:10:39] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[11:10:39] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[11:10:39] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[11:10:39] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[11:10:39] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[11:10:39] [PASSED] Automatic
[11:10:39] [PASSED] Full
[11:10:39] [PASSED] Limited 16:235
[11:10:39] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[11:10:39] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[11:10:39] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[11:10:39] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[11:10:39] === drm_test_drm_hdmi_connector_get_output_format_name ====
[11:10:39] [PASSED] RGB
[11:10:39] [PASSED] YUV 4:2:0
[11:10:39] [PASSED] YUV 4:2:2
[11:10:39] [PASSED] YUV 4:4:4
[11:10:39] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[11:10:39] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[11:10:39] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[11:10:39] ============= drm_damage_helper (21 subtests) ==============
[11:10:39] [PASSED] drm_test_damage_iter_no_damage
[11:10:39] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[11:10:39] [PASSED] drm_test_damage_iter_no_damage_src_moved
[11:10:39] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[11:10:39] [PASSED] drm_test_damage_iter_no_damage_not_visible
[11:10:39] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[11:10:39] [PASSED] drm_test_damage_iter_no_damage_no_fb
[11:10:39] [PASSED] drm_test_damage_iter_simple_damage
[11:10:39] [PASSED] drm_test_damage_iter_single_damage
[11:10:39] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[11:10:39] [PASSED] drm_test_damage_iter_single_damage_outside_src
[11:10:39] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[11:10:39] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[11:10:39] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[11:10:39] [PASSED] drm_test_damage_iter_single_damage_src_moved
[11:10:39] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[11:10:39] [PASSED] drm_test_damage_iter_damage
[11:10:39] [PASSED] drm_test_damage_iter_damage_one_intersect
[11:10:39] [PASSED] drm_test_damage_iter_damage_one_outside
[11:10:39] [PASSED] drm_test_damage_iter_damage_src_moved
[11:10:39] [PASSED] drm_test_damage_iter_damage_not_visible
[11:10:39] ================ [PASSED] drm_damage_helper ================
[11:10:39] ============== drm_dp_mst_helper (3 subtests) ==============
[11:10:39] ============== drm_test_dp_mst_calc_pbn_mode ==============
[11:10:39] [PASSED] Clock 154000 BPP 30 DSC disabled
[11:10:39] [PASSED] Clock 234000 BPP 30 DSC disabled
[11:10:39] [PASSED] Clock 297000 BPP 24 DSC disabled
[11:10:39] [PASSED] Clock 332880 BPP 24 DSC enabled
[11:10:39] [PASSED] Clock 324540 BPP 24 DSC enabled
[11:10:39] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[11:10:39] ============== drm_test_dp_mst_calc_pbn_div ===============
[11:10:39] [PASSED] Link rate 2000000 lane count 4
[11:10:39] [PASSED] Link rate 2000000 lane count 2
[11:10:39] [PASSED] Link rate 2000000 lane count 1
[11:10:39] [PASSED] Link rate 1350000 lane count 4
[11:10:39] [PASSED] Link rate 1350000 lane count 2
[11:10:39] [PASSED] Link rate 1350000 lane count 1
[11:10:39] [PASSED] Link rate 1000000 lane count 4
[11:10:39] [PASSED] Link rate 1000000 lane count 2
[11:10:39] [PASSED] Link rate 1000000 lane count 1
[11:10:39] [PASSED] Link rate 810000 lane count 4
[11:10:39] [PASSED] Link rate 810000 lane count 2
[11:10:39] [PASSED] Link rate 810000 lane count 1
[11:10:39] [PASSED] Link rate 540000 lane count 4
[11:10:39] [PASSED] Link rate 540000 lane count 2
[11:10:39] [PASSED] Link rate 540000 lane count 1
[11:10:39] [PASSED] Link rate 270000 lane count 4
[11:10:39] [PASSED] Link rate 270000 lane count 2
[11:10:39] [PASSED] Link rate 270000 lane count 1
[11:10:39] [PASSED] Link rate 162000 lane count 4
[11:10:39] [PASSED] Link rate 162000 lane count 2
[11:10:39] [PASSED] Link rate 162000 lane count 1
[11:10:39] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[11:10:39] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[11:10:39] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[11:10:39] [PASSED] DP_POWER_UP_PHY with port number
[11:10:39] [PASSED] DP_POWER_DOWN_PHY with port number
[11:10:39] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[11:10:39] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[11:10:39] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[11:10:39] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[11:10:39] [PASSED] DP_QUERY_PAYLOAD with port number
[11:10:39] [PASSED] DP_QUERY_PAYLOAD with VCPI
[11:10:39] [PASSED] DP_REMOTE_DPCD_READ with port number
[11:10:39] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[11:10:39] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[11:10:39] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[11:10:39] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[11:10:39] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[11:10:39] [PASSED] DP_REMOTE_I2C_READ with port number
[11:10:39] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[11:10:39] [PASSED] DP_REMOTE_I2C_READ with transactions array
[11:10:39] [PASSED] DP_REMOTE_I2C_WRITE with port number
[11:10:39] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[11:10:39] [PASSED] DP_REMOTE_I2C_WRITE with data array
[11:10:39] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[11:10:39] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[11:10:39] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[11:10:39] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[11:10:39] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[11:10:39] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[11:10:39] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[11:10:39] ================ [PASSED] drm_dp_mst_helper ================
[11:10:39] ================== drm_exec (7 subtests) ===================
[11:10:39] [PASSED] sanitycheck
[11:10:39] [PASSED] test_lock
[11:10:39] [PASSED] test_lock_unlock
[11:10:39] [PASSED] test_duplicates
[11:10:39] [PASSED] test_prepare
[11:10:39] [PASSED] test_prepare_array
[11:10:39] [PASSED] test_multiple_loops
[11:10:39] ==================== [PASSED] drm_exec =====================
[11:10:39] =========== drm_format_helper_test (17 subtests) ===========
[11:10:39] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[11:10:39] [PASSED] single_pixel_source_buffer
[11:10:39] [PASSED] single_pixel_clip_rectangle
[11:10:39] [PASSED] well_known_colors
[11:10:39] [PASSED] destination_pitch
[11:10:39] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[11:10:39] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[11:10:39] [PASSED] single_pixel_source_buffer
[11:10:39] [PASSED] single_pixel_clip_rectangle
[11:10:39] [PASSED] well_known_colors
[11:10:39] [PASSED] destination_pitch
[11:10:39] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[11:10:39] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[11:10:39] [PASSED] single_pixel_source_buffer
[11:10:39] [PASSED] single_pixel_clip_rectangle
[11:10:39] [PASSED] well_known_colors
[11:10:39] [PASSED] destination_pitch
[11:10:39] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[11:10:39] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[11:10:39] [PASSED] single_pixel_source_buffer
[11:10:39] [PASSED] single_pixel_clip_rectangle
[11:10:39] [PASSED] well_known_colors
[11:10:39] [PASSED] destination_pitch
[11:10:39] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[11:10:39] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[11:10:39] [PASSED] single_pixel_source_buffer
[11:10:39] [PASSED] single_pixel_clip_rectangle
[11:10:39] [PASSED] well_known_colors
[11:10:39] [PASSED] destination_pitch
[11:10:39] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[11:10:39] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[11:10:39] [PASSED] single_pixel_source_buffer
[11:10:39] [PASSED] single_pixel_clip_rectangle
[11:10:39] [PASSED] well_known_colors
[11:10:39] [PASSED] destination_pitch
[11:10:39] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[11:10:39] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[11:10:39] [PASSED] single_pixel_source_buffer
[11:10:39] [PASSED] single_pixel_clip_rectangle
[11:10:39] [PASSED] well_known_colors
[11:10:39] [PASSED] destination_pitch
[11:10:39] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[11:10:39] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[11:10:39] [PASSED] single_pixel_source_buffer
[11:10:39] [PASSED] single_pixel_clip_rectangle
[11:10:39] [PASSED] well_known_colors
[11:10:39] [PASSED] destination_pitch
[11:10:39] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[11:10:39] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[11:10:39] [PASSED] single_pixel_source_buffer
[11:10:39] [PASSED] single_pixel_clip_rectangle
[11:10:39] [PASSED] well_known_colors
[11:10:39] [PASSED] destination_pitch
[11:10:39] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[11:10:39] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[11:10:39] [PASSED] single_pixel_source_buffer
[11:10:39] [PASSED] single_pixel_clip_rectangle
[11:10:39] [PASSED] well_known_colors
[11:10:39] [PASSED] destination_pitch
[11:10:39] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[11:10:39] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[11:10:39] [PASSED] single_pixel_source_buffer
[11:10:39] [PASSED] single_pixel_clip_rectangle
[11:10:39] [PASSED] well_known_colors
[11:10:39] [PASSED] destination_pitch
[11:10:39] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[11:10:39] ============== drm_test_fb_xrgb8888_to_mono ===============
[11:10:39] [PASSED] single_pixel_source_buffer
[11:10:39] [PASSED] single_pixel_clip_rectangle
[11:10:39] [PASSED] well_known_colors
[11:10:39] [PASSED] destination_pitch
[11:10:39] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[11:10:39] ==================== drm_test_fb_swab =====================
[11:10:39] [PASSED] single_pixel_source_buffer
[11:10:39] [PASSED] single_pixel_clip_rectangle
[11:10:39] [PASSED] well_known_colors
[11:10:39] [PASSED] destination_pitch
[11:10:39] ================ [PASSED] drm_test_fb_swab =================
[11:10:39] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[11:10:39] [PASSED] single_pixel_source_buffer
[11:10:39] [PASSED] single_pixel_clip_rectangle
[11:10:39] [PASSED] well_known_colors
[11:10:39] [PASSED] destination_pitch
[11:10:39] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[11:10:39] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[11:10:39] [PASSED] single_pixel_source_buffer
[11:10:39] [PASSED] single_pixel_clip_rectangle
[11:10:39] [PASSED] well_known_colors
[11:10:39] [PASSED] destination_pitch
[11:10:39] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[11:10:39] ================= drm_test_fb_clip_offset =================
[11:10:39] [PASSED] pass through
[11:10:39] [PASSED] horizontal offset
[11:10:39] [PASSED] vertical offset
[11:10:39] [PASSED] horizontal and vertical offset
[11:10:39] [PASSED] horizontal offset (custom pitch)
[11:10:39] [PASSED] vertical offset (custom pitch)
[11:10:39] [PASSED] horizontal and vertical offset (custom pitch)
[11:10:39] ============= [PASSED] drm_test_fb_clip_offset =============
[11:10:39] =================== drm_test_fb_memcpy ====================
[11:10:39] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[11:10:39] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[11:10:39] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[11:10:39] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[11:10:39] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[11:10:39] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[11:10:39] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[11:10:39] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[11:10:39] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[11:10:39] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[11:10:39] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[11:10:39] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[11:10:39] =============== [PASSED] drm_test_fb_memcpy ================
[11:10:39] ============= [PASSED] drm_format_helper_test ==============
[11:10:39] ================= drm_format (18 subtests) =================
[11:10:39] [PASSED] drm_test_format_block_width_invalid
[11:10:39] [PASSED] drm_test_format_block_width_one_plane
[11:10:39] [PASSED] drm_test_format_block_width_two_plane
[11:10:39] [PASSED] drm_test_format_block_width_three_plane
[11:10:39] [PASSED] drm_test_format_block_width_tiled
[11:10:39] [PASSED] drm_test_format_block_height_invalid
[11:10:39] [PASSED] drm_test_format_block_height_one_plane
[11:10:39] [PASSED] drm_test_format_block_height_two_plane
[11:10:39] [PASSED] drm_test_format_block_height_three_plane
[11:10:39] [PASSED] drm_test_format_block_height_tiled
[11:10:39] [PASSED] drm_test_format_min_pitch_invalid
[11:10:39] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[11:10:39] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[11:10:39] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[11:10:39] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[11:10:39] [PASSED] drm_test_format_min_pitch_two_plane
[11:10:39] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[11:10:39] [PASSED] drm_test_format_min_pitch_tiled
[11:10:39] =================== [PASSED] drm_format ====================
[11:10:39] ============== drm_framebuffer (10 subtests) ===============
[11:10:39] ========== drm_test_framebuffer_check_src_coords ==========
[11:10:39] [PASSED] Success: source fits into fb
[11:10:39] [PASSED] Fail: overflowing fb with x-axis coordinate
[11:10:39] [PASSED] Fail: overflowing fb with y-axis coordinate
[11:10:39] [PASSED] Fail: overflowing fb with source width
[11:10:39] [PASSED] Fail: overflowing fb with source height
[11:10:39] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[11:10:39] [PASSED] drm_test_framebuffer_cleanup
[11:10:39] =============== drm_test_framebuffer_create ===============
[11:10:39] [PASSED] ABGR8888 normal sizes
[11:10:39] [PASSED] ABGR8888 max sizes
[11:10:39] [PASSED] ABGR8888 pitch greater than min required
[11:10:39] [PASSED] ABGR8888 pitch less than min required
[11:10:39] [PASSED] ABGR8888 Invalid width
[11:10:39] [PASSED] ABGR8888 Invalid buffer handle
[11:10:39] [PASSED] No pixel format
[11:10:39] [PASSED] ABGR8888 Width 0
[11:10:39] [PASSED] ABGR8888 Height 0
[11:10:39] [PASSED] ABGR8888 Out of bound height * pitch combination
[11:10:39] [PASSED] ABGR8888 Large buffer offset
[11:10:39] [PASSED] ABGR8888 Buffer offset for inexistent plane
[11:10:39] [PASSED] ABGR8888 Invalid flag
[11:10:39] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[11:10:39] [PASSED] ABGR8888 Valid buffer modifier
[11:10:39] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[11:10:39] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[11:10:39] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[11:10:39] [PASSED] NV12 Normal sizes
[11:10:39] [PASSED] NV12 Max sizes
[11:10:39] [PASSED] NV12 Invalid pitch
[11:10:39] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[11:10:39] [PASSED] NV12 different modifier per-plane
[11:10:39] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[11:10:39] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[11:10:39] [PASSED] NV12 Modifier for inexistent plane
[11:10:39] [PASSED] NV12 Handle for inexistent plane
[11:10:39] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[11:10:39] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[11:10:39] [PASSED] YVU420 Normal sizes
[11:10:39] [PASSED] YVU420 Max sizes
[11:10:39] [PASSED] YVU420 Invalid pitch
[11:10:39] [PASSED] YVU420 Different pitches
[11:10:39] [PASSED] YVU420 Different buffer offsets/pitches
[11:10:39] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[11:10:39] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[11:10:39] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[11:10:39] [PASSED] YVU420 Valid modifier
[11:10:39] [PASSED] YVU420 Different modifiers per plane
[11:10:39] [PASSED] YVU420 Modifier for inexistent plane
[11:10:39] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[11:10:39] [PASSED] X0L2 Normal sizes
[11:10:39] [PASSED] X0L2 Max sizes
[11:10:39] [PASSED] X0L2 Invalid pitch
[11:10:39] [PASSED] X0L2 Pitch greater than minimum required
[11:10:39] [PASSED] X0L2 Handle for inexistent plane
[11:10:39] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[11:10:39] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[11:10:39] [PASSED] X0L2 Valid modifier
[11:10:39] [PASSED] X0L2 Modifier for inexistent plane
[11:10:39] =========== [PASSED] drm_test_framebuffer_create ===========
[11:10:39] [PASSED] drm_test_framebuffer_free
[11:10:39] [PASSED] drm_test_framebuffer_init
[11:10:39] [PASSED] drm_test_framebuffer_init_bad_format
[11:10:39] [PASSED] drm_test_framebuffer_init_dev_mismatch
[11:10:39] [PASSED] drm_test_framebuffer_lookup
[11:10:39] [PASSED] drm_test_framebuffer_lookup_inexistent
[11:10:39] [PASSED] drm_test_framebuffer_modifiers_not_supported
[11:10:39] ================= [PASSED] drm_framebuffer =================
[11:10:39] ================ drm_gem_shmem (8 subtests) ================
[11:10:39] [PASSED] drm_gem_shmem_test_obj_create
[11:10:39] [PASSED] drm_gem_shmem_test_obj_create_private
[11:10:39] [PASSED] drm_gem_shmem_test_pin_pages
[11:10:39] [PASSED] drm_gem_shmem_test_vmap
[11:10:39] [PASSED] drm_gem_shmem_test_get_sg_table
[11:10:39] [PASSED] drm_gem_shmem_test_get_pages_sgt
[11:10:39] [PASSED] drm_gem_shmem_test_madvise
[11:10:39] [PASSED] drm_gem_shmem_test_purge
[11:10:39] ================== [PASSED] drm_gem_shmem ==================
[11:10:39] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[11:10:39] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[11:10:39] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[11:10:39] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[11:10:39] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[11:10:39] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[11:10:39] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[11:10:39] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[11:10:39] [PASSED] Automatic
[11:10:39] [PASSED] Full
[11:10:39] [PASSED] Limited 16:235
[11:10:39] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[11:10:39] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[11:10:39] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[11:10:39] [PASSED] drm_test_check_disable_connector
[11:10:39] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[11:10:39] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[11:10:39] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[11:10:39] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[11:10:39] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[11:10:39] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[11:10:39] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[11:10:39] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[11:10:39] [PASSED] drm_test_check_output_bpc_dvi
[11:10:39] [PASSED] drm_test_check_output_bpc_format_vic_1
[11:10:39] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[11:10:39] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[11:10:39] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[11:10:39] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[11:10:39] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[11:10:39] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[11:10:39] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[11:10:39] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[11:10:39] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[11:10:39] [PASSED] drm_test_check_broadcast_rgb_value
[11:10:39] [PASSED] drm_test_check_bpc_8_value
[11:10:39] [PASSED] drm_test_check_bpc_10_value
[11:10:39] [PASSED] drm_test_check_bpc_12_value
[11:10:39] [PASSED] drm_test_check_format_value
[11:10:39] [PASSED] drm_test_check_tmds_char_value
[11:10:39] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[11:10:39] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[11:10:39] [PASSED] drm_test_check_mode_valid
[11:10:39] [PASSED] drm_test_check_mode_valid_reject
[11:10:39] [PASSED] drm_test_check_mode_valid_reject_rate
[11:10:39] [PASSED] drm_test_check_mode_valid_reject_max_clock
[11:10:39] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[11:10:39] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[11:10:39] [PASSED] drm_test_check_infoframes
[11:10:39] [PASSED] drm_test_check_reject_avi_infoframe
[11:10:39] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[11:10:39] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[11:10:39] [PASSED] drm_test_check_reject_audio_infoframe
[11:10:39] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[11:10:39] ================= drm_managed (2 subtests) =================
[11:10:39] [PASSED] drm_test_managed_release_action
[11:10:39] [PASSED] drm_test_managed_run_action
[11:10:39] =================== [PASSED] drm_managed ===================
[11:10:39] =================== drm_mm (6 subtests) ====================
[11:10:39] [PASSED] drm_test_mm_init
[11:10:39] [PASSED] drm_test_mm_debug
[11:10:39] [PASSED] drm_test_mm_align32
[11:10:39] [PASSED] drm_test_mm_align64
[11:10:39] [PASSED] drm_test_mm_lowest
[11:10:39] [PASSED] drm_test_mm_highest
[11:10:39] ===================== [PASSED] drm_mm ======================
[11:10:39] ============= drm_modes_analog_tv (5 subtests) =============
[11:10:39] [PASSED] drm_test_modes_analog_tv_mono_576i
[11:10:39] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[11:10:39] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[11:10:39] [PASSED] drm_test_modes_analog_tv_pal_576i
[11:10:39] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[11:10:39] =============== [PASSED] drm_modes_analog_tv ===============
[11:10:39] ============== drm_plane_helper (2 subtests) ===============
[11:10:39] =============== drm_test_check_plane_state ================
[11:10:39] [PASSED] clipping_simple
[11:10:39] [PASSED] clipping_rotate_reflect
[11:10:39] [PASSED] positioning_simple
[11:10:39] [PASSED] upscaling
[11:10:39] [PASSED] downscaling
[11:10:39] [PASSED] rounding1
[11:10:39] [PASSED] rounding2
[11:10:39] [PASSED] rounding3
[11:10:39] [PASSED] rounding4
[11:10:39] =========== [PASSED] drm_test_check_plane_state ============
[11:10:39] =========== drm_test_check_invalid_plane_state ============
[11:10:39] [PASSED] positioning_invalid
[11:10:39] [PASSED] upscaling_invalid
[11:10:39] [PASSED] downscaling_invalid
[11:10:39] ======= [PASSED] drm_test_check_invalid_plane_state ========
[11:10:39] ================ [PASSED] drm_plane_helper =================
[11:10:39] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[11:10:39] ====== drm_test_connector_helper_tv_get_modes_check =======
[11:10:39] [PASSED] None
[11:10:39] [PASSED] PAL
[11:10:39] [PASSED] NTSC
[11:10:39] [PASSED] Both, NTSC Default
[11:10:39] [PASSED] Both, PAL Default
[11:10:39] [PASSED] Both, NTSC Default, with PAL on command-line
[11:10:39] [PASSED] Both, PAL Default, with NTSC on command-line
[11:10:39] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[11:10:39] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[11:10:39] ================== drm_rect (9 subtests) ===================
[11:10:39] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[11:10:39] [PASSED] drm_test_rect_clip_scaled_not_clipped
[11:10:39] [PASSED] drm_test_rect_clip_scaled_clipped
[11:10:39] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[11:10:39] ================= drm_test_rect_intersect =================
[11:10:39] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[11:10:39] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[11:10:39] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[11:10:39] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[11:10:39] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[11:10:39] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[11:10:39] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[11:10:39] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[11:10:39] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[11:10:39] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[11:10:39] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[11:10:39] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[11:10:39] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[11:10:39] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[11:10:39] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[11:10:39] ============= [PASSED] drm_test_rect_intersect =============
[11:10:39] ================ drm_test_rect_calc_hscale ================
[11:10:39] [PASSED] normal use
[11:10:39] [PASSED] out of max range
[11:10:39] [PASSED] out of min range
[11:10:39] [PASSED] zero dst
[11:10:39] [PASSED] negative src
[11:10:39] [PASSED] negative dst
[11:10:39] ============ [PASSED] drm_test_rect_calc_hscale ============
[11:10:39] ================ drm_test_rect_calc_vscale ================
[11:10:39] [PASSED] normal use
[11:10:39] [PASSED] out of max range
[11:10:39] [PASSED] out of min range
[11:10:39] [PASSED] zero dst
[11:10:39] [PASSED] negative src
[11:10:39] [PASSED] negative dst
[11:10:39] ============ [PASSED] drm_test_rect_calc_vscale ============
[11:10:39] ================== drm_test_rect_rotate ===================
[11:10:39] [PASSED] reflect-x
[11:10:39] [PASSED] reflect-y
[11:10:39] [PASSED] rotate-0
[11:10:39] [PASSED] rotate-90
[11:10:39] [PASSED] rotate-180
[11:10:39] [PASSED] rotate-270
[11:10:39] ============== [PASSED] drm_test_rect_rotate ===============
[11:10:39] ================ drm_test_rect_rotate_inv =================
[11:10:39] [PASSED] reflect-x
[11:10:39] [PASSED] reflect-y
[11:10:39] [PASSED] rotate-0
[11:10:39] [PASSED] rotate-90
[11:10:39] [PASSED] rotate-180
[11:10:39] [PASSED] rotate-270
[11:10:39] ============ [PASSED] drm_test_rect_rotate_inv =============
[11:10:39] ==================== [PASSED] drm_rect =====================
[11:10:39] ============ drm_sysfb_modeset_test (1 subtest) ============
[11:10:39] ============ drm_test_sysfb_build_fourcc_list =============
[11:10:39] [PASSED] no native formats
[11:10:39] [PASSED] XRGB8888 as native format
[11:10:39] [PASSED] remove duplicates
[11:10:39] [PASSED] convert alpha formats
[11:10:39] [PASSED] random formats
[11:10:39] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[11:10:39] ============= [PASSED] drm_sysfb_modeset_test ==============
[11:10:39] ================== drm_fixp (2 subtests) ===================
[11:10:39] [PASSED] drm_test_int2fixp
[11:10:39] [PASSED] drm_test_sm2fixp
[11:10:39] ==================== [PASSED] drm_fixp =====================
[11:10:39] ============================================================
[11:10:39] Testing complete. Ran 621 tests: passed: 621
[11:10:39] Elapsed time: 25.808s total, 1.762s configuring, 23.830s building, 0.179s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[11:10:39] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[11:10:41] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[11:10:50] Starting KUnit Kernel (1/1)...
[11:10:50] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[11:10:50] ================= ttm_device (5 subtests) ==================
[11:10:50] [PASSED] ttm_device_init_basic
[11:10:50] [PASSED] ttm_device_init_multiple
[11:10:50] [PASSED] ttm_device_fini_basic
[11:10:50] [PASSED] ttm_device_init_no_vma_man
[11:10:50] ================== ttm_device_init_pools ==================
[11:10:50] [PASSED] No DMA allocations, no DMA32 required
[11:10:50] [PASSED] DMA allocations, DMA32 required
[11:10:50] [PASSED] No DMA allocations, DMA32 required
[11:10:50] [PASSED] DMA allocations, no DMA32 required
[11:10:50] ============== [PASSED] ttm_device_init_pools ==============
[11:10:50] =================== [PASSED] ttm_device ====================
[11:10:50] ================== ttm_pool (8 subtests) ===================
[11:10:50] ================== ttm_pool_alloc_basic ===================
[11:10:50] [PASSED] One page
[11:10:50] [PASSED] More than one page
[11:10:50] [PASSED] Above the allocation limit
[11:10:50] [PASSED] One page, with coherent DMA mappings enabled
[11:10:50] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[11:10:50] ============== [PASSED] ttm_pool_alloc_basic ===============
[11:10:50] ============== ttm_pool_alloc_basic_dma_addr ==============
[11:10:50] [PASSED] One page
[11:10:50] [PASSED] More than one page
[11:10:50] [PASSED] Above the allocation limit
[11:10:50] [PASSED] One page, with coherent DMA mappings enabled
[11:10:50] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[11:10:50] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[11:10:50] [PASSED] ttm_pool_alloc_order_caching_match
[11:10:50] [PASSED] ttm_pool_alloc_caching_mismatch
[11:10:50] [PASSED] ttm_pool_alloc_order_mismatch
[11:10:50] [PASSED] ttm_pool_free_dma_alloc
[11:10:50] [PASSED] ttm_pool_free_no_dma_alloc
[11:10:50] [PASSED] ttm_pool_fini_basic
[11:10:50] ==================== [PASSED] ttm_pool =====================
[11:10:50] ================ ttm_resource (8 subtests) =================
[11:10:50] ================= ttm_resource_init_basic =================
[11:10:50] [PASSED] Init resource in TTM_PL_SYSTEM
[11:10:50] [PASSED] Init resource in TTM_PL_VRAM
[11:10:50] [PASSED] Init resource in a private placement
[11:10:50] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[11:10:50] ============= [PASSED] ttm_resource_init_basic =============
[11:10:50] [PASSED] ttm_resource_init_pinned
[11:10:50] [PASSED] ttm_resource_fini_basic
[11:10:50] [PASSED] ttm_resource_manager_init_basic
[11:10:50] [PASSED] ttm_resource_manager_usage_basic
[11:10:50] [PASSED] ttm_resource_manager_set_used_basic
[11:10:50] [PASSED] ttm_sys_man_alloc_basic
[11:10:50] [PASSED] ttm_sys_man_free_basic
[11:10:50] ================== [PASSED] ttm_resource ===================
[11:10:50] =================== ttm_tt (15 subtests) ===================
[11:10:50] ==================== ttm_tt_init_basic ====================
[11:10:50] [PASSED] Page-aligned size
[11:10:50] [PASSED] Extra pages requested
[11:10:50] ================ [PASSED] ttm_tt_init_basic ================
[11:10:50] [PASSED] ttm_tt_init_misaligned
[11:10:50] [PASSED] ttm_tt_fini_basic
[11:10:50] [PASSED] ttm_tt_fini_sg
[11:10:50] [PASSED] ttm_tt_fini_shmem
[11:10:50] [PASSED] ttm_tt_create_basic
[11:10:50] [PASSED] ttm_tt_create_invalid_bo_type
[11:10:50] [PASSED] ttm_tt_create_ttm_exists
[11:10:50] [PASSED] ttm_tt_create_failed
[11:10:50] [PASSED] ttm_tt_destroy_basic
[11:10:50] [PASSED] ttm_tt_populate_null_ttm
[11:10:50] [PASSED] ttm_tt_populate_populated_ttm
[11:10:50] [PASSED] ttm_tt_unpopulate_basic
[11:10:50] [PASSED] ttm_tt_unpopulate_empty_ttm
[11:10:50] [PASSED] ttm_tt_swapin_basic
[11:10:50] ===================== [PASSED] ttm_tt ======================
[11:10:50] =================== ttm_bo (14 subtests) ===================
[11:10:50] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[11:10:50] [PASSED] Cannot be interrupted and sleeps
[11:10:50] [PASSED] Cannot be interrupted, locks straight away
[11:10:50] [PASSED] Can be interrupted, sleeps
[11:10:50] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[11:10:50] [PASSED] ttm_bo_reserve_locked_no_sleep
[11:10:50] [PASSED] ttm_bo_reserve_no_wait_ticket
[11:10:50] [PASSED] ttm_bo_reserve_double_resv
[11:10:50] [PASSED] ttm_bo_reserve_interrupted
[11:10:50] [PASSED] ttm_bo_reserve_deadlock
[11:10:50] [PASSED] ttm_bo_unreserve_basic
[11:10:50] [PASSED] ttm_bo_unreserve_pinned
[11:10:50] [PASSED] ttm_bo_unreserve_bulk
[11:10:50] [PASSED] ttm_bo_fini_basic
[11:10:50] [PASSED] ttm_bo_fini_shared_resv
[11:10:50] [PASSED] ttm_bo_pin_basic
[11:10:50] [PASSED] ttm_bo_pin_unpin_resource
[11:10:50] [PASSED] ttm_bo_multiple_pin_one_unpin
[11:10:50] ===================== [PASSED] ttm_bo ======================
[11:10:50] ============== ttm_bo_validate (22 subtests) ===============
[11:10:50] ============== ttm_bo_init_reserved_sys_man ===============
[11:10:50] [PASSED] Buffer object for userspace
[11:10:50] [PASSED] Kernel buffer object
[11:10:50] [PASSED] Shared buffer object
[11:10:50] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[11:10:50] ============== ttm_bo_init_reserved_mock_man ==============
[11:10:50] [PASSED] Buffer object for userspace
[11:10:50] [PASSED] Kernel buffer object
[11:10:50] [PASSED] Shared buffer object
[11:10:50] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[11:10:50] [PASSED] ttm_bo_init_reserved_resv
[11:10:50] ================== ttm_bo_validate_basic ==================
[11:10:50] [PASSED] Buffer object for userspace
[11:10:50] [PASSED] Kernel buffer object
[11:10:50] [PASSED] Shared buffer object
[11:10:50] ============== [PASSED] ttm_bo_validate_basic ==============
[11:10:50] [PASSED] ttm_bo_validate_invalid_placement
[11:10:50] ============= ttm_bo_validate_same_placement ==============
[11:10:50] [PASSED] System manager
[11:10:50] [PASSED] VRAM manager
[11:10:50] ========= [PASSED] ttm_bo_validate_same_placement ==========
[11:10:50] [PASSED] ttm_bo_validate_failed_alloc
[11:10:50] [PASSED] ttm_bo_validate_pinned
[11:10:50] [PASSED] ttm_bo_validate_busy_placement
[11:10:50] ================ ttm_bo_validate_multihop =================
[11:10:50] [PASSED] Buffer object for userspace
[11:10:50] [PASSED] Kernel buffer object
[11:10:50] [PASSED] Shared buffer object
[11:10:50] ============ [PASSED] ttm_bo_validate_multihop =============
[11:10:50] ========== ttm_bo_validate_no_placement_signaled ==========
[11:10:50] [PASSED] Buffer object in system domain, no page vector
[11:10:50] [PASSED] Buffer object in system domain with an existing page vector
[11:10:50] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[11:10:50] ======== ttm_bo_validate_no_placement_not_signaled ========
[11:10:50] [PASSED] Buffer object for userspace
[11:10:50] [PASSED] Kernel buffer object
[11:10:50] [PASSED] Shared buffer object
[11:10:50] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[11:10:50] [PASSED] ttm_bo_validate_move_fence_signaled
[11:10:50] ========= ttm_bo_validate_move_fence_not_signaled =========
[11:10:50] [PASSED] Waits for GPU
[11:10:50] [PASSED] Tries to lock straight away
[11:10:50] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[11:10:50] [PASSED] ttm_bo_validate_swapout
[11:10:50] [PASSED] ttm_bo_validate_happy_evict
[11:10:50] [PASSED] ttm_bo_validate_all_pinned_evict
[11:10:50] [PASSED] ttm_bo_validate_allowed_only_evict
[11:10:50] [PASSED] ttm_bo_validate_deleted_evict
[11:10:50] [PASSED] ttm_bo_validate_busy_domain_evict
[11:10:50] [PASSED] ttm_bo_validate_evict_gutting
[11:10:50] [PASSED] ttm_bo_validate_recrusive_evict
[11:10:50] ================= [PASSED] ttm_bo_validate =================
[11:10:50] ============================================================
[11:10:50] Testing complete. Ran 102 tests: passed: 102
[11:10:50] Elapsed time: 11.620s total, 1.726s configuring, 9.629s building, 0.227s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 32+ messages in thread* ✓ Xe.CI.BAT: success for Intel Xe GPU Debug Support (eudebug) v8
2026-04-30 10:50 [PATCH 00/24] Intel Xe GPU Debug Support (eudebug) v8 Mika Kuoppala
` (25 preceding siblings ...)
2026-04-30 11:10 ` ✓ CI.KUnit: success " Patchwork
@ 2026-04-30 12:06 ` Patchwork
2026-04-30 22:41 ` ✗ Xe.CI.FULL: failure " Patchwork
27 siblings, 0 replies; 32+ messages in thread
From: Patchwork @ 2026-04-30 12:06 UTC (permalink / raw)
To: Mika Kuoppala; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 953 bytes --]
== Series Details ==
Series: Intel Xe GPU Debug Support (eudebug) v8
URL : https://patchwork.freedesktop.org/series/165777/
State : success
== Summary ==
CI Bug Log - changes from xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d_BAT -> xe-pw-165777v1_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (13 -> 13)
------------------------------
No changes in participating hosts
Changes
-------
No changes found
Build changes
-------------
* Linux: xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d -> xe-pw-165777v1
IGT_8879: 02b0e01dd9a5a3ab1efe976bb8c4f13cfcdbab1a @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d: 3ac514cf64f272cc4d5143f4cc28fb18a8aba76d
xe-pw-165777v1: 165777v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/index.html
[-- Attachment #2: Type: text/html, Size: 1501 bytes --]
^ permalink raw reply [flat|nested] 32+ messages in thread* ✗ Xe.CI.FULL: failure for Intel Xe GPU Debug Support (eudebug) v8
2026-04-30 10:50 [PATCH 00/24] Intel Xe GPU Debug Support (eudebug) v8 Mika Kuoppala
` (26 preceding siblings ...)
2026-04-30 12:06 ` ✓ Xe.CI.BAT: " Patchwork
@ 2026-04-30 22:41 ` Patchwork
27 siblings, 0 replies; 32+ messages in thread
From: Patchwork @ 2026-04-30 22:41 UTC (permalink / raw)
To: Mika Kuoppala; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 63655 bytes --]
== Series Details ==
Series: Intel Xe GPU Debug Support (eudebug) v8
URL : https://patchwork.freedesktop.org/series/165777/
State : failure
== Summary ==
CI Bug Log - changes from xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d_FULL -> xe-pw-165777v1_FULL
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with xe-pw-165777v1_FULL absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-165777v1_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (2 -> 2)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in xe-pw-165777v1_FULL:
### IGT changes ###
#### Possible regressions ####
* igt@xe_eudebug_online@interrupt-all@drm_xe_engine_class_compute0:
- shard-bmg: NOTRUN -> [FAIL][1] +39 other tests fail
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-bmg-9/igt@xe_eudebug_online@interrupt-all@drm_xe_engine_class_compute0.html
* igt@xe_exec_reset@cm-multi-queue-cat-error-on-secondary:
- shard-bmg: NOTRUN -> [SKIP][2]
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-bmg-9/igt@xe_exec_reset@cm-multi-queue-cat-error-on-secondary.html
* igt@xe_exec_system_allocator@threads-shared-vm-many-malloc-race:
- shard-bmg: [PASS][3] -> [FAIL][4] +1822 other tests fail
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-bmg-7/igt@xe_exec_system_allocator@threads-shared-vm-many-malloc-race.html
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-bmg-1/igt@xe_exec_system_allocator@threads-shared-vm-many-malloc-race.html
* igt@xe_exec_system_allocator@threads-shared-vm-many-mmap-remap-dontunmap-eocheck:
- shard-lnl: NOTRUN -> [FAIL][5] +156 other tests fail
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-8/igt@xe_exec_system_allocator@threads-shared-vm-many-mmap-remap-dontunmap-eocheck.html
* igt@xe_exec_system_allocator@twice-new-prefetch:
- shard-lnl: [PASS][6] -> [FAIL][7] +1611 other tests fail
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-lnl-2/igt@xe_exec_system_allocator@twice-new-prefetch.html
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-5/igt@xe_exec_system_allocator@twice-new-prefetch.html
* igt@xe_vm@overcommit-nonfault-vram-lr-defer:
- shard-lnl: NOTRUN -> [SKIP][8]
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-8/igt@xe_vm@overcommit-nonfault-vram-lr-defer.html
#### Warnings ####
* igt@xe_eudebug@basic-vm-bind-metadata-discovery:
- shard-bmg: [SKIP][9] ([Intel XE#7636]) -> [FAIL][10] +7 other tests fail
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-bmg-10/igt@xe_eudebug@basic-vm-bind-metadata-discovery.html
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-bmg-5/igt@xe_eudebug@basic-vm-bind-metadata-discovery.html
* igt@xe_eudebug_online@interrupt-all-set-breakpoint:
- shard-lnl: [SKIP][11] ([Intel XE#7636]) -> [FAIL][12] +8 other tests fail
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-lnl-3/igt@xe_eudebug_online@interrupt-all-set-breakpoint.html
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-1/igt@xe_eudebug_online@interrupt-all-set-breakpoint.html
* igt@xe_eudebug_sriov@deny-eudebug:
- shard-bmg: [SKIP][13] ([Intel XE#5793] / [Intel XE#7320] / [Intel XE#7464]) -> [FAIL][14]
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-bmg-7/igt@xe_eudebug_sriov@deny-eudebug.html
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-bmg-1/igt@xe_eudebug_sriov@deny-eudebug.html
* igt@xe_exec_system_allocator@many-stride-new-prefetch:
- shard-bmg: [INCOMPLETE][15] ([Intel XE#7098]) -> [FAIL][16]
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-bmg-2/igt@xe_exec_system_allocator@many-stride-new-prefetch.html
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-bmg-1/igt@xe_exec_system_allocator@many-stride-new-prefetch.html
Known issues
------------
Here are the changes found in xe-pw-165777v1_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@intel_hwmon@hwmon-read:
- shard-lnl: NOTRUN -> [SKIP][17] ([Intel XE#1125] / [Intel XE#7312])
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-2/igt@intel_hwmon@hwmon-read.html
* igt@kms_big_fb@4-tiled-16bpp-rotate-270:
- shard-lnl: NOTRUN -> [SKIP][18] ([Intel XE#1407]) +2 other tests skip
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-2/igt@kms_big_fb@4-tiled-16bpp-rotate-270.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
- shard-lnl: NOTRUN -> [SKIP][19] ([Intel XE#3658] / [Intel XE#7360])
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-2/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- shard-bmg: NOTRUN -> [SKIP][20] ([Intel XE#1124]) +2 other tests skip
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-bmg-9/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- shard-lnl: NOTRUN -> [SKIP][21] ([Intel XE#1124]) +4 other tests skip
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-8/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_bw@linear-tiling-3-displays-target-2560x1440p:
- shard-lnl: NOTRUN -> [SKIP][22] ([Intel XE#367])
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-8/igt@kms_bw@linear-tiling-3-displays-target-2560x1440p.html
* igt@kms_bw@linear-tiling-4-displays-target-2160x1440p:
- shard-lnl: NOTRUN -> [SKIP][23] ([Intel XE#7676])
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-2/igt@kms_bw@linear-tiling-4-displays-target-2160x1440p.html
* igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs@pipe-a-edp-1:
- shard-lnl: NOTRUN -> [SKIP][24] ([Intel XE#2669] / [Intel XE#7389]) +3 other tests skip
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-8/igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs@pipe-a-edp-1.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-mc-ccs:
- shard-lnl: NOTRUN -> [SKIP][25] ([Intel XE#2887]) +5 other tests skip
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-2/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-mc-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs-cc:
- shard-bmg: NOTRUN -> [SKIP][26] ([Intel XE#2887])
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-bmg-9/igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs-cc.html
* igt@kms_chamelium_audio@dp-audio-edid:
- shard-lnl: NOTRUN -> [SKIP][27] ([Intel XE#373]) +2 other tests skip
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-2/igt@kms_chamelium_audio@dp-audio-edid.html
* igt@kms_chamelium_color@ctm-negative:
- shard-lnl: NOTRUN -> [SKIP][28] ([Intel XE#306] / [Intel XE#7358]) +1 other test skip
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-8/igt@kms_chamelium_color@ctm-negative.html
* igt@kms_chamelium_frames@hdmi-aspect-ratio:
- shard-bmg: NOTRUN -> [SKIP][29] ([Intel XE#2252])
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-bmg-9/igt@kms_chamelium_frames@hdmi-aspect-ratio.html
* igt@kms_content_protection@lic-type-0:
- shard-lnl: NOTRUN -> [SKIP][30] ([Intel XE#7642]) +1 other test skip
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-2/igt@kms_content_protection@lic-type-0.html
* igt@kms_content_protection@lic-type-0-hdcp14@pipe-a-dp-2:
- shard-bmg: NOTRUN -> [FAIL][31] ([Intel XE#1178] / [Intel XE#3304] / [Intel XE#7374]) +1 other test fail
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-bmg-9/igt@kms_content_protection@lic-type-0-hdcp14@pipe-a-dp-2.html
* igt@kms_cursor_crc@cursor-rapid-movement-512x512:
- shard-bmg: NOTRUN -> [SKIP][32] ([Intel XE#2321] / [Intel XE#7355])
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-bmg-1/igt@kms_cursor_crc@cursor-rapid-movement-512x512.html
* igt@kms_cursor_crc@cursor-rapid-movement-max-size:
- shard-lnl: NOTRUN -> [SKIP][33] ([Intel XE#1424]) +4 other tests skip
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-2/igt@kms_cursor_crc@cursor-rapid-movement-max-size.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
- shard-lnl: NOTRUN -> [SKIP][34] ([Intel XE#309] / [Intel XE#7343]) +2 other tests skip
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-2/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
* igt@kms_dsc@dsc-basic:
- shard-lnl: NOTRUN -> [SKIP][35] ([Intel XE#2244])
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-8/igt@kms_dsc@dsc-basic.html
* igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-dirtyfb-tests:
- shard-lnl: NOTRUN -> [SKIP][36] ([Intel XE#4422] / [Intel XE#7442])
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-2/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-dirtyfb-tests.html
* igt@kms_flip@2x-flip-vs-rmfb:
- shard-lnl: NOTRUN -> [SKIP][37] ([Intel XE#1421]) +2 other tests skip
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-2/igt@kms_flip@2x-flip-vs-rmfb.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling:
- shard-lnl: NOTRUN -> [SKIP][38] ([Intel XE#7178] / [Intel XE#7349])
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-8/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling:
- shard-lnl: NOTRUN -> [SKIP][39] ([Intel XE#1397] / [Intel XE#1745] / [Intel XE#7385]) +1 other test skip
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-8/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling@pipe-a-default-mode:
- shard-lnl: NOTRUN -> [SKIP][40] ([Intel XE#1397] / [Intel XE#7385]) +1 other test skip
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-8/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling:
- shard-lnl: NOTRUN -> [SKIP][41] ([Intel XE#7178] / [Intel XE#7351]) +1 other test skip
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-8/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling.html
* igt@kms_flip_scaled_crc@flip-p016-linear-to-p016-linear-reflect-x:
- shard-lnl: NOTRUN -> [SKIP][42] ([Intel XE#7179])
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-2/igt@kms_flip_scaled_crc@flip-p016-linear-to-p016-linear-reflect-x.html
* igt@kms_frontbuffer_tracking@fbcdrrs-1p-offscreen-pri-shrfb-draw-mmap-wc:
- shard-lnl: NOTRUN -> [SKIP][43] ([Intel XE#6312])
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-8/igt@kms_frontbuffer_tracking@fbcdrrs-1p-offscreen-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-shrfb-plflip-blt:
- shard-lnl: NOTRUN -> [SKIP][44] ([Intel XE#6312] / [Intel XE#651]) +2 other tests skip
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-2/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-shrfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-draw-render:
- shard-bmg: NOTRUN -> [SKIP][45] ([Intel XE#2311])
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-bmg-9/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-indfb-draw-render:
- shard-lnl: NOTRUN -> [SKIP][46] ([Intel XE#5812] / [Intel XE#656]) +17 other tests skip
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-8/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcdrrs-tiling-y:
- shard-lnl: NOTRUN -> [SKIP][47] ([Intel XE#1469] / [Intel XE#7399])
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-8/igt@kms_frontbuffer_tracking@fbcdrrs-tiling-y.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw:
- shard-bmg: NOTRUN -> [SKIP][48] ([Intel XE#2313])
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-bmg-9/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html
* igt@kms_frontbuffer_tracking@fbcpsr-abgr161616f-draw-blt:
- shard-lnl: NOTRUN -> [SKIP][49] ([Intel XE#7061] / [Intel XE#7356]) +2 other tests skip
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-2/igt@kms_frontbuffer_tracking@fbcpsr-abgr161616f-draw-blt.html
* igt@kms_hdmi_inject@inject-4k:
- shard-lnl: NOTRUN -> [SKIP][50] ([Intel XE#1470])
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-8/igt@kms_hdmi_inject@inject-4k.html
* igt@kms_hdr@invalid-hdr:
- shard-bmg: [PASS][51] -> [SKIP][52] ([Intel XE#1503])
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-bmg-8/igt@kms_hdr@invalid-hdr.html
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-bmg-10/igt@kms_hdr@invalid-hdr.html
* igt@kms_joiner@basic-force-ultra-joiner:
- shard-bmg: NOTRUN -> [SKIP][53] ([Intel XE#6911] / [Intel XE#7466])
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-bmg-9/igt@kms_joiner@basic-force-ultra-joiner.html
* igt@kms_joiner@invalid-modeset-force-ultra-joiner:
- shard-lnl: NOTRUN -> [SKIP][54] ([Intel XE#6900] / [Intel XE#7362])
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-8/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html
* igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-cc-modifier:
- shard-bmg: NOTRUN -> [SKIP][55] ([Intel XE#7283])
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-bmg-9/igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-cc-modifier.html
* igt@kms_plane@pixel-format-4-tiled-lnl-ccs-modifier@pipe-a-plane-5:
- shard-lnl: NOTRUN -> [SKIP][56] ([Intel XE#7130]) +1 other test skip
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-2/igt@kms_plane@pixel-format-4-tiled-lnl-ccs-modifier@pipe-a-plane-5.html
* igt@kms_plane@pixel-format-yf-tiled-modifier:
- shard-lnl: NOTRUN -> [SKIP][57] ([Intel XE#7283]) +1 other test skip
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-2/igt@kms_plane@pixel-format-yf-tiled-modifier.html
* igt@kms_plane_lowres@tiling-yf:
- shard-lnl: NOTRUN -> [SKIP][58] ([Intel XE#599])
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-2/igt@kms_plane_lowres@tiling-yf.html
* igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-a:
- shard-lnl: NOTRUN -> [SKIP][59] ([Intel XE#2763] / [Intel XE#6886]) +3 other tests skip
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-2/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-a.html
* igt@kms_pm_backlight@fade:
- shard-bmg: NOTRUN -> [SKIP][60] ([Intel XE#7376] / [Intel XE#870])
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-bmg-1/igt@kms_pm_backlight@fade.html
* igt@kms_pm_rpm@package-g7:
- shard-lnl: NOTRUN -> [SKIP][61] ([Intel XE#6813])
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-8/igt@kms_pm_rpm@package-g7.html
* igt@kms_psr2_sf@fbc-pr-overlay-primary-update-sf-dmg-area:
- shard-bmg: NOTRUN -> [SKIP][62] ([Intel XE#1489]) +1 other test skip
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-bmg-9/igt@kms_psr2_sf@fbc-pr-overlay-primary-update-sf-dmg-area.html
* igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf@pipe-a-edp-1:
- shard-lnl: NOTRUN -> [SKIP][63] ([Intel XE#4608]) +1 other test skip
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-2/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf@pipe-a-edp-1.html
* igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-continuous-sf:
- shard-lnl: NOTRUN -> [SKIP][64] ([Intel XE#2893] / [Intel XE#4608] / [Intel XE#7304]) +1 other test skip
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-8/igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-continuous-sf.html
* igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-continuous-sf@pipe-b-edp-1:
- shard-lnl: NOTRUN -> [SKIP][65] ([Intel XE#4608] / [Intel XE#7304]) +1 other test skip
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-8/igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-continuous-sf@pipe-b-edp-1.html
* igt@kms_psr@fbc-pr-dpms:
- shard-lnl: NOTRUN -> [SKIP][66] ([Intel XE#1406]) +1 other test skip
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-8/igt@kms_psr@fbc-pr-dpms.html
* igt@kms_psr@fbc-psr2-primary-blt:
- shard-lnl: NOTRUN -> [SKIP][67] ([Intel XE#1406] / [Intel XE#7345]) +1 other test skip
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-8/igt@kms_psr@fbc-psr2-primary-blt.html
* igt@kms_psr@fbc-psr2-primary-blt@edp-1:
- shard-lnl: NOTRUN -> [SKIP][68] ([Intel XE#1406] / [Intel XE#4609]) +1 other test skip
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-8/igt@kms_psr@fbc-psr2-primary-blt@edp-1.html
* igt@kms_tv_load_detect@load-detect:
- shard-lnl: NOTRUN -> [SKIP][69] ([Intel XE#330] / [Intel XE#5857])
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-2/igt@kms_tv_load_detect@load-detect.html
* igt@xe_eudebug@basic-connect:
- shard-lnl: NOTRUN -> [FAIL][70] ([Intel XE#7717])
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-8/igt@xe_eudebug@basic-connect.html
* igt@xe_eudebug@basic-vm-bind-discovery:
- shard-bmg: NOTRUN -> [FAIL][71] ([Intel XE#7709])
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-bmg-1/igt@xe_eudebug@basic-vm-bind-discovery.html
* igt@xe_eudebug@connect-user:
- shard-lnl: NOTRUN -> [FAIL][72] ([Intel XE#7708])
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-2/igt@xe_eudebug@connect-user.html
* igt@xe_eudebug@discovery-empty-clients:
- shard-lnl: NOTRUN -> [FAIL][73] ([Intel XE#7718])
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-2/igt@xe_eudebug@discovery-empty-clients.html
* igt@xe_eudebug_online@pagefault-read-stress@drm_xe_engine_class_render0:
- shard-lnl: NOTRUN -> [FAIL][74] ([Intel XE#7707]) +20 other tests fail
[74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-5/igt@xe_eudebug_online@pagefault-read-stress@drm_xe_engine_class_render0.html
* igt@xe_eudebug_online@stopped-thread@drm_xe_engine_class_compute0:
- shard-bmg: NOTRUN -> [FAIL][75] ([Intel XE#7707]) +25 other tests fail
[75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-bmg-6/igt@xe_eudebug_online@stopped-thread@drm_xe_engine_class_compute0.html
* igt@xe_eudebug_online@writes-caching-sram-bb-vram-target-vram@drm_xe_engine_class_compute0:
- shard-lnl: NOTRUN -> [SKIP][76] ([Intel XE#2825]) +1 other test skip
[76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-5/igt@xe_eudebug_online@writes-caching-sram-bb-vram-target-vram@drm_xe_engine_class_compute0.html
* igt@xe_eudebug_online@writes-caching-vram-bb-vram-target-sram@drm_xe_engine_class_compute0:
- shard-lnl: NOTRUN -> [SKIP][77] ([Intel XE#2825] / [Intel XE#7430]) +3 other tests skip
[77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-5/igt@xe_eudebug_online@writes-caching-vram-bb-vram-target-sram@drm_xe_engine_class_compute0.html
* igt@xe_evict_ccs@evict-overcommit-parallel-nofree-samefd:
- shard-lnl: NOTRUN -> [SKIP][78] ([Intel XE#6540] / [Intel XE#688]) +4 other tests skip
[78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-8/igt@xe_evict_ccs@evict-overcommit-parallel-nofree-samefd.html
* igt@xe_exec_balancer@once-parallel-userptr-rebind:
- shard-lnl: NOTRUN -> [SKIP][79] ([Intel XE#7482]) +9 other tests skip
[79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-2/igt@xe_exec_balancer@once-parallel-userptr-rebind.html
* igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-rebind:
- shard-lnl: NOTRUN -> [SKIP][80] ([Intel XE#1392]) +2 other tests skip
[80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-2/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-rebind.html
* igt@xe_exec_basic@multigpu-no-exec-userptr-invalidate:
- shard-bmg: NOTRUN -> [SKIP][81] ([Intel XE#2322] / [Intel XE#7372])
[81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-bmg-9/igt@xe_exec_basic@multigpu-no-exec-userptr-invalidate.html
* igt@xe_exec_fault_mode@once-multi-queue-invalid-fault:
- shard-lnl: NOTRUN -> [SKIP][82] ([Intel XE#7136]) +8 other tests skip
[82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-8/igt@xe_exec_fault_mode@once-multi-queue-invalid-fault.html
* igt@xe_exec_fault_mode@twice-multi-queue-userptr-rebind-prefetch:
- shard-bmg: NOTRUN -> [SKIP][83] ([Intel XE#7136]) +3 other tests skip
[83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-bmg-9/igt@xe_exec_fault_mode@twice-multi-queue-userptr-rebind-prefetch.html
* igt@xe_exec_multi_queue@many-queues-preempt-mode-userptr:
- shard-lnl: NOTRUN -> [SKIP][84] ([Intel XE#6874]) +13 other tests skip
[84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-2/igt@xe_exec_multi_queue@many-queues-preempt-mode-userptr.html
* igt@xe_exec_multi_queue@two-queues-priority:
- shard-bmg: NOTRUN -> [SKIP][85] ([Intel XE#6874]) +2 other tests skip
[85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-bmg-1/igt@xe_exec_multi_queue@two-queues-priority.html
* igt@xe_exec_sip_eudebug@breakpoint-waitsip-heavy@drm_xe_engine_class_render0:
- shard-lnl: NOTRUN -> [FAIL][86] ([Intel XE#7715]) +7 other tests fail
[86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-4/igt@xe_exec_sip_eudebug@breakpoint-waitsip-heavy@drm_xe_engine_class_render0.html
* igt@xe_exec_sip_eudebug@breakpoint-writesip@drm_xe_engine_class_compute0:
- shard-bmg: NOTRUN -> [FAIL][87] ([Intel XE#7715]) +7 other tests fail
[87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-bmg-9/igt@xe_exec_sip_eudebug@breakpoint-writesip@drm_xe_engine_class_compute0.html
* igt@xe_exec_threads@threads-multi-queue-cm-shared-vm-userptr-invalidate:
- shard-bmg: NOTRUN -> [SKIP][88] ([Intel XE#7138]) +1 other test skip
[88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-bmg-9/igt@xe_exec_threads@threads-multi-queue-cm-shared-vm-userptr-invalidate.html
* igt@xe_exec_threads@threads-multi-queue-cm-shared-vm-userptr-rebind:
- shard-lnl: NOTRUN -> [SKIP][89] ([Intel XE#7138]) +4 other tests skip
[89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-2/igt@xe_exec_threads@threads-multi-queue-cm-shared-vm-userptr-rebind.html
* igt@xe_mmap@pci-membarrier:
- shard-lnl: NOTRUN -> [SKIP][90] ([Intel XE#5100] / [Intel XE#7322] / [Intel XE#7408])
[90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-8/igt@xe_mmap@pci-membarrier.html
* igt@xe_module_load@load:
- shard-lnl: ([PASS][91], [PASS][92], [PASS][93], [PASS][94], [PASS][95], [PASS][96], [PASS][97], [PASS][98], [PASS][99], [PASS][100], [PASS][101], [PASS][102], [PASS][103], [PASS][104], [PASS][105], [PASS][106], [PASS][107], [PASS][108], [PASS][109], [PASS][110], [PASS][111], [PASS][112], [PASS][113], [PASS][114]) -> ([PASS][115], [SKIP][116], [PASS][117], [PASS][118], [PASS][119], [PASS][120], [PASS][121], [PASS][122], [PASS][123], [PASS][124], [PASS][125], [PASS][126], [PASS][127], [PASS][128], [PASS][129], [PASS][130], [PASS][131], [PASS][132], [PASS][133], [PASS][134], [PASS][135], [PASS][136], [PASS][137], [PASS][138], [PASS][139]) ([Intel XE#378] / [Intel XE#7405])
[91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-lnl-4/igt@xe_module_load@load.html
[92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-lnl-5/igt@xe_module_load@load.html
[93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-lnl-3/igt@xe_module_load@load.html
[94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-lnl-3/igt@xe_module_load@load.html
[95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-lnl-3/igt@xe_module_load@load.html
[96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-lnl-3/igt@xe_module_load@load.html
[97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-lnl-5/igt@xe_module_load@load.html
[98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-lnl-2/igt@xe_module_load@load.html
[99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-lnl-2/igt@xe_module_load@load.html
[100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-lnl-8/igt@xe_module_load@load.html
[101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-lnl-1/igt@xe_module_load@load.html
[102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-lnl-1/igt@xe_module_load@load.html
[103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-lnl-8/igt@xe_module_load@load.html
[104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-lnl-8/igt@xe_module_load@load.html
[105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-lnl-2/igt@xe_module_load@load.html
[106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-lnl-7/igt@xe_module_load@load.html
[107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-lnl-8/igt@xe_module_load@load.html
[108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-lnl-5/igt@xe_module_load@load.html
[109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-lnl-1/igt@xe_module_load@load.html
[110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-lnl-6/igt@xe_module_load@load.html
[111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-lnl-7/igt@xe_module_load@load.html
[112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-lnl-4/igt@xe_module_load@load.html
[113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-lnl-7/igt@xe_module_load@load.html
[114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-lnl-4/igt@xe_module_load@load.html
[115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-7/igt@xe_module_load@load.html
[116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-8/igt@xe_module_load@load.html
[117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-8/igt@xe_module_load@load.html
[118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-8/igt@xe_module_load@load.html
[119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-2/igt@xe_module_load@load.html
[120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-7/igt@xe_module_load@load.html
[121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-7/igt@xe_module_load@load.html
[122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-5/igt@xe_module_load@load.html
[123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-2/igt@xe_module_load@load.html
[124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-4/igt@xe_module_load@load.html
[125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-4/igt@xe_module_load@load.html
[126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-2/igt@xe_module_load@load.html
[127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-2/igt@xe_module_load@load.html
[128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-5/igt@xe_module_load@load.html
[129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-5/igt@xe_module_load@load.html
[130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-5/igt@xe_module_load@load.html
[131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-8/igt@xe_module_load@load.html
[132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-3/igt@xe_module_load@load.html
[133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-3/igt@xe_module_load@load.html
[134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-3/igt@xe_module_load@load.html
[135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-1/igt@xe_module_load@load.html
[136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-1/igt@xe_module_load@load.html
[137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-1/igt@xe_module_load@load.html
[138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-1/igt@xe_module_load@load.html
[139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-4/igt@xe_module_load@load.html
* igt@xe_multigpu_svm@mgpu-migration-basic:
- shard-lnl: NOTRUN -> [SKIP][140] ([Intel XE#6964]) +1 other test skip
[140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-2/igt@xe_multigpu_svm@mgpu-migration-basic.html
* igt@xe_page_reclaim@binds-null-vma:
- shard-lnl: NOTRUN -> [SKIP][141] ([Intel XE#7793]) +1 other test skip
[141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-8/igt@xe_page_reclaim@binds-null-vma.html
* igt@xe_pat@pat-index-xehpc:
- shard-lnl: NOTRUN -> [SKIP][142] ([Intel XE#1420] / [Intel XE#2838] / [Intel XE#7590])
[142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-2/igt@xe_pat@pat-index-xehpc.html
* igt@xe_pat@pat-index-xelp:
- shard-lnl: NOTRUN -> [SKIP][143] ([Intel XE#7590] / [Intel XE#977])
[143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-8/igt@xe_pat@pat-index-xelp.html
* igt@xe_pm@d3cold-mocs:
- shard-lnl: NOTRUN -> [SKIP][144] ([Intel XE#2284] / [Intel XE#7370])
[144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-8/igt@xe_pm@d3cold-mocs.html
* igt@xe_pm@s3-vm-bind-prefetch:
- shard-lnl: NOTRUN -> [SKIP][145] ([Intel XE#584] / [Intel XE#7369])
[145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-8/igt@xe_pm@s3-vm-bind-prefetch.html
* igt@xe_query@multigpu-query-topology:
- shard-lnl: NOTRUN -> [SKIP][146] ([Intel XE#944])
[146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-2/igt@xe_query@multigpu-query-topology.html
* igt@xe_sriov_admin@bulk-exec-quantum-vfs-disabled:
- shard-lnl: NOTRUN -> [SKIP][147] ([Intel XE#7174])
[147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-2/igt@xe_sriov_admin@bulk-exec-quantum-vfs-disabled.html
* igt@xe_sriov_scheduling@equal-throughput:
- shard-lnl: NOTRUN -> [SKIP][148] ([Intel XE#4351] / [Intel XE#7357])
[148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-8/igt@xe_sriov_scheduling@equal-throughput.html
* igt@xe_sriov_vram@vf-access-after-resize-down:
- shard-lnl: NOTRUN -> [SKIP][149] ([Intel XE#6376] / [Intel XE#7330] / [Intel XE#7422])
[149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-2/igt@xe_sriov_vram@vf-access-after-resize-down.html
* igt@xe_survivability@runtime-survivability:
- shard-bmg: [PASS][150] -> [DMESG-WARN][151] ([Intel XE#6627] / [Intel XE#7419])
[150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-bmg-6/igt@xe_survivability@runtime-survivability.html
[151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-bmg-8/igt@xe_survivability@runtime-survivability.html
* igt@xe_vm@out-of-memory:
- shard-lnl: NOTRUN -> [SKIP][152] ([Intel XE#5745])
[152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-2/igt@xe_vm@out-of-memory.html
#### Possible fixes ####
* igt@kms_cursor_legacy@flip-vs-cursor-atomic:
- shard-bmg: [FAIL][153] ([Intel XE#7571]) -> [PASS][154]
[153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-bmg-9/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
[154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-bmg-9/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bd-dp2-hdmi-a3:
- shard-bmg: [FAIL][155] ([Intel XE#3321]) -> [PASS][156] +1 other test pass
[155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-bmg-5/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bd-dp2-hdmi-a3.html
[156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-bmg-4/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bd-dp2-hdmi-a3.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
- shard-lnl: [FAIL][157] ([Intel XE#301]) -> [PASS][158] +1 other test pass
[157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
[158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
* igt@kms_vrr@max-min@pipe-a-edp-1:
- shard-lnl: [FAIL][159] ([Intel XE#4227]) -> [PASS][160] +1 other test pass
[159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-lnl-4/igt@kms_vrr@max-min@pipe-a-edp-1.html
[160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-8/igt@kms_vrr@max-min@pipe-a-edp-1.html
* igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1:
- shard-lnl: [FAIL][161] ([Intel XE#2142]) -> [PASS][162] +1 other test pass
[161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-lnl-8/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html
[162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-5/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html
* igt@xe_eudebug@basic-exec-queues-enable:
- shard-bmg: [SKIP][163] ([Intel XE#7636]) -> [PASS][164] +2 other tests pass
[163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-bmg-4/igt@xe_eudebug@basic-exec-queues-enable.html
[164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-bmg-8/igt@xe_eudebug@basic-exec-queues-enable.html
* igt@xe_eudebug_sriov@deny-sriov:
- shard-bmg: [SKIP][165] ([Intel XE#5793] / [Intel XE#7320] / [Intel XE#7464]) -> [PASS][166]
[165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-bmg-5/igt@xe_eudebug_sriov@deny-sriov.html
[166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-bmg-4/igt@xe_eudebug_sriov@deny-sriov.html
* igt@xe_evict@evict-beng-large-multi-vm-cm:
- shard-bmg: [INCOMPLETE][167] -> [PASS][168]
[167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-bmg-7/igt@xe_evict@evict-beng-large-multi-vm-cm.html
[168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-bmg-1/igt@xe_evict@evict-beng-large-multi-vm-cm.html
* igt@xe_evict@evict-beng-mixed-many-threads-small:
- shard-bmg: [INCOMPLETE][169] ([Intel XE#6321]) -> [PASS][170]
[169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-bmg-9/igt@xe_evict@evict-beng-mixed-many-threads-small.html
[170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-bmg-9/igt@xe_evict@evict-beng-mixed-many-threads-small.html
* igt@xe_exec_sip_eudebug@wait-writesip-nodebug:
- shard-lnl: [SKIP][171] ([Intel XE#7636]) -> [PASS][172] +2 other tests pass
[171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-lnl-3/igt@xe_exec_sip_eudebug@wait-writesip-nodebug.html
[172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-1/igt@xe_exec_sip_eudebug@wait-writesip-nodebug.html
* igt@xe_live_ktest@xe_eudebug:
- shard-lnl: [SKIP][173] ([Intel XE#2833]) -> [PASS][174]
[173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-lnl-7/igt@xe_live_ktest@xe_eudebug.html
[174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-3/igt@xe_live_ktest@xe_eudebug.html
- shard-bmg: [SKIP][175] ([Intel XE#2833]) -> [PASS][176]
[175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-bmg-1/igt@xe_live_ktest@xe_eudebug.html
[176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-bmg-2/igt@xe_live_ktest@xe_eudebug.html
#### Warnings ####
* igt@kms_hdr@brightness-with-hdr:
- shard-bmg: [SKIP][177] ([Intel XE#3374] / [Intel XE#3544]) -> [SKIP][178] ([Intel XE#3544])
[177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-bmg-8/igt@kms_hdr@brightness-with-hdr.html
[178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-bmg-6/igt@kms_hdr@brightness-with-hdr.html
* igt@kms_tiled_display@basic-test-pattern:
- shard-bmg: [FAIL][179] ([Intel XE#1729] / [Intel XE#7424]) -> [SKIP][180] ([Intel XE#2426] / [Intel XE#5848])
[179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-bmg-6/igt@kms_tiled_display@basic-test-pattern.html
[180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-bmg-8/igt@kms_tiled_display@basic-test-pattern.html
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-bmg: [SKIP][181] ([Intel XE#2426] / [Intel XE#5848]) -> [SKIP][182] ([Intel XE#2509] / [Intel XE#7437])
[181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-bmg-1/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
[182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-bmg-2/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
* igt@xe_eudebug@basic-close:
- shard-lnl: [SKIP][183] ([Intel XE#7636]) -> [FAIL][184] ([Intel XE#7716])
[183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-lnl-1/igt@xe_eudebug@basic-close.html
[184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-7/igt@xe_eudebug@basic-close.html
- shard-bmg: [SKIP][185] ([Intel XE#7636]) -> [FAIL][186] ([Intel XE#7716])
[185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-bmg-5/igt@xe_eudebug@basic-close.html
[186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-bmg-4/igt@xe_eudebug@basic-close.html
* igt@xe_eudebug@basic-connect:
- shard-bmg: [SKIP][187] ([Intel XE#7636]) -> [FAIL][188] ([Intel XE#7717])
[187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-bmg-2/igt@xe_eudebug@basic-connect.html
[188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-bmg-1/igt@xe_eudebug@basic-connect.html
* igt@xe_eudebug@basic-read-event:
- shard-bmg: [SKIP][189] ([Intel XE#7636]) -> [FAIL][190] ([Intel XE#7709]) +6 other tests fail
[189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-bmg-1/igt@xe_eudebug@basic-read-event.html
[190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-bmg-2/igt@xe_eudebug@basic-read-event.html
* igt@xe_eudebug@basic-vm-access-faultable:
- shard-lnl: [SKIP][191] ([Intel XE#7636]) -> [FAIL][192] ([Intel XE#7707]) +31 other tests fail
[191]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-lnl-3/igt@xe_eudebug@basic-vm-access-faultable.html
[192]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-1/igt@xe_eudebug@basic-vm-access-faultable.html
* igt@xe_eudebug@basic-vm-bind-ufence-delay-ack:
- shard-lnl: [SKIP][193] ([Intel XE#7636]) -> [FAIL][194] ([Intel XE#7709]) +7 other tests fail
[193]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-lnl-1/igt@xe_eudebug@basic-vm-bind-ufence-delay-ack.html
[194]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-7/igt@xe_eudebug@basic-vm-bind-ufence-delay-ack.html
* igt@xe_eudebug@connect-user:
- shard-bmg: [SKIP][195] ([Intel XE#7636]) -> [FAIL][196] ([Intel XE#7708])
[195]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-bmg-5/igt@xe_eudebug@connect-user.html
[196]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-bmg-7/igt@xe_eudebug@connect-user.html
* igt@xe_eudebug@discovery-empty:
- shard-bmg: [SKIP][197] ([Intel XE#7636]) -> [FAIL][198] ([Intel XE#7718]) +1 other test fail
[197]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-bmg-7/igt@xe_eudebug@discovery-empty.html
[198]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-bmg-1/igt@xe_eudebug@discovery-empty.html
- shard-lnl: [SKIP][199] ([Intel XE#7636]) -> [FAIL][200] ([Intel XE#7718])
[199]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-lnl-8/igt@xe_eudebug@discovery-empty.html
[200]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-5/igt@xe_eudebug@discovery-empty.html
* igt@xe_eudebug@discovery-race-sigint:
- shard-lnl: [SKIP][201] ([Intel XE#7636]) -> [FAIL][202] ([Intel XE#7753]) +1 other test fail
[201]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-lnl-4/igt@xe_eudebug@discovery-race-sigint.html
[202]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-8/igt@xe_eudebug@discovery-race-sigint.html
* igt@xe_eudebug@discovery-race-vmbind:
- shard-bmg: [SKIP][203] ([Intel XE#7636]) -> [FAIL][204] ([Intel XE#7753]) +2 other tests fail
[203]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-bmg-8/igt@xe_eudebug@discovery-race-vmbind.html
[204]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-bmg-10/igt@xe_eudebug@discovery-race-vmbind.html
* igt@xe_eudebug@multigpu-basic-client:
- shard-bmg: [SKIP][205] ([Intel XE#7636]) -> [SKIP][206] ([Intel XE#3894]) +1 other test skip
[205]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-bmg-1/igt@xe_eudebug@multigpu-basic-client.html
[206]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-bmg-2/igt@xe_eudebug@multigpu-basic-client.html
* igt@xe_eudebug@multigpu-basic-client-many:
- shard-lnl: [SKIP][207] ([Intel XE#7636]) -> [SKIP][208] ([Intel XE#5132]) +1 other test skip
[207]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-lnl-5/igt@xe_eudebug@multigpu-basic-client-many.html
[208]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-4/igt@xe_eudebug@multigpu-basic-client-many.html
* igt@xe_eudebug@sysfs-toggle:
- shard-lnl: [SKIP][209] ([Intel XE#7636]) -> [FAIL][210] ([Intel XE#7720])
[209]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-lnl-4/igt@xe_eudebug@sysfs-toggle.html
[210]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-8/igt@xe_eudebug@sysfs-toggle.html
- shard-bmg: [SKIP][211] ([Intel XE#7636]) -> [FAIL][212] ([Intel XE#7720])
[211]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-bmg-8/igt@xe_eudebug@sysfs-toggle.html
[212]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-bmg-6/igt@xe_eudebug@sysfs-toggle.html
* igt@xe_eudebug@vm-bind-clear:
- shard-bmg: [SKIP][213] ([Intel XE#7636]) -> [FAIL][214] ([Intel XE#7723]) +3 other tests fail
[213]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-bmg-1/igt@xe_eudebug@vm-bind-clear.html
[214]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-bmg-2/igt@xe_eudebug@vm-bind-clear.html
* igt@xe_eudebug@vm-bind-clear-faultable:
- shard-lnl: [SKIP][215] ([Intel XE#7636]) -> [FAIL][216] ([Intel XE#7723]) +3 other tests fail
[215]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-lnl-4/igt@xe_eudebug@vm-bind-clear-faultable.html
[216]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-2/igt@xe_eudebug@vm-bind-clear-faultable.html
* igt@xe_eudebug_online@breakpoint-many-sessions-single-tile:
- shard-bmg: [SKIP][217] ([Intel XE#7636]) -> [FAIL][218] ([Intel XE#7754])
[217]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-bmg-6/igt@xe_eudebug_online@breakpoint-many-sessions-single-tile.html
[218]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-bmg-8/igt@xe_eudebug_online@breakpoint-many-sessions-single-tile.html
- shard-lnl: [SKIP][219] ([Intel XE#7636]) -> [FAIL][220] ([Intel XE#7754])
[219]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-lnl-3/igt@xe_eudebug_online@breakpoint-many-sessions-single-tile.html
[220]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-2/igt@xe_eudebug_online@breakpoint-many-sessions-single-tile.html
* igt@xe_eudebug_online@breakpoint-many-sessions-tiles:
- shard-bmg: [SKIP][221] ([Intel XE#7636]) -> [SKIP][222] ([Intel XE#2846])
[221]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-bmg-7/igt@xe_eudebug_online@breakpoint-many-sessions-tiles.html
[222]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-bmg-1/igt@xe_eudebug_online@breakpoint-many-sessions-tiles.html
- shard-lnl: [SKIP][223] ([Intel XE#7636]) -> [SKIP][224] ([Intel XE#2846])
[223]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-lnl-2/igt@xe_eudebug_online@breakpoint-many-sessions-tiles.html
[224]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-5/igt@xe_eudebug_online@breakpoint-many-sessions-tiles.html
* igt@xe_eudebug_online@set-breakpoint-faultable:
- shard-bmg: [SKIP][225] ([Intel XE#7636]) -> [FAIL][226] ([Intel XE#7707]) +41 other tests fail
[225]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-bmg-2/igt@xe_eudebug_online@set-breakpoint-faultable.html
[226]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-bmg-2/igt@xe_eudebug_online@set-breakpoint-faultable.html
* igt@xe_eudebug_online@writes-caching-sram-bb-vram-target-sram:
- shard-lnl: [SKIP][227] ([Intel XE#7636]) -> [SKIP][228] ([Intel XE#2825] / [Intel XE#7430]) +3 other tests skip
[227]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-lnl-7/igt@xe_eudebug_online@writes-caching-sram-bb-vram-target-sram.html
[228]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-3/igt@xe_eudebug_online@writes-caching-sram-bb-vram-target-sram.html
* igt@xe_eudebug_online@writes-caching-sram-bb-vram-target-vram:
- shard-lnl: [SKIP][229] ([Intel XE#7636]) -> [SKIP][230] ([Intel XE#2825]) +1 other test skip
[229]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-lnl-2/igt@xe_eudebug_online@writes-caching-sram-bb-vram-target-vram.html
[230]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-5/igt@xe_eudebug_online@writes-caching-sram-bb-vram-target-vram.html
* igt@xe_exec_sip_eudebug@breakpoint-writesip:
- shard-lnl: [SKIP][231] ([Intel XE#7636]) -> [FAIL][232] ([Intel XE#7715]) +3 other tests fail
[231]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-lnl-5/igt@xe_exec_sip_eudebug@breakpoint-writesip.html
[232]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-lnl-4/igt@xe_exec_sip_eudebug@breakpoint-writesip.html
- shard-bmg: [SKIP][233] ([Intel XE#7636]) -> [FAIL][234] ([Intel XE#7715]) +3 other tests fail
[233]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d/shard-bmg-9/igt@xe_exec_sip_eudebug@breakpoint-writesip.html
[234]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/shard-bmg-9/igt@xe_exec_sip_eudebug@breakpoint-writesip.html
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1125]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1125
[Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
[Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
[Intel XE#1397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1397
[Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
[Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
[Intel XE#1420]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1420
[Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
[Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
[Intel XE#1469]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1469
[Intel XE#1470]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1470
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
[Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
[Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
[Intel XE#2142]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2142
[Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
[Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
[Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
[Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
[Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
[Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
[Intel XE#2669]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2669
[Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
[Intel XE#2825]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2825
[Intel XE#2833]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2833
[Intel XE#2838]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2838
[Intel XE#2846]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2846
[Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
[Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
[Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
[Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
[Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
[Intel XE#330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/330
[Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
[Intel XE#3321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3321
[Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
[Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
[Intel XE#3658]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3658
[Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
[Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
[Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378
[Intel XE#3894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3894
[Intel XE#4227]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4227
[Intel XE#4351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4351
[Intel XE#4422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4422
[Intel XE#4608]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4608
[Intel XE#4609]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4609
[Intel XE#5100]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5100
[Intel XE#5132]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5132
[Intel XE#5745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5745
[Intel XE#5793]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5793
[Intel XE#5812]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5812
[Intel XE#584]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/584
[Intel XE#5848]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5848
[Intel XE#5857]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5857
[Intel XE#599]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/599
[Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
[Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
[Intel XE#6376]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6376
[Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
[Intel XE#6540]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6540
[Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
[Intel XE#6627]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6627
[Intel XE#6813]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6813
[Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
[Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
[Intel XE#6886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6886
[Intel XE#6900]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6900
[Intel XE#6911]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6911
[Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
[Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
[Intel XE#7098]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7098
[Intel XE#7130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7130
[Intel XE#7136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7136
[Intel XE#7138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7138
[Intel XE#7174]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7174
[Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
[Intel XE#7179]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7179
[Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
[Intel XE#7304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7304
[Intel XE#7312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7312
[Intel XE#7320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7320
[Intel XE#7322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7322
[Intel XE#7330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7330
[Intel XE#7343]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7343
[Intel XE#7345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7345
[Intel XE#7349]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7349
[Intel XE#7351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7351
[Intel XE#7355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7355
[Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
[Intel XE#7357]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7357
[Intel XE#7358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7358
[Intel XE#7360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7360
[Intel XE#7362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7362
[Intel XE#7369]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7369
[Intel XE#7370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7370
[Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
[Intel XE#7374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7374
[Intel XE#7376]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7376
[Intel XE#7385]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7385
[Intel XE#7389]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7389
[Intel XE#7399]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7399
[Intel XE#7405]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7405
[Intel XE#7408]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7408
[Intel XE#7419]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7419
[Intel XE#7422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7422
[Intel XE#7424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7424
[Intel XE#7430]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7430
[Intel XE#7437]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7437
[Intel XE#7442]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7442
[Intel XE#7464]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7464
[Intel XE#7466]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7466
[Intel XE#7482]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7482
[Intel XE#7571]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7571
[Intel XE#7590]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7590
[Intel XE#7636]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7636
[Intel XE#7642]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7642
[Intel XE#7676]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7676
[Intel XE#7707]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7707
[Intel XE#7708]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7708
[Intel XE#7709]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7709
[Intel XE#7715]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7715
[Intel XE#7716]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7716
[Intel XE#7717]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7717
[Intel XE#7718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7718
[Intel XE#7720]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7720
[Intel XE#7723]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7723
[Intel XE#7753]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7753
[Intel XE#7754]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7754
[Intel XE#7793]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7793
[Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
[Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
[Intel XE#977]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/977
Build changes
-------------
* Linux: xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d -> xe-pw-165777v1
IGT_8879: 02b0e01dd9a5a3ab1efe976bb8c4f13cfcdbab1a @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-4959-3ac514cf64f272cc4d5143f4cc28fb18a8aba76d: 3ac514cf64f272cc4d5143f4cc28fb18a8aba76d
xe-pw-165777v1: 165777v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-165777v1/index.html
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