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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org
Subject: [PATCH 1/2] drm/xe: Use fb cached min alignment
Date: Thu, 30 Apr 2026 18:46:01 +0300	[thread overview]
Message-ID: <20260430154602.11393-1-ville.syrjala@linux.intel.com> (raw)

From: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>

Instead of just looking at the first plane use the fb cached overall
minimum alignment.

This aligns with how the i915 version of intel_plane_pin_fb works.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
[vsyrjala: Rebase due to pin_params]
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/xe/display/xe_fb_pin.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c
index 948446346c53..3e8114fbfbaa 100644
--- a/drivers/gpu/drm/xe/display/xe_fb_pin.c
+++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c
@@ -459,6 +459,14 @@ static bool reuse_vma(struct intel_plane_state *new_plane_state,
 	return true;
 }
 
+static unsigned int
+intel_plane_fb_min_alignment(const struct intel_plane_state *plane_state)
+{
+	const struct intel_framebuffer *fb = to_intel_framebuffer(plane_state->hw.fb);
+
+	return fb->min_alignment;
+}
+
 int intel_plane_pin_fb(struct intel_plane_state *new_plane_state,
 		       const struct intel_plane_state *old_plane_state)
 {
@@ -469,7 +477,7 @@ int intel_plane_pin_fb(struct intel_plane_state *new_plane_state,
 	struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
 	struct intel_fb_pin_params pin_params = {
 		.view = &new_plane_state->view.gtt,
-		.alignment = plane->min_alignment(plane, fb, 0),
+		.alignment = intel_plane_fb_min_alignment(new_plane_state),
 		.needs_cpu_lmem_access = intel_fb_needs_cpu_access(fb),
 	};
 
-- 
2.52.0


             reply	other threads:[~2026-04-30 15:46 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-04-30 15:46 Ville Syrjala [this message]
2026-04-30 15:46 ` [PATCH 2/2] drm/xe: Respect pin_params.alignment for GGTT Ville Syrjala
2026-05-06 16:46   ` Juha-Pekka Heikkilä
2026-04-30 16:32 ` ✓ CI.KUnit: success for series starting with [1/2] drm/xe: Use fb cached min alignment Patchwork
2026-04-30 17:40 ` ✓ Xe.CI.BAT: " Patchwork
2026-05-01  4:18 ` ✗ Xe.CI.FULL: failure " Patchwork
2026-05-06 16:44 ` [PATCH 1/2] " Juha-Pekka Heikkilä

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