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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org
Subject: [PATCH 2/2] drm/xe: Respect pin_params.alignment for GGTT
Date: Thu, 30 Apr 2026 18:46:02 +0300	[thread overview]
Message-ID: <20260430154602.11393-2-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20260430154602.11393-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Fix __xe_pin_fb_vma_ggtt() to actually respect the GGTT alignment
specified by the display code. Misalignment can cause GTT faults
etc.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/xe/display/xe_fb_pin.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c
index 3e8114fbfbaa..8d0067f908c5 100644
--- a/drivers/gpu/drm/xe/display/xe_fb_pin.c
+++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c
@@ -286,7 +286,7 @@ static int __xe_pin_fb_vma_ggtt(struct drm_gem_object *obj,
 	 */
 	guard(xe_pm_runtime_noresume)(xe);
 
-	align = XE_PAGE_SIZE;
+	align = max(XE_PAGE_SIZE, pin_params->alignment);
 	if (xe_bo_is_vram(bo) && xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K)
 		align = max(align, SZ_64K);
 
-- 
2.52.0


  reply	other threads:[~2026-04-30 15:46 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-04-30 15:46 [PATCH 1/2] drm/xe: Use fb cached min alignment Ville Syrjala
2026-04-30 15:46 ` Ville Syrjala [this message]
2026-05-06 16:46   ` [PATCH 2/2] drm/xe: Respect pin_params.alignment for GGTT Juha-Pekka Heikkilä
2026-04-30 16:32 ` ✓ CI.KUnit: success for series starting with [1/2] drm/xe: Use fb cached min alignment Patchwork
2026-04-30 17:40 ` ✓ Xe.CI.BAT: " Patchwork
2026-05-01  4:18 ` ✗ Xe.CI.FULL: failure " Patchwork
2026-05-06 16:44 ` [PATCH 1/2] " Juha-Pekka Heikkilä

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