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From: Stuart Summers <stuart.summers@intel.com>
Cc: michal.wajdeczko@intel.com, ilia.levi@intel.com,
	x.wang@intel.com, rodrigo.vivi@intel.com,
	intel-xe@lists.freedesktop.org,
	alan.previn.teres.alexis@intel.com,
	Stuart Summers <stuart.summers@intel.com>
Subject: [PATCH 06/11] drm/xe: Remove memirq status and source checks for engine interrupts
Date: Wed, 10 Jun 2026 21:28:38 +0000	[thread overview]
Message-ID: <20260610212833.153366-19-stuart.summers@intel.com> (raw)
In-Reply-To: <20260610212833.153366-13-stuart.summers@intel.com>

For engine-specific, memory-based interrupts, hardware will not fill in
the source and status offsets, assuming that software will utilize the
vector ID to determine the destination for a particular interrupt.

GuC and VF based interrupts are still handled the same - explicitly
checking these offsets.

Bspec: 62316
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Assisted-by: Copilot:claude-sonnet-4.6
---
 drivers/gpu/drm/xe/xe_memirq.c | 36 ++++++++++------------------------
 1 file changed, 10 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_memirq.c b/drivers/gpu/drm/xe/xe_memirq.c
index 9dfe965cb46e..96ab2c59c5d7 100644
--- a/drivers/gpu/drm/xe/xe_memirq.c
+++ b/drivers/gpu/drm/xe/xe_memirq.c
@@ -447,21 +447,6 @@ static void memirq_assume_received(struct xe_memirq *memirq, const char *source,
 	memirq_debug(memirq, "ASSUME %s %s(%u)\n", source, status, offset);
 }
 
-static void memirq_dispatch_engine(struct xe_memirq *memirq, struct iosys_map *status,
-				   struct xe_hw_engine *hwe)
-{
-	memirq_debug(memirq, "STATUS %s %*ph\n", hwe->name, 16, status->vaddr);
-
-	/*
-	 * The programming note says to assume that GT_MI_USER_INTERRUPT is always
-	 * set. Check and clear related status byte just for a debug.
-	 */
-	if (IS_ENABLED(CONFIG_DRM_XE_DEBUG_MEMIRQ) &&
-	    !memirq_received(memirq, status, ilog2(GT_MI_USER_INTERRUPT), hwe->name))
-		memirq_assume_received(memirq, hwe->name, ilog2(GT_MI_USER_INTERRUPT), "USER");
-	xe_hw_engine_handle_irq(hwe, GT_MI_USER_INTERRUPT);
-}
-
 static void memirq_dispatch_guc(struct xe_memirq *memirq, struct iosys_map *status,
 				struct xe_guc *guc)
 {
@@ -499,17 +484,16 @@ static void memirq_dispatch_guc(struct xe_memirq *memirq, struct iosys_map *stat
  */
 void xe_memirq_hwe_handler(struct xe_memirq *memirq, struct xe_hw_engine *hwe)
 {
-	struct iosys_map source =
-		IOSYS_MAP_INIT_OFFSET(&memirq->bo->vmap,
-				      XE_MEMIRQ_SOURCE_OFFSET(hwe->irq_page));
-
-	if (memirq_received(memirq, &source, hwe->irq_offset, "SRC")) {
-		struct iosys_map status =
-			IOSYS_MAP_INIT_OFFSET(&memirq->bo->vmap,
-					      XE_MEMIRQ_VECTOR_OFFSET(hwe->irq_page,
-								      hwe->irq_offset));
-		memirq_dispatch_engine(memirq, &status, hwe);
-	}
+	memirq_debug(memirq, "dispatching engine %s\n", hwe->name);
+
+	/*
+	 * On MSI-X platforms hardware does not fill in the source and status
+	 * fields for engine-based interrupts (only GuC and VF interrupts have
+	 * a valid source/status). The dma-fence check for the fence completion
+	 * is opportunistic, unconditionally pass MI_USER_INTERRUPT to issue
+	 * that check.
+	 */
+	xe_hw_engine_handle_irq(hwe, GT_MI_USER_INTERRUPT);
 }
 
 /**
-- 
2.43.0


  parent reply	other threads:[~2026-06-10 21:28 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-10 21:28 [PATCH 00/11] Enable per exec queue MSI-X vector assignment Stuart Summers
2026-06-10 21:28 ` [PATCH 01/11] drm/xe: Add kerneldoc to xe_wait_user_fence_ioctl() Stuart Summers
2026-06-10 21:28 ` [PATCH 02/11] drm/xe: Handle NULL in xe_exec_queue_get_unless_zero() Stuart Summers
2026-06-10 21:28 ` [PATCH 03/11] drm/xe: Cap MSI-X vector count to XE_MSIX_MAX_VECS Stuart Summers
2026-06-11 10:47   ` Maarten Lankhorst
2026-06-11 22:49     ` Summers, Stuart
2026-06-12  8:50       ` Maarten Lankhorst
2026-06-12 15:32         ` Summers, Stuart
2026-06-10 21:28 ` [PATCH 04/11] drm/xe: Assign dedicated MSI-X vectors to exec queues Stuart Summers
2026-06-10 21:28 ` [PATCH 05/11] drm/xe: Add configfs max_msix_vecs attribute Stuart Summers
2026-06-10 21:28 ` Stuart Summers [this message]
2026-06-10 21:28 ` [PATCH 07/11] drm/xe: Add per-exec-queue user fence wait queue Stuart Summers
2026-06-10 23:35   ` Matthew Brost
2026-06-11 22:50     ` Summers, Stuart
2026-06-10 21:28 ` [PATCH 08/11] drm/xe: Track all exec queues in a device-level ufence list Stuart Summers
2026-06-10 21:28 ` [PATCH 09/11] drm/xe: Hook up per queue thread wake to the unique MSI-X vector allocation Stuart Summers
2026-06-10 21:28 ` [PATCH 10/11] drm/xe: Enable per-queue ufence wake in ioctl and wake function Stuart Summers
2026-06-10 21:28 ` [PATCH 11/11] drm/xe/memirq: Enable compute walker post-sync interrupt Stuart Summers
2026-06-10 22:06 ` ✗ CI.checkpatch: warning for Enable per exec queue MSI-X vector assignment (rev2) Patchwork
2026-06-10 22:07 ` ✓ CI.KUnit: success " Patchwork
2026-06-10 22:59 ` ✓ Xe.CI.BAT: " Patchwork
2026-06-10 23:51 ` [PATCH 00/11] Enable per exec queue MSI-X vector assignment Matthew Brost
2026-06-11 23:08   ` Summers, Stuart
2026-06-12  0:17     ` Matthew Brost
2026-06-11  6:58 ` ✓ Xe.CI.FULL: success for Enable per exec queue MSI-X vector assignment (rev2) Patchwork

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