Intel-XE Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: Stuart Summers <stuart.summers@intel.com>
Cc: michal.wajdeczko@intel.com, ilia.levi@intel.com,
	x.wang@intel.com, rodrigo.vivi@intel.com,
	intel-xe@lists.freedesktop.org,
	alan.previn.teres.alexis@intel.com,
	Stuart Summers <stuart.summers@intel.com>
Subject: [PATCH 09/11] drm/xe: Hook up per queue thread wake to the unique MSI-X vector allocation
Date: Wed, 10 Jun 2026 21:28:41 +0000	[thread overview]
Message-ID: <20260610212833.153366-22-stuart.summers@intel.com> (raw)
In-Reply-To: <20260610212833.153366-13-stuart.summers@intel.com>

When a dedicated MSI-X vector fires for a specific exec queue, the
interrupt handler already has the queue pointer available.  Thread it
through the call chain so we can wake the per-queue ufence_wq without
impact any other user threads.

Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Assisted-by: Copilot:claude-sonnet-4.6
---
 drivers/gpu/drm/xe/xe_irq.c    |  4 ++--
 drivers/gpu/drm/xe/xe_memirq.c | 13 +++++++++----
 drivers/gpu/drm/xe/xe_memirq.h |  4 +++-
 3 files changed, 14 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index fc99d021405f..b25cfcdc4b43 100644
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -927,7 +927,7 @@ static irqreturn_t xe_irq_msix_default_hwe_handler(int irq, void *arg)
 				continue;
 
 			for_each_hw_engine(hwe, gt, id)
-				xe_memirq_hwe_handler(memirq, hwe);
+				xe_memirq_hwe_handler(memirq, hwe, NULL);
 		}
 	}
 
@@ -942,7 +942,7 @@ irqreturn_t xe_irq_msix_hwe_handler(int irq, void *arg)
 	if (!atomic_read(&tile->xe->irq.enabled))
 		return IRQ_NONE;
 
-	xe_memirq_hwe_handler(&tile->memirq, q->hwe);
+	xe_memirq_hwe_handler(&tile->memirq, q->hwe, q);
 
 	return IRQ_HANDLED;
 }
diff --git a/drivers/gpu/drm/xe/xe_memirq.c b/drivers/gpu/drm/xe/xe_memirq.c
index 318ef7c72eba..dc21f154db71 100644
--- a/drivers/gpu/drm/xe/xe_memirq.c
+++ b/drivers/gpu/drm/xe/xe_memirq.c
@@ -479,10 +479,15 @@ static void memirq_dispatch_guc(struct xe_memirq *memirq, struct iosys_map *stat
  * xe_memirq_hwe_handler - Check and process interrupts for a specific HW engine.
  * @memirq: the &xe_memirq
  * @hwe: the hw engine to process
+ * @q: the exec queue associated with this interrupt, or NULL
  *
- * This function reads and dispatches `Memory Based Interrupts` for the provided HW engine.
+ * This function reads and dispatches `Memory Based Interrupts` for the provided
+ * HW engine. When @q is non-NULL (e.g. called from a dedicated MSI-X vector
+ * handler), it is passed through so the per-queue user fence wait queue is
+ * woken rather than the device-level one.
  */
-void xe_memirq_hwe_handler(struct xe_memirq *memirq, struct xe_hw_engine *hwe)
+void xe_memirq_hwe_handler(struct xe_memirq *memirq, struct xe_hw_engine *hwe,
+			   struct xe_exec_queue *q)
 {
 	memirq_debug(memirq, "dispatching engine %s\n", hwe->name);
 
@@ -493,7 +498,7 @@ void xe_memirq_hwe_handler(struct xe_memirq *memirq, struct xe_hw_engine *hwe)
 	 * is opportunistic, unconditionally pass MI_USER_INTERRUPT to issue
 	 * that check.
 	 */
-	xe_hw_engine_handle_irq(hwe, GT_MI_USER_INTERRUPT, NULL);
+	xe_hw_engine_handle_irq(hwe, GT_MI_USER_INTERRUPT, q);
 }
 
 /**
@@ -553,7 +558,7 @@ void xe_memirq_handler(struct xe_memirq *memirq)
 			continue;
 
 		for_each_hw_engine(hwe, gt, id)
-			xe_memirq_hwe_handler(memirq, hwe);
+			xe_memirq_hwe_handler(memirq, hwe, NULL);
 	}
 
 	/* GuC and media GuC (if present) must be checked separately */
diff --git a/drivers/gpu/drm/xe/xe_memirq.h b/drivers/gpu/drm/xe/xe_memirq.h
index e25d2234ab87..7e2229ad1d38 100644
--- a/drivers/gpu/drm/xe/xe_memirq.h
+++ b/drivers/gpu/drm/xe/xe_memirq.h
@@ -8,6 +8,7 @@
 
 #include <linux/types.h>
 
+struct xe_exec_queue;
 struct xe_guc;
 struct xe_hw_engine;
 struct xe_memirq;
@@ -20,7 +21,8 @@ u32 xe_memirq_enable_ptr(struct xe_memirq *memirq);
 
 void xe_memirq_reset(struct xe_memirq *memirq);
 void xe_memirq_postinstall(struct xe_memirq *memirq);
-void xe_memirq_hwe_handler(struct xe_memirq *memirq, struct xe_hw_engine *hwe);
+void xe_memirq_hwe_handler(struct xe_memirq *memirq, struct xe_hw_engine *hwe,
+			   struct xe_exec_queue *q);
 void xe_memirq_handler(struct xe_memirq *memirq);
 
 int xe_memirq_init_guc(struct xe_memirq *memirq, struct xe_guc *guc);
-- 
2.43.0


  parent reply	other threads:[~2026-06-10 21:28 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-10 21:28 [PATCH 00/11] Enable per exec queue MSI-X vector assignment Stuart Summers
2026-06-10 21:28 ` [PATCH 01/11] drm/xe: Add kerneldoc to xe_wait_user_fence_ioctl() Stuart Summers
2026-06-10 21:28 ` [PATCH 02/11] drm/xe: Handle NULL in xe_exec_queue_get_unless_zero() Stuart Summers
2026-06-10 21:28 ` [PATCH 03/11] drm/xe: Cap MSI-X vector count to XE_MSIX_MAX_VECS Stuart Summers
2026-06-11 10:47   ` Maarten Lankhorst
2026-06-11 22:49     ` Summers, Stuart
2026-06-12  8:50       ` Maarten Lankhorst
2026-06-12 15:32         ` Summers, Stuart
2026-06-10 21:28 ` [PATCH 04/11] drm/xe: Assign dedicated MSI-X vectors to exec queues Stuart Summers
2026-06-10 21:28 ` [PATCH 05/11] drm/xe: Add configfs max_msix_vecs attribute Stuart Summers
2026-06-10 21:28 ` [PATCH 06/11] drm/xe: Remove memirq status and source checks for engine interrupts Stuart Summers
2026-06-10 21:28 ` [PATCH 07/11] drm/xe: Add per-exec-queue user fence wait queue Stuart Summers
2026-06-10 23:35   ` Matthew Brost
2026-06-11 22:50     ` Summers, Stuart
2026-06-10 21:28 ` [PATCH 08/11] drm/xe: Track all exec queues in a device-level ufence list Stuart Summers
2026-06-10 21:28 ` Stuart Summers [this message]
2026-06-10 21:28 ` [PATCH 10/11] drm/xe: Enable per-queue ufence wake in ioctl and wake function Stuart Summers
2026-06-10 21:28 ` [PATCH 11/11] drm/xe/memirq: Enable compute walker post-sync interrupt Stuart Summers
2026-06-10 22:06 ` ✗ CI.checkpatch: warning for Enable per exec queue MSI-X vector assignment (rev2) Patchwork
2026-06-10 22:07 ` ✓ CI.KUnit: success " Patchwork
2026-06-10 22:59 ` ✓ Xe.CI.BAT: " Patchwork
2026-06-10 23:51 ` [PATCH 00/11] Enable per exec queue MSI-X vector assignment Matthew Brost
2026-06-11 23:08   ` Summers, Stuart
2026-06-12  0:17     ` Matthew Brost
2026-06-11  6:58 ` ✓ Xe.CI.FULL: success for Enable per exec queue MSI-X vector assignment (rev2) Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20260610212833.153366-22-stuart.summers@intel.com \
    --to=stuart.summers@intel.com \
    --cc=alan.previn.teres.alexis@intel.com \
    --cc=ilia.levi@intel.com \
    --cc=intel-xe@lists.freedesktop.org \
    --cc=michal.wajdeczko@intel.com \
    --cc=rodrigo.vivi@intel.com \
    --cc=x.wang@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox