[PATCH v2 7/8] drm/xe/vm: validate large-page user BO bind alignment

[Nareshkumar Gollakoti <naresh.kumar.g@intel.com>]

Add VM bind validation for BOs that request 64K, 2M, or 1G pages.

When a BO is created with XE_BO_FLAG_NEEDS_64K, XE_BO_FLAG_NEEDS_2M,
or XE_BO_FLAG_NEEDS_1G, require the bind offset, virtual address, and
range to be aligned to the requested page size for map operations.
Skip these checks for unmap and unmap-all.

Also allow the corresponding VMA page table flags in the user-visible
VMA flag mask.

This prevents invalid bind requests for large-page BOs from reaching
later VM setup paths.

v2:(sashiko)
- add 64K alignment validation alongside 2M and 1G
  for user bindpaths
- keep large-page alignment checks skipped for
  UNMAP and UNMAP_ALL
- refine commit message wordings

Signed-off-by: Nareshkumar Gollakoti <naresh.kumar.g@intel.com>
---
 drivers/gpu/drm/xe/xe_vm.c | 35 ++++++++++++++++++++++++++++++++++-
 1 file changed, 34 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
index 50ca29a79533..3fc5f1db93d0 100644
--- a/drivers/gpu/drm/xe/xe_vm.c
+++ b/drivers/gpu/drm/xe/xe_vm.c
@@ -721,7 +721,10 @@ static void xe_vma_ops_incr_pt_update_ops(struct xe_vma_ops *vops, u8 tile_mask,
 	XE_VMA_DUMPABLE |		    \
 	XE_VMA_SYSTEM_ALLOCATOR |           \
 	DRM_GPUVA_SPARSE |		    \
-	XE_VMA_MADV_AUTORESET)
+	XE_VMA_MADV_AUTORESET |		    \
+	XE_VMA_PTE_64K |		    \
+	XE_VMA_PTE_2M  |		    \
+	XE_VMA_PTE_1G)
 
 static void xe_vm_populate_rebind(struct xe_vma_op *op, struct xe_vma *vma,
 				  u8 tile_mask)
@@ -3835,6 +3838,36 @@ static int xe_vm_bind_ioctl_validate_bo(struct xe_device *xe, struct xe_bo *bo,
 		}
 	}
 
+	if (bo->flags & XE_BO_FLAG_NEEDS_64K &&
+	    (op != DRM_XE_VM_BIND_OP_UNMAP &&
+	     op != DRM_XE_VM_BIND_OP_UNMAP_ALL)) {
+		if (XE_IOCTL_DBG(xe, obj_offset & (SZ_64K - 1)) ||
+		    XE_IOCTL_DBG(xe, addr & (SZ_64K - 1)) ||
+		    XE_IOCTL_DBG(xe, range & (SZ_64K - 1))) {
+			return -EINVAL;
+		}
+	}
+
+	if (bo->flags & XE_BO_FLAG_NEEDS_2M &&
+	    (op != DRM_XE_VM_BIND_OP_UNMAP &&
+	     op != DRM_XE_VM_BIND_OP_UNMAP_ALL)) {
+		if (XE_IOCTL_DBG(xe, obj_offset & (SZ_2M - 1)) ||
+		    XE_IOCTL_DBG(xe, addr & (SZ_2M - 1)) ||
+		    XE_IOCTL_DBG(xe, range & (SZ_2M - 1))) {
+			return -EINVAL;
+		}
+	}
+
+	if (bo->flags & XE_BO_FLAG_NEEDS_1G &&
+	    (op != DRM_XE_VM_BIND_OP_UNMAP &&
+	     op != DRM_XE_VM_BIND_OP_UNMAP_ALL)) {
+		if (XE_IOCTL_DBG(xe, obj_offset & (SZ_1G - 1)) ||
+		    XE_IOCTL_DBG(xe, addr & (SZ_1G - 1)) ||
+		    XE_IOCTL_DBG(xe, range & (SZ_1G - 1))) {
+			return -EINVAL;
+		}
+	}
+
 	coh_mode = xe_pat_index_get_coh_mode(xe, pat_index);
 	if (bo->cpu_caching) {
 		if (XE_IOCTL_DBG(xe, coh_mode == XE_COH_NONE &&
-- 
2.43.0