[RFC PATCH 7/7] drm/xe/cper: Log CPER record for correctable errors

[Badal Nilawar <badal.nilawar@intel.com>]

In xe_ras_counter_threshold_crossed(), emit a CPER record for each
correctable error reported via the counter threshold crossed event.

Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
Assisted-by: Copilot:claude-sonnet-4.6
---
 drivers/gpu/drm/xe/xe_ras.c | 75 +++++++++++++++++++++++++++++++++++++
 1 file changed, 75 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
index 8579cde6a4bf..53f192a2e97f 100644
--- a/drivers/gpu/drm/xe/xe_ras.c
+++ b/drivers/gpu/drm/xe/xe_ras.c
@@ -11,6 +11,7 @@
 #include "xe_printk.h"
 #include "xe_ras.h"
 #include "xe_ras_types.h"
+#include "xe_sig_ids.h"
 #include "xe_sysctrl.h"
 #include "xe_sysctrl_event_types.h"
 #include "xe_sysctrl_mailbox.h"
@@ -67,6 +68,10 @@ static const char *const xe_ras_components[] = {
 };
 static_assert(ARRAY_SIZE(xe_ras_components) == XE_RAS_COMP_MAX);
 
+static void emit_hw_error_cper(struct xe_device *xe,
+			       const struct xe_ras_error_class *error_class,
+			       u64 timestamp, u32 sig_id, u8 severity);
+
 static u8 drm_to_xe_ras_severity(u8 severity)
 {
 	switch (severity) {
@@ -133,6 +138,38 @@ static inline const char *comp_to_str(u8 component)
 	return xe_ras_components[component];
 }
 
+static u32 ras_comp_to_hw_sigid(u8 component)
+{
+	switch (component) {
+	case XE_RAS_COMP_DEVICE_MEMORY:
+		return XE_SIG_HW_DEVICE_MEMORY;
+	case XE_RAS_COMP_CORE_COMPUTE:
+		return XE_SIG_HW_CORE_COMPUTE;
+	case XE_RAS_COMP_PCIE:
+		return XE_SIG_HW_PCIE;
+	case XE_RAS_COMP_FABRIC:
+		return XE_SIG_HW_FABRIC;
+	case XE_RAS_COMP_SOC_INTERNAL:
+		return XE_SIG_HW_SOC_INTERNAL;
+	default:
+		return U32_MAX;
+	}
+}
+
+static u8 ras_sev_to_cper_sev(u8 ras_sev)
+{
+	switch (ras_sev) {
+	case XE_RAS_SEV_CORRECTABLE:
+		return CPER_SEV_CORRECTED;
+	case XE_RAS_SEV_UNCORRECTABLE:
+		return CPER_SEV_RECOVERABLE;
+	case XE_RAS_SEV_INFORMATIONAL:
+		return CPER_SEV_INFORMATIONAL;
+	default:
+		return CPER_SEV_RECOVERABLE;
+	}
+}
+
 void xe_ras_counter_threshold_crossed(struct xe_device *xe,
 				      struct xe_sysctrl_event_response *response)
 {
@@ -154,6 +191,9 @@ void xe_ras_counter_threshold_crossed(struct xe_device *xe,
 		severity = errors[id].common.severity;
 		component = errors[id].common.component;
 
+		/* Emit a CPER record for this error */
+		emit_hw_error_cper(xe, &errors[id], 0, ras_comp_to_hw_sigid(component), severity);
+
 		xe_warn(xe, "[RAS]: %s %s detected\n",
 			comp_to_str(component), sev_to_str(severity));
 	}
@@ -451,6 +491,41 @@ prepare_cper_error_info(struct xe_device *xe,
 	return einfo;
 }
 
+static void emit_hw_error_cper(struct xe_device *xe,
+			       const struct xe_ras_error_class *error_class,
+			       u64 timestamp, u32 sig_id, u8 severity)
+{
+	struct xe_ras_get_counter_response counter_response = {};
+	struct xe_cper_sec_intel_err_hdr ihdr = {};
+	struct xe_cper_sec_intel_error_info *einfo = NULL;
+	u32 einfo_size = 0;
+
+	if (get_counter(xe, error_class, &counter_response)) {
+		xe_err(xe, "[RAS]: CPER: failed to get counter, skipping record\n");
+		return;
+	}
+
+	xe_cper_init_intel_err_hdr(xe,
+				   (const u8 *)error_class,
+				   timestamp,
+				   sig_id,
+				   counter_response.value,
+				   &ihdr);
+
+	if (counter_response.has_info_queue) {
+		einfo = prepare_cper_error_info(xe, &counter_response,
+						error_class, &einfo_size);
+		if (!einfo)
+			xe_err(xe, "[RAS]: CPER: failed to build einfo from info queue\n");
+	}
+
+	xe_cper_record_emit(xe, &guid_null,
+			    ras_sev_to_cper_sev(severity),
+			    INTEL_CPER_NOTIFY_GPU_ERROR,
+			    &ihdr, einfo, einfo_size);
+	kfree(einfo);
+}
+
 /**
  * xe_ras_init - Initialize Xe RAS
  * @xe: xe device instance
-- 
2.54.0