[RFC PATCH 0/2] LNL_FLUSH

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* [RFC PATCH 0/2] LNL_FLUSH_* enhancements
@ 2026-07-22 21:59 Matthew Brost
  2026-07-22 21:59 ` [RFC PATCH 1/2] drm/xe: Scope LNL_FLUSH_* workaround to affected CPUs, not GPU platform Matthew Brost
                   ` (4 more replies)
  0 siblings, 5 replies; 6+ messages in thread
From: Matthew Brost @ 2026-07-22 21:59 UTC (permalink / raw)
  To: intel-xe

The LNL_FLUSH_* workaround is a horrid hack that has been papering over
bugs. Let's limit its scope to determine whether it is actually needed
on newer platforms and add more debug information for cases where it
still occurs.

This came up again in the context of this series [1].

Matt

[1] https://patchwork.freedesktop.org/series/170916/ 

Matthew Brost (2):
  drm/xe: Scope LNL_FLUSH_* workaround to affected CPUs, not GPU
    platform
  drm/xe: Add DRM_XE_DEBUG_FLUSH_WA to force the CPU flush workaround on

 drivers/gpu/drm/xe/Kconfig.debug        | 16 ++++++
 drivers/gpu/drm/xe/Makefile             |  1 +
 drivers/gpu/drm/xe/xe_cpu_info.c        | 67 +++++++++++++++++++++++++
 drivers/gpu/drm/xe/xe_cpu_info.h        | 13 +++++
 drivers/gpu/drm/xe/xe_device.h          | 35 +++++++++----
 drivers/gpu/drm/xe/xe_device_types.h    | 10 ++++
 drivers/gpu/drm/xe/xe_guc_ct.c          | 56 +++++++++++++++++++--
 drivers/gpu/drm/xe/xe_guc_ct.h          |  1 +
 drivers/gpu/drm/xe/xe_guc_tlb_inval.c   |  2 +-
 drivers/gpu/drm/xe/xe_pci.c             | 10 ++++
 drivers/gpu/drm/xe/xe_tlb_inval.c       | 28 +++++++++++
 drivers/gpu/drm/xe/xe_wait_user_fence.c |  6 ++-
 12 files changed, 228 insertions(+), 17 deletions(-)
 create mode 100644 drivers/gpu/drm/xe/xe_cpu_info.c
 create mode 100644 drivers/gpu/drm/xe/xe_cpu_info.h

-- 
2.34.1


^ permalink raw reply	[flat|nested] 6+ messages in thread

* [RFC PATCH 1/2] drm/xe: Scope LNL_FLUSH_* workaround to affected CPUs, not GPU platform
  2026-07-22 21:59 [RFC PATCH 0/2] LNL_FLUSH_* enhancements Matthew Brost
@ 2026-07-22 21:59 ` Matthew Brost
  2026-07-22 21:59 ` [RFC PATCH 2/2] drm/xe: Add DRM_XE_DEBUG_FLUSH_WA to force the CPU flush workaround on Matthew Brost
                   ` (3 subsequent siblings)
  4 siblings, 0 replies; 6+ messages in thread
From: Matthew Brost @ 2026-07-22 21:59 UTC (permalink / raw)
  To: intel-xe; +Cc: Tales A . Mendonça

The LNL_FLUSH_WORKQUEUE()/LNL_FLUSH_WORK() workaround exists because
some Intel hybrid (Performance + Efficiency core) client CPUs can
delay workqueue worker scheduling by more than a second, causing
spurious G2H timeouts. This is purely a host CPU scheduling issue, but
the workaround was unconditionally applied on every platform,
regardless of the actual CPU it's paired with (e.g. a discrete GPU
attached to an unaffected CPU still paid the cost, while an affected
CPU paired with any other GPU was never covered).

Add xe_cpu_info.c/h (modeled on i915's intel_cpu_info.c) to detect the
affected CPUs (Alder Lake through Arrow Lake) via x86_match_cpu(), and
store the result in xe->info.needs_flush_wa at probe time. The
workaround is now only applied when this bit is set, independent of
xe->info.platform.

Also add loud diagnostics around the workaround:

 - xe_wait_user_fence.c: bump the 'WA resolved timeout' message from
   drm_dbg to drm_warn and gate it on the WA flag.
 - xe_tlb_inval.c: the TLB invalidation timeout path was missing a
   complaint when the WA-driven flush actually resolved pending
   fences before they were reported as timed out; add one.
 - xe_guc_ct.c: add xe_guc_ct_flush_g2h_worker(), which detects
   (best-effort, since the workqueue API offers no way to prove a
   work item's scheduling was delayed) whether the G2H ring has
   messages available but the G2H worker is neither queued nor
   running, warns loudly when so, and re-queues the worker before
   flushing. Use this instead of raw LNL_FLUSH_WORK() in both call
   sites and drop the now-unused macro.
 - xe_guc_ct.c: warn in receive_g2h() when we bail out because we
   can't get a runtime PM reference and aren't in a PM callback,
   since pending G2H may be silently dropped in that case.

Cc: Tales A. Mendonça <talesam@gmail.com>
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Assisted-by: GitHub Copilot:claude-sonnet-5
---
 drivers/gpu/drm/xe/Makefile             |  1 +
 drivers/gpu/drm/xe/xe_cpu_info.c        | 67 +++++++++++++++++++++++++
 drivers/gpu/drm/xe/xe_cpu_info.h        | 13 +++++
 drivers/gpu/drm/xe/xe_device.h          | 35 +++++++++----
 drivers/gpu/drm/xe/xe_device_types.h    |  9 ++++
 drivers/gpu/drm/xe/xe_guc_ct.c          | 56 +++++++++++++++++++--
 drivers/gpu/drm/xe/xe_guc_ct.h          |  1 +
 drivers/gpu/drm/xe/xe_guc_tlb_inval.c   |  2 +-
 drivers/gpu/drm/xe/xe_pci.c             |  9 ++++
 drivers/gpu/drm/xe/xe_tlb_inval.c       | 28 +++++++++++
 drivers/gpu/drm/xe/xe_wait_user_fence.c |  6 ++-
 11 files changed, 210 insertions(+), 17 deletions(-)
 create mode 100644 drivers/gpu/drm/xe/xe_cpu_info.c
 create mode 100644 drivers/gpu/drm/xe/xe_cpu_info.h

diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 67ada1d6c2fb..0a317d6b69f3 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -35,6 +35,7 @@ $(obj)/generated/%_device_wa_oob.c $(obj)/generated/%_device_wa_oob.h: $(obj)/xe
 xe-y += xe_bb.o \
 	xe_bo.o \
 	xe_bo_evict.o \
+	xe_cpu_info.o \
 	xe_dep_scheduler.o \
 	xe_devcoredump.o \
 	xe_device.o \
diff --git a/drivers/gpu/drm/xe/xe_cpu_info.c b/drivers/gpu/drm/xe/xe_cpu_info.c
new file mode 100644
index 000000000000..29cbd540f8cb
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_cpu_info.c
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2025 Intel Corporation
+ *
+ * Avoid INTEL_<PLATFORM> name collisions between asm/intel-family.h and
+ * xe_platform_types.h by having a separate file.
+ */
+
+#include "xe_cpu_info.h"
+
+#ifdef CONFIG_X86
+#include <asm/cpu_device_id.h>
+#include <asm/intel-family.h>
+
+/*
+ * Intel hybrid (Performance + Efficiency core) client CPUs up to and
+ * including Arrow Lake are known to occasionally delay scheduling of
+ * workqueue workers by more than a second, even after the work has been
+ * queued and the workqueue activated. This is caused by P/E core scheduling
+ * behavior on the host CPU and is unrelated to which GPU is attached,
+ * including a discrete GPU, so this cannot be inferred from the GPU
+ * platform.
+ *
+ * Platforms newer than Arrow Lake are intentionally excluded here: the issue
+ * has not been reproduced on them and this list should not be grown without
+ * new evidence the workaround is required.
+ */
+static const struct x86_cpu_id hybrid_flush_wa_cpu_ids[] = {
+	X86_MATCH_VFM(INTEL_ALDERLAKE,		NULL),
+	X86_MATCH_VFM(INTEL_ALDERLAKE_L,	NULL),
+	X86_MATCH_VFM(INTEL_RAPTORLAKE,		NULL),
+	X86_MATCH_VFM(INTEL_RAPTORLAKE_P,	NULL),
+	X86_MATCH_VFM(INTEL_RAPTORLAKE_S,	NULL),
+	X86_MATCH_VFM(INTEL_METEORLAKE,		NULL),
+	X86_MATCH_VFM(INTEL_METEORLAKE_L,	NULL),
+	X86_MATCH_VFM(INTEL_LUNARLAKE_M,	NULL),
+	X86_MATCH_VFM(INTEL_ARROWLAKE,		NULL),
+	X86_MATCH_VFM(INTEL_ARROWLAKE_H,	NULL),
+	X86_MATCH_VFM(INTEL_ARROWLAKE_U,	NULL),
+	{}
+};
+
+/**
+ * xe_cpu_has_hybrid_flush_wa - detect a CPU affected by the hybrid
+ * scheduling latency issue
+ *
+ * Matches the running CPU against the set of Intel hybrid client CPUs (up to
+ * and including Arrow Lake) that are known to exhibit excessive workqueue
+ * worker scheduling latency. The workaround this feeds into is a host CPU
+ * property, not a GPU platform property, and applies regardless of which GPU
+ * (including a discrete GPU) is attached to the affected CPU.
+ *
+ * Return: %true if the current CPU is known to be affected, %false
+ * otherwise.
+ */
+bool xe_cpu_has_hybrid_flush_wa(void)
+{
+	return x86_match_cpu(hybrid_flush_wa_cpu_ids);
+}
+#else /* CONFIG_X86 */
+
+bool xe_cpu_has_hybrid_flush_wa(void)
+{
+	return false;
+}
+
+#endif /* CONFIG_X86 */
diff --git a/drivers/gpu/drm/xe/xe_cpu_info.h b/drivers/gpu/drm/xe/xe_cpu_info.h
new file mode 100644
index 000000000000..031e8a4096ee
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_cpu_info.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef _XE_CPU_INFO_H_
+#define _XE_CPU_INFO_H_
+
+#include <linux/types.h>
+
+bool xe_cpu_has_hybrid_flush_wa(void);
+
+#endif /* _XE_CPU_INFO_H_ */
diff --git a/drivers/gpu/drm/xe/xe_device.h b/drivers/gpu/drm/xe/xe_device.h
index a03760d0ce38..6fe9fcc80063 100644
--- a/drivers/gpu/drm/xe/xe_device.h
+++ b/drivers/gpu/drm/xe/xe_device.h
@@ -235,18 +235,35 @@ static inline bool xe_device_is_admin_only(const struct xe_device *xe)
 }
 #endif
 
-/*
+/**
+ * xe_device_has_flush_wa() - Whether the running host CPU needs the
+ * workqueue/work flush workaround
+ * @xe: xe device
+ *
  * Occasionally it is seen that the G2H worker starts running after a delay of more than
  * a second even after being queued and activated by the Linux workqueue subsystem. This
- * leads to G2H timeout error. The root cause of issue lies with scheduling latency of
- * Lunarlake Hybrid CPU. Issue disappears if we disable Lunarlake atom cores from BIOS
- * and this is beyond xe kmd.
+ * leads to G2H timeout errors. The root cause lies with the scheduling latency of Intel
+ * hybrid (Performance + Efficiency core) CPUs up to and including Arrow Lake, and is
+ * independent of which GPU is attached to the affected CPU -- a discrete GPU on an
+ * affected CPU can hit this just the same as an integrated one. Because of that, this
+ * cannot be scoped by xe->info.platform; xe->info.needs_flush_wa is set at probe time
+ * based on the actual host CPU.
+ *
+ * Return: %true if flush_workqueue()/flush_work() should be used to work around the
+ * scheduling latency, %false otherwise.
  *
- * TODO: Drop this change once workqueue scheduling delay issue is fixed on LNL Hybrid CPU.
+ * TODO: Drop this workaround once the workqueue scheduling delay issue is fixed on the
+ * affected hybrid CPUs.
  */
-#define LNL_FLUSH_WORKQUEUE(wq__) \
-	flush_workqueue(wq__)
-#define LNL_FLUSH_WORK(wrk__) \
-	flush_work(wrk__)
+static inline bool xe_device_has_flush_wa(struct xe_device *xe)
+{
+	return xe->info.needs_flush_wa;
+}
+
+#define LNL_FLUSH_WORKQUEUE(xe__, wq__) \
+	do { \
+		if (xe_device_has_flush_wa(xe__)) \
+			flush_workqueue(wq__); \
+	} while (0)
 
 #endif
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 860ad322237f..853a39579686 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -223,6 +223,15 @@ struct xe_device {
 		u8 skip_pcode:1;
 		/** @info.needs_shared_vf_gt_wq: needs shared GT WQ on VF */
 		u8 needs_shared_vf_gt_wq:1;
+		/**
+		 * @info.needs_flush_wa: Set if the host CPU is affected by a
+		 * scheduling latency issue that can delay workqueue worker
+		 * execution by more than a second. This is a property of the
+		 * host CPU (hybrid Performance + Efficiency core designs up
+		 * to and including Arrow Lake), not of the GPU platform, so
+		 * it must not be inferred from xe->info.platform.
+		 */
+		u8 needs_flush_wa:1;
 	} info;
 
 	/** @wa_active: keep track of active workarounds */
diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c b/drivers/gpu/drm/xe/xe_guc_ct.c
index fe70c0fd85c5..4555b9745a50 100644
--- a/drivers/gpu/drm/xe/xe_guc_ct.c
+++ b/drivers/gpu/drm/xe/xe_guc_ct.c
@@ -1135,6 +1135,11 @@ static void kick_reset(struct xe_guc_ct *ct)
 
 static int dequeue_one_g2h(struct xe_guc_ct *ct);
 
+static bool g2h_avail(struct xe_guc_ct *ct)
+{
+	return desc_read(ct_to_xe(ct), (&ct->ctbs.g2h), tail) != ct->ctbs.g2h.info.head;
+}
+
 /*
  * wait before retry of sending h2g message
  * Return: true if ready for retry, false if the wait timeouted
@@ -1176,12 +1181,9 @@ static bool guc_ct_send_wait_for_retry(struct xe_guc_ct *ct, u32 len,
 						 GUC_CTB_HXG_MSG_MAX_LEN :
 						 g2h_len);
 
-#define g2h_avail(ct)	\
-	(desc_read(ct_to_xe(ct), (&ct->ctbs.g2h), tail) != ct->ctbs.g2h.info.head)
 		if (!wait_event_timeout(ct->wq, !ct->g2h_outstanding ||
 					g2h_avail(ct), HZ))
 			return false;
-#undef g2h_avail
 
 		ret = dequeue_one_g2h(ct);
 		if (ret < 0) {
@@ -1377,7 +1379,7 @@ static int guc_ct_send_recv(struct xe_guc_ct *ct, const u32 *action, u32 len,
 wait_again:
 	ret = wait_event_timeout(ct->g2h_fence_wq, READ_ONCE(g2h_fence.done), HZ);
 	if (!ret) {
-		LNL_FLUSH_WORK(&ct->g2h_worker);
+		xe_guc_ct_flush_g2h_worker(ct);
 		if (READ_ONCE(g2h_fence.done)) {
 			xe_gt_warn(gt, "G2H fence %u, action %04x, done\n",
 				   g2h_fence.seqno, action[0]);
@@ -2020,8 +2022,19 @@ static void receive_g2h(struct xe_guc_ct *ct)
 	 * completing, creating a deadlock.
 	 */
 	ongoing = xe_pm_runtime_get_if_active(ct_to_xe(ct));
-	if (!ongoing && xe_pm_read_callback_task(ct_to_xe(ct)) == NULL)
+	if (!ongoing && xe_pm_read_callback_task(ct_to_xe(ct)) == NULL) {
+		/*
+		 * We were woken to process G2H (e.g. by an interrupt) but
+		 * couldn't get a runtime PM ref and aren't inside a PM
+		 * callback either. Any pending G2H will not be processed
+		 * until the next wake and, per the comment above, may be
+		 * lost entirely if we are fully suspended before then - warn
+		 * loudly so this isn't silently swallowed.
+		 */
+		xe_gt_warn(ct_to_gt(ct),
+			  "G2H worker woken w/o PM ref, dropping pending G2H\n");
 		return;
+	}
 
 	do {
 		mutex_lock(&ct->lock);
@@ -2046,6 +2059,39 @@ static void g2h_worker_func(struct work_struct *w)
 	receive_g2h(ct);
 }
 
+/**
+ * xe_guc_ct_flush_g2h_worker() - Flush the G2H worker, working around and
+ * detecting the hybrid CPU workqueue scheduling latency issue
+ * @ct: GuC CT object
+ *
+ * On CPUs affected by the hybrid P/E core scheduling latency issue (see
+ * xe_device_has_flush_wa()), flush_work() may be waiting on a worker that the
+ * workqueue subsystem has not actually scheduled to run yet. If the G2H ring
+ * buffer already has messages available (head != tail) but @ct->g2h_worker is
+ * neither queued nor running, that is exactly this scenario: warn loudly, as
+ * it means the WA is doing real work, and (re)queue the worker so
+ * flush_work() has something to wait on.
+ *
+ * There is no workqueue API to prove a work item's scheduling was actually
+ * delayed (as opposed to, e.g., not being queued at all for an unrelated
+ * reason), so this is only a best-effort detection, not a guarantee.
+ */
+void xe_guc_ct_flush_g2h_worker(struct xe_guc_ct *ct)
+{
+	struct xe_device *xe = ct_to_xe(ct);
+
+	if (!xe_device_has_flush_wa(xe))
+		return;
+
+	if (g2h_avail(ct) && !work_busy(&ct->g2h_worker)) {
+		xe_gt_warn(ct_to_gt(ct),
+			  "G2H worker not queued/running, CPU flush WA engaging\n");
+		queue_work(ct->g2h_wq, &ct->g2h_worker);
+	}
+
+	flush_work(&ct->g2h_worker);
+}
+
 static struct xe_guc_ct_snapshot *guc_ct_snapshot_alloc(struct xe_guc_ct *ct, bool atomic,
 							bool want_ctb)
 {
diff --git a/drivers/gpu/drm/xe/xe_guc_ct.h b/drivers/gpu/drm/xe/xe_guc_ct.h
index 767365a33dee..b8cfe1217cf8 100644
--- a/drivers/gpu/drm/xe/xe_guc_ct.h
+++ b/drivers/gpu/drm/xe/xe_guc_ct.h
@@ -22,6 +22,7 @@ void xe_guc_ct_runtime_suspend(struct xe_guc_ct *ct);
 void xe_guc_ct_stop(struct xe_guc_ct *ct);
 void xe_guc_ct_flush_and_stop(struct xe_guc_ct *ct);
 void xe_guc_ct_fast_path(struct xe_guc_ct *ct);
+void xe_guc_ct_flush_g2h_worker(struct xe_guc_ct *ct);
 
 struct xe_guc_ct_snapshot *xe_guc_ct_snapshot_capture(struct xe_guc_ct *ct);
 void xe_guc_ct_snapshot_print(struct xe_guc_ct_snapshot *snapshot, struct drm_printer *p);
diff --git a/drivers/gpu/drm/xe/xe_guc_tlb_inval.c b/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
index 046d0655122f..6047e7c44362 100644
--- a/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
+++ b/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
@@ -327,7 +327,7 @@ static void tlb_inval_flush(struct xe_tlb_inval *tlb_inval)
 {
 	struct xe_guc *guc = tlb_inval->private;
 
-	LNL_FLUSH_WORK(&guc->ct.g2h_worker);
+	xe_guc_ct_flush_g2h_worker(&guc->ct);
 }
 
 static long tlb_inval_timeout_delay(struct xe_tlb_inval *tlb_inval)
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 123ffd4c1ee9..4d6e1b544188 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -19,6 +19,7 @@
 #include "regs/xe_gt_regs.h"
 #include "regs/xe_regs.h"
 #include "xe_configfs.h"
+#include "xe_cpu_info.h"
 #include "xe_device.h"
 #include "xe_drv.h"
 #include "xe_gt.h"
@@ -820,6 +821,14 @@ static int xe_info_init_early(struct xe_device *xe,
 	xe->info.needs_shared_vf_gt_wq = desc->needs_shared_vf_gt_wq;
 	xe->info.multi_lrc_mask = desc->multi_lrc_mask;
 
+	/*
+	 * The hybrid P/E core scheduling latency workaround is a property of
+	 * the host CPU, not of the GPU platform: a CPU affected by it can be
+	 * paired with a discrete GPU, so this cannot be derived from
+	 * desc/platform.
+	 */
+	xe->info.needs_flush_wa = xe_cpu_has_hybrid_flush_wa();
+
 	xe->info.probe_display = IS_ENABLED(CONFIG_DRM_XE_DISPLAY) &&
 				 xe_modparam.probe_display &&
 				 desc->has_display &&
diff --git a/drivers/gpu/drm/xe/xe_tlb_inval.c b/drivers/gpu/drm/xe/xe_tlb_inval.c
index bbd21d393062..be12904cc65a 100644
--- a/drivers/gpu/drm/xe/xe_tlb_inval.c
+++ b/drivers/gpu/drm/xe/xe_tlb_inval.c
@@ -5,6 +5,7 @@
 
 #include <drm/drm_managed.h>
 
+#include "xe_device.h"
 #include "xe_device_types.h"
 #include "xe_force_wake.h"
 #include "xe_gt_stats.h"
@@ -73,10 +74,37 @@ static void xe_tlb_inval_fence_timeout(struct work_struct *work)
 	struct xe_device *xe = tlb_inval->xe;
 	struct xe_tlb_inval_fence *fence, *next;
 	long timeout_delay = tlb_inval->ops->timeout_delay(tlb_inval);
+	bool flush_wa = xe_device_has_flush_wa(xe);
+	unsigned int pending_before = 0;
+
+	if (flush_wa) {
+		spin_lock_irq(&tlb_inval->pending_lock);
+		list_for_each_entry(fence, &tlb_inval->pending_fences, link)
+			pending_before++;
+		spin_unlock_irq(&tlb_inval->pending_lock);
+	}
 
 	tlb_inval->ops->flush(tlb_inval);
 
 	spin_lock_irq(&tlb_inval->pending_lock);
+	if (flush_wa && pending_before) {
+		unsigned int pending_after = 0;
+
+		list_for_each_entry(fence, &tlb_inval->pending_fences, link)
+			pending_after++;
+
+		/*
+		 * If the flush forced by the hybrid CPU scheduling latency
+		 * workaround caused fences that were about to be reported as
+		 * timed out to be signaled instead, the underlying scheduling
+		 * delay this workaround papers over really did happen here.
+		 * Complain loudly so this doesn't go unnoticed.
+		 */
+		if (pending_after < pending_before)
+			drm_err(&xe->drm,
+				"CPU flush WA resolved %u pending TLB inval fence(s)\n",
+				pending_before - pending_after);
+	}
 	list_for_each_entry_safe(fence, next,
 				 &tlb_inval->pending_fences, link) {
 		s64 since_inval_ms = ktime_ms_delta(ktime_get(),
diff --git a/drivers/gpu/drm/xe/xe_wait_user_fence.c b/drivers/gpu/drm/xe/xe_wait_user_fence.c
index 51eb940ceb4e..ba29ad3840dc 100644
--- a/drivers/gpu/drm/xe/xe_wait_user_fence.c
+++ b/drivers/gpu/drm/xe/xe_wait_user_fence.c
@@ -154,11 +154,13 @@ int xe_wait_user_fence_ioctl(struct drm_device *dev, void *data,
 		}
 
 		if (!timeout) {
-			LNL_FLUSH_WORKQUEUE(xe->ordered_wq);
+			LNL_FLUSH_WORKQUEUE(xe, xe->ordered_wq);
 			err = do_compare(addr, args->value, args->mask,
 					 args->op);
 			if (err <= 0) {
-				drm_dbg(&xe->drm, "LNL_FLUSH_WORKQUEUE resolved ufence timeout\n");
+				if (xe_device_has_flush_wa(xe))
+					drm_warn(&xe->drm,
+						 "LNL_FLUSH_WORKQUEUE resolved ufence timeout\n");
 				break;
 			}
 			err = -ETIME;
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 6+ messages in thread

* [RFC PATCH 2/2] drm/xe: Add DRM_XE_DEBUG_FLUSH_WA to force the CPU flush workaround on
  2026-07-22 21:59 [RFC PATCH 0/2] LNL_FLUSH_* enhancements Matthew Brost
  2026-07-22 21:59 ` [RFC PATCH 1/2] drm/xe: Scope LNL_FLUSH_* workaround to affected CPUs, not GPU platform Matthew Brost
@ 2026-07-22 21:59 ` Matthew Brost
  2026-07-22 23:45 ` ✗ CI.checkpatch: warning for LNL_FLUSH_* enhancements Patchwork
                   ` (2 subsequent siblings)
  4 siblings, 0 replies; 6+ messages in thread
From: Matthew Brost @ 2026-07-22 21:59 UTC (permalink / raw)
  To: intel-xe; +Cc: Tales A . Mendonça

Add a DRM_XE_DEBUG_FLUSH_WA debug Kconfig option, depending on
DRM_XE_DEBUG, that unconditionally forces xe->info.needs_flush_wa on
regardless of the detected host CPU. This lets driver developers
exercise the LNL_FLUSH_WORKQUEUE()/xe_guc_ct_flush_g2h_worker() code
paths (including the new best-effort scheduling-delay detection and
warnings) on CPUs that aren't otherwise affected.

Cc: Tales A. Mendonça <talesam@gmail.com>
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Assisted-by: GitHub Copilot:claude-sonnet-5
---
 drivers/gpu/drm/xe/Kconfig.debug     | 16 ++++++++++++++++
 drivers/gpu/drm/xe/xe_device_types.h |  3 ++-
 drivers/gpu/drm/xe/xe_pci.c          |  3 ++-
 3 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/Kconfig.debug b/drivers/gpu/drm/xe/Kconfig.debug
index 01227c77f6d7..f0332e061453 100644
--- a/drivers/gpu/drm/xe/Kconfig.debug
+++ b/drivers/gpu/drm/xe/Kconfig.debug
@@ -112,3 +112,19 @@ config DRM_XE_USERPTR_INVAL_INJECT
 
 	 Recommended for driver developers only.
 	 If in doubt, say "N".
+
+config DRM_XE_DEBUG_FLUSH_WA
+	bool "Force enable the workqueue/work flush scheduling latency workaround"
+	depends on DRM_XE_DEBUG
+	default n
+	help
+	  Unconditionally enable the workaround for the workqueue/work
+	  scheduling latency issue seen on some Intel hybrid
+	  (Performance + Efficiency core) client CPUs (see
+	  xe_device_has_flush_wa()), regardless of the host CPU actually
+	  running the driver. Useful for exercising/debugging the
+	  workaround's code paths on CPUs that aren't otherwise affected.
+
+	  Recommended for driver developers only.
+
+	  If in doubt, say "N".
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 853a39579686..2dfdce200be7 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -229,7 +229,8 @@ struct xe_device {
 		 * execution by more than a second. This is a property of the
 		 * host CPU (hybrid Performance + Efficiency core designs up
 		 * to and including Arrow Lake), not of the GPU platform, so
-		 * it must not be inferred from xe->info.platform.
+		 * it must not be inferred from xe->info.platform. Forced on
+		 * unconditionally when CONFIG_DRM_XE_DEBUG_FLUSH_WA=y.
 		 */
 		u8 needs_flush_wa:1;
 	} info;
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 4d6e1b544188..ff04e37dbea9 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -827,7 +827,8 @@ static int xe_info_init_early(struct xe_device *xe,
 	 * paired with a discrete GPU, so this cannot be derived from
 	 * desc/platform.
 	 */
-	xe->info.needs_flush_wa = xe_cpu_has_hybrid_flush_wa();
+	xe->info.needs_flush_wa = IS_ENABLED(CONFIG_DRM_XE_DEBUG_FLUSH_WA) ||
+		xe_cpu_has_hybrid_flush_wa();
 
 	xe->info.probe_display = IS_ENABLED(CONFIG_DRM_XE_DISPLAY) &&
 				 xe_modparam.probe_display &&
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 6+ messages in thread

* ✗ CI.checkpatch: warning for LNL_FLUSH_* enhancements
  2026-07-22 21:59 [RFC PATCH 0/2] LNL_FLUSH_* enhancements Matthew Brost
  2026-07-22 21:59 ` [RFC PATCH 1/2] drm/xe: Scope LNL_FLUSH_* workaround to affected CPUs, not GPU platform Matthew Brost
  2026-07-22 21:59 ` [RFC PATCH 2/2] drm/xe: Add DRM_XE_DEBUG_FLUSH_WA to force the CPU flush workaround on Matthew Brost
@ 2026-07-22 23:45 ` Patchwork
  2026-07-22 23:46 ` ✓ CI.KUnit: success " Patchwork
  2026-07-23  0:20 ` ✓ Xe.CI.BAT: " Patchwork
  4 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2026-07-22 23:45 UTC (permalink / raw)
  To: Matthew Brost; +Cc: intel-xe

== Series Details ==

Series: LNL_FLUSH_* enhancements
URL   : https://patchwork.freedesktop.org/series/170939/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
061140b9bc586ae7f40abc1249c97e1cc72d1b9d
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 89dd63e4a198e087671b347d7471084fc60f2e9b
Author: Matthew Brost <matthew.brost@intel.com>
Date:   Wed Jul 22 14:59:35 2026 -0700

    drm/xe: Add DRM_XE_DEBUG_FLUSH_WA to force the CPU flush workaround on
    
    Add a DRM_XE_DEBUG_FLUSH_WA debug Kconfig option, depending on
    DRM_XE_DEBUG, that unconditionally forces xe->info.needs_flush_wa on
    regardless of the detected host CPU. This lets driver developers
    exercise the LNL_FLUSH_WORKQUEUE()/xe_guc_ct_flush_g2h_worker() code
    paths (including the new best-effort scheduling-delay detection and
    warnings) on CPUs that aren't otherwise affected.
    
    Cc: Tales A. Mendonça <talesam@gmail.com>
    Signed-off-by: Matthew Brost <matthew.brost@intel.com>
    Assisted-by: GitHub Copilot:claude-sonnet-5
+ /mt/dim checkpatch aff95d2d4b516f1618e3fb1cdb5850b6e1b19bb9 drm-intel
2e593f65da22 drm/xe: Scope LNL_FLUSH_* workaround to affected CPUs, not GPU platform
-:45: WARNING:BAD_SIGN_OFF: Assisted-by expects 'AGENT_NAME:MODEL_VERSION [TOOL1] [TOOL2]' format
#45: 
Assisted-by: GitHub Copilot:claude-sonnet-5

-:60: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#60: 
new file mode 100644

-:263: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "!xe_pm_read_callback_task"
#263: FILE: drivers/gpu/drm/xe/xe_guc_ct.c:2025:
+	if (!ongoing && xe_pm_read_callback_task(ct_to_xe(ct)) == NULL) {

-:273: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#273: FILE: drivers/gpu/drm/xe/xe_guc_ct.c:2035:
+		xe_gt_warn(ct_to_gt(ct),
+			  "G2H worker woken w/o PM ref, dropping pending G2H\n");

-:309: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#309: FILE: drivers/gpu/drm/xe/xe_guc_ct.c:2088:
+		xe_gt_warn(ct_to_gt(ct),
+			  "G2H worker not queued/running, CPU flush WA engaging\n");

total: 0 errors, 2 warnings, 3 checks, 331 lines checked
89dd63e4a198 drm/xe: Add DRM_XE_DEBUG_FLUSH_WA to force the CPU flush workaround on
-:19: WARNING:BAD_SIGN_OFF: Assisted-by expects 'AGENT_NAME:MODEL_VERSION [TOOL1] [TOOL2]' format
#19: 
Assisted-by: GitHub Copilot:claude-sonnet-5

total: 0 errors, 1 warnings, 0 checks, 37 lines checked



^ permalink raw reply	[flat|nested] 6+ messages in thread

* ✓ CI.KUnit: success for LNL_FLUSH_* enhancements
  2026-07-22 21:59 [RFC PATCH 0/2] LNL_FLUSH_* enhancements Matthew Brost
                   ` (2 preceding siblings ...)
  2026-07-22 23:45 ` ✗ CI.checkpatch: warning for LNL_FLUSH_* enhancements Patchwork
@ 2026-07-22 23:46 ` Patchwork
  2026-07-23  0:20 ` ✓ Xe.CI.BAT: " Patchwork
  4 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2026-07-22 23:46 UTC (permalink / raw)
  To: Matthew Brost; +Cc: intel-xe

== Series Details ==

Series: LNL_FLUSH_* enhancements
URL   : https://patchwork.freedesktop.org/series/170939/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[23:45:15] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[23:45:19] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[23:45:51] Starting KUnit Kernel (1/1)...
[23:45:51] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[23:45:51] ================== guc_buf (11 subtests) ===================
[23:45:51] [PASSED] test_smallest
[23:45:51] [PASSED] test_largest
[23:45:51] [PASSED] test_granular
[23:45:51] [PASSED] test_unique
[23:45:51] [PASSED] test_overlap
[23:45:51] [PASSED] test_reusable
[23:45:51] [PASSED] test_too_big
[23:45:51] [PASSED] test_flush
[23:45:51] [PASSED] test_lookup
[23:45:51] [PASSED] test_data
[23:45:51] [PASSED] test_class
[23:45:51] ===================== [PASSED] guc_buf =====================
[23:45:51] =================== guc_dbm (7 subtests) ===================
[23:45:51] [PASSED] test_empty
[23:45:51] [PASSED] test_default
[23:45:51] ======================== test_size  ========================
[23:45:51] [PASSED] 4
[23:45:51] [PASSED] 8
[23:45:51] [PASSED] 32
[23:45:51] [PASSED] 256
[23:45:51] ==================== [PASSED] test_size ====================
[23:45:51] ======================= test_reuse  ========================
[23:45:51] [PASSED] 4
[23:45:51] [PASSED] 8
[23:45:51] [PASSED] 32
[23:45:51] [PASSED] 256
[23:45:51] =================== [PASSED] test_reuse ====================
[23:45:51] =================== test_range_overlap  ====================
[23:45:51] [PASSED] 4
[23:45:51] [PASSED] 8
[23:45:51] [PASSED] 32
[23:45:51] [PASSED] 256
[23:45:51] =============== [PASSED] test_range_overlap ================
[23:45:51] =================== test_range_compact  ====================
[23:45:51] [PASSED] 4
[23:45:51] [PASSED] 8
[23:45:51] [PASSED] 32
[23:45:51] [PASSED] 256
[23:45:51] =============== [PASSED] test_range_compact ================
[23:45:51] ==================== test_range_spare  =====================
[23:45:51] [PASSED] 4
[23:45:51] [PASSED] 8
[23:45:51] [PASSED] 32
[23:45:51] [PASSED] 256
[23:45:51] ================ [PASSED] test_range_spare =================
[23:45:51] ===================== [PASSED] guc_dbm =====================
[23:45:51] =================== guc_idm (6 subtests) ===================
[23:45:51] [PASSED] bad_init
[23:45:51] [PASSED] no_init
[23:45:51] [PASSED] init_fini
[23:45:51] [PASSED] check_used
[23:45:51] [PASSED] check_quota
[23:45:51] [PASSED] check_all
[23:45:51] ===================== [PASSED] guc_idm =====================
[23:45:51] =============== guc_klv_helpers (9 subtests) ===============
[23:45:51] [PASSED] test_count
[23:45:51] [PASSED] test_encode_u32
[23:45:51] [PASSED] test_encode_u64
[23:45:51] [PASSED] test_encode_string
[23:45:51] [PASSED] test_encode_object_raw
[23:45:51] [PASSED] test_encode_object_klv
[23:45:51] [PASSED] test_encode_object_nested
[23:45:51] [PASSED] test_encode_object_basic
[23:45:51] [PASSED] test_print
[23:45:51] ================= [PASSED] guc_klv_helpers =================
[23:45:51] ================== no_relay (3 subtests) ===================
[23:45:51] [PASSED] xe_drops_guc2pf_if_not_ready
[23:45:51] [PASSED] xe_drops_guc2vf_if_not_ready
[23:45:51] [PASSED] xe_rejects_send_if_not_ready
[23:45:51] ==================== [PASSED] no_relay =====================
[23:45:51] ================== pf_relay (14 subtests) ==================
[23:45:51] [PASSED] pf_rejects_guc2pf_too_short
[23:45:51] [PASSED] pf_rejects_guc2pf_too_long
[23:45:51] [PASSED] pf_rejects_guc2pf_no_payload
[23:45:51] [PASSED] pf_fails_no_payload
[23:45:51] [PASSED] pf_fails_bad_origin
[23:45:51] [PASSED] pf_fails_bad_type
[23:45:51] [PASSED] pf_txn_reports_error
[23:45:51] [PASSED] pf_txn_sends_pf2guc
[23:45:51] [PASSED] pf_sends_pf2guc
[23:45:51] [SKIPPED] pf_loopback_nop (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[23:45:51] [SKIPPED] pf_loopback_echo (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[23:45:51] [SKIPPED] pf_loopback_fail (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[23:45:51] [SKIPPED] pf_loopback_busy (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[23:45:51] [SKIPPED] pf_loopback_retry (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[23:45:51] ==================== [PASSED] pf_relay =====================
[23:45:51] ================== vf_relay (3 subtests) ===================
[23:45:51] [PASSED] vf_rejects_guc2vf_too_short
[23:45:51] [PASSED] vf_rejects_guc2vf_too_long
[23:45:51] [PASSED] vf_rejects_guc2vf_no_payload
[23:45:51] ==================== [PASSED] vf_relay =====================
[23:45:51] ================ pf_gt_config (9 subtests) =================
[23:45:51] [PASSED] fair_contexts_1vf
[23:45:51] [PASSED] fair_doorbells_1vf
[23:45:51] [PASSED] fair_ggtt_1vf
[23:45:51] ====================== fair_vram_1vf  ======================
[23:45:51] [PASSED] 3.50 GiB
[23:45:51] [PASSED] 11.5 GiB
[23:45:51] [PASSED] 15.5 GiB
[23:45:51] [PASSED] 31.5 GiB
[23:45:51] [PASSED] 63.5 GiB
[23:45:51] [PASSED] 1.91 GiB
[23:45:51] ================== [PASSED] fair_vram_1vf ==================
[23:45:51] ================ fair_vram_1vf_admin_only  =================
[23:45:51] [PASSED] 3.50 GiB
[23:45:51] [PASSED] 11.5 GiB
[23:45:51] [PASSED] 15.5 GiB
[23:45:51] [PASSED] 31.5 GiB
[23:45:51] [PASSED] 63.5 GiB
[23:45:51] [PASSED] 1.91 GiB
[23:45:51] ============ [PASSED] fair_vram_1vf_admin_only =============
[23:45:51] ====================== fair_contexts  ======================
[23:45:51] [PASSED] 1 VF
[23:45:51] [PASSED] 2 VFs
[23:45:51] [PASSED] 3 VFs
[23:45:51] [PASSED] 4 VFs
[23:45:51] [PASSED] 5 VFs
[23:45:51] [PASSED] 6 VFs
[23:45:51] [PASSED] 7 VFs
[23:45:51] [PASSED] 8 VFs
[23:45:51] [PASSED] 9 VFs
[23:45:51] [PASSED] 10 VFs
[23:45:51] [PASSED] 11 VFs
[23:45:51] [PASSED] 12 VFs
[23:45:51] [PASSED] 13 VFs
[23:45:51] [PASSED] 14 VFs
[23:45:51] [PASSED] 15 VFs
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[23:45:51] [PASSED] 17 VFs
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[23:45:51] [PASSED] 35 VFs
[23:45:51] [PASSED] 36 VFs
[23:45:51] [PASSED] 37 VFs
[23:45:51] [PASSED] 38 VFs
[23:45:51] [PASSED] 39 VFs
[23:45:51] [PASSED] 40 VFs
[23:45:51] [PASSED] 41 VFs
[23:45:51] [PASSED] 42 VFs
[23:45:51] [PASSED] 43 VFs
[23:45:51] [PASSED] 44 VFs
[23:45:51] [PASSED] 45 VFs
[23:45:51] [PASSED] 46 VFs
[23:45:51] [PASSED] 47 VFs
[23:45:51] [PASSED] 48 VFs
[23:45:51] [PASSED] 49 VFs
[23:45:51] [PASSED] 50 VFs
[23:45:51] [PASSED] 51 VFs
[23:45:51] [PASSED] 52 VFs
[23:45:51] [PASSED] 53 VFs
[23:45:51] [PASSED] 54 VFs
[23:45:51] [PASSED] 55 VFs
[23:45:51] [PASSED] 56 VFs
[23:45:51] [PASSED] 57 VFs
[23:45:51] [PASSED] 58 VFs
[23:45:51] [PASSED] 59 VFs
[23:45:51] [PASSED] 60 VFs
[23:45:51] [PASSED] 61 VFs
[23:45:51] [PASSED] 62 VFs
[23:45:51] [PASSED] 63 VFs
[23:45:51] ================== [PASSED] fair_contexts ==================
[23:45:51] ===================== fair_doorbells  ======================
[23:45:51] [PASSED] 1 VF
[23:45:51] [PASSED] 2 VFs
[23:45:51] [PASSED] 3 VFs
[23:45:51] [PASSED] 4 VFs
[23:45:51] [PASSED] 5 VFs
[23:45:51] [PASSED] 6 VFs
[23:45:51] [PASSED] 7 VFs
[23:45:51] [PASSED] 8 VFs
[23:45:51] [PASSED] 9 VFs
[23:45:51] [PASSED] 10 VFs
[23:45:51] [PASSED] 11 VFs
[23:45:51] [PASSED] 12 VFs
[23:45:51] [PASSED] 13 VFs
[23:45:51] [PASSED] 14 VFs
[23:45:51] [PASSED] 15 VFs
[23:45:51] [PASSED] 16 VFs
[23:45:51] [PASSED] 17 VFs
[23:45:51] [PASSED] 18 VFs
[23:45:51] [PASSED] 19 VFs
[23:45:51] [PASSED] 20 VFs
[23:45:51] [PASSED] 21 VFs
[23:45:51] [PASSED] 22 VFs
[23:45:51] [PASSED] 23 VFs
[23:45:51] [PASSED] 24 VFs
[23:45:51] [PASSED] 25 VFs
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[23:45:51] [PASSED] 27 VFs
[23:45:51] [PASSED] 28 VFs
[23:45:51] [PASSED] 29 VFs
[23:45:51] [PASSED] 30 VFs
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[23:45:51] [PASSED] 32 VFs
[23:45:51] [PASSED] 33 VFs
[23:45:51] [PASSED] 34 VFs
[23:45:51] [PASSED] 35 VFs
[23:45:51] [PASSED] 36 VFs
[23:45:51] [PASSED] 37 VFs
[23:45:51] [PASSED] 38 VFs
[23:45:51] [PASSED] 39 VFs
[23:45:51] [PASSED] 40 VFs
[23:45:51] [PASSED] 41 VFs
[23:45:51] [PASSED] 42 VFs
[23:45:51] [PASSED] 43 VFs
[23:45:51] [PASSED] 44 VFs
[23:45:51] [PASSED] 45 VFs
[23:45:51] [PASSED] 46 VFs
[23:45:51] [PASSED] 47 VFs
[23:45:51] [PASSED] 48 VFs
[23:45:51] [PASSED] 49 VFs
[23:45:51] [PASSED] 50 VFs
[23:45:51] [PASSED] 51 VFs
[23:45:51] [PASSED] 52 VFs
[23:45:51] [PASSED] 53 VFs
[23:45:51] [PASSED] 54 VFs
[23:45:51] [PASSED] 55 VFs
[23:45:51] [PASSED] 56 VFs
[23:45:51] [PASSED] 57 VFs
[23:45:51] [PASSED] 58 VFs
[23:45:51] [PASSED] 59 VFs
[23:45:51] [PASSED] 60 VFs
[23:45:51] [PASSED] 61 VFs
[23:45:51] [PASSED] 62 VFs
[23:45:51] [PASSED] 63 VFs
[23:45:51] ================= [PASSED] fair_doorbells ==================
[23:45:51] ======================== fair_ggtt  ========================
[23:45:51] [PASSED] 1 VF
[23:45:51] [PASSED] 2 VFs
[23:45:51] [PASSED] 3 VFs
[23:45:51] [PASSED] 4 VFs
[23:45:51] [PASSED] 5 VFs
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[23:45:51] [PASSED] 33 VFs
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[23:45:51] [PASSED] 42 VFs
[23:45:51] [PASSED] 43 VFs
[23:45:51] [PASSED] 44 VFs
[23:45:51] [PASSED] 45 VFs
[23:45:51] [PASSED] 46 VFs
[23:45:51] [PASSED] 47 VFs
[23:45:51] [PASSED] 48 VFs
[23:45:51] [PASSED] 49 VFs
[23:45:51] [PASSED] 50 VFs
[23:45:51] [PASSED] 51 VFs
[23:45:51] [PASSED] 52 VFs
[23:45:51] [PASSED] 53 VFs
[23:45:51] [PASSED] 54 VFs
[23:45:51] [PASSED] 55 VFs
[23:45:51] [PASSED] 56 VFs
[23:45:51] [PASSED] 57 VFs
[23:45:51] [PASSED] 58 VFs
[23:45:51] [PASSED] 59 VFs
[23:45:51] [PASSED] 60 VFs
[23:45:51] [PASSED] 61 VFs
[23:45:51] [PASSED] 62 VFs
[23:45:51] [PASSED] 63 VFs
[23:45:51] ==================== [PASSED] fair_ggtt ====================
[23:45:51] ======================== fair_vram  ========================
[23:45:51] [PASSED] 1 VF
[23:45:51] [PASSED] 2 VFs
[23:45:51] [PASSED] 3 VFs
[23:45:51] [PASSED] 4 VFs
[23:45:51] [PASSED] 5 VFs
[23:45:51] [PASSED] 6 VFs
[23:45:51] [PASSED] 7 VFs
[23:45:51] [PASSED] 8 VFs
[23:45:51] [PASSED] 9 VFs
[23:45:51] [PASSED] 10 VFs
[23:45:51] [PASSED] 11 VFs
[23:45:51] [PASSED] 12 VFs
[23:45:51] [PASSED] 13 VFs
[23:45:51] [PASSED] 14 VFs
[23:45:51] [PASSED] 15 VFs
[23:45:51] [PASSED] 16 VFs
[23:45:51] [PASSED] 17 VFs
[23:45:51] [PASSED] 18 VFs
[23:45:51] [PASSED] 19 VFs
[23:45:51] [PASSED] 20 VFs
[23:45:51] [PASSED] 21 VFs
[23:45:51] [PASSED] 22 VFs
[23:45:51] [PASSED] 23 VFs
[23:45:51] [PASSED] 24 VFs
[23:45:51] [PASSED] 25 VFs
[23:45:51] [PASSED] 26 VFs
[23:45:51] [PASSED] 27 VFs
[23:45:51] [PASSED] 28 VFs
[23:45:51] [PASSED] 29 VFs
[23:45:51] [PASSED] 30 VFs
[23:45:51] [PASSED] 31 VFs
[23:45:51] [PASSED] 32 VFs
[23:45:51] [PASSED] 33 VFs
[23:45:51] [PASSED] 34 VFs
[23:45:51] [PASSED] 35 VFs
[23:45:51] [PASSED] 36 VFs
[23:45:51] [PASSED] 37 VFs
[23:45:51] [PASSED] 38 VFs
[23:45:51] [PASSED] 39 VFs
[23:45:51] [PASSED] 40 VFs
[23:45:51] [PASSED] 41 VFs
[23:45:51] [PASSED] 42 VFs
[23:45:51] [PASSED] 43 VFs
[23:45:51] [PASSED] 44 VFs
[23:45:51] [PASSED] 45 VFs
[23:45:51] [PASSED] 46 VFs
[23:45:51] [PASSED] 47 VFs
[23:45:51] [PASSED] 48 VFs
[23:45:51] [PASSED] 49 VFs
[23:45:51] [PASSED] 50 VFs
[23:45:51] [PASSED] 51 VFs
[23:45:51] [PASSED] 52 VFs
[23:45:51] [PASSED] 53 VFs
[23:45:51] [PASSED] 54 VFs
[23:45:51] [PASSED] 55 VFs
[23:45:51] [PASSED] 56 VFs
[23:45:51] [PASSED] 57 VFs
[23:45:51] [PASSED] 58 VFs
[23:45:51] [PASSED] 59 VFs
[23:45:51] [PASSED] 60 VFs
[23:45:51] [PASSED] 61 VFs
[23:45:51] [PASSED] 62 VFs
[23:45:51] [PASSED] 63 VFs
[23:45:51] ==================== [PASSED] fair_vram ====================
[23:45:51] ================== [PASSED] pf_gt_config ===================
[23:45:51] ===================== lmtt (1 subtest) =====================
[23:45:51] ======================== test_ops  =========================
[23:45:51] [PASSED] 2-level
[23:45:51] [PASSED] multi-level
[23:45:51] ==================== [PASSED] test_ops =====================
[23:45:51] ====================== [PASSED] lmtt =======================
[23:45:51] ================= sriov_packet (1 subtest) =================
[23:45:51] [PASSED] test_descriptor_init
[23:45:51] ================== [PASSED] sriov_packet ===================
[23:45:51] ================= pf_service (11 subtests) =================
[23:45:51] [PASSED] pf_negotiate_any
[23:45:51] [PASSED] pf_negotiate_base_match
[23:45:51] [PASSED] pf_negotiate_base_newer
[23:45:51] [PASSED] pf_negotiate_base_next
[23:45:51] [SKIPPED] pf_negotiate_base_older (no older minor)
[23:45:51] [PASSED] pf_negotiate_base_prev
[23:45:51] [PASSED] pf_negotiate_latest_match
[23:45:51] [PASSED] pf_negotiate_latest_newer
[23:45:51] [PASSED] pf_negotiate_latest_next
[23:45:51] [SKIPPED] pf_negotiate_latest_older (no older minor)
[23:45:51] [SKIPPED] pf_negotiate_latest_prev (no prev major)
[23:45:51] =================== [PASSED] pf_service ====================
[23:45:51] ================= xe_guc_g2g (2 subtests) ==================
[23:45:51] ============== xe_live_guc_g2g_kunit_default  ==============
[23:45:51] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[23:45:51] ============== xe_live_guc_g2g_kunit_allmem  ===============
[23:45:51] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[23:45:51] =================== [SKIPPED] xe_guc_g2g ===================
[23:45:51] =================== xe_mocs (2 subtests) ===================
[23:45:51] ================ xe_live_mocs_kernel_kunit  ================
[23:45:51] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[23:45:51] ================ xe_live_mocs_reset_kunit  =================
[23:45:51] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[23:45:51] ==================== [SKIPPED] xe_mocs =====================
[23:45:51] ================= xe_migrate (2 subtests) ==================
[23:45:51] ================= xe_migrate_sanity_kunit  =================
[23:45:51] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[23:45:51] ================== xe_validate_ccs_kunit  ==================
[23:45:51] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[23:45:51] =================== [SKIPPED] xe_migrate ===================
[23:45:51] ================== xe_dma_buf (1 subtest) ==================
[23:45:51] ==================== xe_dma_buf_kunit  =====================
[23:45:51] ================ [SKIPPED] xe_dma_buf_kunit ================
[23:45:51] =================== [SKIPPED] xe_dma_buf ===================
[23:45:51] ================= xe_bo_shrink (1 subtest) =================
[23:45:51] =================== xe_bo_shrink_kunit  ====================
[23:45:51] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[23:45:51] ================== [SKIPPED] xe_bo_shrink ==================
[23:45:51] ==================== xe_bo (2 subtests) ====================
[23:45:51] ================== xe_ccs_migrate_kunit  ===================
[23:45:51] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[23:45:51] ==================== xe_bo_evict_kunit  ====================
[23:45:51] =============== [SKIPPED] xe_bo_evict_kunit ================
[23:45:51] ===================== [SKIPPED] xe_bo ======================
[23:45:51] ==================== args (13 subtests) ====================
[23:45:51] [PASSED] count_args_test
[23:45:51] [PASSED] call_args_example
[23:45:51] [PASSED] call_args_test
[23:45:51] [PASSED] drop_first_arg_example
[23:45:51] [PASSED] drop_first_arg_test
[23:45:51] [PASSED] first_arg_example
[23:45:51] [PASSED] first_arg_test
[23:45:51] [PASSED] last_arg_example
[23:45:51] [PASSED] last_arg_test
[23:45:51] [PASSED] pick_arg_example
[23:45:51] [PASSED] if_args_example
[23:45:51] [PASSED] if_args_test
[23:45:51] [PASSED] sep_comma_example
[23:45:51] ====================== [PASSED] args =======================
[23:45:51] =================== xe_pci (3 subtests) ====================
[23:45:51] ==================== check_graphics_ip  ====================
[23:45:51] [PASSED] 12.00 Xe_LP
[23:45:51] [PASSED] 12.10 Xe_LP+
[23:45:51] [PASSED] 12.55 Xe_HPG
[23:45:51] [PASSED] 12.60 Xe_HPC
[23:45:51] [PASSED] 12.70 Xe_LPG
[23:45:51] [PASSED] 12.71 Xe_LPG
[23:45:51] [PASSED] 12.74 Xe_LPG+
[23:45:51] [PASSED] 20.01 Xe2_HPG
[23:45:51] [PASSED] 20.02 Xe2_HPG
[23:45:51] [PASSED] 20.04 Xe2_LPG
[23:45:51] [PASSED] 30.00 Xe3_LPG
[23:45:51] [PASSED] 30.01 Xe3_LPG
[23:45:51] [PASSED] 30.03 Xe3_LPG
[23:45:51] [PASSED] 30.04 Xe3_LPG
[23:45:51] [PASSED] 30.05 Xe3_LPG
[23:45:51] [PASSED] 35.10 Xe3p_LPG
[23:45:51] [PASSED] 35.11 Xe3p_XPC
[23:45:51] ================ [PASSED] check_graphics_ip ================
[23:45:51] ===================== check_media_ip  ======================
[23:45:51] [PASSED] 12.00 Xe_M
[23:45:51] [PASSED] 12.55 Xe_HPM
[23:45:51] [PASSED] 13.00 Xe_LPM+
[23:45:51] [PASSED] 13.01 Xe2_HPM
[23:45:51] [PASSED] 20.00 Xe2_LPM
[23:45:51] [PASSED] 30.00 Xe3_LPM
[23:45:51] [PASSED] 30.02 Xe3_LPM
[23:45:51] [PASSED] 35.00 Xe3p_LPM
[23:45:51] [PASSED] 35.03 Xe3p_HPM
[23:45:51] ================= [PASSED] check_media_ip ==================
[23:45:51] =================== check_platform_desc  ===================
[23:45:51] [PASSED] 0x9A60 (TIGERLAKE)
[23:45:51] [PASSED] 0x9A68 (TIGERLAKE)
[23:45:51] [PASSED] 0x9A70 (TIGERLAKE)
[23:45:51] [PASSED] 0x9A40 (TIGERLAKE)
[23:45:51] [PASSED] 0x9A49 (TIGERLAKE)
[23:45:51] [PASSED] 0x9A59 (TIGERLAKE)
[23:45:51] [PASSED] 0x9A78 (TIGERLAKE)
[23:45:51] [PASSED] 0x9AC0 (TIGERLAKE)
[23:45:51] [PASSED] 0x9AC9 (TIGERLAKE)
[23:45:51] [PASSED] 0x9AD9 (TIGERLAKE)
[23:45:51] [PASSED] 0x9AF8 (TIGERLAKE)
[23:45:51] [PASSED] 0x4C80 (ROCKETLAKE)
[23:45:51] [PASSED] 0x4C8A (ROCKETLAKE)
[23:45:51] [PASSED] 0x4C8B (ROCKETLAKE)
[23:45:51] [PASSED] 0x4C8C (ROCKETLAKE)
[23:45:51] [PASSED] 0x4C90 (ROCKETLAKE)
[23:45:51] [PASSED] 0x4C9A (ROCKETLAKE)
[23:45:51] [PASSED] 0x4680 (ALDERLAKE_S)
[23:45:51] [PASSED] 0x4682 (ALDERLAKE_S)
[23:45:51] [PASSED] 0x4688 (ALDERLAKE_S)
[23:45:51] [PASSED] 0x468A (ALDERLAKE_S)
[23:45:51] [PASSED] 0x468B (ALDERLAKE_S)
[23:45:51] [PASSED] 0x4690 (ALDERLAKE_S)
[23:45:51] [PASSED] 0x4692 (ALDERLAKE_S)
[23:45:51] [PASSED] 0x4693 (ALDERLAKE_S)
[23:45:51] [PASSED] 0x46A0 (ALDERLAKE_P)
[23:45:51] [PASSED] 0x46A1 (ALDERLAKE_P)
[23:45:51] [PASSED] 0x46A2 (ALDERLAKE_P)
[23:45:51] [PASSED] 0x46A3 (ALDERLAKE_P)
[23:45:51] [PASSED] 0x46A6 (ALDERLAKE_P)
[23:45:51] [PASSED] 0x46A8 (ALDERLAKE_P)
[23:45:51] [PASSED] 0x46AA (ALDERLAKE_P)
[23:45:51] [PASSED] 0x462A (ALDERLAKE_P)
[23:45:51] [PASSED] 0x4626 (ALDERLAKE_P)
[23:45:51] [PASSED] 0x4628 (ALDERLAKE_P)
[23:45:51] [PASSED] 0x46B0 (ALDERLAKE_P)
[23:45:51] [PASSED] 0x46B1 (ALDERLAKE_P)
[23:45:51] [PASSED] 0x46B2 (ALDERLAKE_P)
[23:45:51] [PASSED] 0x46B3 (ALDERLAKE_P)
[23:45:51] [PASSED] 0x46C0 (ALDERLAKE_P)
[23:45:51] [PASSED] 0x46C1 (ALDERLAKE_P)
[23:45:51] [PASSED] 0x46C2 (ALDERLAKE_P)
[23:45:51] [PASSED] 0x46C3 (ALDERLAKE_P)
[23:45:51] [PASSED] 0x46D0 (ALDERLAKE_N)
[23:45:51] [PASSED] 0x46D1 (ALDERLAKE_N)
[23:45:51] [PASSED] 0x46D2 (ALDERLAKE_N)
[23:45:51] [PASSED] 0x46D3 (ALDERLAKE_N)
[23:45:51] [PASSED] 0x46D4 (ALDERLAKE_N)
[23:45:51] [PASSED] 0xA721 (ALDERLAKE_P)
[23:45:51] [PASSED] 0xA7A1 (ALDERLAKE_P)
[23:45:51] [PASSED] 0xA7A9 (ALDERLAKE_P)
[23:45:51] [PASSED] 0xA7AC (ALDERLAKE_P)
[23:45:51] [PASSED] 0xA7AD (ALDERLAKE_P)
[23:45:51] [PASSED] 0xA720 (ALDERLAKE_P)
[23:45:51] [PASSED] 0xA7A0 (ALDERLAKE_P)
[23:45:51] [PASSED] 0xA7A8 (ALDERLAKE_P)
[23:45:51] [PASSED] 0xA7AA (ALDERLAKE_P)
[23:45:51] [PASSED] 0xA7AB (ALDERLAKE_P)
[23:45:51] [PASSED] 0xA780 (ALDERLAKE_S)
[23:45:51] [PASSED] 0xA781 (ALDERLAKE_S)
[23:45:51] [PASSED] 0xA782 (ALDERLAKE_S)
[23:45:51] [PASSED] 0xA783 (ALDERLAKE_S)
[23:45:51] [PASSED] 0xA788 (ALDERLAKE_S)
[23:45:51] [PASSED] 0xA789 (ALDERLAKE_S)
[23:45:51] [PASSED] 0xA78A (ALDERLAKE_S)
[23:45:51] [PASSED] 0xA78B (ALDERLAKE_S)
[23:45:51] [PASSED] 0x4905 (DG1)
[23:45:51] [PASSED] 0x4906 (DG1)
[23:45:51] [PASSED] 0x4907 (DG1)
[23:45:51] [PASSED] 0x4908 (DG1)
[23:45:51] [PASSED] 0x4909 (DG1)
[23:45:51] [PASSED] 0x56C0 (DG2)
[23:45:51] [PASSED] 0x56C2 (DG2)
[23:45:51] [PASSED] 0x56C1 (DG2)
[23:45:51] [PASSED] 0x7D51 (METEORLAKE)
[23:45:51] [PASSED] 0x7DD1 (METEORLAKE)
[23:45:51] [PASSED] 0x7D41 (METEORLAKE)
[23:45:51] [PASSED] 0x7D67 (METEORLAKE)
[23:45:51] [PASSED] 0xB640 (METEORLAKE)
[23:45:51] [PASSED] 0x56A0 (DG2)
[23:45:51] [PASSED] 0x56A1 (DG2)
[23:45:51] [PASSED] 0x56A2 (DG2)
[23:45:51] [PASSED] 0x56BE (DG2)
[23:45:51] [PASSED] 0x56BF (DG2)
[23:45:51] [PASSED] 0x5690 (DG2)
[23:45:51] [PASSED] 0x5691 (DG2)
[23:45:51] [PASSED] 0x5692 (DG2)
[23:45:51] [PASSED] 0x56A5 (DG2)
[23:45:51] [PASSED] 0x56A6 (DG2)
[23:45:51] [PASSED] 0x56B0 (DG2)
[23:45:51] [PASSED] 0x56B1 (DG2)
[23:45:51] [PASSED] 0x56BA (DG2)
[23:45:51] [PASSED] 0x56BB (DG2)
[23:45:51] [PASSED] 0x56BC (DG2)
[23:45:51] [PASSED] 0x56BD (DG2)
[23:45:51] [PASSED] 0x5693 (DG2)
[23:45:51] [PASSED] 0x5694 (DG2)
[23:45:51] [PASSED] 0x5695 (DG2)
[23:45:51] [PASSED] 0x56A3 (DG2)
[23:45:51] [PASSED] 0x56A4 (DG2)
[23:45:51] [PASSED] 0x56B2 (DG2)
[23:45:51] [PASSED] 0x56B3 (DG2)
[23:45:51] [PASSED] 0x5696 (DG2)
[23:45:51] [PASSED] 0x5697 (DG2)
[23:45:51] [PASSED] 0xB69 (PVC)
[23:45:51] [PASSED] 0xB6E (PVC)
[23:45:51] [PASSED] 0xBD4 (PVC)
[23:45:51] [PASSED] 0xBD5 (PVC)
[23:45:51] [PASSED] 0xBD6 (PVC)
[23:45:51] [PASSED] 0xBD7 (PVC)
[23:45:51] [PASSED] 0xBD8 (PVC)
[23:45:51] [PASSED] 0xBD9 (PVC)
[23:45:51] [PASSED] 0xBDA (PVC)
[23:45:51] [PASSED] 0xBDB (PVC)
[23:45:51] [PASSED] 0xBE0 (PVC)
[23:45:51] [PASSED] 0xBE1 (PVC)
[23:45:51] [PASSED] 0xBE5 (PVC)
[23:45:51] [PASSED] 0x7D40 (METEORLAKE)
[23:45:51] [PASSED] 0x7D45 (METEORLAKE)
[23:45:51] [PASSED] 0x7D55 (METEORLAKE)
[23:45:51] [PASSED] 0x7D60 (METEORLAKE)
[23:45:51] [PASSED] 0x7DD5 (METEORLAKE)
[23:45:51] [PASSED] 0x6420 (LUNARLAKE)
[23:45:51] [PASSED] 0x64A0 (LUNARLAKE)
[23:45:51] [PASSED] 0x64B0 (LUNARLAKE)
[23:45:51] [PASSED] 0xE202 (BATTLEMAGE)
[23:45:51] [PASSED] 0xE209 (BATTLEMAGE)
[23:45:51] [PASSED] 0xE20B (BATTLEMAGE)
[23:45:51] [PASSED] 0xE20C (BATTLEMAGE)
[23:45:51] [PASSED] 0xE20D (BATTLEMAGE)
[23:45:51] [PASSED] 0xE210 (BATTLEMAGE)
[23:45:51] [PASSED] 0xE211 (BATTLEMAGE)
[23:45:51] [PASSED] 0xE212 (BATTLEMAGE)
[23:45:51] [PASSED] 0xE216 (BATTLEMAGE)
[23:45:51] [PASSED] 0xE220 (BATTLEMAGE)
[23:45:51] [PASSED] 0xE221 (BATTLEMAGE)
[23:45:51] [PASSED] 0xE222 (BATTLEMAGE)
[23:45:51] [PASSED] 0xE223 (BATTLEMAGE)
[23:45:51] [PASSED] 0xB080 (PANTHERLAKE)
[23:45:51] [PASSED] 0xB081 (PANTHERLAKE)
[23:45:51] [PASSED] 0xB082 (PANTHERLAKE)
[23:45:51] [PASSED] 0xB083 (PANTHERLAKE)
[23:45:51] [PASSED] 0xB084 (PANTHERLAKE)
[23:45:51] [PASSED] 0xB085 (PANTHERLAKE)
[23:45:51] [PASSED] 0xB086 (PANTHERLAKE)
[23:45:51] [PASSED] 0xB087 (PANTHERLAKE)
[23:45:51] [PASSED] 0xB08F (PANTHERLAKE)
[23:45:51] [PASSED] 0xB090 (PANTHERLAKE)
[23:45:51] [PASSED] 0xB0A0 (PANTHERLAKE)
[23:45:51] [PASSED] 0xB0B0 (PANTHERLAKE)
[23:45:51] [PASSED] 0xFD80 (PANTHERLAKE)
[23:45:51] [PASSED] 0xFD81 (PANTHERLAKE)
[23:45:51] [PASSED] 0xD740 (NOVALAKE_S)
[23:45:51] [PASSED] 0xD741 (NOVALAKE_S)
[23:45:51] [PASSED] 0xD742 (NOVALAKE_S)
[23:45:51] [PASSED] 0xD743 (NOVALAKE_S)
[23:45:51] [PASSED] 0xD745 (NOVALAKE_S)
[23:45:51] [PASSED] 0xD74A (NOVALAKE_S)
[23:45:51] [PASSED] 0xD74B (NOVALAKE_S)
[23:45:51] [PASSED] 0x674C (CRESCENTISLAND)
[23:45:51] [PASSED] 0x674D (CRESCENTISLAND)
[23:45:51] [PASSED] 0x674E (CRESCENTISLAND)
[23:45:51] [PASSED] 0x674F (CRESCENTISLAND)
[23:45:51] [PASSED] 0x6750 (CRESCENTISLAND)
[23:45:51] [PASSED] 0xD750 (NOVALAKE_P)
[23:45:51] [PASSED] 0xD751 (NOVALAKE_P)
[23:45:51] [PASSED] 0xD752 (NOVALAKE_P)
[23:45:51] [PASSED] 0xD753 (NOVALAKE_P)
[23:45:51] [PASSED] 0xD754 (NOVALAKE_P)
[23:45:51] [PASSED] 0xD755 (NOVALAKE_P)
[23:45:51] [PASSED] 0xD756 (NOVALAKE_P)
[23:45:51] [PASSED] 0xD757 (NOVALAKE_P)
[23:45:51] [PASSED] 0xD75F (NOVALAKE_P)
[23:45:51] =============== [PASSED] check_platform_desc ===============
[23:45:51] ===================== [PASSED] xe_pci ======================
[23:45:51] ============= xe_rtp_tables_test (5 subtests) ==============
[23:45:51] ================== xe_rtp_table_gt_test  ===================
[23:45:51] [PASSED] gt_was/14011060649
[23:45:51] [PASSED] gt_was/14011059788
[23:45:51] [PASSED] gt_was/14015795083
[23:45:51] [PASSED] gt_was/16021867713
[23:45:51] [PASSED] gt_was/14019449301
[23:45:51] [PASSED] gt_was/16028005424
[23:45:51] [PASSED] gt_was/14026578760
[23:45:51] [PASSED] gt_was/1409420604
[23:45:51] [PASSED] gt_was/1408615072
[23:45:51] [PASSED] gt_was/22010523718
[23:45:51] [PASSED] gt_was/14011006942
[23:45:51] [PASSED] gt_was/14014830051
[23:45:51] [PASSED] gt_was/18018781329
[23:45:51] [PASSED] gt_was/1509235366
[23:45:51] [PASSED] gt_was/18018781329
[23:45:51] [PASSED] gt_was/16016694945
[23:45:51] [PASSED] gt_was/14018575942
[23:45:51] [PASSED] gt_was/22016670082
[23:45:51] [PASSED] gt_was/22016670082
[23:45:51] [PASSED] gt_was/14017421178
[23:45:51] [PASSED] gt_was/16025250150
[23:45:51] [PASSED] gt_was/14021871409
[23:45:51] [PASSED] gt_was/16021865536
[23:45:51] [PASSED] gt_was/14021486841
[23:45:51] [PASSED] gt_was/14025160223
[23:45:51] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[23:45:51] [PASSED] gt_was/14025635424
[23:45:51] [PASSED] gt_was/16028005424
[23:45:51] ============== [PASSED] xe_rtp_table_gt_test ===============
[23:45:51] ================== xe_rtp_table_gt_test  ===================
[23:45:51] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[23:45:51] [PASSED] gt_tunings/Tuning: 32B Access Enable
[23:45:51] [PASSED] gt_tunings/Tuning: L3 cache
[23:45:51] [PASSED] gt_tunings/Tuning: L3 cache - media
[23:45:51] [PASSED] gt_tunings/Tuning: Compression Overfetch
[23:45:51] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[23:45:51] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[23:45:51] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[23:45:51] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[23:45:51] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[23:45:51] [PASSED] gt_tunings/Tuning: Stateless compression control
[23:45:51] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[23:45:51] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[23:45:51] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[23:45:51] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[23:45:51] ============== [PASSED] xe_rtp_table_gt_test ===============
[23:45:51] ================== xe_rtp_table_oob_test  ==================
[23:45:51] [PASSED] oob_was/1607983814
[23:45:51] [PASSED] oob_was/16010904313
[23:45:51] [PASSED] oob_was/18022495364
[23:45:51] [PASSED] oob_was/22012773006
[23:45:51] [PASSED] oob_was/14014475959
[23:45:51] [PASSED] oob_was/22011391025
[23:45:51] [PASSED] oob_was/22012727170
[23:45:51] [PASSED] oob_was/22012727685
[23:45:51] [PASSED] oob_was/22016596838
[23:45:51] [PASSED] oob_was/18020744125
[23:45:51] [PASSED] oob_was/1409600907
[23:45:51] [PASSED] oob_was/22014953428
[23:45:51] [PASSED] oob_was/16017236439
[23:45:51] [PASSED] oob_was/14019821291
[23:45:51] [PASSED] oob_was/14015076503
[23:45:51] [PASSED] oob_was/14018913170
[23:45:51] [PASSED] oob_was/14018094691
[23:45:51] [PASSED] oob_was/18024947630
[23:45:51] [PASSED] oob_was/16022287689
[23:45:51] [PASSED] oob_was/13011645652
[23:45:51] [PASSED] oob_was/14022293748
[23:45:51] [PASSED] oob_was/22019794406
[23:45:51] [PASSED] oob_was/22019338487
[23:45:51] [PASSED] oob_was/16023588340
[23:45:51] [PASSED] oob_was/14019789679
[23:45:51] [PASSED] oob_was/14022866841
[23:45:51] [PASSED] oob_was/16021333562
[23:45:51] [PASSED] oob_was/14016712196
[23:45:51] [PASSED] oob_was/14015568240
[23:45:51] [PASSED] oob_was/18013179988
[23:45:51] [PASSED] oob_was/1508761755
[23:45:51] [PASSED] oob_was/16023105232
[23:45:51] [PASSED] oob_was/16026508708
[23:45:51] [PASSED] oob_was/14020001231
[23:45:51] [PASSED] oob_was/16023683509
[23:45:51] [PASSED] oob_was/14025515070
[23:45:51] [PASSED] oob_was/15015404425_disable
[23:45:51] [PASSED] oob_was/16026007364
[23:45:51] [PASSED] oob_was/14020316580
[23:45:51] [PASSED] oob_was/14025883347
[23:45:51] [PASSED] oob_was/16029380221
[23:45:51] [PASSED] oob_was/22022079272
[23:45:51] [PASSED] oob_was/16029897822
[23:45:51] ============== [PASSED] xe_rtp_table_oob_test ==============
[23:45:51] ================ xe_rtp_table_dev_oob_test  ================
[23:45:51] [PASSED] device_oob_was/22010954014
[23:45:51] [PASSED] device_oob_was/15015404425
[23:45:51] [PASSED] device_oob_was/22019338487_display
[23:45:51] [PASSED] device_oob_was/14022085890
[23:45:51] [PASSED] device_oob_was/14026539277
[23:45:51] [PASSED] device_oob_was/14026633728
[23:45:51] [PASSED] device_oob_was/14026746987
[23:45:51] [PASSED] device_oob_was/14026779378
[23:45:51] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[23:45:51] ========== xe_rtp_table_missing_upper_bound_test  ==========
[23:45:51] [PASSED] register_whitelist/WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865
[23:45:51] [PASSED] register_whitelist/1508744258, 14012131227, 1808121037
[23:45:51] [PASSED] register_whitelist/1806527549
[23:45:51] [PASSED] register_whitelist/allow_read_ctx_timestamp
[23:45:51] [PASSED] register_whitelist/allow_read_queue_timestamp
[23:45:51] [PASSED] register_whitelist/16014440446
[23:45:51] [PASSED] register_whitelist/16017236439
[23:45:51] [PASSED] register_whitelist/16020183090
[23:45:51] [PASSED] register_whitelist/14024997852
[23:45:51] [PASSED] register_whitelist/14024997852
[23:45:51] ====== [PASSED] xe_rtp_table_missing_upper_bound_test ======
[23:45:51] =============== [PASSED] xe_rtp_tables_test ================
[23:45:51] =================== xe_rtp (3 subtests) ====================
[23:45:51] =================== xe_rtp_rules_tests  ====================
[23:45:51] [PASSED] no
[23:45:51] [PASSED] yes
[23:45:51] [PASSED] no-and-no
[23:45:51] [PASSED] no-and-yes
[23:45:51] [PASSED] yes-and-no
[23:45:51] [PASSED] yes-and-yes
[23:45:51] [PASSED] no-or-no
[23:45:51] [PASSED] no-or-yes
[23:45:51] [PASSED] yes-or-no
[23:45:51] [PASSED] yes-or-yes
[23:45:51] [PASSED] no-yes-or-yes-no
[23:45:51] [PASSED] no-yes-or-yes-yes
[23:45:51] [PASSED] yes-yes-or-no-yes
[23:45:51] [PASSED] yes-yes-or-yes-yes
[23:45:51] [PASSED] no-no-or-yes-or-no
[23:45:51] [PASSED] or
[23:45:51] [PASSED] or-yes
[23:45:51] [PASSED] or-no
[23:45:51] [PASSED] yes-or
[23:45:51] [PASSED] no-or
[23:45:51] [PASSED] no-or-or-yes
[23:45:51] [PASSED] yes-or-or-no
[23:45:51] [PASSED] no-or-or-no
[23:45:51] [PASSED] missing-context-engine-class
[23:45:51] [PASSED] missing-context-engine-class-or-yes
[23:45:51] [PASSED] missing-context-engine-class-or-or-yes
[23:45:51] =============== [PASSED] xe_rtp_rules_tests ================
[23:45:51] =============== xe_rtp_process_to_sr_tests  ================
[23:45:51] [PASSED] coalesce-same-reg
[23:45:51] [PASSED] coalesce-same-reg-literal-and-func
[23:45:51] [PASSED] no-match-no-add
[23:45:51] [PASSED] two-regs-two-entries
[23:45:51] [PASSED] clr-one-set-other
[23:45:51] [PASSED] set-field
[23:45:51] [PASSED] conflict-duplicate
[23:45:51] [PASSED] conflict-not-disjoint
[23:45:51] [PASSED] conflict-not-disjoint-literal-and-func
[23:45:51] [PASSED] conflict-reg-type
[23:45:51] [PASSED] bad-mcr-reg-forced-to-regular
[23:45:51] [PASSED] bad-regular-reg-forced-to-mcr
[23:45:51] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[23:45:51] ================== xe_rtp_process_tests  ===================
[23:45:51] [PASSED] active1
[23:45:51] [PASSED] active2
[23:45:51] [PASSED] active-inactive
[23:45:51] [PASSED] inactive-active
[23:45:51] [PASSED] inactive-active-inactive
[23:45:51] [PASSED] inactive-inactive-inactive
[23:45:51] ============== [PASSED] xe_rtp_process_tests ===============
[23:45:51] ===================== [PASSED] xe_rtp ======================
[23:45:51] ==================== xe_wa (1 subtest) =====================
[23:45:51] ======================== xe_wa_gt  =========================
[23:45:51] [PASSED] TIGERLAKE B0
[23:45:51] [PASSED] DG1 A0
[23:45:51] [PASSED] DG1 B0
[23:45:51] [PASSED] ALDERLAKE_S A0
[23:45:51] [PASSED] ALDERLAKE_S B0
[23:45:51] [PASSED] ALDERLAKE_S C0
[23:45:51] [PASSED] ALDERLAKE_S D0
[23:45:51] [PASSED] ALDERLAKE_P A0
[23:45:51] [PASSED] ALDERLAKE_P B0
[23:45:51] [PASSED] ALDERLAKE_P C0
[23:45:51] [PASSED] ALDERLAKE_S RPLS D0
[23:45:51] [PASSED] ALDERLAKE_P RPLU E0
[23:45:51] [PASSED] DG2 G10 C0
[23:45:51] [PASSED] DG2 G11 B1
[23:45:51] [PASSED] DG2 G12 A1
[23:45:51] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[23:45:51] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[23:45:51] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[23:45:51] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[23:45:51] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[23:45:51] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[23:45:51] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[23:45:51] ==================== [PASSED] xe_wa_gt =====================
[23:45:51] ====================== [PASSED] xe_wa ======================
[23:45:51] ============================================================
[23:45:51] Testing complete. Ran 741 tests: passed: 723, skipped: 18
[23:45:51] Elapsed time: 36.653s total, 4.392s configuring, 31.595s building, 0.643s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[23:45:51] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[23:45:53] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[23:46:18] Starting KUnit Kernel (1/1)...
[23:46:18] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[23:46:18] ============ drm_test_pick_cmdline (2 subtests) ============
[23:46:18] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[23:46:18] =============== drm_test_pick_cmdline_named  ===============
[23:46:18] [PASSED] NTSC
[23:46:18] [PASSED] NTSC-J
[23:46:18] [PASSED] PAL
[23:46:18] [PASSED] PAL-M
[23:46:18] =========== [PASSED] drm_test_pick_cmdline_named ===========
[23:46:18] ============== [PASSED] drm_test_pick_cmdline ==============
[23:46:18] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[23:46:18] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[23:46:18] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[23:46:18] =========== drm_validate_clone_mode (2 subtests) ===========
[23:46:18] ============== drm_test_check_in_clone_mode  ===============
[23:46:18] [PASSED] in_clone_mode
[23:46:18] [PASSED] not_in_clone_mode
[23:46:18] ========== [PASSED] drm_test_check_in_clone_mode ===========
[23:46:18] =============== drm_test_check_valid_clones  ===============
[23:46:18] [PASSED] not_in_clone_mode
[23:46:18] [PASSED] valid_clone
[23:46:18] [PASSED] invalid_clone
[23:46:18] =========== [PASSED] drm_test_check_valid_clones ===========
[23:46:18] ============= [PASSED] drm_validate_clone_mode =============
[23:46:18] ============= drm_validate_modeset (1 subtest) =============
[23:46:18] [PASSED] drm_test_check_connector_changed_modeset
[23:46:18] ============== [PASSED] drm_validate_modeset ===============
[23:46:18] ====== drm_test_bridge_get_current_state (1 subtest) =======
[23:46:18] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[23:46:18] ======== [PASSED] drm_test_bridge_get_current_state ========
[23:46:18] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[23:46:18] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[23:46:18] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[23:46:18] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[23:46:18] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[23:46:18] ============== drm_bridge_alloc (2 subtests) ===============
[23:46:18] [PASSED] drm_test_drm_bridge_alloc_basic
[23:46:18] [PASSED] drm_test_drm_bridge_alloc_get_put
[23:46:18] ================ [PASSED] drm_bridge_alloc =================
[23:46:18] ============= drm_bridge_bus_fmt (5 subtests) ==============
[23:46:18] [PASSED] drm_test_bridge_rgb_yuv_rgb
[23:46:18] [PASSED] drm_test_bridge_must_convert_to_yuv444
[23:46:18] [PASSED] drm_test_bridge_hdmi_auto_rgb
[23:46:18] [PASSED] drm_test_bridge_auto_first
[23:46:18] [PASSED] drm_test_bridge_rgb_yuv_no_path
[23:46:18] =============== [PASSED] drm_bridge_bus_fmt ================
[23:46:18] ============= drm_cmdline_parser (40 subtests) =============
[23:46:18] [PASSED] drm_test_cmdline_force_d_only
[23:46:18] [PASSED] drm_test_cmdline_force_D_only_dvi
[23:46:18] [PASSED] drm_test_cmdline_force_D_only_hdmi
[23:46:18] [PASSED] drm_test_cmdline_force_D_only_not_digital
[23:46:18] [PASSED] drm_test_cmdline_force_e_only
[23:46:18] [PASSED] drm_test_cmdline_res
[23:46:18] [PASSED] drm_test_cmdline_res_vesa
[23:46:18] [PASSED] drm_test_cmdline_res_vesa_rblank
[23:46:18] [PASSED] drm_test_cmdline_res_rblank
[23:46:18] [PASSED] drm_test_cmdline_res_bpp
[23:46:18] [PASSED] drm_test_cmdline_res_refresh
[23:46:18] [PASSED] drm_test_cmdline_res_bpp_refresh
[23:46:18] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[23:46:18] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[23:46:18] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[23:46:18] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[23:46:18] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[23:46:18] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[23:46:18] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[23:46:18] [PASSED] drm_test_cmdline_res_margins_force_on
[23:46:18] [PASSED] drm_test_cmdline_res_vesa_margins
[23:46:18] [PASSED] drm_test_cmdline_name
[23:46:18] [PASSED] drm_test_cmdline_name_bpp
[23:46:18] [PASSED] drm_test_cmdline_name_option
[23:46:18] [PASSED] drm_test_cmdline_name_bpp_option
[23:46:18] [PASSED] drm_test_cmdline_rotate_0
[23:46:18] [PASSED] drm_test_cmdline_rotate_90
[23:46:18] [PASSED] drm_test_cmdline_rotate_180
[23:46:18] [PASSED] drm_test_cmdline_rotate_270
[23:46:18] [PASSED] drm_test_cmdline_hmirror
[23:46:18] [PASSED] drm_test_cmdline_vmirror
[23:46:18] [PASSED] drm_test_cmdline_margin_options
[23:46:18] [PASSED] drm_test_cmdline_multiple_options
[23:46:18] [PASSED] drm_test_cmdline_bpp_extra_and_option
[23:46:18] [PASSED] drm_test_cmdline_extra_and_option
[23:46:18] [PASSED] drm_test_cmdline_freestanding_options
[23:46:18] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[23:46:18] [PASSED] drm_test_cmdline_panel_orientation
[23:46:18] ================ drm_test_cmdline_invalid  =================
[23:46:18] [PASSED] margin_only
[23:46:18] [PASSED] interlace_only
[23:46:18] [PASSED] res_missing_x
[23:46:18] [PASSED] res_missing_y
[23:46:18] [PASSED] res_bad_y
[23:46:18] [PASSED] res_missing_y_bpp
[23:46:18] [PASSED] res_bad_bpp
[23:46:18] [PASSED] res_bad_refresh
[23:46:18] [PASSED] res_bpp_refresh_force_on_off
[23:46:18] [PASSED] res_invalid_mode
[23:46:18] [PASSED] res_bpp_wrong_place_mode
[23:46:18] [PASSED] name_bpp_refresh
[23:46:18] [PASSED] name_refresh
[23:46:18] [PASSED] name_refresh_wrong_mode
[23:46:18] [PASSED] name_refresh_invalid_mode
[23:46:18] [PASSED] rotate_multiple
[23:46:18] [PASSED] rotate_invalid_val
[23:46:18] [PASSED] rotate_truncated
[23:46:18] [PASSED] invalid_option
[23:46:18] [PASSED] invalid_tv_option
[23:46:18] [PASSED] truncated_tv_option
[23:46:18] ============ [PASSED] drm_test_cmdline_invalid =============
[23:46:18] =============== drm_test_cmdline_tv_options  ===============
[23:46:18] [PASSED] NTSC
[23:46:18] [PASSED] NTSC_443
[23:46:18] [PASSED] NTSC_J
[23:46:18] [PASSED] PAL
[23:46:18] [PASSED] PAL_M
[23:46:18] [PASSED] PAL_N
[23:46:18] [PASSED] SECAM
[23:46:18] [PASSED] MONO_525
[23:46:18] [PASSED] MONO_625
[23:46:18] =========== [PASSED] drm_test_cmdline_tv_options ===========
[23:46:18] =============== [PASSED] drm_cmdline_parser ================
[23:46:18] ========== drmm_connector_hdmi_init (20 subtests) ==========
[23:46:18] [PASSED] drm_test_connector_hdmi_init_valid
[23:46:18] [PASSED] drm_test_connector_hdmi_init_bpc_8
[23:46:18] [PASSED] drm_test_connector_hdmi_init_bpc_10
[23:46:18] [PASSED] drm_test_connector_hdmi_init_bpc_12
[23:46:18] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[23:46:18] [PASSED] drm_test_connector_hdmi_init_bpc_null
[23:46:18] [PASSED] drm_test_connector_hdmi_init_formats_empty
[23:46:18] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[23:46:18] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[23:46:18] [PASSED] supported_formats=0x9 yuv420_allowed=1
[23:46:18] [PASSED] supported_formats=0x9 yuv420_allowed=0
[23:46:18] [PASSED] supported_formats=0x5 yuv420_allowed=1
[23:46:18] [PASSED] supported_formats=0x5 yuv420_allowed=0
[23:46:18] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[23:46:18] [PASSED] drm_test_connector_hdmi_init_null_ddc
[23:46:18] [PASSED] drm_test_connector_hdmi_init_null_product
[23:46:18] [PASSED] drm_test_connector_hdmi_init_null_vendor
[23:46:18] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[23:46:18] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[23:46:18] [PASSED] drm_test_connector_hdmi_init_product_valid
[23:46:18] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[23:46:18] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[23:46:18] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[23:46:18] ========= drm_test_connector_hdmi_init_type_valid  =========
[23:46:18] [PASSED] HDMI-A
[23:46:18] [PASSED] HDMI-B
[23:46:18] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[23:46:18] ======== drm_test_connector_hdmi_init_type_invalid  ========
[23:46:18] [PASSED] Unknown
[23:46:18] [PASSED] VGA
[23:46:18] [PASSED] DVI-I
[23:46:18] [PASSED] DVI-D
[23:46:18] [PASSED] DVI-A
[23:46:18] [PASSED] Composite
[23:46:18] [PASSED] SVIDEO
[23:46:18] [PASSED] LVDS
[23:46:18] [PASSED] Component
[23:46:18] [PASSED] DIN
[23:46:18] [PASSED] DP
[23:46:18] [PASSED] TV
[23:46:18] [PASSED] eDP
[23:46:18] [PASSED] Virtual
[23:46:18] [PASSED] DSI
[23:46:18] [PASSED] DPI
[23:46:18] [PASSED] Writeback
[23:46:18] [PASSED] SPI
[23:46:18] [PASSED] USB
[23:46:18] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[23:46:18] ============ [PASSED] drmm_connector_hdmi_init =============
[23:46:18] ============= drmm_connector_init (3 subtests) =============
[23:46:18] [PASSED] drm_test_drmm_connector_init
[23:46:18] [PASSED] drm_test_drmm_connector_init_null_ddc
[23:46:18] ========= drm_test_drmm_connector_init_type_valid  =========
[23:46:18] [PASSED] Unknown
[23:46:18] [PASSED] VGA
[23:46:18] [PASSED] DVI-I
[23:46:18] [PASSED] DVI-D
[23:46:18] [PASSED] DVI-A
[23:46:18] [PASSED] Composite
[23:46:18] [PASSED] SVIDEO
[23:46:18] [PASSED] LVDS
[23:46:18] [PASSED] Component
[23:46:18] [PASSED] DIN
[23:46:18] [PASSED] DP
[23:46:18] [PASSED] HDMI-A
[23:46:18] [PASSED] HDMI-B
[23:46:18] [PASSED] TV
[23:46:18] [PASSED] eDP
[23:46:18] [PASSED] Virtual
[23:46:18] [PASSED] DSI
[23:46:18] [PASSED] DPI
[23:46:18] [PASSED] Writeback
[23:46:18] [PASSED] SPI
[23:46:18] [PASSED] USB
[23:46:18] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[23:46:18] =============== [PASSED] drmm_connector_init ===============
[23:46:18] ========= drm_connector_dynamic_init (6 subtests) ==========
[23:46:18] [PASSED] drm_test_drm_connector_dynamic_init
[23:46:18] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[23:46:18] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[23:46:18] [PASSED] drm_test_drm_connector_dynamic_init_properties
[23:46:18] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[23:46:18] [PASSED] Unknown
[23:46:18] [PASSED] VGA
[23:46:18] [PASSED] DVI-I
[23:46:18] [PASSED] DVI-D
[23:46:18] [PASSED] DVI-A
[23:46:18] [PASSED] Composite
[23:46:18] [PASSED] SVIDEO
[23:46:18] [PASSED] LVDS
[23:46:18] [PASSED] Component
[23:46:18] [PASSED] DIN
[23:46:18] [PASSED] DP
[23:46:18] [PASSED] HDMI-A
[23:46:18] [PASSED] HDMI-B
[23:46:18] [PASSED] TV
[23:46:18] [PASSED] eDP
[23:46:18] [PASSED] Virtual
[23:46:18] [PASSED] DSI
[23:46:18] [PASSED] DPI
[23:46:18] [PASSED] Writeback
[23:46:18] [PASSED] SPI
[23:46:18] [PASSED] USB
[23:46:18] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[23:46:18] ======== drm_test_drm_connector_dynamic_init_name  =========
[23:46:18] [PASSED] Unknown
[23:46:18] [PASSED] VGA
[23:46:18] [PASSED] DVI-I
[23:46:18] [PASSED] DVI-D
[23:46:18] [PASSED] DVI-A
[23:46:18] [PASSED] Composite
[23:46:18] [PASSED] SVIDEO
[23:46:18] [PASSED] LVDS
[23:46:18] [PASSED] Component
[23:46:18] [PASSED] DIN
[23:46:18] [PASSED] DP
[23:46:18] [PASSED] HDMI-A
[23:46:18] [PASSED] HDMI-B
[23:46:18] [PASSED] TV
[23:46:18] [PASSED] eDP
[23:46:18] [PASSED] Virtual
[23:46:18] [PASSED] DSI
[23:46:18] [PASSED] DPI
[23:46:18] [PASSED] Writeback
[23:46:18] [PASSED] SPI
[23:46:18] [PASSED] USB
[23:46:18] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[23:46:18] =========== [PASSED] drm_connector_dynamic_init ============
[23:46:18] ==== drm_connector_dynamic_register_early (4 subtests) =====
[23:46:18] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[23:46:18] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[23:46:18] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[23:46:18] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[23:46:18] ====== [PASSED] drm_connector_dynamic_register_early =======
[23:46:18] ======= drm_connector_dynamic_register (7 subtests) ========
[23:46:18] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[23:46:18] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[23:46:18] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[23:46:18] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[23:46:18] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[23:46:18] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[23:46:18] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[23:46:18] ========= [PASSED] drm_connector_dynamic_register ==========
[23:46:18] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[23:46:18] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[23:46:18] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[23:46:18] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[23:46:18] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[23:46:18] ========== drm_test_get_tv_mode_from_name_valid  ===========
[23:46:18] [PASSED] NTSC
[23:46:18] [PASSED] NTSC-443
[23:46:18] [PASSED] NTSC-J
[23:46:18] [PASSED] PAL
[23:46:18] [PASSED] PAL-M
[23:46:18] [PASSED] PAL-N
[23:46:18] [PASSED] SECAM
[23:46:18] [PASSED] Mono
[23:46:18] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[23:46:18] [PASSED] drm_test_get_tv_mode_from_name_truncated
[23:46:18] ============ [PASSED] drm_get_tv_mode_from_name ============
[23:46:18] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[23:46:18] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[23:46:18] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[23:46:18] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[23:46:18] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[23:46:18] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[23:46:18] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[23:46:18] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[23:46:18] [PASSED] VIC 96
[23:46:18] [PASSED] VIC 97
[23:46:18] [PASSED] VIC 101
[23:46:18] [PASSED] VIC 102
[23:46:18] [PASSED] VIC 106
[23:46:18] [PASSED] VIC 107
[23:46:18] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[23:46:18] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[23:46:18] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[23:46:18] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[23:46:18] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[23:46:18] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[23:46:18] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[23:46:18] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[23:46:18] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[23:46:18] [PASSED] Automatic
[23:46:18] [PASSED] Full
[23:46:18] [PASSED] Limited 16:235
[23:46:18] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[23:46:18] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[23:46:18] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[23:46:18] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[23:46:18] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[23:46:18] [PASSED] RGB
[23:46:18] [PASSED] YUV 4:2:0
[23:46:18] [PASSED] YUV 4:2:2
[23:46:18] [PASSED] YUV 4:4:4
[23:46:18] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[23:46:18] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[23:46:18] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[23:46:18] ============= drm_damage_helper (21 subtests) ==============
[23:46:18] [PASSED] drm_test_damage_iter_no_damage
[23:46:18] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[23:46:18] [PASSED] drm_test_damage_iter_no_damage_src_moved
[23:46:18] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[23:46:18] [PASSED] drm_test_damage_iter_no_damage_not_visible
[23:46:18] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[23:46:18] [PASSED] drm_test_damage_iter_no_damage_no_fb
[23:46:18] [PASSED] drm_test_damage_iter_simple_damage
[23:46:18] [PASSED] drm_test_damage_iter_single_damage
[23:46:18] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[23:46:18] [PASSED] drm_test_damage_iter_single_damage_outside_src
[23:46:18] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[23:46:18] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[23:46:18] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[23:46:18] [PASSED] drm_test_damage_iter_single_damage_src_moved
[23:46:18] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[23:46:18] [PASSED] drm_test_damage_iter_damage
[23:46:18] [PASSED] drm_test_damage_iter_damage_one_intersect
[23:46:18] [PASSED] drm_test_damage_iter_damage_one_outside
[23:46:18] [PASSED] drm_test_damage_iter_damage_src_moved
[23:46:18] [PASSED] drm_test_damage_iter_damage_not_visible
[23:46:18] ================ [PASSED] drm_damage_helper ================
[23:46:18] ============== drm_dp_mst_helper (3 subtests) ==============
[23:46:18] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[23:46:18] [PASSED] Clock 154000 BPP 30 DSC disabled
[23:46:18] [PASSED] Clock 234000 BPP 30 DSC disabled
[23:46:18] [PASSED] Clock 297000 BPP 24 DSC disabled
[23:46:18] [PASSED] Clock 332880 BPP 24 DSC enabled
[23:46:18] [PASSED] Clock 324540 BPP 24 DSC enabled
[23:46:18] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[23:46:18] ============== drm_test_dp_mst_calc_pbn_div  ===============
[23:46:18] [PASSED] Link rate 2000000 lane count 4
[23:46:18] [PASSED] Link rate 2000000 lane count 2
[23:46:18] [PASSED] Link rate 2000000 lane count 1
[23:46:18] [PASSED] Link rate 1350000 lane count 4
[23:46:18] [PASSED] Link rate 1350000 lane count 2
[23:46:18] [PASSED] Link rate 1350000 lane count 1
[23:46:18] [PASSED] Link rate 1000000 lane count 4
[23:46:18] [PASSED] Link rate 1000000 lane count 2
[23:46:18] [PASSED] Link rate 1000000 lane count 1
[23:46:18] [PASSED] Link rate 810000 lane count 4
[23:46:18] [PASSED] Link rate 810000 lane count 2
[23:46:18] [PASSED] Link rate 810000 lane count 1
[23:46:18] [PASSED] Link rate 540000 lane count 4
[23:46:18] [PASSED] Link rate 540000 lane count 2
[23:46:18] [PASSED] Link rate 540000 lane count 1
[23:46:18] [PASSED] Link rate 270000 lane count 4
[23:46:18] [PASSED] Link rate 270000 lane count 2
[23:46:18] [PASSED] Link rate 270000 lane count 1
[23:46:18] [PASSED] Link rate 162000 lane count 4
[23:46:18] [PASSED] Link rate 162000 lane count 2
[23:46:18] [PASSED] Link rate 162000 lane count 1
[23:46:18] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[23:46:18] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[23:46:18] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[23:46:18] [PASSED] DP_POWER_UP_PHY with port number
[23:46:18] [PASSED] DP_POWER_DOWN_PHY with port number
[23:46:18] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[23:46:18] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[23:46:18] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[23:46:18] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[23:46:18] [PASSED] DP_QUERY_PAYLOAD with port number
[23:46:18] [PASSED] DP_QUERY_PAYLOAD with VCPI
[23:46:18] [PASSED] DP_REMOTE_DPCD_READ with port number
[23:46:18] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[23:46:18] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[23:46:18] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[23:46:18] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[23:46:18] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[23:46:18] [PASSED] DP_REMOTE_I2C_READ with port number
[23:46:18] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[23:46:18] [PASSED] DP_REMOTE_I2C_READ with transactions array
[23:46:18] [PASSED] DP_REMOTE_I2C_WRITE with port number
[23:46:18] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[23:46:18] [PASSED] DP_REMOTE_I2C_WRITE with data array
[23:46:18] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[23:46:18] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[23:46:18] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[23:46:18] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[23:46:18] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[23:46:18] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[23:46:18] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[23:46:18] ================ [PASSED] drm_dp_mst_helper ================
[23:46:18] ================== drm_exec (7 subtests) ===================
[23:46:18] [PASSED] sanitycheck
[23:46:18] [PASSED] test_lock
[23:46:18] [PASSED] test_lock_unlock
[23:46:18] [PASSED] test_duplicates
[23:46:18] [PASSED] test_prepare
[23:46:18] [PASSED] test_prepare_array
[23:46:18] [PASSED] test_multiple_loops
[23:46:18] ==================== [PASSED] drm_exec =====================
[23:46:18] =========== drm_format_helper_test (17 subtests) ===========
[23:46:18] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[23:46:18] [PASSED] single_pixel_source_buffer
[23:46:18] [PASSED] single_pixel_clip_rectangle
[23:46:18] [PASSED] well_known_colors
[23:46:18] [PASSED] destination_pitch
[23:46:18] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[23:46:18] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[23:46:18] [PASSED] single_pixel_source_buffer
[23:46:18] [PASSED] single_pixel_clip_rectangle
[23:46:18] [PASSED] well_known_colors
[23:46:18] [PASSED] destination_pitch
[23:46:18] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[23:46:18] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[23:46:18] [PASSED] single_pixel_source_buffer
[23:46:18] [PASSED] single_pixel_clip_rectangle
[23:46:18] [PASSED] well_known_colors
[23:46:18] [PASSED] destination_pitch
[23:46:18] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[23:46:18] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[23:46:18] [PASSED] single_pixel_source_buffer
[23:46:18] [PASSED] single_pixel_clip_rectangle
[23:46:18] [PASSED] well_known_colors
[23:46:18] [PASSED] destination_pitch
[23:46:18] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[23:46:18] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[23:46:18] [PASSED] single_pixel_source_buffer
[23:46:18] [PASSED] single_pixel_clip_rectangle
[23:46:18] [PASSED] well_known_colors
[23:46:18] [PASSED] destination_pitch
[23:46:18] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[23:46:18] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[23:46:18] [PASSED] single_pixel_source_buffer
[23:46:18] [PASSED] single_pixel_clip_rectangle
[23:46:18] [PASSED] well_known_colors
[23:46:18] [PASSED] destination_pitch
[23:46:18] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[23:46:18] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[23:46:18] [PASSED] single_pixel_source_buffer
[23:46:18] [PASSED] single_pixel_clip_rectangle
[23:46:18] [PASSED] well_known_colors
[23:46:18] [PASSED] destination_pitch
[23:46:18] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[23:46:18] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[23:46:18] [PASSED] single_pixel_source_buffer
[23:46:18] [PASSED] single_pixel_clip_rectangle
[23:46:18] [PASSED] well_known_colors
[23:46:18] [PASSED] destination_pitch
[23:46:18] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[23:46:18] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[23:46:18] [PASSED] single_pixel_source_buffer
[23:46:18] [PASSED] single_pixel_clip_rectangle
[23:46:18] [PASSED] well_known_colors
[23:46:18] [PASSED] destination_pitch
[23:46:18] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[23:46:18] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[23:46:18] [PASSED] single_pixel_source_buffer
[23:46:18] [PASSED] single_pixel_clip_rectangle
[23:46:18] [PASSED] well_known_colors
[23:46:18] [PASSED] destination_pitch
[23:46:18] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[23:46:18] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[23:46:18] [PASSED] single_pixel_source_buffer
[23:46:18] [PASSED] single_pixel_clip_rectangle
[23:46:18] [PASSED] well_known_colors
[23:46:18] [PASSED] destination_pitch
[23:46:18] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[23:46:18] ============== drm_test_fb_xrgb8888_to_mono  ===============
[23:46:18] [PASSED] single_pixel_source_buffer
[23:46:18] [PASSED] single_pixel_clip_rectangle
[23:46:18] [PASSED] well_known_colors
[23:46:18] [PASSED] destination_pitch
[23:46:18] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[23:46:18] ==================== drm_test_fb_swab  =====================
[23:46:18] [PASSED] single_pixel_source_buffer
[23:46:18] [PASSED] single_pixel_clip_rectangle
[23:46:18] [PASSED] well_known_colors
[23:46:18] [PASSED] destination_pitch
[23:46:18] ================ [PASSED] drm_test_fb_swab =================
[23:46:18] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[23:46:18] [PASSED] single_pixel_source_buffer
[23:46:18] [PASSED] single_pixel_clip_rectangle
[23:46:18] [PASSED] well_known_colors
[23:46:18] [PASSED] destination_pitch
[23:46:18] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[23:46:18] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[23:46:18] [PASSED] single_pixel_source_buffer
[23:46:18] [PASSED] single_pixel_clip_rectangle
[23:46:18] [PASSED] well_known_colors
[23:46:18] [PASSED] destination_pitch
[23:46:18] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[23:46:18] ================= drm_test_fb_clip_offset  =================
[23:46:18] [PASSED] pass through
[23:46:18] [PASSED] horizontal offset
[23:46:18] [PASSED] vertical offset
[23:46:18] [PASSED] horizontal and vertical offset
[23:46:18] [PASSED] horizontal offset (custom pitch)
[23:46:18] [PASSED] vertical offset (custom pitch)
[23:46:18] [PASSED] horizontal and vertical offset (custom pitch)
[23:46:18] ============= [PASSED] drm_test_fb_clip_offset =============
[23:46:18] =================== drm_test_fb_memcpy  ====================
[23:46:18] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[23:46:18] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[23:46:18] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[23:46:18] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[23:46:18] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[23:46:18] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[23:46:18] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[23:46:18] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[23:46:18] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[23:46:18] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[23:46:18] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[23:46:18] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[23:46:18] =============== [PASSED] drm_test_fb_memcpy ================
[23:46:18] ============= [PASSED] drm_format_helper_test ==============
[23:46:18] ================= drm_format (18 subtests) =================
[23:46:18] [PASSED] drm_test_format_block_width_invalid
[23:46:18] [PASSED] drm_test_format_block_width_one_plane
[23:46:18] [PASSED] drm_test_format_block_width_two_plane
[23:46:18] [PASSED] drm_test_format_block_width_three_plane
[23:46:18] [PASSED] drm_test_format_block_width_tiled
[23:46:18] [PASSED] drm_test_format_block_height_invalid
[23:46:18] [PASSED] drm_test_format_block_height_one_plane
[23:46:18] [PASSED] drm_test_format_block_height_two_plane
[23:46:18] [PASSED] drm_test_format_block_height_three_plane
[23:46:18] [PASSED] drm_test_format_block_height_tiled
[23:46:18] [PASSED] drm_test_format_min_pitch_invalid
[23:46:18] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[23:46:18] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[23:46:18] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[23:46:18] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[23:46:18] [PASSED] drm_test_format_min_pitch_two_plane
[23:46:18] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[23:46:18] [PASSED] drm_test_format_min_pitch_tiled
[23:46:18] =================== [PASSED] drm_format ====================
[23:46:18] ============== drm_framebuffer (10 subtests) ===============
[23:46:18] ========== drm_test_framebuffer_check_src_coords  ==========
[23:46:18] [PASSED] Success: source fits into fb
[23:46:18] [PASSED] Fail: overflowing fb with x-axis coordinate
[23:46:18] [PASSED] Fail: overflowing fb with y-axis coordinate
[23:46:18] [PASSED] Fail: overflowing fb with source width
[23:46:18] [PASSED] Fail: overflowing fb with source height
[23:46:18] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[23:46:18] [PASSED] drm_test_framebuffer_cleanup
[23:46:18] =============== drm_test_framebuffer_create  ===============
[23:46:18] [PASSED] ABGR8888 normal sizes
[23:46:18] [PASSED] ABGR8888 max sizes
[23:46:18] [PASSED] ABGR8888 pitch greater than min required
[23:46:18] [PASSED] ABGR8888 pitch less than min required
[23:46:18] [PASSED] ABGR8888 Invalid width
[23:46:18] [PASSED] ABGR8888 Invalid buffer handle
[23:46:18] [PASSED] No pixel format
[23:46:18] [PASSED] ABGR8888 Width 0
[23:46:18] [PASSED] ABGR8888 Height 0
[23:46:18] [PASSED] ABGR8888 Out of bound height * pitch combination
[23:46:18] [PASSED] ABGR8888 Large buffer offset
[23:46:18] [PASSED] ABGR8888 Buffer offset for inexistent plane
[23:46:18] [PASSED] ABGR8888 Invalid flag
[23:46:18] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[23:46:18] [PASSED] ABGR8888 Valid buffer modifier
[23:46:18] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[23:46:18] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[23:46:18] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[23:46:18] [PASSED] NV12 Normal sizes
[23:46:18] [PASSED] NV12 Max sizes
[23:46:18] [PASSED] NV12 Invalid pitch
[23:46:18] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[23:46:18] [PASSED] NV12 different  modifier per-plane
[23:46:18] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[23:46:18] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[23:46:18] [PASSED] NV12 Modifier for inexistent plane
[23:46:18] [PASSED] NV12 Handle for inexistent plane
[23:46:18] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[23:46:18] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[23:46:18] [PASSED] YVU420 Normal sizes
[23:46:18] [PASSED] YVU420 Max sizes
[23:46:18] [PASSED] YVU420 Invalid pitch
[23:46:18] [PASSED] YVU420 Different pitches
[23:46:18] [PASSED] YVU420 Different buffer offsets/pitches
[23:46:18] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[23:46:18] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[23:46:18] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[23:46:18] [PASSED] YVU420 Valid modifier
[23:46:18] [PASSED] YVU420 Different modifiers per plane
[23:46:18] [PASSED] YVU420 Modifier for inexistent plane
[23:46:18] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[23:46:18] [PASSED] X0L2 Normal sizes
[23:46:18] [PASSED] X0L2 Max sizes
[23:46:18] [PASSED] X0L2 Invalid pitch
[23:46:18] [PASSED] X0L2 Pitch greater than minimum required
[23:46:18] [PASSED] X0L2 Handle for inexistent plane
[23:46:18] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[23:46:18] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[23:46:18] [PASSED] X0L2 Valid modifier
[23:46:18] [PASSED] X0L2 Modifier for inexistent plane
[23:46:18] =========== [PASSED] drm_test_framebuffer_create ===========
[23:46:18] [PASSED] drm_test_framebuffer_free
[23:46:18] [PASSED] drm_test_framebuffer_init
[23:46:18] [PASSED] drm_test_framebuffer_init_bad_format
[23:46:18] [PASSED] drm_test_framebuffer_init_dev_mismatch
[23:46:18] [PASSED] drm_test_framebuffer_lookup
[23:46:18] [PASSED] drm_test_framebuffer_lookup_inexistent
[23:46:18] [PASSED] drm_test_framebuffer_modifiers_not_supported
[23:46:18] ================= [PASSED] drm_framebuffer =================
[23:46:18] ================ drm_gem_shmem (8 subtests) ================
[23:46:18] [PASSED] drm_gem_shmem_test_obj_create
[23:46:18] [PASSED] drm_gem_shmem_test_obj_create_private
[23:46:18] [PASSED] drm_gem_shmem_test_pin_pages
[23:46:18] [PASSED] drm_gem_shmem_test_vmap
[23:46:18] [PASSED] drm_gem_shmem_test_get_sg_table
[23:46:18] [PASSED] drm_gem_shmem_test_get_pages_sgt
[23:46:18] [PASSED] drm_gem_shmem_test_madvise
[23:46:18] [PASSED] drm_gem_shmem_test_purge
[23:46:18] ================== [PASSED] drm_gem_shmem ==================
[23:46:18] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[23:46:18] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[23:46:18] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[23:46:18] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[23:46:18] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[23:46:18] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[23:46:18] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[23:46:18] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[23:46:18] [PASSED] Automatic
[23:46:18] [PASSED] Full
[23:46:18] [PASSED] Limited 16:235
[23:46:18] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[23:46:18] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[23:46:18] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[23:46:18] [PASSED] drm_test_check_disable_connector
[23:46:18] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[23:46:18] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[23:46:18] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[23:46:18] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[23:46:18] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[23:46:18] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[23:46:18] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[23:46:18] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[23:46:18] [PASSED] drm_test_check_output_bpc_dvi
[23:46:18] [PASSED] drm_test_check_output_bpc_format_vic_1
[23:46:18] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[23:46:18] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[23:46:18] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[23:46:18] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[23:46:18] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[23:46:18] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[23:46:18] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[23:46:18] ============ drm_test_check_hdmi_color_format  =============
[23:46:18] [PASSED] AUTO -> RGB
[23:46:18] [PASSED] YCBCR422 -> YUV422
[23:46:18] [PASSED] YCBCR420 -> YUV420
[23:46:18] [PASSED] YCBCR444 -> YUV444
[23:46:18] [PASSED] RGB -> RGB
[23:46:18] ======== [PASSED] drm_test_check_hdmi_color_format =========
[23:46:18] ======== drm_test_check_hdmi_color_format_420_only  ========
[23:46:18] [PASSED] RGB should fail
[23:46:18] [PASSED] YUV444 should fail
[23:46:18] [PASSED] YUV422 should fail
[23:46:18] [PASSED] YUV420 should work
[23:46:18] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[23:46:18] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[23:46:18] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[23:46:18] [PASSED] drm_test_check_broadcast_rgb_value
[23:46:18] [PASSED] drm_test_check_bpc_8_value
[23:46:18] [PASSED] drm_test_check_bpc_10_value
[23:46:18] [PASSED] drm_test_check_bpc_12_value
[23:46:18] [PASSED] drm_test_check_format_value
[23:46:18] [PASSED] drm_test_check_tmds_char_value
[23:46:18] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[23:46:18] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[23:46:18] [PASSED] drm_test_check_mode_valid
[23:46:18] [PASSED] drm_test_check_mode_valid_reject
[23:46:18] [PASSED] drm_test_check_mode_valid_reject_rate
[23:46:18] [PASSED] drm_test_check_mode_valid_reject_max_clock
[23:46:18] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[23:46:18] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[23:46:18] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[23:46:18] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[23:46:18] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[23:46:18] [PASSED] drm_test_check_infoframes
[23:46:18] [PASSED] drm_test_check_reject_avi_infoframe
[23:46:18] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[23:46:18] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[23:46:18] [PASSED] drm_test_check_reject_audio_infoframe
[23:46:18] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[23:46:18] ================= drm_managed (2 subtests) =================
[23:46:18] [PASSED] drm_test_managed_release_action
[23:46:18] [PASSED] drm_test_managed_run_action
[23:46:18] =================== [PASSED] drm_managed ===================
[23:46:18] =================== drm_mm (6 subtests) ====================
[23:46:18] [PASSED] drm_test_mm_init
[23:46:18] [PASSED] drm_test_mm_debug
[23:46:18] [PASSED] drm_test_mm_align32
[23:46:18] [PASSED] drm_test_mm_align64
[23:46:18] [PASSED] drm_test_mm_lowest
[23:46:18] [PASSED] drm_test_mm_highest
[23:46:18] ===================== [PASSED] drm_mm ======================
[23:46:18] ============= drm_modes_analog_tv (5 subtests) =============
[23:46:18] [PASSED] drm_test_modes_analog_tv_mono_576i
[23:46:18] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[23:46:18] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[23:46:18] [PASSED] drm_test_modes_analog_tv_pal_576i
[23:46:18] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[23:46:18] =============== [PASSED] drm_modes_analog_tv ===============
[23:46:18] ============== drm_plane_helper (2 subtests) ===============
[23:46:18] =============== drm_test_check_plane_state  ================
[23:46:18] [PASSED] clipping_simple
[23:46:18] [PASSED] clipping_rotate_reflect
[23:46:18] [PASSED] positioning_simple
[23:46:18] [PASSED] upscaling
[23:46:18] [PASSED] downscaling
[23:46:18] [PASSED] rounding1
[23:46:18] [PASSED] rounding2
[23:46:18] [PASSED] rounding3
[23:46:18] [PASSED] rounding4
[23:46:18] =========== [PASSED] drm_test_check_plane_state ============
[23:46:18] =========== drm_test_check_invalid_plane_state  ============
[23:46:18] [PASSED] positioning_invalid
[23:46:18] [PASSED] upscaling_invalid
[23:46:18] [PASSED] downscaling_invalid
[23:46:18] ======= [PASSED] drm_test_check_invalid_plane_state ========
[23:46:18] ================ [PASSED] drm_plane_helper =================
[23:46:18] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[23:46:18] ====== drm_test_connector_helper_tv_get_modes_check  =======
[23:46:18] [PASSED] None
[23:46:18] [PASSED] PAL
[23:46:18] [PASSED] NTSC
[23:46:18] [PASSED] Both, NTSC Default
[23:46:18] [PASSED] Both, PAL Default
[23:46:18] [PASSED] Both, NTSC Default, with PAL on command-line
[23:46:18] [PASSED] Both, PAL Default, with NTSC on command-line
[23:46:18] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[23:46:18] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[23:46:18] ================== drm_rect (9 subtests) ===================
[23:46:18] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[23:46:18] [PASSED] drm_test_rect_clip_scaled_not_clipped
[23:46:18] [PASSED] drm_test_rect_clip_scaled_clipped
[23:46:18] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[23:46:18] ================= drm_test_rect_intersect  =================
[23:46:18] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[23:46:18] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[23:46:18] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[23:46:18] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[23:46:18] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[23:46:18] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[23:46:18] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[23:46:18] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[23:46:18] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[23:46:18] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[23:46:18] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[23:46:18] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[23:46:18] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[23:46:18] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[23:46:18] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[23:46:18] ============= [PASSED] drm_test_rect_intersect =============
[23:46:18] ================ drm_test_rect_calc_hscale  ================
[23:46:18] [PASSED] normal use
[23:46:18] [PASSED] out of max range
[23:46:18] [PASSED] out of min range
[23:46:18] [PASSED] zero dst
[23:46:18] [PASSED] negative src
[23:46:18] [PASSED] negative dst
[23:46:18] ============ [PASSED] drm_test_rect_calc_hscale ============
[23:46:18] ================ drm_test_rect_calc_vscale  ================
[23:46:18] [PASSED] normal use
[23:46:18] [PASSED] out of max range
[23:46:18] [PASSED] out of min range
[23:46:18] [PASSED] zero dst
[23:46:18] [PASSED] negative src
[23:46:18] [PASSED] negative dst
[23:46:18] ============ [PASSED] drm_test_rect_calc_vscale ============
[23:46:18] ================== drm_test_rect_rotate  ===================
[23:46:18] [PASSED] reflect-x
[23:46:18] [PASSED] reflect-y
[23:46:18] [PASSED] rotate-0
[23:46:18] [PASSED] rotate-90
[23:46:18] [PASSED] rotate-180
[23:46:18] [PASSED] rotate-270
[23:46:18] ============== [PASSED] drm_test_rect_rotate ===============
[23:46:18] ================ drm_test_rect_rotate_inv  =================
[23:46:18] [PASSED] reflect-x
[23:46:18] [PASSED] reflect-y
[23:46:18] [PASSED] rotate-0
[23:46:18] [PASSED] rotate-90
[23:46:18] [PASSED] rotate-180
[23:46:18] [PASSED] rotate-270
[23:46:18] ============ [PASSED] drm_test_rect_rotate_inv =============
[23:46:18] ==================== [PASSED] drm_rect =====================
[23:46:18] ============ drm_sysfb_modeset_test (1 subtest) ============
[23:46:18] ============ drm_test_sysfb_build_fourcc_list  =============
[23:46:18] [PASSED] no native formats
[23:46:18] [PASSED] XRGB8888 as native format
[23:46:18] [PASSED] remove duplicates
[23:46:18] [PASSED] convert alpha formats
[23:46:18] [PASSED] random formats
[23:46:18] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[23:46:18] ============= [PASSED] drm_sysfb_modeset_test ==============
[23:46:18] ================== drm_fixp (2 subtests) ===================
[23:46:18] [PASSED] drm_test_int2fixp
[23:46:18] [PASSED] drm_test_sm2fixp
[23:46:18] ==================== [PASSED] drm_fixp =====================
[23:46:18] ============================================================
[23:46:18] Testing complete. Ran 637 tests: passed: 637
[23:46:18] Elapsed time: 26.668s total, 1.793s configuring, 24.709s building, 0.148s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[23:46:18] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[23:46:20] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[23:46:30] Starting KUnit Kernel (1/1)...
[23:46:30] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[23:46:30] ================= ttm_device (5 subtests) ==================
[23:46:30] [PASSED] ttm_device_init_basic
[23:46:30] [PASSED] ttm_device_init_multiple
[23:46:30] [PASSED] ttm_device_fini_basic
[23:46:30] [PASSED] ttm_device_init_no_vma_man
[23:46:30] ================== ttm_device_init_pools  ==================
[23:46:30] [PASSED] No DMA allocations, no DMA32 required
[23:46:30] [PASSED] DMA allocations, DMA32 required
[23:46:30] [PASSED] No DMA allocations, DMA32 required
[23:46:30] [PASSED] DMA allocations, no DMA32 required
[23:46:30] ============== [PASSED] ttm_device_init_pools ==============
[23:46:30] =================== [PASSED] ttm_device ====================
[23:46:30] ================== ttm_pool (8 subtests) ===================
[23:46:30] ================== ttm_pool_alloc_basic  ===================
[23:46:30] [PASSED] One page
[23:46:30] [PASSED] More than one page
[23:46:30] [PASSED] Above the allocation limit
[23:46:30] [PASSED] One page, with coherent DMA mappings enabled
[23:46:30] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[23:46:30] ============== [PASSED] ttm_pool_alloc_basic ===============
[23:46:30] ============== ttm_pool_alloc_basic_dma_addr  ==============
[23:46:30] [PASSED] One page
[23:46:30] [PASSED] More than one page
[23:46:30] [PASSED] Above the allocation limit
[23:46:30] [PASSED] One page, with coherent DMA mappings enabled
[23:46:30] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[23:46:30] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[23:46:30] [PASSED] ttm_pool_alloc_order_caching_match
[23:46:30] [PASSED] ttm_pool_alloc_caching_mismatch
[23:46:30] [PASSED] ttm_pool_alloc_order_mismatch
[23:46:30] [PASSED] ttm_pool_free_dma_alloc
[23:46:30] [PASSED] ttm_pool_free_no_dma_alloc
[23:46:30] [PASSED] ttm_pool_fini_basic
[23:46:30] ==================== [PASSED] ttm_pool =====================
[23:46:30] ================ ttm_resource (8 subtests) =================
[23:46:30] ================= ttm_resource_init_basic  =================
[23:46:30] [PASSED] Init resource in TTM_PL_SYSTEM
[23:46:30] [PASSED] Init resource in TTM_PL_VRAM
[23:46:30] [PASSED] Init resource in a private placement
[23:46:30] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[23:46:30] ============= [PASSED] ttm_resource_init_basic =============
[23:46:30] [PASSED] ttm_resource_init_pinned
[23:46:30] [PASSED] ttm_resource_fini_basic
[23:46:30] [PASSED] ttm_resource_manager_init_basic
[23:46:30] [PASSED] ttm_resource_manager_usage_basic
[23:46:30] [PASSED] ttm_resource_manager_set_used_basic
[23:46:30] [PASSED] ttm_sys_man_alloc_basic
[23:46:30] [PASSED] ttm_sys_man_free_basic
[23:46:30] ================== [PASSED] ttm_resource ===================
[23:46:30] =================== ttm_tt (15 subtests) ===================
[23:46:30] ==================== ttm_tt_init_basic  ====================
[23:46:30] [PASSED] Page-aligned size
[23:46:30] [PASSED] Extra pages requested
[23:46:30] ================ [PASSED] ttm_tt_init_basic ================
[23:46:30] [PASSED] ttm_tt_init_misaligned
[23:46:30] [PASSED] ttm_tt_fini_basic
[23:46:30] [PASSED] ttm_tt_fini_sg
[23:46:30] [PASSED] ttm_tt_fini_shmem
[23:46:30] [PASSED] ttm_tt_create_basic
[23:46:30] [PASSED] ttm_tt_create_invalid_bo_type
[23:46:30] [PASSED] ttm_tt_create_ttm_exists
[23:46:30] [PASSED] ttm_tt_create_failed
[23:46:30] [PASSED] ttm_tt_destroy_basic
[23:46:30] [PASSED] ttm_tt_populate_null_ttm
[23:46:30] [PASSED] ttm_tt_populate_populated_ttm
[23:46:30] [PASSED] ttm_tt_unpopulate_basic
[23:46:30] [PASSED] ttm_tt_unpopulate_empty_ttm
[23:46:30] [PASSED] ttm_tt_swapin_basic
[23:46:30] ===================== [PASSED] ttm_tt ======================
[23:46:30] =================== ttm_bo (14 subtests) ===================
[23:46:30] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[23:46:30] [PASSED] Cannot be interrupted and sleeps
[23:46:30] [PASSED] Cannot be interrupted, locks straight away
[23:46:30] [PASSED] Can be interrupted, sleeps
[23:46:30] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[23:46:30] [PASSED] ttm_bo_reserve_locked_no_sleep
[23:46:30] [PASSED] ttm_bo_reserve_no_wait_ticket
[23:46:30] [PASSED] ttm_bo_reserve_double_resv
[23:46:30] [PASSED] ttm_bo_reserve_interrupted
[23:46:30] [PASSED] ttm_bo_reserve_deadlock
[23:46:30] [PASSED] ttm_bo_unreserve_basic
[23:46:30] [PASSED] ttm_bo_unreserve_pinned
[23:46:30] [PASSED] ttm_bo_unreserve_bulk
[23:46:30] [PASSED] ttm_bo_fini_basic
[23:46:30] [PASSED] ttm_bo_fini_shared_resv
[23:46:30] [PASSED] ttm_bo_pin_basic
[23:46:30] [PASSED] ttm_bo_pin_unpin_resource
[23:46:30] [PASSED] ttm_bo_multiple_pin_one_unpin
[23:46:30] ===================== [PASSED] ttm_bo ======================
[23:46:30] ============== ttm_bo_validate (22 subtests) ===============
[23:46:30] ============== ttm_bo_init_reserved_sys_man  ===============
[23:46:30] [PASSED] Buffer object for userspace
[23:46:30] [PASSED] Kernel buffer object
[23:46:30] [PASSED] Shared buffer object
[23:46:30] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[23:46:30] ============== ttm_bo_init_reserved_mock_man  ==============
[23:46:30] [PASSED] Buffer object for userspace
[23:46:30] [PASSED] Kernel buffer object
[23:46:30] [PASSED] Shared buffer object
[23:46:30] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[23:46:30] [PASSED] ttm_bo_init_reserved_resv
[23:46:30] ================== ttm_bo_validate_basic  ==================
[23:46:30] [PASSED] Buffer object for userspace
[23:46:30] [PASSED] Kernel buffer object
[23:46:30] [PASSED] Shared buffer object
[23:46:30] ============== [PASSED] ttm_bo_validate_basic ==============
[23:46:30] [PASSED] ttm_bo_validate_invalid_placement
[23:46:30] ============= ttm_bo_validate_same_placement  ==============
[23:46:30] [PASSED] System manager
[23:46:30] [PASSED] VRAM manager
[23:46:30] ========= [PASSED] ttm_bo_validate_same_placement ==========
[23:46:30] [PASSED] ttm_bo_validate_failed_alloc
[23:46:30] [PASSED] ttm_bo_validate_pinned
[23:46:30] [PASSED] ttm_bo_validate_busy_placement
[23:46:30] ================ ttm_bo_validate_multihop  =================
[23:46:30] [PASSED] Buffer object for userspace
[23:46:30] [PASSED] Kernel buffer object
[23:46:30] [PASSED] Shared buffer object
[23:46:30] ============ [PASSED] ttm_bo_validate_multihop =============
[23:46:30] ========== ttm_bo_validate_no_placement_signaled  ==========
[23:46:30] [PASSED] Buffer object in system domain, no page vector
[23:46:30] [PASSED] Buffer object in system domain with an existing page vector
[23:46:30] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[23:46:30] ======== ttm_bo_validate_no_placement_not_signaled  ========
[23:46:30] [PASSED] Buffer object for userspace
[23:46:30] [PASSED] Kernel buffer object
[23:46:30] [PASSED] Shared buffer object
[23:46:30] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[23:46:30] [PASSED] ttm_bo_validate_move_fence_signaled
[23:46:30] ========= ttm_bo_validate_move_fence_not_signaled  =========
[23:46:30] [PASSED] Waits for GPU
[23:46:30] [PASSED] Tries to lock straight away
[23:46:30] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[23:46:30] [PASSED] ttm_bo_validate_swapout
[23:46:30] [PASSED] ttm_bo_validate_happy_evict
[23:46:30] [PASSED] ttm_bo_validate_all_pinned_evict
[23:46:30] [PASSED] ttm_bo_validate_allowed_only_evict
[23:46:30] [PASSED] ttm_bo_validate_deleted_evict
[23:46:30] [PASSED] ttm_bo_validate_busy_domain_evict
[23:46:30] [PASSED] ttm_bo_validate_evict_gutting
[23:46:30] [PASSED] ttm_bo_validate_recrusive_evict
[23:46:30] ================= [PASSED] ttm_bo_validate =================
[23:46:30] ============================================================
[23:46:30] Testing complete. Ran 102 tests: passed: 102
[23:46:30] Elapsed time: 11.919s total, 1.821s configuring, 9.883s building, 0.186s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel



^ permalink raw reply	[flat|nested] 6+ messages in thread

* ✓ Xe.CI.BAT: success for LNL_FLUSH_* enhancements
  2026-07-22 21:59 [RFC PATCH 0/2] LNL_FLUSH_* enhancements Matthew Brost
                   ` (3 preceding siblings ...)
  2026-07-22 23:46 ` ✓ CI.KUnit: success " Patchwork
@ 2026-07-23  0:20 ` Patchwork
  4 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2026-07-23  0:20 UTC (permalink / raw)
  To: Matthew Brost; +Cc: intel-xe

[-- Attachment #1: Type: text/plain, Size: 847 bytes --]

== Series Details ==

Series: LNL_FLUSH_* enhancements
URL   : https://patchwork.freedesktop.org/series/170939/
State : success

== Summary ==

CI Bug Log - changes from xe-5463-aff95d2d4b516f1618e3fb1cdb5850b6e1b19bb9_BAT -> xe-pw-170939v1_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (13 -> 13)
------------------------------

  No changes in participating hosts


Changes
-------

  No changes found


Build changes
-------------

  * Linux: xe-5463-aff95d2d4b516f1618e3fb1cdb5850b6e1b19bb9 -> xe-pw-170939v1

  IGT_9020: 9020
  xe-5463-aff95d2d4b516f1618e3fb1cdb5850b6e1b19bb9: aff95d2d4b516f1618e3fb1cdb5850b6e1b19bb9
  xe-pw-170939v1: 170939v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-170939v1/index.html

[-- Attachment #2: Type: text/html, Size: 1395 bytes --]

^ permalink raw reply	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2026-07-23  0:20 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-07-22 21:59 [RFC PATCH 0/2] LNL_FLUSH_* enhancements Matthew Brost
2026-07-22 21:59 ` [RFC PATCH 1/2] drm/xe: Scope LNL_FLUSH_* workaround to affected CPUs, not GPU platform Matthew Brost
2026-07-22 21:59 ` [RFC PATCH 2/2] drm/xe: Add DRM_XE_DEBUG_FLUSH_WA to force the CPU flush workaround on Matthew Brost
2026-07-22 23:45 ` ✗ CI.checkpatch: warning for LNL_FLUSH_* enhancements Patchwork
2026-07-22 23:46 ` ✓ CI.KUnit: success " Patchwork
2026-07-23  0:20 ` ✓ Xe.CI.BAT: " Patchwork

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