[PATCH 0/2] cdclk mismatch with sw/hw

[Arun R Murthy <arun.r.murthy@intel.com>]

With 4k eDP panel and an external DP, cdclk sw/hw state mismatch
warnings are observed along with cdclk mismatch on DC6 exit is also
observed and eventually FIFO underrun.

On boot, skl_cdclk_init_hw()->skl_sanitize_cdclk() decides to use the
pre-OS cdclk leading to programming a very low cdclk that doesnt satisfy
the pipes requirement. This leads to FIFO underrun.
Also this programmed and the sw calculated cdclk mismatches and on every
dc state exit warnings are thrown.

In this series the cdclk is programmed to max instead of 0, and then the
first modeset will bring it back to the required/calculated.

Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
Arun R Murthy (2):
      drm/i915/display: Seed skl_cdclk_init_hw() with SKU-max, not zero
      drm/i915/display: Reconcile cdclk SW state with HW on DC-off exit

 drivers/gpu/drm/i915/display/intel_cdclk.c         | 65 +++++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_cdclk.h         |  2 +
 .../drm/i915/display/intel_display_power_well.c    |  1 +
 3 files changed, 67 insertions(+), 1 deletion(-)
---
base-commit: 0377b35cbeef071dfeed06ccadc0d7607eccaa64
change-id: 20260804-cdclk-9e7ffc71f82a

Best regards,
-- 
Arun R Murthy <arun.r.murthy@intel.com>