* [PATCH 0/2] cdclk mismatch with sw/hw
@ 2026-08-04 9:28 Arun R Murthy
2026-08-04 9:28 ` [PATCH 1/2] drm/i915/display: Seed skl_cdclk_init_hw() with SKU-max, not zero Arun R Murthy
` (4 more replies)
0 siblings, 5 replies; 6+ messages in thread
From: Arun R Murthy @ 2026-08-04 9:28 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: Jani Nikula, Arun R Murthy, Polo-François Poli
With 4k eDP panel and an external DP, cdclk sw/hw state mismatch
warnings are observed along with cdclk mismatch on DC6 exit is also
observed and eventually FIFO underrun.
On boot, skl_cdclk_init_hw()->skl_sanitize_cdclk() decides to use the
pre-OS cdclk leading to programming a very low cdclk that doesnt satisfy
the pipes requirement. This leads to FIFO underrun.
Also this programmed and the sw calculated cdclk mismatches and on every
dc state exit warnings are thrown.
In this series the cdclk is programmed to max instead of 0, and then the
first modeset will bring it back to the required/calculated.
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
Arun R Murthy (2):
drm/i915/display: Seed skl_cdclk_init_hw() with SKU-max, not zero
drm/i915/display: Reconcile cdclk SW state with HW on DC-off exit
drivers/gpu/drm/i915/display/intel_cdclk.c | 65 +++++++++++++++++++++-
drivers/gpu/drm/i915/display/intel_cdclk.h | 2 +
.../drm/i915/display/intel_display_power_well.c | 1 +
3 files changed, 67 insertions(+), 1 deletion(-)
---
base-commit: 0377b35cbeef071dfeed06ccadc0d7607eccaa64
change-id: 20260804-cdclk-9e7ffc71f82a
Best regards,
--
Arun R Murthy <arun.r.murthy@intel.com>
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/2] drm/i915/display: Seed skl_cdclk_init_hw() with SKU-max, not zero
2026-08-04 9:28 [PATCH 0/2] cdclk mismatch with sw/hw Arun R Murthy
@ 2026-08-04 9:28 ` Arun R Murthy
2026-08-04 9:28 ` [PATCH 2/2] drm/i915/display: Reconcile cdclk SW state with HW on DC-off exit Arun R Murthy
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Arun R Murthy @ 2026-08-04 9:28 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: Jani Nikula, Arun R Murthy, Polo-François Poli
skl_cdclk_init_hw() has a recovery path that runs when skl_sanitize_cdclk()
has decided the pre-OS CDCLK state is not usable and zeroes
display->cdclk.hw.
Seed with the SKU-permitted maximum instead (as read from SKL_DFSM), so
the recovery path lands on a cdclk that satisfies every pipe on the SKU.
The very first atomic commit that follows will dial cdclk down to what
active pipes actually need via the normal skl_modeset_calc_cdclk() path.
Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/work_items/16595
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
Tested-by: Polo-François Poli <polo.code.dev@gmail.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 65 +++++++++++++++++++++++++++++-
1 file changed, 64 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index a53d887271778193fd400b9199ad841d5d9730fe..19f3ef8adfcded378428924539db9336834278ea 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1288,6 +1288,31 @@ static void skl_sanitize_cdclk(struct intel_display *display)
display->cdclk.hw.vco = ~0;
}
+/*
+ * Seed cdclk from the SKU-permitted maximum. Used by skl_cdclk_init_hw()'s
+ * recovery path when skl_sanitize_cdclk() has decided the pre-OS CDCLK state
+ * is not usable and has zeroed display->cdclk.hw.
+ * Seed with the SKU top instead: it is guaranteed to satisfy every pipe on
+ * the platform, and the very first atomic commit will dial cdclk down via
+ * skl_modeset_calc_cdclk() once per-pipe min_cdclk is known.
+ */
+static int skl_cdclk_init_hw_seed(struct intel_display *display, int vco)
+{
+ u32 limit = intel_de_read(display, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
+ int max_cdclk;
+
+ if (limit == SKL_DFSM_CDCLK_LIMIT_675)
+ max_cdclk = 617143;
+ else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
+ max_cdclk = 540000;
+ else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
+ max_cdclk = 432000;
+ else
+ max_cdclk = 308571;
+
+ return skl_calc_cdclk(max_cdclk, vco);
+}
+
static void skl_cdclk_init_hw(struct intel_display *display)
{
struct intel_cdclk_config cdclk_config;
@@ -1311,9 +1336,14 @@ static void skl_cdclk_init_hw(struct intel_display *display)
cdclk_config.vco = display->cdclk.skl_preferred_vco_freq;
if (cdclk_config.vco == 0)
cdclk_config.vco = 8100000;
- cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco);
+
+ cdclk_config.cdclk = skl_cdclk_init_hw_seed(display, cdclk_config.vco);
cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk);
+ drm_dbg_kms(display->drm,
+ "cdclk: init seed cdclk=%d vco=%d volt=%d (SKU-max, no per-pipe min_cdclk yet)\n",
+ cdclk_config.cdclk, cdclk_config.vco, cdclk_config.voltage_level);
+
skl_set_cdclk(display, &cdclk_config, INVALID_PIPE);
}
@@ -4231,6 +4261,39 @@ void intel_cdclk_read_hw(struct intel_display *display)
cdclk_state->logical = display->cdclk.hw;
}
+/**
+ * intel_cdclk_sync_hw_state - Adopt the HW-asserted cdclk into SW state.
+ * @display: display instance
+ * @hw_config: the cdclk configuration as currently read back from HW
+ *
+ * This helper reconciles the SW state to match what HW is currently asserting.
+ * It updates display->cdclk.hw and the committed cdclk_state's actual/logical
+ * so that any following atomic commit sees a truthful baseline and will
+ * naturally attach a cdclk_state (via intel_cdclk_atomic_check()) to raise
+ * cdclk when the workload demands it.
+ */
+void intel_cdclk_sync_hw_state(struct intel_display *display,
+ const struct intel_cdclk_config *hw_config)
+{
+ struct intel_cdclk_state *cdclk_state =
+ to_intel_cdclk_state(display->cdclk.obj.state);
+
+ if (!intel_cdclk_clock_changed(&display->cdclk.hw, hw_config))
+ return;
+
+ drm_dbg_kms(display->drm,
+ "cdclk: syncing SW state to HW after drift (sw %d/vco %d/ref %d -> hw %d/vco %d/ref %d)\n",
+ display->cdclk.hw.cdclk, display->cdclk.hw.vco, display->cdclk.hw.ref,
+ hw_config->cdclk, hw_config->vco, hw_config->ref);
+
+ display->cdclk.hw.cdclk = hw_config->cdclk;
+ display->cdclk.hw.vco = hw_config->vco;
+ display->cdclk.hw.ref = hw_config->ref;
+
+ cdclk_state->actual = display->cdclk.hw;
+ cdclk_state->logical = display->cdclk.hw;
+}
+
static int calc_cdclk(const struct intel_crtc_state *crtc_state, int min_cdclk)
{
struct intel_display *display = to_intel_display(crtc_state);
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/2] drm/i915/display: Reconcile cdclk SW state with HW on DC-off exit
2026-08-04 9:28 [PATCH 0/2] cdclk mismatch with sw/hw Arun R Murthy
2026-08-04 9:28 ` [PATCH 1/2] drm/i915/display: Seed skl_cdclk_init_hw() with SKU-max, not zero Arun R Murthy
@ 2026-08-04 9:28 ` Arun R Murthy
2026-08-05 13:55 ` ✓ CI.KUnit: success for cdclk mismatch with sw/hw (rev2) Patchwork
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Arun R Murthy @ 2026-08-04 9:28 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: Jani Nikula, Arun R Murthy, Polo-François Poli
Add intel_cdclk_sync_hw_state() which adopts the HW-asserted cdclk into
display->cdclk.hw and the committed cdclk_state (actual/logical) so that
future atomic checks operate on a truthful baseline. Any pipe that needs
more cdclk than HW is currently delivering will then naturally attach a
cdclk_state via intel_cdclk_atomic_check() and raise cdclk through the
normal modeset path.
voltage_level cannot be reliably read back on all gens, so the SW value
is preserved.
Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/work_items/16595
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
Tested-by: Polo-François Poli <polo.code.dev@gmail.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.h | 2 ++
drivers/gpu/drm/i915/display/intel_display_power_well.c | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
index a60cbf745ee2638a092dbdce98b994b17d7009ef..ed78c855320ad4e92364989fd3f9248748a9de8a 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -69,6 +69,8 @@ int intel_cdclk_min_cdclk(const struct intel_cdclk_state *cdclk_state, enum pipe
bool intel_cdclk_pmdemand_needs_update(struct intel_atomic_state *state);
void intel_cdclk_force_min_cdclk(struct intel_cdclk_state *cdclk_state, int force_min_cdclk);
void intel_cdclk_read_hw(struct intel_display *display);
+void intel_cdclk_sync_hw_state(struct intel_display *display,
+ const struct intel_cdclk_config *hw_config);
unsigned int intel_cdclk_prefill_adjustment(const struct intel_crtc_state *crtc_state);
unsigned int intel_cdclk_prefill_adjustment_worst(const struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 02cb4d800e2389fc2a7d958ed78339a74f5c057e..11b8521d9d0c8b5381d3b90b5cbf24b97deacf65 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -1105,6 +1105,7 @@ void gen9_disable_dc_states(struct intel_display *display)
intel_cdclk_get_cdclk(display, &cdclk_config);
/* Can't read out voltage_level so can't use intel_cdclk_changed() */
+ intel_cdclk_sync_hw_state(display, &cdclk_config);
drm_WARN_ON(display->drm,
intel_cdclk_clock_changed(&display->cdclk.hw,
&cdclk_config));
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* ✓ CI.KUnit: success for cdclk mismatch with sw/hw (rev2)
2026-08-04 9:28 [PATCH 0/2] cdclk mismatch with sw/hw Arun R Murthy
2026-08-04 9:28 ` [PATCH 1/2] drm/i915/display: Seed skl_cdclk_init_hw() with SKU-max, not zero Arun R Murthy
2026-08-04 9:28 ` [PATCH 2/2] drm/i915/display: Reconcile cdclk SW state with HW on DC-off exit Arun R Murthy
@ 2026-08-05 13:55 ` Patchwork
2026-08-05 14:39 ` ✗ Xe.CI.BAT: failure " Patchwork
2026-08-06 1:53 ` ✗ Xe.CI.FULL: " Patchwork
4 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2026-08-05 13:55 UTC (permalink / raw)
To: Murthy, Arun R; +Cc: intel-xe
== Series Details ==
Series: cdclk mismatch with sw/hw (rev2)
URL : https://patchwork.freedesktop.org/series/171570/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[13:54:18] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[13:54:23] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[13:54:54] Starting KUnit Kernel (1/1)...
[13:54:54] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[13:54:54] ================== guc_buf (11 subtests) ===================
[13:54:54] [PASSED] test_smallest
[13:54:54] [PASSED] test_largest
[13:54:54] [PASSED] test_granular
[13:54:54] [PASSED] test_unique
[13:54:54] [PASSED] test_overlap
[13:54:54] [PASSED] test_reusable
[13:54:54] [PASSED] test_too_big
[13:54:54] [PASSED] test_flush
[13:54:54] [PASSED] test_lookup
[13:54:54] [PASSED] test_data
[13:54:54] [PASSED] test_class
[13:54:54] ===================== [PASSED] guc_buf =====================
[13:54:54] =================== guc_dbm (7 subtests) ===================
[13:54:54] [PASSED] test_empty
[13:54:54] [PASSED] test_default
[13:54:54] ======================== test_size ========================
[13:54:54] [PASSED] 4
[13:54:54] [PASSED] 8
[13:54:54] [PASSED] 32
[13:54:54] [PASSED] 256
[13:54:54] ==================== [PASSED] test_size ====================
[13:54:54] ======================= test_reuse ========================
[13:54:54] [PASSED] 4
[13:54:54] [PASSED] 8
[13:54:54] [PASSED] 32
[13:54:54] [PASSED] 256
[13:54:54] =================== [PASSED] test_reuse ====================
[13:54:54] =================== test_range_overlap ====================
[13:54:54] [PASSED] 4
[13:54:54] [PASSED] 8
[13:54:54] [PASSED] 32
[13:54:54] [PASSED] 256
[13:54:54] =============== [PASSED] test_range_overlap ================
[13:54:54] =================== test_range_compact ====================
[13:54:54] [PASSED] 4
[13:54:54] [PASSED] 8
[13:54:54] [PASSED] 32
[13:54:54] [PASSED] 256
[13:54:54] =============== [PASSED] test_range_compact ================
[13:54:54] ==================== test_range_spare =====================
[13:54:54] [PASSED] 4
[13:54:54] [PASSED] 8
[13:54:54] [PASSED] 32
[13:54:54] [PASSED] 256
[13:54:54] ================ [PASSED] test_range_spare =================
[13:54:54] ===================== [PASSED] guc_dbm =====================
[13:54:54] =================== guc_idm (6 subtests) ===================
[13:54:54] [PASSED] bad_init
[13:54:54] [PASSED] no_init
[13:54:54] [PASSED] init_fini
[13:54:54] [PASSED] check_used
[13:54:54] [PASSED] check_quota
[13:54:54] [PASSED] check_all
[13:54:54] ===================== [PASSED] guc_idm =====================
[13:54:54] =============== guc_klv_helpers (9 subtests) ===============
[13:54:54] [PASSED] test_count
[13:54:54] [PASSED] test_encode_u32
[13:54:54] [PASSED] test_encode_u64
[13:54:54] [PASSED] test_encode_string
[13:54:54] [PASSED] test_encode_object_raw
[13:54:54] [PASSED] test_encode_object_klv
[13:54:54] [PASSED] test_encode_object_nested
[13:54:54] [PASSED] test_encode_object_basic
[13:54:54] [PASSED] test_print
[13:54:54] ================= [PASSED] guc_klv_helpers =================
[13:54:54] ================== no_relay (3 subtests) ===================
[13:54:54] [PASSED] xe_drops_guc2pf_if_not_ready
[13:54:54] [PASSED] xe_drops_guc2vf_if_not_ready
[13:54:54] [PASSED] xe_rejects_send_if_not_ready
[13:54:54] ==================== [PASSED] no_relay =====================
[13:54:54] ================== pf_relay (14 subtests) ==================
[13:54:54] [PASSED] pf_rejects_guc2pf_too_short
[13:54:54] [PASSED] pf_rejects_guc2pf_too_long
[13:54:54] [PASSED] pf_rejects_guc2pf_no_payload
[13:54:54] [PASSED] pf_fails_no_payload
[13:54:54] [PASSED] pf_fails_bad_origin
[13:54:54] [PASSED] pf_fails_bad_type
[13:54:54] [PASSED] pf_txn_reports_error
[13:54:54] [PASSED] pf_txn_sends_pf2guc
[13:54:54] [PASSED] pf_sends_pf2guc
[13:54:54] [SKIPPED] pf_loopback_nop (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[13:54:54] [SKIPPED] pf_loopback_echo (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[13:54:54] [SKIPPED] pf_loopback_fail (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[13:54:54] [SKIPPED] pf_loopback_busy (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[13:54:54] [SKIPPED] pf_loopback_retry (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[13:54:54] ==================== [PASSED] pf_relay =====================
[13:54:54] ================== vf_relay (3 subtests) ===================
[13:54:54] [PASSED] vf_rejects_guc2vf_too_short
[13:54:54] [PASSED] vf_rejects_guc2vf_too_long
[13:54:54] [PASSED] vf_rejects_guc2vf_no_payload
[13:54:54] ==================== [PASSED] vf_relay =====================
[13:54:54] ================ pf_gt_config (9 subtests) =================
[13:54:54] [PASSED] fair_contexts_1vf
[13:54:54] [PASSED] fair_doorbells_1vf
[13:54:54] [PASSED] fair_ggtt_1vf
[13:54:54] ====================== fair_vram_1vf ======================
[13:54:54] [PASSED] 3.50 GiB
[13:54:54] [PASSED] 11.5 GiB
[13:54:54] [PASSED] 15.5 GiB
[13:54:54] [PASSED] 31.5 GiB
[13:54:54] [PASSED] 63.5 GiB
[13:54:54] [PASSED] 1.91 GiB
[13:54:54] ================== [PASSED] fair_vram_1vf ==================
[13:54:54] ================ fair_vram_1vf_admin_only =================
[13:54:54] [PASSED] 3.50 GiB
[13:54:54] [PASSED] 11.5 GiB
[13:54:54] [PASSED] 15.5 GiB
[13:54:54] [PASSED] 31.5 GiB
[13:54:54] [PASSED] 63.5 GiB
[13:54:54] [PASSED] 1.91 GiB
[13:54:54] ============ [PASSED] fair_vram_1vf_admin_only =============
[13:54:54] ====================== fair_contexts ======================
[13:54:54] [PASSED] 1 VF
[13:54:54] [PASSED] 2 VFs
[13:54:54] [PASSED] 3 VFs
[13:54:54] [PASSED] 4 VFs
[13:54:54] [PASSED] 5 VFs
[13:54:54] [PASSED] 6 VFs
[13:54:54] [PASSED] 7 VFs
[13:54:54] [PASSED] 8 VFs
[13:54:54] [PASSED] 9 VFs
[13:54:54] [PASSED] 10 VFs
[13:54:54] [PASSED] 11 VFs
[13:54:54] [PASSED] 12 VFs
[13:54:54] [PASSED] 13 VFs
[13:54:54] [PASSED] 14 VFs
[13:54:54] [PASSED] 15 VFs
[13:54:54] [PASSED] 16 VFs
[13:54:54] [PASSED] 17 VFs
[13:54:54] [PASSED] 18 VFs
[13:54:54] [PASSED] 19 VFs
[13:54:54] [PASSED] 20 VFs
[13:54:54] [PASSED] 21 VFs
[13:54:54] [PASSED] 22 VFs
[13:54:54] [PASSED] 23 VFs
[13:54:54] [PASSED] 24 VFs
[13:54:54] [PASSED] 25 VFs
[13:54:54] [PASSED] 26 VFs
[13:54:54] [PASSED] 27 VFs
[13:54:54] [PASSED] 28 VFs
[13:54:54] [PASSED] 29 VFs
[13:54:54] [PASSED] 30 VFs
[13:54:54] [PASSED] 31 VFs
[13:54:54] [PASSED] 32 VFs
[13:54:54] [PASSED] 33 VFs
[13:54:54] [PASSED] 34 VFs
[13:54:54] [PASSED] 35 VFs
[13:54:54] [PASSED] 36 VFs
[13:54:54] [PASSED] 37 VFs
[13:54:54] [PASSED] 38 VFs
[13:54:54] [PASSED] 39 VFs
[13:54:54] [PASSED] 40 VFs
[13:54:54] [PASSED] 41 VFs
[13:54:54] [PASSED] 42 VFs
[13:54:54] [PASSED] 43 VFs
[13:54:54] [PASSED] 44 VFs
[13:54:54] [PASSED] 45 VFs
[13:54:54] [PASSED] 46 VFs
[13:54:54] [PASSED] 47 VFs
[13:54:54] [PASSED] 48 VFs
[13:54:54] [PASSED] 49 VFs
[13:54:54] [PASSED] 50 VFs
[13:54:54] [PASSED] 51 VFs
[13:54:54] [PASSED] 52 VFs
[13:54:54] [PASSED] 53 VFs
[13:54:54] [PASSED] 54 VFs
[13:54:54] [PASSED] 55 VFs
[13:54:54] [PASSED] 56 VFs
[13:54:54] [PASSED] 57 VFs
[13:54:54] [PASSED] 58 VFs
[13:54:54] [PASSED] 59 VFs
[13:54:54] [PASSED] 60 VFs
[13:54:54] [PASSED] 61 VFs
[13:54:54] [PASSED] 62 VFs
[13:54:54] [PASSED] 63 VFs
[13:54:54] ================== [PASSED] fair_contexts ==================
[13:54:54] ===================== fair_doorbells ======================
[13:54:54] [PASSED] 1 VF
[13:54:54] [PASSED] 2 VFs
[13:54:54] [PASSED] 3 VFs
[13:54:54] [PASSED] 4 VFs
[13:54:54] [PASSED] 5 VFs
[13:54:54] [PASSED] 6 VFs
[13:54:54] [PASSED] 7 VFs
[13:54:54] [PASSED] 8 VFs
[13:54:54] [PASSED] 9 VFs
[13:54:54] [PASSED] 10 VFs
[13:54:54] [PASSED] 11 VFs
[13:54:54] [PASSED] 12 VFs
[13:54:54] [PASSED] 13 VFs
[13:54:54] [PASSED] 14 VFs
[13:54:54] [PASSED] 15 VFs
[13:54:54] [PASSED] 16 VFs
[13:54:54] [PASSED] 17 VFs
[13:54:54] [PASSED] 18 VFs
[13:54:54] [PASSED] 19 VFs
[13:54:54] [PASSED] 20 VFs
[13:54:54] [PASSED] 21 VFs
[13:54:54] [PASSED] 22 VFs
[13:54:54] [PASSED] 23 VFs
[13:54:54] [PASSED] 24 VFs
[13:54:54] [PASSED] 25 VFs
[13:54:54] [PASSED] 26 VFs
[13:54:54] [PASSED] 27 VFs
[13:54:54] [PASSED] 28 VFs
[13:54:54] [PASSED] 29 VFs
[13:54:54] [PASSED] 30 VFs
[13:54:54] [PASSED] 31 VFs
[13:54:54] [PASSED] 32 VFs
[13:54:54] [PASSED] 33 VFs
[13:54:54] [PASSED] 34 VFs
[13:54:54] [PASSED] 35 VFs
[13:54:54] [PASSED] 36 VFs
[13:54:54] [PASSED] 37 VFs
[13:54:54] [PASSED] 38 VFs
[13:54:54] [PASSED] 39 VFs
[13:54:54] [PASSED] 40 VFs
[13:54:54] [PASSED] 41 VFs
[13:54:54] [PASSED] 42 VFs
[13:54:54] [PASSED] 43 VFs
[13:54:54] [PASSED] 44 VFs
[13:54:54] [PASSED] 45 VFs
[13:54:54] [PASSED] 46 VFs
[13:54:54] [PASSED] 47 VFs
[13:54:54] [PASSED] 48 VFs
[13:54:54] [PASSED] 49 VFs
[13:54:54] [PASSED] 50 VFs
[13:54:54] [PASSED] 51 VFs
[13:54:54] [PASSED] 52 VFs
[13:54:54] [PASSED] 53 VFs
[13:54:54] [PASSED] 54 VFs
[13:54:54] [PASSED] 55 VFs
[13:54:54] [PASSED] 56 VFs
[13:54:54] [PASSED] 57 VFs
[13:54:54] [PASSED] 58 VFs
[13:54:54] [PASSED] 59 VFs
[13:54:54] [PASSED] 60 VFs
[13:54:54] [PASSED] 61 VFs
[13:54:54] [PASSED] 62 VFs
[13:54:54] [PASSED] 63 VFs
[13:54:54] ================= [PASSED] fair_doorbells ==================
[13:54:54] ======================== fair_ggtt ========================
[13:54:54] [PASSED] 1 VF
[13:54:54] [PASSED] 2 VFs
[13:54:54] [PASSED] 3 VFs
[13:54:54] [PASSED] 4 VFs
[13:54:54] [PASSED] 5 VFs
[13:54:54] [PASSED] 6 VFs
[13:54:54] [PASSED] 7 VFs
[13:54:54] [PASSED] 8 VFs
[13:54:54] [PASSED] 9 VFs
[13:54:54] [PASSED] 10 VFs
[13:54:54] [PASSED] 11 VFs
[13:54:54] [PASSED] 12 VFs
[13:54:54] [PASSED] 13 VFs
[13:54:54] [PASSED] 14 VFs
[13:54:54] [PASSED] 15 VFs
[13:54:54] [PASSED] 16 VFs
[13:54:54] [PASSED] 17 VFs
[13:54:54] [PASSED] 18 VFs
[13:54:54] [PASSED] 19 VFs
[13:54:54] [PASSED] 20 VFs
[13:54:54] [PASSED] 21 VFs
[13:54:54] [PASSED] 22 VFs
[13:54:54] [PASSED] 23 VFs
[13:54:54] [PASSED] 24 VFs
[13:54:54] [PASSED] 25 VFs
[13:54:54] [PASSED] 26 VFs
[13:54:54] [PASSED] 27 VFs
[13:54:54] [PASSED] 28 VFs
[13:54:54] [PASSED] 29 VFs
[13:54:54] [PASSED] 30 VFs
[13:54:54] [PASSED] 31 VFs
[13:54:54] [PASSED] 32 VFs
[13:54:54] [PASSED] 33 VFs
[13:54:54] [PASSED] 34 VFs
[13:54:54] [PASSED] 35 VFs
[13:54:54] [PASSED] 36 VFs
[13:54:54] [PASSED] 37 VFs
[13:54:54] [PASSED] 38 VFs
[13:54:54] [PASSED] 39 VFs
[13:54:54] [PASSED] 40 VFs
[13:54:54] [PASSED] 41 VFs
[13:54:54] [PASSED] 42 VFs
[13:54:54] [PASSED] 43 VFs
[13:54:54] [PASSED] 44 VFs
[13:54:54] [PASSED] 45 VFs
[13:54:54] [PASSED] 46 VFs
[13:54:54] [PASSED] 47 VFs
[13:54:54] [PASSED] 48 VFs
[13:54:54] [PASSED] 49 VFs
[13:54:54] [PASSED] 50 VFs
[13:54:54] [PASSED] 51 VFs
[13:54:54] [PASSED] 52 VFs
[13:54:55] [PASSED] 53 VFs
[13:54:55] [PASSED] 54 VFs
[13:54:55] [PASSED] 55 VFs
[13:54:55] [PASSED] 56 VFs
[13:54:55] [PASSED] 57 VFs
[13:54:55] [PASSED] 58 VFs
[13:54:55] [PASSED] 59 VFs
[13:54:55] [PASSED] 60 VFs
[13:54:55] [PASSED] 61 VFs
[13:54:55] [PASSED] 62 VFs
[13:54:55] [PASSED] 63 VFs
[13:54:55] ==================== [PASSED] fair_ggtt ====================
[13:54:55] ======================== fair_vram ========================
[13:54:55] [PASSED] 1 VF
[13:54:55] [PASSED] 2 VFs
[13:54:55] [PASSED] 3 VFs
[13:54:55] [PASSED] 4 VFs
[13:54:55] [PASSED] 5 VFs
[13:54:55] [PASSED] 6 VFs
[13:54:55] [PASSED] 7 VFs
[13:54:55] [PASSED] 8 VFs
[13:54:55] [PASSED] 9 VFs
[13:54:55] [PASSED] 10 VFs
[13:54:55] [PASSED] 11 VFs
[13:54:55] [PASSED] 12 VFs
[13:54:55] [PASSED] 13 VFs
[13:54:55] [PASSED] 14 VFs
[13:54:55] [PASSED] 15 VFs
[13:54:55] [PASSED] 16 VFs
[13:54:55] [PASSED] 17 VFs
[13:54:55] [PASSED] 18 VFs
[13:54:55] [PASSED] 19 VFs
[13:54:55] [PASSED] 20 VFs
[13:54:55] [PASSED] 21 VFs
[13:54:55] [PASSED] 22 VFs
[13:54:55] [PASSED] 23 VFs
[13:54:55] [PASSED] 24 VFs
[13:54:55] [PASSED] 25 VFs
[13:54:55] [PASSED] 26 VFs
[13:54:55] [PASSED] 27 VFs
[13:54:55] [PASSED] 28 VFs
[13:54:55] [PASSED] 29 VFs
[13:54:55] [PASSED] 30 VFs
[13:54:55] [PASSED] 31 VFs
[13:54:55] [PASSED] 32 VFs
[13:54:55] [PASSED] 33 VFs
[13:54:55] [PASSED] 34 VFs
[13:54:55] [PASSED] 35 VFs
[13:54:55] [PASSED] 36 VFs
[13:54:55] [PASSED] 37 VFs
[13:54:55] [PASSED] 38 VFs
[13:54:55] [PASSED] 39 VFs
[13:54:55] [PASSED] 40 VFs
[13:54:55] [PASSED] 41 VFs
[13:54:55] [PASSED] 42 VFs
[13:54:55] [PASSED] 43 VFs
[13:54:55] [PASSED] 44 VFs
[13:54:55] [PASSED] 45 VFs
[13:54:55] [PASSED] 46 VFs
[13:54:55] [PASSED] 47 VFs
[13:54:55] [PASSED] 48 VFs
[13:54:55] [PASSED] 49 VFs
[13:54:55] [PASSED] 50 VFs
[13:54:55] [PASSED] 51 VFs
[13:54:55] [PASSED] 52 VFs
[13:54:55] [PASSED] 53 VFs
[13:54:55] [PASSED] 54 VFs
[13:54:55] [PASSED] 55 VFs
[13:54:55] [PASSED] 56 VFs
[13:54:55] [PASSED] 57 VFs
[13:54:55] [PASSED] 58 VFs
[13:54:55] [PASSED] 59 VFs
[13:54:55] [PASSED] 60 VFs
[13:54:55] [PASSED] 61 VFs
[13:54:55] [PASSED] 62 VFs
[13:54:55] [PASSED] 63 VFs
[13:54:55] ==================== [PASSED] fair_vram ====================
[13:54:55] ================== [PASSED] pf_gt_config ===================
[13:54:55] ===================== lmtt (1 subtest) =====================
[13:54:55] ======================== test_ops =========================
[13:54:55] [PASSED] 2-level
[13:54:55] [PASSED] multi-level
[13:54:55] ==================== [PASSED] test_ops =====================
[13:54:55] ====================== [PASSED] lmtt =======================
[13:54:55] ================= sriov_packet (1 subtest) =================
[13:54:55] [PASSED] test_descriptor_init
[13:54:55] ================== [PASSED] sriov_packet ===================
[13:54:55] ================= pf_service (11 subtests) =================
[13:54:55] [PASSED] pf_negotiate_any
[13:54:55] [PASSED] pf_negotiate_base_match
[13:54:55] [PASSED] pf_negotiate_base_newer
[13:54:55] [PASSED] pf_negotiate_base_next
[13:54:55] [SKIPPED] pf_negotiate_base_older (no older minor)
[13:54:55] [PASSED] pf_negotiate_base_prev
[13:54:55] [PASSED] pf_negotiate_latest_match
[13:54:55] [PASSED] pf_negotiate_latest_newer
[13:54:55] [PASSED] pf_negotiate_latest_next
[13:54:55] [SKIPPED] pf_negotiate_latest_older (no older minor)
[13:54:55] [SKIPPED] pf_negotiate_latest_prev (no prev major)
[13:54:55] =================== [PASSED] pf_service ====================
[13:54:55] ================= xe_guc_g2g (2 subtests) ==================
[13:54:55] ============== xe_live_guc_g2g_kunit_default ==============
[13:54:55] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[13:54:55] ============== xe_live_guc_g2g_kunit_allmem ===============
[13:54:55] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[13:54:55] =================== [SKIPPED] xe_guc_g2g ===================
[13:54:55] =================== xe_mocs (2 subtests) ===================
[13:54:55] ================ xe_live_mocs_kernel_kunit ================
[13:54:55] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[13:54:55] ================ xe_live_mocs_reset_kunit =================
[13:54:55] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[13:54:55] ==================== [SKIPPED] xe_mocs =====================
[13:54:55] ================= xe_migrate (2 subtests) ==================
[13:54:55] ================= xe_migrate_sanity_kunit =================
[13:54:55] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[13:54:55] ================== xe_validate_ccs_kunit ==================
[13:54:55] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[13:54:55] =================== [SKIPPED] xe_migrate ===================
[13:54:55] ================== xe_dma_buf (1 subtest) ==================
[13:54:55] ==================== xe_dma_buf_kunit =====================
[13:54:55] ================ [SKIPPED] xe_dma_buf_kunit ================
[13:54:55] =================== [SKIPPED] xe_dma_buf ===================
[13:54:55] ================= xe_bo_shrink (1 subtest) =================
[13:54:55] =================== xe_bo_shrink_kunit ====================
[13:54:55] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[13:54:55] ================== [SKIPPED] xe_bo_shrink ==================
[13:54:55] ==================== xe_bo (2 subtests) ====================
[13:54:55] ================== xe_ccs_migrate_kunit ===================
[13:54:55] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[13:54:55] ==================== xe_bo_evict_kunit ====================
[13:54:55] =============== [SKIPPED] xe_bo_evict_kunit ================
[13:54:55] ===================== [SKIPPED] xe_bo ======================
[13:54:55] ==================== args (13 subtests) ====================
[13:54:55] [PASSED] count_args_test
[13:54:55] [PASSED] call_args_example
[13:54:55] [PASSED] call_args_test
[13:54:55] [PASSED] drop_first_arg_example
[13:54:55] [PASSED] drop_first_arg_test
[13:54:55] [PASSED] first_arg_example
[13:54:55] [PASSED] first_arg_test
[13:54:55] [PASSED] last_arg_example
[13:54:55] [PASSED] last_arg_test
[13:54:55] [PASSED] pick_arg_example
[13:54:55] [PASSED] if_args_example
[13:54:55] [PASSED] if_args_test
[13:54:55] [PASSED] sep_comma_example
[13:54:55] ====================== [PASSED] args =======================
[13:54:55] =================== xe_pci (3 subtests) ====================
[13:54:55] ==================== check_graphics_ip ====================
[13:54:55] [PASSED] 12.00 Xe_LP
[13:54:55] [PASSED] 12.10 Xe_LP+
[13:54:55] [PASSED] 12.55 Xe_HPG
[13:54:55] [PASSED] 12.60 Xe_HPC
[13:54:55] [PASSED] 12.70 Xe_LPG
[13:54:55] [PASSED] 12.71 Xe_LPG
[13:54:55] [PASSED] 12.74 Xe_LPG+
[13:54:55] [PASSED] 20.01 Xe2_HPG
[13:54:55] [PASSED] 20.02 Xe2_HPG
[13:54:55] [PASSED] 20.04 Xe2_LPG
[13:54:55] [PASSED] 30.00 Xe3_LPG
[13:54:55] [PASSED] 30.01 Xe3_LPG
[13:54:55] [PASSED] 30.03 Xe3_LPG
[13:54:55] [PASSED] 30.04 Xe3_LPG
[13:54:55] [PASSED] 30.05 Xe3_LPG
[13:54:55] [PASSED] 35.10 Xe3p_LPG
[13:54:55] [PASSED] 35.11 Xe3p_XPC
[13:54:55] ================ [PASSED] check_graphics_ip ================
[13:54:55] ===================== check_media_ip ======================
[13:54:55] [PASSED] 12.00 Xe_M
[13:54:55] [PASSED] 12.55 Xe_HPM
[13:54:55] [PASSED] 13.00 Xe_LPM+
[13:54:55] [PASSED] 13.01 Xe2_HPM
[13:54:55] [PASSED] 20.00 Xe2_LPM
[13:54:55] [PASSED] 30.00 Xe3_LPM
[13:54:55] [PASSED] 30.02 Xe3_LPM
[13:54:55] [PASSED] 35.00 Xe3p_LPM
[13:54:55] [PASSED] 35.03 Xe3p_HPM
[13:54:55] ================= [PASSED] check_media_ip ==================
[13:54:55] =================== check_platform_desc ===================
[13:54:55] [PASSED] 0x9A60 (TIGERLAKE)
[13:54:55] [PASSED] 0x9A68 (TIGERLAKE)
[13:54:55] [PASSED] 0x9A70 (TIGERLAKE)
[13:54:55] [PASSED] 0x9A40 (TIGERLAKE)
[13:54:55] [PASSED] 0x9A49 (TIGERLAKE)
[13:54:55] [PASSED] 0x9A59 (TIGERLAKE)
[13:54:55] [PASSED] 0x9A78 (TIGERLAKE)
[13:54:55] [PASSED] 0x9AC0 (TIGERLAKE)
[13:54:55] [PASSED] 0x9AC9 (TIGERLAKE)
[13:54:55] [PASSED] 0x9AD9 (TIGERLAKE)
[13:54:55] [PASSED] 0x9AF8 (TIGERLAKE)
[13:54:55] [PASSED] 0x4C80 (ROCKETLAKE)
[13:54:55] [PASSED] 0x4C8A (ROCKETLAKE)
[13:54:55] [PASSED] 0x4C8B (ROCKETLAKE)
[13:54:55] [PASSED] 0x4C8C (ROCKETLAKE)
[13:54:55] [PASSED] 0x4C90 (ROCKETLAKE)
[13:54:55] [PASSED] 0x4C9A (ROCKETLAKE)
[13:54:55] [PASSED] 0x4680 (ALDERLAKE_S)
[13:54:55] [PASSED] 0x4682 (ALDERLAKE_S)
[13:54:55] [PASSED] 0x4688 (ALDERLAKE_S)
[13:54:55] [PASSED] 0x468A (ALDERLAKE_S)
[13:54:55] [PASSED] 0x468B (ALDERLAKE_S)
[13:54:55] [PASSED] 0x4690 (ALDERLAKE_S)
[13:54:55] [PASSED] 0x4692 (ALDERLAKE_S)
[13:54:55] [PASSED] 0x4693 (ALDERLAKE_S)
[13:54:55] [PASSED] 0x46A0 (ALDERLAKE_P)
[13:54:55] [PASSED] 0x46A1 (ALDERLAKE_P)
[13:54:55] [PASSED] 0x46A2 (ALDERLAKE_P)
[13:54:55] [PASSED] 0x46A3 (ALDERLAKE_P)
[13:54:55] [PASSED] 0x46A6 (ALDERLAKE_P)
[13:54:55] [PASSED] 0x46A8 (ALDERLAKE_P)
[13:54:55] [PASSED] 0x46AA (ALDERLAKE_P)
[13:54:55] [PASSED] 0x462A (ALDERLAKE_P)
[13:54:55] [PASSED] 0x4626 (ALDERLAKE_P)
[13:54:55] [PASSED] 0x4628 (ALDERLAKE_P)
[13:54:55] [PASSED] 0x46B0 (ALDERLAKE_P)
[13:54:55] [PASSED] 0x46B1 (ALDERLAKE_P)
[13:54:55] [PASSED] 0x46B2 (ALDERLAKE_P)
[13:54:55] [PASSED] 0x46B3 (ALDERLAKE_P)
[13:54:55] [PASSED] 0x46C0 (ALDERLAKE_P)
[13:54:55] [PASSED] 0x46C1 (ALDERLAKE_P)
[13:54:55] [PASSED] 0x46C2 (ALDERLAKE_P)
[13:54:55] [PASSED] 0x46C3 (ALDERLAKE_P)
[13:54:55] [PASSED] 0x46D0 (ALDERLAKE_N)
[13:54:55] [PASSED] 0x46D1 (ALDERLAKE_N)
[13:54:55] [PASSED] 0x46D2 (ALDERLAKE_N)
[13:54:55] [PASSED] 0x46D3 (ALDERLAKE_N)
[13:54:55] [PASSED] 0x46D4 (ALDERLAKE_N)
[13:54:55] [PASSED] 0xA721 (ALDERLAKE_P)
[13:54:55] [PASSED] 0xA7A1 (ALDERLAKE_P)
[13:54:55] [PASSED] 0xA7A9 (ALDERLAKE_P)
[13:54:55] [PASSED] 0xA7AC (ALDERLAKE_P)
[13:54:55] [PASSED] 0xA7AD (ALDERLAKE_P)
[13:54:55] [PASSED] 0xA720 (ALDERLAKE_P)
[13:54:55] [PASSED] 0xA7A0 (ALDERLAKE_P)
[13:54:55] [PASSED] 0xA7A8 (ALDERLAKE_P)
[13:54:55] [PASSED] 0xA7AA (ALDERLAKE_P)
[13:54:55] [PASSED] 0xA7AB (ALDERLAKE_P)
[13:54:55] [PASSED] 0xA780 (ALDERLAKE_S)
[13:54:55] [PASSED] 0xA781 (ALDERLAKE_S)
[13:54:55] [PASSED] 0xA782 (ALDERLAKE_S)
[13:54:55] [PASSED] 0xA783 (ALDERLAKE_S)
[13:54:55] [PASSED] 0xA788 (ALDERLAKE_S)
[13:54:55] [PASSED] 0xA789 (ALDERLAKE_S)
[13:54:55] [PASSED] 0xA78A (ALDERLAKE_S)
[13:54:55] [PASSED] 0xA78B (ALDERLAKE_S)
[13:54:55] [PASSED] 0x4905 (DG1)
[13:54:55] [PASSED] 0x4906 (DG1)
[13:54:55] [PASSED] 0x4907 (DG1)
[13:54:55] [PASSED] 0x4908 (DG1)
[13:54:55] [PASSED] 0x4909 (DG1)
[13:54:55] [PASSED] 0x56C0 (DG2)
[13:54:55] [PASSED] 0x56C2 (DG2)
[13:54:55] [PASSED] 0x56C1 (DG2)
[13:54:55] [PASSED] 0x7D51 (METEORLAKE)
[13:54:55] [PASSED] 0x7DD1 (METEORLAKE)
[13:54:55] [PASSED] 0x7D41 (METEORLAKE)
[13:54:55] [PASSED] 0x7D67 (METEORLAKE)
[13:54:55] [PASSED] 0xB640 (METEORLAKE)
[13:54:55] [PASSED] 0x56A0 (DG2)
[13:54:55] [PASSED] 0x56A1 (DG2)
[13:54:55] [PASSED] 0x56A2 (DG2)
[13:54:55] [PASSED] 0x56BE (DG2)
[13:54:55] [PASSED] 0x56BF (DG2)
[13:54:55] [PASSED] 0x5690 (DG2)
[13:54:55] [PASSED] 0x5691 (DG2)
[13:54:55] [PASSED] 0x5692 (DG2)
[13:54:55] [PASSED] 0x56A5 (DG2)
[13:54:55] [PASSED] 0x56A6 (DG2)
[13:54:55] [PASSED] 0x56B0 (DG2)
[13:54:55] [PASSED] 0x56B1 (DG2)
[13:54:55] [PASSED] 0x56BA (DG2)
[13:54:55] [PASSED] 0x56BB (DG2)
[13:54:55] [PASSED] 0x56BC (DG2)
[13:54:55] [PASSED] 0x56BD (DG2)
[13:54:55] [PASSED] 0x5693 (DG2)
[13:54:55] [PASSED] 0x5694 (DG2)
[13:54:55] [PASSED] 0x5695 (DG2)
[13:54:55] [PASSED] 0x56A3 (DG2)
[13:54:55] [PASSED] 0x56A4 (DG2)
[13:54:55] [PASSED] 0x56B2 (DG2)
[13:54:55] [PASSED] 0x56B3 (DG2)
[13:54:55] [PASSED] 0x5696 (DG2)
[13:54:55] [PASSED] 0x5697 (DG2)
[13:54:55] [PASSED] 0xB69 (PVC)
[13:54:55] [PASSED] 0xB6E (PVC)
[13:54:55] [PASSED] 0xBD4 (PVC)
[13:54:55] [PASSED] 0xBD5 (PVC)
[13:54:55] [PASSED] 0xBD6 (PVC)
[13:54:55] [PASSED] 0xBD7 (PVC)
[13:54:55] [PASSED] 0xBD8 (PVC)
[13:54:55] [PASSED] 0xBD9 (PVC)
[13:54:55] [PASSED] 0xBDA (PVC)
[13:54:55] [PASSED] 0xBDB (PVC)
[13:54:55] [PASSED] 0xBE0 (PVC)
[13:54:55] [PASSED] 0xBE1 (PVC)
[13:54:55] [PASSED] 0xBE5 (PVC)
[13:54:55] [PASSED] 0x7D40 (METEORLAKE)
[13:54:55] [PASSED] 0x7D45 (METEORLAKE)
[13:54:55] [PASSED] 0x7D55 (METEORLAKE)
[13:54:55] [PASSED] 0x7D60 (METEORLAKE)
[13:54:55] [PASSED] 0x7DD5 (METEORLAKE)
[13:54:55] [PASSED] 0x6420 (LUNARLAKE)
[13:54:55] [PASSED] 0x64A0 (LUNARLAKE)
[13:54:55] [PASSED] 0x64B0 (LUNARLAKE)
[13:54:55] [PASSED] 0xE202 (BATTLEMAGE)
[13:54:55] [PASSED] 0xE209 (BATTLEMAGE)
[13:54:55] [PASSED] 0xE20B (BATTLEMAGE)
[13:54:55] [PASSED] 0xE20C (BATTLEMAGE)
[13:54:55] [PASSED] 0xE20D (BATTLEMAGE)
[13:54:55] [PASSED] 0xE210 (BATTLEMAGE)
[13:54:55] [PASSED] 0xE211 (BATTLEMAGE)
[13:54:55] [PASSED] 0xE212 (BATTLEMAGE)
[13:54:55] [PASSED] 0xE216 (BATTLEMAGE)
[13:54:55] [PASSED] 0xE220 (BATTLEMAGE)
[13:54:55] [PASSED] 0xE221 (BATTLEMAGE)
[13:54:55] [PASSED] 0xE222 (BATTLEMAGE)
[13:54:55] [PASSED] 0xE223 (BATTLEMAGE)
[13:54:55] [PASSED] 0xB080 (PANTHERLAKE)
[13:54:55] [PASSED] 0xB081 (PANTHERLAKE)
[13:54:55] [PASSED] 0xB082 (PANTHERLAKE)
[13:54:55] [PASSED] 0xB083 (PANTHERLAKE)
[13:54:55] [PASSED] 0xB084 (PANTHERLAKE)
[13:54:55] [PASSED] 0xB085 (PANTHERLAKE)
[13:54:55] [PASSED] 0xB086 (PANTHERLAKE)
[13:54:55] [PASSED] 0xB087 (PANTHERLAKE)
[13:54:55] [PASSED] 0xB08F (PANTHERLAKE)
[13:54:55] [PASSED] 0xB090 (PANTHERLAKE)
[13:54:55] [PASSED] 0xB0A0 (PANTHERLAKE)
[13:54:55] [PASSED] 0xB0B0 (PANTHERLAKE)
[13:54:55] [PASSED] 0xFD80 (PANTHERLAKE)
[13:54:55] [PASSED] 0xFD81 (PANTHERLAKE)
[13:54:55] [PASSED] 0xD740 (NOVALAKE_S)
[13:54:55] [PASSED] 0xD741 (NOVALAKE_S)
[13:54:55] [PASSED] 0xD742 (NOVALAKE_S)
[13:54:55] [PASSED] 0xD743 (NOVALAKE_S)
[13:54:55] [PASSED] 0xD745 (NOVALAKE_S)
[13:54:55] [PASSED] 0xD74A (NOVALAKE_S)
[13:54:55] [PASSED] 0xD74B (NOVALAKE_S)
[13:54:55] [PASSED] 0x674C (CRESCENTISLAND)
[13:54:55] [PASSED] 0x674D (CRESCENTISLAND)
[13:54:55] [PASSED] 0x674E (CRESCENTISLAND)
[13:54:55] [PASSED] 0x674F (CRESCENTISLAND)
[13:54:55] [PASSED] 0x6750 (CRESCENTISLAND)
[13:54:55] [PASSED] 0xD750 (NOVALAKE_P)
[13:54:55] [PASSED] 0xD751 (NOVALAKE_P)
[13:54:55] [PASSED] 0xD752 (NOVALAKE_P)
[13:54:55] [PASSED] 0xD753 (NOVALAKE_P)
[13:54:55] [PASSED] 0xD754 (NOVALAKE_P)
[13:54:55] [PASSED] 0xD755 (NOVALAKE_P)
[13:54:55] [PASSED] 0xD756 (NOVALAKE_P)
[13:54:55] [PASSED] 0xD757 (NOVALAKE_P)
[13:54:55] [PASSED] 0xD75F (NOVALAKE_P)
[13:54:55] =============== [PASSED] check_platform_desc ===============
[13:54:55] ===================== [PASSED] xe_pci ======================
[13:54:55] ============= xe_rtp_tables_test (5 subtests) ==============
[13:54:55] ================== xe_rtp_table_gt_test ===================
[13:54:55] [PASSED] gt_was/14011060649
[13:54:55] [PASSED] gt_was/14011059788
[13:54:55] [PASSED] gt_was/14015795083
[13:54:55] [PASSED] gt_was/16021867713
[13:54:55] [PASSED] gt_was/14019449301
[13:54:55] [PASSED] gt_was/16028005424
[13:54:55] [PASSED] gt_was/14026578760
[13:54:55] [PASSED] gt_was/1409420604
[13:54:55] [PASSED] gt_was/1408615072
[13:54:55] [PASSED] gt_was/22010523718
[13:54:55] [PASSED] gt_was/14011006942
[13:54:55] [PASSED] gt_was/14014830051
[13:54:55] [PASSED] gt_was/18018781329
[13:54:55] [PASSED] gt_was/1509235366
[13:54:55] [PASSED] gt_was/18018781329
[13:54:55] [PASSED] gt_was/16016694945
[13:54:55] [PASSED] gt_was/14018575942
[13:54:55] [PASSED] gt_was/22016670082
[13:54:55] [PASSED] gt_was/22016670082
[13:54:55] [PASSED] gt_was/14017421178
[13:54:55] [PASSED] gt_was/16025250150
[13:54:55] [PASSED] gt_was/14021871409
[13:54:55] [PASSED] gt_was/16021865536
[13:54:55] [PASSED] gt_was/14021486841
[13:54:55] [PASSED] gt_was/14025160223
[13:54:55] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[13:54:55] [PASSED] gt_was/14025635424
[13:54:55] [PASSED] gt_was/16028005424
[13:54:55] ============== [PASSED] xe_rtp_table_gt_test ===============
[13:54:55] ================== xe_rtp_table_gt_test ===================
[13:54:55] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[13:54:55] [PASSED] gt_tunings/Tuning: 32B Access Enable
[13:54:55] [PASSED] gt_tunings/Tuning: L3 cache
[13:54:55] [PASSED] gt_tunings/Tuning: L3 cache - media
[13:54:55] [PASSED] gt_tunings/Tuning: Compression Overfetch
[13:54:55] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[13:54:55] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[13:54:55] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[13:54:55] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[13:54:55] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[13:54:55] [PASSED] gt_tunings/Tuning: Stateless compression control
[13:54:55] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[13:54:55] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[13:54:55] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[13:54:55] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[13:54:55] ============== [PASSED] xe_rtp_table_gt_test ===============
[13:54:55] ================== xe_rtp_table_oob_test ==================
[13:54:55] [PASSED] oob_was/1607983814
[13:54:55] [PASSED] oob_was/16010904313
[13:54:55] [PASSED] oob_was/18022495364
[13:54:55] [PASSED] oob_was/22012773006
[13:54:55] [PASSED] oob_was/14014475959
[13:54:55] [PASSED] oob_was/22011391025
[13:54:55] [PASSED] oob_was/22012727170
[13:54:55] [PASSED] oob_was/22012727685
[13:54:55] [PASSED] oob_was/22016596838
[13:54:55] [PASSED] oob_was/18020744125
[13:54:55] [PASSED] oob_was/1409600907
[13:54:55] [PASSED] oob_was/22014953428
[13:54:55] [PASSED] oob_was/16017236439
[13:54:55] [PASSED] oob_was/14019821291
[13:54:55] [PASSED] oob_was/14015076503
[13:54:55] [PASSED] oob_was/14018913170
[13:54:55] [PASSED] oob_was/14018094691
[13:54:55] [PASSED] oob_was/18024947630
[13:54:55] [PASSED] oob_was/16022287689
[13:54:55] [PASSED] oob_was/13011645652
[13:54:55] [PASSED] oob_was/14022293748
[13:54:55] [PASSED] oob_was/22019794406
[13:54:55] [PASSED] oob_was/22019338487
[13:54:55] [PASSED] oob_was/16023588340
[13:54:55] [PASSED] oob_was/14019789679
[13:54:55] [PASSED] oob_was/14022866841
[13:54:55] [PASSED] oob_was/16021333562
[13:54:55] [PASSED] oob_was/14016712196
[13:54:55] [PASSED] oob_was/14015568240
[13:54:55] [PASSED] oob_was/18013179988
[13:54:55] [PASSED] oob_was/1508761755
[13:54:55] [PASSED] oob_was/16023105232
[13:54:55] [PASSED] oob_was/16026508708
[13:54:55] [PASSED] oob_was/14020001231
[13:54:55] [PASSED] oob_was/16023683509
[13:54:55] [PASSED] oob_was/14025515070
[13:54:55] [PASSED] oob_was/15015404425_disable
[13:54:55] [PASSED] oob_was/16026007364
[13:54:55] [PASSED] oob_was/14020316580
[13:54:55] [PASSED] oob_was/14025883347
[13:54:55] [PASSED] oob_was/16029380221
[13:54:55] [PASSED] oob_was/22022079272
[13:54:55] [PASSED] oob_was/16029897822
[13:54:55] [PASSED] oob_was/14027054324
[13:54:55] ============== [PASSED] xe_rtp_table_oob_test ==============
[13:54:55] ================ xe_rtp_table_dev_oob_test ================
[13:54:55] [PASSED] device_oob_was/22010954014
[13:54:55] [PASSED] device_oob_was/15015404425
[13:54:55] [PASSED] device_oob_was/22019338487_display
[13:54:55] [PASSED] device_oob_was/14022085890
[13:54:55] [PASSED] device_oob_was/14026539277
[13:54:55] [PASSED] device_oob_was/14026633728
[13:54:55] [PASSED] device_oob_was/14026746987
[13:54:55] [PASSED] device_oob_was/14026779378
[13:54:55] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[13:54:55] ========== xe_rtp_table_missing_upper_bound_test ==========
[13:54:55] [PASSED] register_whitelist/WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865
[13:54:55] [PASSED] register_whitelist/1508744258, 14012131227, 1808121037
[13:54:55] [PASSED] register_whitelist/1806527549
[13:54:55] [PASSED] register_whitelist/allow_read_ctx_timestamp
[13:54:55] [PASSED] register_whitelist/allow_read_queue_timestamp
[13:54:55] [PASSED] register_whitelist/16014440446
[13:54:55] [PASSED] register_whitelist/16017236439
[13:54:55] [PASSED] register_whitelist/16020183090
[13:54:55] [PASSED] register_whitelist/14024997852
[13:54:55] [PASSED] register_whitelist/14024997852
[13:54:55] ====== [PASSED] xe_rtp_table_missing_upper_bound_test ======
[13:54:55] =============== [PASSED] xe_rtp_tables_test ================
[13:54:55] =================== xe_rtp (3 subtests) ====================
[13:54:55] =================== xe_rtp_rules_tests ====================
[13:54:55] [PASSED] no
[13:54:55] [PASSED] yes
[13:54:55] [PASSED] no-and-no
[13:54:55] [PASSED] no-and-yes
[13:54:55] [PASSED] yes-and-no
[13:54:55] [PASSED] yes-and-yes
[13:54:55] [PASSED] no-or-no
[13:54:55] [PASSED] no-or-yes
[13:54:55] [PASSED] yes-or-no
[13:54:55] [PASSED] yes-or-yes
[13:54:55] [PASSED] no-yes-or-yes-no
[13:54:55] [PASSED] no-yes-or-yes-yes
[13:54:55] [PASSED] yes-yes-or-no-yes
[13:54:55] [PASSED] yes-yes-or-yes-yes
[13:54:55] [PASSED] no-no-or-yes-or-no
[13:54:55] [PASSED] or
[13:54:55] [PASSED] or-yes
[13:54:55] [PASSED] or-no
[13:54:55] [PASSED] yes-or
[13:54:55] [PASSED] no-or
[13:54:55] [PASSED] no-or-or-yes
[13:54:55] [PASSED] yes-or-or-no
[13:54:55] [PASSED] no-or-or-no
[13:54:55] [PASSED] missing-context-engine-class
[13:54:55] [PASSED] missing-context-engine-class-or-yes
[13:54:55] [PASSED] missing-context-engine-class-or-or-yes
[13:54:55] =============== [PASSED] xe_rtp_rules_tests ================
[13:54:55] =============== xe_rtp_process_to_sr_tests ================
[13:54:55] [PASSED] coalesce-same-reg
[13:54:55] [PASSED] coalesce-same-reg-literal-and-func
[13:54:55] [PASSED] no-match-no-add
[13:54:55] [PASSED] two-regs-two-entries
[13:54:55] [PASSED] clr-one-set-other
[13:54:55] [PASSED] set-field
[13:54:55] [PASSED] conflict-duplicate
[13:54:55] [PASSED] conflict-not-disjoint
[13:54:55] [PASSED] conflict-not-disjoint-literal-and-func
[13:54:55] [PASSED] conflict-reg-type
[13:54:55] [PASSED] bad-mcr-reg-forced-to-regular
[13:54:55] [PASSED] bad-regular-reg-forced-to-mcr
[13:54:55] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[13:54:55] ================== xe_rtp_process_tests ===================
[13:54:55] [PASSED] active1
[13:54:55] [PASSED] active2
[13:54:55] [PASSED] active-inactive
[13:54:55] [PASSED] inactive-active
[13:54:55] [PASSED] inactive-active-inactive
[13:54:55] [PASSED] inactive-inactive-inactive
[13:54:55] ============== [PASSED] xe_rtp_process_tests ===============
[13:54:55] ===================== [PASSED] xe_rtp ======================
[13:54:55] ==================== xe_wa (1 subtest) =====================
[13:54:55] ======================== xe_wa_gt =========================
[13:54:55] [PASSED] TIGERLAKE B0
[13:54:55] [PASSED] DG1 A0
[13:54:55] [PASSED] DG1 B0
[13:54:55] [PASSED] ALDERLAKE_S A0
[13:54:55] [PASSED] ALDERLAKE_S B0
[13:54:55] [PASSED] ALDERLAKE_S C0
[13:54:55] [PASSED] ALDERLAKE_S D0
[13:54:55] [PASSED] ALDERLAKE_P A0
[13:54:55] [PASSED] ALDERLAKE_P B0
[13:54:55] [PASSED] ALDERLAKE_P C0
[13:54:55] [PASSED] ALDERLAKE_S RPLS D0
[13:54:55] [PASSED] ALDERLAKE_P RPLU E0
[13:54:55] [PASSED] DG2 G10 C0
[13:54:55] [PASSED] DG2 G11 B1
[13:54:55] [PASSED] DG2 G12 A1
[13:54:55] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[13:54:55] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[13:54:55] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[13:54:55] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[13:54:55] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[13:54:55] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[13:54:55] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[13:54:55] ==================== [PASSED] xe_wa_gt =====================
[13:54:55] ====================== [PASSED] xe_wa ======================
[13:54:55] ============================================================
[13:54:55] Testing complete. Ran 742 tests: passed: 724, skipped: 18
[13:54:55] Elapsed time: 36.595s total, 4.437s configuring, 31.492s building, 0.639s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[13:54:55] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[13:54:57] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[13:55:21] Starting KUnit Kernel (1/1)...
[13:55:21] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[13:55:21] ============ drm_test_pick_cmdline (2 subtests) ============
[13:55:21] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[13:55:21] =============== drm_test_pick_cmdline_named ===============
[13:55:21] [PASSED] NTSC
[13:55:21] [PASSED] NTSC-J
[13:55:21] [PASSED] PAL
[13:55:21] [PASSED] PAL-M
[13:55:21] =========== [PASSED] drm_test_pick_cmdline_named ===========
[13:55:21] ============== [PASSED] drm_test_pick_cmdline ==============
[13:55:21] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[13:55:21] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[13:55:21] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[13:55:21] =========== drm_validate_clone_mode (2 subtests) ===========
[13:55:21] ============== drm_test_check_in_clone_mode ===============
[13:55:21] [PASSED] in_clone_mode
[13:55:21] [PASSED] not_in_clone_mode
[13:55:21] ========== [PASSED] drm_test_check_in_clone_mode ===========
[13:55:21] =============== drm_test_check_valid_clones ===============
[13:55:21] [PASSED] not_in_clone_mode
[13:55:21] [PASSED] valid_clone
[13:55:21] [PASSED] invalid_clone
[13:55:21] =========== [PASSED] drm_test_check_valid_clones ===========
[13:55:21] ============= [PASSED] drm_validate_clone_mode =============
[13:55:21] ============= drm_validate_modeset (1 subtest) =============
[13:55:21] [PASSED] drm_test_check_connector_changed_modeset
[13:55:21] ============== [PASSED] drm_validate_modeset ===============
[13:55:21] ====== drm_test_bridge_get_current_state (1 subtest) =======
[13:55:21] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[13:55:21] ======== [PASSED] drm_test_bridge_get_current_state ========
[13:55:21] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[13:55:21] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[13:55:21] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[13:55:21] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[13:55:21] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[13:55:21] ============== drm_bridge_alloc (2 subtests) ===============
[13:55:21] [PASSED] drm_test_drm_bridge_alloc_basic
[13:55:21] [PASSED] drm_test_drm_bridge_alloc_get_put
[13:55:21] ================ [PASSED] drm_bridge_alloc =================
[13:55:21] ============= drm_bridge_bus_fmt (5 subtests) ==============
[13:55:21] [PASSED] drm_test_bridge_rgb_yuv_rgb
[13:55:21] [PASSED] drm_test_bridge_must_convert_to_yuv444
[13:55:21] [PASSED] drm_test_bridge_hdmi_auto_rgb
[13:55:21] [PASSED] drm_test_bridge_auto_first
[13:55:21] [PASSED] drm_test_bridge_rgb_yuv_no_path
[13:55:21] =============== [PASSED] drm_bridge_bus_fmt ================
[13:55:21] ============= drm_cmdline_parser (40 subtests) =============
[13:55:21] [PASSED] drm_test_cmdline_force_d_only
[13:55:21] [PASSED] drm_test_cmdline_force_D_only_dvi
[13:55:21] [PASSED] drm_test_cmdline_force_D_only_hdmi
[13:55:21] [PASSED] drm_test_cmdline_force_D_only_not_digital
[13:55:21] [PASSED] drm_test_cmdline_force_e_only
[13:55:21] [PASSED] drm_test_cmdline_res
[13:55:21] [PASSED] drm_test_cmdline_res_vesa
[13:55:21] [PASSED] drm_test_cmdline_res_vesa_rblank
[13:55:21] [PASSED] drm_test_cmdline_res_rblank
[13:55:21] [PASSED] drm_test_cmdline_res_bpp
[13:55:21] [PASSED] drm_test_cmdline_res_refresh
[13:55:21] [PASSED] drm_test_cmdline_res_bpp_refresh
[13:55:21] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[13:55:21] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[13:55:21] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[13:55:21] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[13:55:21] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[13:55:21] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[13:55:21] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[13:55:21] [PASSED] drm_test_cmdline_res_margins_force_on
[13:55:21] [PASSED] drm_test_cmdline_res_vesa_margins
[13:55:21] [PASSED] drm_test_cmdline_name
[13:55:21] [PASSED] drm_test_cmdline_name_bpp
[13:55:21] [PASSED] drm_test_cmdline_name_option
[13:55:21] [PASSED] drm_test_cmdline_name_bpp_option
[13:55:21] [PASSED] drm_test_cmdline_rotate_0
[13:55:21] [PASSED] drm_test_cmdline_rotate_90
[13:55:21] [PASSED] drm_test_cmdline_rotate_180
[13:55:21] [PASSED] drm_test_cmdline_rotate_270
[13:55:21] [PASSED] drm_test_cmdline_hmirror
[13:55:21] [PASSED] drm_test_cmdline_vmirror
[13:55:21] [PASSED] drm_test_cmdline_margin_options
[13:55:21] [PASSED] drm_test_cmdline_multiple_options
[13:55:21] [PASSED] drm_test_cmdline_bpp_extra_and_option
[13:55:21] [PASSED] drm_test_cmdline_extra_and_option
[13:55:21] [PASSED] drm_test_cmdline_freestanding_options
[13:55:21] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[13:55:21] [PASSED] drm_test_cmdline_panel_orientation
[13:55:21] ================ drm_test_cmdline_invalid =================
[13:55:21] [PASSED] margin_only
[13:55:21] [PASSED] interlace_only
[13:55:21] [PASSED] res_missing_x
[13:55:21] [PASSED] res_missing_y
[13:55:21] [PASSED] res_bad_y
[13:55:21] [PASSED] res_missing_y_bpp
[13:55:21] [PASSED] res_bad_bpp
[13:55:21] [PASSED] res_bad_refresh
[13:55:21] [PASSED] res_bpp_refresh_force_on_off
[13:55:21] [PASSED] res_invalid_mode
[13:55:21] [PASSED] res_bpp_wrong_place_mode
[13:55:21] [PASSED] name_bpp_refresh
[13:55:21] [PASSED] name_refresh
[13:55:21] [PASSED] name_refresh_wrong_mode
[13:55:21] [PASSED] name_refresh_invalid_mode
[13:55:21] [PASSED] rotate_multiple
[13:55:21] [PASSED] rotate_invalid_val
[13:55:21] [PASSED] rotate_truncated
[13:55:21] [PASSED] invalid_option
[13:55:21] [PASSED] invalid_tv_option
[13:55:21] [PASSED] truncated_tv_option
[13:55:21] ============ [PASSED] drm_test_cmdline_invalid =============
[13:55:21] =============== drm_test_cmdline_tv_options ===============
[13:55:21] [PASSED] NTSC
[13:55:21] [PASSED] NTSC_443
[13:55:21] [PASSED] NTSC_J
[13:55:21] [PASSED] PAL
[13:55:21] [PASSED] PAL_M
[13:55:21] [PASSED] PAL_N
[13:55:21] [PASSED] SECAM
[13:55:21] [PASSED] MONO_525
[13:55:21] [PASSED] MONO_625
[13:55:21] =========== [PASSED] drm_test_cmdline_tv_options ===========
[13:55:21] =============== [PASSED] drm_cmdline_parser ================
[13:55:21] ========== drmm_connector_hdmi_init (20 subtests) ==========
[13:55:21] [PASSED] drm_test_connector_hdmi_init_valid
[13:55:21] [PASSED] drm_test_connector_hdmi_init_bpc_8
[13:55:21] [PASSED] drm_test_connector_hdmi_init_bpc_10
[13:55:21] [PASSED] drm_test_connector_hdmi_init_bpc_12
[13:55:21] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[13:55:21] [PASSED] drm_test_connector_hdmi_init_bpc_null
[13:55:21] [PASSED] drm_test_connector_hdmi_init_formats_empty
[13:55:21] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[13:55:21] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[13:55:21] [PASSED] supported_formats=0x9 yuv420_allowed=1
[13:55:21] [PASSED] supported_formats=0x9 yuv420_allowed=0
[13:55:21] [PASSED] supported_formats=0x5 yuv420_allowed=1
[13:55:21] [PASSED] supported_formats=0x5 yuv420_allowed=0
[13:55:21] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[13:55:21] [PASSED] drm_test_connector_hdmi_init_null_ddc
[13:55:21] [PASSED] drm_test_connector_hdmi_init_null_product
[13:55:21] [PASSED] drm_test_connector_hdmi_init_null_vendor
[13:55:21] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[13:55:21] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[13:55:21] [PASSED] drm_test_connector_hdmi_init_product_valid
[13:55:21] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[13:55:21] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[13:55:21] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[13:55:21] ========= drm_test_connector_hdmi_init_type_valid =========
[13:55:21] [PASSED] HDMI-A
[13:55:21] [PASSED] HDMI-B
[13:55:21] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[13:55:21] ======== drm_test_connector_hdmi_init_type_invalid ========
[13:55:21] [PASSED] Unknown
[13:55:21] [PASSED] VGA
[13:55:21] [PASSED] DVI-I
[13:55:21] [PASSED] DVI-D
[13:55:21] [PASSED] DVI-A
[13:55:21] [PASSED] Composite
[13:55:21] [PASSED] SVIDEO
[13:55:21] [PASSED] LVDS
[13:55:21] [PASSED] Component
[13:55:21] [PASSED] DIN
[13:55:21] [PASSED] DP
[13:55:21] [PASSED] TV
[13:55:21] [PASSED] eDP
[13:55:21] [PASSED] Virtual
[13:55:21] [PASSED] DSI
[13:55:21] [PASSED] DPI
[13:55:21] [PASSED] Writeback
[13:55:21] [PASSED] SPI
[13:55:21] [PASSED] USB
[13:55:21] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[13:55:21] ============ [PASSED] drmm_connector_hdmi_init =============
[13:55:21] ============= drmm_connector_init (3 subtests) =============
[13:55:21] [PASSED] drm_test_drmm_connector_init
[13:55:21] [PASSED] drm_test_drmm_connector_init_null_ddc
[13:55:21] ========= drm_test_drmm_connector_init_type_valid =========
[13:55:21] [PASSED] Unknown
[13:55:21] [PASSED] VGA
[13:55:21] [PASSED] DVI-I
[13:55:21] [PASSED] DVI-D
[13:55:21] [PASSED] DVI-A
[13:55:21] [PASSED] Composite
[13:55:21] [PASSED] SVIDEO
[13:55:21] [PASSED] LVDS
[13:55:21] [PASSED] Component
[13:55:21] [PASSED] DIN
[13:55:21] [PASSED] DP
[13:55:21] [PASSED] HDMI-A
[13:55:21] [PASSED] HDMI-B
[13:55:21] [PASSED] TV
[13:55:21] [PASSED] eDP
[13:55:21] [PASSED] Virtual
[13:55:21] [PASSED] DSI
[13:55:21] [PASSED] DPI
[13:55:21] [PASSED] Writeback
[13:55:21] [PASSED] SPI
[13:55:21] [PASSED] USB
[13:55:21] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[13:55:21] =============== [PASSED] drmm_connector_init ===============
[13:55:21] ========= drm_connector_dynamic_init (6 subtests) ==========
[13:55:21] [PASSED] drm_test_drm_connector_dynamic_init
[13:55:21] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[13:55:21] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[13:55:21] [PASSED] drm_test_drm_connector_dynamic_init_properties
[13:55:21] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[13:55:21] [PASSED] Unknown
[13:55:21] [PASSED] VGA
[13:55:21] [PASSED] DVI-I
[13:55:21] [PASSED] DVI-D
[13:55:21] [PASSED] DVI-A
[13:55:21] [PASSED] Composite
[13:55:21] [PASSED] SVIDEO
[13:55:21] [PASSED] LVDS
[13:55:21] [PASSED] Component
[13:55:21] [PASSED] DIN
[13:55:21] [PASSED] DP
[13:55:21] [PASSED] HDMI-A
[13:55:21] [PASSED] HDMI-B
[13:55:21] [PASSED] TV
[13:55:21] [PASSED] eDP
[13:55:21] [PASSED] Virtual
[13:55:21] [PASSED] DSI
[13:55:21] [PASSED] DPI
[13:55:21] [PASSED] Writeback
[13:55:21] [PASSED] SPI
[13:55:21] [PASSED] USB
[13:55:21] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[13:55:21] ======== drm_test_drm_connector_dynamic_init_name =========
[13:55:21] [PASSED] Unknown
[13:55:21] [PASSED] VGA
[13:55:21] [PASSED] DVI-I
[13:55:21] [PASSED] DVI-D
[13:55:21] [PASSED] DVI-A
[13:55:21] [PASSED] Composite
[13:55:21] [PASSED] SVIDEO
[13:55:21] [PASSED] LVDS
[13:55:21] [PASSED] Component
[13:55:21] [PASSED] DIN
[13:55:21] [PASSED] DP
[13:55:21] [PASSED] HDMI-A
[13:55:21] [PASSED] HDMI-B
[13:55:21] [PASSED] TV
[13:55:21] [PASSED] eDP
[13:55:21] [PASSED] Virtual
[13:55:21] [PASSED] DSI
[13:55:21] [PASSED] DPI
[13:55:21] [PASSED] Writeback
[13:55:21] [PASSED] SPI
[13:55:21] [PASSED] USB
[13:55:21] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[13:55:21] =========== [PASSED] drm_connector_dynamic_init ============
[13:55:21] ==== drm_connector_dynamic_register_early (4 subtests) =====
[13:55:21] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[13:55:21] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[13:55:21] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[13:55:21] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[13:55:21] ====== [PASSED] drm_connector_dynamic_register_early =======
[13:55:21] ======= drm_connector_dynamic_register (7 subtests) ========
[13:55:21] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[13:55:21] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[13:55:21] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[13:55:21] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[13:55:21] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[13:55:21] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[13:55:21] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[13:55:21] ========= [PASSED] drm_connector_dynamic_register ==========
[13:55:21] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[13:55:21] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[13:55:21] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[13:55:21] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[13:55:21] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[13:55:21] ========== drm_test_get_tv_mode_from_name_valid ===========
[13:55:21] [PASSED] NTSC
[13:55:21] [PASSED] NTSC-443
[13:55:21] [PASSED] NTSC-J
[13:55:21] [PASSED] PAL
[13:55:21] [PASSED] PAL-M
[13:55:21] [PASSED] PAL-N
[13:55:21] [PASSED] SECAM
[13:55:21] [PASSED] Mono
[13:55:21] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[13:55:21] [PASSED] drm_test_get_tv_mode_from_name_truncated
[13:55:21] ============ [PASSED] drm_get_tv_mode_from_name ============
[13:55:21] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[13:55:21] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[13:55:21] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[13:55:21] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[13:55:21] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[13:55:21] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[13:55:21] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[13:55:21] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[13:55:21] [PASSED] VIC 96
[13:55:21] [PASSED] VIC 97
[13:55:21] [PASSED] VIC 101
[13:55:21] [PASSED] VIC 102
[13:55:21] [PASSED] VIC 106
[13:55:21] [PASSED] VIC 107
[13:55:21] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[13:55:21] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[13:55:21] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[13:55:21] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[13:55:21] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[13:55:21] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[13:55:21] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[13:55:21] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[13:55:21] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[13:55:21] [PASSED] Automatic
[13:55:21] [PASSED] Full
[13:55:21] [PASSED] Limited 16:235
[13:55:21] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[13:55:21] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[13:55:21] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[13:55:21] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[13:55:21] === drm_test_drm_hdmi_connector_get_output_format_name ====
[13:55:21] [PASSED] RGB
[13:55:21] [PASSED] YUV 4:2:0
[13:55:21] [PASSED] YUV 4:2:2
[13:55:21] [PASSED] YUV 4:4:4
[13:55:21] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[13:55:21] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[13:55:21] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[13:55:21] ============= drm_damage_helper (21 subtests) ==============
[13:55:21] [PASSED] drm_test_damage_iter_no_damage
[13:55:21] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[13:55:21] [PASSED] drm_test_damage_iter_no_damage_src_moved
[13:55:21] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[13:55:21] [PASSED] drm_test_damage_iter_no_damage_not_visible
[13:55:21] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[13:55:21] [PASSED] drm_test_damage_iter_no_damage_no_fb
[13:55:21] [PASSED] drm_test_damage_iter_simple_damage
[13:55:21] [PASSED] drm_test_damage_iter_single_damage
[13:55:21] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[13:55:21] [PASSED] drm_test_damage_iter_single_damage_outside_src
[13:55:21] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[13:55:21] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[13:55:21] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[13:55:21] [PASSED] drm_test_damage_iter_single_damage_src_moved
[13:55:21] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[13:55:21] [PASSED] drm_test_damage_iter_damage
[13:55:21] [PASSED] drm_test_damage_iter_damage_one_intersect
[13:55:21] [PASSED] drm_test_damage_iter_damage_one_outside
[13:55:21] [PASSED] drm_test_damage_iter_damage_src_moved
[13:55:21] [PASSED] drm_test_damage_iter_damage_not_visible
[13:55:21] ================ [PASSED] drm_damage_helper ================
[13:55:21] ============== drm_dp_mst_helper (3 subtests) ==============
[13:55:21] ============== drm_test_dp_mst_calc_pbn_mode ==============
[13:55:21] [PASSED] Clock 154000 BPP 30 DSC disabled
[13:55:21] [PASSED] Clock 234000 BPP 30 DSC disabled
[13:55:21] [PASSED] Clock 297000 BPP 24 DSC disabled
[13:55:21] [PASSED] Clock 332880 BPP 24 DSC enabled
[13:55:21] [PASSED] Clock 324540 BPP 24 DSC enabled
[13:55:21] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[13:55:21] ============== drm_test_dp_mst_calc_pbn_div ===============
[13:55:21] [PASSED] Link rate 2000000 lane count 4
[13:55:21] [PASSED] Link rate 2000000 lane count 2
[13:55:21] [PASSED] Link rate 2000000 lane count 1
[13:55:21] [PASSED] Link rate 1350000 lane count 4
[13:55:21] [PASSED] Link rate 1350000 lane count 2
[13:55:21] [PASSED] Link rate 1350000 lane count 1
[13:55:21] [PASSED] Link rate 1000000 lane count 4
[13:55:21] [PASSED] Link rate 1000000 lane count 2
[13:55:21] [PASSED] Link rate 1000000 lane count 1
[13:55:21] [PASSED] Link rate 810000 lane count 4
[13:55:21] [PASSED] Link rate 810000 lane count 2
[13:55:21] [PASSED] Link rate 810000 lane count 1
[13:55:21] [PASSED] Link rate 540000 lane count 4
[13:55:21] [PASSED] Link rate 540000 lane count 2
[13:55:21] [PASSED] Link rate 540000 lane count 1
[13:55:21] [PASSED] Link rate 270000 lane count 4
[13:55:21] [PASSED] Link rate 270000 lane count 2
[13:55:21] [PASSED] Link rate 270000 lane count 1
[13:55:21] [PASSED] Link rate 162000 lane count 4
[13:55:21] [PASSED] Link rate 162000 lane count 2
[13:55:21] [PASSED] Link rate 162000 lane count 1
[13:55:21] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[13:55:21] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[13:55:21] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[13:55:21] [PASSED] DP_POWER_UP_PHY with port number
[13:55:21] [PASSED] DP_POWER_DOWN_PHY with port number
[13:55:21] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[13:55:21] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[13:55:21] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[13:55:21] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[13:55:21] [PASSED] DP_QUERY_PAYLOAD with port number
[13:55:21] [PASSED] DP_QUERY_PAYLOAD with VCPI
[13:55:21] [PASSED] DP_REMOTE_DPCD_READ with port number
[13:55:21] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[13:55:21] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[13:55:21] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[13:55:21] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[13:55:21] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[13:55:21] [PASSED] DP_REMOTE_I2C_READ with port number
[13:55:21] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[13:55:21] [PASSED] DP_REMOTE_I2C_READ with transactions array
[13:55:21] [PASSED] DP_REMOTE_I2C_WRITE with port number
[13:55:21] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[13:55:21] [PASSED] DP_REMOTE_I2C_WRITE with data array
[13:55:21] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[13:55:21] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[13:55:21] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[13:55:21] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[13:55:21] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[13:55:21] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[13:55:21] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[13:55:21] ================ [PASSED] drm_dp_mst_helper ================
[13:55:21] ================== drm_exec (7 subtests) ===================
[13:55:21] [PASSED] sanitycheck
[13:55:21] [PASSED] test_lock
[13:55:21] [PASSED] test_lock_unlock
[13:55:21] [PASSED] test_duplicates
[13:55:21] [PASSED] test_prepare
[13:55:21] [PASSED] test_prepare_array
[13:55:21] [PASSED] test_multiple_loops
[13:55:21] ==================== [PASSED] drm_exec =====================
[13:55:21] =========== drm_format_helper_test (17 subtests) ===========
[13:55:21] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[13:55:21] [PASSED] single_pixel_source_buffer
[13:55:21] [PASSED] single_pixel_clip_rectangle
[13:55:21] [PASSED] well_known_colors
[13:55:21] [PASSED] destination_pitch
[13:55:21] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[13:55:21] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[13:55:21] [PASSED] single_pixel_source_buffer
[13:55:21] [PASSED] single_pixel_clip_rectangle
[13:55:21] [PASSED] well_known_colors
[13:55:21] [PASSED] destination_pitch
[13:55:21] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[13:55:21] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[13:55:21] [PASSED] single_pixel_source_buffer
[13:55:21] [PASSED] single_pixel_clip_rectangle
[13:55:21] [PASSED] well_known_colors
[13:55:21] [PASSED] destination_pitch
[13:55:21] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[13:55:21] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[13:55:21] [PASSED] single_pixel_source_buffer
[13:55:21] [PASSED] single_pixel_clip_rectangle
[13:55:21] [PASSED] well_known_colors
[13:55:21] [PASSED] destination_pitch
[13:55:21] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[13:55:21] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[13:55:21] [PASSED] single_pixel_source_buffer
[13:55:21] [PASSED] single_pixel_clip_rectangle
[13:55:21] [PASSED] well_known_colors
[13:55:21] [PASSED] destination_pitch
[13:55:21] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[13:55:21] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[13:55:21] [PASSED] single_pixel_source_buffer
[13:55:21] [PASSED] single_pixel_clip_rectangle
[13:55:21] [PASSED] well_known_colors
[13:55:21] [PASSED] destination_pitch
[13:55:21] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[13:55:21] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[13:55:21] [PASSED] single_pixel_source_buffer
[13:55:21] [PASSED] single_pixel_clip_rectangle
[13:55:21] [PASSED] well_known_colors
[13:55:21] [PASSED] destination_pitch
[13:55:21] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[13:55:21] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[13:55:21] [PASSED] single_pixel_source_buffer
[13:55:21] [PASSED] single_pixel_clip_rectangle
[13:55:21] [PASSED] well_known_colors
[13:55:21] [PASSED] destination_pitch
[13:55:21] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[13:55:21] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[13:55:21] [PASSED] single_pixel_source_buffer
[13:55:21] [PASSED] single_pixel_clip_rectangle
[13:55:21] [PASSED] well_known_colors
[13:55:21] [PASSED] destination_pitch
[13:55:21] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[13:55:21] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[13:55:21] [PASSED] single_pixel_source_buffer
[13:55:21] [PASSED] single_pixel_clip_rectangle
[13:55:21] [PASSED] well_known_colors
[13:55:21] [PASSED] destination_pitch
[13:55:21] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[13:55:21] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[13:55:21] [PASSED] single_pixel_source_buffer
[13:55:21] [PASSED] single_pixel_clip_rectangle
[13:55:21] [PASSED] well_known_colors
[13:55:21] [PASSED] destination_pitch
[13:55:21] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[13:55:21] ============== drm_test_fb_xrgb8888_to_mono ===============
[13:55:21] [PASSED] single_pixel_source_buffer
[13:55:21] [PASSED] single_pixel_clip_rectangle
[13:55:21] [PASSED] well_known_colors
[13:55:21] [PASSED] destination_pitch
[13:55:21] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[13:55:21] ==================== drm_test_fb_swab =====================
[13:55:21] [PASSED] single_pixel_source_buffer
[13:55:21] [PASSED] single_pixel_clip_rectangle
[13:55:21] [PASSED] well_known_colors
[13:55:21] [PASSED] destination_pitch
[13:55:21] ================ [PASSED] drm_test_fb_swab =================
[13:55:21] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[13:55:21] [PASSED] single_pixel_source_buffer
[13:55:21] [PASSED] single_pixel_clip_rectangle
[13:55:21] [PASSED] well_known_colors
[13:55:21] [PASSED] destination_pitch
[13:55:21] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[13:55:21] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[13:55:21] [PASSED] single_pixel_source_buffer
[13:55:21] [PASSED] single_pixel_clip_rectangle
[13:55:21] [PASSED] well_known_colors
[13:55:21] [PASSED] destination_pitch
[13:55:21] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[13:55:21] ================= drm_test_fb_clip_offset =================
[13:55:21] [PASSED] pass through
[13:55:21] [PASSED] horizontal offset
[13:55:21] [PASSED] vertical offset
[13:55:21] [PASSED] horizontal and vertical offset
[13:55:21] [PASSED] horizontal offset (custom pitch)
[13:55:21] [PASSED] vertical offset (custom pitch)
[13:55:21] [PASSED] horizontal and vertical offset (custom pitch)
[13:55:21] ============= [PASSED] drm_test_fb_clip_offset =============
[13:55:21] =================== drm_test_fb_memcpy ====================
[13:55:21] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[13:55:21] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[13:55:21] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[13:55:21] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[13:55:21] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[13:55:21] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[13:55:21] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[13:55:21] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[13:55:21] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[13:55:21] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[13:55:21] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[13:55:21] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[13:55:21] =============== [PASSED] drm_test_fb_memcpy ================
[13:55:21] ============= [PASSED] drm_format_helper_test ==============
[13:55:21] ================= drm_format (18 subtests) =================
[13:55:21] [PASSED] drm_test_format_block_width_invalid
[13:55:21] [PASSED] drm_test_format_block_width_one_plane
[13:55:21] [PASSED] drm_test_format_block_width_two_plane
[13:55:21] [PASSED] drm_test_format_block_width_three_plane
[13:55:21] [PASSED] drm_test_format_block_width_tiled
[13:55:21] [PASSED] drm_test_format_block_height_invalid
[13:55:21] [PASSED] drm_test_format_block_height_one_plane
[13:55:21] [PASSED] drm_test_format_block_height_two_plane
[13:55:21] [PASSED] drm_test_format_block_height_three_plane
[13:55:21] [PASSED] drm_test_format_block_height_tiled
[13:55:21] [PASSED] drm_test_format_min_pitch_invalid
[13:55:21] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[13:55:21] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[13:55:21] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[13:55:21] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[13:55:21] [PASSED] drm_test_format_min_pitch_two_plane
[13:55:21] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[13:55:21] [PASSED] drm_test_format_min_pitch_tiled
[13:55:21] =================== [PASSED] drm_format ====================
[13:55:21] ============== drm_framebuffer (10 subtests) ===============
[13:55:21] ========== drm_test_framebuffer_check_src_coords ==========
[13:55:21] [PASSED] Success: source fits into fb
[13:55:21] [PASSED] Fail: overflowing fb with x-axis coordinate
[13:55:21] [PASSED] Fail: overflowing fb with y-axis coordinate
[13:55:21] [PASSED] Fail: overflowing fb with source width
[13:55:21] [PASSED] Fail: overflowing fb with source height
[13:55:21] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[13:55:21] [PASSED] drm_test_framebuffer_cleanup
[13:55:21] =============== drm_test_framebuffer_create ===============
[13:55:21] [PASSED] ABGR8888 normal sizes
[13:55:21] [PASSED] ABGR8888 max sizes
[13:55:21] [PASSED] ABGR8888 pitch greater than min required
[13:55:21] [PASSED] ABGR8888 pitch less than min required
[13:55:21] [PASSED] ABGR8888 Invalid width
[13:55:21] [PASSED] ABGR8888 Invalid buffer handle
[13:55:21] [PASSED] No pixel format
[13:55:21] [PASSED] ABGR8888 Width 0
[13:55:21] [PASSED] ABGR8888 Height 0
[13:55:21] [PASSED] ABGR8888 Out of bound height * pitch combination
[13:55:21] [PASSED] ABGR8888 Large buffer offset
[13:55:21] [PASSED] ABGR8888 Buffer offset for inexistent plane
[13:55:21] [PASSED] ABGR8888 Invalid flag
[13:55:21] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[13:55:21] [PASSED] ABGR8888 Valid buffer modifier
[13:55:21] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[13:55:21] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[13:55:21] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[13:55:21] [PASSED] NV12 Normal sizes
[13:55:21] [PASSED] NV12 Max sizes
[13:55:21] [PASSED] NV12 Invalid pitch
[13:55:21] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[13:55:21] [PASSED] NV12 different modifier per-plane
[13:55:21] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[13:55:21] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[13:55:21] [PASSED] NV12 Modifier for inexistent plane
[13:55:21] [PASSED] NV12 Handle for inexistent plane
[13:55:21] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[13:55:21] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[13:55:21] [PASSED] YVU420 Normal sizes
[13:55:21] [PASSED] YVU420 Max sizes
[13:55:21] [PASSED] YVU420 Invalid pitch
[13:55:21] [PASSED] YVU420 Different pitches
[13:55:21] [PASSED] YVU420 Different buffer offsets/pitches
[13:55:21] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[13:55:21] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[13:55:21] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[13:55:21] [PASSED] YVU420 Valid modifier
[13:55:21] [PASSED] YVU420 Different modifiers per plane
[13:55:21] [PASSED] YVU420 Modifier for inexistent plane
[13:55:21] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[13:55:21] [PASSED] X0L2 Normal sizes
[13:55:21] [PASSED] X0L2 Max sizes
[13:55:21] [PASSED] X0L2 Invalid pitch
[13:55:21] [PASSED] X0L2 Pitch greater than minimum required
[13:55:21] [PASSED] X0L2 Handle for inexistent plane
[13:55:21] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[13:55:21] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[13:55:21] [PASSED] X0L2 Valid modifier
[13:55:21] [PASSED] X0L2 Modifier for inexistent plane
[13:55:21] =========== [PASSED] drm_test_framebuffer_create ===========
[13:55:21] [PASSED] drm_test_framebuffer_free
[13:55:21] [PASSED] drm_test_framebuffer_init
[13:55:21] [PASSED] drm_test_framebuffer_init_bad_format
[13:55:21] [PASSED] drm_test_framebuffer_init_dev_mismatch
[13:55:21] [PASSED] drm_test_framebuffer_lookup
[13:55:21] [PASSED] drm_test_framebuffer_lookup_inexistent
[13:55:21] [PASSED] drm_test_framebuffer_modifiers_not_supported
[13:55:21] ================= [PASSED] drm_framebuffer =================
[13:55:21] ================ drm_gem_shmem (8 subtests) ================
[13:55:21] [PASSED] drm_gem_shmem_test_obj_create
[13:55:21] [PASSED] drm_gem_shmem_test_obj_create_private
[13:55:21] [PASSED] drm_gem_shmem_test_pin_pages
[13:55:21] [PASSED] drm_gem_shmem_test_vmap
[13:55:21] [PASSED] drm_gem_shmem_test_get_sg_table
[13:55:21] [PASSED] drm_gem_shmem_test_get_pages_sgt
[13:55:21] [PASSED] drm_gem_shmem_test_madvise
[13:55:21] [PASSED] drm_gem_shmem_test_purge
[13:55:21] ================== [PASSED] drm_gem_shmem ==================
[13:55:21] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[13:55:21] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[13:55:21] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[13:55:21] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[13:55:21] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[13:55:21] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[13:55:21] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[13:55:21] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[13:55:21] [PASSED] Automatic
[13:55:21] [PASSED] Full
[13:55:21] [PASSED] Limited 16:235
[13:55:21] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[13:55:21] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[13:55:21] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[13:55:21] [PASSED] drm_test_check_disable_connector
[13:55:21] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[13:55:21] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[13:55:21] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[13:55:21] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[13:55:21] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[13:55:21] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[13:55:21] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[13:55:21] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[13:55:21] [PASSED] drm_test_check_output_bpc_dvi
[13:55:21] [PASSED] drm_test_check_output_bpc_format_vic_1
[13:55:21] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[13:55:21] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[13:55:21] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[13:55:21] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[13:55:21] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[13:55:21] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[13:55:21] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[13:55:21] ============ drm_test_check_hdmi_color_format =============
[13:55:21] [PASSED] AUTO -> RGB
[13:55:21] [PASSED] YCBCR422 -> YUV422
[13:55:21] [PASSED] YCBCR420 -> YUV420
[13:55:21] [PASSED] YCBCR444 -> YUV444
[13:55:21] [PASSED] RGB -> RGB
[13:55:21] ======== [PASSED] drm_test_check_hdmi_color_format =========
[13:55:21] ======== drm_test_check_hdmi_color_format_420_only ========
[13:55:21] [PASSED] RGB should fail
[13:55:21] [PASSED] YUV444 should fail
[13:55:21] [PASSED] YUV422 should fail
[13:55:21] [PASSED] YUV420 should work
[13:55:21] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[13:55:21] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[13:55:21] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[13:55:21] [PASSED] drm_test_check_broadcast_rgb_value
[13:55:21] [PASSED] drm_test_check_bpc_8_value
[13:55:21] [PASSED] drm_test_check_bpc_10_value
[13:55:21] [PASSED] drm_test_check_bpc_12_value
[13:55:21] [PASSED] drm_test_check_format_value
[13:55:21] [PASSED] drm_test_check_tmds_char_value
[13:55:21] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[13:55:21] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[13:55:21] [PASSED] drm_test_check_mode_valid
[13:55:21] [PASSED] drm_test_check_mode_valid_reject
[13:55:21] [PASSED] drm_test_check_mode_valid_reject_rate
[13:55:21] [PASSED] drm_test_check_mode_valid_reject_max_clock
[13:55:21] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[13:55:21] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[13:55:21] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[13:55:21] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[13:55:21] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[13:55:21] [PASSED] drm_test_check_infoframes
[13:55:21] [PASSED] drm_test_check_reject_avi_infoframe
[13:55:21] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[13:55:21] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[13:55:21] [PASSED] drm_test_check_reject_audio_infoframe
[13:55:21] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[13:55:21] ================= drm_managed (2 subtests) =================
[13:55:21] [PASSED] drm_test_managed_release_action
[13:55:21] [PASSED] drm_test_managed_run_action
[13:55:21] =================== [PASSED] drm_managed ===================
[13:55:21] =================== drm_mm (6 subtests) ====================
[13:55:21] [PASSED] drm_test_mm_init
[13:55:21] [PASSED] drm_test_mm_debug
[13:55:21] [PASSED] drm_test_mm_align32
[13:55:21] [PASSED] drm_test_mm_align64
[13:55:21] [PASSED] drm_test_mm_lowest
[13:55:21] [PASSED] drm_test_mm_highest
[13:55:21] ===================== [PASSED] drm_mm ======================
[13:55:21] ============= drm_modes_analog_tv (5 subtests) =============
[13:55:21] [PASSED] drm_test_modes_analog_tv_mono_576i
[13:55:21] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[13:55:21] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[13:55:21] [PASSED] drm_test_modes_analog_tv_pal_576i
[13:55:21] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[13:55:21] =============== [PASSED] drm_modes_analog_tv ===============
[13:55:21] ============== drm_plane_helper (2 subtests) ===============
[13:55:21] =============== drm_test_check_plane_state ================
[13:55:21] [PASSED] clipping_simple
[13:55:21] [PASSED] clipping_rotate_reflect
[13:55:21] [PASSED] positioning_simple
[13:55:21] [PASSED] upscaling
[13:55:21] [PASSED] downscaling
[13:55:21] [PASSED] rounding1
[13:55:21] [PASSED] rounding2
[13:55:21] [PASSED] rounding3
[13:55:21] [PASSED] rounding4
[13:55:21] =========== [PASSED] drm_test_check_plane_state ============
[13:55:21] =========== drm_test_check_invalid_plane_state ============
[13:55:21] [PASSED] positioning_invalid
[13:55:21] [PASSED] upscaling_invalid
[13:55:21] [PASSED] downscaling_invalid
[13:55:21] ======= [PASSED] drm_test_check_invalid_plane_state ========
[13:55:21] ================ [PASSED] drm_plane_helper =================
[13:55:21] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[13:55:21] ====== drm_test_connector_helper_tv_get_modes_check =======
[13:55:21] [PASSED] None
[13:55:21] [PASSED] PAL
[13:55:21] [PASSED] NTSC
[13:55:21] [PASSED] Both, NTSC Default
[13:55:21] [PASSED] Both, PAL Default
[13:55:21] [PASSED] Both, NTSC Default, with PAL on command-line
[13:55:21] [PASSED] Both, PAL Default, with NTSC on command-line
[13:55:21] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[13:55:21] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[13:55:21] ================== drm_rect (9 subtests) ===================
[13:55:21] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[13:55:21] [PASSED] drm_test_rect_clip_scaled_not_clipped
[13:55:21] [PASSED] drm_test_rect_clip_scaled_clipped
[13:55:21] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[13:55:21] ================= drm_test_rect_intersect =================
[13:55:21] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[13:55:21] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[13:55:21] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[13:55:21] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[13:55:21] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[13:55:21] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[13:55:21] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[13:55:21] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[13:55:21] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[13:55:21] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[13:55:21] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[13:55:21] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[13:55:21] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[13:55:21] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[13:55:21] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[13:55:21] ============= [PASSED] drm_test_rect_intersect =============
[13:55:21] ================ drm_test_rect_calc_hscale ================
[13:55:21] [PASSED] normal use
[13:55:21] [PASSED] out of max range
[13:55:21] [PASSED] out of min range
[13:55:21] [PASSED] zero dst
[13:55:21] [PASSED] negative src
[13:55:21] [PASSED] negative dst
[13:55:21] ============ [PASSED] drm_test_rect_calc_hscale ============
[13:55:21] ================ drm_test_rect_calc_vscale ================
[13:55:21] [PASSED] normal use
[13:55:21] [PASSED] out of max range
[13:55:21] [PASSED] out of min range
[13:55:21] [PASSED] zero dst
[13:55:21] [PASSED] negative src
[13:55:21] [PASSED] negative dst
[13:55:21] ============ [PASSED] drm_test_rect_calc_vscale ============
[13:55:21] ================== drm_test_rect_rotate ===================
[13:55:21] [PASSED] reflect-x
[13:55:21] [PASSED] reflect-y
[13:55:21] [PASSED] rotate-0
[13:55:21] [PASSED] rotate-90
[13:55:21] [PASSED] rotate-180
[13:55:21] [PASSED] rotate-270
[13:55:21] ============== [PASSED] drm_test_rect_rotate ===============
[13:55:21] ================ drm_test_rect_rotate_inv =================
[13:55:21] [PASSED] reflect-x
[13:55:21] [PASSED] reflect-y
[13:55:21] [PASSED] rotate-0
[13:55:21] [PASSED] rotate-90
[13:55:21] [PASSED] rotate-180
[13:55:21] [PASSED] rotate-270
[13:55:21] ============ [PASSED] drm_test_rect_rotate_inv =============
[13:55:21] ==================== [PASSED] drm_rect =====================
[13:55:21] ============ drm_sysfb_modeset_test (1 subtest) ============
[13:55:21] ============ drm_test_sysfb_build_fourcc_list =============
[13:55:21] [PASSED] no native formats
[13:55:21] [PASSED] XRGB8888 as native format
[13:55:21] [PASSED] remove duplicates
[13:55:21] [PASSED] convert alpha formats
[13:55:21] [PASSED] random formats
[13:55:21] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[13:55:21] ============= [PASSED] drm_sysfb_modeset_test ==============
[13:55:21] ================== drm_fixp (2 subtests) ===================
[13:55:21] [PASSED] drm_test_int2fixp
[13:55:21] [PASSED] drm_test_sm2fixp
[13:55:21] ==================== [PASSED] drm_fixp =====================
[13:55:21] ============================================================
[13:55:21] Testing complete. Ran 637 tests: passed: 637
[13:55:21] Elapsed time: 26.490s total, 1.833s configuring, 24.490s building, 0.142s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[13:55:21] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[13:55:23] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[13:55:33] Starting KUnit Kernel (1/1)...
[13:55:33] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[13:55:33] ================= ttm_device (5 subtests) ==================
[13:55:33] [PASSED] ttm_device_init_basic
[13:55:33] [PASSED] ttm_device_init_multiple
[13:55:33] [PASSED] ttm_device_fini_basic
[13:55:33] [PASSED] ttm_device_init_no_vma_man
[13:55:33] ================== ttm_device_init_pools ==================
[13:55:33] [PASSED] No DMA allocations, no DMA32 required
[13:55:33] [PASSED] DMA allocations, DMA32 required
[13:55:33] [PASSED] No DMA allocations, DMA32 required
[13:55:33] [PASSED] DMA allocations, no DMA32 required
[13:55:33] ============== [PASSED] ttm_device_init_pools ==============
[13:55:33] =================== [PASSED] ttm_device ====================
[13:55:33] ================== ttm_pool (8 subtests) ===================
[13:55:33] ================== ttm_pool_alloc_basic ===================
[13:55:33] [PASSED] One page
[13:55:33] [PASSED] More than one page
[13:55:33] [PASSED] Above the allocation limit
[13:55:33] [PASSED] One page, with coherent DMA mappings enabled
[13:55:33] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[13:55:33] ============== [PASSED] ttm_pool_alloc_basic ===============
[13:55:33] ============== ttm_pool_alloc_basic_dma_addr ==============
[13:55:33] [PASSED] One page
[13:55:33] [PASSED] More than one page
[13:55:33] [PASSED] Above the allocation limit
[13:55:33] [PASSED] One page, with coherent DMA mappings enabled
[13:55:33] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[13:55:33] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[13:55:33] [PASSED] ttm_pool_alloc_order_caching_match
[13:55:33] [PASSED] ttm_pool_alloc_caching_mismatch
[13:55:33] [PASSED] ttm_pool_alloc_order_mismatch
[13:55:33] [PASSED] ttm_pool_free_dma_alloc
[13:55:33] [PASSED] ttm_pool_free_no_dma_alloc
[13:55:33] [PASSED] ttm_pool_fini_basic
[13:55:33] ==================== [PASSED] ttm_pool =====================
[13:55:33] ================ ttm_resource (8 subtests) =================
[13:55:33] ================= ttm_resource_init_basic =================
[13:55:33] [PASSED] Init resource in TTM_PL_SYSTEM
[13:55:33] [PASSED] Init resource in TTM_PL_VRAM
[13:55:33] [PASSED] Init resource in a private placement
[13:55:33] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[13:55:33] ============= [PASSED] ttm_resource_init_basic =============
[13:55:33] [PASSED] ttm_resource_init_pinned
[13:55:33] [PASSED] ttm_resource_fini_basic
[13:55:33] [PASSED] ttm_resource_manager_init_basic
[13:55:33] [PASSED] ttm_resource_manager_usage_basic
[13:55:33] [PASSED] ttm_resource_manager_set_used_basic
[13:55:33] [PASSED] ttm_sys_man_alloc_basic
[13:55:33] [PASSED] ttm_sys_man_free_basic
[13:55:33] ================== [PASSED] ttm_resource ===================
[13:55:33] =================== ttm_tt (15 subtests) ===================
[13:55:33] ==================== ttm_tt_init_basic ====================
[13:55:33] [PASSED] Page-aligned size
[13:55:33] [PASSED] Extra pages requested
[13:55:33] ================ [PASSED] ttm_tt_init_basic ================
[13:55:33] [PASSED] ttm_tt_init_misaligned
[13:55:33] [PASSED] ttm_tt_fini_basic
[13:55:33] [PASSED] ttm_tt_fini_sg
[13:55:33] [PASSED] ttm_tt_fini_shmem
[13:55:33] [PASSED] ttm_tt_create_basic
[13:55:33] [PASSED] ttm_tt_create_invalid_bo_type
[13:55:33] [PASSED] ttm_tt_create_ttm_exists
[13:55:33] [PASSED] ttm_tt_create_failed
[13:55:33] [PASSED] ttm_tt_destroy_basic
[13:55:33] [PASSED] ttm_tt_populate_null_ttm
[13:55:33] [PASSED] ttm_tt_populate_populated_ttm
[13:55:33] [PASSED] ttm_tt_unpopulate_basic
[13:55:33] [PASSED] ttm_tt_unpopulate_empty_ttm
[13:55:33] [PASSED] ttm_tt_swapin_basic
[13:55:33] ===================== [PASSED] ttm_tt ======================
[13:55:33] =================== ttm_bo (14 subtests) ===================
[13:55:33] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[13:55:33] [PASSED] Cannot be interrupted and sleeps
[13:55:33] [PASSED] Cannot be interrupted, locks straight away
[13:55:33] [PASSED] Can be interrupted, sleeps
[13:55:33] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[13:55:33] [PASSED] ttm_bo_reserve_locked_no_sleep
[13:55:33] [PASSED] ttm_bo_reserve_no_wait_ticket
[13:55:33] [PASSED] ttm_bo_reserve_double_resv
[13:55:33] [PASSED] ttm_bo_reserve_interrupted
[13:55:33] [PASSED] ttm_bo_reserve_deadlock
[13:55:33] [PASSED] ttm_bo_unreserve_basic
[13:55:33] [PASSED] ttm_bo_unreserve_pinned
[13:55:33] [PASSED] ttm_bo_unreserve_bulk
[13:55:33] [PASSED] ttm_bo_fini_basic
[13:55:33] [PASSED] ttm_bo_fini_shared_resv
[13:55:33] [PASSED] ttm_bo_pin_basic
[13:55:33] [PASSED] ttm_bo_pin_unpin_resource
[13:55:33] [PASSED] ttm_bo_multiple_pin_one_unpin
[13:55:33] ===================== [PASSED] ttm_bo ======================
[13:55:33] ============== ttm_bo_validate (22 subtests) ===============
[13:55:33] ============== ttm_bo_init_reserved_sys_man ===============
[13:55:33] [PASSED] Buffer object for userspace
[13:55:33] [PASSED] Kernel buffer object
[13:55:33] [PASSED] Shared buffer object
[13:55:33] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[13:55:33] ============== ttm_bo_init_reserved_mock_man ==============
[13:55:33] [PASSED] Buffer object for userspace
[13:55:33] [PASSED] Kernel buffer object
[13:55:33] [PASSED] Shared buffer object
[13:55:33] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[13:55:33] [PASSED] ttm_bo_init_reserved_resv
[13:55:33] ================== ttm_bo_validate_basic ==================
[13:55:33] [PASSED] Buffer object for userspace
[13:55:33] [PASSED] Kernel buffer object
[13:55:33] [PASSED] Shared buffer object
[13:55:33] ============== [PASSED] ttm_bo_validate_basic ==============
[13:55:33] [PASSED] ttm_bo_validate_invalid_placement
[13:55:33] ============= ttm_bo_validate_same_placement ==============
[13:55:33] [PASSED] System manager
[13:55:33] [PASSED] VRAM manager
[13:55:33] ========= [PASSED] ttm_bo_validate_same_placement ==========
[13:55:33] [PASSED] ttm_bo_validate_failed_alloc
[13:55:33] [PASSED] ttm_bo_validate_pinned
[13:55:33] [PASSED] ttm_bo_validate_busy_placement
[13:55:33] ================ ttm_bo_validate_multihop =================
[13:55:33] [PASSED] Buffer object for userspace
[13:55:33] [PASSED] Kernel buffer object
[13:55:33] [PASSED] Shared buffer object
[13:55:33] ============ [PASSED] ttm_bo_validate_multihop =============
[13:55:33] ========== ttm_bo_validate_no_placement_signaled ==========
[13:55:33] [PASSED] Buffer object in system domain, no page vector
[13:55:33] [PASSED] Buffer object in system domain with an existing page vector
[13:55:33] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[13:55:33] ======== ttm_bo_validate_no_placement_not_signaled ========
[13:55:33] [PASSED] Buffer object for userspace
[13:55:33] [PASSED] Kernel buffer object
[13:55:33] [PASSED] Shared buffer object
[13:55:33] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[13:55:33] [PASSED] ttm_bo_validate_move_fence_signaled
[13:55:33] ========= ttm_bo_validate_move_fence_not_signaled =========
[13:55:33] [PASSED] Waits for GPU
[13:55:33] [PASSED] Tries to lock straight away
[13:55:33] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[13:55:33] [PASSED] ttm_bo_validate_swapout
[13:55:33] [PASSED] ttm_bo_validate_happy_evict
[13:55:33] [PASSED] ttm_bo_validate_all_pinned_evict
[13:55:33] [PASSED] ttm_bo_validate_allowed_only_evict
[13:55:33] [PASSED] ttm_bo_validate_deleted_evict
[13:55:33] [PASSED] ttm_bo_validate_busy_domain_evict
[13:55:33] [PASSED] ttm_bo_validate_evict_gutting
[13:55:33] [PASSED] ttm_bo_validate_recrusive_evict
[13:55:33] ================= [PASSED] ttm_bo_validate =================
[13:55:33] ============================================================
[13:55:33] Testing complete. Ran 102 tests: passed: 102
[13:55:34] Elapsed time: 12.079s total, 1.825s configuring, 10.040s building, 0.180s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 6+ messages in thread
* ✗ Xe.CI.BAT: failure for cdclk mismatch with sw/hw (rev2)
2026-08-04 9:28 [PATCH 0/2] cdclk mismatch with sw/hw Arun R Murthy
` (2 preceding siblings ...)
2026-08-05 13:55 ` ✓ CI.KUnit: success for cdclk mismatch with sw/hw (rev2) Patchwork
@ 2026-08-05 14:39 ` Patchwork
2026-08-06 1:53 ` ✗ Xe.CI.FULL: " Patchwork
4 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2026-08-05 14:39 UTC (permalink / raw)
To: Murthy, Arun R; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 5781 bytes --]
== Series Details ==
Series: cdclk mismatch with sw/hw (rev2)
URL : https://patchwork.freedesktop.org/series/171570/
State : failure
== Summary ==
CI Bug Log - changes from xe-5545-4c13a67db118ee0019231dbc1362bcb8115ac660_BAT -> xe-pw-171570v2_BAT
====================================================
Summary
-------
**WARNING**
Minor unknown changes coming with xe-pw-171570v2_BAT need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-171570v2_BAT, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (14 -> 15)
------------------------------
Additional (1): bat-bmg-2
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in xe-pw-171570v2_BAT:
### IGT changes ###
#### Warnings ####
* igt@kms_frontbuffer_tracking@basic:
- bat-nvls-2: [SKIP][1] ([Intel XE#7779]) -> [SKIP][2]
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5545-4c13a67db118ee0019231dbc1362bcb8115ac660/bat-nvls-2/igt@kms_frontbuffer_tracking@basic.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171570v2/bat-nvls-2/igt@kms_frontbuffer_tracking@basic.html
Known issues
------------
Here are the changes found in xe-pw-171570v2_BAT that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@fbdev@write:
- bat-bmg-2: NOTRUN -> [SKIP][3] ([Intel XE#2134]) +4 other tests skip
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171570v2/bat-bmg-2/igt@fbdev@write.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-bmg-2: NOTRUN -> [SKIP][4] ([Intel XE#2233])
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171570v2/bat-bmg-2/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
- bat-bmg-2: NOTRUN -> [SKIP][5] ([Intel XE#2489] / [Intel XE#3419]) +13 other tests skip
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171570v2/bat-bmg-2/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
* igt@kms_flip@basic-flip-vs-modeset:
- bat-bmg-2: NOTRUN -> [SKIP][6] ([Intel XE#2482]) +3 other tests skip
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171570v2/bat-bmg-2/igt@kms_flip@basic-flip-vs-modeset.html
* igt@kms_frontbuffer_tracking@basic:
- bat-bmg-2: NOTRUN -> [SKIP][7] ([Intel XE#2434] / [Intel XE#2548] / [Intel XE#6314])
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171570v2/bat-bmg-2/igt@kms_frontbuffer_tracking@basic.html
* igt@kms_psr@psr-sprite-plane-onoff:
- bat-bmg-2: NOTRUN -> [SKIP][8] ([Intel XE#2234] / [Intel XE#2850]) +2 other tests skip
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171570v2/bat-bmg-2/igt@kms_psr@psr-sprite-plane-onoff.html
* igt@xe_exec_multi_queue@priority:
- bat-bmg-2: NOTRUN -> [SKIP][9] ([Intel XE#8364]) +13 other tests skip
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171570v2/bat-bmg-2/igt@xe_exec_multi_queue@priority.html
* igt@xe_live_ktest@xe_bo@xe_ccs_migrate_kunit:
- bat-bmg-2: NOTRUN -> [SKIP][10] ([Intel XE#2229])
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171570v2/bat-bmg-2/igt@xe_live_ktest@xe_bo@xe_ccs_migrate_kunit.html
* igt@xe_pat@pat-index-xehpc:
- bat-bmg-2: NOTRUN -> [SKIP][11] ([Intel XE#1420] / [Intel XE#7590])
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171570v2/bat-bmg-2/igt@xe_pat@pat-index-xehpc.html
* igt@xe_pat@pat-index-xelp:
- bat-bmg-2: NOTRUN -> [SKIP][12] ([Intel XE#2245] / [Intel XE#7590])
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171570v2/bat-bmg-2/igt@xe_pat@pat-index-xelp.html
* igt@xe_pat@pat-index-xelpg:
- bat-bmg-2: NOTRUN -> [SKIP][13] ([Intel XE#2236] / [Intel XE#7590])
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171570v2/bat-bmg-2/igt@xe_pat@pat-index-xelpg.html
[Intel XE#1420]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1420
[Intel XE#2134]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2134
[Intel XE#2229]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2229
[Intel XE#2233]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2233
[Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
[Intel XE#2236]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2236
[Intel XE#2245]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2245
[Intel XE#2434]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2434
[Intel XE#2482]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2482
[Intel XE#2489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2489
[Intel XE#2548]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2548
[Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
[Intel XE#3419]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3419
[Intel XE#6314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6314
[Intel XE#7590]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7590
[Intel XE#7779]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7779
[Intel XE#8364]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8364
Build changes
-------------
* Linux: xe-5545-4c13a67db118ee0019231dbc1362bcb8115ac660 -> xe-pw-171570v2
IGT_9038: 9038
xe-5545-4c13a67db118ee0019231dbc1362bcb8115ac660: 4c13a67db118ee0019231dbc1362bcb8115ac660
xe-pw-171570v2: 171570v2
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171570v2/index.html
[-- Attachment #2: Type: text/html, Size: 6723 bytes --]
^ permalink raw reply [flat|nested] 6+ messages in thread
* ✗ Xe.CI.FULL: failure for cdclk mismatch with sw/hw (rev2)
2026-08-04 9:28 [PATCH 0/2] cdclk mismatch with sw/hw Arun R Murthy
` (3 preceding siblings ...)
2026-08-05 14:39 ` ✗ Xe.CI.BAT: failure " Patchwork
@ 2026-08-06 1:53 ` Patchwork
4 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2026-08-06 1:53 UTC (permalink / raw)
To: Murthy, Arun R; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 363 bytes --]
== Series Details ==
Series: cdclk mismatch with sw/hw (rev2)
URL : https://patchwork.freedesktop.org/series/171570/
State : failure
== Summary ==
ERROR: The runconfig 'xe-5545-4c13a67db118ee0019231dbc1362bcb8115ac660_FULL' does not exist in the database
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171570v2/index.html
[-- Attachment #2: Type: text/html, Size: 928 bytes --]
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2026-08-06 1:53 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-08-04 9:28 [PATCH 0/2] cdclk mismatch with sw/hw Arun R Murthy
2026-08-04 9:28 ` [PATCH 1/2] drm/i915/display: Seed skl_cdclk_init_hw() with SKU-max, not zero Arun R Murthy
2026-08-04 9:28 ` [PATCH 2/2] drm/i915/display: Reconcile cdclk SW state with HW on DC-off exit Arun R Murthy
2026-08-05 13:55 ` ✓ CI.KUnit: success for cdclk mismatch with sw/hw (rev2) Patchwork
2026-08-05 14:39 ` ✗ Xe.CI.BAT: failure " Patchwork
2026-08-06 1:53 ` ✗ Xe.CI.FULL: " Patchwork
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