[PATCH v3 0/3] drm/xe: fix GuC TLB invalidation ack stalls on ARL (Wa_22016122933)

[PATCH v3 0/3] drm/xe: fix GuC TLB invalidation ack stalls on ARL (Wa_22016122933)

[Tales A. Mendonça]

Hi,

v3 of the TLB invalidation ack stall fix for ARL, tracked in:

  https://gitlab.freedesktop.org/drm/xe/kernel/-/work_items/8678

Root cause recap: the GuC replies in time, but on the standalone media
GT the CPU reads a stale cache line of the G2H CTB - the caching
erratum i915 works around as Wa_22016122933 and xe never inherited.
Patch 3 implements it, scoped like i915.

Since v2, Navon John Lukose A/B tested the series on an ARL 7d51 and
produced three results that are folded into this version:

 * Making the mapping coherent instead of uncached does not work: a
   GGTT PAT entry repurposed to WB|COH_2WAY still stalls
   (request-to-ack 2290ms). Now documented in patch 3 - it is the
   obvious question to ask about this patch, and the answer is
   measured rather than assumed.

 * xe_guc_engine_activity.c allocates GuC-written, CPU-read buffers on
   the same GT without the workaround flags; the symptom there would
   be stale busyness stats rather than hangs. Now covered.

 * CPU-WC (matching i915's wording) is equally effective, but
   XE_BO_FLAG_NEEDS_UC currently drives both the CPU mapping and the
   GGTT cache mode, and naively switching to XE_BO_FLAG_FORCE_WC
   relaxes the GPU side back to WB and brings the stalls back
   (3 hits/20min measured).

His Tested-by on patch 3 is from v2; the only code change since is the
added engine activity coverage.

Two questions I would rather have answered than decide unilaterally:

 1. CPU mapping: keep the stricter UC as in this series, or add a way
    to express i915's exact combination (CPU WC + GGTT XE_CACHE_NONE)?
    The latter needs either a new BO flag or decoupling the GGTT
    cache-mode selection from XE_BO_FLAG_NEEDS_UC. No measurable
    throughput difference between the two.

 2. Scope: i915 applies the workaround to all media-GT shared memory,
    including LRC/ring state; this series covers the GuC-shared
    allocations only (CTBs, log, ADS, SLPC, engine activity). Should
    xe match i915's full scope?

I also left out Fixes:/Cc: stable, since MTL/ARL is still
require_force_probe in xe - happy to add them if you would prefer the
fix to reach stable kernels.

Validation of patch 3: two ARL machines (7d51 and 7dd1), ~4 weeks of
combined runtime, >7M TLB invalidations, zero stalls. Before the fix
both machines reproduced 20-60 stalls/day, every day, on every kernel
and on two GuC firmware versions. The 7dd1 machine, which could not
survive a day of media workloads on xe without a platform freeze, has
been running xe continuously for two weeks including video
transcoding, with zero incidents.

Patches 1-2 are the diagnostics that made the investigation possible,
unchanged from v2 except for a commit-message line wrap.

v2 -> v3:
- Rebased on drm-tip.
- Patch 3: cover xe_guc_engine_activity.c; document the coherency
  experiment and the UC-vs-WC tradeoff; add Suggested-by/Tested-by.
- Patch 2: wrap a quoted log line to silence checkpatch.
- checkpatch is clean on all three patches now.

Thanks,
Tales

Tales A. Mendonça (3):
  drm/xe: Capture devcoredump on TLB invalidation timeout
  drm/xe: Log when a timed out TLB invalidation ack finally arrives
  drm/xe: Implement Wa_22016122933

 drivers/gpu/drm/xe/xe_devcoredump.c         | 46 +++++++++++----------
 drivers/gpu/drm/xe/xe_devcoredump.h         | 15 +++++--
 drivers/gpu/drm/xe/xe_guc.c                 | 16 +++++++
 drivers/gpu/drm/xe/xe_guc.h                 |  2 +
 drivers/gpu/drm/xe/xe_guc_ads.c             |  3 +-
 drivers/gpu/drm/xe/xe_guc_ct.c              |  6 ++-
 drivers/gpu/drm/xe/xe_guc_engine_activity.c |  6 ++-
 drivers/gpu/drm/xe/xe_guc_log.c             |  7 +++-
 drivers/gpu/drm/xe/xe_guc_pc.c              |  3 +-
 drivers/gpu/drm/xe/xe_tlb_inval.c           | 39 +++++++++++++++++
 drivers/gpu/drm/xe/xe_tlb_inval_types.h     | 17 ++++++++
 drivers/gpu/drm/xe/xe_wa_oob.rules          |  1 +
 12 files changed, 128 insertions(+), 33 deletions(-)

-- 
2.55.0

[PATCH v3 1/3] drm/xe: Capture devcoredump on TLB invalidation timeout

[Tales A. Mendonça]

TLB invalidation timeouts currently leave no record of the firmware
state behind: there is no exec queue or job to blame, so nothing calls
xe_devcoredump() and the GuC log content at the time of the hang is
lost.

Add xe_devcoredump_gt(), a variant of xe_devcoredump() for hangs that
are not tied to an exec queue or job. It captures the GuC log and CT
state of the affected GT, reusing the existing snapshot machinery and
the "only first snapshot" policy, and hook it up to the TLB invalidation
timeout path.

This was instrumental in diagnosing GuC TLB invalidation ack stalls on
ARL (see Link), where the invalidation request is consumed from the H2G
CTB immediately but the ack G2H only arrives ~2.3s later, after the
timeout has already fired.

Link: https://gitlab.freedesktop.org/drm/xe/kernel/-/work_items/8678
Signed-off-by: Tales A. Mendonça <talesam@gmail.com>
---
 drivers/gpu/drm/xe/xe_devcoredump.c | 46 ++++++++++++++++-------------
 drivers/gpu/drm/xe/xe_devcoredump.h | 15 +++++++---
 drivers/gpu/drm/xe/xe_tlb_inval.c   | 20 +++++++++++++
 3 files changed, 56 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_devcoredump.c b/drivers/gpu/drm/xe/xe_devcoredump.c
index 5f2b90b18f9..6bee8933f95 100644
--- a/drivers/gpu/drm/xe/xe_devcoredump.c
+++ b/drivers/gpu/drm/xe/xe_devcoredump.c
@@ -74,11 +74,6 @@ static struct xe_device *coredump_to_xe(const struct xe_devcoredump *coredump)
 	return container_of(coredump, struct xe_device, devcoredump);
 }
 
-static struct xe_guc *exec_queue_to_guc(struct xe_exec_queue *q)
-{
-	return &q->gt->uc.guc;
-}
-
 static ssize_t __xe_devcoredump_read(char *buffer, ssize_t count,
 				     ssize_t start,
 				     struct xe_devcoredump *coredump)
@@ -323,40 +318,44 @@ static void xe_devcoredump_deferred_snap_work(struct work_struct *work)
 }
 
 static void devcoredump_snapshot(struct xe_devcoredump *coredump,
+				 struct xe_gt *gt,
 				 struct xe_exec_queue *q,
 				 struct xe_sched_job *job)
 {
 	struct xe_devcoredump_snapshot *ss = &coredump->snapshot;
-	struct xe_guc *guc = exec_queue_to_guc(q);
+	struct xe_guc *guc = &gt->uc.guc;
 	const char *process_name = "no process";
 	bool cookie;
 
 	ss->snapshot_time = ktime_get_real();
 	ss->boot_time = ktime_get_boottime();
 
-	if (q->vm && q->vm->xef) {
+	if (q && q->vm && q->vm->xef) {
 		process_name = q->vm->xef->process_name;
 		ss->pid = q->vm->xef->pid;
 	}
 
 	strscpy(ss->process_name, process_name);
 
-	ss->gt = q->gt;
+	ss->gt = gt;
 	INIT_WORK(&ss->work, xe_devcoredump_deferred_snap_work);
 
 	/* keep going if fw fails as we still want to save the memory and SW data */
-	CLASS(xe_force_wake, fw_ref)(gt_to_fw(q->gt), XE_FORCEWAKE_ALL);
+	CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FORCEWAKE_ALL);
 
 	cookie = dma_fence_begin_signalling();
 
 	ss->guc.log = xe_guc_log_snapshot_capture(&guc->log, true);
 	ss->guc.ct = xe_guc_ct_snapshot_capture(&guc->ct);
-	ss->ge = xe_guc_exec_queue_snapshot_capture(q);
-	if (job)
-		ss->job = xe_sched_job_snapshot_capture(job);
-	ss->vm = xe_vm_snapshot_capture(q->vm);
 
-	xe_engine_snapshot_capture_for_queue(q);
+	if (q) {
+		ss->ge = xe_guc_exec_queue_snapshot_capture(q);
+		if (job)
+			ss->job = xe_sched_job_snapshot_capture(job);
+		ss->vm = xe_vm_snapshot_capture(q->vm);
+
+		xe_engine_snapshot_capture_for_queue(q);
+	}
 
 	queue_work(system_dfl_wq, &ss->work);
 
@@ -364,19 +363,24 @@ static void devcoredump_snapshot(struct xe_devcoredump *coredump,
 }
 
 /**
- * xe_devcoredump - Take the required snapshots and initialize coredump device.
- * @q: The faulty xe_exec_queue, where the issue was detected.
- * @job: The faulty xe_sched_job, where the issue was detected.
+ * __xe_devcoredump - Take the required snapshots and initialize coredump device.
+ * @gt: The GT where the issue was detected.
+ * @q: The faulty xe_exec_queue, where the issue was detected, may be NULL for
+ *     hangs that are not tied to an exec queue (e.g. TLB invalidation
+ *     timeouts); in that case only the GT-level state (GuC log and CT state)
+ *     is captured.
+ * @job: The faulty xe_sched_job, where the issue was detected, may be NULL.
  * @fmt: Printf format + args to describe the reason for the core dump
  *
  * This function should be called at the crash time within the serialized
  * gt_reset. It is skipped if we still have the core dump device available
  * with the information of the 'first' snapshot.
  */
-__printf(3, 4)
-void xe_devcoredump(struct xe_exec_queue *q, struct xe_sched_job *job, const char *fmt, ...)
+__printf(4, 5)
+void __xe_devcoredump(struct xe_gt *gt, struct xe_exec_queue *q,
+		      struct xe_sched_job *job, const char *fmt, ...)
 {
-	struct xe_device *xe = gt_to_xe(q->gt);
+	struct xe_device *xe = gt_to_xe(gt);
 	struct xe_devcoredump *coredump = &xe->devcoredump;
 	va_list varg;
 
@@ -394,7 +398,7 @@ void xe_devcoredump(struct xe_exec_queue *q, struct xe_sched_job *job, const cha
 	coredump->snapshot.reason = kvasprintf(GFP_ATOMIC, fmt, varg);
 	va_end(varg);
 
-	devcoredump_snapshot(coredump, q, job);
+	devcoredump_snapshot(coredump, gt, q, job);
 
 	drm_info(&xe->drm, "Xe device coredump has been created\n");
 	drm_info(&xe->drm, "Check your /sys/class/drm/card%d/device/devcoredump/data\n",
diff --git a/drivers/gpu/drm/xe/xe_devcoredump.h b/drivers/gpu/drm/xe/xe_devcoredump.h
index 5391a80a4d1..bc4800b3a3f 100644
--- a/drivers/gpu/drm/xe/xe_devcoredump.h
+++ b/drivers/gpu/drm/xe/xe_devcoredump.h
@@ -11,15 +11,17 @@
 struct drm_printer;
 struct xe_device;
 struct xe_exec_queue;
+struct xe_gt;
 struct xe_sched_job;
 
 #ifdef CONFIG_DEV_COREDUMP
-void xe_devcoredump(struct xe_exec_queue *q, struct xe_sched_job *job, const char *fmt, ...);
+void __xe_devcoredump(struct xe_gt *gt, struct xe_exec_queue *q,
+		      struct xe_sched_job *job, const char *fmt, ...);
 int xe_devcoredump_init(struct xe_device *xe);
 #else
-static inline void xe_devcoredump(struct xe_exec_queue *q,
-				  struct xe_sched_job *job,
-				  const char *fmt, ...)
+static inline void __xe_devcoredump(struct xe_gt *gt, struct xe_exec_queue *q,
+				    struct xe_sched_job *job,
+				    const char *fmt, ...)
 {
 }
 
@@ -29,6 +31,11 @@ static inline int xe_devcoredump_init(struct xe_device *xe)
 }
 #endif
 
+#define xe_devcoredump(_q, _job, _fmt, ...) \
+	__xe_devcoredump((_q)->gt, _q, _job, _fmt, ##__VA_ARGS__)
+#define xe_devcoredump_gt(_gt, _fmt, ...) \
+	__xe_devcoredump(_gt, NULL, NULL, _fmt, ##__VA_ARGS__)
+
 void xe_print_blob_ascii85(struct drm_printer *p, const char *prefix, char suffix,
 			   const void *blob, size_t offset, size_t size);
 
diff --git a/drivers/gpu/drm/xe/xe_tlb_inval.c b/drivers/gpu/drm/xe/xe_tlb_inval.c
index bbd21d39306..833fb92cd3e 100644
--- a/drivers/gpu/drm/xe/xe_tlb_inval.c
+++ b/drivers/gpu/drm/xe/xe_tlb_inval.c
@@ -5,6 +5,7 @@
 
 #include <drm/drm_managed.h>
 
+#include "xe_devcoredump.h"
 #include "xe_device_types.h"
 #include "xe_force_wake.h"
 #include "xe_gt_stats.h"
@@ -29,6 +30,12 @@
 
 #define FENCE_STACK_BIT		DMA_FENCE_FLAG_USER_BITS
 
+/* The frontend is only ever embedded in a GT */
+static struct xe_gt *tlb_inval_to_gt(struct xe_tlb_inval *tlb_inval)
+{
+	return container_of(tlb_inval, struct xe_gt, tlb_inval);
+}
+
 static void xe_tlb_inval_fence_fini(struct xe_tlb_inval_fence *fence)
 {
 	if (WARN_ON_ONCE(!fence->tlb_inval))
@@ -73,6 +80,7 @@ static void xe_tlb_inval_fence_timeout(struct work_struct *work)
 	struct xe_device *xe = tlb_inval->xe;
 	struct xe_tlb_inval_fence *fence, *next;
 	long timeout_delay = tlb_inval->ops->timeout_delay(tlb_inval);
+	int timedout_seqno = 0;
 
 	tlb_inval->ops->flush(tlb_inval);
 
@@ -90,6 +98,8 @@ static void xe_tlb_inval_fence_timeout(struct work_struct *work)
 			"TLB invalidation fence timeout, seqno=%d recv=%d",
 			fence->seqno, tlb_inval->seqno_recv);
 
+		timedout_seqno = fence->seqno;
+
 		fence->base.error = -ETIME;
 		xe_tlb_inval_fence_signal(fence);
 	}
@@ -97,6 +107,16 @@ static void xe_tlb_inval_fence_timeout(struct work_struct *work)
 		queue_delayed_work(tlb_inval->timeout_wq, &tlb_inval->fence_tdr,
 				   timeout_delay);
 	spin_unlock_irq(&tlb_inval->pending_lock);
+
+	/*
+	 * Capture the GuC log and CT state so the firmware side of the hang
+	 * can be inspected; there is no queue or job to blame here. Must be
+	 * outside pending_lock as the capture takes sleeping locks.
+	 */
+	if (timedout_seqno)
+		xe_devcoredump_gt(tlb_inval_to_gt(tlb_inval),
+				  "TLB invalidation fence timeout, seqno=%d recv=%d",
+				  timedout_seqno, tlb_inval->seqno_recv);
 }
 
 /**
-- 
2.55.0

Re: [PATCH v3 1/3] drm/xe: Capture devcoredump on TLB invalidation timeout

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] Uncancelled deferred devcoredump work on the global workqueue leads to UAF if the driver is unbound/unloaded before the work executes.
--

--- Patch [1]: [PATCH v3 1/3] drm/xe: Capture devcoredump on TLB invalidation timeout ---
commit e17a9749756454a4d7c32af8d34a73ac7b919a3e
Author: Tales A. Mendonça <talesam@gmail.com>

drm/xe: Capture devcoredump on TLB invalidation timeout

This commit adds xe_devcoredump_gt() to capture GuC log and CT state
for hangs that are not tied to an exec queue or job. It also hooks
this mechanism up to the TLB invalidation timeout path.

Link: https://gitlab.freedesktop.org/drm/xe/kernel/-/work_items/8678

> diff --git a/drivers/gpu/drm/xe/xe_devcoredump.c b/drivers/gpu/drm/xe/xe_devcoredump.c
> --- a/drivers/gpu/drm/xe/xe_devcoredump.c
> +++ b/drivers/gpu/drm/xe/xe_devcoredump.c
[ ... ]
> @@ -323,40 +318,44 @@ static void devcoredump_snapshot(struct xe_devcoredump *coredump,
[ ... ]
> +	if (q) {
> +		ss->ge = xe_guc_exec_queue_snapshot_capture(q);
> +		if (job)
> +			ss->job = xe_sched_job_snapshot_capture(job);
> +		ss->vm = xe_vm_snapshot_capture(q->vm);
> +
> +		xe_engine_snapshot_capture_for_queue(q);
> +	}
>  
>  	queue_work(system_dfl_wq, &ss->work);

[Severity: High]
This is a pre-existing issue, but does this deferred work item on the global
system_dfl_wq cause a use-after-free if the driver is unbound before it
executes?

During teardown, xe_driver_devcoredump_fini() calls dev_coredump_put(). If
the work hasn't run yet, the coredump device hasn't been registered by the
deferred worker.

Consequently, dev_coredump_put() finds no device, returns silently, and
never invokes xe_devcoredump_free(). The work remains uncanceled on
system_dfl_wq and will eventually execute using a freed xe_device.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260824140748.54974-1-talesam@gmail.com?part=1

[PATCH v3 2/3] drm/xe: Log when a timed out TLB invalidation ack finally arrives

[Tales A. Mendonça]

When a TLB invalidation fence times out we log the timeout, but if the
ack for that seqno later shows up there is no record of it, making it
impossible to tell from logs whether the ack was lost forever or merely
(very) late.

Track the most recent timed out seqno and log how late its ack arrives,
relative to both the original request and the moment the fence was
signaled with -ETIME.

On ARL with GuC 70.53.0 this shows the acks are never lost: they
consistently arrive ~2.3s after the request, tens of milliseconds after
the TDR has already signaled the fence:

  TLB invalidation fence timeout, seqno=10992 recv=10991
  TLB invalidation late ack: seqno=10992 recv=10992,
    request-to-ack=2314ms, timeout-to-ack=45ms

Link: https://gitlab.freedesktop.org/drm/xe/kernel/-/work_items/8678
Signed-off-by: Tales A. Mendonça <talesam@gmail.com>
---
 drivers/gpu/drm/xe/xe_tlb_inval.c       | 19 +++++++++++++++++++
 drivers/gpu/drm/xe/xe_tlb_inval_types.h | 17 +++++++++++++++++
 2 files changed, 36 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_tlb_inval.c b/drivers/gpu/drm/xe/xe_tlb_inval.c
index 833fb92cd3e..e98c6a0b7a6 100644
--- a/drivers/gpu/drm/xe/xe_tlb_inval.c
+++ b/drivers/gpu/drm/xe/xe_tlb_inval.c
@@ -14,6 +14,7 @@
 #include "xe_guc_tlb_inval.h"
 #include "xe_mmio.h"
 #include "xe_pm.h"
+#include "xe_printk.h"
 #include "xe_tlb_inval.h"
 #include "xe_trace.h"
 
@@ -99,6 +100,11 @@ static void xe_tlb_inval_fence_timeout(struct work_struct *work)
 			fence->seqno, tlb_inval->seqno_recv);
 
 		timedout_seqno = fence->seqno;
+		if (!tlb_inval->timedout_seqno) {
+			tlb_inval->timedout_seqno = fence->seqno;
+			tlb_inval->timedout_inval_time = fence->inval_time;
+			tlb_inval->timedout_time = ktime_get();
+		}
 
 		fence->base.error = -ETIME;
 		xe_tlb_inval_fence_signal(fence);
@@ -227,6 +233,7 @@ void xe_tlb_inval_reset(struct xe_tlb_inval *tlb_inval)
 	else
 		pending_seqno = tlb_inval->seqno - 1;
 	WRITE_ONCE(tlb_inval->seqno_recv, pending_seqno);
+	tlb_inval->timedout_seqno = 0;
 
 	list_for_each_entry_safe(fence, next,
 				 &tlb_inval->pending_fences, link)
@@ -424,6 +431,18 @@ void xe_tlb_inval_done_handler(struct xe_tlb_inval *tlb_inval, int seqno)
 
 	WRITE_ONCE(tlb_inval->seqno_recv, seqno);
 
+	if (tlb_inval->timedout_seqno &&
+	    xe_tlb_inval_seqno_past(tlb_inval, tlb_inval->timedout_seqno)) {
+		ktime_t now = ktime_get();
+
+		xe_warn(xe,
+			"TLB invalidation late ack: seqno=%d recv=%d, request-to-ack=%lldms, timeout-to-ack=%lldms",
+			tlb_inval->timedout_seqno, seqno,
+			ktime_ms_delta(now, tlb_inval->timedout_inval_time),
+			ktime_ms_delta(now, tlb_inval->timedout_time));
+		tlb_inval->timedout_seqno = 0;
+	}
+
 	list_for_each_entry_safe(fence, next,
 				 &tlb_inval->pending_fences, link) {
 		trace_xe_tlb_inval_fence_recv(xe, fence);
diff --git a/drivers/gpu/drm/xe/xe_tlb_inval_types.h b/drivers/gpu/drm/xe/xe_tlb_inval_types.h
index 3d1797d186f..38288966254 100644
--- a/drivers/gpu/drm/xe/xe_tlb_inval_types.h
+++ b/drivers/gpu/drm/xe/xe_tlb_inval_types.h
@@ -102,6 +102,23 @@ struct xe_tlb_inval {
 	 * @pending_lock: protects @pending_fences and updating @seqno_recv.
 	 */
 	spinlock_t pending_lock;
+	/**
+	 * @timedout_seqno: seqno of the most recent timed out TLB
+	 * invalidation, 0 if none. Used to measure how late the ack for a
+	 * timed out invalidation actually arrives. Protected by
+	 * @pending_lock.
+	 */
+	int timedout_seqno;
+	/**
+	 * @timedout_inval_time: request time of @timedout_seqno. Protected by
+	 * @pending_lock.
+	 */
+	ktime_t timedout_inval_time;
+	/**
+	 * @timedout_time: time @timedout_seqno was signaled with -ETIME.
+	 * Protected by @pending_lock.
+	 */
+	ktime_t timedout_time;
 	/**
 	 * @fence_tdr: schedules a delayed call to xe_tlb_fence_timeout after
 	 * the timeout interval is over.
-- 
2.55.0

[PATCH v3 3/3] drm/xe: Implement Wa_22016122933

[Tales A. Mendonça]

On platforms with a standalone media GT and media version 13.00
(MTL/ARL), memory shared between the CPU and the media GT's GuC must
not be mapped cached on the CPU side: the CPU can otherwise read stale
cache lines for data the GuC has already written.

i915 implements this as Wa_22016122933 (see
intel_gt_needs_wa_22016122933(), used by intel_guc_allocate_vma() and
intel_gt_coherent_map_type()); xe never inherited it.

The visible symptom on ARL is TLB invalidation acks stalling for a
near-constant ~2.3s: the GuC writes the G2H ack in time, but the CPU
keeps reading a stale (empty) view of the G2H CTB until the line is
naturally evicted, so the fence timeout at 2.25s fires first. GuC log
decode confirmed all invalidations were handled promptly by the
firmware, and only the media GT was affected. See Link for the full
investigation (three machines affected: 7d51, 7dd1, Arc Pro 130T).

Making the mapping coherent instead of uncached does not help: with a
GGTT PAT entry repurposed to WB|COH_2WAY the driver comes up and the
media GT GuC runs, but the stalls remain (request-to-ack 2290ms).
Uncached really is required here. Note that 2-way coherency is not
normally reachable from a GGTT PTE (only 2 PAT bits), so that
experiment needed a modified PAT table and may not reflect a supported
configuration.

Add the OOB workaround scoped like i915 (media version 13.00, media GT
only - MEDIA_VERSION() OOB rules only match the media GT on standalone
media platforms) and apply XE_BO_FLAG_NEEDS_UC to the GuC-shared
allocations the CPU reads from: the CTBs, the GuC log, ADS, the SLPC
shared data and the engine activity buffers. hwconfig and the G2G
buffer are allocated on the primary GT only, where the workaround does
not apply.

Note that XE_BO_FLAG_NEEDS_UC drives both the CPU mapping (uncached)
and the GGTT cache mode (XE_CACHE_NONE instead of XE_CACHE_WB), which
is stricter than i915: i915 documents the workaround as WC on the CPU
side and UC on the GPU side. A CPU-WC variant with the GGTT side kept
at XE_CACHE_NONE was tested and is equally effective, but reaching it
would require either a new flag or decoupling the GGTT cache-mode
selection from XE_BO_FLAG_NEEDS_UC - simply swapping in
XE_BO_FLAG_FORCE_WC silently relaxes the GPU side back to WB and the
stalls return. Keeping the stricter mapping here; no throughput
difference between the two was measurable.

Validation on two ARL machines (7d51 and 7dd1): before, 20-60 TLB
invalidation ack stalls per day, every day, for weeks, on every kernel
and on two GuC firmware versions (70.53.0 and 70.72.1). After: zero
stalls in ~4 weeks of combined runtime, over 7M TLB invalidations
processed under the same workloads. The 7dd1 machine, which could not
survive a day of media workloads on xe without a platform freeze, has
been running xe continuously for two weeks including video
transcoding, with zero incidents.

The coherency experiment, the CPU-WC measurements and the engine
activity coverage gap were found by Navon John Lukose while A/B
testing v2 on an ARL 7d51.

Link: https://gitlab.freedesktop.org/drm/xe/kernel/-/work_items/8678
Suggested-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Tales A. Mendonça <talesam@gmail.com>
Tested-by: Navon John Lukose <navonjohnlukose@gmail.com>
---
 drivers/gpu/drm/xe/xe_guc.c                 | 16 ++++++++++++++++
 drivers/gpu/drm/xe/xe_guc.h                 |  2 ++
 drivers/gpu/drm/xe/xe_guc_ads.c             |  3 ++-
 drivers/gpu/drm/xe/xe_guc_ct.c              |  6 ++++--
 drivers/gpu/drm/xe/xe_guc_engine_activity.c |  6 ++++--
 drivers/gpu/drm/xe/xe_guc_log.c             |  7 +++++--
 drivers/gpu/drm/xe/xe_guc_pc.c              |  3 ++-
 drivers/gpu/drm/xe/xe_wa_oob.rules          |  1 +
 8 files changed, 36 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index c7f8bbd4cb9..3ab4cb9e496 100644
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -1469,6 +1469,22 @@ int xe_guc_suspend(struct xe_guc *guc)
 	return 0;
 }
 
+/**
+ * xe_guc_bo_wa_flags - Extra BO flags for memory shared with the GuC
+ * @gt: the &xe_gt whose GuC the buffer will be shared with
+ *
+ * Wa_22016122933: on the standalone media GT, memory shared between the
+ * CPU and the GuC must not be mapped cached on the CPU side, otherwise
+ * the CPU can read stale data written by the GuC (e.g. G2H CTB writes)
+ * for multiple seconds.
+ *
+ * Return: additional XE_BO_FLAG_* to use when allocating GuC-shared memory
+ */
+u32 xe_guc_bo_wa_flags(struct xe_gt *gt)
+{
+	return XE_GT_WA(gt, 22016122933) ? XE_BO_FLAG_NEEDS_UC : 0;
+}
+
 void xe_guc_notify(struct xe_guc *guc)
 {
 	struct xe_gt *gt = guc_to_gt(guc);
diff --git a/drivers/gpu/drm/xe/xe_guc.h b/drivers/gpu/drm/xe/xe_guc.h
index 61e3ee19a59..c4eca40d69c 100644
--- a/drivers/gpu/drm/xe/xe_guc.h
+++ b/drivers/gpu/drm/xe/xe_guc.h
@@ -30,6 +30,7 @@
 	xe_guc_fw_version_at_least((guc), MAKE_GUC_VER_ARGS(ver))
 
 struct drm_printer;
+struct xe_gt;
 
 void xe_guc_comm_init_early(struct xe_guc *guc);
 int xe_guc_init_noalloc(struct xe_guc *guc);
@@ -45,6 +46,7 @@ void xe_guc_runtime_suspend(struct xe_guc *guc);
 void xe_guc_runtime_resume(struct xe_guc *guc);
 int xe_guc_suspend(struct xe_guc *guc);
 int xe_guc_softreset(struct xe_guc *guc);
+u32 xe_guc_bo_wa_flags(struct xe_gt *gt);
 void xe_guc_notify(struct xe_guc *guc);
 int xe_guc_auth_huc(struct xe_guc *guc, u32 rsa_addr);
 int xe_guc_mmio_send(struct xe_guc *guc, const u32 *request, u32 len);
diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
index ff8eee3831a..abc7266fc6f 100644
--- a/drivers/gpu/drm/xe/xe_guc_ads.c
+++ b/drivers/gpu/drm/xe/xe_guc_ads.c
@@ -435,7 +435,8 @@ int xe_guc_ads_init(struct xe_guc_ads *ads)
 					  XE_BO_FLAG_SYSTEM |
 					  XE_BO_FLAG_GGTT |
 					  XE_BO_FLAG_GGTT_INVALIDATE |
-					  XE_BO_FLAG_PINNED_NORESTORE);
+					  XE_BO_FLAG_PINNED_NORESTORE |
+					  xe_guc_bo_wa_flags(gt));
 	if (IS_ERR(bo))
 		return PTR_ERR(bo);
 
diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c b/drivers/gpu/drm/xe/xe_guc_ct.c
index 5c4733da385..5c393aa29de 100644
--- a/drivers/gpu/drm/xe/xe_guc_ct.c
+++ b/drivers/gpu/drm/xe/xe_guc_ct.c
@@ -376,7 +376,8 @@ int xe_guc_ct_init(struct xe_guc_ct *ct)
 					  XE_BO_FLAG_SYSTEM |
 					  XE_BO_FLAG_GGTT |
 					  XE_BO_FLAG_GGTT_INVALIDATE |
-					  XE_BO_FLAG_PINNED_NORESTORE);
+					  XE_BO_FLAG_PINNED_NORESTORE |
+					  xe_guc_bo_wa_flags(gt));
 	if (IS_ERR(bo))
 		return PTR_ERR(bo);
 
@@ -386,7 +387,8 @@ int xe_guc_ct_init(struct xe_guc_ct *ct)
 					  XE_BO_FLAG_SYSTEM |
 					  XE_BO_FLAG_GGTT |
 					  XE_BO_FLAG_GGTT_INVALIDATE |
-					  XE_BO_FLAG_PINNED_NORESTORE);
+					  XE_BO_FLAG_PINNED_NORESTORE |
+					  xe_guc_bo_wa_flags(gt));
 	if (IS_ERR(bo))
 		return PTR_ERR(bo);
 
diff --git a/drivers/gpu/drm/xe/xe_guc_engine_activity.c b/drivers/gpu/drm/xe/xe_guc_engine_activity.c
index a782be57caa..729ce8ac140 100644
--- a/drivers/gpu/drm/xe/xe_guc_engine_activity.c
+++ b/drivers/gpu/drm/xe/xe_guc_engine_activity.c
@@ -97,7 +97,8 @@ static int allocate_engine_activity_buffers(struct xe_guc *guc,
 
 	metadata_bo = xe_bo_create_pin_map_novm(gt_to_xe(gt), tile, PAGE_ALIGN(metadata_size),
 						ttm_bo_type_kernel, XE_BO_FLAG_SYSTEM |
-						XE_BO_FLAG_GGTT | XE_BO_FLAG_GGTT_INVALIDATE,
+						XE_BO_FLAG_GGTT | XE_BO_FLAG_GGTT_INVALIDATE |
+						xe_guc_bo_wa_flags(gt),
 						false);
 
 	if (IS_ERR(metadata_bo))
@@ -105,7 +106,8 @@ static int allocate_engine_activity_buffers(struct xe_guc *guc,
 
 	bo = xe_bo_create_pin_map_novm(gt_to_xe(gt), tile, PAGE_ALIGN(size),
 				       ttm_bo_type_kernel, XE_BO_FLAG_VRAM_IF_DGFX(tile) |
-				       XE_BO_FLAG_GGTT | XE_BO_FLAG_GGTT_INVALIDATE, false);
+				       XE_BO_FLAG_GGTT | XE_BO_FLAG_GGTT_INVALIDATE |
+				       xe_guc_bo_wa_flags(gt), false);
 
 	if (IS_ERR(bo)) {
 		xe_bo_unpin_map_no_vm(metadata_bo);
diff --git a/drivers/gpu/drm/xe/xe_guc_log.c b/drivers/gpu/drm/xe/xe_guc_log.c
index 538d4df0f7a..7d006268ce9 100644
--- a/drivers/gpu/drm/xe/xe_guc_log.c
+++ b/drivers/gpu/drm/xe/xe_guc_log.c
@@ -17,6 +17,7 @@
 #include "xe_force_wake.h"
 #include "xe_gt_printk.h"
 #include "xe_gt_types.h"
+#include "xe_guc.h"
 #include "xe_map.h"
 #include "xe_mmio.h"
 #include "xe_module.h"
@@ -624,14 +625,16 @@ void xe_guc_log_print_lfd(struct xe_guc_log *log, struct drm_printer *p)
 int xe_guc_log_init(struct xe_guc_log *log)
 {
 	struct xe_device *xe = log_to_xe(log);
-	struct xe_tile *tile = gt_to_tile(log_to_gt(log));
+	struct xe_gt *gt = log_to_gt(log);
+	struct xe_tile *tile = gt_to_tile(gt);
 	struct xe_bo *bo;
 
 	bo = xe_managed_bo_create_pin_map(xe, tile, GUC_LOG_SIZE,
 					  XE_BO_FLAG_SYSTEM |
 					  XE_BO_FLAG_GGTT |
 					  XE_BO_FLAG_GGTT_INVALIDATE |
-					  XE_BO_FLAG_PINNED_NORESTORE);
+					  XE_BO_FLAG_PINNED_NORESTORE |
+					  xe_guc_bo_wa_flags(gt));
 	if (IS_ERR(bo))
 		return PTR_ERR(bo);
 
diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
index 097b075bd89..e0105222a2c 100644
--- a/drivers/gpu/drm/xe/xe_guc_pc.c
+++ b/drivers/gpu/drm/xe/xe_guc_pc.c
@@ -1391,7 +1391,8 @@ int xe_guc_pc_init(struct xe_guc_pc *pc)
 					  XE_BO_FLAG_VRAM_IF_DGFX(tile) |
 					  XE_BO_FLAG_GGTT |
 					  XE_BO_FLAG_GGTT_INVALIDATE |
-					  XE_BO_FLAG_PINNED_NORESTORE);
+					  XE_BO_FLAG_PINNED_NORESTORE |
+					  xe_guc_bo_wa_flags(gt));
 	if (IS_ERR(bo))
 		return PTR_ERR(bo);
 
diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
index dd69ad07f7a..30958b26a1d 100644
--- a/drivers/gpu/drm/xe/xe_wa_oob.rules
+++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
@@ -14,6 +14,7 @@
 16017236439	PLATFORM(PVC)
 14019821291	MEDIA_VERSION_RANGE(1300, 2000)
 14015076503	MEDIA_VERSION(1300)
+22016122933	MEDIA_VERSION(1300)
 14018913170	GRAPHICS_VERSION_RANGE(1270, 1274)
 		MEDIA_VERSION(1300)
 		PLATFORM(DG2)
-- 
2.55.0

✗ CI.checkpatch: warning for drm/xe: fix GuC TLB invalidation ack stalls on ARL (Wa_22016122933) (rev2)

[Patchwork]

== Series Details ==

Series: drm/xe: fix GuC TLB invalidation ack stalls on ARL (Wa_22016122933) (rev2)
URL   : https://patchwork.freedesktop.org/series/172110/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
061140b9bc586ae7f40abc1249c97e1cc72d1b9d
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit eebd19cb013f128d9c92b93a603b663318f8abf3
Author: Tales A. Mendonça <talesam@gmail.com>
Date:   Mon Aug 24 11:07:48 2026 -0300

    drm/xe: Implement Wa_22016122933
    
    On platforms with a standalone media GT and media version 13.00
    (MTL/ARL), memory shared between the CPU and the media GT's GuC must
    not be mapped cached on the CPU side: the CPU can otherwise read stale
    cache lines for data the GuC has already written.
    
    i915 implements this as Wa_22016122933 (see
    intel_gt_needs_wa_22016122933(), used by intel_guc_allocate_vma() and
    intel_gt_coherent_map_type()); xe never inherited it.
    
    The visible symptom on ARL is TLB invalidation acks stalling for a
    near-constant ~2.3s: the GuC writes the G2H ack in time, but the CPU
    keeps reading a stale (empty) view of the G2H CTB until the line is
    naturally evicted, so the fence timeout at 2.25s fires first. GuC log
    decode confirmed all invalidations were handled promptly by the
    firmware, and only the media GT was affected. See Link for the full
    investigation (three machines affected: 7d51, 7dd1, Arc Pro 130T).
    
    Making the mapping coherent instead of uncached does not help: with a
    GGTT PAT entry repurposed to WB|COH_2WAY the driver comes up and the
    media GT GuC runs, but the stalls remain (request-to-ack 2290ms).
    Uncached really is required here. Note that 2-way coherency is not
    normally reachable from a GGTT PTE (only 2 PAT bits), so that
    experiment needed a modified PAT table and may not reflect a supported
    configuration.
    
    Add the OOB workaround scoped like i915 (media version 13.00, media GT
    only - MEDIA_VERSION() OOB rules only match the media GT on standalone
    media platforms) and apply XE_BO_FLAG_NEEDS_UC to the GuC-shared
    allocations the CPU reads from: the CTBs, the GuC log, ADS, the SLPC
    shared data and the engine activity buffers. hwconfig and the G2G
    buffer are allocated on the primary GT only, where the workaround does
    not apply.
    
    Note that XE_BO_FLAG_NEEDS_UC drives both the CPU mapping (uncached)
    and the GGTT cache mode (XE_CACHE_NONE instead of XE_CACHE_WB), which
    is stricter than i915: i915 documents the workaround as WC on the CPU
    side and UC on the GPU side. A CPU-WC variant with the GGTT side kept
    at XE_CACHE_NONE was tested and is equally effective, but reaching it
    would require either a new flag or decoupling the GGTT cache-mode
    selection from XE_BO_FLAG_NEEDS_UC - simply swapping in
    XE_BO_FLAG_FORCE_WC silently relaxes the GPU side back to WB and the
    stalls return. Keeping the stricter mapping here; no throughput
    difference between the two was measurable.
    
    Validation on two ARL machines (7d51 and 7dd1): before, 20-60 TLB
    invalidation ack stalls per day, every day, for weeks, on every kernel
    and on two GuC firmware versions (70.53.0 and 70.72.1). After: zero
    stalls in ~4 weeks of combined runtime, over 7M TLB invalidations
    processed under the same workloads. The 7dd1 machine, which could not
    survive a day of media workloads on xe without a platform freeze, has
    been running xe continuously for two weeks including video
    transcoding, with zero incidents.
    
    The coherency experiment, the CPU-WC measurements and the engine
    activity coverage gap were found by Navon John Lukose while A/B
    testing v2 on an ARL 7d51.
    
    Link: https://gitlab.freedesktop.org/drm/xe/kernel/-/work_items/8678
    Suggested-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
    Signed-off-by: Tales A. Mendonça <talesam@gmail.com>
    Tested-by: Navon John Lukose <navonjohnlukose@gmail.com>
+ /mt/dim checkpatch 15e2ba2fb6d25c03d89519aec46f8d5be3e118ad drm-intel
0ba5f0836fb7 drm/xe: Capture devcoredump on TLB invalidation timeout
-:168: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_q' - possible side-effects?
#168: FILE: drivers/gpu/drm/xe/xe_devcoredump.h:34:
+#define xe_devcoredump(_q, _job, _fmt, ...) \
+	__xe_devcoredump((_q)->gt, _q, _job, _fmt, ##__VA_ARGS__)

total: 0 errors, 0 warnings, 1 checks, 184 lines checked
37f890bc677c drm/xe: Log when a timed out TLB invalidation ack finally arrives
eebd19cb013f drm/xe: Implement Wa_22016122933

✓ CI.KUnit: success for drm/xe: fix GuC TLB invalidation ack stalls on ARL (Wa_22016122933) (rev2)

[Patchwork]

== Series Details ==

Series: drm/xe: fix GuC TLB invalidation ack stalls on ARL (Wa_22016122933) (rev2)
URL   : https://patchwork.freedesktop.org/series/172110/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[06:23:18] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[06:23:22] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[06:23:55] Starting KUnit Kernel (1/1)...
[06:23:55] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[06:23:55] ================== guc_buf (11 subtests) ===================
[06:23:55] [PASSED] test_smallest
[06:23:55] [PASSED] test_largest
[06:23:55] [PASSED] test_granular
[06:23:55] [PASSED] test_unique
[06:23:55] [PASSED] test_overlap
[06:23:55] [PASSED] test_reusable
[06:23:55] [PASSED] test_too_big
[06:23:55] [PASSED] test_flush
[06:23:55] [PASSED] test_lookup
[06:23:55] [PASSED] test_data
[06:23:55] [PASSED] test_class
[06:23:55] ===================== [PASSED] guc_buf =====================
[06:23:55] =================== guc_dbm (7 subtests) ===================
[06:23:55] [PASSED] test_empty
[06:23:55] [PASSED] test_default
[06:23:55] ======================== test_size  ========================
[06:23:55] [PASSED] 4
[06:23:55] [PASSED] 8
[06:23:55] [PASSED] 32
[06:23:55] [PASSED] 256
[06:23:55] ==================== [PASSED] test_size ====================
[06:23:55] ======================= test_reuse  ========================
[06:23:55] [PASSED] 4
[06:23:55] [PASSED] 8
[06:23:55] [PASSED] 32
[06:23:55] [PASSED] 256
[06:23:55] =================== [PASSED] test_reuse ====================
[06:23:55] =================== test_range_overlap  ====================
[06:23:55] [PASSED] 4
[06:23:55] [PASSED] 8
[06:23:55] [PASSED] 32
[06:23:55] [PASSED] 256
[06:23:55] =============== [PASSED] test_range_overlap ================
[06:23:55] =================== test_range_compact  ====================
[06:23:55] [PASSED] 4
[06:23:55] [PASSED] 8
[06:23:55] [PASSED] 32
[06:23:55] [PASSED] 256
[06:23:55] =============== [PASSED] test_range_compact ================
[06:23:55] ==================== test_range_spare  =====================
[06:23:55] [PASSED] 4
[06:23:55] [PASSED] 8
[06:23:55] [PASSED] 32
[06:23:55] [PASSED] 256
[06:23:55] ================ [PASSED] test_range_spare =================
[06:23:55] ===================== [PASSED] guc_dbm =====================
[06:23:55] =================== guc_idm (6 subtests) ===================
[06:23:55] [PASSED] bad_init
[06:23:55] [PASSED] no_init
[06:23:55] [PASSED] init_fini
[06:23:55] [PASSED] check_used
[06:23:55] [PASSED] check_quota
[06:23:55] [PASSED] check_all
[06:23:55] ===================== [PASSED] guc_idm =====================
[06:23:55] =============== guc_klv_helpers (9 subtests) ===============
[06:23:55] [PASSED] test_count
[06:23:55] [PASSED] test_encode_u32
[06:23:55] [PASSED] test_encode_u64
[06:23:55] [PASSED] test_encode_string
[06:23:55] [PASSED] test_encode_object_raw
[06:23:55] [PASSED] test_encode_object_klv
[06:23:55] [PASSED] test_encode_object_nested
[06:23:55] [PASSED] test_encode_object_basic
[06:23:55] [PASSED] test_print
[06:23:55] ================= [PASSED] guc_klv_helpers =================
[06:23:55] =================== xe_log (4 subtests) ====================
[06:23:55] [PASSED] demo_cper
[06:23:55] [PASSED] demo_dmesg
[06:23:55] ======================= test_dmesg  ========================
[06:23:55] [PASSED] test_fatal
[06:23:55] [PASSED] test_fatal_tile
[06:23:55] [PASSED] test_fatal_gt
[06:23:55] [PASSED] test_fatal_comp
[06:23:55] [PASSED] test_fatal_comp_tile
[06:23:55] [PASSED] test_fatal_comp_gt
[06:23:55] [PASSED] test_fatal_all
[06:23:55] [PASSED] test_recoverable
[06:23:55] [PASSED] test_recoverable_tile
[06:23:55] [PASSED] test_recoverable_gt
[06:23:55] [PASSED] test_recoverable_comp
[06:23:55] [PASSED] test_recoverable_comp_tile
[06:23:55] [PASSED] test_recoverable_comp_gt
[06:23:55] [PASSED] test_recoverable_all
[06:23:55] [PASSED] test_info
[06:23:55] [PASSED] test_info_tile
[06:23:55] [PASSED] test_info_gt
[06:23:55] [PASSED] test_info_err
[06:23:55] [PASSED] test_info_comp
[06:23:55] [PASSED] test_info_comp_tile
[06:23:55] [PASSED] test_info_comp_gt
[06:23:55] [PASSED] test_info_all
[06:23:55] [PASSED] test_hw_fatal
[06:23:55] [PASSED] test_hw_recoverable
[06:23:55] [PASSED] test_hw_corrected
[06:23:55] [PASSED] test_hw_informational
[06:23:55] =================== [PASSED] test_dmesg ====================
[06:23:55] ====================== test_invalid  =======================
[06:23:55] [SKIPPED] no-component no-location no-warn (requires CONFIG_DRM_XE_DEBUG)
[06:23:55] [SKIPPED] reserved location (requires CONFIG_DRM_XE_DEBUG)
[06:23:55] [SKIPPED] unknown location (requires CONFIG_DRM_XE_DEBUG)
[06:23:55] [SKIPPED] nonzero-device-id location (requires CONFIG_DRM_XE_DEBUG)
[06:23:55] [SKIPPED] invalid-tile-id location (requires CONFIG_DRM_XE_DEBUG)
[06:23:55] [SKIPPED] invalid-gt-id location (requires CONFIG_DRM_XE_DEBUG)
[06:23:55] [SKIPPED] unknown component class (requires CONFIG_DRM_XE_DEBUG)
[06:23:55] [SKIPPED] unknown system component (requires CONFIG_DRM_XE_DEBUG)
[06:23:55] [SKIPPED] unknown hardware component (requires CONFIG_DRM_XE_DEBUG)
[06:23:55] [SKIPPED] unknown component and location (requires CONFIG_DRM_XE_DEBUG)
[06:23:55] ================== [SKIPPED] test_invalid ==================
[06:23:55] ===================== [PASSED] xe_log ======================
[06:23:55] ================== no_relay (3 subtests) ===================
[06:23:55] [PASSED] xe_drops_guc2pf_if_not_ready
[06:23:55] [PASSED] xe_drops_guc2vf_if_not_ready
[06:23:55] [PASSED] xe_rejects_send_if_not_ready
[06:23:55] ==================== [PASSED] no_relay =====================
[06:23:55] ================== pf_relay (14 subtests) ==================
[06:23:55] [PASSED] pf_rejects_guc2pf_too_short
[06:23:55] [PASSED] pf_rejects_guc2pf_too_long
[06:23:55] [PASSED] pf_rejects_guc2pf_no_payload
[06:23:55] [PASSED] pf_fails_no_payload
[06:23:55] [PASSED] pf_fails_bad_origin
[06:23:55] [PASSED] pf_fails_bad_type
[06:23:55] [PASSED] pf_txn_reports_error
[06:23:55] [PASSED] pf_txn_sends_pf2guc
[06:23:55] [PASSED] pf_sends_pf2guc
[06:23:55] [SKIPPED] pf_loopback_nop (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[06:23:55] [SKIPPED] pf_loopback_echo (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[06:23:55] [SKIPPED] pf_loopback_fail (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[06:23:55] [SKIPPED] pf_loopback_busy (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[06:23:55] [SKIPPED] pf_loopback_retry (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[06:23:55] ==================== [PASSED] pf_relay =====================
[06:23:55] ================== vf_relay (3 subtests) ===================
[06:23:55] [PASSED] vf_rejects_guc2vf_too_short
[06:23:55] [PASSED] vf_rejects_guc2vf_too_long
[06:23:55] [PASSED] vf_rejects_guc2vf_no_payload
[06:23:55] ==================== [PASSED] vf_relay =====================
[06:23:55] ================ pf_gt_config (9 subtests) =================
[06:23:55] [PASSED] fair_contexts_1vf
[06:23:55] [PASSED] fair_doorbells_1vf
[06:23:55] [PASSED] fair_ggtt_1vf
[06:23:55] ====================== fair_vram_1vf  ======================
[06:23:55] [PASSED] 3.50 GiB
[06:23:55] [PASSED] 11.5 GiB
[06:23:55] [PASSED] 15.5 GiB
[06:23:55] [PASSED] 31.5 GiB
[06:23:55] [PASSED] 63.5 GiB
[06:23:55] [PASSED] 1.91 GiB
[06:23:55] ================== [PASSED] fair_vram_1vf ==================
[06:23:55] ================ fair_vram_1vf_admin_only  =================
[06:23:55] [PASSED] 3.50 GiB
[06:23:55] [PASSED] 11.5 GiB
[06:23:55] [PASSED] 15.5 GiB
[06:23:55] [PASSED] 31.5 GiB
[06:23:55] [PASSED] 63.5 GiB
[06:23:55] [PASSED] 1.91 GiB
[06:23:55] ============ [PASSED] fair_vram_1vf_admin_only =============
[06:23:55] ====================== fair_contexts  ======================
[06:23:55] [PASSED] 1 VF
[06:23:55] [PASSED] 2 VFs
[06:23:55] [PASSED] 3 VFs
[06:23:55] [PASSED] 4 VFs
[06:23:55] [PASSED] 5 VFs
[06:23:55] [PASSED] 6 VFs
[06:23:55] [PASSED] 7 VFs
[06:23:55] [PASSED] 8 VFs
[06:23:55] [PASSED] 9 VFs
[06:23:55] [PASSED] 10 VFs
[06:23:55] [PASSED] 11 VFs
[06:23:55] [PASSED] 12 VFs
[06:23:55] [PASSED] 13 VFs
[06:23:55] [PASSED] 14 VFs
[06:23:55] [PASSED] 15 VFs
[06:23:55] [PASSED] 16 VFs
[06:23:55] [PASSED] 17 VFs
[06:23:55] [PASSED] 18 VFs
[06:23:55] [PASSED] 19 VFs
[06:23:55] [PASSED] 20 VFs
[06:23:55] [PASSED] 21 VFs
[06:23:55] [PASSED] 22 VFs
[06:23:55] [PASSED] 23 VFs
[06:23:55] [PASSED] 24 VFs
[06:23:55] [PASSED] 25 VFs
[06:23:55] [PASSED] 26 VFs
[06:23:55] [PASSED] 27 VFs
[06:23:55] [PASSED] 28 VFs
[06:23:55] [PASSED] 29 VFs
[06:23:55] [PASSED] 30 VFs
[06:23:55] [PASSED] 31 VFs
[06:23:55] [PASSED] 32 VFs
[06:23:55] [PASSED] 33 VFs
[06:23:55] [PASSED] 34 VFs
[06:23:55] [PASSED] 35 VFs
[06:23:55] [PASSED] 36 VFs
[06:23:55] [PASSED] 37 VFs
[06:23:55] [PASSED] 38 VFs
[06:23:55] [PASSED] 39 VFs
[06:23:55] [PASSED] 40 VFs
[06:23:55] [PASSED] 41 VFs
[06:23:55] [PASSED] 42 VFs
[06:23:55] [PASSED] 43 VFs
[06:23:55] [PASSED] 44 VFs
[06:23:55] [PASSED] 45 VFs
[06:23:55] [PASSED] 46 VFs
[06:23:55] [PASSED] 47 VFs
[06:23:55] [PASSED] 48 VFs
[06:23:55] [PASSED] 49 VFs
[06:23:55] [PASSED] 50 VFs
[06:23:55] [PASSED] 51 VFs
[06:23:55] [PASSED] 52 VFs
[06:23:55] [PASSED] 53 VFs
[06:23:55] [PASSED] 54 VFs
[06:23:55] [PASSED] 55 VFs
[06:23:55] [PASSED] 56 VFs
[06:23:55] [PASSED] 57 VFs
[06:23:55] [PASSED] 58 VFs
[06:23:55] [PASSED] 59 VFs
[06:23:55] [PASSED] 60 VFs
[06:23:55] [PASSED] 61 VFs
[06:23:55] [PASSED] 62 VFs
[06:23:55] [PASSED] 63 VFs
[06:23:55] ================== [PASSED] fair_contexts ==================
[06:23:55] ===================== fair_doorbells  ======================
[06:23:55] [PASSED] 1 VF
[06:23:55] [PASSED] 2 VFs
[06:23:55] [PASSED] 3 VFs
[06:23:55] [PASSED] 4 VFs
[06:23:55] [PASSED] 5 VFs
[06:23:55] [PASSED] 6 VFs
[06:23:55] [PASSED] 7 VFs
[06:23:55] [PASSED] 8 VFs
[06:23:55] [PASSED] 9 VFs
[06:23:55] [PASSED] 10 VFs
[06:23:55] [PASSED] 11 VFs
[06:23:55] [PASSED] 12 VFs
[06:23:55] [PASSED] 13 VFs
[06:23:55] [PASSED] 14 VFs
[06:23:55] [PASSED] 15 VFs
[06:23:55] [PASSED] 16 VFs
[06:23:55] [PASSED] 17 VFs
[06:23:55] [PASSED] 18 VFs
[06:23:55] [PASSED] 19 VFs
[06:23:55] [PASSED] 20 VFs
[06:23:55] [PASSED] 21 VFs
[06:23:55] [PASSED] 22 VFs
[06:23:55] [PASSED] 23 VFs
[06:23:55] [PASSED] 24 VFs
[06:23:55] [PASSED] 25 VFs
[06:23:55] [PASSED] 26 VFs
[06:23:55] [PASSED] 27 VFs
[06:23:55] [PASSED] 28 VFs
[06:23:55] [PASSED] 29 VFs
[06:23:55] [PASSED] 30 VFs
[06:23:55] [PASSED] 31 VFs
[06:23:55] [PASSED] 32 VFs
[06:23:55] [PASSED] 33 VFs
[06:23:55] [PASSED] 34 VFs
[06:23:55] [PASSED] 35 VFs
[06:23:55] [PASSED] 36 VFs
[06:23:55] [PASSED] 37 VFs
[06:23:55] [PASSED] 38 VFs
[06:23:55] [PASSED] 39 VFs
[06:23:55] [PASSED] 40 VFs
[06:23:55] [PASSED] 41 VFs
[06:23:55] [PASSED] 42 VFs
[06:23:55] [PASSED] 43 VFs
[06:23:55] [PASSED] 44 VFs
[06:23:55] [PASSED] 45 VFs
[06:23:55] [PASSED] 46 VFs
[06:23:55] [PASSED] 47 VFs
[06:23:55] [PASSED] 48 VFs
[06:23:55] [PASSED] 49 VFs
[06:23:55] [PASSED] 50 VFs
[06:23:55] [PASSED] 51 VFs
[06:23:55] [PASSED] 52 VFs
[06:23:55] [PASSED] 53 VFs
[06:23:55] [PASSED] 54 VFs
[06:23:55] [PASSED] 55 VFs
[06:23:55] [PASSED] 56 VFs
[06:23:55] [PASSED] 57 VFs
[06:23:55] [PASSED] 58 VFs
[06:23:55] [PASSED] 59 VFs
[06:23:55] [PASSED] 60 VFs
[06:23:55] [PASSED] 61 VFs
[06:23:55] [PASSED] 62 VFs
[06:23:55] [PASSED] 63 VFs
[06:23:55] ================= [PASSED] fair_doorbells ==================
[06:23:55] ======================== fair_ggtt  ========================
[06:23:55] [PASSED] 1 VF
[06:23:55] [PASSED] 2 VFs
[06:23:55] [PASSED] 3 VFs
[06:23:55] [PASSED] 4 VFs
[06:23:55] [PASSED] 5 VFs
[06:23:55] [PASSED] 6 VFs
[06:23:55] [PASSED] 7 VFs
[06:23:55] [PASSED] 8 VFs
[06:23:55] [PASSED] 9 VFs
[06:23:55] [PASSED] 10 VFs
[06:23:55] [PASSED] 11 VFs
[06:23:55] [PASSED] 12 VFs
[06:23:55] [PASSED] 13 VFs
[06:23:55] [PASSED] 14 VFs
[06:23:55] [PASSED] 15 VFs
[06:23:55] [PASSED] 16 VFs
[06:23:55] [PASSED] 17 VFs
[06:23:55] [PASSED] 18 VFs
[06:23:55] [PASSED] 19 VFs
[06:23:55] [PASSED] 20 VFs
[06:23:55] [PASSED] 21 VFs
[06:23:55] [PASSED] 22 VFs
[06:23:55] [PASSED] 23 VFs
[06:23:55] [PASSED] 24 VFs
[06:23:55] [PASSED] 25 VFs
[06:23:55] [PASSED] 26 VFs
[06:23:55] [PASSED] 27 VFs
[06:23:55] [PASSED] 28 VFs
[06:23:55] [PASSED] 29 VFs
[06:23:55] [PASSED] 30 VFs
[06:23:55] [PASSED] 31 VFs
[06:23:55] [PASSED] 32 VFs
[06:23:55] [PASSED] 33 VFs
[06:23:55] [PASSED] 34 VFs
[06:23:55] [PASSED] 35 VFs
[06:23:55] [PASSED] 36 VFs
[06:23:55] [PASSED] 37 VFs
[06:23:55] [PASSED] 38 VFs
[06:23:55] [PASSED] 39 VFs
[06:23:55] [PASSED] 40 VFs
[06:23:55] [PASSED] 41 VFs
[06:23:55] [PASSED] 42 VFs
[06:23:55] [PASSED] 43 VFs
[06:23:55] [PASSED] 44 VFs
[06:23:55] [PASSED] 45 VFs
[06:23:55] [PASSED] 46 VFs
[06:23:55] [PASSED] 47 VFs
[06:23:55] [PASSED] 48 VFs
[06:23:55] [PASSED] 49 VFs
[06:23:55] [PASSED] 50 VFs
[06:23:55] [PASSED] 51 VFs
[06:23:55] [PASSED] 52 VFs
[06:23:55] [PASSED] 53 VFs
[06:23:55] [PASSED] 54 VFs
[06:23:55] [PASSED] 55 VFs
[06:23:55] [PASSED] 56 VFs
[06:23:55] [PASSED] 57 VFs
[06:23:55] [PASSED] 58 VFs
[06:23:55] [PASSED] 59 VFs
[06:23:55] [PASSED] 60 VFs
[06:23:55] [PASSED] 61 VFs
[06:23:55] [PASSED] 62 VFs
[06:23:55] [PASSED] 63 VFs
[06:23:55] ==================== [PASSED] fair_ggtt ====================
[06:23:55] ======================== fair_vram  ========================
[06:23:55] [PASSED] 1 VF
[06:23:55] [PASSED] 2 VFs
[06:23:55] [PASSED] 3 VFs
[06:23:55] [PASSED] 4 VFs
[06:23:55] [PASSED] 5 VFs
[06:23:55] [PASSED] 6 VFs
[06:23:55] [PASSED] 7 VFs
[06:23:55] [PASSED] 8 VFs
[06:23:56] [PASSED] 9 VFs
[06:23:56] [PASSED] 10 VFs
[06:23:56] [PASSED] 11 VFs
[06:23:56] [PASSED] 12 VFs
[06:23:56] [PASSED] 13 VFs
[06:23:56] [PASSED] 14 VFs
[06:23:56] [PASSED] 15 VFs
[06:23:56] [PASSED] 16 VFs
[06:23:56] [PASSED] 17 VFs
[06:23:56] [PASSED] 18 VFs
[06:23:56] [PASSED] 19 VFs
[06:23:56] [PASSED] 20 VFs
[06:23:56] [PASSED] 21 VFs
[06:23:56] [PASSED] 22 VFs
[06:23:56] [PASSED] 23 VFs
[06:23:56] [PASSED] 24 VFs
[06:23:56] [PASSED] 25 VFs
[06:23:56] [PASSED] 26 VFs
[06:23:56] [PASSED] 27 VFs
[06:23:56] [PASSED] 28 VFs
[06:23:56] [PASSED] 29 VFs
[06:23:56] [PASSED] 30 VFs
[06:23:56] [PASSED] 31 VFs
[06:23:56] [PASSED] 32 VFs
[06:23:56] [PASSED] 33 VFs
[06:23:56] [PASSED] 34 VFs
[06:23:56] [PASSED] 35 VFs
[06:23:56] [PASSED] 36 VFs
[06:23:56] [PASSED] 37 VFs
[06:23:56] [PASSED] 38 VFs
[06:23:56] [PASSED] 39 VFs
[06:23:56] [PASSED] 40 VFs
[06:23:56] [PASSED] 41 VFs
[06:23:56] [PASSED] 42 VFs
[06:23:56] [PASSED] 43 VFs
[06:23:56] [PASSED] 44 VFs
[06:23:56] [PASSED] 45 VFs
[06:23:56] [PASSED] 46 VFs
[06:23:56] [PASSED] 47 VFs
[06:23:56] [PASSED] 48 VFs
[06:23:56] [PASSED] 49 VFs
[06:23:56] [PASSED] 50 VFs
[06:23:56] [PASSED] 51 VFs
[06:23:56] [PASSED] 52 VFs
[06:23:56] [PASSED] 53 VFs
[06:23:56] [PASSED] 54 VFs
[06:23:56] [PASSED] 55 VFs
[06:23:56] [PASSED] 56 VFs
[06:23:56] [PASSED] 57 VFs
[06:23:56] [PASSED] 58 VFs
[06:23:56] [PASSED] 59 VFs
[06:23:56] [PASSED] 60 VFs
[06:23:56] [PASSED] 61 VFs
[06:23:56] [PASSED] 62 VFs
[06:23:56] [PASSED] 63 VFs
[06:23:56] ==================== [PASSED] fair_vram ====================
[06:23:56] ================== [PASSED] pf_gt_config ===================
[06:23:56] ===================== lmtt (1 subtest) =====================
[06:23:56] ======================== test_ops  =========================
[06:23:56] [PASSED] 2-level
[06:23:56] [PASSED] multi-level
[06:23:56] ==================== [PASSED] test_ops =====================
[06:23:56] ====================== [PASSED] lmtt =======================
[06:23:56] ================= sriov_packet (1 subtest) =================
[06:23:56] [PASSED] test_descriptor_init
[06:23:56] ================== [PASSED] sriov_packet ===================
[06:23:56] ================= pf_service (11 subtests) =================
[06:23:56] [PASSED] pf_negotiate_any
[06:23:56] [PASSED] pf_negotiate_base_match
[06:23:56] [PASSED] pf_negotiate_base_newer
[06:23:56] [PASSED] pf_negotiate_base_next
[06:23:56] [SKIPPED] pf_negotiate_base_older (no older minor)
[06:23:56] [PASSED] pf_negotiate_base_prev
[06:23:56] [PASSED] pf_negotiate_latest_match
[06:23:56] [PASSED] pf_negotiate_latest_newer
[06:23:56] [PASSED] pf_negotiate_latest_next
[06:23:56] [SKIPPED] pf_negotiate_latest_older (no older minor)
[06:23:56] [SKIPPED] pf_negotiate_latest_prev (no prev major)
[06:23:56] =================== [PASSED] pf_service ====================
[06:23:56] ================= xe_guc_g2g (2 subtests) ==================
[06:23:56] ============== xe_live_guc_g2g_kunit_default  ==============
[06:23:56] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[06:23:56] ============== xe_live_guc_g2g_kunit_allmem  ===============
[06:23:56] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[06:23:56] =================== [SKIPPED] xe_guc_g2g ===================
[06:23:56] =================== xe_mocs (2 subtests) ===================
[06:23:56] ================ xe_live_mocs_kernel_kunit  ================
[06:23:56] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[06:23:56] ================ xe_live_mocs_reset_kunit  =================
[06:23:56] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[06:23:56] ==================== [SKIPPED] xe_mocs =====================
[06:23:56] ================= xe_migrate (2 subtests) ==================
[06:23:56] ================= xe_migrate_sanity_kunit  =================
[06:23:56] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[06:23:56] ================== xe_validate_ccs_kunit  ==================
[06:23:56] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[06:23:56] =================== [SKIPPED] xe_migrate ===================
[06:23:56] ================== xe_dma_buf (1 subtest) ==================
[06:23:56] ==================== xe_dma_buf_kunit  =====================
[06:23:56] ================ [SKIPPED] xe_dma_buf_kunit ================
[06:23:56] =================== [SKIPPED] xe_dma_buf ===================
[06:23:56] ================= xe_bo_shrink (1 subtest) =================
[06:23:56] =================== xe_bo_shrink_kunit  ====================
[06:23:56] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[06:23:56] ================== [SKIPPED] xe_bo_shrink ==================
[06:23:56] ==================== xe_bo (2 subtests) ====================
[06:23:56] ================== xe_ccs_migrate_kunit  ===================
[06:23:56] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[06:23:56] ==================== xe_bo_evict_kunit  ====================
[06:23:56] =============== [SKIPPED] xe_bo_evict_kunit ================
[06:23:56] ===================== [SKIPPED] xe_bo ======================
[06:23:56] =================== xe_any (9 subtests) ====================
[06:23:56] [PASSED] test_to_xe
[06:23:56] [PASSED] test_to_dev
[06:23:56] [PASSED] test_to_pdev
[06:23:56] [PASSED] test_to_drm
[06:23:56] [PASSED] test_if_pdev
[06:23:56] [PASSED] test_if_xe
[06:23:56] [PASSED] test_if_tile
[06:23:56] [PASSED] test_if_gt
[06:23:56] [PASSED] test_to_id
[06:23:56] ===================== [PASSED] xe_any ======================
[06:23:56] ==================== args (13 subtests) ====================
[06:23:56] [PASSED] count_args_test
[06:23:56] [PASSED] call_args_example
[06:23:56] [PASSED] call_args_test
[06:23:56] [PASSED] drop_first_arg_example
[06:23:56] [PASSED] drop_first_arg_test
[06:23:56] [PASSED] first_arg_example
[06:23:56] [PASSED] first_arg_test
[06:23:56] [PASSED] last_arg_example
[06:23:56] [PASSED] last_arg_test
[06:23:56] [PASSED] pick_arg_example
[06:23:56] [PASSED] if_args_example
[06:23:56] [PASSED] if_args_test
[06:23:56] [PASSED] sep_comma_example
[06:23:56] ====================== [PASSED] args =======================
[06:23:56] =================== xe_pci (3 subtests) ====================
[06:23:56] ==================== check_graphics_ip  ====================
[06:23:56] [PASSED] 12.00 Xe_LP
[06:23:56] [PASSED] 12.10 Xe_LP+
[06:23:56] [PASSED] 12.55 Xe_HPG
[06:23:56] [PASSED] 12.60 Xe_HPC
[06:23:56] [PASSED] 12.70 Xe_LPG
[06:23:56] [PASSED] 12.71 Xe_LPG
[06:23:56] [PASSED] 12.74 Xe_LPG+
[06:23:56] [PASSED] 20.01 Xe2_HPG
[06:23:56] [PASSED] 20.02 Xe2_HPG
[06:23:56] [PASSED] 20.04 Xe2_LPG
[06:23:56] [PASSED] 30.00 Xe3_LPG
[06:23:56] [PASSED] 30.01 Xe3_LPG
[06:23:56] [PASSED] 30.03 Xe3_LPG
[06:23:56] [PASSED] 30.04 Xe3_LPG
[06:23:56] [PASSED] 30.05 Xe3_LPG
[06:23:56] [PASSED] 35.10 Xe3p_LPG
[06:23:56] [PASSED] 35.11 Xe3p_XPC
[06:23:56] ================ [PASSED] check_graphics_ip ================
[06:23:56] ===================== check_media_ip  ======================
[06:23:56] [PASSED] 12.00 Xe_M
[06:23:56] [PASSED] 12.55 Xe_HPM
[06:23:56] [PASSED] 13.00 Xe_LPM+
[06:23:56] [PASSED] 13.01 Xe2_HPM
[06:23:56] [PASSED] 20.00 Xe2_LPM
[06:23:56] [PASSED] 30.00 Xe3_LPM
[06:23:56] [PASSED] 30.02 Xe3_LPM
[06:23:56] [PASSED] 35.00 Xe3p_LPM
[06:23:56] [PASSED] 35.03 Xe3p_HPM
[06:23:56] ================= [PASSED] check_media_ip ==================
[06:23:56] =================== check_platform_desc  ===================
[06:23:56] [PASSED] 0x9A60 (TIGERLAKE)
[06:23:56] [PASSED] 0x9A68 (TIGERLAKE)
[06:23:56] [PASSED] 0x9A70 (TIGERLAKE)
[06:23:56] [PASSED] 0x9A40 (TIGERLAKE)
[06:23:56] [PASSED] 0x9A49 (TIGERLAKE)
[06:23:56] [PASSED] 0x9A59 (TIGERLAKE)
[06:23:56] [PASSED] 0x9A78 (TIGERLAKE)
[06:23:56] [PASSED] 0x9AC0 (TIGERLAKE)
[06:23:56] [PASSED] 0x9AC9 (TIGERLAKE)
[06:23:56] [PASSED] 0x9AD9 (TIGERLAKE)
[06:23:56] [PASSED] 0x9AF8 (TIGERLAKE)
[06:23:56] [PASSED] 0x4C80 (ROCKETLAKE)
[06:23:56] [PASSED] 0x4C8A (ROCKETLAKE)
[06:23:56] [PASSED] 0x4C8B (ROCKETLAKE)
[06:23:56] [PASSED] 0x4C8C (ROCKETLAKE)
[06:23:56] [PASSED] 0x4C90 (ROCKETLAKE)
[06:23:56] [PASSED] 0x4C9A (ROCKETLAKE)
[06:23:56] [PASSED] 0x4680 (ALDERLAKE_S)
[06:23:56] [PASSED] 0x4682 (ALDERLAKE_S)
[06:23:56] [PASSED] 0x4688 (ALDERLAKE_S)
[06:23:56] [PASSED] 0x468A (ALDERLAKE_S)
[06:23:56] [PASSED] 0x468B (ALDERLAKE_S)
[06:23:56] [PASSED] 0x4690 (ALDERLAKE_S)
[06:23:56] [PASSED] 0x4692 (ALDERLAKE_S)
[06:23:56] [PASSED] 0x4693 (ALDERLAKE_S)
[06:23:56] [PASSED] 0x46A0 (ALDERLAKE_P)
[06:23:56] [PASSED] 0x46A1 (ALDERLAKE_P)
[06:23:56] [PASSED] 0x46A2 (ALDERLAKE_P)
[06:23:56] [PASSED] 0x46A3 (ALDERLAKE_P)
[06:23:56] [PASSED] 0x46A6 (ALDERLAKE_P)
[06:23:56] [PASSED] 0x46A8 (ALDERLAKE_P)
[06:23:56] [PASSED] 0x46AA (ALDERLAKE_P)
[06:23:56] [PASSED] 0x462A (ALDERLAKE_P)
[06:23:56] [PASSED] 0x4626 (ALDERLAKE_P)
[06:23:56] [PASSED] 0x4628 (ALDERLAKE_P)
[06:23:56] [PASSED] 0x46B0 (ALDERLAKE_P)
[06:23:56] [PASSED] 0x46B1 (ALDERLAKE_P)
[06:23:56] [PASSED] 0x46B2 (ALDERLAKE_P)
[06:23:56] [PASSED] 0x46B3 (ALDERLAKE_P)
[06:23:56] [PASSED] 0x46C0 (ALDERLAKE_P)
[06:23:56] [PASSED] 0x46C1 (ALDERLAKE_P)
[06:23:56] [PASSED] 0x46C2 (ALDERLAKE_P)
[06:23:56] [PASSED] 0x46C3 (ALDERLAKE_P)
[06:23:56] [PASSED] 0x46D0 (ALDERLAKE_N)
[06:23:56] [PASSED] 0x46D1 (ALDERLAKE_N)
[06:23:56] [PASSED] 0x46D2 (ALDERLAKE_N)
[06:23:56] [PASSED] 0x46D3 (ALDERLAKE_N)
[06:23:56] [PASSED] 0x46D4 (ALDERLAKE_N)
[06:23:56] [PASSED] 0xA721 (ALDERLAKE_P)
[06:23:56] [PASSED] 0xA7A1 (ALDERLAKE_P)
[06:23:56] [PASSED] 0xA7A9 (ALDERLAKE_P)
[06:23:56] [PASSED] 0xA7AC (ALDERLAKE_P)
[06:23:56] [PASSED] 0xA7AD (ALDERLAKE_P)
[06:23:56] [PASSED] 0xA720 (ALDERLAKE_P)
[06:23:56] [PASSED] 0xA7A0 (ALDERLAKE_P)
[06:23:56] [PASSED] 0xA7A8 (ALDERLAKE_P)
[06:23:56] [PASSED] 0xA7AA (ALDERLAKE_P)
[06:23:56] [PASSED] 0xA7AB (ALDERLAKE_P)
[06:23:56] [PASSED] 0xA780 (ALDERLAKE_S)
[06:23:56] [PASSED] 0xA781 (ALDERLAKE_S)
[06:23:56] [PASSED] 0xA782 (ALDERLAKE_S)
[06:23:56] [PASSED] 0xA783 (ALDERLAKE_S)
[06:23:56] [PASSED] 0xA788 (ALDERLAKE_S)
[06:23:56] [PASSED] 0xA789 (ALDERLAKE_S)
[06:23:56] [PASSED] 0xA78A (ALDERLAKE_S)
[06:23:56] [PASSED] 0xA78B (ALDERLAKE_S)
[06:23:56] [PASSED] 0x4905 (DG1)
[06:23:56] [PASSED] 0x4906 (DG1)
[06:23:56] [PASSED] 0x4907 (DG1)
[06:23:56] [PASSED] 0x4908 (DG1)
[06:23:56] [PASSED] 0x4909 (DG1)
[06:23:56] [PASSED] 0x56C0 (DG2)
[06:23:56] [PASSED] 0x56C2 (DG2)
[06:23:56] [PASSED] 0x56C1 (DG2)
[06:23:56] [PASSED] 0x7D51 (METEORLAKE)
[06:23:56] [PASSED] 0x7DD1 (METEORLAKE)
[06:23:56] [PASSED] 0x7D41 (METEORLAKE)
[06:23:56] [PASSED] 0x7D67 (METEORLAKE)
[06:23:56] [PASSED] 0xB640 (METEORLAKE)
[06:23:56] [PASSED] 0x56A0 (DG2)
[06:23:56] [PASSED] 0x56A1 (DG2)
[06:23:56] [PASSED] 0x56A2 (DG2)
[06:23:56] [PASSED] 0x56BE (DG2)
[06:23:56] [PASSED] 0x56BF (DG2)
[06:23:56] [PASSED] 0x5690 (DG2)
[06:23:56] [PASSED] 0x5691 (DG2)
[06:23:56] [PASSED] 0x5692 (DG2)
[06:23:56] [PASSED] 0x56A5 (DG2)
[06:23:56] [PASSED] 0x56A6 (DG2)
[06:23:56] [PASSED] 0x56B0 (DG2)
[06:23:56] [PASSED] 0x56B1 (DG2)
[06:23:56] [PASSED] 0x56BA (DG2)
[06:23:56] [PASSED] 0x56BB (DG2)
[06:23:56] [PASSED] 0x56BC (DG2)
[06:23:56] [PASSED] 0x56BD (DG2)
[06:23:56] [PASSED] 0x5693 (DG2)
[06:23:56] [PASSED] 0x5694 (DG2)
[06:23:56] [PASSED] 0x5695 (DG2)
[06:23:56] [PASSED] 0x56A3 (DG2)
[06:23:56] [PASSED] 0x56A4 (DG2)
[06:23:56] [PASSED] 0x56B2 (DG2)
[06:23:56] [PASSED] 0x56B3 (DG2)
[06:23:56] [PASSED] 0x5696 (DG2)
[06:23:56] [PASSED] 0x5697 (DG2)
[06:23:56] [PASSED] 0xB69 (PVC)
[06:23:56] [PASSED] 0xB6E (PVC)
[06:23:56] [PASSED] 0xBD4 (PVC)
[06:23:56] [PASSED] 0xBD5 (PVC)
[06:23:56] [PASSED] 0xBD6 (PVC)
[06:23:56] [PASSED] 0xBD7 (PVC)
[06:23:56] [PASSED] 0xBD8 (PVC)
[06:23:56] [PASSED] 0xBD9 (PVC)
[06:23:56] [PASSED] 0xBDA (PVC)
[06:23:56] [PASSED] 0xBDB (PVC)
[06:23:56] [PASSED] 0xBE0 (PVC)
[06:23:56] [PASSED] 0xBE1 (PVC)
[06:23:56] [PASSED] 0xBE5 (PVC)
[06:23:56] [PASSED] 0x7D40 (METEORLAKE)
[06:23:56] [PASSED] 0x7D45 (METEORLAKE)
[06:23:56] [PASSED] 0x7D55 (METEORLAKE)
[06:23:56] [PASSED] 0x7D60 (METEORLAKE)
[06:23:56] [PASSED] 0x7DD5 (METEORLAKE)
[06:23:56] [PASSED] 0x6420 (LUNARLAKE)
[06:23:56] [PASSED] 0x64A0 (LUNARLAKE)
[06:23:56] [PASSED] 0x64B0 (LUNARLAKE)
[06:23:56] [PASSED] 0xE202 (BATTLEMAGE)
[06:23:56] [PASSED] 0xE209 (BATTLEMAGE)
[06:23:56] [PASSED] 0xE20B (BATTLEMAGE)
[06:23:56] [PASSED] 0xE20C (BATTLEMAGE)
[06:23:56] [PASSED] 0xE20D (BATTLEMAGE)
[06:23:56] [PASSED] 0xE210 (BATTLEMAGE)
[06:23:56] [PASSED] 0xE211 (BATTLEMAGE)
[06:23:56] [PASSED] 0xE212 (BATTLEMAGE)
[06:23:56] [PASSED] 0xE216 (BATTLEMAGE)
[06:23:56] [PASSED] 0xE220 (BATTLEMAGE)
[06:23:56] [PASSED] 0xE221 (BATTLEMAGE)
[06:23:56] [PASSED] 0xE222 (BATTLEMAGE)
[06:23:56] [PASSED] 0xE223 (BATTLEMAGE)
[06:23:56] [PASSED] 0xB080 (PANTHERLAKE)
[06:23:56] [PASSED] 0xB081 (PANTHERLAKE)
[06:23:56] [PASSED] 0xB082 (PANTHERLAKE)
[06:23:56] [PASSED] 0xB083 (PANTHERLAKE)
[06:23:56] [PASSED] 0xB084 (PANTHERLAKE)
[06:23:56] [PASSED] 0xB085 (PANTHERLAKE)
[06:23:56] [PASSED] 0xB086 (PANTHERLAKE)
[06:23:56] [PASSED] 0xB087 (PANTHERLAKE)
[06:23:56] [PASSED] 0xB08F (PANTHERLAKE)
[06:23:56] [PASSED] 0xB090 (PANTHERLAKE)
[06:23:56] [PASSED] 0xB0A0 (PANTHERLAKE)
[06:23:56] [PASSED] 0xB0B0 (PANTHERLAKE)
[06:23:56] [PASSED] 0xFD80 (PANTHERLAKE)
[06:23:56] [PASSED] 0xFD81 (PANTHERLAKE)
[06:23:56] [PASSED] 0xD740 (NOVALAKE_S)
[06:23:56] [PASSED] 0xD741 (NOVALAKE_S)
[06:23:56] [PASSED] 0xD742 (NOVALAKE_S)
[06:23:56] [PASSED] 0xD743 (NOVALAKE_S)
[06:23:56] [PASSED] 0xD745 (NOVALAKE_S)
[06:23:56] [PASSED] 0xD74A (NOVALAKE_S)
[06:23:56] [PASSED] 0xD74B (NOVALAKE_S)
[06:23:56] [PASSED] 0x674C (CRESCENTISLAND)
[06:23:56] [PASSED] 0x674D (CRESCENTISLAND)
[06:23:56] [PASSED] 0x674E (CRESCENTISLAND)
[06:23:56] [PASSED] 0x674F (CRESCENTISLAND)
[06:23:56] [PASSED] 0x6750 (CRESCENTISLAND)
[06:23:56] [PASSED] 0xD750 (NOVALAKE_P)
[06:23:56] [PASSED] 0xD751 (NOVALAKE_P)
[06:23:56] [PASSED] 0xD752 (NOVALAKE_P)
[06:23:56] [PASSED] 0xD753 (NOVALAKE_P)
[06:23:56] [PASSED] 0xD754 (NOVALAKE_P)
[06:23:56] [PASSED] 0xD755 (NOVALAKE_P)
[06:23:56] [PASSED] 0xD756 (NOVALAKE_P)
[06:23:56] [PASSED] 0xD757 (NOVALAKE_P)
[06:23:56] [PASSED] 0xD75F (NOVALAKE_P)
[06:23:56] =============== [PASSED] check_platform_desc ===============
[06:23:56] ===================== [PASSED] xe_pci ======================
[06:23:56] ============= xe_rtp_tables_test (5 subtests) ==============
[06:23:56] ================== xe_rtp_table_gt_test  ===================
[06:23:56] [PASSED] gt_was/14011060649
[06:23:56] [PASSED] gt_was/14011059788
[06:23:56] [PASSED] gt_was/14015795083
[06:23:56] [PASSED] gt_was/16021867713
[06:23:56] [PASSED] gt_was/14019449301
[06:23:56] [PASSED] gt_was/16028005424
[06:23:56] [PASSED] gt_was/14026578760
[06:23:56] [PASSED] gt_was/1409420604
[06:23:56] [PASSED] gt_was/1408615072
[06:23:56] [PASSED] gt_was/22010523718
[06:23:56] [PASSED] gt_was/14011006942
[06:23:56] [PASSED] gt_was/14014830051
[06:23:56] [PASSED] gt_was/18018781329
[06:23:56] [PASSED] gt_was/1509235366
[06:23:56] [PASSED] gt_was/18018781329
[06:23:56] [PASSED] gt_was/16016694945
[06:23:56] [PASSED] gt_was/14018575942
[06:23:56] [PASSED] gt_was/22016670082
[06:23:56] [PASSED] gt_was/22016670082
[06:23:56] [PASSED] gt_was/14017421178
[06:23:56] [PASSED] gt_was/16025250150
[06:23:56] [PASSED] gt_was/14021871409
[06:23:56] [PASSED] gt_was/16021865536
[06:23:56] [PASSED] gt_was/14021486841
[06:23:56] [PASSED] gt_was/14025160223
[06:23:56] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[06:23:56] [PASSED] gt_was/14025635424
[06:23:56] [PASSED] gt_was/16028005424
[06:23:56] ============== [PASSED] xe_rtp_table_gt_test ===============
[06:23:56] ================== xe_rtp_table_gt_test  ===================
[06:23:56] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[06:23:56] [PASSED] gt_tunings/Tuning: 32B Access Enable
[06:23:56] [PASSED] gt_tunings/Tuning: L3 cache
[06:23:56] [PASSED] gt_tunings/Tuning: L3 cache - media
[06:23:56] [PASSED] gt_tunings/Tuning: Compression Overfetch
[06:23:56] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[06:23:56] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[06:23:56] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[06:23:56] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[06:23:56] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[06:23:56] [PASSED] gt_tunings/Tuning: Stateless compression control
[06:23:56] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[06:23:56] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[06:23:56] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[06:23:56] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[06:23:56] ============== [PASSED] xe_rtp_table_gt_test ===============
[06:23:56] ================== xe_rtp_table_oob_test  ==================
[06:23:56] [PASSED] oob_was/1607983814
[06:23:56] [PASSED] oob_was/16010904313
[06:23:56] [PASSED] oob_was/18022495364
[06:23:56] [PASSED] oob_was/22012773006
[06:23:56] [PASSED] oob_was/14014475959
[06:23:56] [PASSED] oob_was/22011391025
[06:23:56] [PASSED] oob_was/22012727170
[06:23:56] [PASSED] oob_was/22012727685
[06:23:56] [PASSED] oob_was/22016596838
[06:23:56] [PASSED] oob_was/18020744125
[06:23:56] [PASSED] oob_was/1409600907
[06:23:56] [PASSED] oob_was/22014953428
[06:23:56] [PASSED] oob_was/16017236439
[06:23:56] [PASSED] oob_was/14019821291
[06:23:56] [PASSED] oob_was/14015076503
[06:23:56] [PASSED] oob_was/22016122933
[06:23:56] [PASSED] oob_was/14018913170
[06:23:56] [PASSED] oob_was/14018094691
[06:23:56] [PASSED] oob_was/18024947630
[06:23:56] [PASSED] oob_was/16022287689
[06:23:56] [PASSED] oob_was/13011645652
[06:23:56] [PASSED] oob_was/14022293748
[06:23:56] [PASSED] oob_was/22019794406
[06:23:56] [PASSED] oob_was/22019338487
[06:23:56] [PASSED] oob_was/16023588340
[06:23:56] [PASSED] oob_was/14019789679
[06:23:56] [PASSED] oob_was/14022866841
[06:23:56] [PASSED] oob_was/16021333562
[06:23:56] [PASSED] oob_was/14016712196
[06:23:56] [PASSED] oob_was/14015568240
[06:23:56] [PASSED] oob_was/18013179988
[06:23:56] [PASSED] oob_was/1508761755
[06:23:56] [PASSED] oob_was/16023105232
[06:23:56] [PASSED] oob_was/16026508708
[06:23:56] [PASSED] oob_was/14020001231
[06:23:56] [PASSED] oob_was/16023683509
[06:23:56] [PASSED] oob_was/14025515070
[06:23:56] [PASSED] oob_was/15015404425_disable
[06:23:56] [PASSED] oob_was/16026007364
[06:23:56] [PASSED] oob_was/14020316580
[06:23:56] [PASSED] oob_was/14025883347
[06:23:56] [PASSED] oob_was/16029380221
[06:23:56] [PASSED] oob_was/22022079272
[06:23:56] [PASSED] oob_was/16029897822
[06:23:56] [PASSED] oob_was/14027054324
[06:23:56] ============== [PASSED] xe_rtp_table_oob_test ==============
[06:23:56] ================ xe_rtp_table_dev_oob_test  ================
[06:23:56] [PASSED] device_oob_was/22010954014
[06:23:56] [PASSED] device_oob_was/15015404425
[06:23:56] [PASSED] device_oob_was/22019338487_display
[06:23:56] [PASSED] device_oob_was/14022085890
[06:23:56] [PASSED] device_oob_was/14026539277
[06:23:56] [PASSED] device_oob_was/14026633728
[06:23:56] [PASSED] device_oob_was/14026746987
[06:23:56] [PASSED] device_oob_was/14026779378
[06:23:56] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[06:23:56] ========== xe_rtp_table_missing_upper_bound_test  ==========
[06:23:56] [PASSED] register_whitelist/WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865
[06:23:56] [PASSED] register_whitelist/1508744258, 14012131227, 1808121037
[06:23:56] [PASSED] register_whitelist/1806527549
[06:23:56] [PASSED] register_whitelist/allow_read_ctx_timestamp
[06:23:56] [PASSED] register_whitelist/allow_read_queue_timestamp
[06:23:56] [PASSED] register_whitelist/16014440446
[06:23:56] [PASSED] register_whitelist/16017236439
[06:23:56] [PASSED] register_whitelist/16020183090
[06:23:56] [PASSED] register_whitelist/14024997852
[06:23:56] [PASSED] register_whitelist/14024997852
[06:23:56] ====== [PASSED] xe_rtp_table_missing_upper_bound_test ======
[06:23:56] =============== [PASSED] xe_rtp_tables_test ================
[06:23:56] =================== xe_rtp (3 subtests) ====================
[06:23:56] =================== xe_rtp_rules_tests  ====================
[06:23:56] [PASSED] no
[06:23:56] [PASSED] yes
[06:23:56] [PASSED] no-and-no
[06:23:56] [PASSED] no-and-yes
[06:23:56] [PASSED] yes-and-no
[06:23:56] [PASSED] yes-and-yes
[06:23:56] [PASSED] no-or-no
[06:23:56] [PASSED] no-or-yes
[06:23:56] [PASSED] yes-or-no
[06:23:56] [PASSED] yes-or-yes
[06:23:56] [PASSED] no-yes-or-yes-no
[06:23:56] [PASSED] no-yes-or-yes-yes
[06:23:56] [PASSED] yes-yes-or-no-yes
[06:23:56] [PASSED] yes-yes-or-yes-yes
[06:23:56] [PASSED] no-no-or-yes-or-no
[06:23:56] [PASSED] or
[06:23:56] [PASSED] or-yes
[06:23:56] [PASSED] or-no
[06:23:56] [PASSED] yes-or
[06:23:56] [PASSED] no-or
[06:23:56] [PASSED] no-or-or-yes
[06:23:56] [PASSED] yes-or-or-no
[06:23:56] [PASSED] no-or-or-no
[06:23:56] [PASSED] missing-context-engine-class
[06:23:56] [PASSED] missing-context-engine-class-or-yes
[06:23:56] [PASSED] missing-context-engine-class-or-or-yes
[06:23:56] =============== [PASSED] xe_rtp_rules_tests ================
[06:23:56] =============== xe_rtp_process_to_sr_tests  ================
[06:23:56] [PASSED] coalesce-same-reg
[06:23:56] [PASSED] coalesce-same-reg-literal-and-func
[06:23:56] [PASSED] no-match-no-add
[06:23:56] [PASSED] two-regs-two-entries
[06:23:56] [PASSED] clr-one-set-other
[06:23:56] [PASSED] set-field
[06:23:56] [PASSED] conflict-duplicate
[06:23:56] [PASSED] conflict-not-disjoint
[06:23:56] [PASSED] conflict-not-disjoint-literal-and-func
[06:23:56] [PASSED] conflict-reg-type
[06:23:56] [PASSED] bad-mcr-reg-forced-to-regular
[06:23:56] [PASSED] bad-regular-reg-forced-to-mcr
[06:23:56] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[06:23:56] ================== xe_rtp_process_tests  ===================
[06:23:56] [PASSED] active1
[06:23:56] [PASSED] active2
[06:23:56] [PASSED] active-inactive
[06:23:56] [PASSED] inactive-active
[06:23:56] [PASSED] inactive-active-inactive
[06:23:56] [PASSED] inactive-inactive-inactive
[06:23:56] ============== [PASSED] xe_rtp_process_tests ===============
[06:23:56] ===================== [PASSED] xe_rtp ======================
[06:23:56] ==================== xe_wa (1 subtest) =====================
[06:23:56] ======================== xe_wa_gt  =========================
[06:23:56] [PASSED] TIGERLAKE B0
[06:23:56] [PASSED] DG1 A0
[06:23:56] [PASSED] DG1 B0
[06:23:56] [PASSED] ALDERLAKE_S A0
[06:23:56] [PASSED] ALDERLAKE_S B0
[06:23:56] [PASSED] ALDERLAKE_S C0
[06:23:56] [PASSED] ALDERLAKE_S D0
[06:23:56] [PASSED] ALDERLAKE_P A0
[06:23:56] [PASSED] ALDERLAKE_P B0
[06:23:56] [PASSED] ALDERLAKE_P C0
[06:23:56] [PASSED] ALDERLAKE_S RPLS D0
[06:23:56] [PASSED] ALDERLAKE_P RPLU E0
[06:23:56] [PASSED] DG2 G10 C0
[06:23:56] [PASSED] DG2 G11 B1
[06:23:56] [PASSED] DG2 G12 A1
[06:23:56] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[06:23:56] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[06:23:56] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[06:23:56] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[06:23:56] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[06:23:56] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[06:23:56] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[06:23:56] ==================== [PASSED] xe_wa_gt =====================
[06:23:56] ====================== [PASSED] xe_wa ======================
[06:23:56] ============================================================
[06:23:56] Testing complete. Ran 790 tests: passed: 762, skipped: 28
[06:23:56] Elapsed time: 37.903s total, 4.446s configuring, 32.741s building, 0.695s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[06:23:56] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[06:23:58] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[06:24:23] Starting KUnit Kernel (1/1)...
[06:24:23] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[06:24:23] ============ drm_test_pick_cmdline (2 subtests) ============
[06:24:23] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[06:24:23] =============== drm_test_pick_cmdline_named  ===============
[06:24:23] [PASSED] NTSC
[06:24:23] [PASSED] NTSC-J
[06:24:23] [PASSED] PAL
[06:24:23] [PASSED] PAL-M
[06:24:23] =========== [PASSED] drm_test_pick_cmdline_named ===========
[06:24:23] ============== [PASSED] drm_test_pick_cmdline ==============
[06:24:23] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[06:24:23] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[06:24:23] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[06:24:23] =========== drm_validate_clone_mode (2 subtests) ===========
[06:24:23] ============== drm_test_check_in_clone_mode  ===============
[06:24:23] [PASSED] in_clone_mode
[06:24:23] [PASSED] not_in_clone_mode
[06:24:23] ========== [PASSED] drm_test_check_in_clone_mode ===========
[06:24:23] =============== drm_test_check_valid_clones  ===============
[06:24:23] [PASSED] not_in_clone_mode
[06:24:23] [PASSED] valid_clone
[06:24:23] [PASSED] invalid_clone
[06:24:23] =========== [PASSED] drm_test_check_valid_clones ===========
[06:24:23] ============= [PASSED] drm_validate_clone_mode =============
[06:24:23] ============= drm_validate_modeset (1 subtest) =============
[06:24:23] [PASSED] drm_test_check_connector_changed_modeset
[06:24:23] ============== [PASSED] drm_validate_modeset ===============
[06:24:23] ====== drm_test_bridge_get_current_state (1 subtest) =======
[06:24:23] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[06:24:23] ======== [PASSED] drm_test_bridge_get_current_state ========
[06:24:23] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[06:24:23] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[06:24:23] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[06:24:23] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[06:24:23] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[06:24:23] ============== drm_bridge_alloc (2 subtests) ===============
[06:24:23] [PASSED] drm_test_drm_bridge_alloc_basic
[06:24:23] [PASSED] drm_test_drm_bridge_alloc_get_put
[06:24:23] ================ [PASSED] drm_bridge_alloc =================
[06:24:23] ============= drm_bridge_bus_fmt (5 subtests) ==============
[06:24:23] [PASSED] drm_test_bridge_rgb_yuv_rgb
[06:24:23] [PASSED] drm_test_bridge_must_convert_to_yuv444
[06:24:23] [PASSED] drm_test_bridge_hdmi_auto_rgb
[06:24:23] [PASSED] drm_test_bridge_auto_first
[06:24:23] [PASSED] drm_test_bridge_rgb_yuv_no_path
[06:24:23] =============== [PASSED] drm_bridge_bus_fmt ================
[06:24:23] ============= drm_cmdline_parser (40 subtests) =============
[06:24:23] [PASSED] drm_test_cmdline_force_d_only
[06:24:23] [PASSED] drm_test_cmdline_force_D_only_dvi
[06:24:23] [PASSED] drm_test_cmdline_force_D_only_hdmi
[06:24:23] [PASSED] drm_test_cmdline_force_D_only_not_digital
[06:24:23] [PASSED] drm_test_cmdline_force_e_only
[06:24:23] [PASSED] drm_test_cmdline_res
[06:24:23] [PASSED] drm_test_cmdline_res_vesa
[06:24:23] [PASSED] drm_test_cmdline_res_vesa_rblank
[06:24:23] [PASSED] drm_test_cmdline_res_rblank
[06:24:23] [PASSED] drm_test_cmdline_res_bpp
[06:24:23] [PASSED] drm_test_cmdline_res_refresh
[06:24:23] [PASSED] drm_test_cmdline_res_bpp_refresh
[06:24:23] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[06:24:23] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[06:24:23] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[06:24:23] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[06:24:23] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[06:24:23] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[06:24:23] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[06:24:23] [PASSED] drm_test_cmdline_res_margins_force_on
[06:24:23] [PASSED] drm_test_cmdline_res_vesa_margins
[06:24:23] [PASSED] drm_test_cmdline_name
[06:24:23] [PASSED] drm_test_cmdline_name_bpp
[06:24:23] [PASSED] drm_test_cmdline_name_option
[06:24:23] [PASSED] drm_test_cmdline_name_bpp_option
[06:24:23] [PASSED] drm_test_cmdline_rotate_0
[06:24:23] [PASSED] drm_test_cmdline_rotate_90
[06:24:23] [PASSED] drm_test_cmdline_rotate_180
[06:24:23] [PASSED] drm_test_cmdline_rotate_270
[06:24:23] [PASSED] drm_test_cmdline_hmirror
[06:24:23] [PASSED] drm_test_cmdline_vmirror
[06:24:23] [PASSED] drm_test_cmdline_margin_options
[06:24:23] [PASSED] drm_test_cmdline_multiple_options
[06:24:23] [PASSED] drm_test_cmdline_bpp_extra_and_option
[06:24:23] [PASSED] drm_test_cmdline_extra_and_option
[06:24:23] [PASSED] drm_test_cmdline_freestanding_options
[06:24:23] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[06:24:23] [PASSED] drm_test_cmdline_panel_orientation
[06:24:23] ================ drm_test_cmdline_invalid  =================
[06:24:23] [PASSED] margin_only
[06:24:23] [PASSED] interlace_only
[06:24:23] [PASSED] res_missing_x
[06:24:23] [PASSED] res_missing_y
[06:24:23] [PASSED] res_bad_y
[06:24:23] [PASSED] res_missing_y_bpp
[06:24:23] [PASSED] res_bad_bpp
[06:24:23] [PASSED] res_bad_refresh
[06:24:23] [PASSED] res_bpp_refresh_force_on_off
[06:24:23] [PASSED] res_invalid_mode
[06:24:23] [PASSED] res_bpp_wrong_place_mode
[06:24:23] [PASSED] name_bpp_refresh
[06:24:23] [PASSED] name_refresh
[06:24:23] [PASSED] name_refresh_wrong_mode
[06:24:23] [PASSED] name_refresh_invalid_mode
[06:24:23] [PASSED] rotate_multiple
[06:24:23] [PASSED] rotate_invalid_val
[06:24:23] [PASSED] rotate_truncated
[06:24:23] [PASSED] invalid_option
[06:24:23] [PASSED] invalid_tv_option
[06:24:23] [PASSED] truncated_tv_option
[06:24:23] ============ [PASSED] drm_test_cmdline_invalid =============
[06:24:23] =============== drm_test_cmdline_tv_options  ===============
[06:24:23] [PASSED] NTSC
[06:24:23] [PASSED] NTSC_443
[06:24:23] [PASSED] NTSC_J
[06:24:23] [PASSED] PAL
[06:24:23] [PASSED] PAL_M
[06:24:23] [PASSED] PAL_N
[06:24:23] [PASSED] SECAM
[06:24:23] [PASSED] MONO_525
[06:24:23] [PASSED] MONO_625
[06:24:23] =========== [PASSED] drm_test_cmdline_tv_options ===========
[06:24:23] =============== [PASSED] drm_cmdline_parser ================
[06:24:23] ========== drmm_connector_hdmi_init (20 subtests) ==========
[06:24:23] [PASSED] drm_test_connector_hdmi_init_valid
[06:24:23] [PASSED] drm_test_connector_hdmi_init_bpc_8
[06:24:23] [PASSED] drm_test_connector_hdmi_init_bpc_10
[06:24:23] [PASSED] drm_test_connector_hdmi_init_bpc_12
[06:24:23] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[06:24:23] [PASSED] drm_test_connector_hdmi_init_bpc_null
[06:24:23] [PASSED] drm_test_connector_hdmi_init_formats_empty
[06:24:23] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[06:24:23] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[06:24:23] [PASSED] supported_formats=0x9 yuv420_allowed=1
[06:24:23] [PASSED] supported_formats=0x9 yuv420_allowed=0
[06:24:23] [PASSED] supported_formats=0x5 yuv420_allowed=1
[06:24:23] [PASSED] supported_formats=0x5 yuv420_allowed=0
[06:24:23] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[06:24:23] [PASSED] drm_test_connector_hdmi_init_null_ddc
[06:24:23] [PASSED] drm_test_connector_hdmi_init_null_product
[06:24:23] [PASSED] drm_test_connector_hdmi_init_null_vendor
[06:24:23] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[06:24:23] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[06:24:23] [PASSED] drm_test_connector_hdmi_init_product_valid
[06:24:23] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[06:24:23] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[06:24:23] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[06:24:23] ========= drm_test_connector_hdmi_init_type_valid  =========
[06:24:23] [PASSED] HDMI-A
[06:24:23] [PASSED] HDMI-B
[06:24:23] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[06:24:23] ======== drm_test_connector_hdmi_init_type_invalid  ========
[06:24:23] [PASSED] Unknown
[06:24:23] [PASSED] VGA
[06:24:23] [PASSED] DVI-I
[06:24:23] [PASSED] DVI-D
[06:24:23] [PASSED] DVI-A
[06:24:23] [PASSED] Composite
[06:24:23] [PASSED] SVIDEO
[06:24:23] [PASSED] LVDS
[06:24:23] [PASSED] Component
[06:24:23] [PASSED] DIN
[06:24:23] [PASSED] DP
[06:24:23] [PASSED] TV
[06:24:23] [PASSED] eDP
[06:24:23] [PASSED] Virtual
[06:24:23] [PASSED] DSI
[06:24:23] [PASSED] DPI
[06:24:23] [PASSED] Writeback
[06:24:23] [PASSED] SPI
[06:24:23] [PASSED] USB
[06:24:23] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[06:24:23] ============ [PASSED] drmm_connector_hdmi_init =============
[06:24:23] ============= drmm_connector_init (3 subtests) =============
[06:24:23] [PASSED] drm_test_drmm_connector_init
[06:24:23] [PASSED] drm_test_drmm_connector_init_null_ddc
[06:24:23] ========= drm_test_drmm_connector_init_type_valid  =========
[06:24:23] [PASSED] Unknown
[06:24:23] [PASSED] VGA
[06:24:23] [PASSED] DVI-I
[06:24:23] [PASSED] DVI-D
[06:24:23] [PASSED] DVI-A
[06:24:23] [PASSED] Composite
[06:24:23] [PASSED] SVIDEO
[06:24:23] [PASSED] LVDS
[06:24:23] [PASSED] Component
[06:24:23] [PASSED] DIN
[06:24:23] [PASSED] DP
[06:24:23] [PASSED] HDMI-A
[06:24:23] [PASSED] HDMI-B
[06:24:23] [PASSED] TV
[06:24:23] [PASSED] eDP
[06:24:23] [PASSED] Virtual
[06:24:23] [PASSED] DSI
[06:24:23] [PASSED] DPI
[06:24:23] [PASSED] Writeback
[06:24:23] [PASSED] SPI
[06:24:23] [PASSED] USB
[06:24:23] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[06:24:23] =============== [PASSED] drmm_connector_init ===============
[06:24:23] ========= drm_connector_dynamic_init (6 subtests) ==========
[06:24:23] [PASSED] drm_test_drm_connector_dynamic_init
[06:24:23] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[06:24:23] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[06:24:23] [PASSED] drm_test_drm_connector_dynamic_init_properties
[06:24:23] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[06:24:23] [PASSED] Unknown
[06:24:23] [PASSED] VGA
[06:24:23] [PASSED] DVI-I
[06:24:23] [PASSED] DVI-D
[06:24:23] [PASSED] DVI-A
[06:24:23] [PASSED] Composite
[06:24:23] [PASSED] SVIDEO
[06:24:23] [PASSED] LVDS
[06:24:23] [PASSED] Component
[06:24:23] [PASSED] DIN
[06:24:23] [PASSED] DP
[06:24:23] [PASSED] HDMI-A
[06:24:23] [PASSED] HDMI-B
[06:24:23] [PASSED] TV
[06:24:23] [PASSED] eDP
[06:24:23] [PASSED] Virtual
[06:24:23] [PASSED] DSI
[06:24:23] [PASSED] DPI
[06:24:23] [PASSED] Writeback
[06:24:23] [PASSED] SPI
[06:24:23] [PASSED] USB
[06:24:23] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[06:24:23] ======== drm_test_drm_connector_dynamic_init_name  =========
[06:24:23] [PASSED] Unknown
[06:24:23] [PASSED] VGA
[06:24:23] [PASSED] DVI-I
[06:24:23] [PASSED] DVI-D
[06:24:23] [PASSED] DVI-A
[06:24:23] [PASSED] Composite
[06:24:23] [PASSED] SVIDEO
[06:24:23] [PASSED] LVDS
[06:24:23] [PASSED] Component
[06:24:23] [PASSED] DIN
[06:24:23] [PASSED] DP
[06:24:23] [PASSED] HDMI-A
[06:24:23] [PASSED] HDMI-B
[06:24:23] [PASSED] TV
[06:24:23] [PASSED] eDP
[06:24:23] [PASSED] Virtual
[06:24:23] [PASSED] DSI
[06:24:23] [PASSED] DPI
[06:24:23] [PASSED] Writeback
[06:24:23] [PASSED] SPI
[06:24:23] [PASSED] USB
[06:24:23] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[06:24:23] =========== [PASSED] drm_connector_dynamic_init ============
[06:24:23] ==== drm_connector_dynamic_register_early (4 subtests) =====
[06:24:23] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[06:24:23] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[06:24:23] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[06:24:23] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[06:24:23] ====== [PASSED] drm_connector_dynamic_register_early =======
[06:24:23] ======= drm_connector_dynamic_register (7 subtests) ========
[06:24:23] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[06:24:23] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[06:24:23] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[06:24:23] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[06:24:23] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[06:24:23] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[06:24:23] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[06:24:23] ========= [PASSED] drm_connector_dynamic_register ==========
[06:24:23] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[06:24:23] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[06:24:23] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[06:24:23] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[06:24:23] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[06:24:23] ========== drm_test_get_tv_mode_from_name_valid  ===========
[06:24:23] [PASSED] NTSC
[06:24:23] [PASSED] NTSC-443
[06:24:23] [PASSED] NTSC-J
[06:24:23] [PASSED] PAL
[06:24:23] [PASSED] PAL-M
[06:24:23] [PASSED] PAL-N
[06:24:23] [PASSED] SECAM
[06:24:23] [PASSED] Mono
[06:24:23] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[06:24:23] [PASSED] drm_test_get_tv_mode_from_name_truncated
[06:24:23] ============ [PASSED] drm_get_tv_mode_from_name ============
[06:24:23] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[06:24:23] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[06:24:23] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[06:24:23] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[06:24:23] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[06:24:23] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[06:24:23] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[06:24:23] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[06:24:23] [PASSED] VIC 96
[06:24:23] [PASSED] VIC 97
[06:24:23] [PASSED] VIC 101
[06:24:23] [PASSED] VIC 102
[06:24:23] [PASSED] VIC 106
[06:24:23] [PASSED] VIC 107
[06:24:23] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[06:24:23] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[06:24:23] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[06:24:23] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[06:24:23] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[06:24:23] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[06:24:23] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[06:24:23] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[06:24:23] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[06:24:23] [PASSED] Automatic
[06:24:23] [PASSED] Full
[06:24:23] [PASSED] Limited 16:235
[06:24:23] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[06:24:23] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[06:24:23] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[06:24:23] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[06:24:23] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[06:24:23] [PASSED] RGB
[06:24:23] [PASSED] YUV 4:2:0
[06:24:23] [PASSED] YUV 4:2:2
[06:24:23] [PASSED] YUV 4:4:4
[06:24:23] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[06:24:23] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[06:24:23] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[06:24:23] ============= drm_damage_helper (21 subtests) ==============
[06:24:23] [PASSED] drm_test_damage_iter_no_damage
[06:24:23] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[06:24:23] [PASSED] drm_test_damage_iter_no_damage_src_moved
[06:24:23] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[06:24:23] [PASSED] drm_test_damage_iter_no_damage_not_visible
[06:24:23] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[06:24:23] [PASSED] drm_test_damage_iter_no_damage_no_fb
[06:24:23] [PASSED] drm_test_damage_iter_simple_damage
[06:24:23] [PASSED] drm_test_damage_iter_single_damage
[06:24:23] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[06:24:23] [PASSED] drm_test_damage_iter_single_damage_outside_src
[06:24:23] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[06:24:23] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[06:24:23] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[06:24:23] [PASSED] drm_test_damage_iter_single_damage_src_moved
[06:24:23] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[06:24:23] [PASSED] drm_test_damage_iter_damage
[06:24:23] [PASSED] drm_test_damage_iter_damage_one_intersect
[06:24:23] [PASSED] drm_test_damage_iter_damage_one_outside
[06:24:23] [PASSED] drm_test_damage_iter_damage_src_moved
[06:24:23] [PASSED] drm_test_damage_iter_damage_not_visible
[06:24:23] ================ [PASSED] drm_damage_helper ================
[06:24:23] ============== drm_dp_mst_helper (3 subtests) ==============
[06:24:23] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[06:24:23] [PASSED] Clock 154000 BPP 30 DSC disabled
[06:24:23] [PASSED] Clock 234000 BPP 30 DSC disabled
[06:24:23] [PASSED] Clock 297000 BPP 24 DSC disabled
[06:24:23] [PASSED] Clock 332880 BPP 24 DSC enabled
[06:24:23] [PASSED] Clock 324540 BPP 24 DSC enabled
[06:24:23] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[06:24:23] ============== drm_test_dp_mst_calc_pbn_div  ===============
[06:24:23] [PASSED] Link rate 2000000 lane count 4
[06:24:23] [PASSED] Link rate 2000000 lane count 2
[06:24:23] [PASSED] Link rate 2000000 lane count 1
[06:24:23] [PASSED] Link rate 1350000 lane count 4
[06:24:23] [PASSED] Link rate 1350000 lane count 2
[06:24:23] [PASSED] Link rate 1350000 lane count 1
[06:24:23] [PASSED] Link rate 1000000 lane count 4
[06:24:23] [PASSED] Link rate 1000000 lane count 2
[06:24:23] [PASSED] Link rate 1000000 lane count 1
[06:24:23] [PASSED] Link rate 810000 lane count 4
[06:24:23] [PASSED] Link rate 810000 lane count 2
[06:24:23] [PASSED] Link rate 810000 lane count 1
[06:24:23] [PASSED] Link rate 540000 lane count 4
[06:24:23] [PASSED] Link rate 540000 lane count 2
[06:24:23] [PASSED] Link rate 540000 lane count 1
[06:24:23] [PASSED] Link rate 270000 lane count 4
[06:24:23] [PASSED] Link rate 270000 lane count 2
[06:24:23] [PASSED] Link rate 270000 lane count 1
[06:24:23] [PASSED] Link rate 162000 lane count 4
[06:24:23] [PASSED] Link rate 162000 lane count 2
[06:24:23] [PASSED] Link rate 162000 lane count 1
[06:24:23] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[06:24:23] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[06:24:23] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[06:24:23] [PASSED] DP_POWER_UP_PHY with port number
[06:24:23] [PASSED] DP_POWER_DOWN_PHY with port number
[06:24:23] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[06:24:23] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[06:24:23] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[06:24:23] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[06:24:23] [PASSED] DP_QUERY_PAYLOAD with port number
[06:24:23] [PASSED] DP_QUERY_PAYLOAD with VCPI
[06:24:23] [PASSED] DP_REMOTE_DPCD_READ with port number
[06:24:23] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[06:24:23] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[06:24:23] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[06:24:23] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[06:24:23] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[06:24:23] [PASSED] DP_REMOTE_I2C_READ with port number
[06:24:23] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[06:24:23] [PASSED] DP_REMOTE_I2C_READ with transactions array
[06:24:23] [PASSED] DP_REMOTE_I2C_WRITE with port number
[06:24:23] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[06:24:23] [PASSED] DP_REMOTE_I2C_WRITE with data array
[06:24:23] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[06:24:23] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[06:24:23] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[06:24:23] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[06:24:23] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[06:24:23] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[06:24:23] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[06:24:23] ================ [PASSED] drm_dp_mst_helper ================
[06:24:23] ================== drm_exec (7 subtests) ===================
[06:24:23] [PASSED] sanitycheck
[06:24:23] [PASSED] test_lock
[06:24:23] [PASSED] test_lock_unlock
[06:24:23] [PASSED] test_duplicates
[06:24:23] [PASSED] test_prepare
[06:24:23] [PASSED] test_prepare_array
[06:24:23] [PASSED] test_multiple_loops
[06:24:23] ==================== [PASSED] drm_exec =====================
[06:24:23] =========== drm_format_helper_test (17 subtests) ===========
[06:24:23] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[06:24:23] [PASSED] single_pixel_source_buffer
[06:24:23] [PASSED] single_pixel_clip_rectangle
[06:24:23] [PASSED] well_known_colors
[06:24:23] [PASSED] destination_pitch
[06:24:23] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[06:24:23] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[06:24:23] [PASSED] single_pixel_source_buffer
[06:24:23] [PASSED] single_pixel_clip_rectangle
[06:24:23] [PASSED] well_known_colors
[06:24:23] [PASSED] destination_pitch
[06:24:23] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[06:24:23] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[06:24:23] [PASSED] single_pixel_source_buffer
[06:24:23] [PASSED] single_pixel_clip_rectangle
[06:24:23] [PASSED] well_known_colors
[06:24:23] [PASSED] destination_pitch
[06:24:23] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[06:24:23] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[06:24:23] [PASSED] single_pixel_source_buffer
[06:24:23] [PASSED] single_pixel_clip_rectangle
[06:24:23] [PASSED] well_known_colors
[06:24:23] [PASSED] destination_pitch
[06:24:23] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[06:24:23] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[06:24:23] [PASSED] single_pixel_source_buffer
[06:24:23] [PASSED] single_pixel_clip_rectangle
[06:24:23] [PASSED] well_known_colors
[06:24:23] [PASSED] destination_pitch
[06:24:23] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[06:24:23] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[06:24:23] [PASSED] single_pixel_source_buffer
[06:24:23] [PASSED] single_pixel_clip_rectangle
[06:24:23] [PASSED] well_known_colors
[06:24:23] [PASSED] destination_pitch
[06:24:23] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[06:24:23] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[06:24:23] [PASSED] single_pixel_source_buffer
[06:24:23] [PASSED] single_pixel_clip_rectangle
[06:24:23] [PASSED] well_known_colors
[06:24:23] [PASSED] destination_pitch
[06:24:23] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[06:24:23] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[06:24:23] [PASSED] single_pixel_source_buffer
[06:24:23] [PASSED] single_pixel_clip_rectangle
[06:24:23] [PASSED] well_known_colors
[06:24:23] [PASSED] destination_pitch
[06:24:23] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[06:24:23] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[06:24:23] [PASSED] single_pixel_source_buffer
[06:24:23] [PASSED] single_pixel_clip_rectangle
[06:24:23] [PASSED] well_known_colors
[06:24:23] [PASSED] destination_pitch
[06:24:23] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[06:24:23] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[06:24:23] [PASSED] single_pixel_source_buffer
[06:24:23] [PASSED] single_pixel_clip_rectangle
[06:24:23] [PASSED] well_known_colors
[06:24:23] [PASSED] destination_pitch
[06:24:23] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[06:24:23] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[06:24:23] [PASSED] single_pixel_source_buffer
[06:24:23] [PASSED] single_pixel_clip_rectangle
[06:24:23] [PASSED] well_known_colors
[06:24:23] [PASSED] destination_pitch
[06:24:23] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[06:24:23] ============== drm_test_fb_xrgb8888_to_mono  ===============
[06:24:23] [PASSED] single_pixel_source_buffer
[06:24:23] [PASSED] single_pixel_clip_rectangle
[06:24:23] [PASSED] well_known_colors
[06:24:23] [PASSED] destination_pitch
[06:24:23] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[06:24:23] ==================== drm_test_fb_swab  =====================
[06:24:23] [PASSED] single_pixel_source_buffer
[06:24:23] [PASSED] single_pixel_clip_rectangle
[06:24:23] [PASSED] well_known_colors
[06:24:23] [PASSED] destination_pitch
[06:24:23] ================ [PASSED] drm_test_fb_swab =================
[06:24:23] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[06:24:23] [PASSED] single_pixel_source_buffer
[06:24:23] [PASSED] single_pixel_clip_rectangle
[06:24:23] [PASSED] well_known_colors
[06:24:23] [PASSED] destination_pitch
[06:24:23] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[06:24:23] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[06:24:23] [PASSED] single_pixel_source_buffer
[06:24:23] [PASSED] single_pixel_clip_rectangle
[06:24:23] [PASSED] well_known_colors
[06:24:23] [PASSED] destination_pitch
[06:24:23] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[06:24:23] ================= drm_test_fb_clip_offset  =================
[06:24:23] [PASSED] pass through
[06:24:23] [PASSED] horizontal offset
[06:24:23] [PASSED] vertical offset
[06:24:23] [PASSED] horizontal and vertical offset
[06:24:23] [PASSED] horizontal offset (custom pitch)
[06:24:23] [PASSED] vertical offset (custom pitch)
[06:24:23] [PASSED] horizontal and vertical offset (custom pitch)
[06:24:23] ============= [PASSED] drm_test_fb_clip_offset =============
[06:24:23] =================== drm_test_fb_memcpy  ====================
[06:24:23] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[06:24:23] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[06:24:23] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[06:24:23] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[06:24:23] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[06:24:23] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[06:24:23] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[06:24:23] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[06:24:23] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[06:24:23] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[06:24:23] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[06:24:23] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[06:24:23] =============== [PASSED] drm_test_fb_memcpy ================
[06:24:23] ============= [PASSED] drm_format_helper_test ==============
[06:24:23] ================= drm_format (18 subtests) =================
[06:24:23] [PASSED] drm_test_format_block_width_invalid
[06:24:23] [PASSED] drm_test_format_block_width_one_plane
[06:24:23] [PASSED] drm_test_format_block_width_two_plane
[06:24:23] [PASSED] drm_test_format_block_width_three_plane
[06:24:23] [PASSED] drm_test_format_block_width_tiled
[06:24:23] [PASSED] drm_test_format_block_height_invalid
[06:24:23] [PASSED] drm_test_format_block_height_one_plane
[06:24:23] [PASSED] drm_test_format_block_height_two_plane
[06:24:23] [PASSED] drm_test_format_block_height_three_plane
[06:24:23] [PASSED] drm_test_format_block_height_tiled
[06:24:23] [PASSED] drm_test_format_min_pitch_invalid
[06:24:23] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[06:24:23] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[06:24:23] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[06:24:23] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[06:24:23] [PASSED] drm_test_format_min_pitch_two_plane
[06:24:23] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[06:24:23] [PASSED] drm_test_format_min_pitch_tiled
[06:24:23] =================== [PASSED] drm_format ====================
[06:24:23] ============== drm_framebuffer (10 subtests) ===============
[06:24:23] ========== drm_test_framebuffer_check_src_coords  ==========
[06:24:23] [PASSED] Success: source fits into fb
[06:24:23] [PASSED] Fail: overflowing fb with x-axis coordinate
[06:24:23] [PASSED] Fail: overflowing fb with y-axis coordinate
[06:24:23] [PASSED] Fail: overflowing fb with source width
[06:24:23] [PASSED] Fail: overflowing fb with source height
[06:24:23] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[06:24:23] [PASSED] drm_test_framebuffer_cleanup
[06:24:23] =============== drm_test_framebuffer_create  ===============
[06:24:23] [PASSED] ABGR8888 normal sizes
[06:24:23] [PASSED] ABGR8888 max sizes
[06:24:23] [PASSED] ABGR8888 pitch greater than min required
[06:24:23] [PASSED] ABGR8888 pitch less than min required
[06:24:23] [PASSED] ABGR8888 Invalid width
[06:24:23] [PASSED] ABGR8888 Invalid buffer handle
[06:24:23] [PASSED] No pixel format
[06:24:23] [PASSED] ABGR8888 Width 0
[06:24:23] [PASSED] ABGR8888 Height 0
[06:24:23] [PASSED] ABGR8888 Out of bound height * pitch combination
[06:24:23] [PASSED] ABGR8888 Large buffer offset
[06:24:23] [PASSED] ABGR8888 Buffer offset for inexistent plane
[06:24:23] [PASSED] ABGR8888 Invalid flag
[06:24:23] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[06:24:23] [PASSED] ABGR8888 Valid buffer modifier
[06:24:23] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[06:24:23] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[06:24:23] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[06:24:23] [PASSED] NV12 Normal sizes
[06:24:23] [PASSED] NV12 Max sizes
[06:24:23] [PASSED] NV12 Invalid pitch
[06:24:23] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[06:24:23] [PASSED] NV12 different  modifier per-plane
[06:24:23] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[06:24:23] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[06:24:23] [PASSED] NV12 Modifier for inexistent plane
[06:24:23] [PASSED] NV12 Handle for inexistent plane
[06:24:23] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[06:24:23] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[06:24:23] [PASSED] YVU420 Normal sizes
[06:24:23] [PASSED] YVU420 Max sizes
[06:24:23] [PASSED] YVU420 Invalid pitch
[06:24:23] [PASSED] YVU420 Different pitches
[06:24:23] [PASSED] YVU420 Different buffer offsets/pitches
[06:24:23] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[06:24:23] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[06:24:23] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[06:24:23] [PASSED] YVU420 Valid modifier
[06:24:23] [PASSED] YVU420 Different modifiers per plane
[06:24:23] [PASSED] YVU420 Modifier for inexistent plane
[06:24:23] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[06:24:23] [PASSED] X0L2 Normal sizes
[06:24:23] [PASSED] X0L2 Max sizes
[06:24:23] [PASSED] X0L2 Invalid pitch
[06:24:23] [PASSED] X0L2 Pitch greater than minimum required
[06:24:23] [PASSED] X0L2 Handle for inexistent plane
[06:24:23] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[06:24:23] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[06:24:23] [PASSED] X0L2 Valid modifier
[06:24:23] [PASSED] X0L2 Modifier for inexistent plane
[06:24:23] =========== [PASSED] drm_test_framebuffer_create ===========
[06:24:23] [PASSED] drm_test_framebuffer_free
[06:24:23] [PASSED] drm_test_framebuffer_init
[06:24:23] [PASSED] drm_test_framebuffer_init_bad_format
[06:24:23] [PASSED] drm_test_framebuffer_init_dev_mismatch
[06:24:23] [PASSED] drm_test_framebuffer_lookup
[06:24:23] [PASSED] drm_test_framebuffer_lookup_inexistent
[06:24:23] [PASSED] drm_test_framebuffer_modifiers_not_supported
[06:24:23] ================= [PASSED] drm_framebuffer =================
[06:24:23] ================ drm_gem_shmem (8 subtests) ================
[06:24:23] [PASSED] drm_gem_shmem_test_obj_create
[06:24:23] [PASSED] drm_gem_shmem_test_obj_create_private
[06:24:23] [PASSED] drm_gem_shmem_test_pin_pages
[06:24:23] [PASSED] drm_gem_shmem_test_vmap
[06:24:23] [PASSED] drm_gem_shmem_test_get_sg_table
[06:24:23] [PASSED] drm_gem_shmem_test_get_pages_sgt
[06:24:23] [PASSED] drm_gem_shmem_test_madvise
[06:24:23] [PASSED] drm_gem_shmem_test_purge
[06:24:23] ================== [PASSED] drm_gem_shmem ==================
[06:24:23] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[06:24:23] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[06:24:23] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[06:24:23] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[06:24:23] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[06:24:23] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[06:24:23] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[06:24:23] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[06:24:23] [PASSED] Automatic
[06:24:23] [PASSED] Full
[06:24:23] [PASSED] Limited 16:235
[06:24:23] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[06:24:23] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[06:24:23] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[06:24:23] [PASSED] drm_test_check_disable_connector
[06:24:23] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[06:24:23] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[06:24:23] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[06:24:23] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[06:24:23] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[06:24:23] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[06:24:23] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[06:24:23] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[06:24:23] [PASSED] drm_test_check_output_bpc_dvi
[06:24:23] [PASSED] drm_test_check_output_bpc_format_vic_1
[06:24:23] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[06:24:23] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[06:24:23] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[06:24:23] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[06:24:23] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[06:24:23] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[06:24:23] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[06:24:23] ============ drm_test_check_hdmi_color_format  =============
[06:24:23] [PASSED] AUTO -> RGB
[06:24:23] [PASSED] YCBCR422 -> YUV422
[06:24:23] [PASSED] YCBCR420 -> YUV420
[06:24:23] [PASSED] YCBCR444 -> YUV444
[06:24:23] [PASSED] RGB -> RGB
[06:24:23] ======== [PASSED] drm_test_check_hdmi_color_format =========
[06:24:23] ======== drm_test_check_hdmi_color_format_420_only  ========
[06:24:23] [PASSED] RGB should fail
[06:24:23] [PASSED] YUV444 should fail
[06:24:23] [PASSED] YUV422 should fail
[06:24:23] [PASSED] YUV420 should work
[06:24:23] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[06:24:23] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[06:24:23] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[06:24:23] [PASSED] drm_test_check_broadcast_rgb_value
[06:24:23] [PASSED] drm_test_check_bpc_8_value
[06:24:23] [PASSED] drm_test_check_bpc_10_value
[06:24:23] [PASSED] drm_test_check_bpc_12_value
[06:24:23] [PASSED] drm_test_check_format_value
[06:24:23] [PASSED] drm_test_check_tmds_char_value
[06:24:23] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[06:24:23] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[06:24:23] [PASSED] drm_test_check_mode_valid
[06:24:23] [PASSED] drm_test_check_mode_valid_reject
[06:24:23] [PASSED] drm_test_check_mode_valid_reject_rate
[06:24:23] [PASSED] drm_test_check_mode_valid_reject_max_clock
[06:24:23] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[06:24:23] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[06:24:23] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[06:24:23] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[06:24:23] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[06:24:23] [PASSED] drm_test_check_infoframes
[06:24:23] [PASSED] drm_test_check_reject_avi_infoframe
[06:24:23] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[06:24:23] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[06:24:23] [PASSED] drm_test_check_reject_audio_infoframe
[06:24:23] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[06:24:23] ================= drm_managed (2 subtests) =================
[06:24:23] [PASSED] drm_test_managed_release_action
[06:24:23] [PASSED] drm_test_managed_run_action
[06:24:23] =================== [PASSED] drm_managed ===================
[06:24:23] =================== drm_mm (6 subtests) ====================
[06:24:23] [PASSED] drm_test_mm_init
[06:24:23] [PASSED] drm_test_mm_debug
[06:24:23] [PASSED] drm_test_mm_align32
[06:24:23] [PASSED] drm_test_mm_align64
[06:24:23] [PASSED] drm_test_mm_lowest
[06:24:23] [PASSED] drm_test_mm_highest
[06:24:23] ===================== [PASSED] drm_mm ======================
[06:24:23] ============= drm_modes_analog_tv (5 subtests) =============
[06:24:23] [PASSED] drm_test_modes_analog_tv_mono_576i
[06:24:23] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[06:24:23] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[06:24:23] [PASSED] drm_test_modes_analog_tv_pal_576i
[06:24:23] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[06:24:23] =============== [PASSED] drm_modes_analog_tv ===============
[06:24:23] ============== drm_plane_helper (2 subtests) ===============
[06:24:23] =============== drm_test_check_plane_state  ================
[06:24:23] [PASSED] clipping_simple
[06:24:23] [PASSED] clipping_rotate_reflect
[06:24:23] [PASSED] positioning_simple
[06:24:23] [PASSED] upscaling
[06:24:23] [PASSED] downscaling
[06:24:23] [PASSED] rounding1
[06:24:23] [PASSED] rounding2
[06:24:23] [PASSED] rounding3
[06:24:23] [PASSED] rounding4
[06:24:23] =========== [PASSED] drm_test_check_plane_state ============
[06:24:23] =========== drm_test_check_invalid_plane_state  ============
[06:24:23] [PASSED] positioning_invalid
[06:24:23] [PASSED] upscaling_invalid
[06:24:23] [PASSED] downscaling_invalid
[06:24:23] ======= [PASSED] drm_test_check_invalid_plane_state ========
[06:24:23] ================ [PASSED] drm_plane_helper =================
[06:24:23] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[06:24:23] ====== drm_test_connector_helper_tv_get_modes_check  =======
[06:24:23] [PASSED] None
[06:24:23] [PASSED] PAL
[06:24:23] [PASSED] NTSC
[06:24:23] [PASSED] Both, NTSC Default
[06:24:23] [PASSED] Both, PAL Default
[06:24:23] [PASSED] Both, NTSC Default, with PAL on command-line
[06:24:23] [PASSED] Both, PAL Default, with NTSC on command-line
[06:24:23] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[06:24:23] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[06:24:23] ================== drm_rect (9 subtests) ===================
[06:24:23] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[06:24:23] [PASSED] drm_test_rect_clip_scaled_not_clipped
[06:24:23] [PASSED] drm_test_rect_clip_scaled_clipped
[06:24:23] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[06:24:23] ================= drm_test_rect_intersect  =================
[06:24:23] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[06:24:23] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[06:24:23] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[06:24:23] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[06:24:23] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[06:24:23] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[06:24:23] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[06:24:23] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[06:24:23] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[06:24:23] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[06:24:23] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[06:24:23] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[06:24:23] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[06:24:23] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[06:24:23] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[06:24:23] ============= [PASSED] drm_test_rect_intersect =============
[06:24:23] ================ drm_test_rect_calc_hscale  ================
[06:24:23] [PASSED] normal use
[06:24:23] [PASSED] out of max range
[06:24:23] [PASSED] out of min range
[06:24:23] [PASSED] zero dst
[06:24:23] [PASSED] negative src
[06:24:23] [PASSED] negative dst
[06:24:23] ============ [PASSED] drm_test_rect_calc_hscale ============
[06:24:23] ================ drm_test_rect_calc_vscale  ================
[06:24:23] [PASSED] normal use
[06:24:23] [PASSED] out of max range
[06:24:23] [PASSED] out of min range
[06:24:23] [PASSED] zero dst
[06:24:23] [PASSED] negative src
[06:24:23] [PASSED] negative dst
[06:24:23] ============ [PASSED] drm_test_rect_calc_vscale ============
[06:24:23] ================== drm_test_rect_rotate  ===================
[06:24:23] [PASSED] reflect-x
[06:24:23] [PASSED] reflect-y
[06:24:23] [PASSED] rotate-0
[06:24:23] [PASSED] rotate-90
[06:24:23] [PASSED] rotate-180
[06:24:23] [PASSED] rotate-270
[06:24:23] ============== [PASSED] drm_test_rect_rotate ===============
[06:24:23] ================ drm_test_rect_rotate_inv  =================
[06:24:23] [PASSED] reflect-x
[06:24:23] [PASSED] reflect-y
[06:24:23] [PASSED] rotate-0
[06:24:23] [PASSED] rotate-90
[06:24:23] [PASSED] rotate-180
[06:24:23] [PASSED] rotate-270
[06:24:23] ============ [PASSED] drm_test_rect_rotate_inv =============
[06:24:23] ==================== [PASSED] drm_rect =====================
[06:24:23] ============ drm_sysfb_modeset_test (1 subtest) ============
[06:24:23] ============ drm_test_sysfb_build_fourcc_list  =============
[06:24:23] [PASSED] no native formats
[06:24:23] [PASSED] XRGB8888 as native format
[06:24:23] [PASSED] remove duplicates
[06:24:23] [PASSED] convert alpha formats
[06:24:23] [PASSED] random formats
[06:24:23] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[06:24:23] ============= [PASSED] drm_sysfb_modeset_test ==============
[06:24:23] ================== drm_fixp (2 subtests) ===================
[06:24:23] [PASSED] drm_test_int2fixp
[06:24:23] [PASSED] drm_test_sm2fixp
[06:24:23] ==================== [PASSED] drm_fixp =====================
[06:24:23] ============================================================
[06:24:23] Testing complete. Ran 637 tests: passed: 637
[06:24:23] Elapsed time: 27.380s total, 1.871s configuring, 25.293s building, 0.194s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[06:24:23] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[06:24:25] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[06:24:35] Starting KUnit Kernel (1/1)...
[06:24:35] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[06:24:35] ================= ttm_device (5 subtests) ==================
[06:24:35] [PASSED] ttm_device_init_basic
[06:24:35] [PASSED] ttm_device_init_multiple
[06:24:35] [PASSED] ttm_device_fini_basic
[06:24:35] [PASSED] ttm_device_init_no_vma_man
[06:24:35] ================== ttm_device_init_pools  ==================
[06:24:35] [PASSED] No DMA allocations, no DMA32 required
[06:24:35] [PASSED] DMA allocations, DMA32 required
[06:24:35] [PASSED] No DMA allocations, DMA32 required
[06:24:35] [PASSED] DMA allocations, no DMA32 required
[06:24:35] ============== [PASSED] ttm_device_init_pools ==============
[06:24:35] =================== [PASSED] ttm_device ====================
[06:24:35] ================== ttm_pool (8 subtests) ===================
[06:24:35] ================== ttm_pool_alloc_basic  ===================
[06:24:35] [PASSED] One page
[06:24:35] [PASSED] More than one page
[06:24:35] [PASSED] Above the allocation limit
[06:24:35] [PASSED] One page, with coherent DMA mappings enabled
[06:24:35] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[06:24:35] ============== [PASSED] ttm_pool_alloc_basic ===============
[06:24:35] ============== ttm_pool_alloc_basic_dma_addr  ==============
[06:24:35] [PASSED] One page
[06:24:35] [PASSED] More than one page
[06:24:35] [PASSED] Above the allocation limit
[06:24:35] [PASSED] One page, with coherent DMA mappings enabled
[06:24:35] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[06:24:35] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[06:24:35] [PASSED] ttm_pool_alloc_order_caching_match
[06:24:35] [PASSED] ttm_pool_alloc_caching_mismatch
[06:24:35] [PASSED] ttm_pool_alloc_order_mismatch
[06:24:35] [PASSED] ttm_pool_free_dma_alloc
[06:24:35] [PASSED] ttm_pool_free_no_dma_alloc
[06:24:35] [PASSED] ttm_pool_fini_basic
[06:24:35] ==================== [PASSED] ttm_pool =====================
[06:24:35] ================ ttm_resource (8 subtests) =================
[06:24:35] ================= ttm_resource_init_basic  =================
[06:24:35] [PASSED] Init resource in TTM_PL_SYSTEM
[06:24:35] [PASSED] Init resource in TTM_PL_VRAM
[06:24:35] [PASSED] Init resource in a private placement
[06:24:35] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[06:24:35] ============= [PASSED] ttm_resource_init_basic =============
[06:24:35] [PASSED] ttm_resource_init_pinned
[06:24:35] [PASSED] ttm_resource_fini_basic
[06:24:35] [PASSED] ttm_resource_manager_init_basic
[06:24:35] [PASSED] ttm_resource_manager_usage_basic
[06:24:35] [PASSED] ttm_resource_manager_set_used_basic
[06:24:35] [PASSED] ttm_sys_man_alloc_basic
[06:24:35] [PASSED] ttm_sys_man_free_basic
[06:24:35] ================== [PASSED] ttm_resource ===================
[06:24:35] =================== ttm_tt (15 subtests) ===================
[06:24:35] ==================== ttm_tt_init_basic  ====================
[06:24:35] [PASSED] Page-aligned size
[06:24:35] [PASSED] Extra pages requested
[06:24:35] ================ [PASSED] ttm_tt_init_basic ================
[06:24:35] [PASSED] ttm_tt_init_misaligned
[06:24:35] [PASSED] ttm_tt_fini_basic
[06:24:35] [PASSED] ttm_tt_fini_sg
[06:24:35] [PASSED] ttm_tt_fini_shmem
[06:24:35] [PASSED] ttm_tt_create_basic
[06:24:35] [PASSED] ttm_tt_create_invalid_bo_type
[06:24:35] [PASSED] ttm_tt_create_ttm_exists
[06:24:35] [PASSED] ttm_tt_create_failed
[06:24:35] [PASSED] ttm_tt_destroy_basic
[06:24:35] [PASSED] ttm_tt_populate_null_ttm
[06:24:35] [PASSED] ttm_tt_populate_populated_ttm
[06:24:35] [PASSED] ttm_tt_unpopulate_basic
[06:24:35] [PASSED] ttm_tt_unpopulate_empty_ttm
[06:24:35] [PASSED] ttm_tt_swapin_basic
[06:24:35] ===================== [PASSED] ttm_tt ======================
[06:24:35] =================== ttm_bo (14 subtests) ===================
[06:24:35] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[06:24:35] [PASSED] Cannot be interrupted and sleeps
[06:24:35] [PASSED] Cannot be interrupted, locks straight away
[06:24:35] [PASSED] Can be interrupted, sleeps
[06:24:35] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[06:24:35] [PASSED] ttm_bo_reserve_locked_no_sleep
[06:24:35] [PASSED] ttm_bo_reserve_no_wait_ticket
[06:24:35] [PASSED] ttm_bo_reserve_double_resv
[06:24:35] [PASSED] ttm_bo_reserve_interrupted
[06:24:35] [PASSED] ttm_bo_reserve_deadlock
[06:24:35] [PASSED] ttm_bo_unreserve_basic
[06:24:35] [PASSED] ttm_bo_unreserve_pinned
[06:24:35] [PASSED] ttm_bo_unreserve_bulk
[06:24:35] [PASSED] ttm_bo_fini_basic
[06:24:35] [PASSED] ttm_bo_fini_shared_resv
[06:24:35] [PASSED] ttm_bo_pin_basic
[06:24:35] [PASSED] ttm_bo_pin_unpin_resource
[06:24:35] [PASSED] ttm_bo_multiple_pin_one_unpin
[06:24:35] ===================== [PASSED] ttm_bo ======================
[06:24:35] ============== ttm_bo_validate (22 subtests) ===============
[06:24:35] ============== ttm_bo_init_reserved_sys_man  ===============
[06:24:35] [PASSED] Buffer object for userspace
[06:24:35] [PASSED] Kernel buffer object
[06:24:35] [PASSED] Shared buffer object
[06:24:35] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[06:24:35] ============== ttm_bo_init_reserved_mock_man  ==============
[06:24:35] [PASSED] Buffer object for userspace
[06:24:35] [PASSED] Kernel buffer object
[06:24:35] [PASSED] Shared buffer object
[06:24:35] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[06:24:35] [PASSED] ttm_bo_init_reserved_resv
[06:24:35] ================== ttm_bo_validate_basic  ==================
[06:24:35] [PASSED] Buffer object for userspace
[06:24:35] [PASSED] Kernel buffer object
[06:24:35] [PASSED] Shared buffer object
[06:24:35] ============== [PASSED] ttm_bo_validate_basic ==============
[06:24:35] [PASSED] ttm_bo_validate_invalid_placement
[06:24:35] ============= ttm_bo_validate_same_placement  ==============
[06:24:35] [PASSED] System manager
[06:24:35] [PASSED] VRAM manager
[06:24:35] ========= [PASSED] ttm_bo_validate_same_placement ==========
[06:24:35] [PASSED] ttm_bo_validate_failed_alloc
[06:24:35] [PASSED] ttm_bo_validate_pinned
[06:24:35] [PASSED] ttm_bo_validate_busy_placement
[06:24:35] ================ ttm_bo_validate_multihop  =================
[06:24:35] [PASSED] Buffer object for userspace
[06:24:35] [PASSED] Kernel buffer object
[06:24:35] [PASSED] Shared buffer object
[06:24:35] ============ [PASSED] ttm_bo_validate_multihop =============
[06:24:35] ========== ttm_bo_validate_no_placement_signaled  ==========
[06:24:35] [PASSED] Buffer object in system domain, no page vector
[06:24:35] [PASSED] Buffer object in system domain with an existing page vector
[06:24:35] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[06:24:35] ======== ttm_bo_validate_no_placement_not_signaled  ========
[06:24:35] [PASSED] Buffer object for userspace
[06:24:35] [PASSED] Kernel buffer object
[06:24:35] [PASSED] Shared buffer object
[06:24:35] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[06:24:35] [PASSED] ttm_bo_validate_move_fence_signaled
[06:24:35] ========= ttm_bo_validate_move_fence_not_signaled  =========
[06:24:35] [PASSED] Waits for GPU
[06:24:35] [PASSED] Tries to lock straight away
[06:24:35] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[06:24:35] [PASSED] ttm_bo_validate_swapout
[06:24:35] [PASSED] ttm_bo_validate_happy_evict
[06:24:35] [PASSED] ttm_bo_validate_all_pinned_evict
[06:24:35] [PASSED] ttm_bo_validate_allowed_only_evict
[06:24:35] [PASSED] ttm_bo_validate_deleted_evict
[06:24:35] [PASSED] ttm_bo_validate_busy_domain_evict
[06:24:35] [PASSED] ttm_bo_validate_evict_gutting
[06:24:35] [PASSED] ttm_bo_validate_recrusive_evict
[06:24:35] ================= [PASSED] ttm_bo_validate =================
[06:24:35] ============================================================
[06:24:35] Testing complete. Ran 102 tests: passed: 102
[06:24:35] Elapsed time: 11.974s total, 1.786s configuring, 9.973s building, 0.178s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/dma-buf/.kunitconfig
[06:24:35] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[06:24:37] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[06:24:46] Starting KUnit Kernel (1/1)...
[06:24:46] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[06:24:46] =============== dma-buf-fence (12 subtests) ================
[06:24:46] [PASSED] test_sanitycheck
[06:24:46] [PASSED] test_signaling
[06:24:46] [PASSED] test_add_callback
[06:24:46] [PASSED] test_late_add_callback
[06:24:46] [PASSED] test_rm_callback
[06:24:46] [PASSED] test_late_rm_callback
[06:24:46] [PASSED] test_status
[06:24:46] [PASSED] test_error
[06:24:46] [PASSED] test_wait
[06:24:46] [PASSED] test_wait_timeout
[06:24:46] [PASSED] test_stub
[06:24:46] [SKIPPED] test_race_signal_callback (requires at least 2 CPUs)
[06:24:46] ================== [PASSED] dma-buf-fence ==================
[06:24:46] ============ dma-buf-fence-chain (11 subtests) =============
[06:24:46] [PASSED] test_sanitycheck
[06:24:46] [PASSED] test_find_seqno
[06:24:46] [PASSED] test_find_signaled
[06:24:46] [PASSED] test_find_out_of_order
[06:24:51] [PASSED] test_find_gap
[06:24:51] [PASSED] test_find_race
[06:24:51] [PASSED] test_signal_forward
[06:24:51] [PASSED] test_signal_backward
[06:24:51] [PASSED] test_wait_forward
[06:24:51] [PASSED] test_wait_backward
[06:24:51] [PASSED] test_wait_random
[06:24:51] =============== [PASSED] dma-buf-fence-chain ===============
[06:24:51] ============ dma-buf-fence-unwrap (10 subtests) ============
[06:24:51] [PASSED] test_sanitycheck
[06:24:51] [PASSED] test_unwrap_array
[06:24:51] [PASSED] test_unwrap_chain
[06:24:51] [PASSED] test_unwrap_chain_array
[06:24:51] [PASSED] test_unwrap_merge
[06:24:51] [PASSED] test_unwrap_merge_duplicate
[06:24:51] [PASSED] test_unwrap_merge_seqno
[06:24:51] [PASSED] test_unwrap_merge_order
[06:24:51] [PASSED] test_unwrap_merge_complex
[06:24:51] [PASSED] test_unwrap_merge_complex_seqno
[06:24:51] ============== [PASSED] dma-buf-fence-unwrap ===============
[06:24:51] ================ dma-buf-resv (5 subtests) =================
[06:24:51] [PASSED] test_sanitycheck
[06:24:51] ===================== test_signaling  ======================
[06:24:51] [PASSED] kernel
[06:24:51] [PASSED] write
[06:24:51] [PASSED] read
[06:24:51] [PASSED] bookkeep
[06:24:51] ================= [PASSED] test_signaling ==================
[06:24:51] ====================== test_for_each  ======================
[06:24:51] [PASSED] kernel
[06:24:51] [PASSED] write
[06:24:51] [PASSED] read
[06:24:51] [PASSED] bookkeep
[06:24:51] ================== [PASSED] test_for_each ==================
[06:24:51] ================= test_for_each_unlocked  ==================
[06:24:51] [PASSED] kernel
[06:24:51] [PASSED] write
[06:24:51] [PASSED] read
[06:24:51] [PASSED] bookkeep
[06:24:51] ============= [PASSED] test_for_each_unlocked ==============
[06:24:51] ===================== test_get_fences  =====================
[06:24:51] [PASSED] kernel
[06:24:51] [PASSED] write
[06:24:51] [PASSED] read
[06:24:51] [PASSED] bookkeep
[06:24:51] ================= [PASSED] test_get_fences =================
[06:24:51] ================== [PASSED] dma-buf-resv ===================
[06:24:51] ============================================================
[06:24:51] Testing complete. Ran 50 tests: passed: 49, skipped: 1
[06:24:51] Elapsed time: 15.645s total, 1.768s configuring, 8.555s building, 5.276s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel