* [CI] drm/xe/vram: Add early VRAM health check
@ 2026-08-26 12:53 Matthew Auld
2026-08-26 12:59 ` ✗ CI.checkpatch: warning for " Patchwork
` (4 more replies)
0 siblings, 5 replies; 6+ messages in thread
From: Matthew Auld @ 2026-08-26 12:53 UTC (permalink / raw)
To: intel-xe
DO NOT REVIEW.
Use the last page as a canary for BAR sizing, CCS sizing, identity map
setup. If something is wrong the last page is where we will find it. Hit
it with everything we have. Test here should be non-destructive and fast.
Assisted-by: Gemini:gemini-3.1-pro-preview
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/xe/xe_device.c | 6 ++
drivers/gpu/drm/xe/xe_migrate.c | 56 ++++++++++
drivers/gpu/drm/xe/xe_migrate.h | 4 +
drivers/gpu/drm/xe/xe_tile_types.h | 4 +
drivers/gpu/drm/xe/xe_vram.c | 162 ++++++++++++++++++++++++++++-
drivers/gpu/drm/xe/xe_vram.h | 8 ++
6 files changed, 239 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index 74d566693dfd..7f4006b99a5f 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -1051,6 +1051,8 @@ int xe_device_probe(struct xe_device *xe)
if (err)
return err;
+ xe_vram_reserve_memtest_bo(xe);
+
for_each_tile(tile, xe, id) {
err = xe_tile_init(tile);
if (err)
@@ -1067,6 +1069,10 @@ int xe_device_probe(struct xe_device *xe)
return err;
}
+ err = xe_vram_memtest(xe);
+ if (err)
+ return err;
+
err = xe_pagefault_init(xe);
if (err)
return err;
diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
index 75b83687f1b5..f2151f222a17 100644
--- a/drivers/gpu/drm/xe/xe_migrate.c
+++ b/drivers/gpu/drm/xe/xe_migrate.c
@@ -2633,3 +2633,59 @@ void xe_migrate_job_lock_assert(struct xe_exec_queue *q)
#if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)
#include "tests/xe_migrate.c"
#endif
+
+#if IS_ENABLED(CONFIG_DRM_XE_DEBUG_MEM)
+void xe_migrate_debug_ccs_overlap(struct xe_migrate *m, struct xe_bo *last_page_bo, struct xe_bo *scratch_bo)
+{
+ struct xe_device *xe = tile_to_xe(m->tile);
+ struct xe_gt *gt = m->tile->primary_gt;
+ struct dma_fence *fence;
+ struct xe_bb *bb;
+ struct xe_sched_job *job;
+ u64 first_page_dpa, clear_L0_ofs, scratch_dpa, scratch_L0_ofs;
+
+ if (!xe_device_has_flat_ccs(xe))
+ return;
+
+ first_page_dpa = xe_vram_region_dpa_base(m->tile->mem.vram);
+ clear_L0_ofs = xe_migrate_vram_ofs(xe, first_page_dpa, true);
+
+ scratch_dpa = xe_bo_addr(scratch_bo, 0, XE_PAGE_SIZE);
+ scratch_L0_ofs = xe_migrate_vram_ofs(xe, scratch_dpa, false);
+
+ for (int j = 0; j < 4; j++) {
+ bb = xe_bb_new(gt, 256, xe->info.has_usm);
+ if (IS_ERR(bb)) {
+ drm_warn(&xe->drm, "Failed to create bb for VRAM overlap check\n");
+ return;
+ }
+
+ for (int i = 0; i < 16; i++) {
+ int idx = (j * 16) + i;
+ /* 4MB payload = 16KB CCS metadata */
+ emit_copy_ccs(gt, bb, scratch_L0_ofs + (idx * 16384), false,
+ clear_L0_ofs + (idx * SZ_4M), true, SZ_4M);
+ }
+
+ bb->cs[bb->len++] = MI_BATCH_BUFFER_END;
+
+ job = xe_bb_create_migration_job(m->q, bb,
+ xe_migrate_batch_base(m, xe->info.has_usm),
+ bb->len);
+ if (!IS_ERR(job)) {
+ xe_sched_job_add_migrate_flush(job, MI_FLUSH_DW_CCS);
+ xe_sched_job_arm(job);
+
+ fence = dma_fence_get(&job->drm.s_fence->finished);
+ xe_sched_job_push(job);
+
+ dma_fence_wait(fence, false);
+ dma_fence_put(fence);
+ } else {
+ drm_warn(&xe->drm, "Failed to create job for VRAM overlap check\n");
+ }
+
+ xe_bb_free(bb, NULL);
+ }
+}
+#endif
diff --git a/drivers/gpu/drm/xe/xe_migrate.h b/drivers/gpu/drm/xe/xe_migrate.h
index c3a268b01768..17cec0855dad 100644
--- a/drivers/gpu/drm/xe/xe_migrate.h
+++ b/drivers/gpu/drm/xe/xe_migrate.h
@@ -182,4 +182,8 @@ static inline void xe_migrate_job_lock_assert(struct xe_exec_queue *q)
void xe_migrate_job_lock(struct xe_migrate *m, struct xe_exec_queue *q);
void xe_migrate_job_unlock(struct xe_migrate *m, struct xe_exec_queue *q);
+#if IS_ENABLED(CONFIG_DRM_XE_DEBUG_MEM)
+void xe_migrate_debug_ccs_overlap(struct xe_migrate *m, struct xe_bo *last_page_bo, struct xe_bo *scratch_bo);
+#endif
+
#endif
diff --git a/drivers/gpu/drm/xe/xe_tile_types.h b/drivers/gpu/drm/xe/xe_tile_types.h
index 0048100ccb72..75097e4d1c64 100644
--- a/drivers/gpu/drm/xe/xe_tile_types.h
+++ b/drivers/gpu/drm/xe/xe_tile_types.h
@@ -97,6 +97,10 @@ struct xe_tile {
* Only main GT has page reclaim list allocations.
*/
struct xe_sa_manager *reclaim_pool;
+#if IS_ENABLED(CONFIG_DRM_XE_DEBUG)
+ /** @mem.memtest_bo: VRAM overlap check BO */
+ struct xe_bo *memtest_bo;
+#endif
} mem;
/** @sriov: tile level virtualization data */
diff --git a/drivers/gpu/drm/xe/xe_vram.c b/drivers/gpu/drm/xe/xe_vram.c
index 23eb7edbdd57..eb3d7b42371c 100644
--- a/drivers/gpu/drm/xe/xe_vram.c
+++ b/drivers/gpu/drm/xe/xe_vram.c
@@ -17,8 +17,11 @@
#include "xe_device.h"
#include "xe_force_wake.h"
#include "xe_gt_mcr.h"
+#include "xe_map.h"
+#include "xe_migrate.h"
#include "xe_mmio.h"
#include "xe_sriov.h"
+#include "xe_tile.h"
#include "xe_tile_sriov_vf.h"
#include "xe_ttm_vram_mgr.h"
#include "xe_vram.h"
@@ -89,7 +92,7 @@ static int get_flat_ccs_offset(struct xe_gt *gt, u64 tile_size, u64 *poffset)
offset = offset_hi << 32; /* HW view bits 39:32 */
offset |= offset_lo << 6; /* HW view bits 31:6 */
offset *= num_enabled; /* convert to SW view */
- offset = round_up(offset, SZ_128K); /* SW must round up to nearest 128K */
+ offset = round_up(offset, SZ_128K); /* SW must round down to nearest 2M */
/* We don't expect any holes */
xe_assert_msg(xe, offset == (xe_mmio_read64_2x32(>_to_tile(gt)->mmio, GSMBASE) -
@@ -387,3 +390,160 @@ resource_size_t xe_vram_region_actual_physical_size(const struct xe_vram_region
return vram ? vram->actual_physical_size : 0;
}
EXPORT_SYMBOL_IF_KUNIT(xe_vram_region_actual_physical_size);
+
+#if IS_ENABLED(CONFIG_DRM_XE_DEBUG_MEM)
+void xe_vram_reserve_memtest_bo(struct xe_device *xe)
+{
+ struct xe_tile *tile;
+ u8 id;
+
+ for_each_tile(tile, xe, id) {
+ u64 vram_size;
+
+ if (!tile->mem.vram)
+ continue;
+
+ if (tile->mem.vram->io_size < tile->mem.vram->usable_size) {
+ drm_info(&xe->drm, "Tile %d: Small-BAR system detected, skipping VRAM memtest\n", id);
+ continue;
+ }
+
+ vram_size = tile->mem.vram->usable_size;
+
+ tile->mem.memtest_bo = xe_bo_create_pin_map_at_novm(xe, tile, SZ_64K,
+ vram_size - SZ_64K,
+ ttm_bo_type_kernel,
+ XE_BO_FLAG_VRAM_IF_DGFX(tile),
+ 0, false);
+ if (IS_ERR(tile->mem.memtest_bo)) {
+ drm_warn(&xe->drm, "Tile %d: Failed to reserve memtest BO\n", id);
+ tile->mem.memtest_bo = NULL;
+ continue;
+ }
+
+ drm_info(&xe->drm, "Tile %d: Reserved memtest BO at offset 0x%llx\n",
+ id, vram_size - SZ_64K);
+ }
+}
+
+int xe_vram_memtest(struct xe_device *xe)
+{
+ struct xe_tile *tile;
+ u8 id;
+ int err = 0;
+
+ for_each_tile(tile, xe, id) {
+ struct xe_bo *last_page_bo = tile->mem.memtest_bo;
+ struct dma_fence *fence;
+ bool overlap = false;
+ int i, consecutive = 0;
+ u8 val;
+
+ if (!last_page_bo || !tile->migrate)
+ continue;
+
+ drm_info(&xe->drm, "Tile %d: Running VRAM memtest...\n", id);
+
+ /* 1. CPU write and readback first and last byte of the last page */
+ xe_map_wr(xe, &last_page_bo->vmap, 0, u8, 0xA5);
+ xe_map_wr(xe, &last_page_bo->vmap, SZ_64K - 1, u8, 0x5A);
+
+ wmb();
+ rmb();
+
+ val = xe_map_rd(xe, &last_page_bo->vmap, 0, u8);
+ if (drm_WARN(&xe->drm, val != 0xA5,
+ "Tile %d: CPU memtest failed at offset 0 (expected 0xA5, got 0x%02x)\n",
+ id, val)) {
+ err = -EIO;
+ goto unpin;
+ }
+
+ val = xe_map_rd(xe, &last_page_bo->vmap, SZ_64K - 1, u8);
+ if (drm_WARN(&xe->drm, val != 0x5A,
+ "Tile %d: CPU memtest failed at offset 65535 (expected 0x5A, got 0x%02x)\n",
+ id, val)) {
+ err = -EIO;
+ goto unpin;
+ }
+
+ /* 2. Non-CCS access via GPU on the last page */
+ fence = xe_migrate_clear(tile->migrate, last_page_bo,
+ last_page_bo->ttm.resource,
+ XE_MIGRATE_CLEAR_FLAG_BO_DATA);
+ if (!IS_ERR(fence)) {
+ dma_fence_wait(fence, false);
+ dma_fence_put(fence);
+ }
+
+ rmb();
+
+ val = xe_map_rd(xe, &last_page_bo->vmap, 0, u8);
+ if (drm_WARN(&xe->drm, val != 0x00,
+ "Tile %d: GPU memtest clear failed at offset 0 (expected 0x00, got 0x%02x)\n",
+ id, val)) {
+ err = -EIO;
+ goto unpin;
+ }
+
+ if (xe_device_has_flat_ccs(xe)) {
+ struct xe_bo *scratch_bo;
+
+ scratch_bo = xe_bo_create_pin_map_novm(xe, tile, SZ_1M,
+ ttm_bo_type_kernel,
+ XE_BO_FLAG_VRAM_IF_DGFX(tile), false);
+ if (IS_ERR(scratch_bo)) {
+ err = PTR_ERR(scratch_bo);
+ goto unpin;
+ }
+
+ /* Fill the last page with a known pattern */
+ xe_map_memset(xe, &last_page_bo->vmap, 0, 0x79, SZ_64K);
+ xe_map_memset(xe, &scratch_bo->vmap, 0, 0x00, SZ_1M);
+ wmb();
+
+ /* Manually check CCS overlap */
+ xe_migrate_debug_ccs_overlap(tile->migrate, last_page_bo, scratch_bo);
+
+ rmb();
+
+ /*
+ * If the bounds are wrong, the CPU's write to last_page_bo
+ * physically overwrote the CCS metadata of PA 0.
+ * We search for a consecutive block of 0x79 to avoid false positives.
+ */
+ consecutive = 0;
+ for (i = 0; i < SZ_1M; i++) {
+ if (xe_map_rd(xe, &scratch_bo->vmap, i, u8) == 0x79) {
+ consecutive++;
+ if (consecutive >= 8) {
+ overlap = true;
+ break;
+ }
+ } else {
+ consecutive = 0;
+ }
+ }
+
+ xe_bo_unpin_map_no_vm(scratch_bo);
+
+ if (drm_WARN(&xe->drm, overlap,
+ "Tile %d: VRAM bounds overlap CCS region! VRAM sizing is incorrect.\n",
+ id)) {
+ err = -EINVAL;
+ goto unpin;
+ }
+ }
+
+ drm_info(&xe->drm, "Tile %d: VRAM memtest completed.\n", id);
+
+unpin:
+ xe_bo_unpin_map_no_vm(last_page_bo);
+ tile->mem.memtest_bo = NULL;
+ if (err)
+ return err;
+ }
+
+ return 0;
+}
+#endif
diff --git a/drivers/gpu/drm/xe/xe_vram.h b/drivers/gpu/drm/xe/xe_vram.h
index dd1c8bf17922..3fa1afc467aa 100644
--- a/drivers/gpu/drm/xe/xe_vram.h
+++ b/drivers/gpu/drm/xe/xe_vram.h
@@ -23,4 +23,12 @@ resource_size_t xe_vram_region_dpa_base(const struct xe_vram_region *vram);
resource_size_t xe_vram_region_usable_size(const struct xe_vram_region *vram);
resource_size_t xe_vram_region_actual_physical_size(const struct xe_vram_region *vram);
+#if IS_ENABLED(CONFIG_DRM_XE_DEBUG_MEM)
+void xe_vram_reserve_memtest_bo(struct xe_device *xe);
+int xe_vram_memtest(struct xe_device *xe);
+#else
+static inline void xe_vram_reserve_memtest_bo(struct xe_device *xe) {}
+static inline int xe_vram_memtest(struct xe_device *xe) { return 0; }
+#endif
+
#endif
--
2.55.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* ✗ CI.checkpatch: warning for drm/xe/vram: Add early VRAM health check
2026-08-26 12:53 [CI] drm/xe/vram: Add early VRAM health check Matthew Auld
@ 2026-08-26 12:59 ` Patchwork
2026-08-26 13:01 ` ✓ CI.KUnit: success " Patchwork
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2026-08-26 12:59 UTC (permalink / raw)
To: Matthew Auld; +Cc: intel-xe
== Series Details ==
Series: drm/xe/vram: Add early VRAM health check
URL : https://patchwork.freedesktop.org/series/172786/
State : warning
== Summary ==
+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
061140b9bc586ae7f40abc1249c97e1cc72d1b9d
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit a4805e9ac8af8ad4b3a8a101e9cbed3cb1edb573
Author: Matthew Auld <matthew.auld@intel.com>
Date: Wed Aug 26 13:53:05 2026 +0100
drm/xe/vram: Add early VRAM health check
DO NOT REVIEW.
Use the last page as a canary for BAR sizing, CCS sizing, identity map
setup. If something is wrong the last page is where we will find it. Hit
it with everything we have. Test here should be non-destructive and fast.
Assisted-by: Gemini:gemini-3.1-pro-preview
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
+ /mt/dim checkpatch 4a47d4b5bf957bd7e34d8d3ab7096c42161892c6 drm-intel
a4805e9ac8af drm/xe/vram: Add early VRAM health check
-:49: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#49: FILE: drivers/gpu/drm/xe/xe_migrate.c:2638:
+void xe_migrate_debug_ccs_overlap(struct xe_migrate *m, struct xe_bo *last_page_bo, struct xe_bo *scratch_bo)
-:112: WARNING:LONG_LINE: line length of 110 exceeds 100 columns
#112: FILE: drivers/gpu/drm/xe/xe_migrate.h:186:
+void xe_migrate_debug_ccs_overlap(struct xe_migrate *m, struct xe_bo *last_page_bo, struct xe_bo *scratch_bo);
-:174: WARNING:LONG_LINE: line length of 110 exceeds 100 columns
#174: FILE: drivers/gpu/drm/xe/xe_vram.c:407:
+ drm_info(&xe->drm, "Tile %d: Small-BAR system detected, skipping VRAM memtest\n", id);
-:181: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#181: FILE: drivers/gpu/drm/xe/xe_vram.c:414:
+ tile->mem.memtest_bo = xe_bo_create_pin_map_at_novm(xe, tile, SZ_64K,
+ vram_size - SZ_64K,
-:218: WARNING:MEMORY_BARRIER: memory barrier without comment
#218: FILE: drivers/gpu/drm/xe/xe_vram.c:451:
+ wmb();
-:219: WARNING:MEMORY_BARRIER: memory barrier without comment
#219: FILE: drivers/gpu/drm/xe/xe_vram.c:452:
+ rmb();
-:246: WARNING:MEMORY_BARRIER: memory barrier without comment
#246: FILE: drivers/gpu/drm/xe/xe_vram.c:479:
+ rmb();
-:261: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#261: FILE: drivers/gpu/drm/xe/xe_vram.c:494:
+ XE_BO_FLAG_VRAM_IF_DGFX(tile), false);
-:270: WARNING:MEMORY_BARRIER: memory barrier without comment
#270: FILE: drivers/gpu/drm/xe/xe_vram.c:503:
+ wmb();
-:275: WARNING:MEMORY_BARRIER: memory barrier without comment
#275: FILE: drivers/gpu/drm/xe/xe_vram.c:508:
+ rmb();
total: 0 errors, 9 warnings, 1 checks, 286 lines checked
^ permalink raw reply [flat|nested] 6+ messages in thread
* ✓ CI.KUnit: success for drm/xe/vram: Add early VRAM health check
2026-08-26 12:53 [CI] drm/xe/vram: Add early VRAM health check Matthew Auld
2026-08-26 12:59 ` ✗ CI.checkpatch: warning for " Patchwork
@ 2026-08-26 13:01 ` Patchwork
2026-08-26 13:11 ` [CI] " sashiko-bot
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2026-08-26 13:01 UTC (permalink / raw)
To: Matthew Auld; +Cc: intel-xe
== Series Details ==
Series: drm/xe/vram: Add early VRAM health check
URL : https://patchwork.freedesktop.org/series/172786/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[12:59:31] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[12:59:35] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[13:00:07] Starting KUnit Kernel (1/1)...
[13:00:07] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[13:00:07] ================== guc_buf (11 subtests) ===================
[13:00:07] [PASSED] test_smallest
[13:00:07] [PASSED] test_largest
[13:00:07] [PASSED] test_granular
[13:00:07] [PASSED] test_unique
[13:00:07] [PASSED] test_overlap
[13:00:07] [PASSED] test_reusable
[13:00:07] [PASSED] test_too_big
[13:00:07] [PASSED] test_flush
[13:00:07] [PASSED] test_lookup
[13:00:07] [PASSED] test_data
[13:00:07] [PASSED] test_class
[13:00:07] ===================== [PASSED] guc_buf =====================
[13:00:07] =================== guc_dbm (7 subtests) ===================
[13:00:07] [PASSED] test_empty
[13:00:07] [PASSED] test_default
[13:00:07] ======================== test_size ========================
[13:00:07] [PASSED] 4
[13:00:07] [PASSED] 8
[13:00:07] [PASSED] 32
[13:00:07] [PASSED] 256
[13:00:07] ==================== [PASSED] test_size ====================
[13:00:07] ======================= test_reuse ========================
[13:00:07] [PASSED] 4
[13:00:07] [PASSED] 8
[13:00:07] [PASSED] 32
[13:00:07] [PASSED] 256
[13:00:07] =================== [PASSED] test_reuse ====================
[13:00:07] =================== test_range_overlap ====================
[13:00:07] [PASSED] 4
[13:00:07] [PASSED] 8
[13:00:07] [PASSED] 32
[13:00:07] [PASSED] 256
[13:00:07] =============== [PASSED] test_range_overlap ================
[13:00:07] =================== test_range_compact ====================
[13:00:07] [PASSED] 4
[13:00:07] [PASSED] 8
[13:00:07] [PASSED] 32
[13:00:07] [PASSED] 256
[13:00:07] =============== [PASSED] test_range_compact ================
[13:00:07] ==================== test_range_spare =====================
[13:00:07] [PASSED] 4
[13:00:07] [PASSED] 8
[13:00:07] [PASSED] 32
[13:00:07] [PASSED] 256
[13:00:07] ================ [PASSED] test_range_spare =================
[13:00:07] ===================== [PASSED] guc_dbm =====================
[13:00:07] =================== guc_idm (6 subtests) ===================
[13:00:07] [PASSED] bad_init
[13:00:07] [PASSED] no_init
[13:00:07] [PASSED] init_fini
[13:00:07] [PASSED] check_used
[13:00:07] [PASSED] check_quota
[13:00:07] [PASSED] check_all
[13:00:07] ===================== [PASSED] guc_idm =====================
[13:00:07] =============== guc_klv_helpers (9 subtests) ===============
[13:00:07] [PASSED] test_count
[13:00:07] [PASSED] test_encode_u32
[13:00:07] [PASSED] test_encode_u64
[13:00:07] [PASSED] test_encode_string
[13:00:07] [PASSED] test_encode_object_raw
[13:00:07] [PASSED] test_encode_object_klv
[13:00:07] [PASSED] test_encode_object_nested
[13:00:07] [PASSED] test_encode_object_basic
[13:00:07] [PASSED] test_print
[13:00:07] ================= [PASSED] guc_klv_helpers =================
[13:00:07] =================== xe_log (4 subtests) ====================
[13:00:07] [PASSED] demo_cper
[13:00:07] [PASSED] demo_dmesg
[13:00:07] ======================= test_dmesg ========================
[13:00:07] [PASSED] test_fatal
[13:00:07] [PASSED] test_fatal_tile
[13:00:07] [PASSED] test_fatal_gt
[13:00:07] [PASSED] test_fatal_comp
[13:00:07] [PASSED] test_fatal_comp_tile
[13:00:07] [PASSED] test_fatal_comp_gt
[13:00:07] [PASSED] test_fatal_all
[13:00:07] [PASSED] test_recoverable
[13:00:07] [PASSED] test_recoverable_tile
[13:00:07] [PASSED] test_recoverable_gt
[13:00:07] [PASSED] test_recoverable_comp
[13:00:07] [PASSED] test_recoverable_comp_tile
[13:00:07] [PASSED] test_recoverable_comp_gt
[13:00:07] [PASSED] test_recoverable_all
[13:00:07] [PASSED] test_info
[13:00:07] [PASSED] test_info_tile
[13:00:07] [PASSED] test_info_gt
[13:00:07] [PASSED] test_info_err
[13:00:07] [PASSED] test_info_comp
[13:00:07] [PASSED] test_info_comp_tile
[13:00:07] [PASSED] test_info_comp_gt
[13:00:07] [PASSED] test_info_all
[13:00:07] [PASSED] test_hw_fatal
[13:00:07] [PASSED] test_hw_recoverable
[13:00:07] [PASSED] test_hw_corrected
[13:00:07] [PASSED] test_hw_informational
[13:00:07] =================== [PASSED] test_dmesg ====================
[13:00:07] ====================== test_invalid =======================
[13:00:07] [SKIPPED] no-component no-location no-warn (requires CONFIG_DRM_XE_DEBUG)
[13:00:07] [SKIPPED] reserved location (requires CONFIG_DRM_XE_DEBUG)
[13:00:07] [SKIPPED] unknown location (requires CONFIG_DRM_XE_DEBUG)
[13:00:07] [SKIPPED] nonzero-device-id location (requires CONFIG_DRM_XE_DEBUG)
[13:00:07] [SKIPPED] invalid-tile-id location (requires CONFIG_DRM_XE_DEBUG)
[13:00:07] [SKIPPED] invalid-gt-id location (requires CONFIG_DRM_XE_DEBUG)
[13:00:07] [SKIPPED] unknown component class (requires CONFIG_DRM_XE_DEBUG)
[13:00:07] [SKIPPED] unknown system component (requires CONFIG_DRM_XE_DEBUG)
[13:00:07] [SKIPPED] unknown hardware component (requires CONFIG_DRM_XE_DEBUG)
[13:00:07] [SKIPPED] unknown component and location (requires CONFIG_DRM_XE_DEBUG)
[13:00:07] ================== [SKIPPED] test_invalid ==================
[13:00:07] ===================== [PASSED] xe_log ======================
[13:00:07] ================== no_relay (3 subtests) ===================
[13:00:07] [PASSED] xe_drops_guc2pf_if_not_ready
[13:00:07] [PASSED] xe_drops_guc2vf_if_not_ready
[13:00:07] [PASSED] xe_rejects_send_if_not_ready
[13:00:07] ==================== [PASSED] no_relay =====================
[13:00:07] ================== pf_relay (14 subtests) ==================
[13:00:07] [PASSED] pf_rejects_guc2pf_too_short
[13:00:07] [PASSED] pf_rejects_guc2pf_too_long
[13:00:07] [PASSED] pf_rejects_guc2pf_no_payload
[13:00:07] [PASSED] pf_fails_no_payload
[13:00:07] [PASSED] pf_fails_bad_origin
[13:00:07] [PASSED] pf_fails_bad_type
[13:00:07] [PASSED] pf_txn_reports_error
[13:00:07] [PASSED] pf_txn_sends_pf2guc
[13:00:07] [PASSED] pf_sends_pf2guc
[13:00:07] [SKIPPED] pf_loopback_nop (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[13:00:07] [SKIPPED] pf_loopback_echo (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[13:00:07] [SKIPPED] pf_loopback_fail (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[13:00:07] [SKIPPED] pf_loopback_busy (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[13:00:07] [SKIPPED] pf_loopback_retry (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[13:00:07] ==================== [PASSED] pf_relay =====================
[13:00:07] ================== vf_relay (3 subtests) ===================
[13:00:07] [PASSED] vf_rejects_guc2vf_too_short
[13:00:07] [PASSED] vf_rejects_guc2vf_too_long
[13:00:07] [PASSED] vf_rejects_guc2vf_no_payload
[13:00:07] ==================== [PASSED] vf_relay =====================
[13:00:07] ================ pf_gt_config (9 subtests) =================
[13:00:07] [PASSED] fair_contexts_1vf
[13:00:07] [PASSED] fair_doorbells_1vf
[13:00:07] [PASSED] fair_ggtt_1vf
[13:00:07] ====================== fair_vram_1vf ======================
[13:00:07] [PASSED] 3.50 GiB
[13:00:07] [PASSED] 11.5 GiB
[13:00:07] [PASSED] 15.5 GiB
[13:00:07] [PASSED] 31.5 GiB
[13:00:07] [PASSED] 63.5 GiB
[13:00:07] [PASSED] 1.91 GiB
[13:00:07] ================== [PASSED] fair_vram_1vf ==================
[13:00:07] ================ fair_vram_1vf_admin_only =================
[13:00:07] [PASSED] 3.50 GiB
[13:00:07] [PASSED] 11.5 GiB
[13:00:07] [PASSED] 15.5 GiB
[13:00:07] [PASSED] 31.5 GiB
[13:00:07] [PASSED] 63.5 GiB
[13:00:07] [PASSED] 1.91 GiB
[13:00:07] ============ [PASSED] fair_vram_1vf_admin_only =============
[13:00:07] ====================== fair_contexts ======================
[13:00:07] [PASSED] 1 VF
[13:00:07] [PASSED] 2 VFs
[13:00:07] [PASSED] 3 VFs
[13:00:07] [PASSED] 4 VFs
[13:00:07] [PASSED] 5 VFs
[13:00:07] [PASSED] 6 VFs
[13:00:07] [PASSED] 7 VFs
[13:00:07] [PASSED] 8 VFs
[13:00:07] [PASSED] 9 VFs
[13:00:07] [PASSED] 10 VFs
[13:00:07] [PASSED] 11 VFs
[13:00:07] [PASSED] 12 VFs
[13:00:07] [PASSED] 13 VFs
[13:00:07] [PASSED] 14 VFs
[13:00:07] [PASSED] 15 VFs
[13:00:07] [PASSED] 16 VFs
[13:00:07] [PASSED] 17 VFs
[13:00:07] [PASSED] 18 VFs
[13:00:07] [PASSED] 19 VFs
[13:00:07] [PASSED] 20 VFs
[13:00:07] [PASSED] 21 VFs
[13:00:07] [PASSED] 22 VFs
[13:00:07] [PASSED] 23 VFs
[13:00:07] [PASSED] 24 VFs
[13:00:07] [PASSED] 25 VFs
[13:00:07] [PASSED] 26 VFs
[13:00:07] [PASSED] 27 VFs
[13:00:07] [PASSED] 28 VFs
[13:00:07] [PASSED] 29 VFs
[13:00:07] [PASSED] 30 VFs
[13:00:07] [PASSED] 31 VFs
[13:00:07] [PASSED] 32 VFs
[13:00:07] [PASSED] 33 VFs
[13:00:07] [PASSED] 34 VFs
[13:00:07] [PASSED] 35 VFs
[13:00:07] [PASSED] 36 VFs
[13:00:07] [PASSED] 37 VFs
[13:00:07] [PASSED] 38 VFs
[13:00:07] [PASSED] 39 VFs
[13:00:07] [PASSED] 40 VFs
[13:00:07] [PASSED] 41 VFs
[13:00:07] [PASSED] 42 VFs
[13:00:07] [PASSED] 43 VFs
[13:00:07] [PASSED] 44 VFs
[13:00:07] [PASSED] 45 VFs
[13:00:07] [PASSED] 46 VFs
[13:00:07] [PASSED] 47 VFs
[13:00:07] [PASSED] 48 VFs
[13:00:07] [PASSED] 49 VFs
[13:00:07] [PASSED] 50 VFs
[13:00:07] [PASSED] 51 VFs
[13:00:07] [PASSED] 52 VFs
[13:00:07] [PASSED] 53 VFs
[13:00:07] [PASSED] 54 VFs
[13:00:07] [PASSED] 55 VFs
[13:00:07] [PASSED] 56 VFs
[13:00:07] [PASSED] 57 VFs
[13:00:07] [PASSED] 58 VFs
[13:00:07] [PASSED] 59 VFs
[13:00:07] [PASSED] 60 VFs
[13:00:07] [PASSED] 61 VFs
[13:00:07] [PASSED] 62 VFs
[13:00:07] [PASSED] 63 VFs
[13:00:07] ================== [PASSED] fair_contexts ==================
[13:00:07] ===================== fair_doorbells ======================
[13:00:07] [PASSED] 1 VF
[13:00:07] [PASSED] 2 VFs
[13:00:07] [PASSED] 3 VFs
[13:00:07] [PASSED] 4 VFs
[13:00:07] [PASSED] 5 VFs
[13:00:07] [PASSED] 6 VFs
[13:00:07] [PASSED] 7 VFs
[13:00:07] [PASSED] 8 VFs
[13:00:07] [PASSED] 9 VFs
[13:00:07] [PASSED] 10 VFs
[13:00:07] [PASSED] 11 VFs
[13:00:07] [PASSED] 12 VFs
[13:00:07] [PASSED] 13 VFs
[13:00:07] [PASSED] 14 VFs
[13:00:07] [PASSED] 15 VFs
[13:00:07] [PASSED] 16 VFs
[13:00:07] [PASSED] 17 VFs
[13:00:07] [PASSED] 18 VFs
[13:00:07] [PASSED] 19 VFs
[13:00:07] [PASSED] 20 VFs
[13:00:07] [PASSED] 21 VFs
[13:00:07] [PASSED] 22 VFs
[13:00:07] [PASSED] 23 VFs
[13:00:07] [PASSED] 24 VFs
[13:00:07] [PASSED] 25 VFs
[13:00:07] [PASSED] 26 VFs
[13:00:07] [PASSED] 27 VFs
[13:00:07] [PASSED] 28 VFs
[13:00:07] [PASSED] 29 VFs
[13:00:07] [PASSED] 30 VFs
[13:00:07] [PASSED] 31 VFs
[13:00:07] [PASSED] 32 VFs
[13:00:07] [PASSED] 33 VFs
[13:00:07] [PASSED] 34 VFs
[13:00:07] [PASSED] 35 VFs
[13:00:07] [PASSED] 36 VFs
[13:00:07] [PASSED] 37 VFs
[13:00:07] [PASSED] 38 VFs
[13:00:07] [PASSED] 39 VFs
[13:00:07] [PASSED] 40 VFs
[13:00:07] [PASSED] 41 VFs
[13:00:07] [PASSED] 42 VFs
[13:00:07] [PASSED] 43 VFs
[13:00:07] [PASSED] 44 VFs
[13:00:07] [PASSED] 45 VFs
[13:00:07] [PASSED] 46 VFs
[13:00:07] [PASSED] 47 VFs
[13:00:07] [PASSED] 48 VFs
[13:00:07] [PASSED] 49 VFs
[13:00:07] [PASSED] 50 VFs
[13:00:07] [PASSED] 51 VFs
[13:00:07] [PASSED] 52 VFs
[13:00:07] [PASSED] 53 VFs
[13:00:07] [PASSED] 54 VFs
[13:00:07] [PASSED] 55 VFs
[13:00:07] [PASSED] 56 VFs
[13:00:07] [PASSED] 57 VFs
[13:00:07] [PASSED] 58 VFs
[13:00:07] [PASSED] 59 VFs
[13:00:07] [PASSED] 60 VFs
[13:00:07] [PASSED] 61 VFs
[13:00:07] [PASSED] 62 VFs
[13:00:07] [PASSED] 63 VFs
[13:00:07] ================= [PASSED] fair_doorbells ==================
[13:00:07] ======================== fair_ggtt ========================
[13:00:07] [PASSED] 1 VF
[13:00:07] [PASSED] 2 VFs
[13:00:07] [PASSED] 3 VFs
[13:00:07] [PASSED] 4 VFs
[13:00:07] [PASSED] 5 VFs
[13:00:07] [PASSED] 6 VFs
[13:00:07] [PASSED] 7 VFs
[13:00:07] [PASSED] 8 VFs
[13:00:07] [PASSED] 9 VFs
[13:00:07] [PASSED] 10 VFs
[13:00:07] [PASSED] 11 VFs
[13:00:07] [PASSED] 12 VFs
[13:00:07] [PASSED] 13 VFs
[13:00:07] [PASSED] 14 VFs
[13:00:07] [PASSED] 15 VFs
[13:00:07] [PASSED] 16 VFs
[13:00:07] [PASSED] 17 VFs
[13:00:07] [PASSED] 18 VFs
[13:00:07] [PASSED] 19 VFs
[13:00:07] [PASSED] 20 VFs
[13:00:07] [PASSED] 21 VFs
[13:00:07] [PASSED] 22 VFs
[13:00:07] [PASSED] 23 VFs
[13:00:07] [PASSED] 24 VFs
[13:00:07] [PASSED] 25 VFs
[13:00:07] [PASSED] 26 VFs
[13:00:07] [PASSED] 27 VFs
[13:00:07] [PASSED] 28 VFs
[13:00:07] [PASSED] 29 VFs
[13:00:07] [PASSED] 30 VFs
[13:00:07] [PASSED] 31 VFs
[13:00:07] [PASSED] 32 VFs
[13:00:07] [PASSED] 33 VFs
[13:00:07] [PASSED] 34 VFs
[13:00:07] [PASSED] 35 VFs
[13:00:07] [PASSED] 36 VFs
[13:00:07] [PASSED] 37 VFs
[13:00:07] [PASSED] 38 VFs
[13:00:07] [PASSED] 39 VFs
[13:00:07] [PASSED] 40 VFs
[13:00:07] [PASSED] 41 VFs
[13:00:07] [PASSED] 42 VFs
[13:00:07] [PASSED] 43 VFs
[13:00:07] [PASSED] 44 VFs
[13:00:07] [PASSED] 45 VFs
[13:00:07] [PASSED] 46 VFs
[13:00:07] [PASSED] 47 VFs
[13:00:07] [PASSED] 48 VFs
[13:00:07] [PASSED] 49 VFs
[13:00:07] [PASSED] 50 VFs
[13:00:07] [PASSED] 51 VFs
[13:00:07] [PASSED] 52 VFs
[13:00:07] [PASSED] 53 VFs
[13:00:07] [PASSED] 54 VFs
[13:00:07] [PASSED] 55 VFs
[13:00:07] [PASSED] 56 VFs
[13:00:07] [PASSED] 57 VFs
[13:00:08] [PASSED] 58 VFs
[13:00:08] [PASSED] 59 VFs
[13:00:08] [PASSED] 60 VFs
[13:00:08] [PASSED] 61 VFs
[13:00:08] [PASSED] 62 VFs
[13:00:08] [PASSED] 63 VFs
[13:00:08] ==================== [PASSED] fair_ggtt ====================
[13:00:08] ======================== fair_vram ========================
[13:00:08] [PASSED] 1 VF
[13:00:08] [PASSED] 2 VFs
[13:00:08] [PASSED] 3 VFs
[13:00:08] [PASSED] 4 VFs
[13:00:08] [PASSED] 5 VFs
[13:00:08] [PASSED] 6 VFs
[13:00:08] [PASSED] 7 VFs
[13:00:08] [PASSED] 8 VFs
[13:00:08] [PASSED] 9 VFs
[13:00:08] [PASSED] 10 VFs
[13:00:08] [PASSED] 11 VFs
[13:00:08] [PASSED] 12 VFs
[13:00:08] [PASSED] 13 VFs
[13:00:08] [PASSED] 14 VFs
[13:00:08] [PASSED] 15 VFs
[13:00:08] [PASSED] 16 VFs
[13:00:08] [PASSED] 17 VFs
[13:00:08] [PASSED] 18 VFs
[13:00:08] [PASSED] 19 VFs
[13:00:08] [PASSED] 20 VFs
[13:00:08] [PASSED] 21 VFs
[13:00:08] [PASSED] 22 VFs
[13:00:08] [PASSED] 23 VFs
[13:00:08] [PASSED] 24 VFs
[13:00:08] [PASSED] 25 VFs
[13:00:08] [PASSED] 26 VFs
[13:00:08] [PASSED] 27 VFs
[13:00:08] [PASSED] 28 VFs
[13:00:08] [PASSED] 29 VFs
[13:00:08] [PASSED] 30 VFs
[13:00:08] [PASSED] 31 VFs
[13:00:08] [PASSED] 32 VFs
[13:00:08] [PASSED] 33 VFs
[13:00:08] [PASSED] 34 VFs
[13:00:08] [PASSED] 35 VFs
[13:00:08] [PASSED] 36 VFs
[13:00:08] [PASSED] 37 VFs
[13:00:08] [PASSED] 38 VFs
[13:00:08] [PASSED] 39 VFs
[13:00:08] [PASSED] 40 VFs
[13:00:08] [PASSED] 41 VFs
[13:00:08] [PASSED] 42 VFs
[13:00:08] [PASSED] 43 VFs
[13:00:08] [PASSED] 44 VFs
[13:00:08] [PASSED] 45 VFs
[13:00:08] [PASSED] 46 VFs
[13:00:08] [PASSED] 47 VFs
[13:00:08] [PASSED] 48 VFs
[13:00:08] [PASSED] 49 VFs
[13:00:08] [PASSED] 50 VFs
[13:00:08] [PASSED] 51 VFs
[13:00:08] [PASSED] 52 VFs
[13:00:08] [PASSED] 53 VFs
[13:00:08] [PASSED] 54 VFs
[13:00:08] [PASSED] 55 VFs
[13:00:08] [PASSED] 56 VFs
[13:00:08] [PASSED] 57 VFs
[13:00:08] [PASSED] 58 VFs
[13:00:08] [PASSED] 59 VFs
[13:00:08] [PASSED] 60 VFs
[13:00:08] [PASSED] 61 VFs
[13:00:08] [PASSED] 62 VFs
[13:00:08] [PASSED] 63 VFs
[13:00:08] ==================== [PASSED] fair_vram ====================
[13:00:08] ================== [PASSED] pf_gt_config ===================
[13:00:08] ===================== lmtt (1 subtest) =====================
[13:00:08] ======================== test_ops =========================
[13:00:08] [PASSED] 2-level
[13:00:08] [PASSED] multi-level
[13:00:08] ==================== [PASSED] test_ops =====================
[13:00:08] ====================== [PASSED] lmtt =======================
[13:00:08] ================= sriov_packet (1 subtest) =================
[13:00:08] [PASSED] test_descriptor_init
[13:00:08] ================== [PASSED] sriov_packet ===================
[13:00:08] ================= pf_service (11 subtests) =================
[13:00:08] [PASSED] pf_negotiate_any
[13:00:08] [PASSED] pf_negotiate_base_match
[13:00:08] [PASSED] pf_negotiate_base_newer
[13:00:08] [PASSED] pf_negotiate_base_next
[13:00:08] [SKIPPED] pf_negotiate_base_older (no older minor)
[13:00:08] [PASSED] pf_negotiate_base_prev
[13:00:08] [PASSED] pf_negotiate_latest_match
[13:00:08] [PASSED] pf_negotiate_latest_newer
[13:00:08] [PASSED] pf_negotiate_latest_next
[13:00:08] [SKIPPED] pf_negotiate_latest_older (no older minor)
[13:00:08] [SKIPPED] pf_negotiate_latest_prev (no prev major)
[13:00:08] =================== [PASSED] pf_service ====================
[13:00:08] ================= xe_guc_g2g (2 subtests) ==================
[13:00:08] ============== xe_live_guc_g2g_kunit_default ==============
[13:00:08] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[13:00:08] ============== xe_live_guc_g2g_kunit_allmem ===============
[13:00:08] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[13:00:08] =================== [SKIPPED] xe_guc_g2g ===================
[13:00:08] =================== xe_mocs (2 subtests) ===================
[13:00:08] ================ xe_live_mocs_kernel_kunit ================
[13:00:08] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[13:00:08] ================ xe_live_mocs_reset_kunit =================
[13:00:08] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[13:00:08] ==================== [SKIPPED] xe_mocs =====================
[13:00:08] ================= xe_migrate (2 subtests) ==================
[13:00:08] ================= xe_migrate_sanity_kunit =================
[13:00:08] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[13:00:08] ================== xe_validate_ccs_kunit ==================
[13:00:08] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[13:00:08] =================== [SKIPPED] xe_migrate ===================
[13:00:08] ================== xe_dma_buf (1 subtest) ==================
[13:00:08] ==================== xe_dma_buf_kunit =====================
[13:00:08] ================ [SKIPPED] xe_dma_buf_kunit ================
[13:00:08] =================== [SKIPPED] xe_dma_buf ===================
[13:00:08] ================= xe_bo_shrink (1 subtest) =================
[13:00:08] =================== xe_bo_shrink_kunit ====================
[13:00:08] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[13:00:08] ================== [SKIPPED] xe_bo_shrink ==================
[13:00:08] ==================== xe_bo (2 subtests) ====================
[13:00:08] ================== xe_ccs_migrate_kunit ===================
[13:00:08] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[13:00:08] ==================== xe_bo_evict_kunit ====================
[13:00:08] =============== [SKIPPED] xe_bo_evict_kunit ================
[13:00:08] ===================== [SKIPPED] xe_bo ======================
[13:00:08] =================== xe_any (9 subtests) ====================
[13:00:08] [PASSED] test_to_xe
[13:00:08] [PASSED] test_to_dev
[13:00:08] [PASSED] test_to_pdev
[13:00:08] [PASSED] test_to_drm
[13:00:08] [PASSED] test_if_pdev
[13:00:08] [PASSED] test_if_xe
[13:00:08] [PASSED] test_if_tile
[13:00:08] [PASSED] test_if_gt
[13:00:08] [PASSED] test_to_id
[13:00:08] ===================== [PASSED] xe_any ======================
[13:00:08] ==================== args (13 subtests) ====================
[13:00:08] [PASSED] count_args_test
[13:00:08] [PASSED] call_args_example
[13:00:08] [PASSED] call_args_test
[13:00:08] [PASSED] drop_first_arg_example
[13:00:08] [PASSED] drop_first_arg_test
[13:00:08] [PASSED] first_arg_example
[13:00:08] [PASSED] first_arg_test
[13:00:08] [PASSED] last_arg_example
[13:00:08] [PASSED] last_arg_test
[13:00:08] [PASSED] pick_arg_example
[13:00:08] [PASSED] if_args_example
[13:00:08] [PASSED] if_args_test
[13:00:08] [PASSED] sep_comma_example
[13:00:08] ====================== [PASSED] args =======================
[13:00:08] =================== xe_pci (3 subtests) ====================
[13:00:08] ==================== check_graphics_ip ====================
[13:00:08] [PASSED] 12.00 Xe_LP
[13:00:08] [PASSED] 12.10 Xe_LP+
[13:00:08] [PASSED] 12.55 Xe_HPG
[13:00:08] [PASSED] 12.60 Xe_HPC
[13:00:08] [PASSED] 12.70 Xe_LPG
[13:00:08] [PASSED] 12.71 Xe_LPG
[13:00:08] [PASSED] 12.74 Xe_LPG+
[13:00:08] [PASSED] 20.01 Xe2_HPG
[13:00:08] [PASSED] 20.02 Xe2_HPG
[13:00:08] [PASSED] 20.04 Xe2_LPG
[13:00:08] [PASSED] 30.00 Xe3_LPG
[13:00:08] [PASSED] 30.01 Xe3_LPG
[13:00:08] [PASSED] 30.03 Xe3_LPG
[13:00:08] [PASSED] 30.04 Xe3_LPG
[13:00:08] [PASSED] 30.05 Xe3_LPG
[13:00:08] [PASSED] 35.10 Xe3p_LPG
[13:00:08] [PASSED] 35.11 Xe3p_XPC
[13:00:08] ================ [PASSED] check_graphics_ip ================
[13:00:08] ===================== check_media_ip ======================
[13:00:08] [PASSED] 12.00 Xe_M
[13:00:08] [PASSED] 12.55 Xe_HPM
[13:00:08] [PASSED] 13.00 Xe_LPM+
[13:00:08] [PASSED] 13.01 Xe2_HPM
[13:00:08] [PASSED] 20.00 Xe2_LPM
[13:00:08] [PASSED] 30.00 Xe3_LPM
[13:00:08] [PASSED] 30.02 Xe3_LPM
[13:00:08] [PASSED] 35.00 Xe3p_LPM
[13:00:08] [PASSED] 35.03 Xe3p_HPM
[13:00:08] ================= [PASSED] check_media_ip ==================
[13:00:08] =================== check_platform_desc ===================
[13:00:08] [PASSED] 0x9A60 (TIGERLAKE)
[13:00:08] [PASSED] 0x9A68 (TIGERLAKE)
[13:00:08] [PASSED] 0x9A70 (TIGERLAKE)
[13:00:08] [PASSED] 0x9A40 (TIGERLAKE)
[13:00:08] [PASSED] 0x9A49 (TIGERLAKE)
[13:00:08] [PASSED] 0x9A59 (TIGERLAKE)
[13:00:08] [PASSED] 0x9A78 (TIGERLAKE)
[13:00:08] [PASSED] 0x9AC0 (TIGERLAKE)
[13:00:08] [PASSED] 0x9AC9 (TIGERLAKE)
[13:00:08] [PASSED] 0x9AD9 (TIGERLAKE)
[13:00:08] [PASSED] 0x9AF8 (TIGERLAKE)
[13:00:08] [PASSED] 0x4C80 (ROCKETLAKE)
[13:00:08] [PASSED] 0x4C8A (ROCKETLAKE)
[13:00:08] [PASSED] 0x4C8B (ROCKETLAKE)
[13:00:08] [PASSED] 0x4C8C (ROCKETLAKE)
[13:00:08] [PASSED] 0x4C90 (ROCKETLAKE)
[13:00:08] [PASSED] 0x4C9A (ROCKETLAKE)
[13:00:08] [PASSED] 0x4680 (ALDERLAKE_S)
[13:00:08] [PASSED] 0x4682 (ALDERLAKE_S)
[13:00:08] [PASSED] 0x4688 (ALDERLAKE_S)
[13:00:08] [PASSED] 0x468A (ALDERLAKE_S)
[13:00:08] [PASSED] 0x468B (ALDERLAKE_S)
[13:00:08] [PASSED] 0x4690 (ALDERLAKE_S)
[13:00:08] [PASSED] 0x4692 (ALDERLAKE_S)
[13:00:08] [PASSED] 0x4693 (ALDERLAKE_S)
[13:00:08] [PASSED] 0x46A0 (ALDERLAKE_P)
[13:00:08] [PASSED] 0x46A1 (ALDERLAKE_P)
[13:00:08] [PASSED] 0x46A2 (ALDERLAKE_P)
[13:00:08] [PASSED] 0x46A3 (ALDERLAKE_P)
[13:00:08] [PASSED] 0x46A6 (ALDERLAKE_P)
[13:00:08] [PASSED] 0x46A8 (ALDERLAKE_P)
[13:00:08] [PASSED] 0x46AA (ALDERLAKE_P)
[13:00:08] [PASSED] 0x462A (ALDERLAKE_P)
[13:00:08] [PASSED] 0x4626 (ALDERLAKE_P)
[13:00:08] [PASSED] 0x4628 (ALDERLAKE_P)
[13:00:08] [PASSED] 0x46B0 (ALDERLAKE_P)
[13:00:08] [PASSED] 0x46B1 (ALDERLAKE_P)
[13:00:08] [PASSED] 0x46B2 (ALDERLAKE_P)
[13:00:08] [PASSED] 0x46B3 (ALDERLAKE_P)
[13:00:08] [PASSED] 0x46C0 (ALDERLAKE_P)
[13:00:08] [PASSED] 0x46C1 (ALDERLAKE_P)
[13:00:08] [PASSED] 0x46C2 (ALDERLAKE_P)
[13:00:08] [PASSED] 0x46C3 (ALDERLAKE_P)
[13:00:08] [PASSED] 0x46D0 (ALDERLAKE_N)
[13:00:08] [PASSED] 0x46D1 (ALDERLAKE_N)
[13:00:08] [PASSED] 0x46D2 (ALDERLAKE_N)
[13:00:08] [PASSED] 0x46D3 (ALDERLAKE_N)
[13:00:08] [PASSED] 0x46D4 (ALDERLAKE_N)
[13:00:08] [PASSED] 0xA721 (ALDERLAKE_P)
[13:00:08] [PASSED] 0xA7A1 (ALDERLAKE_P)
[13:00:08] [PASSED] 0xA7A9 (ALDERLAKE_P)
[13:00:08] [PASSED] 0xA7AC (ALDERLAKE_P)
[13:00:08] [PASSED] 0xA7AD (ALDERLAKE_P)
[13:00:08] [PASSED] 0xA720 (ALDERLAKE_P)
[13:00:08] [PASSED] 0xA7A0 (ALDERLAKE_P)
[13:00:08] [PASSED] 0xA7A8 (ALDERLAKE_P)
[13:00:08] [PASSED] 0xA7AA (ALDERLAKE_P)
[13:00:08] [PASSED] 0xA7AB (ALDERLAKE_P)
[13:00:08] [PASSED] 0xA780 (ALDERLAKE_S)
[13:00:08] [PASSED] 0xA781 (ALDERLAKE_S)
[13:00:08] [PASSED] 0xA782 (ALDERLAKE_S)
[13:00:08] [PASSED] 0xA783 (ALDERLAKE_S)
[13:00:08] [PASSED] 0xA788 (ALDERLAKE_S)
[13:00:08] [PASSED] 0xA789 (ALDERLAKE_S)
[13:00:08] [PASSED] 0xA78A (ALDERLAKE_S)
[13:00:08] [PASSED] 0xA78B (ALDERLAKE_S)
[13:00:08] [PASSED] 0x4905 (DG1)
[13:00:08] [PASSED] 0x4906 (DG1)
[13:00:08] [PASSED] 0x4907 (DG1)
[13:00:08] [PASSED] 0x4908 (DG1)
[13:00:08] [PASSED] 0x4909 (DG1)
[13:00:08] [PASSED] 0x56C0 (DG2)
[13:00:08] [PASSED] 0x56C2 (DG2)
[13:00:08] [PASSED] 0x56C1 (DG2)
[13:00:08] [PASSED] 0x7D51 (METEORLAKE)
[13:00:08] [PASSED] 0x7DD1 (METEORLAKE)
[13:00:08] [PASSED] 0x7D41 (METEORLAKE)
[13:00:08] [PASSED] 0x7D67 (METEORLAKE)
[13:00:08] [PASSED] 0xB640 (METEORLAKE)
[13:00:08] [PASSED] 0x56A0 (DG2)
[13:00:08] [PASSED] 0x56A1 (DG2)
[13:00:08] [PASSED] 0x56A2 (DG2)
[13:00:08] [PASSED] 0x56BE (DG2)
[13:00:08] [PASSED] 0x56BF (DG2)
[13:00:08] [PASSED] 0x5690 (DG2)
[13:00:08] [PASSED] 0x5691 (DG2)
[13:00:08] [PASSED] 0x5692 (DG2)
[13:00:08] [PASSED] 0x56A5 (DG2)
[13:00:08] [PASSED] 0x56A6 (DG2)
[13:00:08] [PASSED] 0x56B0 (DG2)
[13:00:08] [PASSED] 0x56B1 (DG2)
[13:00:08] [PASSED] 0x56BA (DG2)
[13:00:08] [PASSED] 0x56BB (DG2)
[13:00:08] [PASSED] 0x56BC (DG2)
[13:00:08] [PASSED] 0x56BD (DG2)
[13:00:08] [PASSED] 0x5693 (DG2)
[13:00:08] [PASSED] 0x5694 (DG2)
[13:00:08] [PASSED] 0x5695 (DG2)
[13:00:08] [PASSED] 0x56A3 (DG2)
[13:00:08] [PASSED] 0x56A4 (DG2)
[13:00:08] [PASSED] 0x56B2 (DG2)
[13:00:08] [PASSED] 0x56B3 (DG2)
[13:00:08] [PASSED] 0x5696 (DG2)
[13:00:08] [PASSED] 0x5697 (DG2)
[13:00:08] [PASSED] 0xB69 (PVC)
[13:00:08] [PASSED] 0xB6E (PVC)
[13:00:08] [PASSED] 0xBD4 (PVC)
[13:00:08] [PASSED] 0xBD5 (PVC)
[13:00:08] [PASSED] 0xBD6 (PVC)
[13:00:08] [PASSED] 0xBD7 (PVC)
[13:00:08] [PASSED] 0xBD8 (PVC)
[13:00:08] [PASSED] 0xBD9 (PVC)
[13:00:08] [PASSED] 0xBDA (PVC)
[13:00:08] [PASSED] 0xBDB (PVC)
[13:00:08] [PASSED] 0xBE0 (PVC)
[13:00:08] [PASSED] 0xBE1 (PVC)
[13:00:08] [PASSED] 0xBE5 (PVC)
[13:00:08] [PASSED] 0x7D40 (METEORLAKE)
[13:00:08] [PASSED] 0x7D45 (METEORLAKE)
[13:00:08] [PASSED] 0x7D55 (METEORLAKE)
[13:00:08] [PASSED] 0x7D60 (METEORLAKE)
[13:00:08] [PASSED] 0x7DD5 (METEORLAKE)
[13:00:08] [PASSED] 0x6420 (LUNARLAKE)
[13:00:08] [PASSED] 0x64A0 (LUNARLAKE)
[13:00:08] [PASSED] 0x64B0 (LUNARLAKE)
[13:00:08] [PASSED] 0xE202 (BATTLEMAGE)
[13:00:08] [PASSED] 0xE209 (BATTLEMAGE)
[13:00:08] [PASSED] 0xE20B (BATTLEMAGE)
[13:00:08] [PASSED] 0xE20C (BATTLEMAGE)
[13:00:08] [PASSED] 0xE20D (BATTLEMAGE)
[13:00:08] [PASSED] 0xE210 (BATTLEMAGE)
[13:00:08] [PASSED] 0xE211 (BATTLEMAGE)
[13:00:08] [PASSED] 0xE212 (BATTLEMAGE)
[13:00:08] [PASSED] 0xE216 (BATTLEMAGE)
[13:00:08] [PASSED] 0xE220 (BATTLEMAGE)
[13:00:08] [PASSED] 0xE221 (BATTLEMAGE)
[13:00:08] [PASSED] 0xE222 (BATTLEMAGE)
[13:00:08] [PASSED] 0xE223 (BATTLEMAGE)
[13:00:08] [PASSED] 0xB080 (PANTHERLAKE)
[13:00:08] [PASSED] 0xB081 (PANTHERLAKE)
[13:00:08] [PASSED] 0xB082 (PANTHERLAKE)
[13:00:08] [PASSED] 0xB083 (PANTHERLAKE)
[13:00:08] [PASSED] 0xB084 (PANTHERLAKE)
[13:00:08] [PASSED] 0xB085 (PANTHERLAKE)
[13:00:08] [PASSED] 0xB086 (PANTHERLAKE)
[13:00:08] [PASSED] 0xB087 (PANTHERLAKE)
[13:00:08] [PASSED] 0xB08F (PANTHERLAKE)
[13:00:08] [PASSED] 0xB090 (PANTHERLAKE)
[13:00:08] [PASSED] 0xB0A0 (PANTHERLAKE)
[13:00:08] [PASSED] 0xB0B0 (PANTHERLAKE)
[13:00:08] [PASSED] 0xFD80 (PANTHERLAKE)
[13:00:08] [PASSED] 0xFD81 (PANTHERLAKE)
[13:00:08] [PASSED] 0xD740 (NOVALAKE_S)
[13:00:08] [PASSED] 0xD741 (NOVALAKE_S)
[13:00:08] [PASSED] 0xD742 (NOVALAKE_S)
[13:00:08] [PASSED] 0xD743 (NOVALAKE_S)
[13:00:08] [PASSED] 0xD745 (NOVALAKE_S)
[13:00:08] [PASSED] 0xD74A (NOVALAKE_S)
[13:00:08] [PASSED] 0xD74B (NOVALAKE_S)
[13:00:08] [PASSED] 0x674C (CRESCENTISLAND)
[13:00:08] [PASSED] 0x674D (CRESCENTISLAND)
[13:00:08] [PASSED] 0x674E (CRESCENTISLAND)
[13:00:08] [PASSED] 0x674F (CRESCENTISLAND)
[13:00:08] [PASSED] 0x6750 (CRESCENTISLAND)
[13:00:08] [PASSED] 0xD750 (NOVALAKE_P)
[13:00:08] [PASSED] 0xD751 (NOVALAKE_P)
[13:00:08] [PASSED] 0xD752 (NOVALAKE_P)
[13:00:08] [PASSED] 0xD753 (NOVALAKE_P)
[13:00:08] [PASSED] 0xD754 (NOVALAKE_P)
[13:00:08] [PASSED] 0xD755 (NOVALAKE_P)
[13:00:08] [PASSED] 0xD756 (NOVALAKE_P)
[13:00:08] [PASSED] 0xD757 (NOVALAKE_P)
[13:00:08] [PASSED] 0xD75F (NOVALAKE_P)
[13:00:08] =============== [PASSED] check_platform_desc ===============
[13:00:08] ===================== [PASSED] xe_pci ======================
[13:00:08] ============= xe_rtp_tables_test (5 subtests) ==============
[13:00:08] ================== xe_rtp_table_gt_test ===================
[13:00:08] [PASSED] gt_was/14011060649
[13:00:08] [PASSED] gt_was/14011059788
[13:00:08] [PASSED] gt_was/14015795083
[13:00:08] [PASSED] gt_was/16021867713
[13:00:08] [PASSED] gt_was/14019449301
[13:00:08] [PASSED] gt_was/16028005424
[13:00:08] [PASSED] gt_was/14026578760
[13:00:08] [PASSED] gt_was/1409420604
[13:00:08] [PASSED] gt_was/1408615072
[13:00:08] [PASSED] gt_was/22010523718
[13:00:08] [PASSED] gt_was/14011006942
[13:00:08] [PASSED] gt_was/14014830051
[13:00:08] [PASSED] gt_was/18018781329
[13:00:08] [PASSED] gt_was/1509235366
[13:00:08] [PASSED] gt_was/18018781329
[13:00:08] [PASSED] gt_was/16016694945
[13:00:08] [PASSED] gt_was/14018575942
[13:00:08] [PASSED] gt_was/22016670082
[13:00:08] [PASSED] gt_was/22016670082
[13:00:08] [PASSED] gt_was/14017421178
[13:00:08] [PASSED] gt_was/16025250150
[13:00:08] [PASSED] gt_was/14021871409
[13:00:08] [PASSED] gt_was/16021865536
[13:00:08] [PASSED] gt_was/14021486841
[13:00:08] [PASSED] gt_was/14025160223
[13:00:08] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[13:00:08] [PASSED] gt_was/14025635424
[13:00:08] [PASSED] gt_was/16028005424
[13:00:08] ============== [PASSED] xe_rtp_table_gt_test ===============
[13:00:08] ================== xe_rtp_table_gt_test ===================
[13:00:08] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[13:00:08] [PASSED] gt_tunings/Tuning: 32B Access Enable
[13:00:08] [PASSED] gt_tunings/Tuning: L3 cache
[13:00:08] [PASSED] gt_tunings/Tuning: L3 cache - media
[13:00:08] [PASSED] gt_tunings/Tuning: Compression Overfetch
[13:00:08] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[13:00:08] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[13:00:08] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[13:00:08] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[13:00:08] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[13:00:08] [PASSED] gt_tunings/Tuning: Stateless compression control
[13:00:08] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[13:00:08] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[13:00:08] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[13:00:08] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[13:00:08] ============== [PASSED] xe_rtp_table_gt_test ===============
[13:00:08] ================== xe_rtp_table_oob_test ==================
[13:00:08] [PASSED] oob_was/1607983814
[13:00:08] [PASSED] oob_was/16010904313
[13:00:08] [PASSED] oob_was/18022495364
[13:00:08] [PASSED] oob_was/22012773006
[13:00:08] [PASSED] oob_was/14014475959
[13:00:08] [PASSED] oob_was/22011391025
[13:00:08] [PASSED] oob_was/22012727170
[13:00:08] [PASSED] oob_was/22012727685
[13:00:08] [PASSED] oob_was/22016596838
[13:00:08] [PASSED] oob_was/18020744125
[13:00:08] [PASSED] oob_was/1409600907
[13:00:08] [PASSED] oob_was/22014953428
[13:00:08] [PASSED] oob_was/16017236439
[13:00:08] [PASSED] oob_was/14019821291
[13:00:08] [PASSED] oob_was/14015076503
[13:00:08] [PASSED] oob_was/14018913170
[13:00:08] [PASSED] oob_was/14018094691
[13:00:08] [PASSED] oob_was/18024947630
[13:00:08] [PASSED] oob_was/16022287689
[13:00:08] [PASSED] oob_was/13011645652
[13:00:08] [PASSED] oob_was/14022293748
[13:00:08] [PASSED] oob_was/22019794406
[13:00:08] [PASSED] oob_was/22019338487
[13:00:08] [PASSED] oob_was/16023588340
[13:00:08] [PASSED] oob_was/14019789679
[13:00:08] [PASSED] oob_was/14022866841
[13:00:08] [PASSED] oob_was/16021333562
[13:00:08] [PASSED] oob_was/14016712196
[13:00:08] [PASSED] oob_was/14015568240
[13:00:08] [PASSED] oob_was/18013179988
[13:00:08] [PASSED] oob_was/1508761755
[13:00:08] [PASSED] oob_was/16023105232
[13:00:08] [PASSED] oob_was/16026508708
[13:00:08] [PASSED] oob_was/14020001231
[13:00:08] [PASSED] oob_was/16023683509
[13:00:08] [PASSED] oob_was/14025515070
[13:00:08] [PASSED] oob_was/15015404425_disable
[13:00:08] [PASSED] oob_was/16026007364
[13:00:08] [PASSED] oob_was/14020316580
[13:00:08] [PASSED] oob_was/14025883347
[13:00:08] [PASSED] oob_was/16029380221
[13:00:08] [PASSED] oob_was/22022079272
[13:00:08] [PASSED] oob_was/16029897822
[13:00:08] [PASSED] oob_was/14027054324
[13:00:08] ============== [PASSED] xe_rtp_table_oob_test ==============
[13:00:08] ================ xe_rtp_table_dev_oob_test ================
[13:00:08] [PASSED] device_oob_was/22010954014
[13:00:08] [PASSED] device_oob_was/15015404425
[13:00:08] [PASSED] device_oob_was/22019338487_display
[13:00:08] [PASSED] device_oob_was/14022085890
[13:00:08] [PASSED] device_oob_was/14026539277
[13:00:08] [PASSED] device_oob_was/14026633728
[13:00:08] [PASSED] device_oob_was/14026746987
[13:00:08] [PASSED] device_oob_was/14026779378
[13:00:08] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[13:00:08] ========== xe_rtp_table_missing_upper_bound_test ==========
[13:00:08] [PASSED] register_whitelist/WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865
[13:00:08] [PASSED] register_whitelist/1508744258, 14012131227, 1808121037
[13:00:08] [PASSED] register_whitelist/1806527549
[13:00:08] [PASSED] register_whitelist/allow_read_ctx_timestamp
[13:00:08] [PASSED] register_whitelist/allow_read_queue_timestamp
[13:00:08] [PASSED] register_whitelist/16014440446
[13:00:08] [PASSED] register_whitelist/16017236439
[13:00:08] [PASSED] register_whitelist/16020183090
[13:00:08] [PASSED] register_whitelist/14024997852
[13:00:08] [PASSED] register_whitelist/14024997852
[13:00:08] ====== [PASSED] xe_rtp_table_missing_upper_bound_test ======
[13:00:08] =============== [PASSED] xe_rtp_tables_test ================
[13:00:08] =================== xe_rtp (3 subtests) ====================
[13:00:08] =================== xe_rtp_rules_tests ====================
[13:00:08] [PASSED] no
[13:00:08] [PASSED] yes
[13:00:08] [PASSED] no-and-no
[13:00:08] [PASSED] no-and-yes
[13:00:08] [PASSED] yes-and-no
[13:00:08] [PASSED] yes-and-yes
[13:00:08] [PASSED] no-or-no
[13:00:08] [PASSED] no-or-yes
[13:00:08] [PASSED] yes-or-no
[13:00:08] [PASSED] yes-or-yes
[13:00:08] [PASSED] no-yes-or-yes-no
[13:00:08] [PASSED] no-yes-or-yes-yes
[13:00:08] [PASSED] yes-yes-or-no-yes
[13:00:08] [PASSED] yes-yes-or-yes-yes
[13:00:08] [PASSED] no-no-or-yes-or-no
[13:00:08] [PASSED] or
[13:00:08] [PASSED] or-yes
[13:00:08] [PASSED] or-no
[13:00:08] [PASSED] yes-or
[13:00:08] [PASSED] no-or
[13:00:08] [PASSED] no-or-or-yes
[13:00:08] [PASSED] yes-or-or-no
[13:00:08] [PASSED] no-or-or-no
[13:00:08] [PASSED] missing-context-engine-class
[13:00:08] [PASSED] missing-context-engine-class-or-yes
[13:00:08] [PASSED] missing-context-engine-class-or-or-yes
[13:00:08] =============== [PASSED] xe_rtp_rules_tests ================
[13:00:08] =============== xe_rtp_process_to_sr_tests ================
[13:00:08] [PASSED] coalesce-same-reg
[13:00:08] [PASSED] coalesce-same-reg-literal-and-func
[13:00:08] [PASSED] no-match-no-add
[13:00:08] [PASSED] two-regs-two-entries
[13:00:08] [PASSED] clr-one-set-other
[13:00:08] [PASSED] set-field
[13:00:08] [PASSED] conflict-duplicate
[13:00:08] [PASSED] conflict-not-disjoint
[13:00:08] [PASSED] conflict-not-disjoint-literal-and-func
[13:00:08] [PASSED] conflict-reg-type
[13:00:08] [PASSED] bad-mcr-reg-forced-to-regular
[13:00:08] [PASSED] bad-regular-reg-forced-to-mcr
[13:00:08] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[13:00:08] ================== xe_rtp_process_tests ===================
[13:00:08] [PASSED] active1
[13:00:08] [PASSED] active2
[13:00:08] [PASSED] active-inactive
[13:00:08] [PASSED] inactive-active
[13:00:08] [PASSED] inactive-active-inactive
[13:00:08] [PASSED] inactive-inactive-inactive
[13:00:08] ============== [PASSED] xe_rtp_process_tests ===============
[13:00:08] ===================== [PASSED] xe_rtp ======================
[13:00:08] ==================== xe_wa (1 subtest) =====================
[13:00:08] ======================== xe_wa_gt =========================
[13:00:08] [PASSED] TIGERLAKE B0
[13:00:08] [PASSED] DG1 A0
[13:00:08] [PASSED] DG1 B0
[13:00:08] [PASSED] ALDERLAKE_S A0
[13:00:08] [PASSED] ALDERLAKE_S B0
[13:00:08] [PASSED] ALDERLAKE_S C0
[13:00:08] [PASSED] ALDERLAKE_S D0
[13:00:08] [PASSED] ALDERLAKE_P A0
[13:00:08] [PASSED] ALDERLAKE_P B0
[13:00:08] [PASSED] ALDERLAKE_P C0
[13:00:08] [PASSED] ALDERLAKE_S RPLS D0
[13:00:08] [PASSED] ALDERLAKE_P RPLU E0
[13:00:08] [PASSED] DG2 G10 C0
[13:00:08] [PASSED] DG2 G11 B1
[13:00:08] [PASSED] DG2 G12 A1
[13:00:08] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[13:00:08] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[13:00:08] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[13:00:08] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[13:00:08] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[13:00:08] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[13:00:08] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[13:00:08] ==================== [PASSED] xe_wa_gt =====================
[13:00:08] ====================== [PASSED] xe_wa ======================
[13:00:08] ============================================================
[13:00:08] Testing complete. Ran 789 tests: passed: 761, skipped: 28
[13:00:08] Elapsed time: 36.817s total, 4.362s configuring, 31.739s building, 0.682s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[13:00:08] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[13:00:10] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[13:00:34] Starting KUnit Kernel (1/1)...
[13:00:34] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[13:00:34] ============ drm_test_pick_cmdline (2 subtests) ============
[13:00:34] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[13:00:34] =============== drm_test_pick_cmdline_named ===============
[13:00:34] [PASSED] NTSC
[13:00:34] [PASSED] NTSC-J
[13:00:34] [PASSED] PAL
[13:00:34] [PASSED] PAL-M
[13:00:34] =========== [PASSED] drm_test_pick_cmdline_named ===========
[13:00:34] ============== [PASSED] drm_test_pick_cmdline ==============
[13:00:34] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[13:00:34] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[13:00:34] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[13:00:34] =========== drm_validate_clone_mode (2 subtests) ===========
[13:00:34] ============== drm_test_check_in_clone_mode ===============
[13:00:34] [PASSED] in_clone_mode
[13:00:34] [PASSED] not_in_clone_mode
[13:00:34] ========== [PASSED] drm_test_check_in_clone_mode ===========
[13:00:34] =============== drm_test_check_valid_clones ===============
[13:00:34] [PASSED] not_in_clone_mode
[13:00:34] [PASSED] valid_clone
[13:00:34] [PASSED] invalid_clone
[13:00:34] =========== [PASSED] drm_test_check_valid_clones ===========
[13:00:34] ============= [PASSED] drm_validate_clone_mode =============
[13:00:34] ============= drm_validate_modeset (1 subtest) =============
[13:00:34] [PASSED] drm_test_check_connector_changed_modeset
[13:00:34] ============== [PASSED] drm_validate_modeset ===============
[13:00:34] ====== drm_test_bridge_get_current_state (1 subtest) =======
[13:00:34] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[13:00:34] ======== [PASSED] drm_test_bridge_get_current_state ========
[13:00:34] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[13:00:34] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[13:00:34] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[13:00:34] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[13:00:34] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[13:00:34] ============== drm_bridge_alloc (2 subtests) ===============
[13:00:34] [PASSED] drm_test_drm_bridge_alloc_basic
[13:00:34] [PASSED] drm_test_drm_bridge_alloc_get_put
[13:00:34] ================ [PASSED] drm_bridge_alloc =================
[13:00:34] ============= drm_bridge_bus_fmt (5 subtests) ==============
[13:00:34] [PASSED] drm_test_bridge_rgb_yuv_rgb
[13:00:34] [PASSED] drm_test_bridge_must_convert_to_yuv444
[13:00:34] [PASSED] drm_test_bridge_hdmi_auto_rgb
[13:00:34] [PASSED] drm_test_bridge_auto_first
[13:00:34] [PASSED] drm_test_bridge_rgb_yuv_no_path
[13:00:34] =============== [PASSED] drm_bridge_bus_fmt ================
[13:00:34] ============= drm_cmdline_parser (40 subtests) =============
[13:00:34] [PASSED] drm_test_cmdline_force_d_only
[13:00:34] [PASSED] drm_test_cmdline_force_D_only_dvi
[13:00:34] [PASSED] drm_test_cmdline_force_D_only_hdmi
[13:00:34] [PASSED] drm_test_cmdline_force_D_only_not_digital
[13:00:34] [PASSED] drm_test_cmdline_force_e_only
[13:00:34] [PASSED] drm_test_cmdline_res
[13:00:34] [PASSED] drm_test_cmdline_res_vesa
[13:00:34] [PASSED] drm_test_cmdline_res_vesa_rblank
[13:00:34] [PASSED] drm_test_cmdline_res_rblank
[13:00:34] [PASSED] drm_test_cmdline_res_bpp
[13:00:34] [PASSED] drm_test_cmdline_res_refresh
[13:00:34] [PASSED] drm_test_cmdline_res_bpp_refresh
[13:00:34] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[13:00:34] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[13:00:34] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[13:00:34] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[13:00:34] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[13:00:34] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[13:00:34] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[13:00:34] [PASSED] drm_test_cmdline_res_margins_force_on
[13:00:34] [PASSED] drm_test_cmdline_res_vesa_margins
[13:00:34] [PASSED] drm_test_cmdline_name
[13:00:34] [PASSED] drm_test_cmdline_name_bpp
[13:00:34] [PASSED] drm_test_cmdline_name_option
[13:00:34] [PASSED] drm_test_cmdline_name_bpp_option
[13:00:34] [PASSED] drm_test_cmdline_rotate_0
[13:00:34] [PASSED] drm_test_cmdline_rotate_90
[13:00:34] [PASSED] drm_test_cmdline_rotate_180
[13:00:34] [PASSED] drm_test_cmdline_rotate_270
[13:00:34] [PASSED] drm_test_cmdline_hmirror
[13:00:34] [PASSED] drm_test_cmdline_vmirror
[13:00:34] [PASSED] drm_test_cmdline_margin_options
[13:00:34] [PASSED] drm_test_cmdline_multiple_options
[13:00:34] [PASSED] drm_test_cmdline_bpp_extra_and_option
[13:00:34] [PASSED] drm_test_cmdline_extra_and_option
[13:00:34] [PASSED] drm_test_cmdline_freestanding_options
[13:00:34] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[13:00:34] [PASSED] drm_test_cmdline_panel_orientation
[13:00:34] ================ drm_test_cmdline_invalid =================
[13:00:34] [PASSED] margin_only
[13:00:34] [PASSED] interlace_only
[13:00:34] [PASSED] res_missing_x
[13:00:34] [PASSED] res_missing_y
[13:00:34] [PASSED] res_bad_y
[13:00:34] [PASSED] res_missing_y_bpp
[13:00:34] [PASSED] res_bad_bpp
[13:00:34] [PASSED] res_bad_refresh
[13:00:34] [PASSED] res_bpp_refresh_force_on_off
[13:00:34] [PASSED] res_invalid_mode
[13:00:34] [PASSED] res_bpp_wrong_place_mode
[13:00:34] [PASSED] name_bpp_refresh
[13:00:34] [PASSED] name_refresh
[13:00:34] [PASSED] name_refresh_wrong_mode
[13:00:34] [PASSED] name_refresh_invalid_mode
[13:00:34] [PASSED] rotate_multiple
[13:00:34] [PASSED] rotate_invalid_val
[13:00:34] [PASSED] rotate_truncated
[13:00:34] [PASSED] invalid_option
[13:00:34] [PASSED] invalid_tv_option
[13:00:34] [PASSED] truncated_tv_option
[13:00:34] ============ [PASSED] drm_test_cmdline_invalid =============
[13:00:34] =============== drm_test_cmdline_tv_options ===============
[13:00:34] [PASSED] NTSC
[13:00:34] [PASSED] NTSC_443
[13:00:34] [PASSED] NTSC_J
[13:00:34] [PASSED] PAL
[13:00:34] [PASSED] PAL_M
[13:00:34] [PASSED] PAL_N
[13:00:34] [PASSED] SECAM
[13:00:34] [PASSED] MONO_525
[13:00:34] [PASSED] MONO_625
[13:00:34] =========== [PASSED] drm_test_cmdline_tv_options ===========
[13:00:34] =============== [PASSED] drm_cmdline_parser ================
[13:00:34] ========== drmm_connector_hdmi_init (20 subtests) ==========
[13:00:34] [PASSED] drm_test_connector_hdmi_init_valid
[13:00:34] [PASSED] drm_test_connector_hdmi_init_bpc_8
[13:00:34] [PASSED] drm_test_connector_hdmi_init_bpc_10
[13:00:34] [PASSED] drm_test_connector_hdmi_init_bpc_12
[13:00:34] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[13:00:34] [PASSED] drm_test_connector_hdmi_init_bpc_null
[13:00:34] [PASSED] drm_test_connector_hdmi_init_formats_empty
[13:00:34] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[13:00:34] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[13:00:34] [PASSED] supported_formats=0x9 yuv420_allowed=1
[13:00:34] [PASSED] supported_formats=0x9 yuv420_allowed=0
[13:00:34] [PASSED] supported_formats=0x5 yuv420_allowed=1
[13:00:34] [PASSED] supported_formats=0x5 yuv420_allowed=0
[13:00:34] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[13:00:34] [PASSED] drm_test_connector_hdmi_init_null_ddc
[13:00:34] [PASSED] drm_test_connector_hdmi_init_null_product
[13:00:34] [PASSED] drm_test_connector_hdmi_init_null_vendor
[13:00:34] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[13:00:34] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[13:00:34] [PASSED] drm_test_connector_hdmi_init_product_valid
[13:00:34] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[13:00:34] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[13:00:34] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[13:00:34] ========= drm_test_connector_hdmi_init_type_valid =========
[13:00:34] [PASSED] HDMI-A
[13:00:34] [PASSED] HDMI-B
[13:00:34] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[13:00:34] ======== drm_test_connector_hdmi_init_type_invalid ========
[13:00:34] [PASSED] Unknown
[13:00:34] [PASSED] VGA
[13:00:34] [PASSED] DVI-I
[13:00:34] [PASSED] DVI-D
[13:00:34] [PASSED] DVI-A
[13:00:34] [PASSED] Composite
[13:00:34] [PASSED] SVIDEO
[13:00:34] [PASSED] LVDS
[13:00:34] [PASSED] Component
[13:00:34] [PASSED] DIN
[13:00:34] [PASSED] DP
[13:00:34] [PASSED] TV
[13:00:34] [PASSED] eDP
[13:00:34] [PASSED] Virtual
[13:00:34] [PASSED] DSI
[13:00:34] [PASSED] DPI
[13:00:34] [PASSED] Writeback
[13:00:34] [PASSED] SPI
[13:00:34] [PASSED] USB
[13:00:34] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[13:00:34] ============ [PASSED] drmm_connector_hdmi_init =============
[13:00:34] ============= drmm_connector_init (3 subtests) =============
[13:00:34] [PASSED] drm_test_drmm_connector_init
[13:00:34] [PASSED] drm_test_drmm_connector_init_null_ddc
[13:00:34] ========= drm_test_drmm_connector_init_type_valid =========
[13:00:34] [PASSED] Unknown
[13:00:34] [PASSED] VGA
[13:00:34] [PASSED] DVI-I
[13:00:34] [PASSED] DVI-D
[13:00:34] [PASSED] DVI-A
[13:00:34] [PASSED] Composite
[13:00:34] [PASSED] SVIDEO
[13:00:34] [PASSED] LVDS
[13:00:34] [PASSED] Component
[13:00:34] [PASSED] DIN
[13:00:34] [PASSED] DP
[13:00:34] [PASSED] HDMI-A
[13:00:34] [PASSED] HDMI-B
[13:00:34] [PASSED] TV
[13:00:34] [PASSED] eDP
[13:00:34] [PASSED] Virtual
[13:00:34] [PASSED] DSI
[13:00:34] [PASSED] DPI
[13:00:34] [PASSED] Writeback
[13:00:34] [PASSED] SPI
[13:00:34] [PASSED] USB
[13:00:34] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[13:00:34] =============== [PASSED] drmm_connector_init ===============
[13:00:34] ========= drm_connector_dynamic_init (6 subtests) ==========
[13:00:34] [PASSED] drm_test_drm_connector_dynamic_init
[13:00:34] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[13:00:34] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[13:00:34] [PASSED] drm_test_drm_connector_dynamic_init_properties
[13:00:34] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[13:00:34] [PASSED] Unknown
[13:00:34] [PASSED] VGA
[13:00:34] [PASSED] DVI-I
[13:00:34] [PASSED] DVI-D
[13:00:34] [PASSED] DVI-A
[13:00:34] [PASSED] Composite
[13:00:34] [PASSED] SVIDEO
[13:00:34] [PASSED] LVDS
[13:00:34] [PASSED] Component
[13:00:34] [PASSED] DIN
[13:00:34] [PASSED] DP
[13:00:34] [PASSED] HDMI-A
[13:00:34] [PASSED] HDMI-B
[13:00:34] [PASSED] TV
[13:00:34] [PASSED] eDP
[13:00:34] [PASSED] Virtual
[13:00:34] [PASSED] DSI
[13:00:34] [PASSED] DPI
[13:00:34] [PASSED] Writeback
[13:00:34] [PASSED] SPI
[13:00:34] [PASSED] USB
[13:00:34] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[13:00:34] ======== drm_test_drm_connector_dynamic_init_name =========
[13:00:34] [PASSED] Unknown
[13:00:34] [PASSED] VGA
[13:00:34] [PASSED] DVI-I
[13:00:34] [PASSED] DVI-D
[13:00:34] [PASSED] DVI-A
[13:00:34] [PASSED] Composite
[13:00:34] [PASSED] SVIDEO
[13:00:34] [PASSED] LVDS
[13:00:34] [PASSED] Component
[13:00:34] [PASSED] DIN
[13:00:34] [PASSED] DP
[13:00:34] [PASSED] HDMI-A
[13:00:34] [PASSED] HDMI-B
[13:00:34] [PASSED] TV
[13:00:34] [PASSED] eDP
[13:00:34] [PASSED] Virtual
[13:00:34] [PASSED] DSI
[13:00:34] [PASSED] DPI
[13:00:34] [PASSED] Writeback
[13:00:34] [PASSED] SPI
[13:00:34] [PASSED] USB
[13:00:34] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[13:00:34] =========== [PASSED] drm_connector_dynamic_init ============
[13:00:34] ==== drm_connector_dynamic_register_early (4 subtests) =====
[13:00:34] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[13:00:34] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[13:00:34] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[13:00:34] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[13:00:34] ====== [PASSED] drm_connector_dynamic_register_early =======
[13:00:34] ======= drm_connector_dynamic_register (7 subtests) ========
[13:00:34] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[13:00:34] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[13:00:34] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[13:00:34] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[13:00:34] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[13:00:34] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[13:00:34] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[13:00:34] ========= [PASSED] drm_connector_dynamic_register ==========
[13:00:34] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[13:00:34] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[13:00:34] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[13:00:34] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[13:00:34] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[13:00:34] ========== drm_test_get_tv_mode_from_name_valid ===========
[13:00:34] [PASSED] NTSC
[13:00:34] [PASSED] NTSC-443
[13:00:34] [PASSED] NTSC-J
[13:00:34] [PASSED] PAL
[13:00:34] [PASSED] PAL-M
[13:00:34] [PASSED] PAL-N
[13:00:34] [PASSED] SECAM
[13:00:34] [PASSED] Mono
[13:00:34] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[13:00:34] [PASSED] drm_test_get_tv_mode_from_name_truncated
[13:00:34] ============ [PASSED] drm_get_tv_mode_from_name ============
[13:00:34] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[13:00:34] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[13:00:34] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[13:00:34] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[13:00:34] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[13:00:34] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[13:00:34] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[13:00:34] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[13:00:34] [PASSED] VIC 96
[13:00:34] [PASSED] VIC 97
[13:00:34] [PASSED] VIC 101
[13:00:34] [PASSED] VIC 102
[13:00:34] [PASSED] VIC 106
[13:00:34] [PASSED] VIC 107
[13:00:34] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[13:00:34] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[13:00:34] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[13:00:34] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[13:00:34] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[13:00:34] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[13:00:34] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[13:00:34] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[13:00:34] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[13:00:34] [PASSED] Automatic
[13:00:34] [PASSED] Full
[13:00:34] [PASSED] Limited 16:235
[13:00:34] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[13:00:34] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[13:00:34] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[13:00:34] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[13:00:34] === drm_test_drm_hdmi_connector_get_output_format_name ====
[13:00:34] [PASSED] RGB
[13:00:34] [PASSED] YUV 4:2:0
[13:00:34] [PASSED] YUV 4:2:2
[13:00:34] [PASSED] YUV 4:4:4
[13:00:34] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[13:00:34] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[13:00:34] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[13:00:34] ============= drm_damage_helper (21 subtests) ==============
[13:00:34] [PASSED] drm_test_damage_iter_no_damage
[13:00:34] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[13:00:34] [PASSED] drm_test_damage_iter_no_damage_src_moved
[13:00:34] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[13:00:34] [PASSED] drm_test_damage_iter_no_damage_not_visible
[13:00:34] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[13:00:34] [PASSED] drm_test_damage_iter_no_damage_no_fb
[13:00:34] [PASSED] drm_test_damage_iter_simple_damage
[13:00:34] [PASSED] drm_test_damage_iter_single_damage
[13:00:34] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[13:00:34] [PASSED] drm_test_damage_iter_single_damage_outside_src
[13:00:34] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[13:00:34] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[13:00:34] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[13:00:34] [PASSED] drm_test_damage_iter_single_damage_src_moved
[13:00:34] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[13:00:34] [PASSED] drm_test_damage_iter_damage
[13:00:34] [PASSED] drm_test_damage_iter_damage_one_intersect
[13:00:34] [PASSED] drm_test_damage_iter_damage_one_outside
[13:00:34] [PASSED] drm_test_damage_iter_damage_src_moved
[13:00:34] [PASSED] drm_test_damage_iter_damage_not_visible
[13:00:34] ================ [PASSED] drm_damage_helper ================
[13:00:34] ============== drm_dp_mst_helper (3 subtests) ==============
[13:00:34] ============== drm_test_dp_mst_calc_pbn_mode ==============
[13:00:34] [PASSED] Clock 154000 BPP 30 DSC disabled
[13:00:34] [PASSED] Clock 234000 BPP 30 DSC disabled
[13:00:34] [PASSED] Clock 297000 BPP 24 DSC disabled
[13:00:34] [PASSED] Clock 332880 BPP 24 DSC enabled
[13:00:34] [PASSED] Clock 324540 BPP 24 DSC enabled
[13:00:34] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[13:00:34] ============== drm_test_dp_mst_calc_pbn_div ===============
[13:00:34] [PASSED] Link rate 2000000 lane count 4
[13:00:34] [PASSED] Link rate 2000000 lane count 2
[13:00:34] [PASSED] Link rate 2000000 lane count 1
[13:00:34] [PASSED] Link rate 1350000 lane count 4
[13:00:34] [PASSED] Link rate 1350000 lane count 2
[13:00:34] [PASSED] Link rate 1350000 lane count 1
[13:00:34] [PASSED] Link rate 1000000 lane count 4
[13:00:34] [PASSED] Link rate 1000000 lane count 2
[13:00:34] [PASSED] Link rate 1000000 lane count 1
[13:00:34] [PASSED] Link rate 810000 lane count 4
[13:00:34] [PASSED] Link rate 810000 lane count 2
[13:00:34] [PASSED] Link rate 810000 lane count 1
[13:00:34] [PASSED] Link rate 540000 lane count 4
[13:00:34] [PASSED] Link rate 540000 lane count 2
[13:00:34] [PASSED] Link rate 540000 lane count 1
[13:00:34] [PASSED] Link rate 270000 lane count 4
[13:00:34] [PASSED] Link rate 270000 lane count 2
[13:00:34] [PASSED] Link rate 270000 lane count 1
[13:00:34] [PASSED] Link rate 162000 lane count 4
[13:00:34] [PASSED] Link rate 162000 lane count 2
[13:00:34] [PASSED] Link rate 162000 lane count 1
[13:00:34] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[13:00:34] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[13:00:34] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[13:00:34] [PASSED] DP_POWER_UP_PHY with port number
[13:00:34] [PASSED] DP_POWER_DOWN_PHY with port number
[13:00:34] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[13:00:34] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[13:00:34] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[13:00:34] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[13:00:34] [PASSED] DP_QUERY_PAYLOAD with port number
[13:00:34] [PASSED] DP_QUERY_PAYLOAD with VCPI
[13:00:34] [PASSED] DP_REMOTE_DPCD_READ with port number
[13:00:34] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[13:00:34] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[13:00:34] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[13:00:34] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[13:00:34] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[13:00:34] [PASSED] DP_REMOTE_I2C_READ with port number
[13:00:34] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[13:00:34] [PASSED] DP_REMOTE_I2C_READ with transactions array
[13:00:34] [PASSED] DP_REMOTE_I2C_WRITE with port number
[13:00:34] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[13:00:34] [PASSED] DP_REMOTE_I2C_WRITE with data array
[13:00:34] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[13:00:34] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[13:00:34] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[13:00:34] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[13:00:34] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[13:00:34] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[13:00:34] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[13:00:34] ================ [PASSED] drm_dp_mst_helper ================
[13:00:34] ================== drm_exec (7 subtests) ===================
[13:00:34] [PASSED] sanitycheck
[13:00:34] [PASSED] test_lock
[13:00:34] [PASSED] test_lock_unlock
[13:00:34] [PASSED] test_duplicates
[13:00:34] [PASSED] test_prepare
[13:00:34] [PASSED] test_prepare_array
[13:00:34] [PASSED] test_multiple_loops
[13:00:34] ==================== [PASSED] drm_exec =====================
[13:00:34] =========== drm_format_helper_test (17 subtests) ===========
[13:00:34] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[13:00:34] [PASSED] single_pixel_source_buffer
[13:00:34] [PASSED] single_pixel_clip_rectangle
[13:00:34] [PASSED] well_known_colors
[13:00:34] [PASSED] destination_pitch
[13:00:34] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[13:00:34] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[13:00:34] [PASSED] single_pixel_source_buffer
[13:00:34] [PASSED] single_pixel_clip_rectangle
[13:00:34] [PASSED] well_known_colors
[13:00:34] [PASSED] destination_pitch
[13:00:34] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[13:00:34] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[13:00:34] [PASSED] single_pixel_source_buffer
[13:00:34] [PASSED] single_pixel_clip_rectangle
[13:00:34] [PASSED] well_known_colors
[13:00:34] [PASSED] destination_pitch
[13:00:34] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[13:00:34] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[13:00:34] [PASSED] single_pixel_source_buffer
[13:00:34] [PASSED] single_pixel_clip_rectangle
[13:00:34] [PASSED] well_known_colors
[13:00:34] [PASSED] destination_pitch
[13:00:34] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[13:00:34] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[13:00:34] [PASSED] single_pixel_source_buffer
[13:00:34] [PASSED] single_pixel_clip_rectangle
[13:00:34] [PASSED] well_known_colors
[13:00:34] [PASSED] destination_pitch
[13:00:34] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[13:00:34] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[13:00:34] [PASSED] single_pixel_source_buffer
[13:00:34] [PASSED] single_pixel_clip_rectangle
[13:00:34] [PASSED] well_known_colors
[13:00:34] [PASSED] destination_pitch
[13:00:34] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[13:00:34] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[13:00:34] [PASSED] single_pixel_source_buffer
[13:00:34] [PASSED] single_pixel_clip_rectangle
[13:00:34] [PASSED] well_known_colors
[13:00:34] [PASSED] destination_pitch
[13:00:34] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[13:00:34] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[13:00:34] [PASSED] single_pixel_source_buffer
[13:00:34] [PASSED] single_pixel_clip_rectangle
[13:00:34] [PASSED] well_known_colors
[13:00:34] [PASSED] destination_pitch
[13:00:34] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[13:00:34] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[13:00:34] [PASSED] single_pixel_source_buffer
[13:00:34] [PASSED] single_pixel_clip_rectangle
[13:00:34] [PASSED] well_known_colors
[13:00:34] [PASSED] destination_pitch
[13:00:34] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[13:00:34] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[13:00:34] [PASSED] single_pixel_source_buffer
[13:00:34] [PASSED] single_pixel_clip_rectangle
[13:00:34] [PASSED] well_known_colors
[13:00:34] [PASSED] destination_pitch
[13:00:34] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[13:00:34] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[13:00:34] [PASSED] single_pixel_source_buffer
[13:00:34] [PASSED] single_pixel_clip_rectangle
[13:00:34] [PASSED] well_known_colors
[13:00:34] [PASSED] destination_pitch
[13:00:34] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[13:00:34] ============== drm_test_fb_xrgb8888_to_mono ===============
[13:00:34] [PASSED] single_pixel_source_buffer
[13:00:34] [PASSED] single_pixel_clip_rectangle
[13:00:34] [PASSED] well_known_colors
[13:00:34] [PASSED] destination_pitch
[13:00:34] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[13:00:34] ==================== drm_test_fb_swab =====================
[13:00:34] [PASSED] single_pixel_source_buffer
[13:00:34] [PASSED] single_pixel_clip_rectangle
[13:00:34] [PASSED] well_known_colors
[13:00:34] [PASSED] destination_pitch
[13:00:34] ================ [PASSED] drm_test_fb_swab =================
[13:00:34] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[13:00:34] [PASSED] single_pixel_source_buffer
[13:00:34] [PASSED] single_pixel_clip_rectangle
[13:00:34] [PASSED] well_known_colors
[13:00:34] [PASSED] destination_pitch
[13:00:34] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[13:00:34] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[13:00:34] [PASSED] single_pixel_source_buffer
[13:00:34] [PASSED] single_pixel_clip_rectangle
[13:00:34] [PASSED] well_known_colors
[13:00:34] [PASSED] destination_pitch
[13:00:34] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[13:00:34] ================= drm_test_fb_clip_offset =================
[13:00:34] [PASSED] pass through
[13:00:34] [PASSED] horizontal offset
[13:00:34] [PASSED] vertical offset
[13:00:34] [PASSED] horizontal and vertical offset
[13:00:34] [PASSED] horizontal offset (custom pitch)
[13:00:34] [PASSED] vertical offset (custom pitch)
[13:00:34] [PASSED] horizontal and vertical offset (custom pitch)
[13:00:34] ============= [PASSED] drm_test_fb_clip_offset =============
[13:00:34] =================== drm_test_fb_memcpy ====================
[13:00:34] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[13:00:34] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[13:00:34] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[13:00:34] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[13:00:34] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[13:00:34] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[13:00:34] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[13:00:34] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[13:00:34] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[13:00:34] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[13:00:34] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[13:00:34] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[13:00:34] =============== [PASSED] drm_test_fb_memcpy ================
[13:00:34] ============= [PASSED] drm_format_helper_test ==============
[13:00:34] ================= drm_format (18 subtests) =================
[13:00:34] [PASSED] drm_test_format_block_width_invalid
[13:00:34] [PASSED] drm_test_format_block_width_one_plane
[13:00:34] [PASSED] drm_test_format_block_width_two_plane
[13:00:34] [PASSED] drm_test_format_block_width_three_plane
[13:00:34] [PASSED] drm_test_format_block_width_tiled
[13:00:34] [PASSED] drm_test_format_block_height_invalid
[13:00:34] [PASSED] drm_test_format_block_height_one_plane
[13:00:34] [PASSED] drm_test_format_block_height_two_plane
[13:00:34] [PASSED] drm_test_format_block_height_three_plane
[13:00:34] [PASSED] drm_test_format_block_height_tiled
[13:00:34] [PASSED] drm_test_format_min_pitch_invalid
[13:00:34] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[13:00:34] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[13:00:34] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[13:00:34] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[13:00:34] [PASSED] drm_test_format_min_pitch_two_plane
[13:00:34] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[13:00:34] [PASSED] drm_test_format_min_pitch_tiled
[13:00:34] =================== [PASSED] drm_format ====================
[13:00:34] ============== drm_framebuffer (10 subtests) ===============
[13:00:34] ========== drm_test_framebuffer_check_src_coords ==========
[13:00:34] [PASSED] Success: source fits into fb
[13:00:34] [PASSED] Fail: overflowing fb with x-axis coordinate
[13:00:34] [PASSED] Fail: overflowing fb with y-axis coordinate
[13:00:34] [PASSED] Fail: overflowing fb with source width
[13:00:34] [PASSED] Fail: overflowing fb with source height
[13:00:34] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[13:00:34] [PASSED] drm_test_framebuffer_cleanup
[13:00:34] =============== drm_test_framebuffer_create ===============
[13:00:34] [PASSED] ABGR8888 normal sizes
[13:00:34] [PASSED] ABGR8888 max sizes
[13:00:34] [PASSED] ABGR8888 pitch greater than min required
[13:00:34] [PASSED] ABGR8888 pitch less than min required
[13:00:34] [PASSED] ABGR8888 Invalid width
[13:00:34] [PASSED] ABGR8888 Invalid buffer handle
[13:00:34] [PASSED] No pixel format
[13:00:34] [PASSED] ABGR8888 Width 0
[13:00:34] [PASSED] ABGR8888 Height 0
[13:00:34] [PASSED] ABGR8888 Out of bound height * pitch combination
[13:00:34] [PASSED] ABGR8888 Large buffer offset
[13:00:34] [PASSED] ABGR8888 Buffer offset for inexistent plane
[13:00:34] [PASSED] ABGR8888 Invalid flag
[13:00:34] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[13:00:34] [PASSED] ABGR8888 Valid buffer modifier
[13:00:34] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[13:00:34] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[13:00:34] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[13:00:34] [PASSED] NV12 Normal sizes
[13:00:34] [PASSED] NV12 Max sizes
[13:00:34] [PASSED] NV12 Invalid pitch
[13:00:34] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[13:00:34] [PASSED] NV12 different modifier per-plane
[13:00:34] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[13:00:34] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[13:00:34] [PASSED] NV12 Modifier for inexistent plane
[13:00:34] [PASSED] NV12 Handle for inexistent plane
[13:00:34] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[13:00:34] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[13:00:34] [PASSED] YVU420 Normal sizes
[13:00:34] [PASSED] YVU420 Max sizes
[13:00:34] [PASSED] YVU420 Invalid pitch
[13:00:34] [PASSED] YVU420 Different pitches
[13:00:34] [PASSED] YVU420 Different buffer offsets/pitches
[13:00:34] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[13:00:34] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[13:00:34] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[13:00:34] [PASSED] YVU420 Valid modifier
[13:00:34] [PASSED] YVU420 Different modifiers per plane
[13:00:34] [PASSED] YVU420 Modifier for inexistent plane
[13:00:34] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[13:00:34] [PASSED] X0L2 Normal sizes
[13:00:34] [PASSED] X0L2 Max sizes
[13:00:34] [PASSED] X0L2 Invalid pitch
[13:00:34] [PASSED] X0L2 Pitch greater than minimum required
[13:00:34] [PASSED] X0L2 Handle for inexistent plane
[13:00:34] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[13:00:34] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[13:00:34] [PASSED] X0L2 Valid modifier
[13:00:34] [PASSED] X0L2 Modifier for inexistent plane
[13:00:34] =========== [PASSED] drm_test_framebuffer_create ===========
[13:00:34] [PASSED] drm_test_framebuffer_free
[13:00:34] [PASSED] drm_test_framebuffer_init
[13:00:34] [PASSED] drm_test_framebuffer_init_bad_format
[13:00:34] [PASSED] drm_test_framebuffer_init_dev_mismatch
[13:00:34] [PASSED] drm_test_framebuffer_lookup
[13:00:34] [PASSED] drm_test_framebuffer_lookup_inexistent
[13:00:34] [PASSED] drm_test_framebuffer_modifiers_not_supported
[13:00:34] ================= [PASSED] drm_framebuffer =================
[13:00:34] ================ drm_gem_shmem (8 subtests) ================
[13:00:34] [PASSED] drm_gem_shmem_test_obj_create
[13:00:34] [PASSED] drm_gem_shmem_test_obj_create_private
[13:00:34] [PASSED] drm_gem_shmem_test_pin_pages
[13:00:34] [PASSED] drm_gem_shmem_test_vmap
[13:00:34] [PASSED] drm_gem_shmem_test_get_sg_table
[13:00:34] [PASSED] drm_gem_shmem_test_get_pages_sgt
[13:00:34] [PASSED] drm_gem_shmem_test_madvise
[13:00:34] [PASSED] drm_gem_shmem_test_purge
[13:00:34] ================== [PASSED] drm_gem_shmem ==================
[13:00:34] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[13:00:34] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[13:00:34] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[13:00:34] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[13:00:34] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[13:00:34] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[13:00:34] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[13:00:34] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[13:00:34] [PASSED] Automatic
[13:00:34] [PASSED] Full
[13:00:34] [PASSED] Limited 16:235
[13:00:34] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[13:00:34] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[13:00:34] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[13:00:34] [PASSED] drm_test_check_disable_connector
[13:00:34] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[13:00:34] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[13:00:34] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[13:00:34] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[13:00:34] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[13:00:34] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[13:00:34] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[13:00:34] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[13:00:34] [PASSED] drm_test_check_output_bpc_dvi
[13:00:34] [PASSED] drm_test_check_output_bpc_format_vic_1
[13:00:34] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[13:00:34] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[13:00:34] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[13:00:34] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[13:00:34] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[13:00:34] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[13:00:34] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[13:00:34] ============ drm_test_check_hdmi_color_format =============
[13:00:34] [PASSED] AUTO -> RGB
[13:00:34] [PASSED] YCBCR422 -> YUV422
[13:00:34] [PASSED] YCBCR420 -> YUV420
[13:00:34] [PASSED] YCBCR444 -> YUV444
[13:00:34] [PASSED] RGB -> RGB
[13:00:34] ======== [PASSED] drm_test_check_hdmi_color_format =========
[13:00:34] ======== drm_test_check_hdmi_color_format_420_only ========
[13:00:34] [PASSED] RGB should fail
[13:00:34] [PASSED] YUV444 should fail
[13:00:34] [PASSED] YUV422 should fail
[13:00:34] [PASSED] YUV420 should work
[13:00:34] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[13:00:34] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[13:00:34] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[13:00:34] [PASSED] drm_test_check_broadcast_rgb_value
[13:00:34] [PASSED] drm_test_check_bpc_8_value
[13:00:34] [PASSED] drm_test_check_bpc_10_value
[13:00:34] [PASSED] drm_test_check_bpc_12_value
[13:00:34] [PASSED] drm_test_check_format_value
[13:00:34] [PASSED] drm_test_check_tmds_char_value
[13:00:34] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[13:00:34] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[13:00:34] [PASSED] drm_test_check_mode_valid
[13:00:34] [PASSED] drm_test_check_mode_valid_reject
[13:00:34] [PASSED] drm_test_check_mode_valid_reject_rate
[13:00:34] [PASSED] drm_test_check_mode_valid_reject_max_clock
[13:00:34] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[13:00:34] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[13:00:34] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[13:00:34] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[13:00:34] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[13:00:34] [PASSED] drm_test_check_infoframes
[13:00:34] [PASSED] drm_test_check_reject_avi_infoframe
[13:00:34] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[13:00:34] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[13:00:34] [PASSED] drm_test_check_reject_audio_infoframe
[13:00:34] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[13:00:34] ================= drm_managed (2 subtests) =================
[13:00:34] [PASSED] drm_test_managed_release_action
[13:00:34] [PASSED] drm_test_managed_run_action
[13:00:34] =================== [PASSED] drm_managed ===================
[13:00:34] =================== drm_mm (6 subtests) ====================
[13:00:34] [PASSED] drm_test_mm_init
[13:00:34] [PASSED] drm_test_mm_debug
[13:00:34] [PASSED] drm_test_mm_align32
[13:00:34] [PASSED] drm_test_mm_align64
[13:00:34] [PASSED] drm_test_mm_lowest
[13:00:34] [PASSED] drm_test_mm_highest
[13:00:34] ===================== [PASSED] drm_mm ======================
[13:00:34] ============= drm_modes_analog_tv (5 subtests) =============
[13:00:34] [PASSED] drm_test_modes_analog_tv_mono_576i
[13:00:34] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[13:00:34] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[13:00:34] [PASSED] drm_test_modes_analog_tv_pal_576i
[13:00:34] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[13:00:34] =============== [PASSED] drm_modes_analog_tv ===============
[13:00:34] ============== drm_plane_helper (2 subtests) ===============
[13:00:34] =============== drm_test_check_plane_state ================
[13:00:34] [PASSED] clipping_simple
[13:00:34] [PASSED] clipping_rotate_reflect
[13:00:34] [PASSED] positioning_simple
[13:00:34] [PASSED] upscaling
[13:00:34] [PASSED] downscaling
[13:00:34] [PASSED] rounding1
[13:00:34] [PASSED] rounding2
[13:00:34] [PASSED] rounding3
[13:00:34] [PASSED] rounding4
[13:00:34] =========== [PASSED] drm_test_check_plane_state ============
[13:00:34] =========== drm_test_check_invalid_plane_state ============
[13:00:34] [PASSED] positioning_invalid
[13:00:34] [PASSED] upscaling_invalid
[13:00:34] [PASSED] downscaling_invalid
[13:00:34] ======= [PASSED] drm_test_check_invalid_plane_state ========
[13:00:34] ================ [PASSED] drm_plane_helper =================
[13:00:34] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[13:00:34] ====== drm_test_connector_helper_tv_get_modes_check =======
[13:00:34] [PASSED] None
[13:00:34] [PASSED] PAL
[13:00:34] [PASSED] NTSC
[13:00:34] [PASSED] Both, NTSC Default
[13:00:34] [PASSED] Both, PAL Default
[13:00:34] [PASSED] Both, NTSC Default, with PAL on command-line
[13:00:34] [PASSED] Both, PAL Default, with NTSC on command-line
[13:00:34] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[13:00:34] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[13:00:34] ================== drm_rect (9 subtests) ===================
[13:00:34] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[13:00:34] [PASSED] drm_test_rect_clip_scaled_not_clipped
[13:00:34] [PASSED] drm_test_rect_clip_scaled_clipped
[13:00:34] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[13:00:34] ================= drm_test_rect_intersect =================
[13:00:34] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[13:00:34] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[13:00:34] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[13:00:34] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[13:00:34] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[13:00:34] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[13:00:34] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[13:00:34] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[13:00:34] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[13:00:34] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[13:00:34] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[13:00:34] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[13:00:34] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[13:00:34] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[13:00:34] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[13:00:34] ============= [PASSED] drm_test_rect_intersect =============
[13:00:34] ================ drm_test_rect_calc_hscale ================
[13:00:34] [PASSED] normal use
[13:00:34] [PASSED] out of max range
[13:00:34] [PASSED] out of min range
[13:00:34] [PASSED] zero dst
[13:00:34] [PASSED] negative src
[13:00:34] [PASSED] negative dst
[13:00:34] ============ [PASSED] drm_test_rect_calc_hscale ============
[13:00:34] ================ drm_test_rect_calc_vscale ================
[13:00:34] [PASSED] normal use
[13:00:34] [PASSED] out of max range
[13:00:34] [PASSED] out of min range
[13:00:34] [PASSED] zero dst
[13:00:34] [PASSED] negative src
[13:00:34] [PASSED] negative dst
[13:00:34] ============ [PASSED] drm_test_rect_calc_vscale ============
[13:00:34] ================== drm_test_rect_rotate ===================
[13:00:34] [PASSED] reflect-x
[13:00:34] [PASSED] reflect-y
[13:00:34] [PASSED] rotate-0
[13:00:34] [PASSED] rotate-90
[13:00:34] [PASSED] rotate-180
[13:00:34] [PASSED] rotate-270
[13:00:34] ============== [PASSED] drm_test_rect_rotate ===============
[13:00:34] ================ drm_test_rect_rotate_inv =================
[13:00:34] [PASSED] reflect-x
[13:00:34] [PASSED] reflect-y
[13:00:34] [PASSED] rotate-0
[13:00:34] [PASSED] rotate-90
[13:00:34] [PASSED] rotate-180
[13:00:34] [PASSED] rotate-270
[13:00:34] ============ [PASSED] drm_test_rect_rotate_inv =============
[13:00:34] ==================== [PASSED] drm_rect =====================
[13:00:34] ============ drm_sysfb_modeset_test (1 subtest) ============
[13:00:34] ============ drm_test_sysfb_build_fourcc_list =============
[13:00:34] [PASSED] no native formats
[13:00:34] [PASSED] XRGB8888 as native format
[13:00:34] [PASSED] remove duplicates
[13:00:34] [PASSED] convert alpha formats
[13:00:34] [PASSED] random formats
[13:00:34] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[13:00:34] ============= [PASSED] drm_sysfb_modeset_test ==============
[13:00:34] ================== drm_fixp (2 subtests) ===================
[13:00:34] [PASSED] drm_test_int2fixp
[13:00:34] [PASSED] drm_test_sm2fixp
[13:00:34] ==================== [PASSED] drm_fixp =====================
[13:00:34] ============================================================
[13:00:34] Testing complete. Ran 637 tests: passed: 637
[13:00:34] Elapsed time: 26.576s total, 1.786s configuring, 24.625s building, 0.148s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[13:00:35] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[13:00:36] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[13:00:46] Starting KUnit Kernel (1/1)...
[13:00:46] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[13:00:46] ================= ttm_device (5 subtests) ==================
[13:00:46] [PASSED] ttm_device_init_basic
[13:00:46] [PASSED] ttm_device_init_multiple
[13:00:46] [PASSED] ttm_device_fini_basic
[13:00:46] [PASSED] ttm_device_init_no_vma_man
[13:00:46] ================== ttm_device_init_pools ==================
[13:00:46] [PASSED] No DMA allocations, no DMA32 required
[13:00:46] [PASSED] DMA allocations, DMA32 required
[13:00:46] [PASSED] No DMA allocations, DMA32 required
[13:00:46] [PASSED] DMA allocations, no DMA32 required
[13:00:46] ============== [PASSED] ttm_device_init_pools ==============
[13:00:46] =================== [PASSED] ttm_device ====================
[13:00:46] ================== ttm_pool (8 subtests) ===================
[13:00:46] ================== ttm_pool_alloc_basic ===================
[13:00:46] [PASSED] One page
[13:00:46] [PASSED] More than one page
[13:00:46] [PASSED] Above the allocation limit
[13:00:46] [PASSED] One page, with coherent DMA mappings enabled
[13:00:46] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[13:00:46] ============== [PASSED] ttm_pool_alloc_basic ===============
[13:00:46] ============== ttm_pool_alloc_basic_dma_addr ==============
[13:00:46] [PASSED] One page
[13:00:46] [PASSED] More than one page
[13:00:46] [PASSED] Above the allocation limit
[13:00:46] [PASSED] One page, with coherent DMA mappings enabled
[13:00:46] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[13:00:46] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[13:00:46] [PASSED] ttm_pool_alloc_order_caching_match
[13:00:46] [PASSED] ttm_pool_alloc_caching_mismatch
[13:00:46] [PASSED] ttm_pool_alloc_order_mismatch
[13:00:46] [PASSED] ttm_pool_free_dma_alloc
[13:00:46] [PASSED] ttm_pool_free_no_dma_alloc
[13:00:46] [PASSED] ttm_pool_fini_basic
[13:00:46] ==================== [PASSED] ttm_pool =====================
[13:00:46] ================ ttm_resource (8 subtests) =================
[13:00:46] ================= ttm_resource_init_basic =================
[13:00:46] [PASSED] Init resource in TTM_PL_SYSTEM
[13:00:46] [PASSED] Init resource in TTM_PL_VRAM
[13:00:46] [PASSED] Init resource in a private placement
[13:00:46] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[13:00:46] ============= [PASSED] ttm_resource_init_basic =============
[13:00:46] [PASSED] ttm_resource_init_pinned
[13:00:46] [PASSED] ttm_resource_fini_basic
[13:00:46] [PASSED] ttm_resource_manager_init_basic
[13:00:46] [PASSED] ttm_resource_manager_usage_basic
[13:00:46] [PASSED] ttm_resource_manager_set_used_basic
[13:00:46] [PASSED] ttm_sys_man_alloc_basic
[13:00:46] [PASSED] ttm_sys_man_free_basic
[13:00:46] ================== [PASSED] ttm_resource ===================
[13:00:46] =================== ttm_tt (15 subtests) ===================
[13:00:46] ==================== ttm_tt_init_basic ====================
[13:00:46] [PASSED] Page-aligned size
[13:00:46] [PASSED] Extra pages requested
[13:00:46] ================ [PASSED] ttm_tt_init_basic ================
[13:00:46] [PASSED] ttm_tt_init_misaligned
[13:00:46] [PASSED] ttm_tt_fini_basic
[13:00:46] [PASSED] ttm_tt_fini_sg
[13:00:46] [PASSED] ttm_tt_fini_shmem
[13:00:46] [PASSED] ttm_tt_create_basic
[13:00:46] [PASSED] ttm_tt_create_invalid_bo_type
[13:00:46] [PASSED] ttm_tt_create_ttm_exists
[13:00:46] [PASSED] ttm_tt_create_failed
[13:00:46] [PASSED] ttm_tt_destroy_basic
[13:00:46] [PASSED] ttm_tt_populate_null_ttm
[13:00:46] [PASSED] ttm_tt_populate_populated_ttm
[13:00:46] [PASSED] ttm_tt_unpopulate_basic
[13:00:46] [PASSED] ttm_tt_unpopulate_empty_ttm
[13:00:46] [PASSED] ttm_tt_swapin_basic
[13:00:46] ===================== [PASSED] ttm_tt ======================
[13:00:46] =================== ttm_bo (14 subtests) ===================
[13:00:46] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[13:00:46] [PASSED] Cannot be interrupted and sleeps
[13:00:46] [PASSED] Cannot be interrupted, locks straight away
[13:00:46] [PASSED] Can be interrupted, sleeps
[13:00:46] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[13:00:46] [PASSED] ttm_bo_reserve_locked_no_sleep
[13:00:46] [PASSED] ttm_bo_reserve_no_wait_ticket
[13:00:46] [PASSED] ttm_bo_reserve_double_resv
[13:00:46] [PASSED] ttm_bo_reserve_interrupted
[13:00:46] [PASSED] ttm_bo_reserve_deadlock
[13:00:46] [PASSED] ttm_bo_unreserve_basic
[13:00:46] [PASSED] ttm_bo_unreserve_pinned
[13:00:46] [PASSED] ttm_bo_unreserve_bulk
[13:00:46] [PASSED] ttm_bo_fini_basic
[13:00:46] [PASSED] ttm_bo_fini_shared_resv
[13:00:46] [PASSED] ttm_bo_pin_basic
[13:00:46] [PASSED] ttm_bo_pin_unpin_resource
[13:00:46] [PASSED] ttm_bo_multiple_pin_one_unpin
[13:00:46] ===================== [PASSED] ttm_bo ======================
[13:00:46] ============== ttm_bo_validate (22 subtests) ===============
[13:00:46] ============== ttm_bo_init_reserved_sys_man ===============
[13:00:46] [PASSED] Buffer object for userspace
[13:00:46] [PASSED] Kernel buffer object
[13:00:46] [PASSED] Shared buffer object
[13:00:46] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[13:00:46] ============== ttm_bo_init_reserved_mock_man ==============
[13:00:46] [PASSED] Buffer object for userspace
[13:00:46] [PASSED] Kernel buffer object
[13:00:46] [PASSED] Shared buffer object
[13:00:46] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[13:00:46] [PASSED] ttm_bo_init_reserved_resv
[13:00:46] ================== ttm_bo_validate_basic ==================
[13:00:46] [PASSED] Buffer object for userspace
[13:00:46] [PASSED] Kernel buffer object
[13:00:46] [PASSED] Shared buffer object
[13:00:46] ============== [PASSED] ttm_bo_validate_basic ==============
[13:00:46] [PASSED] ttm_bo_validate_invalid_placement
[13:00:46] ============= ttm_bo_validate_same_placement ==============
[13:00:46] [PASSED] System manager
[13:00:46] [PASSED] VRAM manager
[13:00:46] ========= [PASSED] ttm_bo_validate_same_placement ==========
[13:00:46] [PASSED] ttm_bo_validate_failed_alloc
[13:00:46] [PASSED] ttm_bo_validate_pinned
[13:00:46] [PASSED] ttm_bo_validate_busy_placement
[13:00:46] ================ ttm_bo_validate_multihop =================
[13:00:46] [PASSED] Buffer object for userspace
[13:00:46] [PASSED] Kernel buffer object
[13:00:46] [PASSED] Shared buffer object
[13:00:46] ============ [PASSED] ttm_bo_validate_multihop =============
[13:00:46] ========== ttm_bo_validate_no_placement_signaled ==========
[13:00:46] [PASSED] Buffer object in system domain, no page vector
[13:00:46] [PASSED] Buffer object in system domain with an existing page vector
[13:00:46] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[13:00:46] ======== ttm_bo_validate_no_placement_not_signaled ========
[13:00:46] [PASSED] Buffer object for userspace
[13:00:46] [PASSED] Kernel buffer object
[13:00:46] [PASSED] Shared buffer object
[13:00:46] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[13:00:46] [PASSED] ttm_bo_validate_move_fence_signaled
[13:00:46] ========= ttm_bo_validate_move_fence_not_signaled =========
[13:00:46] [PASSED] Waits for GPU
[13:00:46] [PASSED] Tries to lock straight away
[13:00:46] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[13:00:46] [PASSED] ttm_bo_validate_swapout
[13:00:46] [PASSED] ttm_bo_validate_happy_evict
[13:00:46] [PASSED] ttm_bo_validate_all_pinned_evict
[13:00:46] [PASSED] ttm_bo_validate_allowed_only_evict
[13:00:46] [PASSED] ttm_bo_validate_deleted_evict
[13:00:46] [PASSED] ttm_bo_validate_busy_domain_evict
[13:00:46] [PASSED] ttm_bo_validate_evict_gutting
[13:00:46] [PASSED] ttm_bo_validate_recrusive_evict
[13:00:46] ================= [PASSED] ttm_bo_validate =================
[13:00:46] ============================================================
[13:00:46] Testing complete. Ran 102 tests: passed: 102
[13:00:47] Elapsed time: 11.956s total, 1.773s configuring, 9.917s building, 0.225s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/dma-buf/.kunitconfig
[13:00:47] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[13:00:48] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[13:00:57] Starting KUnit Kernel (1/1)...
[13:00:57] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[13:00:57] =============== dma-buf-fence (12 subtests) ================
[13:00:57] [PASSED] test_sanitycheck
[13:00:57] [PASSED] test_signaling
[13:00:57] [PASSED] test_add_callback
[13:00:57] [PASSED] test_late_add_callback
[13:00:57] [PASSED] test_rm_callback
[13:00:57] [PASSED] test_late_rm_callback
[13:00:57] [PASSED] test_status
[13:00:57] [PASSED] test_error
[13:00:57] [PASSED] test_wait
[13:00:57] [PASSED] test_wait_timeout
[13:00:57] [PASSED] test_stub
[13:00:57] [SKIPPED] test_race_signal_callback (requires at least 2 CPUs)
[13:00:57] ================== [PASSED] dma-buf-fence ==================
[13:00:57] ============ dma-buf-fence-chain (11 subtests) =============
[13:00:57] [PASSED] test_sanitycheck
[13:00:57] [PASSED] test_find_seqno
[13:00:57] [PASSED] test_find_signaled
[13:00:57] [PASSED] test_find_out_of_order
[13:01:02] [PASSED] test_find_gap
[13:01:02] [PASSED] test_find_race
[13:01:02] [PASSED] test_signal_forward
[13:01:02] [PASSED] test_signal_backward
[13:01:02] [PASSED] test_wait_forward
[13:01:02] [PASSED] test_wait_backward
[13:01:02] [PASSED] test_wait_random
[13:01:02] =============== [PASSED] dma-buf-fence-chain ===============
[13:01:02] ============ dma-buf-fence-unwrap (10 subtests) ============
[13:01:02] [PASSED] test_sanitycheck
[13:01:02] [PASSED] test_unwrap_array
[13:01:02] [PASSED] test_unwrap_chain
[13:01:02] [PASSED] test_unwrap_chain_array
[13:01:02] [PASSED] test_unwrap_merge
[13:01:02] [PASSED] test_unwrap_merge_duplicate
[13:01:02] [PASSED] test_unwrap_merge_seqno
[13:01:02] [PASSED] test_unwrap_merge_order
[13:01:02] [PASSED] test_unwrap_merge_complex
[13:01:02] [PASSED] test_unwrap_merge_complex_seqno
[13:01:02] ============== [PASSED] dma-buf-fence-unwrap ===============
[13:01:02] ================ dma-buf-resv (5 subtests) =================
[13:01:02] [PASSED] test_sanitycheck
[13:01:02] ===================== test_signaling ======================
[13:01:02] [PASSED] kernel
[13:01:02] [PASSED] write
[13:01:02] [PASSED] read
[13:01:02] [PASSED] bookkeep
[13:01:02] ================= [PASSED] test_signaling ==================
[13:01:02] ====================== test_for_each ======================
[13:01:02] [PASSED] kernel
[13:01:02] [PASSED] write
[13:01:02] [PASSED] read
[13:01:02] [PASSED] bookkeep
[13:01:02] ================== [PASSED] test_for_each ==================
[13:01:02] ================= test_for_each_unlocked ==================
[13:01:02] [PASSED] kernel
[13:01:02] [PASSED] write
[13:01:02] [PASSED] read
[13:01:02] [PASSED] bookkeep
[13:01:02] ============= [PASSED] test_for_each_unlocked ==============
[13:01:02] ===================== test_get_fences =====================
[13:01:02] [PASSED] kernel
[13:01:02] [PASSED] write
[13:01:02] [PASSED] read
[13:01:02] [PASSED] bookkeep
[13:01:02] ================= [PASSED] test_get_fences =================
[13:01:02] ================== [PASSED] dma-buf-resv ===================
[13:01:02] ============================================================
[13:01:02] Testing complete. Ran 50 tests: passed: 49, skipped: 1
[13:01:02] Elapsed time: 15.786s total, 1.829s configuring, 8.685s building, 5.266s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [CI] drm/xe/vram: Add early VRAM health check
2026-08-26 12:53 [CI] drm/xe/vram: Add early VRAM health check Matthew Auld
2026-08-26 12:59 ` ✗ CI.checkpatch: warning for " Patchwork
2026-08-26 13:01 ` ✓ CI.KUnit: success " Patchwork
@ 2026-08-26 13:11 ` sashiko-bot
2026-08-26 13:59 ` ✗ Xe.CI.BAT: failure for " Patchwork
2026-08-26 16:12 ` ✗ Xe.CI.FULL: " Patchwork
4 siblings, 0 replies; 6+ messages in thread
From: sashiko-bot @ 2026-08-26 13:11 UTC (permalink / raw)
To: Matthew Auld; +Cc: intel-xe
Thank you for your contribution! Sashiko AI review found 8 potential issue(s) to consider:
- [High] VRAM memtest BOs are leaked on error paths and skipped tiles.
- [High] `xe_migrate_debug_ccs_overlap` fails to acquire the necessary `job_mutex` lock.
- [High] `xe_migrate_debug_ccs_overlap` fails to initialize the second migration batch buffer, causing execution of uninitialized GPU memory.
- [High] Hardcoded 256MB VRAM bounds in `xe_migrate_debug_ccs_overlap` causes out-of-bounds GPU reads on systems with small VRAM.
- [High] The CCS overlap test writes a canary to the end of VRAM but checks the CCS metadata for the beginning of VRAM, rendering the test useless.
- [Medium] Mismatch between code implementation and comment for flat CCS offset rounding.
- [Medium] Config guard mismatch for `memtest_bo` causes build failures.
- [Medium] Ignoring the return value of `xe_migrate_clear()` masks software errors as hardware failures.
--
commit c386b266adaf1a488d11cddd5ddf577c88467fb1
Author: Matthew Auld <matthew.auld@intel.com>
Subject: drm/xe/vram: Add early VRAM health check
This commit introduces an early VRAM health check to detect BAR sizing, CCS
sizing, and identity map setup issues using a canary page at the end of VRAM.
> diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
> index 71ce153737abe..5d9e3dc133fa8 100644
> --- a/drivers/gpu/drm/xe/xe_device.c
> +++ b/drivers/gpu/drm/xe/xe_device.c
[ ... ]
> @@ -1040,6 +1040,8 @@ int xe_device_probe(struct xe_device *xe)
> if (err)
> return err;
>
> + xe_vram_reserve_memtest_bo(xe);
> +
> for_each_tile(tile, xe, id) {
> err = xe_tile_init(tile);
> if (err)
> return err;
[Severity: High]
If xe_tile_init() fails, does this code leak the reserved memtest BOs since
there is no cleanup before returning the error?
[ ... ]
> diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
> index f79d0047bec69..644be4c2d4404 100644
> --- a/drivers/gpu/drm/xe/xe_migrate.c
> +++ b/drivers/gpu/drm/xe/xe_migrate.c
[ ... ]
> @@ -2635,3 +2635,59 @@ void xe_migrate_job_lock_assert(struct xe_exec_queue *q)
> #if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)
> #include "tests/xe_migrate.c"
> #endif
> +
> +#if IS_ENABLED(CONFIG_DRM_XE_DEBUG_MEM)
> +void xe_migrate_debug_ccs_overlap(struct xe_migrate *m, struct xe_bo *last_page_bo, struct xe_bo *scratch_bo)
> +{
> + struct xe_device *xe = tile_to_xe(m->tile);
> + struct xe_gt *gt = m->tile->primary_gt;
> + struct dma_fence *fence;
> + struct xe_bb *bb;
> + struct xe_sched_job *job;
> + u64 first_page_dpa, clear_L0_ofs, scratch_dpa, scratch_L0_ofs;
> +
> + if (!xe_device_has_flat_ccs(xe))
> + return;
> +
> + first_page_dpa = xe_vram_region_dpa_base(m->tile->mem.vram);
> + clear_L0_ofs = xe_migrate_vram_ofs(xe, first_page_dpa, true);
[Severity: High]
The test writes a canary pattern to the end of VRAM (vram_size - SZ_64K) later,
but clear_L0_ofs is based on first_page_dpa (the very beginning of VRAM). Does
this check the wrong CCS metadata region and miss the canary pattern entirely?
> +
> + scratch_dpa = xe_bo_addr(scratch_bo, 0, XE_PAGE_SIZE);
> + scratch_L0_ofs = xe_migrate_vram_ofs(xe, scratch_dpa, false);
> +
> + for (int j = 0; j < 4; j++) {
> + bb = xe_bb_new(gt, 256, xe->info.has_usm);
> + if (IS_ERR(bb)) {
> + drm_warn(&xe->drm, "Failed to create bb for VRAM overlap check\n");
> + return;
> + }
> +
> + for (int i = 0; i < 16; i++) {
> + int idx = (j * 16) + i;
> + /* 4MB payload = 16KB CCS metadata */
> + emit_copy_ccs(gt, bb, scratch_L0_ofs + (idx * 16384), false,
> + clear_L0_ofs + (idx * SZ_4M), true, SZ_4M);
[Severity: High]
Is it possible for a tile's VRAM to be smaller than 256MB? This loop
unconditionally tests 256MB (64 iterations of 4MB chunks), which might result
in out-of-bounds GPU reads on smaller VRAM configurations.
> + }
> +
> + bb->cs[bb->len++] = MI_BATCH_BUFFER_END;
> +
> + job = xe_bb_create_migration_job(m->q, bb,
> + xe_migrate_batch_base(m, xe->info.has_usm),
> + bb->len);
[Severity: High]
By passing bb->len as the second_idx right after writing MI_BATCH_BUFFER_END,
does xe_bb_create_migration_job() leave the second batch buffer empty and
unterminated? This might cause the GPU to execute uninitialized memory.
> + if (!IS_ERR(job)) {
> + xe_sched_job_add_migrate_flush(job, MI_FLUSH_DW_CCS);
> + xe_sched_job_arm(job);
> +
> + fence = dma_fence_get(&job->drm.s_fence->finished);
> + xe_sched_job_push(job);
[Severity: High]
Does this code need to acquire m->job_mutex before calling xe_sched_job_arm()
and xe_sched_job_push()? Other migration jobs hold this lock to serialize
queue accesses.
[ ... ]
> diff --git a/drivers/gpu/drm/xe/xe_tile_types.h b/drivers/gpu/drm/xe/xe_tile_types.h
> index 0048100ccb723..75097e4d1c643 100644
> --- a/drivers/gpu/drm/xe/xe_tile_types.h
> +++ b/drivers/gpu/drm/xe/xe_tile_types.h
> @@ -97,6 +97,10 @@ struct xe_tile {
> * Only main GT has page reclaim list allocations.
> */
> struct xe_sa_manager *reclaim_pool;
> +#if IS_ENABLED(CONFIG_DRM_XE_DEBUG)
> + /** @mem.memtest_bo: VRAM overlap check BO */
> + struct xe_bo *memtest_bo;
> +#endif
[Severity: Medium]
In this header, memtest_bo is guarded by CONFIG_DRM_XE_DEBUG, but in
xe_vram.c and xe_migrate.c its usage is guarded by CONFIG_DRM_XE_DEBUG_MEM.
Will this cause a build failure if CONFIG_DRM_XE_DEBUG_MEM is enabled without
CONFIG_DRM_XE_DEBUG?
[ ... ]
> diff --git a/drivers/gpu/drm/xe/xe_vram.c b/drivers/gpu/drm/xe/xe_vram.c
> index 23eb7edbdd572..eb3d7b42371cd 100644
> --- a/drivers/gpu/drm/xe/xe_vram.c
> +++ b/drivers/gpu/drm/xe/xe_vram.c
[ ... ]
> @@ -89,7 +92,7 @@ static int get_flat_ccs_offset(struct xe_gt *gt, u64 tile_size, u64 *poffset)
> offset = offset_hi << 32; /* HW view bits 39:32 */
> offset |= offset_lo << 6; /* HW view bits 31:6 */
> offset *= num_enabled; /* convert to SW view */
> - offset = round_up(offset, SZ_128K); /* SW must round up to nearest 128K */
> + offset = round_up(offset, SZ_128K); /* SW must round down to nearest 2M */
[Severity: Medium]
The comment states we must round down to nearest 2M, but the code still calls
round_up(offset, SZ_128K). Which one is the intended behavior?
[ ... ]
> @@ -387,3 +390,160 @@ resource_size_t xe_vram_region_actual_physical_size(const struct xe_vram_region
[ ... ]
> +int xe_vram_memtest(struct xe_device *xe)
> +{
> + struct xe_tile *tile;
> + u8 id;
> + int err = 0;
> +
> + for_each_tile(tile, xe, id) {
> + struct xe_bo *last_page_bo = tile->mem.memtest_bo;
> + struct dma_fence *fence;
> + bool overlap = false;
> + int i, consecutive = 0;
> + u8 val;
> +
> + if (!last_page_bo || !tile->migrate)
> + continue;
[Severity: High]
For tiles without a migrate engine, does this continue bypass the unpin and
cleanup of tile->mem.memtest_bo, leading to a resource leak?
[ ... ]
> + /* 2. Non-CCS access via GPU on the last page */
> + fence = xe_migrate_clear(tile->migrate, last_page_bo,
> + last_page_bo->ttm.resource,
> + XE_MIGRATE_CLEAR_FLAG_BO_DATA);
> + if (!IS_ERR(fence)) {
> + dma_fence_wait(fence, false);
> + dma_fence_put(fence);
> + }
> +
> + rmb();
> +
> + val = xe_map_rd(xe, &last_page_bo->vmap, 0, u8);
> + if (drm_WARN(&xe->drm, val != 0x00,
> + "Tile %d: GPU memtest clear failed at offset 0 (expected 0x00, got 0x%02x)\n",
> + id, val)) {
[Severity: Medium]
If xe_migrate_clear() fails and returns an ERR_PTR, this skips the wait but
proceeds to read the VRAM validation byte. Will this falsely report a GPU
hardware failure because it reads the old 0xA5 value instead of 0x00?
[ ... ]
> +
> +unpin:
> + xe_bo_unpin_map_no_vm(last_page_bo);
> + tile->mem.memtest_bo = NULL;
> + if (err)
> + return err;
> + }
> +
> + return 0;
> +}
[Severity: High]
On error, this early return skips cleanup for the remaining tiles in the loop.
Does this code leak the memtest_bo for subsequent tiles?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260826125304.378173-2-matthew.auld@intel.com?part=1
^ permalink raw reply [flat|nested] 6+ messages in thread
* ✗ Xe.CI.BAT: failure for drm/xe/vram: Add early VRAM health check
2026-08-26 12:53 [CI] drm/xe/vram: Add early VRAM health check Matthew Auld
` (2 preceding siblings ...)
2026-08-26 13:11 ` [CI] " sashiko-bot
@ 2026-08-26 13:59 ` Patchwork
2026-08-26 16:12 ` ✗ Xe.CI.FULL: " Patchwork
4 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2026-08-26 13:59 UTC (permalink / raw)
To: Matthew Auld; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 2644 bytes --]
== Series Details ==
Series: drm/xe/vram: Add early VRAM health check
URL : https://patchwork.freedesktop.org/series/172786/
State : failure
== Summary ==
CI Bug Log - changes from xe-5647-4a47d4b5bf957bd7e34d8d3ab7096c42161892c6_BAT -> xe-pw-172786v1_BAT
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with xe-pw-172786v1_BAT absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-172786v1_BAT, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (13 -> 13)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in xe-pw-172786v1_BAT:
### IGT changes ###
#### Possible regressions ####
* igt@xe_module_load@load:
- bat-atsm-2: [PASS][1] -> [ABORT][2]
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5647-4a47d4b5bf957bd7e34d8d3ab7096c42161892c6/bat-atsm-2/igt@xe_module_load@load.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172786v1/bat-atsm-2/igt@xe_module_load@load.html
- bat-bmg-3: [PASS][3] -> [ABORT][4]
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5647-4a47d4b5bf957bd7e34d8d3ab7096c42161892c6/bat-bmg-3/igt@xe_module_load@load.html
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172786v1/bat-bmg-3/igt@xe_module_load@load.html
- bat-bmg-2: [PASS][5] -> [ABORT][6]
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5647-4a47d4b5bf957bd7e34d8d3ab7096c42161892c6/bat-bmg-2/igt@xe_module_load@load.html
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172786v1/bat-bmg-2/igt@xe_module_load@load.html
- bat-bmg-1: [PASS][7] -> [ABORT][8]
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5647-4a47d4b5bf957bd7e34d8d3ab7096c42161892c6/bat-bmg-1/igt@xe_module_load@load.html
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172786v1/bat-bmg-1/igt@xe_module_load@load.html
Build changes
-------------
* Linux: xe-5647-4a47d4b5bf957bd7e34d8d3ab7096c42161892c6 -> xe-pw-172786v1
IGT_9076: 8f42b0189d73d9912ad58c99cfaa4ff46c20fcc3 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-5647-4a47d4b5bf957bd7e34d8d3ab7096c42161892c6: 4a47d4b5bf957bd7e34d8d3ab7096c42161892c6
xe-pw-172786v1: 172786v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172786v1/index.html
[-- Attachment #2: Type: text/html, Size: 3253 bytes --]
^ permalink raw reply [flat|nested] 6+ messages in thread
* ✗ Xe.CI.FULL: failure for drm/xe/vram: Add early VRAM health check
2026-08-26 12:53 [CI] drm/xe/vram: Add early VRAM health check Matthew Auld
` (3 preceding siblings ...)
2026-08-26 13:59 ` ✗ Xe.CI.BAT: failure for " Patchwork
@ 2026-08-26 16:12 ` Patchwork
4 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2026-08-26 16:12 UTC (permalink / raw)
To: Matthew Auld; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 10879 bytes --]
== Series Details ==
Series: drm/xe/vram: Add early VRAM health check
URL : https://patchwork.freedesktop.org/series/172786/
State : failure
== Summary ==
CI Bug Log - changes from xe-5647-4a47d4b5bf957bd7e34d8d3ab7096c42161892c6_FULL -> xe-pw-172786v1_FULL
====================================================
Summary
-------
**WARNING**
Minor unknown changes coming with xe-pw-172786v1_FULL need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-172786v1_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (2 -> 2)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in xe-pw-172786v1_FULL:
### IGT changes ###
#### Warnings ####
* igt@xe_module_load@load:
- shard-bmg: ([PASS][1], [PASS][2], [PASS][3], [PASS][4], [SKIP][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26]) ([Intel XE#2457] / [Intel XE#7405]) -> ([DMESG-WARN][27], [DMESG-WARN][28], [DMESG-WARN][29], [DMESG-WARN][30], [DMESG-WARN][31], [DMESG-WARN][32], [DMESG-WARN][33], [DMESG-WARN][34], [DMESG-WARN][35], [DMESG-WARN][36], [DMESG-WARN][37], [DMESG-WARN][38], [DMESG-WARN][39], [DMESG-WARN][40], [DMESG-WARN][41], [DMESG-WARN][42], [DMESG-WARN][43], [DMESG-WARN][44], [DMESG-WARN][45], [DMESG-WARN][46], [DMESG-WARN][47], [DMESG-WARN][48], [DMESG-WARN][49], [DMESG-WARN][50], [DMESG-WARN][51])
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5647-4a47d4b5bf957bd7e34d8d3ab7096c42161892c6/shard-bmg-8/igt@xe_module_load@load.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5647-4a47d4b5bf957bd7e34d8d3ab7096c42161892c6/shard-bmg-1/igt@xe_module_load@load.html
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5647-4a47d4b5bf957bd7e34d8d3ab7096c42161892c6/shard-bmg-1/igt@xe_module_load@load.html
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5647-4a47d4b5bf957bd7e34d8d3ab7096c42161892c6/shard-bmg-1/igt@xe_module_load@load.html
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5647-4a47d4b5bf957bd7e34d8d3ab7096c42161892c6/shard-bmg-1/igt@xe_module_load@load.html
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5647-4a47d4b5bf957bd7e34d8d3ab7096c42161892c6/shard-bmg-6/igt@xe_module_load@load.html
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5647-4a47d4b5bf957bd7e34d8d3ab7096c42161892c6/shard-bmg-3/igt@xe_module_load@load.html
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5647-4a47d4b5bf957bd7e34d8d3ab7096c42161892c6/shard-bmg-6/igt@xe_module_load@load.html
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5647-4a47d4b5bf957bd7e34d8d3ab7096c42161892c6/shard-bmg-6/igt@xe_module_load@load.html
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5647-4a47d4b5bf957bd7e34d8d3ab7096c42161892c6/shard-bmg-4/igt@xe_module_load@load.html
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5647-4a47d4b5bf957bd7e34d8d3ab7096c42161892c6/shard-bmg-4/igt@xe_module_load@load.html
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5647-4a47d4b5bf957bd7e34d8d3ab7096c42161892c6/shard-bmg-10/igt@xe_module_load@load.html
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5647-4a47d4b5bf957bd7e34d8d3ab7096c42161892c6/shard-bmg-10/igt@xe_module_load@load.html
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5647-4a47d4b5bf957bd7e34d8d3ab7096c42161892c6/shard-bmg-5/igt@xe_module_load@load.html
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5647-4a47d4b5bf957bd7e34d8d3ab7096c42161892c6/shard-bmg-3/igt@xe_module_load@load.html
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5647-4a47d4b5bf957bd7e34d8d3ab7096c42161892c6/shard-bmg-5/igt@xe_module_load@load.html
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5647-4a47d4b5bf957bd7e34d8d3ab7096c42161892c6/shard-bmg-7/igt@xe_module_load@load.html
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5647-4a47d4b5bf957bd7e34d8d3ab7096c42161892c6/shard-bmg-7/igt@xe_module_load@load.html
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5647-4a47d4b5bf957bd7e34d8d3ab7096c42161892c6/shard-bmg-7/igt@xe_module_load@load.html
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5647-4a47d4b5bf957bd7e34d8d3ab7096c42161892c6/shard-bmg-9/igt@xe_module_load@load.html
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5647-4a47d4b5bf957bd7e34d8d3ab7096c42161892c6/shard-bmg-8/igt@xe_module_load@load.html
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5647-4a47d4b5bf957bd7e34d8d3ab7096c42161892c6/shard-bmg-3/igt@xe_module_load@load.html
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5647-4a47d4b5bf957bd7e34d8d3ab7096c42161892c6/shard-bmg-2/igt@xe_module_load@load.html
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5647-4a47d4b5bf957bd7e34d8d3ab7096c42161892c6/shard-bmg-2/igt@xe_module_load@load.html
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5647-4a47d4b5bf957bd7e34d8d3ab7096c42161892c6/shard-bmg-2/igt@xe_module_load@load.html
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5647-4a47d4b5bf957bd7e34d8d3ab7096c42161892c6/shard-bmg-9/igt@xe_module_load@load.html
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172786v1/shard-bmg-5/igt@xe_module_load@load.html
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172786v1/shard-bmg-5/igt@xe_module_load@load.html
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172786v1/shard-bmg-5/igt@xe_module_load@load.html
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172786v1/shard-bmg-4/igt@xe_module_load@load.html
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172786v1/shard-bmg-4/igt@xe_module_load@load.html
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172786v1/shard-bmg-4/igt@xe_module_load@load.html
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172786v1/shard-bmg-4/igt@xe_module_load@load.html
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172786v1/shard-bmg-8/igt@xe_module_load@load.html
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172786v1/shard-bmg-10/igt@xe_module_load@load.html
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172786v1/shard-bmg-10/igt@xe_module_load@load.html
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172786v1/shard-bmg-10/igt@xe_module_load@load.html
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172786v1/shard-bmg-10/igt@xe_module_load@load.html
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172786v1/shard-bmg-6/igt@xe_module_load@load.html
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172786v1/shard-bmg-6/igt@xe_module_load@load.html
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172786v1/shard-bmg-1/igt@xe_module_load@load.html
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172786v1/shard-bmg-1/igt@xe_module_load@load.html
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172786v1/shard-bmg-7/igt@xe_module_load@load.html
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172786v1/shard-bmg-7/igt@xe_module_load@load.html
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172786v1/shard-bmg-9/igt@xe_module_load@load.html
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172786v1/shard-bmg-3/igt@xe_module_load@load.html
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172786v1/shard-bmg-9/igt@xe_module_load@load.html
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172786v1/shard-bmg-9/igt@xe_module_load@load.html
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172786v1/shard-bmg-9/igt@xe_module_load@load.html
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172786v1/shard-bmg-2/igt@xe_module_load@load.html
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172786v1/shard-bmg-2/igt@xe_module_load@load.html
Known issues
------------
Here are the changes found in xe-pw-172786v1_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-lnl: [PASS][52] -> [FAIL][53] ([Intel XE#301]) +1 other test fail
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5647-4a47d4b5bf957bd7e34d8d3ab7096c42161892c6/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172786v1/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
#### Possible fixes ####
* igt@kms_flip@flip-vs-expired-vblank@c-edp1:
- shard-lnl: [FAIL][54] ([Intel XE#301] / [Intel XE#3149]) -> [PASS][55] +1 other test pass
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5647-4a47d4b5bf957bd7e34d8d3ab7096c42161892c6/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172786v1/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
* igt@kms_pm_dc@dc6-dpms:
- shard-lnl: [FAIL][56] ([Intel XE#8399]) -> [PASS][57]
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5647-4a47d4b5bf957bd7e34d8d3ab7096c42161892c6/shard-lnl-2/igt@kms_pm_dc@dc6-dpms.html
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172786v1/shard-lnl-3/igt@kms_pm_dc@dc6-dpms.html
#### Warnings ####
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-lnl: [FAIL][58] ([Intel XE#301] / [Intel XE#3149]) -> [FAIL][59] ([Intel XE#301]) +1 other test fail
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5647-4a47d4b5bf957bd7e34d8d3ab7096c42161892c6/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172786v1/shard-lnl-6/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[Intel XE#2457]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2457
[Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
[Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
[Intel XE#7405]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7405
[Intel XE#8399]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8399
Build changes
-------------
* Linux: xe-5647-4a47d4b5bf957bd7e34d8d3ab7096c42161892c6 -> xe-pw-172786v1
IGT_9076: 8f42b0189d73d9912ad58c99cfaa4ff46c20fcc3 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-5647-4a47d4b5bf957bd7e34d8d3ab7096c42161892c6: 4a47d4b5bf957bd7e34d8d3ab7096c42161892c6
xe-pw-172786v1: 172786v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172786v1/index.html
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2026-08-26 12:53 [CI] drm/xe/vram: Add early VRAM health check Matthew Auld
2026-08-26 12:59 ` ✗ CI.checkpatch: warning for " Patchwork
2026-08-26 13:01 ` ✓ CI.KUnit: success " Patchwork
2026-08-26 13:11 ` [CI] " sashiko-bot
2026-08-26 13:59 ` ✗ Xe.CI.BAT: failure for " Patchwork
2026-08-26 16:12 ` ✗ Xe.CI.FULL: " Patchwork
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