[v4 0/4] drm/i915/display: Enable AS SDP Skip Frames

Intel-XE Archive on lore.kernel.org
 help / color / mirror / Atom feed

* [v4 0/4] drm/i915/display: Enable AS SDP Skip Frames
@ 2026-08-31 21:34 Uma Shankar
  2026-08-31 21:20 ` ✗ CI.checkpatch: warning for drm/i915/display: Enable AS SDP Skip Frames (rev5) Patchwork
                   ` (7 more replies)
  0 siblings, 8 replies; 18+ messages in thread
From: Uma Shankar @ 2026-08-31 21:34 UTC (permalink / raw)
  To: intel-gfx, intel-xe; +Cc: dibin.moolakadan.subrahmanian, Uma Shankar

When Panel Replay is active the transcoder timing generator runs at the
panel's maximum refresh rate, but content is often presented at a lower
rate. In that case the Adaptive-Sync SDP (AS SDP) only needs to reach the
panel often enough to satisfy its maximum frame time, so transmitting it
on every frame is redundant and shows up as repeated SDPs on the link.

Xe3LPD adds a HW skip-frame counter in PR_ALPM_CTL that lets the source
send a single AS SDP and then suppress it for a programmed number of
frames. Program this counter so that one AS SDP is followed by
(max_vrefresh / flip_rate - 1) idle frames, matching the effective
content rate and allowing the link to be driven down to as low as 1Hz
when the hardware supports it.

v4:
 - Fix Sashiko review comments

v3:
 - Add module parameter
 - Fix Skip count clearing issue (Dibin)
 - Add DC3Co checks and enabling conditions

Uma Shankar (4):
  drm/i915/display: Enable periodic AS SDP skip frames
  drm/i915/display: Force disable DC3co when AS SDP skip frames is
    enabled
  drm/i915/display: Reprogram AS SDP skip frames on seamless VRR
    transitions
  drm/i915/display: Gate periodic AS SDP skip frames behind a module
    parameter

 drivers/gpu/drm/i915/display/intel_alpm.c     | 154 ++++++++++++++++--
 drivers/gpu/drm/i915/display/intel_alpm.h     |   3 +
 drivers/gpu/drm/i915/display/intel_display.c  |  18 ++
 .../drm/i915/display/intel_display_params.c   |   6 +
 .../drm/i915/display/intel_display_params.h   |   1 +
 .../drm/i915/display/intel_display_power.c    |   9 +
 drivers/gpu/drm/i915/display/intel_psr_regs.h |   2 +
 7 files changed, 177 insertions(+), 16 deletions(-)

-- 
2.50.1

^ permalink raw reply	[flat|nested] 18+ messages in thread

* ✗ CI.checkpatch: warning for drm/i915/display: Enable AS SDP Skip Frames (rev5)
  2026-08-31 21:34 [v4 0/4] drm/i915/display: Enable AS SDP Skip Frames Uma Shankar
@ 2026-08-31 21:20 ` Patchwork
  2026-08-31 21:22 ` ✓ CI.KUnit: success " Patchwork
                   ` (6 subsequent siblings)
  7 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2026-08-31 21:20 UTC (permalink / raw)
  To: Uma Shankar; +Cc: intel-xe

== Series Details ==

Series: drm/i915/display: Enable AS SDP Skip Frames (rev5)
URL   : https://patchwork.freedesktop.org/series/162015/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
061140b9bc586ae7f40abc1249c97e1cc72d1b9d
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit f5ae5574f3a63f4b14095ba5bc0de3c9261e026f
Author: Uma Shankar <uma.shankar@intel.com>
Date:   Tue Sep 1 03:04:21 2026 +0530

    drm/i915/display: Gate periodic AS SDP skip frames behind a module parameter
    
    Periodic AS SDP (skip frames) drives a Panel Replay panel down toward its
    minimum refresh rate. It is a new, panel- and platform-sensitive behaviour,
    so keep it opt-in rather than enabling it unconditionally.
    
    Add a display module parameter, periodic_assdp_enable, shared by both the
    i915 and xe drivers via the intel_display_params infrastructure. It defaults
    to false (feature disabled); set it to true to enable periodic AS SDP.
    
    Gate the feature at its single choke point, intel_pr_as_sdp_skip_frames():
    returning a zero skip count when the parameter is off makes both the
    PR_ALPM_CTL programming (intel_alpm_configure_pr_as_sdp()) and the DC3co
    force-disable predicate (intel_alpm_pr_as_sdp_skip_frames_enabled()) a no-op,
    so AS SDP continues to be sent on every frame as before.
    
    Assisted-by: Claude:claude-opus-4-8
    Signed-off-by: Uma Shankar <uma.shankar@intel.com>
+ /mt/dim checkpatch d60d982526a80c1e429e0ad7f5d92ec90af0cba6 drm-intel
ec4888607a8c drm/i915/display: Enable periodic AS SDP skip frames
-:121: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#121: FILE: drivers/gpu/drm/i915/display/intel_alpm.c:458:
+					pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE;

-:138: WARNING:LONG_LINE: line length of 125 exceeds 100 columns
#138: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:280:
+#define  PR_ALPM_CTL_AS_SDP_SKIP_FRAMES(frames)			REG_FIELD_PREP(PR_ALPM_CTL_AS_SDP_SKIP_FRAMES_MASK, (frames))

total: 0 errors, 2 warnings, 0 checks, 86 lines checked
1bb76d5696e4 drm/i915/display: Force disable DC3co when AS SDP skip frames is enabled
951f90890ea2 drm/i915/display: Reprogram AS SDP skip frames on seamless VRR transitions
f5ae5574f3a6 drm/i915/display: Gate periodic AS SDP skip frames behind a module parameter
-:12: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line (possible unwrapped commit description?)
#12: 
i915 and xe drivers via the intel_display_params infrastructure. It defaults

-:54: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#54: FILE: drivers/gpu/drm/i915/display/intel_display_params.c:143:
+intel_display_param_named_unsafe(periodic_assdp_enable, bool, 0600,
+	"Enable periodic Adaptive-Sync SDP (AS SDP skip frames) for Panel Replay "

total: 0 errors, 1 warnings, 1 checks, 35 lines checked



^ permalink raw reply	[flat|nested] 18+ messages in thread

* ✓ CI.KUnit: success for drm/i915/display: Enable AS SDP Skip Frames (rev5)
  2026-08-31 21:34 [v4 0/4] drm/i915/display: Enable AS SDP Skip Frames Uma Shankar
  2026-08-31 21:20 ` ✗ CI.checkpatch: warning for drm/i915/display: Enable AS SDP Skip Frames (rev5) Patchwork
@ 2026-08-31 21:22 ` Patchwork
  2026-08-31 21:34 ` [v4 1/4] drm/i915/display: Enable periodic AS SDP skip frames Uma Shankar
                   ` (5 subsequent siblings)
  7 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2026-08-31 21:22 UTC (permalink / raw)
  To: Uma Shankar; +Cc: intel-xe

== Series Details ==

Series: drm/i915/display: Enable AS SDP Skip Frames (rev5)
URL   : https://patchwork.freedesktop.org/series/162015/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[21:20:37] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:20:41] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[21:21:13] Starting KUnit Kernel (1/1)...
[21:21:13] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:21:14] ============= refcount_interrupt (4 subtests) ==============
[21:21:14] [PASSED] test_single_irq_change
[21:21:14] [PASSED] test_nested_irq_change
[21:21:14] [PASSED] test_multiple_irq_change
[21:21:14] [PASSED] test_irq_save
[21:21:14] =============== [PASSED] refcount_interrupt ================
[21:21:14] ================== guc_buf (11 subtests) ===================
[21:21:14] [PASSED] test_smallest
[21:21:14] [PASSED] test_largest
[21:21:14] [PASSED] test_granular
[21:21:14] [PASSED] test_unique
[21:21:14] [PASSED] test_overlap
[21:21:14] [PASSED] test_reusable
[21:21:14] [PASSED] test_too_big
[21:21:14] [PASSED] test_flush
[21:21:14] [PASSED] test_lookup
[21:21:14] [PASSED] test_data
[21:21:14] [PASSED] test_class
[21:21:14] ===================== [PASSED] guc_buf =====================
[21:21:14] =================== guc_dbm (7 subtests) ===================
[21:21:14] [PASSED] test_empty
[21:21:14] [PASSED] test_default
[21:21:14] ======================== test_size  ========================
[21:21:14] [PASSED] 4
[21:21:14] [PASSED] 8
[21:21:14] [PASSED] 32
[21:21:14] [PASSED] 256
[21:21:14] ==================== [PASSED] test_size ====================
[21:21:14] ======================= test_reuse  ========================
[21:21:14] [PASSED] 4
[21:21:14] [PASSED] 8
[21:21:14] [PASSED] 32
[21:21:14] [PASSED] 256
[21:21:14] =================== [PASSED] test_reuse ====================
[21:21:14] =================== test_range_overlap  ====================
[21:21:14] [PASSED] 4
[21:21:14] [PASSED] 8
[21:21:14] [PASSED] 32
[21:21:14] [PASSED] 256
[21:21:14] =============== [PASSED] test_range_overlap ================
[21:21:14] =================== test_range_compact  ====================
[21:21:14] [PASSED] 4
[21:21:14] [PASSED] 8
[21:21:14] [PASSED] 32
[21:21:14] [PASSED] 256
[21:21:14] =============== [PASSED] test_range_compact ================
[21:21:14] ==================== test_range_spare  =====================
[21:21:14] [PASSED] 4
[21:21:14] [PASSED] 8
[21:21:14] [PASSED] 32
[21:21:14] [PASSED] 256
[21:21:14] ================ [PASSED] test_range_spare =================
[21:21:14] ===================== [PASSED] guc_dbm =====================
[21:21:14] =================== guc_idm (6 subtests) ===================
[21:21:14] [PASSED] bad_init
[21:21:14] [PASSED] no_init
[21:21:14] [PASSED] init_fini
[21:21:14] [PASSED] check_used
[21:21:14] [PASSED] check_quota
[21:21:14] [PASSED] check_all
[21:21:14] ===================== [PASSED] guc_idm =====================
[21:21:14] =============== guc_klv_helpers (9 subtests) ===============
[21:21:14] [PASSED] test_count
[21:21:14] [PASSED] test_encode_u32
[21:21:14] [PASSED] test_encode_u64
[21:21:14] [PASSED] test_encode_string
[21:21:14] [PASSED] test_encode_object_raw
[21:21:14] [PASSED] test_encode_object_klv
[21:21:14] [PASSED] test_encode_object_nested
[21:21:14] [PASSED] test_encode_object_basic
[21:21:14] [PASSED] test_print
[21:21:14] ================= [PASSED] guc_klv_helpers =================
[21:21:14] =================== xe_log (4 subtests) ====================
[21:21:14] [PASSED] demo_cper
[21:21:14] [PASSED] demo_dmesg
[21:21:14] ======================= test_dmesg  ========================
[21:21:14] [PASSED] test_fatal
[21:21:14] [PASSED] test_fatal_tile
[21:21:14] [PASSED] test_fatal_gt
[21:21:14] [PASSED] test_fatal_comp
[21:21:14] [PASSED] test_fatal_comp_tile
[21:21:14] [PASSED] test_fatal_comp_gt
[21:21:14] [PASSED] test_fatal_all
[21:21:14] [PASSED] test_recoverable
[21:21:14] [PASSED] test_recoverable_tile
[21:21:14] [PASSED] test_recoverable_gt
[21:21:14] [PASSED] test_recoverable_comp
[21:21:14] [PASSED] test_recoverable_comp_tile
[21:21:14] [PASSED] test_recoverable_comp_gt
[21:21:14] [PASSED] test_recoverable_all
[21:21:14] [PASSED] test_info
[21:21:14] [PASSED] test_info_tile
[21:21:14] [PASSED] test_info_gt
[21:21:14] [PASSED] test_info_err
[21:21:14] [PASSED] test_info_comp
[21:21:14] [PASSED] test_info_comp_tile
[21:21:14] [PASSED] test_info_comp_gt
[21:21:14] [PASSED] test_info_all
[21:21:14] [PASSED] test_hw_fatal
[21:21:14] [PASSED] test_hw_recoverable
[21:21:14] [PASSED] test_hw_corrected
[21:21:14] [PASSED] test_hw_informational
[21:21:14] =================== [PASSED] test_dmesg ====================
[21:21:14] ====================== test_invalid  =======================
[21:21:14] [SKIPPED] no-component no-location no-warn (requires CONFIG_DRM_XE_DEBUG)
[21:21:14] [SKIPPED] reserved location (requires CONFIG_DRM_XE_DEBUG)
[21:21:14] [SKIPPED] unknown location (requires CONFIG_DRM_XE_DEBUG)
[21:21:14] [SKIPPED] nonzero-device-id location (requires CONFIG_DRM_XE_DEBUG)
[21:21:14] [SKIPPED] invalid-tile-id location (requires CONFIG_DRM_XE_DEBUG)
[21:21:14] [SKIPPED] invalid-gt-id location (requires CONFIG_DRM_XE_DEBUG)
[21:21:14] [SKIPPED] unknown component class (requires CONFIG_DRM_XE_DEBUG)
[21:21:14] [SKIPPED] unknown system component (requires CONFIG_DRM_XE_DEBUG)
[21:21:14] [SKIPPED] unknown hardware component (requires CONFIG_DRM_XE_DEBUG)
[21:21:14] [SKIPPED] unknown component and location (requires CONFIG_DRM_XE_DEBUG)
[21:21:14] ================== [SKIPPED] test_invalid ==================
[21:21:14] ===================== [PASSED] xe_log ======================
[21:21:14] ================== no_relay (3 subtests) ===================
[21:21:14] [PASSED] xe_drops_guc2pf_if_not_ready
[21:21:14] [PASSED] xe_drops_guc2vf_if_not_ready
[21:21:14] [PASSED] xe_rejects_send_if_not_ready
[21:21:14] ==================== [PASSED] no_relay =====================
[21:21:14] ================== pf_relay (14 subtests) ==================
[21:21:14] [PASSED] pf_rejects_guc2pf_too_short
[21:21:14] [PASSED] pf_rejects_guc2pf_too_long
[21:21:14] [PASSED] pf_rejects_guc2pf_no_payload
[21:21:14] [PASSED] pf_fails_no_payload
[21:21:14] [PASSED] pf_fails_bad_origin
[21:21:14] [PASSED] pf_fails_bad_type
[21:21:14] [PASSED] pf_txn_reports_error
[21:21:14] [PASSED] pf_txn_sends_pf2guc
[21:21:14] [PASSED] pf_sends_pf2guc
[21:21:14] [SKIPPED] pf_loopback_nop (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[21:21:14] [SKIPPED] pf_loopback_echo (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[21:21:14] [SKIPPED] pf_loopback_fail (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[21:21:14] [SKIPPED] pf_loopback_busy (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[21:21:14] [SKIPPED] pf_loopback_retry (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[21:21:14] ==================== [PASSED] pf_relay =====================
[21:21:14] ================== vf_relay (3 subtests) ===================
[21:21:14] [PASSED] vf_rejects_guc2vf_too_short
[21:21:14] [PASSED] vf_rejects_guc2vf_too_long
[21:21:14] [PASSED] vf_rejects_guc2vf_no_payload
[21:21:14] ==================== [PASSED] vf_relay =====================
[21:21:14] ================ pf_gt_config (9 subtests) =================
[21:21:14] [PASSED] fair_contexts_1vf
[21:21:14] [PASSED] fair_doorbells_1vf
[21:21:14] [PASSED] fair_ggtt_1vf
[21:21:14] ====================== fair_vram_1vf  ======================
[21:21:14] [PASSED] 3.50 GiB
[21:21:14] [PASSED] 11.5 GiB
[21:21:14] [PASSED] 15.5 GiB
[21:21:14] [PASSED] 31.5 GiB
[21:21:14] [PASSED] 63.5 GiB
[21:21:14] [PASSED] 1.91 GiB
[21:21:14] ================== [PASSED] fair_vram_1vf ==================
[21:21:14] ================ fair_vram_1vf_admin_only  =================
[21:21:14] [PASSED] 3.50 GiB
[21:21:14] [PASSED] 11.5 GiB
[21:21:14] [PASSED] 15.5 GiB
[21:21:14] [PASSED] 31.5 GiB
[21:21:14] [PASSED] 63.5 GiB
[21:21:14] [PASSED] 1.91 GiB
[21:21:14] ============ [PASSED] fair_vram_1vf_admin_only =============
[21:21:14] ====================== fair_contexts  ======================
[21:21:14] [PASSED] 1 VF
[21:21:14] [PASSED] 2 VFs
[21:21:14] [PASSED] 3 VFs
[21:21:14] [PASSED] 4 VFs
[21:21:14] [PASSED] 5 VFs
[21:21:14] [PASSED] 6 VFs
[21:21:14] [PASSED] 7 VFs
[21:21:14] [PASSED] 8 VFs
[21:21:14] [PASSED] 9 VFs
[21:21:14] [PASSED] 10 VFs
[21:21:14] [PASSED] 11 VFs
[21:21:14] [PASSED] 12 VFs
[21:21:14] [PASSED] 13 VFs
[21:21:14] [PASSED] 14 VFs
[21:21:14] [PASSED] 15 VFs
[21:21:14] [PASSED] 16 VFs
[21:21:14] [PASSED] 17 VFs
[21:21:14] [PASSED] 18 VFs
[21:21:14] [PASSED] 19 VFs
[21:21:14] [PASSED] 20 VFs
[21:21:14] [PASSED] 21 VFs
[21:21:14] [PASSED] 22 VFs
[21:21:14] [PASSED] 23 VFs
[21:21:14] [PASSED] 24 VFs
[21:21:14] [PASSED] 25 VFs
[21:21:14] [PASSED] 26 VFs
[21:21:14] [PASSED] 27 VFs
[21:21:14] [PASSED] 28 VFs
[21:21:14] [PASSED] 29 VFs
[21:21:14] [PASSED] 30 VFs
[21:21:14] [PASSED] 31 VFs
[21:21:14] [PASSED] 32 VFs
[21:21:14] [PASSED] 33 VFs
[21:21:14] [PASSED] 34 VFs
[21:21:14] [PASSED] 35 VFs
[21:21:14] [PASSED] 36 VFs
[21:21:14] [PASSED] 37 VFs
[21:21:14] [PASSED] 38 VFs
[21:21:14] [PASSED] 39 VFs
[21:21:14] [PASSED] 40 VFs
[21:21:14] [PASSED] 41 VFs
[21:21:14] [PASSED] 42 VFs
[21:21:14] [PASSED] 43 VFs
[21:21:14] [PASSED] 44 VFs
[21:21:14] [PASSED] 45 VFs
[21:21:14] [PASSED] 46 VFs
[21:21:14] [PASSED] 47 VFs
[21:21:14] [PASSED] 48 VFs
[21:21:14] [PASSED] 49 VFs
[21:21:14] [PASSED] 50 VFs
[21:21:14] [PASSED] 51 VFs
[21:21:14] [PASSED] 52 VFs
[21:21:14] [PASSED] 53 VFs
[21:21:14] [PASSED] 54 VFs
[21:21:14] [PASSED] 55 VFs
[21:21:14] [PASSED] 56 VFs
[21:21:14] [PASSED] 57 VFs
[21:21:14] [PASSED] 58 VFs
[21:21:14] [PASSED] 59 VFs
[21:21:14] [PASSED] 60 VFs
[21:21:14] [PASSED] 61 VFs
[21:21:14] [PASSED] 62 VFs
[21:21:14] [PASSED] 63 VFs
[21:21:14] ================== [PASSED] fair_contexts ==================
[21:21:14] ===================== fair_doorbells  ======================
[21:21:14] [PASSED] 1 VF
[21:21:14] [PASSED] 2 VFs
[21:21:14] [PASSED] 3 VFs
[21:21:14] [PASSED] 4 VFs
[21:21:14] [PASSED] 5 VFs
[21:21:14] [PASSED] 6 VFs
[21:21:14] [PASSED] 7 VFs
[21:21:14] [PASSED] 8 VFs
[21:21:14] [PASSED] 9 VFs
[21:21:14] [PASSED] 10 VFs
[21:21:14] [PASSED] 11 VFs
[21:21:14] [PASSED] 12 VFs
[21:21:14] [PASSED] 13 VFs
[21:21:14] [PASSED] 14 VFs
[21:21:14] [PASSED] 15 VFs
[21:21:14] [PASSED] 16 VFs
[21:21:14] [PASSED] 17 VFs
[21:21:14] [PASSED] 18 VFs
[21:21:14] [PASSED] 19 VFs
[21:21:14] [PASSED] 20 VFs
[21:21:14] [PASSED] 21 VFs
[21:21:14] [PASSED] 22 VFs
[21:21:14] [PASSED] 23 VFs
[21:21:14] [PASSED] 24 VFs
[21:21:14] [PASSED] 25 VFs
[21:21:14] [PASSED] 26 VFs
[21:21:14] [PASSED] 27 VFs
[21:21:14] [PASSED] 28 VFs
[21:21:14] [PASSED] 29 VFs
[21:21:14] [PASSED] 30 VFs
[21:21:14] [PASSED] 31 VFs
[21:21:14] [PASSED] 32 VFs
[21:21:14] [PASSED] 33 VFs
[21:21:14] [PASSED] 34 VFs
[21:21:14] [PASSED] 35 VFs
[21:21:14] [PASSED] 36 VFs
[21:21:14] [PASSED] 37 VFs
[21:21:14] [PASSED] 38 VFs
[21:21:14] [PASSED] 39 VFs
[21:21:14] [PASSED] 40 VFs
[21:21:14] [PASSED] 41 VFs
[21:21:14] [PASSED] 42 VFs
[21:21:14] [PASSED] 43 VFs
[21:21:14] [PASSED] 44 VFs
[21:21:14] [PASSED] 45 VFs
[21:21:14] [PASSED] 46 VFs
[21:21:14] [PASSED] 47 VFs
[21:21:14] [PASSED] 48 VFs
[21:21:14] [PASSED] 49 VFs
[21:21:14] [PASSED] 50 VFs
[21:21:14] [PASSED] 51 VFs
[21:21:14] [PASSED] 52 VFs
[21:21:14] [PASSED] 53 VFs
[21:21:14] [PASSED] 54 VFs
[21:21:14] [PASSED] 55 VFs
[21:21:14] [PASSED] 56 VFs
[21:21:14] [PASSED] 57 VFs
[21:21:14] [PASSED] 58 VFs
[21:21:14] [PASSED] 59 VFs
[21:21:14] [PASSED] 60 VFs
[21:21:14] [PASSED] 61 VFs
[21:21:14] [PASSED] 62 VFs
[21:21:14] [PASSED] 63 VFs
[21:21:14] ================= [PASSED] fair_doorbells ==================
[21:21:14] ======================== fair_ggtt  ========================
[21:21:14] [PASSED] 1 VF
[21:21:14] [PASSED] 2 VFs
[21:21:14] [PASSED] 3 VFs
[21:21:14] [PASSED] 4 VFs
[21:21:14] [PASSED] 5 VFs
[21:21:14] [PASSED] 6 VFs
[21:21:14] [PASSED] 7 VFs
[21:21:14] [PASSED] 8 VFs
[21:21:14] [PASSED] 9 VFs
[21:21:14] [PASSED] 10 VFs
[21:21:14] [PASSED] 11 VFs
[21:21:14] [PASSED] 12 VFs
[21:21:14] [PASSED] 13 VFs
[21:21:14] [PASSED] 14 VFs
[21:21:14] [PASSED] 15 VFs
[21:21:14] [PASSED] 16 VFs
[21:21:14] [PASSED] 17 VFs
[21:21:14] [PASSED] 18 VFs
[21:21:14] [PASSED] 19 VFs
[21:21:14] [PASSED] 20 VFs
[21:21:14] [PASSED] 21 VFs
[21:21:14] [PASSED] 22 VFs
[21:21:14] [PASSED] 23 VFs
[21:21:14] [PASSED] 24 VFs
[21:21:14] [PASSED] 25 VFs
[21:21:14] [PASSED] 26 VFs
[21:21:14] [PASSED] 27 VFs
[21:21:14] [PASSED] 28 VFs
[21:21:14] [PASSED] 29 VFs
[21:21:14] [PASSED] 30 VFs
[21:21:14] [PASSED] 31 VFs
[21:21:14] [PASSED] 32 VFs
[21:21:14] [PASSED] 33 VFs
[21:21:14] [PASSED] 34 VFs
[21:21:14] [PASSED] 35 VFs
[21:21:14] [PASSED] 36 VFs
[21:21:14] [PASSED] 37 VFs
[21:21:14] [PASSED] 38 VFs
[21:21:14] [PASSED] 39 VFs
[21:21:14] [PASSED] 40 VFs
[21:21:14] [PASSED] 41 VFs
[21:21:14] [PASSED] 42 VFs
[21:21:14] [PASSED] 43 VFs
[21:21:14] [PASSED] 44 VFs
[21:21:14] [PASSED] 45 VFs
[21:21:14] [PASSED] 46 VFs
[21:21:14] [PASSED] 47 VFs
[21:21:14] [PASSED] 48 VFs
[21:21:14] [PASSED] 49 VFs
[21:21:14] [PASSED] 50 VFs
[21:21:14] [PASSED] 51 VFs
[21:21:14] [PASSED] 52 VFs
[21:21:14] [PASSED] 53 VFs
[21:21:14] [PASSED] 54 VFs
[21:21:14] [PASSED] 55 VFs
[21:21:14] [PASSED] 56 VFs
[21:21:14] [PASSED] 57 VFs
[21:21:14] [PASSED] 58 VFs
[21:21:14] [PASSED] 59 VFs
[21:21:14] [PASSED] 60 VFs
[21:21:14] [PASSED] 61 VFs
[21:21:14] [PASSED] 62 VFs
[21:21:14] [PASSED] 63 VFs
[21:21:14] ==================== [PASSED] fair_ggtt ====================
[21:21:14] ======================== fair_vram  ========================
[21:21:14] [PASSED] 1 VF
[21:21:14] [PASSED] 2 VFs
[21:21:14] [PASSED] 3 VFs
[21:21:14] [PASSED] 4 VFs
[21:21:14] [PASSED] 5 VFs
[21:21:14] [PASSED] 6 VFs
[21:21:14] [PASSED] 7 VFs
[21:21:14] [PASSED] 8 VFs
[21:21:14] [PASSED] 9 VFs
[21:21:14] [PASSED] 10 VFs
[21:21:14] [PASSED] 11 VFs
[21:21:14] [PASSED] 12 VFs
[21:21:14] [PASSED] 13 VFs
[21:21:14] [PASSED] 14 VFs
[21:21:14] [PASSED] 15 VFs
[21:21:14] [PASSED] 16 VFs
[21:21:14] [PASSED] 17 VFs
[21:21:14] [PASSED] 18 VFs
[21:21:14] [PASSED] 19 VFs
[21:21:14] [PASSED] 20 VFs
[21:21:14] [PASSED] 21 VFs
[21:21:14] [PASSED] 22 VFs
[21:21:14] [PASSED] 23 VFs
[21:21:14] [PASSED] 24 VFs
[21:21:14] [PASSED] 25 VFs
[21:21:14] [PASSED] 26 VFs
[21:21:14] [PASSED] 27 VFs
[21:21:14] [PASSED] 28 VFs
[21:21:14] [PASSED] 29 VFs
[21:21:14] [PASSED] 30 VFs
[21:21:14] [PASSED] 31 VFs
[21:21:14] [PASSED] 32 VFs
[21:21:14] [PASSED] 33 VFs
[21:21:14] [PASSED] 34 VFs
[21:21:14] [PASSED] 35 VFs
[21:21:14] [PASSED] 36 VFs
[21:21:14] [PASSED] 37 VFs
[21:21:14] [PASSED] 38 VFs
[21:21:14] [PASSED] 39 VFs
[21:21:14] [PASSED] 40 VFs
[21:21:14] [PASSED] 41 VFs
[21:21:14] [PASSED] 42 VFs
[21:21:14] [PASSED] 43 VFs
[21:21:14] [PASSED] 44 VFs
[21:21:14] [PASSED] 45 VFs
[21:21:14] [PASSED] 46 VFs
[21:21:14] [PASSED] 47 VFs
[21:21:14] [PASSED] 48 VFs
[21:21:14] [PASSED] 49 VFs
[21:21:14] [PASSED] 50 VFs
[21:21:14] [PASSED] 51 VFs
[21:21:14] [PASSED] 52 VFs
[21:21:14] [PASSED] 53 VFs
[21:21:14] [PASSED] 54 VFs
[21:21:14] [PASSED] 55 VFs
[21:21:14] [PASSED] 56 VFs
[21:21:14] [PASSED] 57 VFs
[21:21:14] [PASSED] 58 VFs
[21:21:14] [PASSED] 59 VFs
[21:21:14] [PASSED] 60 VFs
[21:21:14] [PASSED] 61 VFs
[21:21:14] [PASSED] 62 VFs
[21:21:14] [PASSED] 63 VFs
[21:21:14] ==================== [PASSED] fair_vram ====================
[21:21:14] ================== [PASSED] pf_gt_config ===================
[21:21:14] ===================== lmtt (1 subtest) =====================
[21:21:14] ======================== test_ops  =========================
[21:21:14] [PASSED] 2-level
[21:21:14] [PASSED] multi-level
[21:21:14] ==================== [PASSED] test_ops =====================
[21:21:14] ====================== [PASSED] lmtt =======================
[21:21:14] ================= sriov_packet (1 subtest) =================
[21:21:14] [PASSED] test_descriptor_init
[21:21:14] ================== [PASSED] sriov_packet ===================
[21:21:14] ================= pf_service (11 subtests) =================
[21:21:14] [PASSED] pf_negotiate_any
[21:21:14] [PASSED] pf_negotiate_base_match
[21:21:14] [PASSED] pf_negotiate_base_newer
[21:21:14] [PASSED] pf_negotiate_base_next
[21:21:14] [SKIPPED] pf_negotiate_base_older (no older minor)
[21:21:14] [PASSED] pf_negotiate_base_prev
[21:21:14] [PASSED] pf_negotiate_latest_match
[21:21:14] [PASSED] pf_negotiate_latest_newer
[21:21:14] [PASSED] pf_negotiate_latest_next
[21:21:14] [SKIPPED] pf_negotiate_latest_older (no older minor)
[21:21:14] [SKIPPED] pf_negotiate_latest_prev (no prev major)
[21:21:14] =================== [PASSED] pf_service ====================
[21:21:14] ================= xe_guc_g2g (2 subtests) ==================
[21:21:14] ============== xe_live_guc_g2g_kunit_default  ==============
[21:21:14] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[21:21:14] ============== xe_live_guc_g2g_kunit_allmem  ===============
[21:21:14] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[21:21:14] =================== [SKIPPED] xe_guc_g2g ===================
[21:21:14] =================== xe_mocs (2 subtests) ===================
[21:21:14] ================ xe_live_mocs_kernel_kunit  ================
[21:21:14] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[21:21:14] ================ xe_live_mocs_reset_kunit  =================
[21:21:14] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[21:21:14] ==================== [SKIPPED] xe_mocs =====================
[21:21:14] ================= xe_migrate (2 subtests) ==================
[21:21:14] ================= xe_migrate_sanity_kunit  =================
[21:21:14] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[21:21:14] ================== xe_validate_ccs_kunit  ==================
[21:21:14] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[21:21:14] =================== [SKIPPED] xe_migrate ===================
[21:21:14] ================== xe_dma_buf (1 subtest) ==================
[21:21:14] ==================== xe_dma_buf_kunit  =====================
[21:21:14] ================ [SKIPPED] xe_dma_buf_kunit ================
[21:21:14] =================== [SKIPPED] xe_dma_buf ===================
[21:21:14] ================= xe_bo_shrink (1 subtest) =================
[21:21:14] =================== xe_bo_shrink_kunit  ====================
[21:21:14] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[21:21:14] ================== [SKIPPED] xe_bo_shrink ==================
[21:21:14] ==================== xe_bo (2 subtests) ====================
[21:21:14] ================== xe_ccs_migrate_kunit  ===================
[21:21:14] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[21:21:14] ==================== xe_bo_evict_kunit  ====================
[21:21:14] =============== [SKIPPED] xe_bo_evict_kunit ================
[21:21:14] ===================== [SKIPPED] xe_bo ======================
[21:21:14] =================== xe_any (9 subtests) ====================
[21:21:14] [PASSED] test_to_xe
[21:21:14] [PASSED] test_to_dev
[21:21:14] [PASSED] test_to_pdev
[21:21:14] [PASSED] test_to_drm
[21:21:14] [PASSED] test_if_pdev
[21:21:14] [PASSED] test_if_xe
[21:21:14] [PASSED] test_if_tile
[21:21:14] [PASSED] test_if_gt
[21:21:14] [PASSED] test_to_id
[21:21:14] ===================== [PASSED] xe_any ======================
[21:21:14] ==================== args (13 subtests) ====================
[21:21:14] [PASSED] count_args_test
[21:21:14] [PASSED] call_args_example
[21:21:14] [PASSED] call_args_test
[21:21:14] [PASSED] drop_first_arg_example
[21:21:14] [PASSED] drop_first_arg_test
[21:21:14] [PASSED] first_arg_example
[21:21:14] [PASSED] first_arg_test
[21:21:14] [PASSED] last_arg_example
[21:21:14] [PASSED] last_arg_test
[21:21:14] [PASSED] pick_arg_example
[21:21:14] [PASSED] if_args_example
[21:21:14] [PASSED] if_args_test
[21:21:14] [PASSED] sep_comma_example
[21:21:14] ====================== [PASSED] args =======================
[21:21:14] =================== xe_pci (3 subtests) ====================
[21:21:14] ==================== check_graphics_ip  ====================
[21:21:14] [PASSED] 12.00 Xe_LP
[21:21:14] [PASSED] 12.10 Xe_LP+
[21:21:14] [PASSED] 12.55 Xe_HPG
[21:21:14] [PASSED] 12.60 Xe_HPC
[21:21:14] [PASSED] 12.70 Xe_LPG
[21:21:14] [PASSED] 12.71 Xe_LPG
[21:21:14] [PASSED] 12.74 Xe_LPG+
[21:21:14] [PASSED] 20.01 Xe2_HPG
[21:21:14] [PASSED] 20.02 Xe2_HPG
[21:21:14] [PASSED] 20.04 Xe2_LPG
[21:21:14] [PASSED] 30.00 Xe3_LPG
[21:21:14] [PASSED] 30.01 Xe3_LPG
[21:21:14] [PASSED] 30.03 Xe3_LPG
[21:21:14] [PASSED] 30.04 Xe3_LPG
[21:21:14] [PASSED] 30.05 Xe3_LPG
[21:21:14] [PASSED] 35.10 Xe3p_LPG
[21:21:14] [PASSED] 35.11 Xe3p_XPC
[21:21:14] ================ [PASSED] check_graphics_ip ================
[21:21:14] ===================== check_media_ip  ======================
[21:21:14] [PASSED] 12.00 Xe_M
[21:21:14] [PASSED] 12.55 Xe_HPM
[21:21:14] [PASSED] 13.00 Xe_LPM+
[21:21:14] [PASSED] 13.01 Xe2_HPM
[21:21:14] [PASSED] 20.00 Xe2_LPM
[21:21:14] [PASSED] 30.00 Xe3_LPM
[21:21:14] [PASSED] 30.02 Xe3_LPM
[21:21:14] [PASSED] 35.00 Xe3p_LPM
[21:21:14] [PASSED] 35.03 Xe3p_HPM
[21:21:14] ================= [PASSED] check_media_ip ==================
[21:21:14] =================== check_platform_desc  ===================
[21:21:14] [PASSED] 0x9A60 (TIGERLAKE)
[21:21:14] [PASSED] 0x9A68 (TIGERLAKE)
[21:21:14] [PASSED] 0x9A70 (TIGERLAKE)
[21:21:14] [PASSED] 0x9A40 (TIGERLAKE)
[21:21:14] [PASSED] 0x9A49 (TIGERLAKE)
[21:21:14] [PASSED] 0x9A59 (TIGERLAKE)
[21:21:14] [PASSED] 0x9A78 (TIGERLAKE)
[21:21:14] [PASSED] 0x9AC0 (TIGERLAKE)
[21:21:14] [PASSED] 0x9AC9 (TIGERLAKE)
[21:21:14] [PASSED] 0x9AD9 (TIGERLAKE)
[21:21:14] [PASSED] 0x9AF8 (TIGERLAKE)
[21:21:14] [PASSED] 0x4C80 (ROCKETLAKE)
[21:21:14] [PASSED] 0x4C8A (ROCKETLAKE)
[21:21:14] [PASSED] 0x4C8B (ROCKETLAKE)
[21:21:14] [PASSED] 0x4C8C (ROCKETLAKE)
[21:21:14] [PASSED] 0x4C90 (ROCKETLAKE)
[21:21:14] [PASSED] 0x4C9A (ROCKETLAKE)
[21:21:14] [PASSED] 0x4680 (ALDERLAKE_S)
[21:21:14] [PASSED] 0x4682 (ALDERLAKE_S)
[21:21:14] [PASSED] 0x4688 (ALDERLAKE_S)
[21:21:14] [PASSED] 0x468A (ALDERLAKE_S)
[21:21:14] [PASSED] 0x468B (ALDERLAKE_S)
[21:21:14] [PASSED] 0x4690 (ALDERLAKE_S)
[21:21:14] [PASSED] 0x4692 (ALDERLAKE_S)
[21:21:14] [PASSED] 0x4693 (ALDERLAKE_S)
[21:21:14] [PASSED] 0x46A0 (ALDERLAKE_P)
[21:21:14] [PASSED] 0x46A1 (ALDERLAKE_P)
[21:21:14] [PASSED] 0x46A2 (ALDERLAKE_P)
[21:21:14] [PASSED] 0x46A3 (ALDERLAKE_P)
[21:21:14] [PASSED] 0x46A6 (ALDERLAKE_P)
[21:21:14] [PASSED] 0x46A8 (ALDERLAKE_P)
[21:21:14] [PASSED] 0x46AA (ALDERLAKE_P)
[21:21:14] [PASSED] 0x462A (ALDERLAKE_P)
[21:21:14] [PASSED] 0x4626 (ALDERLAKE_P)
[21:21:14] [PASSED] 0x4628 (ALDERLAKE_P)
[21:21:14] [PASSED] 0x46B0 (ALDERLAKE_P)
[21:21:14] [PASSED] 0x46B1 (ALDERLAKE_P)
[21:21:14] [PASSED] 0x46B2 (ALDERLAKE_P)
[21:21:14] [PASSED] 0x46B3 (ALDERLAKE_P)
[21:21:14] [PASSED] 0x46C0 (ALDERLAKE_P)
[21:21:14] [PASSED] 0x46C1 (ALDERLAKE_P)
[21:21:14] [PASSED] 0x46C2 (ALDERLAKE_P)
[21:21:14] [PASSED] 0x46C3 (ALDERLAKE_P)
[21:21:14] [PASSED] 0x46D0 (ALDERLAKE_N)
[21:21:14] [PASSED] 0x46D1 (ALDERLAKE_N)
[21:21:14] [PASSED] 0x46D2 (ALDERLAKE_N)
[21:21:14] [PASSED] 0x46D3 (ALDERLAKE_N)
[21:21:14] [PASSED] 0x46D4 (ALDERLAKE_N)
[21:21:14] [PASSED] 0xA721 (ALDERLAKE_P)
[21:21:14] [PASSED] 0xA7A1 (ALDERLAKE_P)
[21:21:14] [PASSED] 0xA7A9 (ALDERLAKE_P)
[21:21:14] [PASSED] 0xA7AC (ALDERLAKE_P)
[21:21:14] [PASSED] 0xA7AD (ALDERLAKE_P)
[21:21:14] [PASSED] 0xA720 (ALDERLAKE_P)
[21:21:14] [PASSED] 0xA7A0 (ALDERLAKE_P)
[21:21:14] [PASSED] 0xA7A8 (ALDERLAKE_P)
[21:21:14] [PASSED] 0xA7AA (ALDERLAKE_P)
[21:21:14] [PASSED] 0xA7AB (ALDERLAKE_P)
[21:21:14] [PASSED] 0xA780 (ALDERLAKE_S)
[21:21:14] [PASSED] 0xA781 (ALDERLAKE_S)
[21:21:14] [PASSED] 0xA782 (ALDERLAKE_S)
[21:21:14] [PASSED] 0xA783 (ALDERLAKE_S)
[21:21:14] [PASSED] 0xA788 (ALDERLAKE_S)
[21:21:14] [PASSED] 0xA789 (ALDERLAKE_S)
[21:21:14] [PASSED] 0xA78A (ALDERLAKE_S)
[21:21:14] [PASSED] 0xA78B (ALDERLAKE_S)
[21:21:14] [PASSED] 0x4905 (DG1)
[21:21:14] [PASSED] 0x4906 (DG1)
[21:21:14] [PASSED] 0x4907 (DG1)
[21:21:14] [PASSED] 0x4908 (DG1)
[21:21:14] [PASSED] 0x4909 (DG1)
[21:21:14] [PASSED] 0x56C0 (DG2)
[21:21:14] [PASSED] 0x56C2 (DG2)
[21:21:14] [PASSED] 0x56C1 (DG2)
[21:21:14] [PASSED] 0x7D51 (METEORLAKE)
[21:21:14] [PASSED] 0x7DD1 (METEORLAKE)
[21:21:14] [PASSED] 0x7D41 (METEORLAKE)
[21:21:14] [PASSED] 0x7D67 (METEORLAKE)
[21:21:14] [PASSED] 0xB640 (METEORLAKE)
[21:21:14] [PASSED] 0x56A0 (DG2)
[21:21:14] [PASSED] 0x56A1 (DG2)
[21:21:14] [PASSED] 0x56A2 (DG2)
[21:21:14] [PASSED] 0x56BE (DG2)
[21:21:14] [PASSED] 0x56BF (DG2)
[21:21:14] [PASSED] 0x5690 (DG2)
[21:21:14] [PASSED] 0x5691 (DG2)
[21:21:14] [PASSED] 0x5692 (DG2)
[21:21:14] [PASSED] 0x56A5 (DG2)
[21:21:14] [PASSED] 0x56A6 (DG2)
[21:21:14] [PASSED] 0x56B0 (DG2)
[21:21:14] [PASSED] 0x56B1 (DG2)
[21:21:14] [PASSED] 0x56BA (DG2)
[21:21:14] [PASSED] 0x56BB (DG2)
[21:21:14] [PASSED] 0x56BC (DG2)
[21:21:14] [PASSED] 0x56BD (DG2)
[21:21:14] [PASSED] 0x5693 (DG2)
[21:21:14] [PASSED] 0x5694 (DG2)
[21:21:14] [PASSED] 0x5695 (DG2)
[21:21:14] [PASSED] 0x56A3 (DG2)
[21:21:14] [PASSED] 0x56A4 (DG2)
[21:21:14] [PASSED] 0x56B2 (DG2)
[21:21:14] [PASSED] 0x56B3 (DG2)
[21:21:14] [PASSED] 0x5696 (DG2)
[21:21:14] [PASSED] 0x5697 (DG2)
[21:21:14] [PASSED] 0xB69 (PVC)
[21:21:14] [PASSED] 0xB6E (PVC)
[21:21:14] [PASSED] 0xBD4 (PVC)
[21:21:14] [PASSED] 0xBD5 (PVC)
[21:21:14] [PASSED] 0xBD6 (PVC)
[21:21:14] [PASSED] 0xBD7 (PVC)
[21:21:14] [PASSED] 0xBD8 (PVC)
[21:21:14] [PASSED] 0xBD9 (PVC)
[21:21:14] [PASSED] 0xBDA (PVC)
[21:21:14] [PASSED] 0xBDB (PVC)
[21:21:14] [PASSED] 0xBE0 (PVC)
[21:21:14] [PASSED] 0xBE1 (PVC)
[21:21:14] [PASSED] 0xBE5 (PVC)
[21:21:14] [PASSED] 0x7D40 (METEORLAKE)
[21:21:14] [PASSED] 0x7D45 (METEORLAKE)
[21:21:14] [PASSED] 0x7D55 (METEORLAKE)
[21:21:14] [PASSED] 0x7D60 (METEORLAKE)
[21:21:14] [PASSED] 0x7DD5 (METEORLAKE)
[21:21:14] [PASSED] 0x6420 (LUNARLAKE)
[21:21:14] [PASSED] 0x64A0 (LUNARLAKE)
[21:21:14] [PASSED] 0x64B0 (LUNARLAKE)
[21:21:14] [PASSED] 0xE202 (BATTLEMAGE)
[21:21:14] [PASSED] 0xE209 (BATTLEMAGE)
[21:21:14] [PASSED] 0xE20B (BATTLEMAGE)
[21:21:14] [PASSED] 0xE20C (BATTLEMAGE)
[21:21:14] [PASSED] 0xE20D (BATTLEMAGE)
[21:21:14] [PASSED] 0xE210 (BATTLEMAGE)
[21:21:14] [PASSED] 0xE211 (BATTLEMAGE)
[21:21:14] [PASSED] 0xE212 (BATTLEMAGE)
[21:21:14] [PASSED] 0xE216 (BATTLEMAGE)
[21:21:14] [PASSED] 0xE220 (BATTLEMAGE)
[21:21:14] [PASSED] 0xE221 (BATTLEMAGE)
[21:21:14] [PASSED] 0xE222 (BATTLEMAGE)
[21:21:14] [PASSED] 0xE223 (BATTLEMAGE)
[21:21:14] [PASSED] 0xB080 (PANTHERLAKE)
[21:21:14] [PASSED] 0xB081 (PANTHERLAKE)
[21:21:14] [PASSED] 0xB082 (PANTHERLAKE)
[21:21:14] [PASSED] 0xB083 (PANTHERLAKE)
[21:21:14] [PASSED] 0xB084 (PANTHERLAKE)
[21:21:14] [PASSED] 0xB085 (PANTHERLAKE)
[21:21:14] [PASSED] 0xB086 (PANTHERLAKE)
[21:21:14] [PASSED] 0xB087 (PANTHERLAKE)
[21:21:14] [PASSED] 0xB08F (PANTHERLAKE)
[21:21:14] [PASSED] 0xB090 (PANTHERLAKE)
[21:21:14] [PASSED] 0xB0A0 (PANTHERLAKE)
[21:21:14] [PASSED] 0xB0B0 (PANTHERLAKE)
[21:21:14] [PASSED] 0xFD80 (PANTHERLAKE)
[21:21:14] [PASSED] 0xFD81 (PANTHERLAKE)
[21:21:14] [PASSED] 0xD740 (NOVALAKE_S)
[21:21:14] [PASSED] 0xD741 (NOVALAKE_S)
[21:21:14] [PASSED] 0xD742 (NOVALAKE_S)
[21:21:14] [PASSED] 0xD743 (NOVALAKE_S)
[21:21:14] [PASSED] 0xD745 (NOVALAKE_S)
[21:21:14] [PASSED] 0xD74A (NOVALAKE_S)
[21:21:14] [PASSED] 0xD74B (NOVALAKE_S)
[21:21:14] [PASSED] 0x674C (CRESCENTISLAND)
[21:21:14] [PASSED] 0x674D (CRESCENTISLAND)
[21:21:14] [PASSED] 0x674E (CRESCENTISLAND)
[21:21:14] [PASSED] 0x674F (CRESCENTISLAND)
[21:21:14] [PASSED] 0x6750 (CRESCENTISLAND)
[21:21:14] [PASSED] 0xD750 (NOVALAKE_P)
[21:21:14] [PASSED] 0xD751 (NOVALAKE_P)
[21:21:14] [PASSED] 0xD752 (NOVALAKE_P)
[21:21:14] [PASSED] 0xD753 (NOVALAKE_P)
[21:21:14] [PASSED] 0xD754 (NOVALAKE_P)
[21:21:14] [PASSED] 0xD755 (NOVALAKE_P)
[21:21:14] [PASSED] 0xD756 (NOVALAKE_P)
[21:21:14] [PASSED] 0xD757 (NOVALAKE_P)
[21:21:14] [PASSED] 0xD75F (NOVALAKE_P)
[21:21:14] =============== [PASSED] check_platform_desc ===============
[21:21:14] ===================== [PASSED] xe_pci ======================
[21:21:14] ============= xe_rtp_tables_test (5 subtests) ==============
[21:21:14] ================== xe_rtp_table_gt_test  ===================
[21:21:14] [PASSED] gt_was/14011060649
[21:21:14] [PASSED] gt_was/14011059788
[21:21:14] [PASSED] gt_was/14015795083
[21:21:14] [PASSED] gt_was/16021867713
[21:21:14] [PASSED] gt_was/14019449301
[21:21:14] [PASSED] gt_was/16028005424
[21:21:14] [PASSED] gt_was/14026578760
[21:21:14] [PASSED] gt_was/1409420604
[21:21:14] [PASSED] gt_was/1408615072
[21:21:14] [PASSED] gt_was/22010523718
[21:21:14] [PASSED] gt_was/14011006942
[21:21:14] [PASSED] gt_was/14014830051
[21:21:14] [PASSED] gt_was/18018781329
[21:21:14] [PASSED] gt_was/1509235366
[21:21:14] [PASSED] gt_was/18018781329
[21:21:14] [PASSED] gt_was/16016694945
[21:21:14] [PASSED] gt_was/14018575942
[21:21:14] [PASSED] gt_was/22016670082
[21:21:14] [PASSED] gt_was/22016670082
[21:21:14] [PASSED] gt_was/14017421178
[21:21:14] [PASSED] gt_was/16025250150
[21:21:14] [PASSED] gt_was/14021871409
[21:21:14] [PASSED] gt_was/16021865536
[21:21:14] [PASSED] gt_was/14021486841
[21:21:14] [PASSED] gt_was/14025160223
[21:21:14] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[21:21:14] [PASSED] gt_was/14025635424
[21:21:14] [PASSED] gt_was/16028005424
[21:21:14] ============== [PASSED] xe_rtp_table_gt_test ===============
[21:21:14] ================== xe_rtp_table_gt_test  ===================
[21:21:14] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[21:21:14] [PASSED] gt_tunings/Tuning: 32B Access Enable
[21:21:14] [PASSED] gt_tunings/Tuning: L3 cache
[21:21:14] [PASSED] gt_tunings/Tuning: L3 cache - media
[21:21:14] [PASSED] gt_tunings/Tuning: Compression Overfetch
[21:21:14] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[21:21:14] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[21:21:14] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[21:21:14] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[21:21:14] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[21:21:14] [PASSED] gt_tunings/Tuning: Stateless compression control
[21:21:14] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[21:21:14] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[21:21:14] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[21:21:14] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[21:21:14] ============== [PASSED] xe_rtp_table_gt_test ===============
[21:21:14] ================== xe_rtp_table_oob_test  ==================
[21:21:14] [PASSED] oob_was/1607983814
[21:21:14] [PASSED] oob_was/16010904313
[21:21:14] [PASSED] oob_was/18022495364
[21:21:14] [PASSED] oob_was/22012773006
[21:21:14] [PASSED] oob_was/14014475959
[21:21:14] [PASSED] oob_was/22011391025
[21:21:14] [PASSED] oob_was/22012727170
[21:21:14] [PASSED] oob_was/22012727685
[21:21:14] [PASSED] oob_was/22016596838
[21:21:14] [PASSED] oob_was/18020744125
[21:21:14] [PASSED] oob_was/1409600907
[21:21:14] [PASSED] oob_was/22014953428
[21:21:14] [PASSED] oob_was/16017236439
[21:21:14] [PASSED] oob_was/14019821291
[21:21:14] [PASSED] oob_was/14015076503
[21:21:14] [PASSED] oob_was/14018913170
[21:21:14] [PASSED] oob_was/14018094691
[21:21:14] [PASSED] oob_was/18024947630
[21:21:14] [PASSED] oob_was/16022287689
[21:21:14] [PASSED] oob_was/13011645652
[21:21:14] [PASSED] oob_was/14022293748
[21:21:14] [PASSED] oob_was/22019794406
[21:21:14] [PASSED] oob_was/22019338487
[21:21:14] [PASSED] oob_was/16023588340
[21:21:14] [PASSED] oob_was/14019789679
[21:21:14] [PASSED] oob_was/14022866841
[21:21:14] [PASSED] oob_was/16021333562
[21:21:14] [PASSED] oob_was/14016712196
[21:21:14] [PASSED] oob_was/14015568240
[21:21:14] [PASSED] oob_was/18013179988
[21:21:14] [PASSED] oob_was/1508761755
[21:21:14] [PASSED] oob_was/16023105232
[21:21:14] [PASSED] oob_was/16026508708
[21:21:14] [PASSED] oob_was/14020001231
[21:21:14] [PASSED] oob_was/16023683509
[21:21:14] [PASSED] oob_was/14025515070
[21:21:14] [PASSED] oob_was/15015404425_disable
[21:21:14] [PASSED] oob_was/16026007364
[21:21:14] [PASSED] oob_was/14020316580
[21:21:14] [PASSED] oob_was/14025883347
[21:21:14] [PASSED] oob_was/16029380221
[21:21:14] [PASSED] oob_was/22022079272
[21:21:14] [PASSED] oob_was/16029897822
[21:21:14] [PASSED] oob_was/14027054324
[21:21:14] ============== [PASSED] xe_rtp_table_oob_test ==============
[21:21:14] ================ xe_rtp_table_dev_oob_test  ================
[21:21:14] [PASSED] device_oob_was/22010954014
[21:21:14] [PASSED] device_oob_was/15015404425
[21:21:14] [PASSED] device_oob_was/22019338487_display
[21:21:14] [PASSED] device_oob_was/14022085890
[21:21:14] [PASSED] device_oob_was/14026539277
[21:21:14] [PASSED] device_oob_was/14026633728
[21:21:14] [PASSED] device_oob_was/14026746987
[21:21:14] [PASSED] device_oob_was/14026779378
[21:21:14] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[21:21:14] ========== xe_rtp_table_missing_upper_bound_test  ==========
[21:21:14] [PASSED] register_whitelist/WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865
[21:21:14] [PASSED] register_whitelist/1508744258, 14012131227, 1808121037
[21:21:14] [PASSED] register_whitelist/1806527549
[21:21:14] [PASSED] register_whitelist/allow_read_ctx_timestamp
[21:21:14] [PASSED] register_whitelist/allow_read_queue_timestamp
[21:21:14] [PASSED] register_whitelist/16014440446
[21:21:14] [PASSED] register_whitelist/16017236439
[21:21:14] [PASSED] register_whitelist/16020183090
[21:21:14] [PASSED] register_whitelist/14024997852
[21:21:14] [PASSED] register_whitelist/14024997852
[21:21:14] ====== [PASSED] xe_rtp_table_missing_upper_bound_test ======
[21:21:14] =============== [PASSED] xe_rtp_tables_test ================
[21:21:14] =================== xe_rtp (3 subtests) ====================
[21:21:14] =================== xe_rtp_rules_tests  ====================
[21:21:14] [PASSED] no
[21:21:14] [PASSED] yes
[21:21:14] [PASSED] no-and-no
[21:21:14] [PASSED] no-and-yes
[21:21:14] [PASSED] yes-and-no
[21:21:14] [PASSED] yes-and-yes
[21:21:14] [PASSED] no-or-no
[21:21:14] [PASSED] no-or-yes
[21:21:14] [PASSED] yes-or-no
[21:21:14] [PASSED] yes-or-yes
[21:21:14] [PASSED] no-yes-or-yes-no
[21:21:14] [PASSED] no-yes-or-yes-yes
[21:21:14] [PASSED] yes-yes-or-no-yes
[21:21:14] [PASSED] yes-yes-or-yes-yes
[21:21:14] [PASSED] no-no-or-yes-or-no
[21:21:14] [PASSED] or
[21:21:14] [PASSED] or-yes
[21:21:14] [PASSED] or-no
[21:21:14] [PASSED] yes-or
[21:21:14] [PASSED] no-or
[21:21:14] [PASSED] no-or-or-yes
[21:21:14] [PASSED] yes-or-or-no
[21:21:14] [PASSED] no-or-or-no
[21:21:14] [PASSED] missing-context-engine-class
[21:21:14] [PASSED] missing-context-engine-class-or-yes
[21:21:14] [PASSED] missing-context-engine-class-or-or-yes
[21:21:14] =============== [PASSED] xe_rtp_rules_tests ================
[21:21:14] =============== xe_rtp_process_to_sr_tests  ================
[21:21:14] [PASSED] coalesce-same-reg
[21:21:14] [PASSED] coalesce-same-reg-literal-and-func
[21:21:14] [PASSED] no-match-no-add
[21:21:14] [PASSED] two-regs-two-entries
[21:21:14] [PASSED] clr-one-set-other
[21:21:14] [PASSED] set-field
[21:21:14] [PASSED] conflict-duplicate
[21:21:14] [PASSED] conflict-not-disjoint
[21:21:14] [PASSED] conflict-not-disjoint-literal-and-func
[21:21:14] [PASSED] conflict-reg-type
[21:21:14] [PASSED] bad-mcr-reg-forced-to-regular
[21:21:14] [PASSED] bad-regular-reg-forced-to-mcr
[21:21:14] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[21:21:14] ================== xe_rtp_process_tests  ===================
[21:21:14] [PASSED] active1
[21:21:14] [PASSED] active2
[21:21:14] [PASSED] active-inactive
[21:21:14] [PASSED] inactive-active
[21:21:14] [PASSED] inactive-active-inactive
[21:21:14] [PASSED] inactive-inactive-inactive
[21:21:14] ============== [PASSED] xe_rtp_process_tests ===============
[21:21:14] ===================== [PASSED] xe_rtp ======================
[21:21:14] ==================== xe_wa (1 subtest) =====================
[21:21:14] ======================== xe_wa_gt  =========================
[21:21:14] [PASSED] TIGERLAKE B0
[21:21:14] [PASSED] DG1 A0
[21:21:14] [PASSED] DG1 B0
[21:21:14] [PASSED] ALDERLAKE_S A0
[21:21:14] [PASSED] ALDERLAKE_S B0
[21:21:14] [PASSED] ALDERLAKE_S C0
[21:21:14] [PASSED] ALDERLAKE_S D0
[21:21:14] [PASSED] ALDERLAKE_P A0
[21:21:14] [PASSED] ALDERLAKE_P B0
[21:21:14] [PASSED] ALDERLAKE_P C0
[21:21:14] [PASSED] ALDERLAKE_S RPLS D0
[21:21:14] [PASSED] ALDERLAKE_P RPLU E0
[21:21:14] [PASSED] DG2 G10 C0
[21:21:14] [PASSED] DG2 G11 B1
[21:21:14] [PASSED] DG2 G12 A1
[21:21:14] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[21:21:14] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[21:21:14] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[21:21:14] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[21:21:14] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[21:21:14] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[21:21:14] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[21:21:14] ==================== [PASSED] xe_wa_gt =====================
[21:21:14] ====================== [PASSED] xe_wa ======================
[21:21:14] ============================================================
[21:21:14] Testing complete. Ran 793 tests: passed: 765, skipped: 28
[21:21:14] Elapsed time: 37.184s total, 4.435s configuring, 32.033s building, 0.695s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[21:21:14] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:21:16] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[21:21:41] Starting KUnit Kernel (1/1)...
[21:21:41] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:21:41] ============= refcount_interrupt (4 subtests) ==============
[21:21:41] [PASSED] test_single_irq_change
[21:21:41] [PASSED] test_nested_irq_change
[21:21:41] [PASSED] test_multiple_irq_change
[21:21:41] [PASSED] test_irq_save
[21:21:41] =============== [PASSED] refcount_interrupt ================
[21:21:41] ============ drm_test_pick_cmdline (2 subtests) ============
[21:21:41] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[21:21:41] =============== drm_test_pick_cmdline_named  ===============
[21:21:41] [PASSED] NTSC
[21:21:41] [PASSED] NTSC-J
[21:21:41] [PASSED] PAL
[21:21:41] [PASSED] PAL-M
[21:21:41] =========== [PASSED] drm_test_pick_cmdline_named ===========
[21:21:41] ============== [PASSED] drm_test_pick_cmdline ==============
[21:21:41] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[21:21:41] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[21:21:41] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[21:21:41] =========== drm_validate_clone_mode (2 subtests) ===========
[21:21:41] ============== drm_test_check_in_clone_mode  ===============
[21:21:41] [PASSED] in_clone_mode
[21:21:41] [PASSED] not_in_clone_mode
[21:21:41] ========== [PASSED] drm_test_check_in_clone_mode ===========
[21:21:41] =============== drm_test_check_valid_clones  ===============
[21:21:41] [PASSED] not_in_clone_mode
[21:21:41] [PASSED] valid_clone
[21:21:41] [PASSED] invalid_clone
[21:21:41] =========== [PASSED] drm_test_check_valid_clones ===========
[21:21:41] ============= [PASSED] drm_validate_clone_mode =============
[21:21:41] ============= drm_validate_modeset (1 subtest) =============
[21:21:41] [PASSED] drm_test_check_connector_changed_modeset
[21:21:41] ============== [PASSED] drm_validate_modeset ===============
[21:21:41] ====== drm_test_bridge_get_current_state (1 subtest) =======
[21:21:41] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[21:21:41] ======== [PASSED] drm_test_bridge_get_current_state ========
[21:21:41] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[21:21:41] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[21:21:41] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[21:21:41] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[21:21:41] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[21:21:41] ============== drm_bridge_alloc (2 subtests) ===============
[21:21:41] [PASSED] drm_test_drm_bridge_alloc_basic
[21:21:41] [PASSED] drm_test_drm_bridge_alloc_get_put
[21:21:41] ================ [PASSED] drm_bridge_alloc =================
[21:21:41] ============= drm_bridge_bus_fmt (5 subtests) ==============
[21:21:41] [PASSED] drm_test_bridge_rgb_yuv_rgb
[21:21:41] [PASSED] drm_test_bridge_must_convert_to_yuv444
[21:21:41] [PASSED] drm_test_bridge_hdmi_auto_rgb
[21:21:41] [PASSED] drm_test_bridge_auto_first
[21:21:41] [PASSED] drm_test_bridge_rgb_yuv_no_path
[21:21:41] =============== [PASSED] drm_bridge_bus_fmt ================
[21:21:41] ============= drm_cmdline_parser (40 subtests) =============
[21:21:41] [PASSED] drm_test_cmdline_force_d_only
[21:21:41] [PASSED] drm_test_cmdline_force_D_only_dvi
[21:21:41] [PASSED] drm_test_cmdline_force_D_only_hdmi
[21:21:41] [PASSED] drm_test_cmdline_force_D_only_not_digital
[21:21:41] [PASSED] drm_test_cmdline_force_e_only
[21:21:41] [PASSED] drm_test_cmdline_res
[21:21:41] [PASSED] drm_test_cmdline_res_vesa
[21:21:41] [PASSED] drm_test_cmdline_res_vesa_rblank
[21:21:41] [PASSED] drm_test_cmdline_res_rblank
[21:21:41] [PASSED] drm_test_cmdline_res_bpp
[21:21:41] [PASSED] drm_test_cmdline_res_refresh
[21:21:41] [PASSED] drm_test_cmdline_res_bpp_refresh
[21:21:41] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[21:21:41] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[21:21:41] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[21:21:41] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[21:21:41] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[21:21:41] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[21:21:41] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[21:21:41] [PASSED] drm_test_cmdline_res_margins_force_on
[21:21:41] [PASSED] drm_test_cmdline_res_vesa_margins
[21:21:41] [PASSED] drm_test_cmdline_name
[21:21:41] [PASSED] drm_test_cmdline_name_bpp
[21:21:41] [PASSED] drm_test_cmdline_name_option
[21:21:41] [PASSED] drm_test_cmdline_name_bpp_option
[21:21:41] [PASSED] drm_test_cmdline_rotate_0
[21:21:41] [PASSED] drm_test_cmdline_rotate_90
[21:21:41] [PASSED] drm_test_cmdline_rotate_180
[21:21:41] [PASSED] drm_test_cmdline_rotate_270
[21:21:41] [PASSED] drm_test_cmdline_hmirror
[21:21:41] [PASSED] drm_test_cmdline_vmirror
[21:21:41] [PASSED] drm_test_cmdline_margin_options
[21:21:41] [PASSED] drm_test_cmdline_multiple_options
[21:21:41] [PASSED] drm_test_cmdline_bpp_extra_and_option
[21:21:41] [PASSED] drm_test_cmdline_extra_and_option
[21:21:41] [PASSED] drm_test_cmdline_freestanding_options
[21:21:41] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[21:21:41] [PASSED] drm_test_cmdline_panel_orientation
[21:21:41] ================ drm_test_cmdline_invalid  =================
[21:21:41] [PASSED] margin_only
[21:21:41] [PASSED] interlace_only
[21:21:41] [PASSED] res_missing_x
[21:21:41] [PASSED] res_missing_y
[21:21:41] [PASSED] res_bad_y
[21:21:41] [PASSED] res_missing_y_bpp
[21:21:41] [PASSED] res_bad_bpp
[21:21:41] [PASSED] res_bad_refresh
[21:21:41] [PASSED] res_bpp_refresh_force_on_off
[21:21:41] [PASSED] res_invalid_mode
[21:21:41] [PASSED] res_bpp_wrong_place_mode
[21:21:41] [PASSED] name_bpp_refresh
[21:21:41] [PASSED] name_refresh
[21:21:41] [PASSED] name_refresh_wrong_mode
[21:21:41] [PASSED] name_refresh_invalid_mode
[21:21:41] [PASSED] rotate_multiple
[21:21:41] [PASSED] rotate_invalid_val
[21:21:41] [PASSED] rotate_truncated
[21:21:41] [PASSED] invalid_option
[21:21:41] [PASSED] invalid_tv_option
[21:21:41] [PASSED] truncated_tv_option
[21:21:41] ============ [PASSED] drm_test_cmdline_invalid =============
[21:21:41] =============== drm_test_cmdline_tv_options  ===============
[21:21:41] [PASSED] NTSC
[21:21:41] [PASSED] NTSC_443
[21:21:41] [PASSED] NTSC_J
[21:21:41] [PASSED] PAL
[21:21:41] [PASSED] PAL_M
[21:21:41] [PASSED] PAL_N
[21:21:41] [PASSED] SECAM
[21:21:41] [PASSED] MONO_525
[21:21:41] [PASSED] MONO_625
[21:21:41] =========== [PASSED] drm_test_cmdline_tv_options ===========
[21:21:41] =============== [PASSED] drm_cmdline_parser ================
[21:21:41] ========== drmm_connector_hdmi_init (20 subtests) ==========
[21:21:41] [PASSED] drm_test_connector_hdmi_init_valid
[21:21:41] [PASSED] drm_test_connector_hdmi_init_bpc_8
[21:21:41] [PASSED] drm_test_connector_hdmi_init_bpc_10
[21:21:41] [PASSED] drm_test_connector_hdmi_init_bpc_12
[21:21:41] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[21:21:41] [PASSED] drm_test_connector_hdmi_init_bpc_null
[21:21:41] [PASSED] drm_test_connector_hdmi_init_formats_empty
[21:21:41] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[21:21:41] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[21:21:41] [PASSED] supported_formats=0x9 yuv420_allowed=1
[21:21:41] [PASSED] supported_formats=0x9 yuv420_allowed=0
[21:21:41] [PASSED] supported_formats=0x5 yuv420_allowed=1
[21:21:41] [PASSED] supported_formats=0x5 yuv420_allowed=0
[21:21:41] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[21:21:41] [PASSED] drm_test_connector_hdmi_init_null_ddc
[21:21:41] [PASSED] drm_test_connector_hdmi_init_null_product
[21:21:41] [PASSED] drm_test_connector_hdmi_init_null_vendor
[21:21:41] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[21:21:41] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[21:21:41] [PASSED] drm_test_connector_hdmi_init_product_valid
[21:21:41] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[21:21:41] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[21:21:41] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[21:21:41] ========= drm_test_connector_hdmi_init_type_valid  =========
[21:21:41] [PASSED] HDMI-A
[21:21:41] [PASSED] HDMI-B
[21:21:41] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[21:21:41] ======== drm_test_connector_hdmi_init_type_invalid  ========
[21:21:41] [PASSED] Unknown
[21:21:41] [PASSED] VGA
[21:21:41] [PASSED] DVI-I
[21:21:41] [PASSED] DVI-D
[21:21:41] [PASSED] DVI-A
[21:21:41] [PASSED] Composite
[21:21:41] [PASSED] SVIDEO
[21:21:41] [PASSED] LVDS
[21:21:41] [PASSED] Component
[21:21:41] [PASSED] DIN
[21:21:41] [PASSED] DP
[21:21:41] [PASSED] TV
[21:21:41] [PASSED] eDP
[21:21:41] [PASSED] Virtual
[21:21:41] [PASSED] DSI
[21:21:41] [PASSED] DPI
[21:21:41] [PASSED] Writeback
[21:21:41] [PASSED] SPI
[21:21:41] [PASSED] USB
[21:21:41] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[21:21:41] ============ [PASSED] drmm_connector_hdmi_init =============
[21:21:41] ============= drmm_connector_init (3 subtests) =============
[21:21:41] [PASSED] drm_test_drmm_connector_init
[21:21:41] [PASSED] drm_test_drmm_connector_init_null_ddc
[21:21:41] ========= drm_test_drmm_connector_init_type_valid  =========
[21:21:41] [PASSED] Unknown
[21:21:41] [PASSED] VGA
[21:21:41] [PASSED] DVI-I
[21:21:41] [PASSED] DVI-D
[21:21:41] [PASSED] DVI-A
[21:21:41] [PASSED] Composite
[21:21:41] [PASSED] SVIDEO
[21:21:41] [PASSED] LVDS
[21:21:41] [PASSED] Component
[21:21:41] [PASSED] DIN
[21:21:41] [PASSED] DP
[21:21:41] [PASSED] HDMI-A
[21:21:41] [PASSED] HDMI-B
[21:21:41] [PASSED] TV
[21:21:41] [PASSED] eDP
[21:21:41] [PASSED] Virtual
[21:21:41] [PASSED] DSI
[21:21:41] [PASSED] DPI
[21:21:41] [PASSED] Writeback
[21:21:41] [PASSED] SPI
[21:21:41] [PASSED] USB
[21:21:41] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[21:21:41] =============== [PASSED] drmm_connector_init ===============
[21:21:41] ========= drm_connector_dynamic_init (6 subtests) ==========
[21:21:41] [PASSED] drm_test_drm_connector_dynamic_init
[21:21:41] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[21:21:41] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[21:21:41] [PASSED] drm_test_drm_connector_dynamic_init_properties
[21:21:41] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[21:21:41] [PASSED] Unknown
[21:21:41] [PASSED] VGA
[21:21:41] [PASSED] DVI-I
[21:21:41] [PASSED] DVI-D
[21:21:41] [PASSED] DVI-A
[21:21:41] [PASSED] Composite
[21:21:41] [PASSED] SVIDEO
[21:21:41] [PASSED] LVDS
[21:21:41] [PASSED] Component
[21:21:41] [PASSED] DIN
[21:21:41] [PASSED] DP
[21:21:41] [PASSED] HDMI-A
[21:21:41] [PASSED] HDMI-B
[21:21:41] [PASSED] TV
[21:21:41] [PASSED] eDP
[21:21:41] [PASSED] Virtual
[21:21:41] [PASSED] DSI
[21:21:41] [PASSED] DPI
[21:21:41] [PASSED] Writeback
[21:21:41] [PASSED] SPI
[21:21:41] [PASSED] USB
[21:21:41] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[21:21:41] ======== drm_test_drm_connector_dynamic_init_name  =========
[21:21:41] [PASSED] Unknown
[21:21:41] [PASSED] VGA
[21:21:41] [PASSED] DVI-I
[21:21:41] [PASSED] DVI-D
[21:21:41] [PASSED] DVI-A
[21:21:41] [PASSED] Composite
[21:21:41] [PASSED] SVIDEO
[21:21:41] [PASSED] LVDS
[21:21:41] [PASSED] Component
[21:21:41] [PASSED] DIN
[21:21:41] [PASSED] DP
[21:21:41] [PASSED] HDMI-A
[21:21:41] [PASSED] HDMI-B
[21:21:41] [PASSED] TV
[21:21:41] [PASSED] eDP
[21:21:41] [PASSED] Virtual
[21:21:41] [PASSED] DSI
[21:21:41] [PASSED] DPI
[21:21:41] [PASSED] Writeback
[21:21:41] [PASSED] SPI
[21:21:41] [PASSED] USB
[21:21:41] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[21:21:41] =========== [PASSED] drm_connector_dynamic_init ============
[21:21:41] ==== drm_connector_dynamic_register_early (4 subtests) =====
[21:21:41] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[21:21:41] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[21:21:41] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[21:21:41] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[21:21:41] ====== [PASSED] drm_connector_dynamic_register_early =======
[21:21:41] ======= drm_connector_dynamic_register (7 subtests) ========
[21:21:41] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[21:21:41] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[21:21:41] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[21:21:41] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[21:21:41] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[21:21:41] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[21:21:41] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[21:21:41] ========= [PASSED] drm_connector_dynamic_register ==========
[21:21:41] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[21:21:41] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[21:21:41] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[21:21:41] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[21:21:41] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[21:21:41] ========== drm_test_get_tv_mode_from_name_valid  ===========
[21:21:41] [PASSED] NTSC
[21:21:41] [PASSED] NTSC-443
[21:21:41] [PASSED] NTSC-J
[21:21:41] [PASSED] PAL
[21:21:41] [PASSED] PAL-M
[21:21:41] [PASSED] PAL-N
[21:21:41] [PASSED] SECAM
[21:21:41] [PASSED] Mono
[21:21:41] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[21:21:41] [PASSED] drm_test_get_tv_mode_from_name_truncated
[21:21:41] ============ [PASSED] drm_get_tv_mode_from_name ============
[21:21:41] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[21:21:41] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[21:21:41] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[21:21:41] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[21:21:41] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[21:21:41] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[21:21:41] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[21:21:41] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[21:21:41] [PASSED] VIC 96
[21:21:41] [PASSED] VIC 97
[21:21:41] [PASSED] VIC 101
[21:21:41] [PASSED] VIC 102
[21:21:41] [PASSED] VIC 106
[21:21:41] [PASSED] VIC 107
[21:21:41] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[21:21:41] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[21:21:41] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[21:21:41] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[21:21:41] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[21:21:41] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[21:21:41] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[21:21:41] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[21:21:41] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[21:21:41] [PASSED] Automatic
[21:21:41] [PASSED] Full
[21:21:41] [PASSED] Limited 16:235
[21:21:41] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[21:21:41] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[21:21:41] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[21:21:41] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[21:21:41] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[21:21:41] [PASSED] RGB
[21:21:41] [PASSED] YUV 4:2:0
[21:21:41] [PASSED] YUV 4:2:2
[21:21:41] [PASSED] YUV 4:4:4
[21:21:41] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[21:21:41] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[21:21:41] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[21:21:41] ============= drm_damage_helper (21 subtests) ==============
[21:21:41] [PASSED] drm_test_damage_iter_no_damage
[21:21:41] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[21:21:41] [PASSED] drm_test_damage_iter_no_damage_src_moved
[21:21:41] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[21:21:41] [PASSED] drm_test_damage_iter_no_damage_not_visible
[21:21:41] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[21:21:41] [PASSED] drm_test_damage_iter_no_damage_no_fb
[21:21:41] [PASSED] drm_test_damage_iter_simple_damage
[21:21:41] [PASSED] drm_test_damage_iter_single_damage
[21:21:41] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[21:21:41] [PASSED] drm_test_damage_iter_single_damage_outside_src
[21:21:41] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[21:21:41] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[21:21:41] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[21:21:41] [PASSED] drm_test_damage_iter_single_damage_src_moved
[21:21:41] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[21:21:41] [PASSED] drm_test_damage_iter_damage
[21:21:41] [PASSED] drm_test_damage_iter_damage_one_intersect
[21:21:41] [PASSED] drm_test_damage_iter_damage_one_outside
[21:21:41] [PASSED] drm_test_damage_iter_damage_src_moved
[21:21:41] [PASSED] drm_test_damage_iter_damage_not_visible
[21:21:41] ================ [PASSED] drm_damage_helper ================
[21:21:41] ============== drm_dp_mst_helper (3 subtests) ==============
[21:21:41] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[21:21:41] [PASSED] Clock 154000 BPP 30 DSC disabled
[21:21:41] [PASSED] Clock 234000 BPP 30 DSC disabled
[21:21:41] [PASSED] Clock 297000 BPP 24 DSC disabled
[21:21:41] [PASSED] Clock 332880 BPP 24 DSC enabled
[21:21:41] [PASSED] Clock 324540 BPP 24 DSC enabled
[21:21:41] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[21:21:41] ============== drm_test_dp_mst_calc_pbn_div  ===============
[21:21:41] [PASSED] Link rate 2000000 lane count 4
[21:21:41] [PASSED] Link rate 2000000 lane count 2
[21:21:41] [PASSED] Link rate 2000000 lane count 1
[21:21:41] [PASSED] Link rate 1350000 lane count 4
[21:21:41] [PASSED] Link rate 1350000 lane count 2
[21:21:41] [PASSED] Link rate 1350000 lane count 1
[21:21:41] [PASSED] Link rate 1000000 lane count 4
[21:21:41] [PASSED] Link rate 1000000 lane count 2
[21:21:41] [PASSED] Link rate 1000000 lane count 1
[21:21:41] [PASSED] Link rate 810000 lane count 4
[21:21:41] [PASSED] Link rate 810000 lane count 2
[21:21:41] [PASSED] Link rate 810000 lane count 1
[21:21:41] [PASSED] Link rate 540000 lane count 4
[21:21:41] [PASSED] Link rate 540000 lane count 2
[21:21:41] [PASSED] Link rate 540000 lane count 1
[21:21:41] [PASSED] Link rate 270000 lane count 4
[21:21:41] [PASSED] Link rate 270000 lane count 2
[21:21:41] [PASSED] Link rate 270000 lane count 1
[21:21:41] [PASSED] Link rate 162000 lane count 4
[21:21:41] [PASSED] Link rate 162000 lane count 2
[21:21:41] [PASSED] Link rate 162000 lane count 1
[21:21:41] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[21:21:41] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[21:21:41] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[21:21:41] [PASSED] DP_POWER_UP_PHY with port number
[21:21:41] [PASSED] DP_POWER_DOWN_PHY with port number
[21:21:41] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[21:21:41] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[21:21:41] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[21:21:41] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[21:21:41] [PASSED] DP_QUERY_PAYLOAD with port number
[21:21:41] [PASSED] DP_QUERY_PAYLOAD with VCPI
[21:21:41] [PASSED] DP_REMOTE_DPCD_READ with port number
[21:21:41] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[21:21:41] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[21:21:41] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[21:21:41] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[21:21:41] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[21:21:41] [PASSED] DP_REMOTE_I2C_READ with port number
[21:21:41] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[21:21:41] [PASSED] DP_REMOTE_I2C_READ with transactions array
[21:21:41] [PASSED] DP_REMOTE_I2C_WRITE with port number
[21:21:41] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[21:21:41] [PASSED] DP_REMOTE_I2C_WRITE with data array
[21:21:41] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[21:21:41] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[21:21:41] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[21:21:41] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[21:21:41] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[21:21:41] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[21:21:41] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[21:21:41] ================ [PASSED] drm_dp_mst_helper ================
[21:21:41] ================== drm_exec (7 subtests) ===================
[21:21:41] [PASSED] sanitycheck
[21:21:41] [PASSED] test_lock
[21:21:41] [PASSED] test_lock_unlock
[21:21:41] [PASSED] test_duplicates
[21:21:41] [PASSED] test_prepare
[21:21:41] [PASSED] test_prepare_array
[21:21:41] [PASSED] test_multiple_loops
[21:21:41] ==================== [PASSED] drm_exec =====================
[21:21:41] =========== drm_format_helper_test (17 subtests) ===========
[21:21:41] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[21:21:41] [PASSED] single_pixel_source_buffer
[21:21:41] [PASSED] single_pixel_clip_rectangle
[21:21:41] [PASSED] well_known_colors
[21:21:41] [PASSED] destination_pitch
[21:21:41] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[21:21:41] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[21:21:41] [PASSED] single_pixel_source_buffer
[21:21:41] [PASSED] single_pixel_clip_rectangle
[21:21:41] [PASSED] well_known_colors
[21:21:41] [PASSED] destination_pitch
[21:21:41] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[21:21:41] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[21:21:41] [PASSED] single_pixel_source_buffer
[21:21:41] [PASSED] single_pixel_clip_rectangle
[21:21:41] [PASSED] well_known_colors
[21:21:41] [PASSED] destination_pitch
[21:21:41] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[21:21:41] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[21:21:41] [PASSED] single_pixel_source_buffer
[21:21:41] [PASSED] single_pixel_clip_rectangle
[21:21:41] [PASSED] well_known_colors
[21:21:41] [PASSED] destination_pitch
[21:21:41] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[21:21:41] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[21:21:41] [PASSED] single_pixel_source_buffer
[21:21:41] [PASSED] single_pixel_clip_rectangle
[21:21:41] [PASSED] well_known_colors
[21:21:41] [PASSED] destination_pitch
[21:21:41] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[21:21:41] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[21:21:41] [PASSED] single_pixel_source_buffer
[21:21:41] [PASSED] single_pixel_clip_rectangle
[21:21:41] [PASSED] well_known_colors
[21:21:41] [PASSED] destination_pitch
[21:21:41] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[21:21:41] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[21:21:41] [PASSED] single_pixel_source_buffer
[21:21:41] [PASSED] single_pixel_clip_rectangle
[21:21:41] [PASSED] well_known_colors
[21:21:41] [PASSED] destination_pitch
[21:21:41] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[21:21:41] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[21:21:41] [PASSED] single_pixel_source_buffer
[21:21:41] [PASSED] single_pixel_clip_rectangle
[21:21:41] [PASSED] well_known_colors
[21:21:41] [PASSED] destination_pitch
[21:21:41] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[21:21:41] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[21:21:41] [PASSED] single_pixel_source_buffer
[21:21:41] [PASSED] single_pixel_clip_rectangle
[21:21:41] [PASSED] well_known_colors
[21:21:41] [PASSED] destination_pitch
[21:21:41] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[21:21:41] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[21:21:41] [PASSED] single_pixel_source_buffer
[21:21:41] [PASSED] single_pixel_clip_rectangle
[21:21:41] [PASSED] well_known_colors
[21:21:41] [PASSED] destination_pitch
[21:21:41] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[21:21:41] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[21:21:41] [PASSED] single_pixel_source_buffer
[21:21:41] [PASSED] single_pixel_clip_rectangle
[21:21:41] [PASSED] well_known_colors
[21:21:41] [PASSED] destination_pitch
[21:21:41] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[21:21:41] ============== drm_test_fb_xrgb8888_to_mono  ===============
[21:21:41] [PASSED] single_pixel_source_buffer
[21:21:41] [PASSED] single_pixel_clip_rectangle
[21:21:41] [PASSED] well_known_colors
[21:21:41] [PASSED] destination_pitch
[21:21:41] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[21:21:41] ==================== drm_test_fb_swab  =====================
[21:21:41] [PASSED] single_pixel_source_buffer
[21:21:41] [PASSED] single_pixel_clip_rectangle
[21:21:41] [PASSED] well_known_colors
[21:21:41] [PASSED] destination_pitch
[21:21:41] ================ [PASSED] drm_test_fb_swab =================
[21:21:41] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[21:21:41] [PASSED] single_pixel_source_buffer
[21:21:41] [PASSED] single_pixel_clip_rectangle
[21:21:41] [PASSED] well_known_colors
[21:21:41] [PASSED] destination_pitch
[21:21:41] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[21:21:41] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[21:21:41] [PASSED] single_pixel_source_buffer
[21:21:41] [PASSED] single_pixel_clip_rectangle
[21:21:41] [PASSED] well_known_colors
[21:21:41] [PASSED] destination_pitch
[21:21:41] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[21:21:41] ================= drm_test_fb_clip_offset  =================
[21:21:41] [PASSED] pass through
[21:21:41] [PASSED] horizontal offset
[21:21:41] [PASSED] vertical offset
[21:21:41] [PASSED] horizontal and vertical offset
[21:21:41] [PASSED] horizontal offset (custom pitch)
[21:21:41] [PASSED] vertical offset (custom pitch)
[21:21:41] [PASSED] horizontal and vertical offset (custom pitch)
[21:21:41] ============= [PASSED] drm_test_fb_clip_offset =============
[21:21:41] =================== drm_test_fb_memcpy  ====================
[21:21:41] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[21:21:41] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[21:21:41] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[21:21:41] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[21:21:41] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[21:21:41] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[21:21:41] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[21:21:41] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[21:21:41] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[21:21:41] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[21:21:41] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[21:21:41] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[21:21:41] =============== [PASSED] drm_test_fb_memcpy ================
[21:21:41] ============= [PASSED] drm_format_helper_test ==============
[21:21:41] ================= drm_format (18 subtests) =================
[21:21:41] [PASSED] drm_test_format_block_width_invalid
[21:21:41] [PASSED] drm_test_format_block_width_one_plane
[21:21:41] [PASSED] drm_test_format_block_width_two_plane
[21:21:41] [PASSED] drm_test_format_block_width_three_plane
[21:21:41] [PASSED] drm_test_format_block_width_tiled
[21:21:41] [PASSED] drm_test_format_block_height_invalid
[21:21:41] [PASSED] drm_test_format_block_height_one_plane
[21:21:41] [PASSED] drm_test_format_block_height_two_plane
[21:21:41] [PASSED] drm_test_format_block_height_three_plane
[21:21:41] [PASSED] drm_test_format_block_height_tiled
[21:21:41] [PASSED] drm_test_format_min_pitch_invalid
[21:21:41] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[21:21:41] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[21:21:41] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[21:21:41] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[21:21:41] [PASSED] drm_test_format_min_pitch_two_plane
[21:21:41] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[21:21:41] [PASSED] drm_test_format_min_pitch_tiled
[21:21:41] =================== [PASSED] drm_format ====================
[21:21:41] ============== drm_framebuffer (10 subtests) ===============
[21:21:41] ========== drm_test_framebuffer_check_src_coords  ==========
[21:21:41] [PASSED] Success: source fits into fb
[21:21:41] [PASSED] Fail: overflowing fb with x-axis coordinate
[21:21:41] [PASSED] Fail: overflowing fb with y-axis coordinate
[21:21:41] [PASSED] Fail: overflowing fb with source width
[21:21:41] [PASSED] Fail: overflowing fb with source height
[21:21:41] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[21:21:41] [PASSED] drm_test_framebuffer_cleanup
[21:21:41] =============== drm_test_framebuffer_create  ===============
[21:21:41] [PASSED] ABGR8888 normal sizes
[21:21:41] [PASSED] ABGR8888 max sizes
[21:21:41] [PASSED] ABGR8888 pitch greater than min required
[21:21:41] [PASSED] ABGR8888 pitch less than min required
[21:21:41] [PASSED] ABGR8888 Invalid width
[21:21:41] [PASSED] ABGR8888 Invalid buffer handle
[21:21:41] [PASSED] No pixel format
[21:21:41] [PASSED] ABGR8888 Width 0
[21:21:41] [PASSED] ABGR8888 Height 0
[21:21:41] [PASSED] ABGR8888 Out of bound height * pitch combination
[21:21:41] [PASSED] ABGR8888 Large buffer offset
[21:21:41] [PASSED] ABGR8888 Buffer offset for inexistent plane
[21:21:41] [PASSED] ABGR8888 Invalid flag
[21:21:41] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[21:21:41] [PASSED] ABGR8888 Valid buffer modifier
[21:21:41] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[21:21:41] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[21:21:41] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[21:21:41] [PASSED] NV12 Normal sizes
[21:21:41] [PASSED] NV12 Max sizes
[21:21:41] [PASSED] NV12 Invalid pitch
[21:21:41] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[21:21:41] [PASSED] NV12 different  modifier per-plane
[21:21:41] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[21:21:41] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[21:21:41] [PASSED] NV12 Modifier for inexistent plane
[21:21:41] [PASSED] NV12 Handle for inexistent plane
[21:21:41] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[21:21:41] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[21:21:41] [PASSED] YVU420 Normal sizes
[21:21:41] [PASSED] YVU420 Max sizes
[21:21:41] [PASSED] YVU420 Invalid pitch
[21:21:41] [PASSED] YVU420 Different pitches
[21:21:41] [PASSED] YVU420 Different buffer offsets/pitches
[21:21:41] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[21:21:41] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[21:21:41] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[21:21:41] [PASSED] YVU420 Valid modifier
[21:21:41] [PASSED] YVU420 Different modifiers per plane
[21:21:41] [PASSED] YVU420 Modifier for inexistent plane
[21:21:41] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[21:21:41] [PASSED] X0L2 Normal sizes
[21:21:41] [PASSED] X0L2 Max sizes
[21:21:41] [PASSED] X0L2 Invalid pitch
[21:21:41] [PASSED] X0L2 Pitch greater than minimum required
[21:21:41] [PASSED] X0L2 Handle for inexistent plane
[21:21:41] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[21:21:41] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[21:21:41] [PASSED] X0L2 Valid modifier
[21:21:41] [PASSED] X0L2 Modifier for inexistent plane
[21:21:41] =========== [PASSED] drm_test_framebuffer_create ===========
[21:21:41] [PASSED] drm_test_framebuffer_free
[21:21:41] [PASSED] drm_test_framebuffer_init
[21:21:41] [PASSED] drm_test_framebuffer_init_bad_format
[21:21:41] [PASSED] drm_test_framebuffer_init_dev_mismatch
[21:21:41] [PASSED] drm_test_framebuffer_lookup
[21:21:41] [PASSED] drm_test_framebuffer_lookup_inexistent
[21:21:41] [PASSED] drm_test_framebuffer_modifiers_not_supported
[21:21:41] ================= [PASSED] drm_framebuffer =================
[21:21:41] ================ drm_gem_shmem (8 subtests) ================
[21:21:41] [PASSED] drm_gem_shmem_test_obj_create
[21:21:41] [PASSED] drm_gem_shmem_test_obj_create_private
[21:21:41] [PASSED] drm_gem_shmem_test_pin_pages
[21:21:41] [PASSED] drm_gem_shmem_test_vmap
[21:21:41] [PASSED] drm_gem_shmem_test_get_sg_table
[21:21:41] [PASSED] drm_gem_shmem_test_get_pages_sgt
[21:21:41] [PASSED] drm_gem_shmem_test_madvise
[21:21:41] [PASSED] drm_gem_shmem_test_purge
[21:21:41] ================== [PASSED] drm_gem_shmem ==================
[21:21:41] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[21:21:41] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[21:21:41] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[21:21:41] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[21:21:41] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[21:21:41] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[21:21:41] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[21:21:41] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[21:21:41] [PASSED] Automatic
[21:21:41] [PASSED] Full
[21:21:41] [PASSED] Limited 16:235
[21:21:41] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[21:21:41] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[21:21:41] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[21:21:41] [PASSED] drm_test_check_disable_connector
[21:21:41] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[21:21:41] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[21:21:41] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[21:21:41] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[21:21:41] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[21:21:41] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[21:21:41] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[21:21:41] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[21:21:41] [PASSED] drm_test_check_output_bpc_dvi
[21:21:41] [PASSED] drm_test_check_output_bpc_format_vic_1
[21:21:41] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[21:21:41] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[21:21:41] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[21:21:41] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[21:21:41] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[21:21:41] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[21:21:41] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[21:21:41] ============ drm_test_check_hdmi_color_format  =============
[21:21:41] [PASSED] AUTO -> RGB
[21:21:41] [PASSED] YCBCR422 -> YUV422
[21:21:41] [PASSED] YCBCR420 -> YUV420
[21:21:41] [PASSED] YCBCR444 -> YUV444
[21:21:41] [PASSED] RGB -> RGB
[21:21:41] ======== [PASSED] drm_test_check_hdmi_color_format =========
[21:21:41] ======== drm_test_check_hdmi_color_format_420_only  ========
[21:21:41] [PASSED] RGB should fail
[21:21:41] [PASSED] YUV444 should fail
[21:21:41] [PASSED] YUV422 should fail
[21:21:41] [PASSED] YUV420 should work
[21:21:41] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[21:21:41] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[21:21:41] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[21:21:41] [PASSED] drm_test_check_broadcast_rgb_value
[21:21:41] [PASSED] drm_test_check_bpc_8_value
[21:21:41] [PASSED] drm_test_check_bpc_10_value
[21:21:41] [PASSED] drm_test_check_bpc_12_value
[21:21:41] [PASSED] drm_test_check_format_value
[21:21:41] [PASSED] drm_test_check_tmds_char_value
[21:21:41] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[21:21:41] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[21:21:41] [PASSED] drm_test_check_mode_valid
[21:21:41] [PASSED] drm_test_check_mode_valid_reject
[21:21:41] [PASSED] drm_test_check_mode_valid_reject_rate
[21:21:41] [PASSED] drm_test_check_mode_valid_reject_max_clock
[21:21:41] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[21:21:41] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[21:21:41] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[21:21:41] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[21:21:41] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[21:21:41] [PASSED] drm_test_check_infoframes
[21:21:41] [PASSED] drm_test_check_reject_avi_infoframe
[21:21:41] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[21:21:41] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[21:21:41] [PASSED] drm_test_check_reject_audio_infoframe
[21:21:41] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[21:21:41] ================= drm_managed (2 subtests) =================
[21:21:41] [PASSED] drm_test_managed_release_action
[21:21:41] [PASSED] drm_test_managed_run_action
[21:21:41] =================== [PASSED] drm_managed ===================
[21:21:41] =================== drm_mm (6 subtests) ====================
[21:21:41] [PASSED] drm_test_mm_init
[21:21:41] [PASSED] drm_test_mm_debug
[21:21:41] [PASSED] drm_test_mm_align32
[21:21:41] [PASSED] drm_test_mm_align64
[21:21:41] [PASSED] drm_test_mm_lowest
[21:21:41] [PASSED] drm_test_mm_highest
[21:21:41] ===================== [PASSED] drm_mm ======================
[21:21:41] ============= drm_modes_analog_tv (5 subtests) =============
[21:21:41] [PASSED] drm_test_modes_analog_tv_mono_576i
[21:21:41] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[21:21:41] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[21:21:41] [PASSED] drm_test_modes_analog_tv_pal_576i
[21:21:41] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[21:21:41] =============== [PASSED] drm_modes_analog_tv ===============
[21:21:41] ============== drm_plane_helper (2 subtests) ===============
[21:21:41] =============== drm_test_check_plane_state  ================
[21:21:41] [PASSED] clipping_simple
[21:21:41] [PASSED] clipping_rotate_reflect
[21:21:41] [PASSED] positioning_simple
[21:21:41] [PASSED] upscaling
[21:21:41] [PASSED] downscaling
[21:21:41] [PASSED] rounding1
[21:21:41] [PASSED] rounding2
[21:21:41] [PASSED] rounding3
[21:21:41] [PASSED] rounding4
[21:21:41] =========== [PASSED] drm_test_check_plane_state ============
[21:21:41] =========== drm_test_check_invalid_plane_state  ============
[21:21:41] [PASSED] positioning_invalid
[21:21:41] [PASSED] upscaling_invalid
[21:21:41] [PASSED] downscaling_invalid
[21:21:41] ======= [PASSED] drm_test_check_invalid_plane_state ========
[21:21:41] ================ [PASSED] drm_plane_helper =================
[21:21:41] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[21:21:41] ====== drm_test_connector_helper_tv_get_modes_check  =======
[21:21:41] [PASSED] None
[21:21:41] [PASSED] PAL
[21:21:41] [PASSED] NTSC
[21:21:41] [PASSED] Both, NTSC Default
[21:21:41] [PASSED] Both, PAL Default
[21:21:41] [PASSED] Both, NTSC Default, with PAL on command-line
[21:21:41] [PASSED] Both, PAL Default, with NTSC on command-line
[21:21:41] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[21:21:41] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[21:21:41] ================== drm_rect (9 subtests) ===================
[21:21:41] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[21:21:41] [PASSED] drm_test_rect_clip_scaled_not_clipped
[21:21:41] [PASSED] drm_test_rect_clip_scaled_clipped
[21:21:41] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[21:21:41] ================= drm_test_rect_intersect  =================
[21:21:41] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[21:21:41] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[21:21:41] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[21:21:41] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[21:21:41] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[21:21:41] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[21:21:41] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[21:21:41] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[21:21:41] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[21:21:41] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[21:21:41] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[21:21:41] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[21:21:41] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[21:21:41] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[21:21:41] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[21:21:41] ============= [PASSED] drm_test_rect_intersect =============
[21:21:41] ================ drm_test_rect_calc_hscale  ================
[21:21:41] [PASSED] normal use
[21:21:41] [PASSED] out of max range
[21:21:41] [PASSED] out of min range
[21:21:41] [PASSED] zero dst
[21:21:41] [PASSED] negative src
[21:21:41] [PASSED] negative dst
[21:21:41] ============ [PASSED] drm_test_rect_calc_hscale ============
[21:21:41] ================ drm_test_rect_calc_vscale  ================
[21:21:41] [PASSED] normal use
[21:21:41] [PASSED] out of max range
[21:21:41] [PASSED] out of min range
[21:21:41] [PASSED] zero dst
[21:21:41] [PASSED] negative src
[21:21:41] [PASSED] negative dst
[21:21:41] ============ [PASSED] drm_test_rect_calc_vscale ============
[21:21:41] ================== drm_test_rect_rotate  ===================
[21:21:41] [PASSED] reflect-x
[21:21:41] [PASSED] reflect-y
[21:21:41] [PASSED] rotate-0
[21:21:41] [PASSED] rotate-90
[21:21:41] [PASSED] rotate-180
[21:21:41] [PASSED] rotate-270
[21:21:41] ============== [PASSED] drm_test_rect_rotate ===============
[21:21:41] ================ drm_test_rect_rotate_inv  =================
[21:21:41] [PASSED] reflect-x
[21:21:41] [PASSED] reflect-y
[21:21:41] [PASSED] rotate-0
[21:21:41] [PASSED] rotate-90
[21:21:41] [PASSED] rotate-180
[21:21:41] [PASSED] rotate-270
[21:21:41] ============ [PASSED] drm_test_rect_rotate_inv =============
[21:21:41] ==================== [PASSED] drm_rect =====================
[21:21:41] ============ drm_sysfb_modeset_test (1 subtest) ============
[21:21:41] ============ drm_test_sysfb_build_fourcc_list  =============
[21:21:41] [PASSED] no native formats
[21:21:41] [PASSED] XRGB8888 as native format
[21:21:41] [PASSED] remove duplicates
[21:21:41] [PASSED] convert alpha formats
[21:21:41] [PASSED] random formats
[21:21:41] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[21:21:41] ============= [PASSED] drm_sysfb_modeset_test ==============
[21:21:41] ================== drm_fixp (2 subtests) ===================
[21:21:41] [PASSED] drm_test_int2fixp
[21:21:41] [PASSED] drm_test_sm2fixp
[21:21:41] ==================== [PASSED] drm_fixp =====================
[21:21:41] ============================================================
[21:21:41] Testing complete. Ran 641 tests: passed: 641
[21:21:41] Elapsed time: 26.700s total, 1.801s configuring, 24.730s building, 0.148s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[21:21:41] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:21:43] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[21:21:53] Starting KUnit Kernel (1/1)...
[21:21:53] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:21:53] ============= refcount_interrupt (4 subtests) ==============
[21:21:53] [PASSED] test_single_irq_change
[21:21:53] [PASSED] test_nested_irq_change
[21:21:53] [PASSED] test_multiple_irq_change
[21:21:53] [PASSED] test_irq_save
[21:21:53] =============== [PASSED] refcount_interrupt ================
[21:21:53] ================= ttm_device (5 subtests) ==================
[21:21:53] [PASSED] ttm_device_init_basic
[21:21:53] [PASSED] ttm_device_init_multiple
[21:21:53] [PASSED] ttm_device_fini_basic
[21:21:53] [PASSED] ttm_device_init_no_vma_man
[21:21:53] ================== ttm_device_init_pools  ==================
[21:21:53] [PASSED] No DMA allocations, no DMA32 required
[21:21:53] [PASSED] DMA allocations, DMA32 required
[21:21:53] [PASSED] No DMA allocations, DMA32 required
[21:21:53] [PASSED] DMA allocations, no DMA32 required
[21:21:53] ============== [PASSED] ttm_device_init_pools ==============
[21:21:53] =================== [PASSED] ttm_device ====================
[21:21:53] ================== ttm_pool (8 subtests) ===================
[21:21:53] ================== ttm_pool_alloc_basic  ===================
[21:21:53] [PASSED] One page
[21:21:53] [PASSED] More than one page
[21:21:53] [PASSED] Above the allocation limit
[21:21:53] [PASSED] One page, with coherent DMA mappings enabled
[21:21:53] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[21:21:53] ============== [PASSED] ttm_pool_alloc_basic ===============
[21:21:53] ============== ttm_pool_alloc_basic_dma_addr  ==============
[21:21:53] [PASSED] One page
[21:21:53] [PASSED] More than one page
[21:21:53] [PASSED] Above the allocation limit
[21:21:53] [PASSED] One page, with coherent DMA mappings enabled
[21:21:53] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[21:21:53] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[21:21:53] [PASSED] ttm_pool_alloc_order_caching_match
[21:21:53] [PASSED] ttm_pool_alloc_caching_mismatch
[21:21:53] [PASSED] ttm_pool_alloc_order_mismatch
[21:21:53] [PASSED] ttm_pool_free_dma_alloc
[21:21:53] [PASSED] ttm_pool_free_no_dma_alloc
[21:21:53] [PASSED] ttm_pool_fini_basic
[21:21:53] ==================== [PASSED] ttm_pool =====================
[21:21:53] ================ ttm_resource (8 subtests) =================
[21:21:53] ================= ttm_resource_init_basic  =================
[21:21:53] [PASSED] Init resource in TTM_PL_SYSTEM
[21:21:53] [PASSED] Init resource in TTM_PL_VRAM
[21:21:53] [PASSED] Init resource in a private placement
[21:21:53] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[21:21:53] ============= [PASSED] ttm_resource_init_basic =============
[21:21:53] [PASSED] ttm_resource_init_pinned
[21:21:53] [PASSED] ttm_resource_fini_basic
[21:21:53] [PASSED] ttm_resource_manager_init_basic
[21:21:53] [PASSED] ttm_resource_manager_usage_basic
[21:21:53] [PASSED] ttm_resource_manager_set_used_basic
[21:21:53] [PASSED] ttm_sys_man_alloc_basic
[21:21:53] [PASSED] ttm_sys_man_free_basic
[21:21:53] ================== [PASSED] ttm_resource ===================
[21:21:53] =================== ttm_tt (15 subtests) ===================
[21:21:53] ==================== ttm_tt_init_basic  ====================
[21:21:53] [PASSED] Page-aligned size
[21:21:53] [PASSED] Extra pages requested
[21:21:53] ================ [PASSED] ttm_tt_init_basic ================
[21:21:53] [PASSED] ttm_tt_init_misaligned
[21:21:53] [PASSED] ttm_tt_fini_basic
[21:21:53] [PASSED] ttm_tt_fini_sg
[21:21:53] [PASSED] ttm_tt_fini_shmem
[21:21:53] [PASSED] ttm_tt_create_basic
[21:21:53] [PASSED] ttm_tt_create_invalid_bo_type
[21:21:53] [PASSED] ttm_tt_create_ttm_exists
[21:21:53] [PASSED] ttm_tt_create_failed
[21:21:53] [PASSED] ttm_tt_destroy_basic
[21:21:53] [PASSED] ttm_tt_populate_null_ttm
[21:21:53] [PASSED] ttm_tt_populate_populated_ttm
[21:21:53] [PASSED] ttm_tt_unpopulate_basic
[21:21:53] [PASSED] ttm_tt_unpopulate_empty_ttm
[21:21:53] [PASSED] ttm_tt_swapin_basic
[21:21:53] ===================== [PASSED] ttm_tt ======================
[21:21:53] =================== ttm_bo (14 subtests) ===================
[21:21:53] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[21:21:53] [PASSED] Cannot be interrupted and sleeps
[21:21:53] [PASSED] Cannot be interrupted, locks straight away
[21:21:53] [PASSED] Can be interrupted, sleeps
[21:21:53] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[21:21:53] [PASSED] ttm_bo_reserve_locked_no_sleep
[21:21:53] [PASSED] ttm_bo_reserve_no_wait_ticket
[21:21:53] [PASSED] ttm_bo_reserve_double_resv
[21:21:53] [PASSED] ttm_bo_reserve_interrupted
[21:21:53] [PASSED] ttm_bo_reserve_deadlock
[21:21:53] [PASSED] ttm_bo_unreserve_basic
[21:21:53] [PASSED] ttm_bo_unreserve_pinned
[21:21:53] [PASSED] ttm_bo_unreserve_bulk
[21:21:53] [PASSED] ttm_bo_fini_basic
[21:21:53] [PASSED] ttm_bo_fini_shared_resv
[21:21:53] [PASSED] ttm_bo_pin_basic
[21:21:53] [PASSED] ttm_bo_pin_unpin_resource
[21:21:53] [PASSED] ttm_bo_multiple_pin_one_unpin
[21:21:53] ===================== [PASSED] ttm_bo ======================
[21:21:53] ============== ttm_bo_validate (22 subtests) ===============
[21:21:53] ============== ttm_bo_init_reserved_sys_man  ===============
[21:21:53] [PASSED] Buffer object for userspace
[21:21:53] [PASSED] Kernel buffer object
[21:21:53] [PASSED] Shared buffer object
[21:21:53] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[21:21:53] ============== ttm_bo_init_reserved_mock_man  ==============
[21:21:53] [PASSED] Buffer object for userspace
[21:21:53] [PASSED] Kernel buffer object
[21:21:53] [PASSED] Shared buffer object
[21:21:53] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[21:21:53] [PASSED] ttm_bo_init_reserved_resv
[21:21:53] ================== ttm_bo_validate_basic  ==================
[21:21:53] [PASSED] Buffer object for userspace
[21:21:53] [PASSED] Kernel buffer object
[21:21:53] [PASSED] Shared buffer object
[21:21:53] ============== [PASSED] ttm_bo_validate_basic ==============
[21:21:53] [PASSED] ttm_bo_validate_invalid_placement
[21:21:53] ============= ttm_bo_validate_same_placement  ==============
[21:21:53] [PASSED] System manager
[21:21:53] [PASSED] VRAM manager
[21:21:53] ========= [PASSED] ttm_bo_validate_same_placement ==========
[21:21:53] [PASSED] ttm_bo_validate_failed_alloc
[21:21:53] [PASSED] ttm_bo_validate_pinned
[21:21:53] [PASSED] ttm_bo_validate_busy_placement
[21:21:53] ================ ttm_bo_validate_multihop  =================
[21:21:53] [PASSED] Buffer object for userspace
[21:21:53] [PASSED] Kernel buffer object
[21:21:53] [PASSED] Shared buffer object
[21:21:53] ============ [PASSED] ttm_bo_validate_multihop =============
[21:21:53] ========== ttm_bo_validate_no_placement_signaled  ==========
[21:21:53] [PASSED] Buffer object in system domain, no page vector
[21:21:53] [PASSED] Buffer object in system domain with an existing page vector
[21:21:53] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[21:21:53] ======== ttm_bo_validate_no_placement_not_signaled  ========
[21:21:53] [PASSED] Buffer object for userspace
[21:21:53] [PASSED] Kernel buffer object
[21:21:53] [PASSED] Shared buffer object
[21:21:53] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[21:21:53] [PASSED] ttm_bo_validate_move_fence_signaled
[21:21:53] ========= ttm_bo_validate_move_fence_not_signaled  =========
[21:21:53] [PASSED] Waits for GPU
[21:21:53] [PASSED] Tries to lock straight away
[21:21:53] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[21:21:53] [PASSED] ttm_bo_validate_swapout
[21:21:53] [PASSED] ttm_bo_validate_happy_evict
[21:21:53] [PASSED] ttm_bo_validate_all_pinned_evict
[21:21:53] [PASSED] ttm_bo_validate_allowed_only_evict
[21:21:53] [PASSED] ttm_bo_validate_deleted_evict
[21:21:53] [PASSED] ttm_bo_validate_busy_domain_evict
[21:21:53] [PASSED] ttm_bo_validate_evict_gutting
[21:21:53] [PASSED] ttm_bo_validate_recrusive_evict
[21:21:53] ================= [PASSED] ttm_bo_validate =================
[21:21:53] ============================================================
[21:21:53] Testing complete. Ran 106 tests: passed: 106
[21:21:53] Elapsed time: 12.220s total, 1.800s configuring, 10.206s building, 0.183s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/dma-buf/.kunitconfig
[21:21:53] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:21:55] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[21:22:04] Starting KUnit Kernel (1/1)...
[21:22:04] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:22:04] ============= refcount_interrupt (4 subtests) ==============
[21:22:04] [PASSED] test_single_irq_change
[21:22:04] [PASSED] test_nested_irq_change
[21:22:04] [PASSED] test_multiple_irq_change
[21:22:04] [PASSED] test_irq_save
[21:22:04] =============== [PASSED] refcount_interrupt ================
[21:22:04] =============== dma-buf-fence (12 subtests) ================
[21:22:04] [PASSED] test_sanitycheck
[21:22:04] [PASSED] test_signaling
[21:22:04] [PASSED] test_add_callback
[21:22:04] [PASSED] test_late_add_callback
[21:22:04] [PASSED] test_rm_callback
[21:22:04] [PASSED] test_late_rm_callback
[21:22:04] [PASSED] test_status
[21:22:04] [PASSED] test_error
[21:22:04] [PASSED] test_wait
[21:22:04] [PASSED] test_wait_timeout
[21:22:04] [PASSED] test_stub
[21:22:04] [SKIPPED] test_race_signal_callback (requires at least 2 CPUs)
[21:22:04] ================== [PASSED] dma-buf-fence ==================
[21:22:04] ============ dma-buf-fence-chain (11 subtests) =============
[21:22:04] [PASSED] test_sanitycheck
[21:22:04] [PASSED] test_find_seqno
[21:22:04] [PASSED] test_find_signaled
[21:22:04] [PASSED] test_find_out_of_order
[21:22:09] [PASSED] test_find_gap
[21:22:09] [PASSED] test_find_race
[21:22:09] [PASSED] test_signal_forward
[21:22:09] [PASSED] test_signal_backward
[21:22:09] [PASSED] test_wait_forward
[21:22:09] [PASSED] test_wait_backward
[21:22:09] [PASSED] test_wait_random
[21:22:09] =============== [PASSED] dma-buf-fence-chain ===============
[21:22:09] ============ dma-buf-fence-unwrap (10 subtests) ============
[21:22:09] [PASSED] test_sanitycheck
[21:22:09] [PASSED] test_unwrap_array
[21:22:09] [PASSED] test_unwrap_chain
[21:22:09] [PASSED] test_unwrap_chain_array
[21:22:09] [PASSED] test_unwrap_merge
[21:22:09] [PASSED] test_unwrap_merge_duplicate
[21:22:09] [PASSED] test_unwrap_merge_seqno
[21:22:09] [PASSED] test_unwrap_merge_order
[21:22:09] [PASSED] test_unwrap_merge_complex
[21:22:09] [PASSED] test_unwrap_merge_complex_seqno
[21:22:09] ============== [PASSED] dma-buf-fence-unwrap ===============
[21:22:09] ================ dma-buf-resv (5 subtests) =================
[21:22:09] [PASSED] test_sanitycheck
[21:22:09] ===================== test_signaling  ======================
[21:22:09] [PASSED] kernel
[21:22:09] [PASSED] write
[21:22:09] [PASSED] read
[21:22:09] [PASSED] bookkeep
[21:22:09] ================= [PASSED] test_signaling ==================
[21:22:09] ====================== test_for_each  ======================
[21:22:09] [PASSED] kernel
[21:22:09] [PASSED] write
[21:22:09] [PASSED] read
[21:22:09] [PASSED] bookkeep
[21:22:09] ================== [PASSED] test_for_each ==================
[21:22:09] ================= test_for_each_unlocked  ==================
[21:22:09] [PASSED] kernel
[21:22:09] [PASSED] write
[21:22:09] [PASSED] read
[21:22:09] [PASSED] bookkeep
[21:22:09] ============= [PASSED] test_for_each_unlocked ==============
[21:22:09] ===================== test_get_fences  =====================
[21:22:09] [PASSED] kernel
[21:22:09] [PASSED] write
[21:22:09] [PASSED] read
[21:22:09] [PASSED] bookkeep
[21:22:09] ================= [PASSED] test_get_fences =================
[21:22:09] ================== [PASSED] dma-buf-resv ===================
[21:22:09] ============================================================
[21:22:09] Testing complete. Ran 54 tests: passed: 53, skipped: 1
[21:22:09] Elapsed time: 15.783s total, 1.831s configuring, 8.580s building, 5.344s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel



^ permalink raw reply	[flat|nested] 18+ messages in thread

* [v4 1/4] drm/i915/display: Enable periodic AS SDP skip frames
  2026-08-31 21:34 [v4 0/4] drm/i915/display: Enable AS SDP Skip Frames Uma Shankar
  2026-08-31 21:20 ` ✗ CI.checkpatch: warning for drm/i915/display: Enable AS SDP Skip Frames (rev5) Patchwork
  2026-08-31 21:22 ` ✓ CI.KUnit: success " Patchwork
@ 2026-08-31 21:34 ` Uma Shankar
  2026-09-02 16:15   ` Dibin Moolakadan Subrahmanian
  2026-08-31 21:34 ` [v4 2/4] drm/i915/display: Force disable DC3co when AS SDP skip frames is enabled Uma Shankar
                   ` (4 subsequent siblings)
  7 siblings, 1 reply; 18+ messages in thread
From: Uma Shankar @ 2026-08-31 21:34 UTC (permalink / raw)
  To: intel-gfx, intel-xe; +Cc: dibin.moolakadan.subrahmanian, Uma Shankar

When Panel Replay is active the transcoder timing generator runs at the
panel's maximum refresh rate. To drive the panel down to its minimum
refresh rate the Adaptive-Sync SDP (AS SDP) only needs to reach the panel
once per minimum-rate frame, so transmitting it on every (maximum-rate)
frame is redundant and shows up as repeated SDPs on the link.

Xe3p_LPD adds a HW skip-frame counter in PR_ALPM_CTL that lets the source
send a single AS SDP and then suppress it for a programmed number of
frames. Program this counter so that one AS SDP is followed by
(max_vrefresh / min_vrefresh - 1) idle frames, i.e. one AS SDP per
slowest panel frame, allowing the link to be driven down to as low as
1Hz when the hardware supports it.

The maximum and minimum refresh rates come from the panel's adaptive-sync
monitor range, so the skip count is a function of the sink's capabilities
and independent of the current content/flip rate. If the panel does not
advertise a usable range the skip counter is left at zero, i.e. the
feature is a no-op and AS SDP continues to be sent on every frame.

Periodic AS SDP drives the panel down to its minimum refresh rate on its
own, so it is only programmed when VRR is not actively driving the
refresh rate.

The skip-frame mechanism relies on the AS SDP still being transmitted
(just less often) while Panel Replay is active, so when a non-zero
skip-frame count is programmed both
PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE and
PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL are left cleared. The previous
behaviour (honouring disable_as_sdp_when_pr_active and the DC3CO idle
protocol) is retained for the non skip-frame case.

v3: Fixed Sashiko review findings

v2: Decoupled CMMRR dependency and using sink refresh rate range for
skip frame claculations. This addresses Dibin's review feedback as well.

Assisted-by: Claude:claude-opus-4-8
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c     | 61 +++++++++++++++++--
 drivers/gpu/drm/i915/display/intel_psr_regs.h |  2 +
 2 files changed, 58 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index f1383764b702..a6838e0fd3aa 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -375,6 +375,35 @@ static u32 get_pr_alpm_as_sdp_transmission_time(const struct intel_crtc_state *c
 	}
 }
 
+/*
+ * Periodic Adaptive-Sync SDP skip frames.
+ *
+ * While Panel Replay is active the transcoder timing generator runs at the
+ * panel's maximum refresh rate. To drive the panel down to its minimum
+ * refresh rate the Adaptive-Sync SDP only needs to reach the panel once per
+ * minimum-rate frame, so transmitting it on every (maximum-rate) frame is
+ * unnecessary and shows up as repeated SDPs on the link. Program the HW skip
+ * counter so that a single AS SDP is followed by
+ * (max_vrefresh / min_vrefresh - 1) idle frames, i.e. one AS SDP per slowest
+ * panel frame.
+ *
+ * The maximum and minimum refresh rates come from the panel's adaptive-sync
+ * monitor range, so this is independent of the current content/flip rate.
+ */
+static u32 intel_pr_as_sdp_skip_frames(struct intel_dp *intel_dp)
+{
+	const struct drm_display_info *info =
+		&intel_dp->attached_connector->base.display_info;
+	int max_vrefresh = info->monitor_range.max_vfreq;
+	int min_vrefresh = info->monitor_range.min_vfreq;
+
+	if (min_vrefresh <= 0 || max_vrefresh <= min_vrefresh)
+		return 0;
+
+	return min_t(u32, max_vrefresh / min_vrefresh - 1,
+		     REG_FIELD_MAX(PR_ALPM_CTL_AS_SDP_SKIP_FRAMES_MASK));
+}
+
 static void lnl_alpm_configure(struct intel_dp *intel_dp,
 			       const struct intel_crtc_state *crtc_state)
 {
@@ -399,16 +428,38 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
 
 		if (intel_dp->as_sdp_supported) {
 			u32 pr_alpm_ctl = get_pr_alpm_as_sdp_transmission_time(crtc_state);
+			u32 skip_frames = 0;
+
+			/*
+			 * AS SDP skip frames field only exists on Xe3p_LPD+, and
+			 * periodic AS SDP is a Panel Replay feature that is only
+			 * used when VRR is not actively driving the refresh rate.
+			 */
+			if (DISPLAY_VER(display) >= 35 && crtc_state->has_panel_replay &&
+			    !crtc_state->vrr.enable)
+				skip_frames = intel_pr_as_sdp_skip_frames(intel_dp);
 
 			if (crtc_state->link_off_after_as_sdp_when_pr_active)
 				pr_alpm_ctl |= PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU;
-			if (crtc_state->disable_as_sdp_when_pr_active)
-				pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE;
 
-			if (intel_display_power_dc3co_allowed(display))
-				pr_alpm_ctl |= PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL;
-			else
+			/*
+			 * Skip frames needs the AS SDP to keep flowing during PR
+			 * active, so it is mutually exclusive with disabling AS SDP
+			 * transmission in active and with the DC3CO idle protocol.
+			 */
+			if (skip_frames) {
+				pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_SKIP_FRAMES(skip_frames);
+				pr_alpm_ctl &= ~PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE;
 				pr_alpm_ctl &= ~PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL;
+			} else {
+				pr_alpm_ctl &= ~PR_ALPM_CTL_AS_SDP_SKIP_FRAMES_MASK;
+
+				if (crtc_state->disable_as_sdp_when_pr_active)
+					pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE;
+
+				if (intel_display_power_dc3co_allowed(display))
+					pr_alpm_ctl |= PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL;
+			}
 
 			intel_de_write(display, PR_ALPM_CTL(display, cpu_transcoder),
 				       pr_alpm_ctl);
diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index 16a9e3af198d..bb577e7e3bbd 100644
--- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
@@ -276,6 +276,8 @@
 #define  PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1_OR_T2	REG_FIELD_PREP(PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_MASK, 0)
 #define  PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1		REG_FIELD_PREP(PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_MASK, 1)
 #define  PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T2		REG_FIELD_PREP(PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_MASK, 2)
+#define  PR_ALPM_CTL_AS_SDP_SKIP_FRAMES_MASK			REG_GENMASK(27, 16)
+#define  PR_ALPM_CTL_AS_SDP_SKIP_FRAMES(frames)			REG_FIELD_PREP(PR_ALPM_CTL_AS_SDP_SKIP_FRAMES_MASK, (frames))
 
 #define _ALPM_CTL_A	0x60950
 #define ALPM_CTL(dev_priv, tran)	_MMIO_TRANS2(dev_priv, tran, _ALPM_CTL_A)
-- 
2.50.1


^ permalink raw reply related	[flat|nested] 18+ messages in thread

* Re: [v4 1/4] drm/i915/display: Enable periodic AS SDP skip frames
  2026-08-31 21:34 ` [v4 1/4] drm/i915/display: Enable periodic AS SDP skip frames Uma Shankar
@ 2026-09-02 16:15   ` Dibin Moolakadan Subrahmanian
  0 siblings, 0 replies; 18+ messages in thread
From: Dibin Moolakadan Subrahmanian @ 2026-09-02 16:15 UTC (permalink / raw)
  To: Uma Shankar, intel-gfx, intel-xe

On 9/1/2026 3:04 AM, Uma Shankar wrote:
> When Panel Replay is active the transcoder timing generator runs at the
> panel's maximum refresh rate. To drive the panel down to its minimum
> refresh rate the Adaptive-Sync SDP (AS SDP) only needs to reach the panel
> once per minimum-rate frame, so transmitting it on every (maximum-rate)
> frame is redundant and shows up as repeated SDPs on the link.
>
> Xe3p_LPD adds a HW skip-frame counter in PR_ALPM_CTL that lets the source
> send a single AS SDP and then suppress it for a programmed number of
> frames. Program this counter so that one AS SDP is followed by
> (max_vrefresh / min_vrefresh - 1) idle frames, i.e. one AS SDP per
> slowest panel frame, allowing the link to be driven down to as low as
> 1Hz when the hardware supports it.
>
> The maximum and minimum refresh rates come from the panel's adaptive-sync
> monitor range, so the skip count is a function of the sink's capabilities
> and independent of the current content/flip rate. If the panel does not
> advertise a usable range the skip counter is left at zero, i.e. the
> feature is a no-op and AS SDP continues to be sent on every frame.
>
> Periodic AS SDP drives the panel down to its minimum refresh rate on its
> own, so it is only programmed when VRR is not actively driving the
> refresh rate.
>
> The skip-frame mechanism relies on the AS SDP still being transmitted
> (just less often) while Panel Replay is active, so when a non-zero
> skip-frame count is programmed both
> PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE and
> PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL are left cleared. The previous
> behaviour (honouring disable_as_sdp_when_pr_active and the DC3CO idle
> protocol) is retained for the non skip-frame case.
>
> v3: Fixed Sashiko review findings
>
> v2: Decoupled CMMRR dependency and using sink refresh rate range for
> skip frame claculations. This addresses Dibin's review feedback as well.
>
> Assisted-by: Claude:claude-opus-4-8
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_alpm.c     | 61 +++++++++++++++++--
>   drivers/gpu/drm/i915/display/intel_psr_regs.h |  2 +
>   2 files changed, 58 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index f1383764b702..a6838e0fd3aa 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -375,6 +375,35 @@ static u32 get_pr_alpm_as_sdp_transmission_time(const struct intel_crtc_state *c
>   	}
>   }
>   
> +/*
> + * Periodic Adaptive-Sync SDP skip frames.
> + *
> + * While Panel Replay is active the transcoder timing generator runs at the
> + * panel's maximum refresh rate. To drive the panel down to its minimum
> + * refresh rate the Adaptive-Sync SDP only needs to reach the panel once per
> + * minimum-rate frame, so transmitting it on every (maximum-rate) frame is
> + * unnecessary and shows up as repeated SDPs on the link. Program the HW skip
> + * counter so that a single AS SDP is followed by
> + * (max_vrefresh / min_vrefresh - 1) idle frames, i.e. one AS SDP per slowest
> + * panel frame.
> + *
> + * The maximum and minimum refresh rates come from the panel's adaptive-sync
> + * monitor range, so this is independent of the current content/flip rate.
> + */
> +static u32 intel_pr_as_sdp_skip_frames(struct intel_dp *intel_dp)
> +{
> +	const struct drm_display_info *info =
> +		&intel_dp->attached_connector->base.display_info;
> +	int max_vrefresh = info->monitor_range.max_vfreq;
> +	int min_vrefresh = info->monitor_range.min_vfreq;
> +
> +	if (min_vrefresh <= 0 || max_vrefresh <= min_vrefresh)
> +		return 0;
> +
> +	return min_t(u32, max_vrefresh / min_vrefresh - 1,
> +		     REG_FIELD_MAX(PR_ALPM_CTL_AS_SDP_SKIP_FRAMES_MASK));
> +}
> +
>   static void lnl_alpm_configure(struct intel_dp *intel_dp,
>   			       const struct intel_crtc_state *crtc_state)
>   {
> @@ -399,16 +428,38 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
>   
>   		if (intel_dp->as_sdp_supported) {
>   			u32 pr_alpm_ctl = get_pr_alpm_as_sdp_transmission_time(crtc_state);
> +			u32 skip_frames = 0;
> +
> +			/*
> +			 * AS SDP skip frames field only exists on Xe3p_LPD+, and
> +			 * periodic AS SDP is a Panel Replay feature that is only
> +			 * used when VRR is not actively driving the refresh rate.
> +			 */
> +			if (DISPLAY_VER(display) >= 35 && crtc_state->has_panel_replay &&
> +			    !crtc_state->vrr.enable)
> +				skip_frames = intel_pr_as_sdp_skip_frames(intel_dp);
>   
>   			if (crtc_state->link_off_after_as_sdp_when_pr_active)
>   				pr_alpm_ctl |= PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU;
> -			if (crtc_state->disable_as_sdp_when_pr_active)
> -				pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE;
>   
> -			if (intel_display_power_dc3co_allowed(display))
> -				pr_alpm_ctl |= PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL;
> -			else
> +			/*
> +			 * Skip frames needs the AS SDP to keep flowing during PR
> +			 * active, so it is mutually exclusive with disabling AS SDP
> +			 * transmission in active and with the DC3CO idle protocol.
> +			 */
> +			if (skip_frames) {
> +				pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_SKIP_FRAMES(skip_frames);
> +				pr_alpm_ctl &= ~PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE;
>   				pr_alpm_ctl &= ~PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL;
> +			} else {
> +				pr_alpm_ctl &= ~PR_ALPM_CTL_AS_SDP_SKIP_FRAMES_MASK;
> +
> +				if (crtc_state->disable_as_sdp_when_pr_active)
> +					pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE;
> +
> +				if (intel_display_power_dc3co_allowed(display))
> +					pr_alpm_ctl |= PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL;
> +			}
>   
>   			intel_de_write(display, PR_ALPM_CTL(display, cpu_transcoder),
>   				       pr_alpm_ctl);
> diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> index 16a9e3af198d..bb577e7e3bbd 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> @@ -276,6 +276,8 @@
>   #define  PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1_OR_T2	REG_FIELD_PREP(PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_MASK, 0)
>   #define  PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1		REG_FIELD_PREP(PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_MASK, 1)
>   #define  PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T2		REG_FIELD_PREP(PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_MASK, 2)
> +#define  PR_ALPM_CTL_AS_SDP_SKIP_FRAMES_MASK			REG_GENMASK(27, 16)
> +#define  PR_ALPM_CTL_AS_SDP_SKIP_FRAMES(frames)			REG_FIELD_PREP(PR_ALPM_CTL_AS_SDP_SKIP_FRAMES_MASK, (frames))
>   
>   #define _ALPM_CTL_A	0x60950
>   #define ALPM_CTL(dev_priv, tran)	_MMIO_TRANS2(dev_priv, tran, _ALPM_CTL_A)

LGTM.
Reviewed-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>


^ permalink raw reply	[flat|nested] 18+ messages in thread

* [v4 2/4] drm/i915/display: Force disable DC3co when AS SDP skip frames is enabled
  2026-08-31 21:34 [v4 0/4] drm/i915/display: Enable AS SDP Skip Frames Uma Shankar
                   ` (2 preceding siblings ...)
  2026-08-31 21:34 ` [v4 1/4] drm/i915/display: Enable periodic AS SDP skip frames Uma Shankar
@ 2026-08-31 21:34 ` Uma Shankar
  2026-09-02 16:29   ` Dibin Moolakadan Subrahmanian
  2026-09-03  6:18   ` Naladala, Ramanaidu
  2026-08-31 21:34 ` [v4 3/4] drm/i915/display: Reprogram AS SDP skip frames on seamless VRR transitions Uma Shankar
                   ` (3 subsequent siblings)
  7 siblings, 2 replies; 18+ messages in thread
From: Uma Shankar @ 2026-08-31 21:34 UTC (permalink / raw)
  To: intel-gfx, intel-xe; +Cc: dibin.moolakadan.subrahmanian, Uma Shankar

Periodic AS SDP (skip frames) relies on the AS SDP still being
transmitted while Panel Replay is active. DC3co uses the idle protocol
which suppresses AS SDP transmission entirely, so the two are mutually
exclusive: leaving DC3co enabled while skip frames is programmed breaks
the periodic AS SDP and the panel never sees the slower refresh.

Add intel_alpm_pr_as_sdp_skip_frames_enabled() as the single predicate
for "skip frames will be programmed" (mirroring the gating in
lnl_alpm_configure(), including that it only applies when VRR is not
active) and use it in intel_display_power_dc3co_compute() to force the
DC3co trigger to NONE. This drops the pipe onto the
DC_STATE_EN_UPTO_DC6 target instead of DC3co whenever skip frames is
active, without touching the DC state module parameter or the allowed
DC mask, and only for the skip-frame case.

v2: Fixed Sashiko review findings

Assisted-by: Claude:claude-opus-4-8
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c     | 23 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_alpm.h     |  2 ++
 .../drm/i915/display/intel_display_power.c    |  9 ++++++++
 3 files changed, 34 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index a6838e0fd3aa..0a33a89975bc 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -404,6 +404,29 @@ static u32 intel_pr_as_sdp_skip_frames(struct intel_dp *intel_dp)
 		     REG_FIELD_MAX(PR_ALPM_CTL_AS_SDP_SKIP_FRAMES_MASK));
 }
 
+/*
+ * Whether periodic AS SDP transmission (AS SDP skip frames) will be programmed
+ * for this Panel Replay config. The skip counter needs the AS SDP to keep
+ * flowing during PR active, which is incompatible with DC3co, so this is used
+ * to keep DC3co disabled while skip frames is enabled.
+ */
+bool intel_alpm_pr_as_sdp_skip_frames_enabled(struct intel_dp *intel_dp,
+					      const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(intel_dp);
+
+	/*
+	 * The AS SDP skip frames field only exists on Xe3p_LPD+. Periodic AS SDP
+	 * drives the panel down to its minimum refresh rate on its own, so it is
+	 * only used when VRR is not actively driving the refresh rate.
+	 */
+	if (DISPLAY_VER(display) < 35 || !intel_dp->as_sdp_supported ||
+	    !crtc_state->has_panel_replay || crtc_state->vrr.enable)
+		return false;
+
+	return intel_pr_as_sdp_skip_frames(intel_dp) > 0;
+}
+
 static void lnl_alpm_configure(struct intel_dp *intel_dp,
 			       const struct intel_crtc_state *crtc_state)
 {
diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h b/drivers/gpu/drm/i915/display/intel_alpm.h
index 1cf70668ab1b..328920027f1c 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.h
+++ b/drivers/gpu/drm/i915/display/intel_alpm.h
@@ -34,6 +34,8 @@ bool intel_alpm_aux_wake_supported(struct intel_dp *intel_dp);
 bool intel_alpm_aux_less_wake_supported(struct intel_dp *intel_dp);
 bool intel_alpm_is_alpm_aux_less(struct intel_dp *intel_dp,
 				 const struct intel_crtc_state *crtc_state);
+bool intel_alpm_pr_as_sdp_skip_frames_enabled(struct intel_dp *intel_dp,
+					      const struct intel_crtc_state *crtc_state);
 void intel_alpm_disable(struct intel_dp *intel_dp);
 bool intel_alpm_get_error(struct intel_dp *intel_dp);
 void intel_alpm_lobf_compute_config_late(struct intel_dp *intel_dp,
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 0ebec6e0c240..1b60ce2dd00c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -10,6 +10,7 @@
 #include <drm/intel/intel_pcode_regs.h>
 #include <drm/intel/step.h>
 
+#include "intel_alpm.h"
 #include "intel_backlight_regs.h"
 #include "intel_cdclk.h"
 #include "intel_clock_gating.h"
@@ -488,6 +489,14 @@ void intel_display_power_dc3co_compute(struct intel_atomic_state *state)
 	if (crtc_state->has_sel_update)
 		trigger |= DC3CO_TRIGGER_PSR2;
 
+	/*
+	 * Periodic AS SDP (skip frames) needs the AS SDP to keep flowing during
+	 * PR active, which is incompatible with DC3co. Keep DC3co disabled while
+	 * skip frames is enabled.
+	 */
+	if (intel_alpm_pr_as_sdp_skip_frames_enabled(intel_dp, crtc_state))
+		trigger = DC3CO_TRIGGER_NONE;
+
 done:
 	intel_display_power_dc3co_update(display, trigger);
 }
-- 
2.50.1


^ permalink raw reply related	[flat|nested] 18+ messages in thread

* Re: [v4 2/4] drm/i915/display: Force disable DC3co when AS SDP skip frames is enabled
  2026-08-31 21:34 ` [v4 2/4] drm/i915/display: Force disable DC3co when AS SDP skip frames is enabled Uma Shankar
@ 2026-09-02 16:29   ` Dibin Moolakadan Subrahmanian
  2026-09-03  6:18   ` Naladala, Ramanaidu
  1 sibling, 0 replies; 18+ messages in thread
From: Dibin Moolakadan Subrahmanian @ 2026-09-02 16:29 UTC (permalink / raw)
  To: Uma Shankar, intel-gfx, intel-xe

On 9/1/2026 3:04 AM, Uma Shankar wrote:
> Periodic AS SDP (skip frames) relies on the AS SDP still being
> transmitted while Panel Replay is active. DC3co uses the idle protocol
> which suppresses AS SDP transmission entirely, so the two are mutually
> exclusive: leaving DC3co enabled while skip frames is programmed breaks
> the periodic AS SDP and the panel never sees the slower refresh.
>
> Add intel_alpm_pr_as_sdp_skip_frames_enabled() as the single predicate
> for "skip frames will be programmed" (mirroring the gating in
> lnl_alpm_configure(), including that it only applies when VRR is not
> active) and use it in intel_display_power_dc3co_compute() to force the
> DC3co trigger to NONE. This drops the pipe onto the
> DC_STATE_EN_UPTO_DC6 target instead of DC3co whenever skip frames is
> active, without touching the DC state module parameter or the allowed
> DC mask, and only for the skip-frame case.
>
> v2: Fixed Sashiko review findings
>
> Assisted-by: Claude:claude-opus-4-8
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_alpm.c     | 23 +++++++++++++++++++
>   drivers/gpu/drm/i915/display/intel_alpm.h     |  2 ++
>   .../drm/i915/display/intel_display_power.c    |  9 ++++++++
>   3 files changed, 34 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index a6838e0fd3aa..0a33a89975bc 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -404,6 +404,29 @@ static u32 intel_pr_as_sdp_skip_frames(struct intel_dp *intel_dp)
>   		     REG_FIELD_MAX(PR_ALPM_CTL_AS_SDP_SKIP_FRAMES_MASK));
>   }
>   
> +/*
> + * Whether periodic AS SDP transmission (AS SDP skip frames) will be programmed
> + * for this Panel Replay config. The skip counter needs the AS SDP to keep
> + * flowing during PR active, which is incompatible with DC3co, so this is used
> + * to keep DC3co disabled while skip frames is enabled.
> + */
> +bool intel_alpm_pr_as_sdp_skip_frames_enabled(struct intel_dp *intel_dp,
> +					      const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(intel_dp);
> +
> +	/*
> +	 * The AS SDP skip frames field only exists on Xe3p_LPD+. Periodic AS SDP
> +	 * drives the panel down to its minimum refresh rate on its own, so it is
> +	 * only used when VRR is not actively driving the refresh rate.
> +	 */
> +	if (DISPLAY_VER(display) < 35 || !intel_dp->as_sdp_supported ||
> +	    !crtc_state->has_panel_replay || crtc_state->vrr.enable)
> +		return false;
> +
> +	return intel_pr_as_sdp_skip_frames(intel_dp) > 0;
> +}
> +
>   static void lnl_alpm_configure(struct intel_dp *intel_dp,
>   			       const struct intel_crtc_state *crtc_state)
>   {
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h b/drivers/gpu/drm/i915/display/intel_alpm.h
> index 1cf70668ab1b..328920027f1c 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.h
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.h
> @@ -34,6 +34,8 @@ bool intel_alpm_aux_wake_supported(struct intel_dp *intel_dp);
>   bool intel_alpm_aux_less_wake_supported(struct intel_dp *intel_dp);
>   bool intel_alpm_is_alpm_aux_less(struct intel_dp *intel_dp,
>   				 const struct intel_crtc_state *crtc_state);
> +bool intel_alpm_pr_as_sdp_skip_frames_enabled(struct intel_dp *intel_dp,
> +					      const struct intel_crtc_state *crtc_state);
>   void intel_alpm_disable(struct intel_dp *intel_dp);
>   bool intel_alpm_get_error(struct intel_dp *intel_dp);
>   void intel_alpm_lobf_compute_config_late(struct intel_dp *intel_dp,
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 0ebec6e0c240..1b60ce2dd00c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -10,6 +10,7 @@
>   #include <drm/intel/intel_pcode_regs.h>
>   #include <drm/intel/step.h>
>   
> +#include "intel_alpm.h"
>   #include "intel_backlight_regs.h"
>   #include "intel_cdclk.h"
>   #include "intel_clock_gating.h"
> @@ -488,6 +489,14 @@ void intel_display_power_dc3co_compute(struct intel_atomic_state *state)
>   	if (crtc_state->has_sel_update)
>   		trigger |= DC3CO_TRIGGER_PSR2;
>   
> +	/*
> +	 * Periodic AS SDP (skip frames) needs the AS SDP to keep flowing during
> +	 * PR active, which is incompatible with DC3co. Keep DC3co disabled while
> +	 * skip frames is enabled.
> +	 */
> +	if (intel_alpm_pr_as_sdp_skip_frames_enabled(intel_dp, crtc_state))
> +		trigger = DC3CO_TRIGGER_NONE;

I think this condition can be moved inside the for loop,
where we already have similar checks:
if (intel_alpm_pr_as_sdp_skip_frames_enabled(intel_dp, crtc_state))
     goto done;
This aligns with the existing checks for DC3CO entry.

Other than this, LGTM.
Reviewed-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>

> +
>   done:
>   	intel_display_power_dc3co_update(display, trigger);
>   }


^ permalink raw reply	[flat|nested] 18+ messages in thread

* Re: [v4 2/4] drm/i915/display: Force disable DC3co when AS SDP skip frames is enabled
  2026-08-31 21:34 ` [v4 2/4] drm/i915/display: Force disable DC3co when AS SDP skip frames is enabled Uma Shankar
  2026-09-02 16:29   ` Dibin Moolakadan Subrahmanian
@ 2026-09-03  6:18   ` Naladala, Ramanaidu
  1 sibling, 0 replies; 18+ messages in thread
From: Naladala, Ramanaidu @ 2026-09-03  6:18 UTC (permalink / raw)
  To: Uma Shankar, intel-gfx, intel-xe; +Cc: dibin.moolakadan.subrahmanian

Hi Uma,

On 9/1/2026 3:04 AM, Uma Shankar wrote:
> Periodic AS SDP (skip frames) relies on the AS SDP still being
> transmitted while Panel Replay is active. DC3co uses the idle protocol
> which suppresses AS SDP transmission entirely, so the two are mutually
> exclusive: leaving DC3co enabled while skip frames is programmed breaks
> the periodic AS SDP and the panel never sees the slower refresh.
>
> Add intel_alpm_pr_as_sdp_skip_frames_enabled() as the single predicate
> for "skip frames will be programmed" (mirroring the gating in
> lnl_alpm_configure(), including that it only applies when VRR is not
> active) and use it in intel_display_power_dc3co_compute() to force the
> DC3co trigger to NONE. This drops the pipe onto the
> DC_STATE_EN_UPTO_DC6 target instead of DC3co whenever skip frames is
> active, without touching the DC state module parameter or the allowed
> DC mask, and only for the skip-frame case.
>
> v2: Fixed Sashiko review findings
>
> Assisted-by: Claude:claude-opus-4-8
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_alpm.c     | 23 +++++++++++++++++++
>   drivers/gpu/drm/i915/display/intel_alpm.h     |  2 ++
>   .../drm/i915/display/intel_display_power.c    |  9 ++++++++
>   3 files changed, 34 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index a6838e0fd3aa..0a33a89975bc 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -404,6 +404,29 @@ static u32 intel_pr_as_sdp_skip_frames(struct intel_dp *intel_dp)
>   		     REG_FIELD_MAX(PR_ALPM_CTL_AS_SDP_SKIP_FRAMES_MASK));
>   }
>   
> +/*
> + * Whether periodic AS SDP transmission (AS SDP skip frames) will be programmed
> + * for this Panel Replay config. The skip counter needs the AS SDP to keep
> + * flowing during PR active, which is incompatible with DC3co, so this is used
> + * to keep DC3co disabled while skip frames is enabled.
> + */
> +bool intel_alpm_pr_as_sdp_skip_frames_enabled(struct intel_dp *intel_dp,
> +					      const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(intel_dp);
> +
> +	/*
> +	 * The AS SDP skip frames field only exists on Xe3p_LPD+. Periodic AS SDP
> +	 * drives the panel down to its minimum refresh rate on its own, so it is
> +	 * only used when VRR is not actively driving the refresh rate.
> +	 */
> +	if (DISPLAY_VER(display) < 35 || !intel_dp->as_sdp_supported ||
> +	    !crtc_state->has_panel_replay || crtc_state->vrr.enable)
> +		return false;
> +
> +	return intel_pr_as_sdp_skip_frames(intel_dp) > 0;
> +}
> +
>   static void lnl_alpm_configure(struct intel_dp *intel_dp,
>   			       const struct intel_crtc_state *crtc_state)
>   {
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h b/drivers/gpu/drm/i915/display/intel_alpm.h
> index 1cf70668ab1b..328920027f1c 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.h
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.h
> @@ -34,6 +34,8 @@ bool intel_alpm_aux_wake_supported(struct intel_dp *intel_dp);
>   bool intel_alpm_aux_less_wake_supported(struct intel_dp *intel_dp);
>   bool intel_alpm_is_alpm_aux_less(struct intel_dp *intel_dp,
>   				 const struct intel_crtc_state *crtc_state);
> +bool intel_alpm_pr_as_sdp_skip_frames_enabled(struct intel_dp *intel_dp,
> +					      const struct intel_crtc_state *crtc_state);
>   void intel_alpm_disable(struct intel_dp *intel_dp);
>   bool intel_alpm_get_error(struct intel_dp *intel_dp);
>   void intel_alpm_lobf_compute_config_late(struct intel_dp *intel_dp,
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 0ebec6e0c240..1b60ce2dd00c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -10,6 +10,7 @@
>   #include <drm/intel/intel_pcode_regs.h>
>   #include <drm/intel/step.h>
>   
> +#include "intel_alpm.h"
>   #include "intel_backlight_regs.h"
>   #include "intel_cdclk.h"
>   #include "intel_clock_gating.h"
> @@ -488,6 +489,14 @@ void intel_display_power_dc3co_compute(struct intel_atomic_state *state)
>   	if (crtc_state->has_sel_update)
>   		trigger |= DC3CO_TRIGGER_PSR2;
>   
> +	/*
> +	 * Periodic AS SDP (skip frames) needs the AS SDP to keep flowing during
> +	 * PR active, which is incompatible with DC3co. Keep DC3co disabled while
> +	 * skip frames is enabled.
> +	 */
> +	if (intel_alpm_pr_as_sdp_skip_frames_enabled(intel_dp, crtc_state))
> +		trigger = DC3CO_TRIGGER_NONE;
> +
>   done:
>   	intel_display_power_dc3co_update(display, trigger);
>   }
Verified locally not seen any issue.
Tested-by: Naladala Ramanaidu <ramanaidu.naladala@intel.com>

^ permalink raw reply	[flat|nested] 18+ messages in thread

* [v4 3/4] drm/i915/display: Reprogram AS SDP skip frames on seamless VRR transitions
  2026-08-31 21:34 [v4 0/4] drm/i915/display: Enable AS SDP Skip Frames Uma Shankar
                   ` (3 preceding siblings ...)
  2026-08-31 21:34 ` [v4 2/4] drm/i915/display: Force disable DC3co when AS SDP skip frames is enabled Uma Shankar
@ 2026-08-31 21:34 ` Uma Shankar
  2026-09-02 16:44   ` Dibin Moolakadan Subrahmanian
                     ` (2 more replies)
  2026-08-31 21:34 ` [v4 4/4] drm/i915/display: Gate periodic AS SDP skip frames behind a module parameter Uma Shankar
                   ` (2 subsequent siblings)
  7 siblings, 3 replies; 18+ messages in thread
From: Uma Shankar @ 2026-08-31 21:34 UTC (permalink / raw)
  To: intel-gfx, intel-xe; +Cc: dibin.moolakadan.subrahmanian, Uma Shankar

The AS SDP skip-frame count is written to PR_ALPM_CTL only from
lnl_alpm_configure(), which runs from intel_psr_enable_locked() on a
Panel Replay disabled->enabled transition. VRR, however, can be enabled
and disabled seamlessly - without a modeset and without cycling Panel
Replay (intel_crtc_vrr_enabling()/disabling() in the pipe update path).

As a result, when a panel comes up with VRR off the non-zero skip count
is programmed, and when VRR is later turned on seamlessly PR stays
enabled, lnl_alpm_configure() is not re-invoked, and the stale skip
count is left in the register. This also leaves the coupled AS SDP
transmission / DC3CO idle-protocol bits inconsistent with the DC3co
state, which is recomputed on every commit.

Factor the PR_ALPM_CTL AS SDP programming out of lnl_alpm_configure()
into intel_alpm_configure_pr_as_sdp() and expose
intel_alpm_pr_as_sdp_update(), which recomputes those fields for the
current VRR state. Call it from the seamless VRR enable and disable
sites (non-modeset only; a modeset re-runs PR enable anyway) so the skip
counter always matches whether VRR is actively driving the refresh rate.

v2: Fixed Sashiko review comments

Assisted-by: Claude:claude-opus-4-8
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c    | 119 +++++++++++++------
 drivers/gpu/drm/i915/display/intel_alpm.h    |   1 +
 drivers/gpu/drm/i915/display/intel_display.c |  18 +++
 3 files changed, 100 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index 0a33a89975bc..c784e77f610b 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -427,6 +427,85 @@ bool intel_alpm_pr_as_sdp_skip_frames_enabled(struct intel_dp *intel_dp,
 	return intel_pr_as_sdp_skip_frames(intel_dp) > 0;
 }
 
+/*
+ * Program the AS SDP portion of PR_ALPM_CTL: the transmission position, the
+ * skip-frame counter and the coupled AS SDP transmission / DC3CO idle-protocol
+ * bits. This is a full recompute of those fields (the base value is built from
+ * scratch, not read back), so it can be called both at PR enable time and when
+ * VRR is toggled seamlessly - which changes whether periodic AS SDP is used.
+ *
+ * Caller must hold intel_dp->alpm.lock.
+ */
+static void intel_alpm_configure_pr_as_sdp(struct intel_dp *intel_dp,
+					   const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(intel_dp);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 pr_alpm_ctl = get_pr_alpm_as_sdp_transmission_time(crtc_state);
+	u32 skip_frames = 0;
+
+	if (intel_alpm_pr_as_sdp_skip_frames_enabled(intel_dp, crtc_state))
+		skip_frames = intel_pr_as_sdp_skip_frames(intel_dp);
+
+	if (crtc_state->link_off_after_as_sdp_when_pr_active)
+		pr_alpm_ctl |= PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU;
+
+	/*
+	 * Skip frames needs the AS SDP to keep flowing during PR active, so it
+	 * is mutually exclusive with disabling AS SDP transmission in active and
+	 * with the DC3CO idle protocol.
+	 */
+	if (skip_frames) {
+		pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_SKIP_FRAMES(skip_frames);
+		pr_alpm_ctl &= ~PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE;
+		pr_alpm_ctl &= ~PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL;
+	} else {
+		pr_alpm_ctl &= ~PR_ALPM_CTL_AS_SDP_SKIP_FRAMES_MASK;
+
+		if (crtc_state->disable_as_sdp_when_pr_active)
+			pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE;
+
+		if (intel_display_power_dc3co_allowed(display))
+			pr_alpm_ctl |= PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL;
+	}
+
+	intel_de_write(display, PR_ALPM_CTL(display, cpu_transcoder), pr_alpm_ctl);
+}
+
+/*
+ * VRR can be enabled or disabled seamlessly, i.e. without a modeset and without
+ * cycling Panel Replay, so the AS SDP skip-frame programming done at PR enable
+ * time would otherwise go stale across a VRR toggle. Reprogram it here so the
+ * skip counter (and the coupled bits) matches the new VRR state.
+ */
+void intel_alpm_pr_as_sdp_update(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	struct intel_encoder *encoder;
+
+	/* AS SDP skip frames field only exists on Xe3p_LPD+ */
+	if (DISPLAY_VER(display) < 35)
+		return;
+
+	for_each_intel_encoder_mask(display->drm, encoder,
+				    crtc_state->uapi.encoder_mask) {
+		struct intel_dp *intel_dp;
+
+		if (!intel_encoder_is_dp(encoder))
+			continue;
+
+		intel_dp = enc_to_intel_dp(encoder);
+
+		if (!intel_dp->as_sdp_supported ||
+		    !intel_alpm_is_alpm_aux_less(intel_dp, crtc_state))
+			continue;
+
+		mutex_lock(&intel_dp->alpm.lock);
+		intel_alpm_configure_pr_as_sdp(intel_dp, crtc_state);
+		mutex_unlock(&intel_dp->alpm.lock);
+	}
+}
+
 static void lnl_alpm_configure(struct intel_dp *intel_dp,
 			       const struct intel_crtc_state *crtc_state)
 {
@@ -449,44 +528,8 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
 			ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS |
 			ALPM_CTL_AUX_LESS_WAKE_TIME(crtc_state->alpm_state.aux_less_wake_lines);
 
-		if (intel_dp->as_sdp_supported) {
-			u32 pr_alpm_ctl = get_pr_alpm_as_sdp_transmission_time(crtc_state);
-			u32 skip_frames = 0;
-
-			/*
-			 * AS SDP skip frames field only exists on Xe3p_LPD+, and
-			 * periodic AS SDP is a Panel Replay feature that is only
-			 * used when VRR is not actively driving the refresh rate.
-			 */
-			if (DISPLAY_VER(display) >= 35 && crtc_state->has_panel_replay &&
-			    !crtc_state->vrr.enable)
-				skip_frames = intel_pr_as_sdp_skip_frames(intel_dp);
-
-			if (crtc_state->link_off_after_as_sdp_when_pr_active)
-				pr_alpm_ctl |= PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU;
-
-			/*
-			 * Skip frames needs the AS SDP to keep flowing during PR
-			 * active, so it is mutually exclusive with disabling AS SDP
-			 * transmission in active and with the DC3CO idle protocol.
-			 */
-			if (skip_frames) {
-				pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_SKIP_FRAMES(skip_frames);
-				pr_alpm_ctl &= ~PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE;
-				pr_alpm_ctl &= ~PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL;
-			} else {
-				pr_alpm_ctl &= ~PR_ALPM_CTL_AS_SDP_SKIP_FRAMES_MASK;
-
-				if (crtc_state->disable_as_sdp_when_pr_active)
-					pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE;
-
-				if (intel_display_power_dc3co_allowed(display))
-					pr_alpm_ctl |= PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL;
-			}
-
-			intel_de_write(display, PR_ALPM_CTL(display, cpu_transcoder),
-				       pr_alpm_ctl);
-		}
+		if (intel_dp->as_sdp_supported)
+			intel_alpm_configure_pr_as_sdp(intel_dp, crtc_state);
 
 	} else {
 		alpm_ctl = ALPM_CTL_EXTENDED_FAST_WAKE_ENABLE |
diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h b/drivers/gpu/drm/i915/display/intel_alpm.h
index 328920027f1c..f8f605d94f96 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.h
+++ b/drivers/gpu/drm/i915/display/intel_alpm.h
@@ -36,6 +36,7 @@ bool intel_alpm_is_alpm_aux_less(struct intel_dp *intel_dp,
 				 const struct intel_crtc_state *crtc_state);
 bool intel_alpm_pr_as_sdp_skip_frames_enabled(struct intel_dp *intel_dp,
 					      const struct intel_crtc_state *crtc_state);
+void intel_alpm_pr_as_sdp_update(const struct intel_crtc_state *crtc_state);
 void intel_alpm_disable(struct intel_dp *intel_dp);
 bool intel_alpm_get_error(struct intel_dp *intel_dp);
 void intel_alpm_lobf_compute_config_late(struct intel_dp *intel_dp,
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index fc30a455bed3..9151ea6c15ab 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1232,6 +1232,14 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
 		intel_vrr_disable(old_crtc_state);
 		intel_vrr_dcb_reset(old_crtc_state, crtc);
 		intel_crtc_update_active_timings(old_crtc_state, false);
+
+		/*
+		 * VRR is being disabled seamlessly (no modeset, Panel Replay
+		 * stays enabled), so re-apply the AS SDP skip-frame programming
+		 * for the new (VRR off) state.
+		 */
+		if (!intel_crtc_needs_modeset(new_crtc_state))
+			intel_alpm_pr_as_sdp_update(new_crtc_state);
 	}
 
 	if (audio_disabling(old_crtc_state, new_crtc_state))
@@ -6971,6 +6979,16 @@ static void intel_update_crtc(struct intel_atomic_state *state,
 		intel_crtc_update_active_timings(new_crtc_state,
 						 new_crtc_state->vrr.enable);
 
+	/*
+	 * VRR is being enabled seamlessly (no modeset, Panel Replay stays
+	 * enabled), so re-apply the AS SDP skip-frame programming for the new
+	 * (VRR on) state. Done here, outside the vblank-evasion critical section
+	 * (which runs with interrupts disabled), because it takes alpm.lock.
+	 */
+	if (intel_crtc_vrr_enabling(state, crtc) &&
+	    !intel_crtc_needs_modeset(new_crtc_state))
+		intel_alpm_pr_as_sdp_update(new_crtc_state);
+
 	if (new_crtc_state->vrr.dc_balance.enable)
 		intel_vrr_dcb_increment_flip_count(new_crtc_state, crtc);
 
-- 
2.50.1


^ permalink raw reply related	[flat|nested] 18+ messages in thread

* Re: [v4 3/4] drm/i915/display: Reprogram AS SDP skip frames on seamless VRR transitions
  2026-08-31 21:34 ` [v4 3/4] drm/i915/display: Reprogram AS SDP skip frames on seamless VRR transitions Uma Shankar
@ 2026-09-02 16:44   ` Dibin Moolakadan Subrahmanian
  2026-09-03  6:21   ` Naladala, Ramanaidu
  2026-09-03  6:36   ` Naladala, Ramanaidu
  2 siblings, 0 replies; 18+ messages in thread
From: Dibin Moolakadan Subrahmanian @ 2026-09-02 16:44 UTC (permalink / raw)
  To: Uma Shankar, intel-gfx, intel-xe

On 9/1/2026 3:04 AM, Uma Shankar wrote:
> The AS SDP skip-frame count is written to PR_ALPM_CTL only from
> lnl_alpm_configure(), which runs from intel_psr_enable_locked() on a
> Panel Replay disabled->enabled transition. VRR, however, can be enabled
> and disabled seamlessly - without a modeset and without cycling Panel
> Replay (intel_crtc_vrr_enabling()/disabling() in the pipe update path).
>
> As a result, when a panel comes up with VRR off the non-zero skip count
> is programmed, and when VRR is later turned on seamlessly PR stays
> enabled, lnl_alpm_configure() is not re-invoked, and the stale skip
> count is left in the register. This also leaves the coupled AS SDP
> transmission / DC3CO idle-protocol bits inconsistent with the DC3co
> state, which is recomputed on every commit.
>
> Factor the PR_ALPM_CTL AS SDP programming out of lnl_alpm_configure()
> into intel_alpm_configure_pr_as_sdp() and expose
> intel_alpm_pr_as_sdp_update(), which recomputes those fields for the
> current VRR state. Call it from the seamless VRR enable and disable
> sites (non-modeset only; a modeset re-runs PR enable anyway) so the skip
> counter always matches whether VRR is actively driving the refresh rate.
>
> v2: Fixed Sashiko review comments
>
> Assisted-by: Claude:claude-opus-4-8
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_alpm.c    | 119 +++++++++++++------
>   drivers/gpu/drm/i915/display/intel_alpm.h    |   1 +
>   drivers/gpu/drm/i915/display/intel_display.c |  18 +++
>   3 files changed, 100 insertions(+), 38 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index 0a33a89975bc..c784e77f610b 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -427,6 +427,85 @@ bool intel_alpm_pr_as_sdp_skip_frames_enabled(struct intel_dp *intel_dp,
>   	return intel_pr_as_sdp_skip_frames(intel_dp) > 0;
>   }
>   
> +/*
> + * Program the AS SDP portion of PR_ALPM_CTL: the transmission position, the
> + * skip-frame counter and the coupled AS SDP transmission / DC3CO idle-protocol
> + * bits. This is a full recompute of those fields (the base value is built from
> + * scratch, not read back), so it can be called both at PR enable time and when
> + * VRR is toggled seamlessly - which changes whether periodic AS SDP is used.
> + *
> + * Caller must hold intel_dp->alpm.lock.
> + */
> +static void intel_alpm_configure_pr_as_sdp(struct intel_dp *intel_dp,
> +					   const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(intel_dp);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +	u32 pr_alpm_ctl = get_pr_alpm_as_sdp_transmission_time(crtc_state);
> +	u32 skip_frames = 0;
> +
> +	if (intel_alpm_pr_as_sdp_skip_frames_enabled(intel_dp, crtc_state))
> +		skip_frames = intel_pr_as_sdp_skip_frames(intel_dp);
> +
> +	if (crtc_state->link_off_after_as_sdp_when_pr_active)
> +		pr_alpm_ctl |= PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU;
> +
> +	/*
> +	 * Skip frames needs the AS SDP to keep flowing during PR active, so it
> +	 * is mutually exclusive with disabling AS SDP transmission in active and
> +	 * with the DC3CO idle protocol.
> +	 */
> +	if (skip_frames) {
> +		pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_SKIP_FRAMES(skip_frames);
> +		pr_alpm_ctl &= ~PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE;
> +		pr_alpm_ctl &= ~PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL;
> +	} else {
> +		pr_alpm_ctl &= ~PR_ALPM_CTL_AS_SDP_SKIP_FRAMES_MASK;
> +
> +		if (crtc_state->disable_as_sdp_when_pr_active)
> +			pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE;
> +
> +		if (intel_display_power_dc3co_allowed(display))
> +			pr_alpm_ctl |= PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL;
> +	}
> +
> +	intel_de_write(display, PR_ALPM_CTL(display, cpu_transcoder), pr_alpm_ctl);
> +}
> +
> +/*
> + * VRR can be enabled or disabled seamlessly, i.e. without a modeset and without
> + * cycling Panel Replay, so the AS SDP skip-frame programming done at PR enable
> + * time would otherwise go stale across a VRR toggle. Reprogram it here so the
> + * skip counter (and the coupled bits) matches the new VRR state.
> + */
> +void intel_alpm_pr_as_sdp_update(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	struct intel_encoder *encoder;
> +
> +	/* AS SDP skip frames field only exists on Xe3p_LPD+ */
> +	if (DISPLAY_VER(display) < 35)
> +		return;
> +
> +	for_each_intel_encoder_mask(display->drm, encoder,
> +				    crtc_state->uapi.encoder_mask) {
> +		struct intel_dp *intel_dp;
> +
> +		if (!intel_encoder_is_dp(encoder))
> +			continue;
> +
> +		intel_dp = enc_to_intel_dp(encoder);
> +
> +		if (!intel_dp->as_sdp_supported ||
> +		    !intel_alpm_is_alpm_aux_less(intel_dp, crtc_state))
> +			continue;
> +
> +		mutex_lock(&intel_dp->alpm.lock);
> +		intel_alpm_configure_pr_as_sdp(intel_dp, crtc_state);
> +		mutex_unlock(&intel_dp->alpm.lock);
> +	}
> +}
> +
>   static void lnl_alpm_configure(struct intel_dp *intel_dp,
>   			       const struct intel_crtc_state *crtc_state)
>   {
> @@ -449,44 +528,8 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
>   			ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS |
>   			ALPM_CTL_AUX_LESS_WAKE_TIME(crtc_state->alpm_state.aux_less_wake_lines);
>   
> -		if (intel_dp->as_sdp_supported) {
> -			u32 pr_alpm_ctl = get_pr_alpm_as_sdp_transmission_time(crtc_state);
> -			u32 skip_frames = 0;
> -
> -			/*
> -			 * AS SDP skip frames field only exists on Xe3p_LPD+, and
> -			 * periodic AS SDP is a Panel Replay feature that is only
> -			 * used when VRR is not actively driving the refresh rate.
> -			 */
> -			if (DISPLAY_VER(display) >= 35 && crtc_state->has_panel_replay &&
> -			    !crtc_state->vrr.enable)
> -				skip_frames = intel_pr_as_sdp_skip_frames(intel_dp);
> -
> -			if (crtc_state->link_off_after_as_sdp_when_pr_active)
> -				pr_alpm_ctl |= PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU;
> -
> -			/*
> -			 * Skip frames needs the AS SDP to keep flowing during PR
> -			 * active, so it is mutually exclusive with disabling AS SDP
> -			 * transmission in active and with the DC3CO idle protocol.
> -			 */
> -			if (skip_frames) {
> -				pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_SKIP_FRAMES(skip_frames);
> -				pr_alpm_ctl &= ~PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE;
> -				pr_alpm_ctl &= ~PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL;
> -			} else {
> -				pr_alpm_ctl &= ~PR_ALPM_CTL_AS_SDP_SKIP_FRAMES_MASK;
> -
> -				if (crtc_state->disable_as_sdp_when_pr_active)
> -					pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE;
> -
> -				if (intel_display_power_dc3co_allowed(display))
> -					pr_alpm_ctl |= PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL;
> -			}
> -
> -			intel_de_write(display, PR_ALPM_CTL(display, cpu_transcoder),
> -				       pr_alpm_ctl);
> -		}
> +		if (intel_dp->as_sdp_supported)
> +			intel_alpm_configure_pr_as_sdp(intel_dp, crtc_state);
>   
>   	} else {
>   		alpm_ctl = ALPM_CTL_EXTENDED_FAST_WAKE_ENABLE |
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h b/drivers/gpu/drm/i915/display/intel_alpm.h
> index 328920027f1c..f8f605d94f96 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.h
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.h
> @@ -36,6 +36,7 @@ bool intel_alpm_is_alpm_aux_less(struct intel_dp *intel_dp,
>   				 const struct intel_crtc_state *crtc_state);
>   bool intel_alpm_pr_as_sdp_skip_frames_enabled(struct intel_dp *intel_dp,
>   					      const struct intel_crtc_state *crtc_state);
> +void intel_alpm_pr_as_sdp_update(const struct intel_crtc_state *crtc_state);
>   void intel_alpm_disable(struct intel_dp *intel_dp);
>   bool intel_alpm_get_error(struct intel_dp *intel_dp);
>   void intel_alpm_lobf_compute_config_late(struct intel_dp *intel_dp,
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index fc30a455bed3..9151ea6c15ab 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1232,6 +1232,14 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
>   		intel_vrr_disable(old_crtc_state);
>   		intel_vrr_dcb_reset(old_crtc_state, crtc);
>   		intel_crtc_update_active_timings(old_crtc_state, false);
> +
> +		/*
> +		 * VRR is being disabled seamlessly (no modeset, Panel Replay
> +		 * stays enabled), so re-apply the AS SDP skip-frame programming
> +		 * for the new (VRR off) state.
> +		 */
> +		if (!intel_crtc_needs_modeset(new_crtc_state))
> +			intel_alpm_pr_as_sdp_update(new_crtc_state);
>   	}
>   
>   	if (audio_disabling(old_crtc_state, new_crtc_state))
> @@ -6971,6 +6979,16 @@ static void intel_update_crtc(struct intel_atomic_state *state,
>   		intel_crtc_update_active_timings(new_crtc_state,
>   						 new_crtc_state->vrr.enable);
>   
> +	/*
> +	 * VRR is being enabled seamlessly (no modeset, Panel Replay stays
> +	 * enabled), so re-apply the AS SDP skip-frame programming for the new
> +	 * (VRR on) state. Done here, outside the vblank-evasion critical section
> +	 * (which runs with interrupts disabled), because it takes alpm.lock.
> +	 */
> +	if (intel_crtc_vrr_enabling(state, crtc) &&
> +	    !intel_crtc_needs_modeset(new_crtc_state))
> +		intel_alpm_pr_as_sdp_update(new_crtc_state);
> +
>   	if (new_crtc_state->vrr.dc_balance.enable)
>   		intel_vrr_dcb_increment_flip_count(new_crtc_state, crtc);
>   

LGTM.
Reviewed-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>


^ permalink raw reply	[flat|nested] 18+ messages in thread

* Re: [v4 3/4] drm/i915/display: Reprogram AS SDP skip frames on seamless VRR transitions
  2026-08-31 21:34 ` [v4 3/4] drm/i915/display: Reprogram AS SDP skip frames on seamless VRR transitions Uma Shankar
  2026-09-02 16:44   ` Dibin Moolakadan Subrahmanian
@ 2026-09-03  6:21   ` Naladala, Ramanaidu
  2026-09-03  6:36   ` Naladala, Ramanaidu
  2 siblings, 0 replies; 18+ messages in thread
From: Naladala, Ramanaidu @ 2026-09-03  6:21 UTC (permalink / raw)
  To: Uma Shankar, intel-gfx, intel-xe; +Cc: dibin.moolakadan.subrahmanian

Hi Uma,

On 9/1/2026 3:04 AM, Uma Shankar wrote:
> The AS SDP skip-frame count is written to PR_ALPM_CTL only from
> lnl_alpm_configure(), which runs from intel_psr_enable_locked() on a
> Panel Replay disabled->enabled transition. VRR, however, can be enabled
> and disabled seamlessly - without a modeset and without cycling Panel
> Replay (intel_crtc_vrr_enabling()/disabling() in the pipe update path).
>
> As a result, when a panel comes up with VRR off the non-zero skip count
> is programmed, and when VRR is later turned on seamlessly PR stays
> enabled, lnl_alpm_configure() is not re-invoked, and the stale skip
> count is left in the register. This also leaves the coupled AS SDP
> transmission / DC3CO idle-protocol bits inconsistent with the DC3co
> state, which is recomputed on every commit.
>
> Factor the PR_ALPM_CTL AS SDP programming out of lnl_alpm_configure()
> into intel_alpm_configure_pr_as_sdp() and expose
> intel_alpm_pr_as_sdp_update(), which recomputes those fields for the
> current VRR state. Call it from the seamless VRR enable and disable
> sites (non-modeset only; a modeset re-runs PR enable anyway) so the skip
> counter always matches whether VRR is actively driving the refresh rate.
>
> v2: Fixed Sashiko review comments
>
> Assisted-by: Claude:claude-opus-4-8
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_alpm.c    | 119 +++++++++++++------
>   drivers/gpu/drm/i915/display/intel_alpm.h    |   1 +
>   drivers/gpu/drm/i915/display/intel_display.c |  18 +++
>   3 files changed, 100 insertions(+), 38 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index 0a33a89975bc..c784e77f610b 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -427,6 +427,85 @@ bool intel_alpm_pr_as_sdp_skip_frames_enabled(struct intel_dp *intel_dp,
>   	return intel_pr_as_sdp_skip_frames(intel_dp) > 0;
>   }
>   
> +/*
> + * Program the AS SDP portion of PR_ALPM_CTL: the transmission position, the
> + * skip-frame counter and the coupled AS SDP transmission / DC3CO idle-protocol
> + * bits. This is a full recompute of those fields (the base value is built from
> + * scratch, not read back), so it can be called both at PR enable time and when
> + * VRR is toggled seamlessly - which changes whether periodic AS SDP is used.
> + *
> + * Caller must hold intel_dp->alpm.lock.
> + */
> +static void intel_alpm_configure_pr_as_sdp(struct intel_dp *intel_dp,
> +					   const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(intel_dp);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +	u32 pr_alpm_ctl = get_pr_alpm_as_sdp_transmission_time(crtc_state);
> +	u32 skip_frames = 0;
> +
> +	if (intel_alpm_pr_as_sdp_skip_frames_enabled(intel_dp, crtc_state))
> +		skip_frames = intel_pr_as_sdp_skip_frames(intel_dp);
> +
> +	if (crtc_state->link_off_after_as_sdp_when_pr_active)
> +		pr_alpm_ctl |= PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU;
> +
> +	/*
> +	 * Skip frames needs the AS SDP to keep flowing during PR active, so it
> +	 * is mutually exclusive with disabling AS SDP transmission in active and
> +	 * with the DC3CO idle protocol.
> +	 */
> +	if (skip_frames) {
> +		pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_SKIP_FRAMES(skip_frames);
> +		pr_alpm_ctl &= ~PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE;
> +		pr_alpm_ctl &= ~PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL;
> +	} else {
> +		pr_alpm_ctl &= ~PR_ALPM_CTL_AS_SDP_SKIP_FRAMES_MASK;
> +
> +		if (crtc_state->disable_as_sdp_when_pr_active)
> +			pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE;
> +
> +		if (intel_display_power_dc3co_allowed(display))
> +			pr_alpm_ctl |= PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL;
> +	}
> +
> +	intel_de_write(display, PR_ALPM_CTL(display, cpu_transcoder), pr_alpm_ctl);
> +}
> +
> +/*
> + * VRR can be enabled or disabled seamlessly, i.e. without a modeset and without
> + * cycling Panel Replay, so the AS SDP skip-frame programming done at PR enable
> + * time would otherwise go stale across a VRR toggle. Reprogram it here so the
> + * skip counter (and the coupled bits) matches the new VRR state.
> + */
> +void intel_alpm_pr_as_sdp_update(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	struct intel_encoder *encoder;
> +
> +	/* AS SDP skip frames field only exists on Xe3p_LPD+ */
> +	if (DISPLAY_VER(display) < 35)
> +		return;
> +
> +	for_each_intel_encoder_mask(display->drm, encoder,
> +				    crtc_state->uapi.encoder_mask) {
> +		struct intel_dp *intel_dp;
> +
> +		if (!intel_encoder_is_dp(encoder))
> +			continue;
> +
> +		intel_dp = enc_to_intel_dp(encoder);
> +
> +		if (!intel_dp->as_sdp_supported ||
> +		    !intel_alpm_is_alpm_aux_less(intel_dp, crtc_state))
> +			continue;
> +
> +		mutex_lock(&intel_dp->alpm.lock);
> +		intel_alpm_configure_pr_as_sdp(intel_dp, crtc_state);
> +		mutex_unlock(&intel_dp->alpm.lock);
> +	}
> +}
> +
>   static void lnl_alpm_configure(struct intel_dp *intel_dp,
>   			       const struct intel_crtc_state *crtc_state)
>   {
> @@ -449,44 +528,8 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
>   			ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS |
>   			ALPM_CTL_AUX_LESS_WAKE_TIME(crtc_state->alpm_state.aux_less_wake_lines);
>   
> -		if (intel_dp->as_sdp_supported) {
> -			u32 pr_alpm_ctl = get_pr_alpm_as_sdp_transmission_time(crtc_state);
> -			u32 skip_frames = 0;
> -
> -			/*
> -			 * AS SDP skip frames field only exists on Xe3p_LPD+, and
> -			 * periodic AS SDP is a Panel Replay feature that is only
> -			 * used when VRR is not actively driving the refresh rate.
> -			 */
> -			if (DISPLAY_VER(display) >= 35 && crtc_state->has_panel_replay &&
> -			    !crtc_state->vrr.enable)
> -				skip_frames = intel_pr_as_sdp_skip_frames(intel_dp);
> -
> -			if (crtc_state->link_off_after_as_sdp_when_pr_active)
> -				pr_alpm_ctl |= PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU;
> -
> -			/*
> -			 * Skip frames needs the AS SDP to keep flowing during PR
> -			 * active, so it is mutually exclusive with disabling AS SDP
> -			 * transmission in active and with the DC3CO idle protocol.
> -			 */
> -			if (skip_frames) {
> -				pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_SKIP_FRAMES(skip_frames);
> -				pr_alpm_ctl &= ~PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE;
> -				pr_alpm_ctl &= ~PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL;
> -			} else {
> -				pr_alpm_ctl &= ~PR_ALPM_CTL_AS_SDP_SKIP_FRAMES_MASK;
> -
> -				if (crtc_state->disable_as_sdp_when_pr_active)
> -					pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE;
> -
> -				if (intel_display_power_dc3co_allowed(display))
> -					pr_alpm_ctl |= PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL;
> -			}
> -
> -			intel_de_write(display, PR_ALPM_CTL(display, cpu_transcoder),
> -				       pr_alpm_ctl);
> -		}
> +		if (intel_dp->as_sdp_supported)
> +			intel_alpm_configure_pr_as_sdp(intel_dp, crtc_state);
>   
>   	} else {
>   		alpm_ctl = ALPM_CTL_EXTENDED_FAST_WAKE_ENABLE |
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h b/drivers/gpu/drm/i915/display/intel_alpm.h
> index 328920027f1c..f8f605d94f96 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.h
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.h
> @@ -36,6 +36,7 @@ bool intel_alpm_is_alpm_aux_less(struct intel_dp *intel_dp,
>   				 const struct intel_crtc_state *crtc_state);
>   bool intel_alpm_pr_as_sdp_skip_frames_enabled(struct intel_dp *intel_dp,
>   					      const struct intel_crtc_state *crtc_state);
> +void intel_alpm_pr_as_sdp_update(const struct intel_crtc_state *crtc_state);
>   void intel_alpm_disable(struct intel_dp *intel_dp);
>   bool intel_alpm_get_error(struct intel_dp *intel_dp);
>   void intel_alpm_lobf_compute_config_late(struct intel_dp *intel_dp,
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index fc30a455bed3..9151ea6c15ab 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1232,6 +1232,14 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
>   		intel_vrr_disable(old_crtc_state);
>   		intel_vrr_dcb_reset(old_crtc_state, crtc);
>   		intel_crtc_update_active_timings(old_crtc_state, false);
> +
> +		/*
> +		 * VRR is being disabled seamlessly (no modeset, Panel Replay
> +		 * stays enabled), so re-apply the AS SDP skip-frame programming
> +		 * for the new (VRR off) state.
> +		 */
> +		if (!intel_crtc_needs_modeset(new_crtc_state))
> +			intel_alpm_pr_as_sdp_update(new_crtc_state);
>   	}
>   
>   	if (audio_disabling(old_crtc_state, new_crtc_state))
> @@ -6971,6 +6979,16 @@ static void intel_update_crtc(struct intel_atomic_state *state,
>   		intel_crtc_update_active_timings(new_crtc_state,
>   						 new_crtc_state->vrr.enable);
>   
> +	/*
> +	 * VRR is being enabled seamlessly (no modeset, Panel Replay stays
> +	 * enabled), so re-apply the AS SDP skip-frame programming for the new
> +	 * (VRR on) state. Done here, outside the vblank-evasion critical section
> +	 * (which runs with interrupts disabled), because it takes alpm.lock.
> +	 */
> +	if (intel_crtc_vrr_enabling(state, crtc) &&
> +	    !intel_crtc_needs_modeset(new_crtc_state))
> +		intel_alpm_pr_as_sdp_update(new_crtc_state);
> +
>   	if (new_crtc_state->vrr.dc_balance.enable)
>   		intel_vrr_dcb_increment_flip_count(new_crtc_state, crtc);

Verified locally. Not seen any issue.

Tested-by: Naladala Ramanaidu <ramanaidu.naladala@intel.com>

>   

^ permalink raw reply	[flat|nested] 18+ messages in thread

* Re: [v4 3/4] drm/i915/display: Reprogram AS SDP skip frames on seamless VRR transitions
  2026-08-31 21:34 ` [v4 3/4] drm/i915/display: Reprogram AS SDP skip frames on seamless VRR transitions Uma Shankar
  2026-09-02 16:44   ` Dibin Moolakadan Subrahmanian
  2026-09-03  6:21   ` Naladala, Ramanaidu
@ 2026-09-03  6:36   ` Naladala, Ramanaidu
  2 siblings, 0 replies; 18+ messages in thread
From: Naladala, Ramanaidu @ 2026-09-03  6:36 UTC (permalink / raw)
  To: Uma Shankar, intel-gfx, intel-xe; +Cc: dibin.moolakadan.subrahmanian

Hi Uma,

On 9/1/2026 3:04 AM, Uma Shankar wrote:
> The AS SDP skip-frame count is written to PR_ALPM_CTL only from
> lnl_alpm_configure(), which runs from intel_psr_enable_locked() on a
> Panel Replay disabled->enabled transition. VRR, however, can be enabled
> and disabled seamlessly - without a modeset and without cycling Panel
> Replay (intel_crtc_vrr_enabling()/disabling() in the pipe update path).
>
> As a result, when a panel comes up with VRR off the non-zero skip count
> is programmed, and when VRR is later turned on seamlessly PR stays
> enabled, lnl_alpm_configure() is not re-invoked, and the stale skip
> count is left in the register. This also leaves the coupled AS SDP
> transmission / DC3CO idle-protocol bits inconsistent with the DC3co
> state, which is recomputed on every commit.
>
> Factor the PR_ALPM_CTL AS SDP programming out of lnl_alpm_configure()
> into intel_alpm_configure_pr_as_sdp() and expose
> intel_alpm_pr_as_sdp_update(), which recomputes those fields for the
> current VRR state. Call it from the seamless VRR enable and disable
> sites (non-modeset only; a modeset re-runs PR enable anyway) so the skip
> counter always matches whether VRR is actively driving the refresh rate.
>
> v2: Fixed Sashiko review comments
>
> Assisted-by: Claude:claude-opus-4-8
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_alpm.c    | 119 +++++++++++++------
>   drivers/gpu/drm/i915/display/intel_alpm.h    |   1 +
>   drivers/gpu/drm/i915/display/intel_display.c |  18 +++
>   3 files changed, 100 insertions(+), 38 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index 0a33a89975bc..c784e77f610b 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -427,6 +427,85 @@ bool intel_alpm_pr_as_sdp_skip_frames_enabled(struct intel_dp *intel_dp,
>   	return intel_pr_as_sdp_skip_frames(intel_dp) > 0;
>   }
>   
> +/*
> + * Program the AS SDP portion of PR_ALPM_CTL: the transmission position, the
> + * skip-frame counter and the coupled AS SDP transmission / DC3CO idle-protocol
> + * bits. This is a full recompute of those fields (the base value is built from
> + * scratch, not read back), so it can be called both at PR enable time and when
> + * VRR is toggled seamlessly - which changes whether periodic AS SDP is used.
> + *
> + * Caller must hold intel_dp->alpm.lock.
> + */
> +static void intel_alpm_configure_pr_as_sdp(struct intel_dp *intel_dp,
> +					   const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(intel_dp);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +	u32 pr_alpm_ctl = get_pr_alpm_as_sdp_transmission_time(crtc_state);
> +	u32 skip_frames = 0;
> +
> +	if (intel_alpm_pr_as_sdp_skip_frames_enabled(intel_dp, crtc_state))
> +		skip_frames = intel_pr_as_sdp_skip_frames(intel_dp);
> +
> +	if (crtc_state->link_off_after_as_sdp_when_pr_active)
> +		pr_alpm_ctl |= PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU;
> +
> +	/*
> +	 * Skip frames needs the AS SDP to keep flowing during PR active, so it
> +	 * is mutually exclusive with disabling AS SDP transmission in active and
> +	 * with the DC3CO idle protocol.
> +	 */
> +	if (skip_frames) {
> +		pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_SKIP_FRAMES(skip_frames);
> +		pr_alpm_ctl &= ~PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE;
> +		pr_alpm_ctl &= ~PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL;
> +	} else {
> +		pr_alpm_ctl &= ~PR_ALPM_CTL_AS_SDP_SKIP_FRAMES_MASK;
> +
> +		if (crtc_state->disable_as_sdp_when_pr_active)
> +			pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE;
> +
> +		if (intel_display_power_dc3co_allowed(display))
> +			pr_alpm_ctl |= PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL;
> +	}
> +
> +	intel_de_write(display, PR_ALPM_CTL(display, cpu_transcoder), pr_alpm_ctl);
> +}
> +
> +/*
> + * VRR can be enabled or disabled seamlessly, i.e. without a modeset and without
> + * cycling Panel Replay, so the AS SDP skip-frame programming done at PR enable
> + * time would otherwise go stale across a VRR toggle. Reprogram it here so the
> + * skip counter (and the coupled bits) matches the new VRR state.
> + */
> +void intel_alpm_pr_as_sdp_update(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	struct intel_encoder *encoder;
> +
> +	/* AS SDP skip frames field only exists on Xe3p_LPD+ */
> +	if (DISPLAY_VER(display) < 35)
> +		return;
> +
> +	for_each_intel_encoder_mask(display->drm, encoder,
> +				    crtc_state->uapi.encoder_mask) {
> +		struct intel_dp *intel_dp;
> +
> +		if (!intel_encoder_is_dp(encoder))
> +			continue;
> +
> +		intel_dp = enc_to_intel_dp(encoder);
> +
> +		if (!intel_dp->as_sdp_supported ||
> +		    !intel_alpm_is_alpm_aux_less(intel_dp, crtc_state))
> +			continue;
> +
> +		mutex_lock(&intel_dp->alpm.lock);
> +		intel_alpm_configure_pr_as_sdp(intel_dp, crtc_state);
> +		mutex_unlock(&intel_dp->alpm.lock);
> +	}
> +}
> +
>   static void lnl_alpm_configure(struct intel_dp *intel_dp,
>   			       const struct intel_crtc_state *crtc_state)
>   {
> @@ -449,44 +528,8 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
>   			ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS |
>   			ALPM_CTL_AUX_LESS_WAKE_TIME(crtc_state->alpm_state.aux_less_wake_lines);
>   
> -		if (intel_dp->as_sdp_supported) {
> -			u32 pr_alpm_ctl = get_pr_alpm_as_sdp_transmission_time(crtc_state);
> -			u32 skip_frames = 0;
> -
> -			/*
> -			 * AS SDP skip frames field only exists on Xe3p_LPD+, and
> -			 * periodic AS SDP is a Panel Replay feature that is only
> -			 * used when VRR is not actively driving the refresh rate.
> -			 */
> -			if (DISPLAY_VER(display) >= 35 && crtc_state->has_panel_replay &&
> -			    !crtc_state->vrr.enable)
> -				skip_frames = intel_pr_as_sdp_skip_frames(intel_dp);
> -
> -			if (crtc_state->link_off_after_as_sdp_when_pr_active)
> -				pr_alpm_ctl |= PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU;
> -
> -			/*
> -			 * Skip frames needs the AS SDP to keep flowing during PR
> -			 * active, so it is mutually exclusive with disabling AS SDP
> -			 * transmission in active and with the DC3CO idle protocol.
> -			 */
> -			if (skip_frames) {
> -				pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_SKIP_FRAMES(skip_frames);
> -				pr_alpm_ctl &= ~PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE;
> -				pr_alpm_ctl &= ~PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL;
> -			} else {
> -				pr_alpm_ctl &= ~PR_ALPM_CTL_AS_SDP_SKIP_FRAMES_MASK;
> -
> -				if (crtc_state->disable_as_sdp_when_pr_active)
> -					pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE;
> -
> -				if (intel_display_power_dc3co_allowed(display))
> -					pr_alpm_ctl |= PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL;
> -			}
> -
> -			intel_de_write(display, PR_ALPM_CTL(display, cpu_transcoder),
> -				       pr_alpm_ctl);
> -		}
> +		if (intel_dp->as_sdp_supported)
> +			intel_alpm_configure_pr_as_sdp(intel_dp, crtc_state);
>   
>   	} else {
>   		alpm_ctl = ALPM_CTL_EXTENDED_FAST_WAKE_ENABLE |
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h b/drivers/gpu/drm/i915/display/intel_alpm.h
> index 328920027f1c..f8f605d94f96 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.h
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.h
> @@ -36,6 +36,7 @@ bool intel_alpm_is_alpm_aux_less(struct intel_dp *intel_dp,
>   				 const struct intel_crtc_state *crtc_state);
>   bool intel_alpm_pr_as_sdp_skip_frames_enabled(struct intel_dp *intel_dp,
>   					      const struct intel_crtc_state *crtc_state);
> +void intel_alpm_pr_as_sdp_update(const struct intel_crtc_state *crtc_state);
>   void intel_alpm_disable(struct intel_dp *intel_dp);
>   bool intel_alpm_get_error(struct intel_dp *intel_dp);
>   void intel_alpm_lobf_compute_config_late(struct intel_dp *intel_dp,
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index fc30a455bed3..9151ea6c15ab 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1232,6 +1232,14 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
>   		intel_vrr_disable(old_crtc_state);
>   		intel_vrr_dcb_reset(old_crtc_state, crtc);
>   		intel_crtc_update_active_timings(old_crtc_state, false);
> +
> +		/*
> +		 * VRR is being disabled seamlessly (no modeset, Panel Replay
> +		 * stays enabled), so re-apply the AS SDP skip-frame programming
> +		 * for the new (VRR off) state.
> +		 */
> +		if (!intel_crtc_needs_modeset(new_crtc_state))
> +			intel_alpm_pr_as_sdp_update(new_crtc_state);
>   	}
>   
>   	if (audio_disabling(old_crtc_state, new_crtc_state))
> @@ -6971,6 +6979,16 @@ static void intel_update_crtc(struct intel_atomic_state *state,
>   		intel_crtc_update_active_timings(new_crtc_state,
>   						 new_crtc_state->vrr.enable);
>   
> +	/*
> +	 * VRR is being enabled seamlessly (no modeset, Panel Replay stays
> +	 * enabled), so re-apply the AS SDP skip-frame programming for the new
> +	 * (VRR on) state. Done here, outside the vblank-evasion critical section
> +	 * (which runs with interrupts disabled), because it takes alpm.lock.
> +	 */
> +	if (intel_crtc_vrr_enabling(state, crtc) &&
> +	    !intel_crtc_needs_modeset(new_crtc_state))
> +		intel_alpm_pr_as_sdp_update(new_crtc_state);
> +
>   	if (new_crtc_state->vrr.dc_balance.enable)
>   		intel_vrr_dcb_increment_flip_count(new_crtc_state, crtc);
Tested-by: Naladala Ramanaidu <ramanaidu.naladala@intel.com>
>   

^ permalink raw reply	[flat|nested] 18+ messages in thread

* [v4 4/4] drm/i915/display: Gate periodic AS SDP skip frames behind a module parameter
  2026-08-31 21:34 [v4 0/4] drm/i915/display: Enable AS SDP Skip Frames Uma Shankar
                   ` (4 preceding siblings ...)
  2026-08-31 21:34 ` [v4 3/4] drm/i915/display: Reprogram AS SDP skip frames on seamless VRR transitions Uma Shankar
@ 2026-08-31 21:34 ` Uma Shankar
  2026-08-31 22:28   ` sashiko-bot
                     ` (2 more replies)
  2026-08-31 22:00 ` ✓ Xe.CI.BAT: success for drm/i915/display: Enable AS SDP Skip Frames (rev5) Patchwork
  2026-08-31 23:07 ` ✗ Xe.CI.FULL: failure " Patchwork
  7 siblings, 3 replies; 18+ messages in thread
From: Uma Shankar @ 2026-08-31 21:34 UTC (permalink / raw)
  To: intel-gfx, intel-xe; +Cc: dibin.moolakadan.subrahmanian, Uma Shankar

Periodic AS SDP (skip frames) drives a Panel Replay panel down toward its
minimum refresh rate. It is a new, panel- and platform-sensitive behaviour,
so keep it opt-in rather than enabling it unconditionally.

Add a display module parameter, periodic_assdp_enable, shared by both the
i915 and xe drivers via the intel_display_params infrastructure. It defaults
to false (feature disabled); set it to true to enable periodic AS SDP.

Gate the feature at its single choke point, intel_pr_as_sdp_skip_frames():
returning a zero skip count when the parameter is off makes both the
PR_ALPM_CTL programming (intel_alpm_configure_pr_as_sdp()) and the DC3co
force-disable predicate (intel_alpm_pr_as_sdp_skip_frames_enabled()) a no-op,
so AS SDP continues to be sent on every frame as before.

Assisted-by: Claude:claude-opus-4-8
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c           | 5 +++++
 drivers/gpu/drm/i915/display/intel_display_params.c | 6 ++++++
 drivers/gpu/drm/i915/display/intel_display_params.h | 1 +
 3 files changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index c784e77f610b..537cad13f0b4 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -392,11 +392,16 @@ static u32 get_pr_alpm_as_sdp_transmission_time(const struct intel_crtc_state *c
  */
 static u32 intel_pr_as_sdp_skip_frames(struct intel_dp *intel_dp)
 {
+	struct intel_display *display = to_intel_display(intel_dp);
 	const struct drm_display_info *info =
 		&intel_dp->attached_connector->base.display_info;
 	int max_vrefresh = info->monitor_range.max_vfreq;
 	int min_vrefresh = info->monitor_range.min_vfreq;
 
+	/* Off by default; gated by the periodic_assdp_enable module parameter. */
+	if (!display->params.periodic_assdp_enable)
+		return 0;
+
 	if (min_vrefresh <= 0 || max_vrefresh <= min_vrefresh)
 		return 0;
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c b/drivers/gpu/drm/i915/display/intel_display_params.c
index 2aed110c5b09..a845d29610cf 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.c
+++ b/drivers/gpu/drm/i915/display/intel_display_params.c
@@ -139,6 +139,12 @@ intel_display_param_named_unsafe(enable_dmc_wl, int, 0400,
 	"(-1=use per-chip default, 0=disabled, 1=enabled, 2=match any register, 3=always locked) "
 	"Default: -1");
 
+intel_display_param_named_unsafe(periodic_assdp_enable, bool, 0600,
+	"Enable periodic Adaptive-Sync SDP (AS SDP skip frames) for Panel Replay "
+	"to drive the panel down to its minimum refresh rate "
+	"(0=disabled, 1=enabled) "
+	"Default: 0");
+
 __maybe_unused
 static void _param_print_bool(struct drm_printer *p, const char *driver_name,
 			      const char *name, bool val)
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h b/drivers/gpu/drm/i915/display/intel_display_params.h
index b95ecf728daa..4d912aab4811 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.h
+++ b/drivers/gpu/drm/i915/display/intel_display_params.h
@@ -50,6 +50,7 @@ struct drm_printer;
 	param(bool, psr_safest_params, false, 0400) \
 	param(bool, enable_psr2_sel_fetch, true, 0400) \
 	param(int, enable_dmc_wl, -1, 0400) \
+	param(bool, periodic_assdp_enable, false, 0600) \
 
 #define MEMBER(T, member, ...) T member;
 struct intel_display_params {
-- 
2.50.1


^ permalink raw reply related	[flat|nested] 18+ messages in thread

* Re: [v4 4/4] drm/i915/display: Gate periodic AS SDP skip frames behind a module parameter
  2026-08-31 21:34 ` [v4 4/4] drm/i915/display: Gate periodic AS SDP skip frames behind a module parameter Uma Shankar
@ 2026-08-31 22:28   ` sashiko-bot
  2026-09-02 18:00   ` Dibin Moolakadan Subrahmanian
  2026-09-03  6:37   ` Naladala, Ramanaidu
  2 siblings, 0 replies; 18+ messages in thread
From: sashiko-bot @ 2026-08-31 22:28 UTC (permalink / raw)
  To: Uma Shankar; +Cc: intel-xe, intel-gfx

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The 'periodic_assdp_enable' module parameter is defined with a writable sysfs permission (0600) instead of the required read-only permission (0400), creating a broken runtime interface.
--

commit 717499623e1a0ce1f0b28267e96deb4b7a335eaf
Author: Uma Shankar <uma.shankar@intel.com>

drm/i915/display: Gate periodic AS SDP skip frames behind a module parameter

This commit introduces a new module parameter, periodic_assdp_enable, to
control periodic Adaptive-Sync SDP skip frames for Panel Replay. The
parameter defaults to false and uses the intel_display_params
infrastructure.

> diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c b/drivers/gpu/drm/i915/display/intel_display_params.c
> index 2aed110c5b090..a845d29610cf1 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_params.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_params.c
[ ... ]
> @@ -139,6 +139,12 @@ intel_display_param_named_unsafe(enable_dmc_wl, int, 0400,
>  	"(-1=use per-chip default, 0=disabled, 1=enabled, 2=match any register, 3=always locked) "
>  	"Default: -1");
>  
> +intel_display_param_named_unsafe(periodic_assdp_enable, bool, 0600,

[Severity: Medium]
Does this parameter need to be writable (0600) at runtime?

Since global module parameters are copied to display->params during driver
initialization, changing this value via sysfs at runtime doesn't appear to
take effect on active displays.

Should this be read-only (0400) like the other intel_display_params to
prevent creating a misleading sysfs interface?

> +	"Enable periodic Adaptive-Sync SDP (AS SDP skip frames) for Panel Replay "
> +	"to drive the panel down to its minimum refresh rate "
> +	"(0=disabled, 1=enabled) "
> +	"Default: 0");
> +

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260831213421.1804635-1-uma.shankar@intel.com?part=4

^ permalink raw reply	[flat|nested] 18+ messages in thread

* Re: [v4 4/4] drm/i915/display: Gate periodic AS SDP skip frames behind a module parameter
  2026-08-31 21:34 ` [v4 4/4] drm/i915/display: Gate periodic AS SDP skip frames behind a module parameter Uma Shankar
  2026-08-31 22:28   ` sashiko-bot
@ 2026-09-02 18:00   ` Dibin Moolakadan Subrahmanian
  2026-09-03  6:37   ` Naladala, Ramanaidu
  2 siblings, 0 replies; 18+ messages in thread
From: Dibin Moolakadan Subrahmanian @ 2026-09-02 18:00 UTC (permalink / raw)
  To: Uma Shankar, intel-gfx, intel-xe

On 9/1/2026 3:04 AM, Uma Shankar wrote:
> Periodic AS SDP (skip frames) drives a Panel Replay panel down toward its
> minimum refresh rate. It is a new, panel- and platform-sensitive behaviour,
> so keep it opt-in rather than enabling it unconditionally.
>
> Add a display module parameter, periodic_assdp_enable, shared by both the
> i915 and xe drivers via the intel_display_params infrastructure. It defaults
> to false (feature disabled); set it to true to enable periodic AS SDP.
>
> Gate the feature at its single choke point, intel_pr_as_sdp_skip_frames():
> returning a zero skip count when the parameter is off makes both the
> PR_ALPM_CTL programming (intel_alpm_configure_pr_as_sdp()) and the DC3co
> force-disable predicate (intel_alpm_pr_as_sdp_skip_frames_enabled()) a no-op,
> so AS SDP continues to be sent on every frame as before.
>
> Assisted-by: Claude:claude-opus-4-8
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_alpm.c           | 5 +++++
>   drivers/gpu/drm/i915/display/intel_display_params.c | 6 ++++++
>   drivers/gpu/drm/i915/display/intel_display_params.h | 1 +
>   3 files changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index c784e77f610b..537cad13f0b4 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -392,11 +392,16 @@ static u32 get_pr_alpm_as_sdp_transmission_time(const struct intel_crtc_state *c
>    */
>   static u32 intel_pr_as_sdp_skip_frames(struct intel_dp *intel_dp)
>   {
> +	struct intel_display *display = to_intel_display(intel_dp);
>   	const struct drm_display_info *info =
>   		&intel_dp->attached_connector->base.display_info;
>   	int max_vrefresh = info->monitor_range.max_vfreq;
>   	int min_vrefresh = info->monitor_range.min_vfreq;
>   
> +	/* Off by default; gated by the periodic_assdp_enable module parameter. */
> +	if (!display->params.periodic_assdp_enable)
> +		return 0;
> +
>   	if (min_vrefresh <= 0 || max_vrefresh <= min_vrefresh)
>   		return 0;
>   
> diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c b/drivers/gpu/drm/i915/display/intel_display_params.c
> index 2aed110c5b09..a845d29610cf 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_params.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_params.c
> @@ -139,6 +139,12 @@ intel_display_param_named_unsafe(enable_dmc_wl, int, 0400,
>   	"(-1=use per-chip default, 0=disabled, 1=enabled, 2=match any register, 3=always locked) "
>   	"Default: -1");
>   
> +intel_display_param_named_unsafe(periodic_assdp_enable, bool, 0600,
> +	"Enable periodic Adaptive-Sync SDP (AS SDP skip frames) for Panel Replay "
> +	"to drive the panel down to its minimum refresh rate "
> +	"(0=disabled, 1=enabled) "
> +	"Default: 0");
> +
>   __maybe_unused
>   static void _param_print_bool(struct drm_printer *p, const char *driver_name,
>   			      const char *name, bool val)
> diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h b/drivers/gpu/drm/i915/display/intel_display_params.h
> index b95ecf728daa..4d912aab4811 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_params.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_params.h
> @@ -50,6 +50,7 @@ struct drm_printer;
>   	param(bool, psr_safest_params, false, 0400) \
>   	param(bool, enable_psr2_sel_fetch, true, 0400) \
>   	param(int, enable_dmc_wl, -1, 0400) \
> +	param(bool, periodic_assdp_enable, false, 0600) \
>   
>   #define MEMBER(T, member, ...) T member;
>   struct intel_display_params {

Wondering if we can rename the parameter to|enable_periodic_assdp| to match the existing params.
Also, I assume the|0600| write permission is intentional to allow runtime enable/disable for testing.

Other than this, LGTM.
Reviewed-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>



^ permalink raw reply	[flat|nested] 18+ messages in thread

* Re: [v4 4/4] drm/i915/display: Gate periodic AS SDP skip frames behind a module parameter
  2026-08-31 21:34 ` [v4 4/4] drm/i915/display: Gate periodic AS SDP skip frames behind a module parameter Uma Shankar
  2026-08-31 22:28   ` sashiko-bot
  2026-09-02 18:00   ` Dibin Moolakadan Subrahmanian
@ 2026-09-03  6:37   ` Naladala, Ramanaidu
  2 siblings, 0 replies; 18+ messages in thread
From: Naladala, Ramanaidu @ 2026-09-03  6:37 UTC (permalink / raw)
  To: Uma Shankar, intel-gfx, intel-xe; +Cc: dibin.moolakadan.subrahmanian

Hi Uma,

On 9/1/2026 3:04 AM, Uma Shankar wrote:
> Periodic AS SDP (skip frames) drives a Panel Replay panel down toward its
> minimum refresh rate. It is a new, panel- and platform-sensitive behaviour,
> so keep it opt-in rather than enabling it unconditionally.
>
> Add a display module parameter, periodic_assdp_enable, shared by both the
> i915 and xe drivers via the intel_display_params infrastructure. It defaults
> to false (feature disabled); set it to true to enable periodic AS SDP.
>
> Gate the feature at its single choke point, intel_pr_as_sdp_skip_frames():
> returning a zero skip count when the parameter is off makes both the
> PR_ALPM_CTL programming (intel_alpm_configure_pr_as_sdp()) and the DC3co
> force-disable predicate (intel_alpm_pr_as_sdp_skip_frames_enabled()) a no-op,
> so AS SDP continues to be sent on every frame as before.
>
> Assisted-by: Claude:claude-opus-4-8
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_alpm.c           | 5 +++++
>   drivers/gpu/drm/i915/display/intel_display_params.c | 6 ++++++
>   drivers/gpu/drm/i915/display/intel_display_params.h | 1 +
>   3 files changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index c784e77f610b..537cad13f0b4 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -392,11 +392,16 @@ static u32 get_pr_alpm_as_sdp_transmission_time(const struct intel_crtc_state *c
>    */
>   static u32 intel_pr_as_sdp_skip_frames(struct intel_dp *intel_dp)
>   {
> +	struct intel_display *display = to_intel_display(intel_dp);
>   	const struct drm_display_info *info =
>   		&intel_dp->attached_connector->base.display_info;
>   	int max_vrefresh = info->monitor_range.max_vfreq;
>   	int min_vrefresh = info->monitor_range.min_vfreq;
>   
> +	/* Off by default; gated by the periodic_assdp_enable module parameter. */
> +	if (!display->params.periodic_assdp_enable)
> +		return 0;
> +
>   	if (min_vrefresh <= 0 || max_vrefresh <= min_vrefresh)
>   		return 0;
>   
> diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c b/drivers/gpu/drm/i915/display/intel_display_params.c
> index 2aed110c5b09..a845d29610cf 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_params.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_params.c
> @@ -139,6 +139,12 @@ intel_display_param_named_unsafe(enable_dmc_wl, int, 0400,
>   	"(-1=use per-chip default, 0=disabled, 1=enabled, 2=match any register, 3=always locked) "
>   	"Default: -1");
>   
> +intel_display_param_named_unsafe(periodic_assdp_enable, bool, 0600,
> +	"Enable periodic Adaptive-Sync SDP (AS SDP skip frames) for Panel Replay "
> +	"to drive the panel down to its minimum refresh rate "
> +	"(0=disabled, 1=enabled) "
> +	"Default: 0");
> +
>   __maybe_unused
>   static void _param_print_bool(struct drm_printer *p, const char *driver_name,
>   			      const char *name, bool val)
> diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h b/drivers/gpu/drm/i915/display/intel_display_params.h
> index b95ecf728daa..4d912aab4811 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_params.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_params.h
> @@ -50,6 +50,7 @@ struct drm_printer;
>   	param(bool, psr_safest_params, false, 0400) \
>   	param(bool, enable_psr2_sel_fetch, true, 0400) \
>   	param(int, enable_dmc_wl, -1, 0400) \
> +	param(bool, periodic_assdp_enable, false, 0600) \
>   
>   #define MEMBER(T, member, ...) T member;
>   struct intel_display_params {
Tested-by: Naladala Ramanaidu <ramanaidu.naladala@intel.com>

^ permalink raw reply	[flat|nested] 18+ messages in thread

* ✓ Xe.CI.BAT: success for drm/i915/display: Enable AS SDP Skip Frames (rev5)
  2026-08-31 21:34 [v4 0/4] drm/i915/display: Enable AS SDP Skip Frames Uma Shankar
                   ` (5 preceding siblings ...)
  2026-08-31 21:34 ` [v4 4/4] drm/i915/display: Gate periodic AS SDP skip frames behind a module parameter Uma Shankar
@ 2026-08-31 22:00 ` Patchwork
  2026-08-31 23:07 ` ✗ Xe.CI.FULL: failure " Patchwork
  7 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2026-08-31 22:00 UTC (permalink / raw)
  To: Uma Shankar; +Cc: intel-xe

[-- Attachment #1: Type: text/plain, Size: 873 bytes --]

== Series Details ==

Series: drm/i915/display: Enable AS SDP Skip Frames (rev5)
URL   : https://patchwork.freedesktop.org/series/162015/
State : success

== Summary ==

CI Bug Log - changes from xe-5665-43b9a5e9d30783bb6f4d7dacdd1739184666940f_BAT -> xe-pw-162015v5_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (13 -> 13)
------------------------------

  No changes in participating hosts


Changes
-------

  No changes found


Build changes
-------------

  * Linux: xe-5665-43b9a5e9d30783bb6f4d7dacdd1739184666940f -> xe-pw-162015v5

  IGT_9078: 9078
  xe-5665-43b9a5e9d30783bb6f4d7dacdd1739184666940f: 43b9a5e9d30783bb6f4d7dacdd1739184666940f
  xe-pw-162015v5: 162015v5

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/index.html

[-- Attachment #2: Type: text/html, Size: 1421 bytes --]

^ permalink raw reply	[flat|nested] 18+ messages in thread

* ✗ Xe.CI.FULL: failure for drm/i915/display: Enable AS SDP Skip Frames (rev5)
  2026-08-31 21:34 [v4 0/4] drm/i915/display: Enable AS SDP Skip Frames Uma Shankar
                   ` (6 preceding siblings ...)
  2026-08-31 22:00 ` ✓ Xe.CI.BAT: success for drm/i915/display: Enable AS SDP Skip Frames (rev5) Patchwork
@ 2026-08-31 23:07 ` Patchwork
  7 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2026-08-31 23:07 UTC (permalink / raw)
  To: Uma Shankar; +Cc: intel-xe

[-- Attachment #1: Type: text/plain, Size: 49615 bytes --]

== Series Details ==

Series: drm/i915/display: Enable AS SDP Skip Frames (rev5)
URL   : https://patchwork.freedesktop.org/series/162015/
State : failure

== Summary ==

CI Bug Log - changes from xe-5665-43b9a5e9d30783bb6f4d7dacdd1739184666940f_FULL -> xe-pw-162015v5_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-162015v5_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-162015v5_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-162015v5_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@xe_exec_threads@threads-hang-userptr-invalidate-race:
    - shard-lnl:          [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5665-43b9a5e9d30783bb6f4d7dacdd1739184666940f/shard-lnl-7/igt@xe_exec_threads@threads-hang-userptr-invalidate-race.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-5/igt@xe_exec_threads@threads-hang-userptr-invalidate-race.html

  
Known issues
------------

  Here are the changes found in xe-pw-162015v5_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@intel_hwmon@hwmon-write:
    - shard-lnl:          NOTRUN -> [SKIP][3] ([Intel XE#1125] / [Intel XE#7312])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-1/igt@intel_hwmon@hwmon-write.html

  * igt@kms_big_fb@4-tiled-8bpp-rotate-270:
    - shard-lnl:          NOTRUN -> [SKIP][4] ([Intel XE#1407]) +5 other tests skip
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-7/igt@kms_big_fb@4-tiled-8bpp-rotate-270.html

  * igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-lnl:          NOTRUN -> [SKIP][5] ([Intel XE#7059] / [Intel XE#7085])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-3/igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_big_fb@y-tiled-32bpp-rotate-0:
    - shard-bmg:          NOTRUN -> [SKIP][6] ([Intel XE#1124]) +2 other tests skip
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-bmg-2/igt@kms_big_fb@y-tiled-32bpp-rotate-0.html

  * igt@kms_big_fb@y-tiled-addfb:
    - shard-lnl:          NOTRUN -> [SKIP][7] ([Intel XE#1467] / [Intel XE#7367])
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-7/igt@kms_big_fb@y-tiled-addfb.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-lnl:          NOTRUN -> [SKIP][8] ([Intel XE#1124]) +8 other tests skip
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-7/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_bw@connected-linear-tiling-4-displays-target-2560x1440p:
    - shard-lnl:          NOTRUN -> [SKIP][9] ([Intel XE#8365]) +1 other test skip
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-3/igt@kms_bw@connected-linear-tiling-4-displays-target-2560x1440p.html

  * igt@kms_bw@connected-linear-tiling-4-displays-target-3840x2160p:
    - shard-bmg:          NOTRUN -> [SKIP][10] ([Intel XE#7679])
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-bmg-2/igt@kms_bw@connected-linear-tiling-4-displays-target-3840x2160p.html

  * igt@kms_bw@linear-tiling-2-displays-target-1920x1080p:
    - shard-lnl:          NOTRUN -> [SKIP][11] ([Intel XE#367]) +1 other test skip
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-1/igt@kms_bw@linear-tiling-2-displays-target-1920x1080p.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs@pipe-b-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][12] ([Intel XE#2669] / [Intel XE#7389]) +3 other tests skip
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-5/igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs@pipe-b-edp-1.html

  * igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs:
    - shard-lnl:          NOTRUN -> [SKIP][13] ([Intel XE#2887]) +11 other tests skip
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-1/igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
    - shard-bmg:          [PASS][14] -> [INCOMPLETE][15] ([Intel XE#7084] / [Intel XE#8150]) +1 other test incomplete
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5665-43b9a5e9d30783bb6f4d7dacdd1739184666940f/shard-bmg-4/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-bmg-1/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-a-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][16] ([Intel XE#2669] / [Intel XE#3433] / [Intel XE#7389]) +3 other tests skip
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-7/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-a-edp-1.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc:
    - shard-lnl:          NOTRUN -> [SKIP][17] ([Intel XE#3432]) +2 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-3/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc.html

  * igt@kms_ccs@missing-ccs-buffer-y-tiled-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][18] ([Intel XE#2887]) +4 other tests skip
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-bmg-2/igt@kms_ccs@missing-ccs-buffer-y-tiled-ccs.html

  * igt@kms_cdclk@plane-scaling:
    - shard-lnl:          NOTRUN -> [SKIP][19] ([Intel XE#4416] / [Intel XE#7381]) +3 other tests skip
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-5/igt@kms_cdclk@plane-scaling.html

  * igt@kms_chamelium_audio@hdmi-audio-after-suspend:
    - shard-lnl:          NOTRUN -> [SKIP][20] ([Intel XE#2252])
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-3/igt@kms_chamelium_audio@hdmi-audio-after-suspend.html

  * igt@kms_chamelium_color@ctm-blue-to-red:
    - shard-lnl:          NOTRUN -> [SKIP][21] ([Intel XE#306] / [Intel XE#7358])
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-7/igt@kms_chamelium_color@ctm-blue-to-red.html

  * igt@kms_chamelium_color@ctm-red-to-blue:
    - shard-bmg:          NOTRUN -> [SKIP][22] ([Intel XE#2325] / [Intel XE#7358])
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-bmg-2/igt@kms_chamelium_color@ctm-red-to-blue.html

  * igt@kms_chamelium_edid@hdmi-edid-change-during-suspend:
    - shard-lnl:          NOTRUN -> [SKIP][23] ([Intel XE#373]) +8 other tests skip
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-5/igt@kms_chamelium_edid@hdmi-edid-change-during-suspend.html

  * igt@kms_chamelium_hpd@dp-hpd-storm-disable:
    - shard-bmg:          NOTRUN -> [SKIP][24] ([Intel XE#2252])
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-bmg-2/igt@kms_chamelium_hpd@dp-hpd-storm-disable.html

  * igt@kms_content_protection@content-type-change:
    - shard-lnl:          NOTRUN -> [SKIP][25] ([Intel XE#7642])
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-1/igt@kms_content_protection@content-type-change.html

  * igt@kms_content_protection@dp-mst-type-0:
    - shard-lnl:          NOTRUN -> [SKIP][26] ([Intel XE#307] / [Intel XE#6974])
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-5/igt@kms_content_protection@dp-mst-type-0.html

  * igt@kms_content_protection@dp-mst-type-1-suspend-resume:
    - shard-bmg:          NOTRUN -> [SKIP][27] ([Intel XE#6974])
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-bmg-2/igt@kms_content_protection@dp-mst-type-1-suspend-resume.html

  * igt@kms_content_protection@mei-interface:
    - shard-lnl:          NOTRUN -> [SKIP][28] ([Intel XE#1468] / [Intel XE#7396])
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-7/igt@kms_content_protection@mei-interface.html

  * igt@kms_cursor_crc@cursor-onscreen-128x42:
    - shard-lnl:          NOTRUN -> [SKIP][29] ([Intel XE#1424]) +5 other tests skip
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-7/igt@kms_cursor_crc@cursor-onscreen-128x42.html

  * igt@kms_cursor_crc@cursor-onscreen-512x170:
    - shard-lnl:          NOTRUN -> [SKIP][30] ([Intel XE#2321] / [Intel XE#7355])
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-5/igt@kms_cursor_crc@cursor-onscreen-512x170.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-legacy:
    - shard-lnl:          NOTRUN -> [SKIP][31] ([Intel XE#309] / [Intel XE#7343]) +6 other tests skip
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-5/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html

  * igt@kms_display_modes@extended-mode-basic:
    - shard-lnl:          NOTRUN -> [SKIP][32] ([Intel XE#4302])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-1/igt@kms_display_modes@extended-mode-basic.html

  * igt@kms_dp_link_training@non-uhbr-mst:
    - shard-bmg:          NOTRUN -> [SKIP][33] ([Intel XE#4354] / [Intel XE#5882])
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-bmg-2/igt@kms_dp_link_training@non-uhbr-mst.html

  * igt@kms_dsc@dsc-fractional-bpp:
    - shard-bmg:          NOTRUN -> [SKIP][34] ([Intel XE#8265])
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-bmg-2/igt@kms_dsc@dsc-fractional-bpp.html

  * igt@kms_dsc@dsc-with-output-formats-with-bpc-ultrajoiner:
    - shard-lnl:          NOTRUN -> [SKIP][35] ([Intel XE#8265]) +4 other tests skip
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-3/igt@kms_dsc@dsc-with-output-formats-with-bpc-ultrajoiner.html

  * igt@kms_feature_discovery@display-2x:
    - shard-lnl:          NOTRUN -> [SKIP][36] ([Intel XE#702] / [Intel XE#7344])
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-5/igt@kms_feature_discovery@display-2x.html

  * igt@kms_flip@2x-flip-vs-dpms:
    - shard-lnl:          NOTRUN -> [SKIP][37] ([Intel XE#1421]) +9 other tests skip
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-3/igt@kms_flip@2x-flip-vs-dpms.html

  * igt@kms_flip@flip-vs-expired-vblank@a-edp1:
    - shard-lnl:          [PASS][38] -> [FAIL][39] ([Intel XE#301]) +2 other tests fail
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5665-43b9a5e9d30783bb6f4d7dacdd1739184666940f/shard-lnl-7/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html

  * igt@kms_flip@wf_vblank-ts-check:
    - shard-bmg:          [PASS][40] -> [FAIL][41] ([Intel XE#5408] / [Intel XE#6266])
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5665-43b9a5e9d30783bb6f4d7dacdd1739184666940f/shard-bmg-5/igt@kms_flip@wf_vblank-ts-check.html
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-bmg-4/igt@kms_flip@wf_vblank-ts-check.html

  * igt@kms_flip@wf_vblank-ts-check@d-dp2:
    - shard-bmg:          [PASS][42] -> [FAIL][43] ([Intel XE#6266]) +2 other tests fail
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5665-43b9a5e9d30783bb6f4d7dacdd1739184666940f/shard-bmg-5/igt@kms_flip@wf_vblank-ts-check@d-dp2.html
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-bmg-4/igt@kms_flip@wf_vblank-ts-check@d-dp2.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling:
    - shard-bmg:          NOTRUN -> [SKIP][44] ([Intel XE#7178] / [Intel XE#7351])
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-bmg-2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling:
    - shard-lnl:          NOTRUN -> [SKIP][45] ([Intel XE#1397] / [Intel XE#1745] / [Intel XE#7385]) +2 other tests skip
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-7/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-default-mode:
    - shard-lnl:          NOTRUN -> [SKIP][46] ([Intel XE#1397] / [Intel XE#7385]) +2 other tests skip
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-5/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling:
    - shard-lnl:          NOTRUN -> [SKIP][47] ([Intel XE#7178] / [Intel XE#7351]) +3 other tests skip
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-7/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-nv12-linear-to-nv12-linear-reflect-x:
    - shard-bmg:          NOTRUN -> [SKIP][48] ([Intel XE#7179])
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-bmg-2/igt@kms_flip_scaled_crc@flip-nv12-linear-to-nv12-linear-reflect-x.html

  * igt@kms_frontbuffer_tracking@drrs-2p-pri-indfb-multidraw:
    - shard-bmg:          NOTRUN -> [SKIP][49] ([Intel XE#2311]) +13 other tests skip
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-2p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-blt:
    - shard-lnl:          NOTRUN -> [SKIP][50] ([Intel XE#656] / [Intel XE#7905]) +37 other tests skip
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-5/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@drrs-modesetfrombusy:
    - shard-lnl:          NOTRUN -> [SKIP][51] ([Intel XE#6312] / [Intel XE#651]) +8 other tests skip
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-7/igt@kms_frontbuffer_tracking@drrs-modesetfrombusy.html

  * igt@kms_frontbuffer_tracking@drrshdr-abgr161616f-draw-render:
    - shard-lnl:          NOTRUN -> [SKIP][52] ([Intel XE#7061]) +4 other tests skip
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-7/igt@kms_frontbuffer_tracking@drrshdr-abgr161616f-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][53] ([Intel XE#4141]) +3 other tests skip
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-1p-offscreen-pri-indfb-draw-blt:
    - shard-lnl:          NOTRUN -> [SKIP][54] ([Intel XE#6312]) +19 other tests skip
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-5/igt@kms_frontbuffer_tracking@fbcdrrs-1p-offscreen-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrshdr-2p-scndscrn-cur-indfb-draw-render:
    - shard-lnl:          NOTRUN -> [SKIP][55] ([Intel XE#7905]) +44 other tests skip
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-7/igt@kms_frontbuffer_tracking@fbcdrrshdr-2p-scndscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbchdr-argb161616f-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][56] ([Intel XE#7061])
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-bmg-2/igt@kms_frontbuffer_tracking@fbchdr-argb161616f-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-primscrn-cur-indfb-draw-blt:
    - shard-lnl:          NOTRUN -> [SKIP][57] ([Intel XE#7865]) +27 other tests skip
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-3/igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-tiling-y:
    - shard-bmg:          NOTRUN -> [SKIP][58] ([Intel XE#7399])
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcpsrhdr-tiling-y.html

  * igt@kms_frontbuffer_tracking@psr-argb161616f-draw-blt:
    - shard-lnl:          NOTRUN -> [SKIP][59] ([Intel XE#7061] / [Intel XE#7356]) +3 other tests skip
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-3/igt@kms_frontbuffer_tracking@psr-argb161616f-draw-blt.html

  * igt@kms_frontbuffer_tracking@psrhdr-1p-pri-indfb-multidraw:
    - shard-bmg:          NOTRUN -> [SKIP][60] ([Intel XE#2313]) +12 other tests skip
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-bmg-2/igt@kms_frontbuffer_tracking@psrhdr-1p-pri-indfb-multidraw.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-lnl:          NOTRUN -> [SKIP][61] ([Intel XE#3374] / [Intel XE#3544])
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-1/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_hdr@static-swap:
    - shard-lnl:          NOTRUN -> [SKIP][62] ([Intel XE#1503])
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-3/igt@kms_hdr@static-swap.html

  * igt@kms_joiner@invalid-modeset-force-big-joiner:
    - shard-lnl:          NOTRUN -> [SKIP][63] ([Intel XE#7086] / [Intel XE#7390])
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-1/igt@kms_joiner@invalid-modeset-force-big-joiner.html

  * igt@kms_mst@mst-suspend-read-crc:
    - shard-lnl:          NOTRUN -> [SKIP][64] ([Intel XE#8348])
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-7/igt@kms_mst@mst-suspend-read-crc.html

  * igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-modifier:
    - shard-bmg:          NOTRUN -> [SKIP][65] ([Intel XE#7283]) +1 other test skip
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-bmg-2/igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-modifier.html

  * igt@kms_plane@pixel-format-4-tiled-lnl-ccs-modifier@pipe-a-plane-5:
    - shard-lnl:          NOTRUN -> [SKIP][66] ([Intel XE#8303]) +1 other test skip
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-7/igt@kms_plane@pixel-format-4-tiled-lnl-ccs-modifier@pipe-a-plane-5.html

  * igt@kms_plane@pixel-format-4-tiled-mtl-mc-ccs-modifier:
    - shard-lnl:          NOTRUN -> [SKIP][67] ([Intel XE#7283]) +4 other tests skip
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-5/igt@kms_plane@pixel-format-4-tiled-mtl-mc-ccs-modifier.html

  * igt@kms_plane_lowres@tiling-none@pipe-b-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][68] ([Intel XE#599] / [Intel XE#7382]) +3 other tests skip
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-1/igt@kms_plane_lowres@tiling-none@pipe-b-edp-1.html

  * igt@kms_plane_multiple@2x-tiling-y:
    - shard-lnl:          NOTRUN -> [SKIP][69] ([Intel XE#4596] / [Intel XE#5854]) +1 other test skip
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-1/igt@kms_plane_multiple@2x-tiling-y.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-a:
    - shard-lnl:          NOTRUN -> [SKIP][70] ([Intel XE#2763] / [Intel XE#6886]) +9 other tests skip
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-7/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-a.html

  * igt@kms_pm_backlight@bad-brightness:
    - shard-bmg:          NOTRUN -> [SKIP][71] ([Intel XE#7376] / [Intel XE#7760] / [Intel XE#870])
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-bmg-2/igt@kms_pm_backlight@bad-brightness.html

  * igt@kms_pm_rpm@dpms-non-lpsp:
    - shard-lnl:          NOTRUN -> [SKIP][72] ([Intel XE#1439] / [Intel XE#3141] / [Intel XE#7383])
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-3/igt@kms_pm_rpm@dpms-non-lpsp.html

  * igt@kms_pm_rpm@package-g7:
    - shard-lnl:          NOTRUN -> [SKIP][73] ([Intel XE#6813])
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-3/igt@kms_pm_rpm@package-g7.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf:
    - shard-lnl:          NOTRUN -> [SKIP][74] ([Intel XE#2893] / [Intel XE#4608] / [Intel XE#7304])
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-1/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf@pipe-a-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][75] ([Intel XE#4608])
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-1/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf@pipe-a-edp-1.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf@pipe-b-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][76] ([Intel XE#4608] / [Intel XE#7304])
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-1/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf@pipe-b-edp-1.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf:
    - shard-bmg:          NOTRUN -> [SKIP][77] ([Intel XE#1489])
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-bmg-2/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@pr-overlay-plane-move-continuous-sf:
    - shard-lnl:          NOTRUN -> [SKIP][78] ([Intel XE#2893] / [Intel XE#7304]) +4 other tests skip
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-5/igt@kms_psr2_sf@pr-overlay-plane-move-continuous-sf.html

  * igt@kms_psr2_su@page_flip-nv12:
    - shard-lnl:          NOTRUN -> [SKIP][79] ([Intel XE#1128] / [Intel XE#7413])
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-3/igt@kms_psr2_su@page_flip-nv12.html

  * igt@kms_psr@fbc-psr2-primary-blt@edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][80] ([Intel XE#1406] / [Intel XE#4609] / [Intel XE#7345]) +2 other tests skip
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-5/igt@kms_psr@fbc-psr2-primary-blt@edp-1.html

  * igt@kms_psr@fbc-psr2-primary-render:
    - shard-lnl:          NOTRUN -> [SKIP][81] ([Intel XE#1406] / [Intel XE#7345]) +2 other tests skip
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-1/igt@kms_psr@fbc-psr2-primary-render.html

  * igt@kms_psr@pr-basic:
    - shard-bmg:          NOTRUN -> [SKIP][82] ([Intel XE#2234] / [Intel XE#2850]) +1 other test skip
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-bmg-2/igt@kms_psr@pr-basic.html

  * igt@kms_psr@pr-cursor-plane-move:
    - shard-lnl:          NOTRUN -> [SKIP][83] ([Intel XE#1406]) +2 other tests skip
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-5/igt@kms_psr@pr-cursor-plane-move.html

  * igt@kms_rotation_crc@primary-rotation-90:
    - shard-lnl:          NOTRUN -> [SKIP][84] ([Intel XE#3414] / [Intel XE#3904] / [Intel XE#7342]) +2 other tests skip
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-7/igt@kms_rotation_crc@primary-rotation-90.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
    - shard-bmg:          NOTRUN -> [SKIP][85] ([Intel XE#2330] / [Intel XE#5813])
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-bmg-2/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html

  * igt@kms_setmode@invalid-clone-exclusive-crtc:
    - shard-lnl:          NOTRUN -> [SKIP][86] ([Intel XE#1435])
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-1/igt@kms_setmode@invalid-clone-exclusive-crtc.html

  * igt@kms_vrr@seamless-rr-switch-drrs:
    - shard-lnl:          NOTRUN -> [SKIP][87] ([Intel XE#1499])
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-5/igt@kms_vrr@seamless-rr-switch-drrs.html

  * igt@xe_ccs@vm-bind-decompress:
    - shard-lnl:          NOTRUN -> [SKIP][88] ([Intel XE#7644])
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-7/igt@xe_ccs@vm-bind-decompress.html

  * igt@xe_compute_preempt@compute-preempt-many-vram-evict:
    - shard-lnl:          NOTRUN -> [SKIP][89] ([Intel XE#5191] / [Intel XE#7316] / [Intel XE#7346])
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-5/igt@xe_compute_preempt@compute-preempt-many-vram-evict.html

  * igt@xe_configfs@survivability-mode:
    - shard-lnl:          NOTRUN -> [SKIP][90] ([Intel XE#8428])
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-1/igt@xe_configfs@survivability-mode.html

  * igt@xe_create@multigpu-create-massive-size:
    - shard-bmg:          NOTRUN -> [SKIP][91] ([Intel XE#2504] / [Intel XE#7319] / [Intel XE#7350])
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-bmg-2/igt@xe_create@multigpu-create-massive-size.html

  * igt@xe_evict@evict-beng-cm-threads-small:
    - shard-lnl:          NOTRUN -> [SKIP][92] ([Intel XE#6540] / [Intel XE#688]) +10 other tests skip
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-1/igt@xe_evict@evict-beng-cm-threads-small.html

  * igt@xe_exec_balancer@twice-cm-virtual-userptr-invalidate-race:
    - shard-lnl:          NOTRUN -> [SKIP][93] ([Intel XE#7482]) +19 other tests skip
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-7/igt@xe_exec_balancer@twice-cm-virtual-userptr-invalidate-race.html

  * igt@xe_exec_basic@multigpu-once-userptr-invalidate:
    - shard-lnl:          NOTRUN -> [SKIP][94] ([Intel XE#1392]) +9 other tests skip
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-7/igt@xe_exec_basic@multigpu-once-userptr-invalidate.html

  * igt@xe_exec_basic@multigpu-once-userptr-rebind:
    - shard-bmg:          NOTRUN -> [SKIP][95] ([Intel XE#2322] / [Intel XE#7372]) +1 other test skip
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-bmg-2/igt@xe_exec_basic@multigpu-once-userptr-rebind.html

  * igt@xe_exec_fault_mode@many-execqueues-multi-queue-userptr-invalidate-imm:
    - shard-bmg:          NOTRUN -> [SKIP][96] ([Intel XE#8374]) +1 other test skip
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-bmg-2/igt@xe_exec_fault_mode@many-execqueues-multi-queue-userptr-invalidate-imm.html

  * igt@xe_exec_fault_mode@once-multi-queue-userptr-rebind:
    - shard-lnl:          NOTRUN -> [SKIP][97] ([Intel XE#8374]) +10 other tests skip
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-7/igt@xe_exec_fault_mode@once-multi-queue-userptr-rebind.html

  * igt@xe_exec_multi_queue@many-execs-preempt-mode-userptr:
    - shard-lnl:          NOTRUN -> [SKIP][98] ([Intel XE#8364]) +28 other tests skip
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-7/igt@xe_exec_multi_queue@many-execs-preempt-mode-userptr.html

  * igt@xe_exec_multi_queue@two-queues-preempt-mode-priority-smem:
    - shard-bmg:          NOTRUN -> [SKIP][99] ([Intel XE#8364]) +6 other tests skip
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-bmg-2/igt@xe_exec_multi_queue@two-queues-preempt-mode-priority-smem.html

  * igt@xe_exec_reset@multi-queue-close-execqueues:
    - shard-lnl:          NOTRUN -> [SKIP][100] ([Intel XE#8369]) +1 other test skip
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-3/igt@xe_exec_reset@multi-queue-close-execqueues.html

  * igt@xe_exec_reset@multi-queue-long-spin-reuse-many-queue-switch:
    - shard-bmg:          NOTRUN -> [SKIP][101] ([Intel XE#8369])
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-bmg-2/igt@xe_exec_reset@multi-queue-long-spin-reuse-many-queue-switch.html

  * igt@xe_exec_threads@threads-multi-queue-cm-fd-userptr:
    - shard-bmg:          NOTRUN -> [SKIP][102] ([Intel XE#8378]) +2 other tests skip
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-bmg-2/igt@xe_exec_threads@threads-multi-queue-cm-fd-userptr.html

  * igt@xe_exec_threads@threads-multi-queue-cm-rebind:
    - shard-lnl:          NOTRUN -> [SKIP][103] ([Intel XE#8378]) +9 other tests skip
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-7/igt@xe_exec_threads@threads-multi-queue-cm-rebind.html

  * igt@xe_fault_injection@inject-fault-probe-function-xe_pcode_probe_early:
    - shard-bmg:          [PASS][104] -> [ABORT][105] ([Intel XE#8007])
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5665-43b9a5e9d30783bb6f4d7dacdd1739184666940f/shard-bmg-5/igt@xe_fault_injection@inject-fault-probe-function-xe_pcode_probe_early.html
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-bmg-1/igt@xe_fault_injection@inject-fault-probe-function-xe_pcode_probe_early.html

  * igt@xe_live_ktest@xe_migrate@xe_validate_ccs_kunit:
    - shard-lnl:          NOTRUN -> [SKIP][106] ([Intel XE#2229])
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-1/igt@xe_live_ktest@xe_migrate@xe_validate_ccs_kunit.html

  * igt@xe_madvise@atomic-device:
    - shard-lnl:          NOTRUN -> [SKIP][107] ([Intel XE#7980])
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-7/igt@xe_madvise@atomic-device.html

  * igt@xe_multigpu_svm@mgpu-coherency-prefetch:
    - shard-lnl:          NOTRUN -> [SKIP][108] ([Intel XE#6964]) +3 other tests skip
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-3/igt@xe_multigpu_svm@mgpu-coherency-prefetch.html

  * igt@xe_page_reclaim@binds-null-vma:
    - shard-lnl:          NOTRUN -> [SKIP][109] ([Intel XE#7793]) +1 other test skip
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-7/igt@xe_page_reclaim@binds-null-vma.html

  * igt@xe_page_reclaim@boundary-split:
    - shard-bmg:          NOTRUN -> [SKIP][110] ([Intel XE#7793])
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-bmg-2/igt@xe_page_reclaim@boundary-split.html

  * igt@xe_pat@pat-sw-hw-reset-compare:
    - shard-lnl:          NOTRUN -> [FAIL][111] ([Intel XE#7695]) +2 other tests fail
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-7/igt@xe_pat@pat-sw-hw-reset-compare.html

  * igt@xe_pat@xa-app-transient-media-off:
    - shard-lnl:          NOTRUN -> [SKIP][112] ([Intel XE#7590] / [Intel XE#7772])
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-1/igt@xe_pat@xa-app-transient-media-off.html

  * igt@xe_pm@d3cold-multiple-execs:
    - shard-lnl:          NOTRUN -> [SKIP][113] ([Intel XE#2284] / [Intel XE#366] / [Intel XE#7370])
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-3/igt@xe_pm@d3cold-multiple-execs.html

  * igt@xe_pm@s3-vm-bind-userptr:
    - shard-lnl:          NOTRUN -> [SKIP][114] ([Intel XE#584] / [Intel XE#7369]) +1 other test skip
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-1/igt@xe_pm@s3-vm-bind-userptr.html

  * igt@xe_pm@vram-d3cold-threshold:
    - shard-lnl:          NOTRUN -> [SKIP][115] ([Intel XE#579] / [Intel XE#7329] / [Intel XE#7456])
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-5/igt@xe_pm@vram-d3cold-threshold.html

  * igt@xe_pm_residency@aspm_link_residency:
    - shard-lnl:          NOTRUN -> [SKIP][116] ([Intel XE#7271])
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-7/igt@xe_pm_residency@aspm_link_residency.html

  * igt@xe_pmu@fn-engine-activity-sched-if-idle:
    - shard-lnl:          NOTRUN -> [SKIP][117] ([Intel XE#4650] / [Intel XE#7347])
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-1/igt@xe_pmu@fn-engine-activity-sched-if-idle.html

  * igt@xe_query@multigpu-query-invalid-cs-cycles:
    - shard-lnl:          NOTRUN -> [SKIP][118] ([Intel XE#944]) +3 other tests skip
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-1/igt@xe_query@multigpu-query-invalid-cs-cycles.html

  * igt@xe_sriov_auto_provisioning@selfconfig-basic:
    - shard-lnl:          NOTRUN -> [SKIP][119] ([Intel XE#4130] / [Intel XE#7366]) +1 other test skip
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-3/igt@xe_sriov_auto_provisioning@selfconfig-basic.html

  * igt@xe_sriov_scheduling@default-enabled-fair-scheduling:
    - shard-lnl:          NOTRUN -> [SKIP][120] ([Intel XE#8339])
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-7/igt@xe_sriov_scheduling@default-enabled-fair-scheduling.html

  * igt@xe_sriov_vfio@region-info:
    - shard-lnl:          NOTRUN -> [SKIP][121] ([Intel XE#7724])
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-7/igt@xe_sriov_vfio@region-info.html

  * igt@xe_vm@overcommit-nonfault-vram-lr-external-nodefer:
    - shard-lnl:          NOTRUN -> [SKIP][122] ([Intel XE#7892]) +1 other test skip
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-1/igt@xe_vm@overcommit-nonfault-vram-lr-external-nodefer.html

  * igt@xe_wedged@wedged-at-any-timeout:
    - shard-bmg:          NOTRUN -> [DMESG-WARN][123] ([Intel XE#8963])
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-bmg-2/igt@xe_wedged@wedged-at-any-timeout.html

  
#### Possible fixes ####

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
    - shard-bmg:          [FAIL][124] ([Intel XE#8098]) -> [PASS][125] +1 other test pass
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5665-43b9a5e9d30783bb6f4d7dacdd1739184666940f/shard-bmg-10/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-bmg-7/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-lnl:          [FAIL][126] ([Intel XE#301]) -> [PASS][127] +1 other test pass
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5665-43b9a5e9d30783bb6f4d7dacdd1739184666940f/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-7/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible:
    - shard-lnl:          [FAIL][128] ([Intel XE#3098] / [Intel XE#3149]) -> [PASS][129] +1 other test pass
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5665-43b9a5e9d30783bb6f4d7dacdd1739184666940f/shard-lnl-6/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-lnl-8/igt@kms_flip@plain-flip-fb-recreate-interruptible.html

  * igt@xe_evict@evict-mixed-many-threads-small:
    - shard-bmg:          [INCOMPLETE][130] ([Intel XE#6321] / [Intel XE#8355]) -> [PASS][131]
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5665-43b9a5e9d30783bb6f4d7dacdd1739184666940f/shard-bmg-8/igt@xe_evict@evict-mixed-many-threads-small.html
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-bmg-9/igt@xe_evict@evict-mixed-many-threads-small.html

  * igt@xe_exec_threads@threads-hang-userptr-invalidate-race:
    - shard-bmg:          [FAIL][132] -> [PASS][133]
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5665-43b9a5e9d30783bb6f4d7dacdd1739184666940f/shard-bmg-2/igt@xe_exec_threads@threads-hang-userptr-invalidate-race.html
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-bmg-4/igt@xe_exec_threads@threads-hang-userptr-invalidate-race.html

  * igt@xe_fault_injection@inject-fault-probe-function-xe_wa_gt_init:
    - shard-bmg:          [ABORT][134] ([Intel XE#8007]) -> [PASS][135]
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5665-43b9a5e9d30783bb6f4d7dacdd1739184666940f/shard-bmg-10/igt@xe_fault_injection@inject-fault-probe-function-xe_wa_gt_init.html
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-bmg-2/igt@xe_fault_injection@inject-fault-probe-function-xe_wa_gt_init.html

  
#### Warnings ####

  * igt@kms_hdr@brightness-with-hdr:
    - shard-bmg:          [SKIP][136] ([Intel XE#3544]) -> [SKIP][137] ([Intel XE#3374] / [Intel XE#3544])
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5665-43b9a5e9d30783bb6f4d7dacdd1739184666940f/shard-bmg-3/igt@kms_hdr@brightness-with-hdr.html
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-bmg-6/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-bmg:          [SKIP][138] ([Intel XE#2426] / [Intel XE#5848]) -> [SKIP][139] ([Intel XE#2509] / [Intel XE#7437])
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5665-43b9a5e9d30783bb6f4d7dacdd1739184666940f/shard-bmg-2/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/shard-bmg-4/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1125]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1125
  [Intel XE#1128]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1128
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1397
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
  [Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
  [Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
  [Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
  [Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
  [Intel XE#1467]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1467
  [Intel XE#1468]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1468
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
  [Intel XE#2229]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2229
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
  [Intel XE#2330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2330
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2504]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2504
  [Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
  [Intel XE#2669]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2669
  [Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/307
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#3098]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3098
  [Intel XE#3141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3141
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
  [Intel XE#3433]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3433
  [Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
  [Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#4130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4130
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4302]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4302
  [Intel XE#4354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4354
  [Intel XE#4416]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4416
  [Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
  [Intel XE#4608]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4608
  [Intel XE#4609]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4609
  [Intel XE#4650]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4650
  [Intel XE#5191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5191
  [Intel XE#5408]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5408
  [Intel XE#579]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/579
  [Intel XE#5813]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5813
  [Intel XE#584]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/584
  [Intel XE#5848]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5848
  [Intel XE#5854]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5854
  [Intel XE#5882]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5882
  [Intel XE#599]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/599
  [Intel XE#6266]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6266
  [Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
  [Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#6540]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6540
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#6813]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6813
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#6886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6886
  [Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
  [Intel XE#6974]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6974
  [Intel XE#702]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/702
  [Intel XE#7059]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7059
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7084]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7084
  [Intel XE#7085]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7085
  [Intel XE#7086]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7086
  [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
  [Intel XE#7179]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7179
  [Intel XE#7271]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7271
  [Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
  [Intel XE#7304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7304
  [Intel XE#7312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7312
  [Intel XE#7316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7316
  [Intel XE#7319]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7319
  [Intel XE#7329]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7329
  [Intel XE#7342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7342
  [Intel XE#7343]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7343
  [Intel XE#7344]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7344
  [Intel XE#7345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7345
  [Intel XE#7346]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7346
  [Intel XE#7347]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7347
  [Intel XE#7350]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7350
  [Intel XE#7351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7351
  [Intel XE#7355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7355
  [Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
  [Intel XE#7358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7358
  [Intel XE#7366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7366
  [Intel XE#7367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7367
  [Intel XE#7369]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7369
  [Intel XE#7370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7370
  [Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
  [Intel XE#7376]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7376
  [Intel XE#7381]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7381
  [Intel XE#7382]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7382
  [Intel XE#7383]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7383
  [Intel XE#7385]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7385
  [Intel XE#7389]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7389
  [Intel XE#7390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7390
  [Intel XE#7396]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7396
  [Intel XE#7399]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7399
  [Intel XE#7413]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7413
  [Intel XE#7437]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7437
  [Intel XE#7456]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7456
  [Intel XE#7482]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7482
  [Intel XE#7590]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7590
  [Intel XE#7642]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7642
  [Intel XE#7644]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7644
  [Intel XE#7679]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7679
  [Intel XE#7695]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7695
  [Intel XE#7724]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7724
  [Intel XE#7760]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7760
  [Intel XE#7772]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7772
  [Intel XE#7793]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7793
  [Intel XE#7865]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7865
  [Intel XE#7892]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7892
  [Intel XE#7905]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7905
  [Intel XE#7980]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7980
  [Intel XE#8007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8007
  [Intel XE#8098]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8098
  [Intel XE#8150]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8150
  [Intel XE#8265]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8265
  [Intel XE#8303]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8303
  [Intel XE#8339]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8339
  [Intel XE#8348]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8348
  [Intel XE#8355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8355
  [Intel XE#8364]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8364
  [Intel XE#8365]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8365
  [Intel XE#8369]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8369
  [Intel XE#8374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8374
  [Intel XE#8378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8378
  [Intel XE#8428]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8428
  [Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
  [Intel XE#8963]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8963
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * Linux: xe-5665-43b9a5e9d30783bb6f4d7dacdd1739184666940f -> xe-pw-162015v5

  IGT_9078: 9078
  xe-5665-43b9a5e9d30783bb6f4d7dacdd1739184666940f: 43b9a5e9d30783bb6f4d7dacdd1739184666940f
  xe-pw-162015v5: 162015v5

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162015v5/index.html

[-- Attachment #2: Type: text/html, Size: 55155 bytes --]

^ permalink raw reply	[flat|nested] 18+ messages in thread

end of thread, other threads:[~2026-09-03  6:41 UTC | newest]

Thread overview: 18+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-08-31 21:34 [v4 0/4] drm/i915/display: Enable AS SDP Skip Frames Uma Shankar
2026-08-31 21:20 ` ✗ CI.checkpatch: warning for drm/i915/display: Enable AS SDP Skip Frames (rev5) Patchwork
2026-08-31 21:22 ` ✓ CI.KUnit: success " Patchwork
2026-08-31 21:34 ` [v4 1/4] drm/i915/display: Enable periodic AS SDP skip frames Uma Shankar
2026-09-02 16:15   ` Dibin Moolakadan Subrahmanian
2026-08-31 21:34 ` [v4 2/4] drm/i915/display: Force disable DC3co when AS SDP skip frames is enabled Uma Shankar
2026-09-02 16:29   ` Dibin Moolakadan Subrahmanian
2026-09-03  6:18   ` Naladala, Ramanaidu
2026-08-31 21:34 ` [v4 3/4] drm/i915/display: Reprogram AS SDP skip frames on seamless VRR transitions Uma Shankar
2026-09-02 16:44   ` Dibin Moolakadan Subrahmanian
2026-09-03  6:21   ` Naladala, Ramanaidu
2026-09-03  6:36   ` Naladala, Ramanaidu
2026-08-31 21:34 ` [v4 4/4] drm/i915/display: Gate periodic AS SDP skip frames behind a module parameter Uma Shankar
2026-08-31 22:28   ` sashiko-bot
2026-09-02 18:00   ` Dibin Moolakadan Subrahmanian
2026-09-03  6:37   ` Naladala, Ramanaidu
2026-08-31 22:00 ` ✓ Xe.CI.BAT: success for drm/i915/display: Enable AS SDP Skip Frames (rev5) Patchwork
2026-08-31 23:07 ` ✗ Xe.CI.FULL: failure " Patchwork

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox