From: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
Subject: [CI 6/9] drm/i915/color: Extract HDR post-CSC LUT programming to helper function
Date: Wed, 2 Sep 2026 13:24:14 +0530 [thread overview]
Message-ID: <20260902075417.656673-7-chaitanya.kumar.borah@intel.com> (raw)
In-Reply-To: <20260902075417.656673-1-chaitanya.kumar.borah@intel.com>
From: Pranay Samala <pranay.samala@intel.com>
Move HDR plane post-CSC LUT programming to improve code organization.
While at it, remove the segment 0 index register writes as it is not
currently programmed.
Signed-off-by: Pranay Samala <pranay.samala@intel.com>
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 35 ++++++++++++----------
1 file changed, 20 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 87ced9f6ff40..36c8688ed28e 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -3998,25 +3998,17 @@ xelpd_program_plane_pre_csc_lut(struct intel_dsb *dsb,
}
static void
-xelpd_program_plane_post_csc_lut(struct intel_dsb *dsb,
- const struct intel_plane_state *plane_state)
+xelpd_load_hdr_post_csc_lut(struct intel_display *display,
+ struct intel_dsb *dsb,
+ enum pipe pipe,
+ enum plane_id plane,
+ const struct drm_color_lut32 *post_csc_lut)
{
- struct intel_display *display = to_intel_display(plane_state);
- const struct drm_plane_state *state = &plane_state->uapi;
- enum pipe pipe = to_intel_plane(state->plane)->pipe;
- enum plane_id plane = to_intel_plane(state->plane)->id;
- const struct drm_color_lut32 *post_csc_lut = plane_state->hw.gamma_lut->data;
int i, lut_size = 32;
u32 lut_val;
- if (!icl_is_hdr_plane(display, plane))
- return;
-
intel_de_write_dsb(display, dsb, PLANE_POST_CSC_GAMC_INDEX_ENH(pipe, plane, 0),
PLANE_PAL_PREC_AUTO_INCREMENT);
- /* TODO: Add macro */
- intel_de_write_dsb(display, dsb, PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH(pipe, plane, 0),
- PLANE_PAL_PREC_AUTO_INCREMENT);
for (i = 0; i < lut_size + 3; i++) {
if (post_csc_lut) {
@@ -4036,8 +4028,21 @@ xelpd_program_plane_post_csc_lut(struct intel_dsb *dsb,
}
intel_de_write_dsb(display, dsb, PLANE_POST_CSC_GAMC_INDEX_ENH(pipe, plane, 0), 0);
- intel_de_write_dsb(display, dsb,
- PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH(pipe, plane, 0), 0);
+}
+
+static void
+xelpd_program_plane_post_csc_lut(struct intel_dsb *dsb,
+ const struct intel_plane_state *plane_state)
+{
+ struct intel_display *display = to_intel_display(plane_state);
+ const struct drm_plane_state *state = &plane_state->uapi;
+ enum pipe pipe = to_intel_plane(state->plane)->pipe;
+ enum plane_id plane = to_intel_plane(state->plane)->id;
+ const struct drm_color_lut32 *post_csc_lut = plane_state->hw.gamma_lut ?
+ plane_state->hw.gamma_lut->data : NULL;
+
+ if (icl_is_hdr_plane(display, plane))
+ xelpd_load_hdr_post_csc_lut(display, dsb, pipe, plane, post_csc_lut);
}
static void
--
2.50.1
next prev parent reply other threads:[~2026-09-02 8:18 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-02 7:54 [CI 0/9] drm/i915/color: Add YUV Support in color pipeline Chaitanya Kumar Borah
2026-09-02 7:54 ` [CI 1/9] drm/i915/color: Add CSC on SDR plane " Chaitanya Kumar Borah
2026-09-02 8:34 ` sashiko-bot
2026-09-02 7:54 ` [CI 2/9] drm/i915/display: extract glk_plane_color_ctl_input_csc helper Chaitanya Kumar Borah
2026-09-02 7:54 ` [CI 3/9] drm/i915/display: simplify glk_plane_color_ctl_input_csc Chaitanya Kumar Borah
2026-09-02 7:54 ` [CI 4/9] drm/i915/display: Program CSC on SDR planes based on Fixed Matrix Colorop Chaitanya Kumar Borah
2026-09-02 7:54 ` [CI 5/9] drm/i915/color: Add support for 1D LUT in SDR planes Chaitanya Kumar Borah
2026-09-02 7:54 ` Chaitanya Kumar Borah [this message]
2026-09-02 7:54 ` [CI 7/9] drm/i915/color: Program Plane Post CSC registers for " Chaitanya Kumar Borah
2026-09-02 7:54 ` [CI 8/9] drm/i915/color: Add color pipeline support " Chaitanya Kumar Borah
2026-09-02 8:34 ` sashiko-bot
2026-09-02 7:54 ` [CI 9/9] drm/i915/color: Add YUV buffer support on HDR planes Chaitanya Kumar Borah
2026-09-02 8:28 ` sashiko-bot
2026-09-02 9:52 ` ✓ CI.KUnit: success for drm/i915/color: Add YUV Support in color pipeline Patchwork
2026-09-02 10:55 ` ✓ Xe.CI.BAT: " Patchwork
2026-09-02 20:47 ` ✗ Xe.CI.FULL: failure " Patchwork
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