From: "Michael J. Ruhl" <michael.j.ruhl@intel.com>
To: platform-driver-x86@vger.kernel.org,
intel-xe@lists.freedesktop.org, hansg@kernel.org,
ilpo.jarvinen@linux.intel.com, matthew.brost@intel.com,
rodrigo.vivi@intel.com, thomas.hellstrom@linux.intel.com,
airlied@gmail.com, simona@ffwll.ch, david.e.box@linux.intel.com,
anoop.c.vijay@intel.com, badal.nilawar@intel.com,
matthew.d.roper@intel.com, james.ausmus@intel.com,
karthik.poosa@intel.com
Subject: [PATCH v5 17/18] drm/xe/vsec: Update PMT internal access
Date: Thu, 3 Sep 2026 13:10:19 -0700 [thread overview]
Message-ID: <20260903201002.1064889-37-michael.j.ruhl@intel.com> (raw)
In-Reply-To: <20260903201002.1064889-20-michael.j.ruhl@intel.com>
Current PMT internal access assumes BMG devices.
Use the new PMT GUID API to read the device specific guid.
Minor cleanup for a newly unused parameter (mmio).
Reviewed-by: Karthik Poosa <karthik.poosa@intel.com>
Signed-off-by: Michael J. Ruhl <michael.j.ruhl@intel.com>
---
drivers/gpu/drm/xe/xe_debugfs.c | 27 ++++++++++++++-------------
drivers/gpu/drm/xe/xe_hwmon.c | 10 ++++++++--
drivers/gpu/drm/xe/xe_pcode.c | 10 ++++++++--
3 files changed, 30 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_debugfs.c b/drivers/gpu/drm/xe/xe_debugfs.c
index b01f1e649b51..f17b993755f3 100644
--- a/drivers/gpu/drm/xe/xe_debugfs.c
+++ b/drivers/gpu/drm/xe/xe_debugfs.c
@@ -5,6 +5,7 @@
#include "xe_debugfs.h"
+#include <linux/array_size.h>
#include <linux/bits.h>
#include <linux/debugfs.h>
#include <linux/fault-inject.h>
@@ -21,7 +22,6 @@
#include "xe_gt_printk.h"
#include "xe_guc_ads.h"
#include "xe_hw_engine.h"
-#include "xe_mmio.h"
#include "xe_pagefault.h"
#include "xe_pcode.h"
#include "xe_pm.h"
@@ -97,16 +97,20 @@ static void xe_fault_inject_debugfs_register(struct xe_device *xe,
}
}
-static void read_residency_counter(struct xe_device *xe, struct xe_mmio *mmio,
- u32 offset, const char *name, struct drm_printer *p)
+static void read_residency_counter(struct xe_device *xe, u32 offset, const char *name,
+ struct drm_printer *p)
{
u64 residency = 0;
-
+ u32 guid;
int ret;
- ret = xe_pmt_telem_read(xe->drm.dev,
- xe_mmio_read32(mmio, BMG_PUNIT_TELEMETRY_GUID),
- &residency, offset, sizeof(residency));
+ ret = xe_vsec_get_guid(xe, &guid);
+ if (ret) {
+ drm_warn(&xe->drm, "PMT device is not available: %d\n", ret);
+ return;
+ }
+
+ ret = xe_pmt_telem_read(xe->drm.dev, guid, &residency, offset, sizeof(residency));
if (ret != sizeof(residency)) {
drm_warn(&xe->drm, "%s counter failed to read, ret %d\n", name, ret);
return;
@@ -245,13 +249,12 @@ static int pcode_info(struct seq_file *m, void *data)
static int dgfx_pkg_residencies_show(struct seq_file *m, void *data)
{
struct xe_device *xe;
- struct xe_mmio *mmio;
struct drm_printer p;
xe = node_to_xe(m->private);
p = drm_seq_file_printer(m);
guard(xe_pm_runtime)(xe);
- mmio = xe_root_tile_mmio(xe);
+
static const struct {
u32 offset;
const char *name;
@@ -265,7 +268,7 @@ static int dgfx_pkg_residencies_show(struct seq_file *m, void *data)
};
for (int i = 0; i < ARRAY_SIZE(residencies); i++)
- read_residency_counter(xe, mmio, residencies[i].offset, residencies[i].name, &p);
+ read_residency_counter(xe, residencies[i].offset, residencies[i].name, &p);
return 0;
}
@@ -273,13 +276,11 @@ static int dgfx_pkg_residencies_show(struct seq_file *m, void *data)
static int dgfx_pcie_link_residencies_show(struct seq_file *m, void *data)
{
struct xe_device *xe;
- struct xe_mmio *mmio;
struct drm_printer p;
xe = node_to_xe(m->private);
p = drm_seq_file_printer(m);
guard(xe_pm_runtime)(xe);
- mmio = xe_root_tile_mmio(xe);
static const struct {
u32 offset;
@@ -291,7 +292,7 @@ static int dgfx_pcie_link_residencies_show(struct seq_file *m, void *data)
};
for (int i = 0; i < ARRAY_SIZE(residencies); i++)
- read_residency_counter(xe, mmio, residencies[i].offset, residencies[i].name, &p);
+ read_residency_counter(xe, residencies[i].offset, residencies[i].name, &p);
return 0;
}
diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index b9740224e07f..c44a7d24816d 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -517,9 +517,15 @@ xe_hwmon_energy_get(struct xe_hwmon *hwmon, int channel, long *energy)
if (hwmon->xe->info.platform == XE_BATTLEMAGE) {
u64 pmt_val;
+ u32 guid;
- ret = xe_pmt_telem_read(hwmon->xe->drm.dev,
- xe_mmio_read32(mmio, BMG_PUNIT_TELEMETRY_GUID),
+ ret = xe_vsec_get_guid(hwmon->xe, &guid);
+ if (ret) {
+ drm_warn(&hwmon->xe->drm, "PMT device is not available: %d\n", ret);
+ *energy = 0;
+ return;
+ }
+ ret = xe_pmt_telem_read(hwmon->xe->drm.dev, guid,
&pmt_val, BMG_ENERGY_STATUS_PMT_OFFSET, sizeof(pmt_val));
if (ret != sizeof(pmt_val)) {
drm_warn(&hwmon->xe->drm, "energy read from pmt failed, ret %d\n", ret);
diff --git a/drivers/gpu/drm/xe/xe_pcode.c b/drivers/gpu/drm/xe/xe_pcode.c
index 844d8c6face6..e534d64834e3 100644
--- a/drivers/gpu/drm/xe/xe_pcode.c
+++ b/drivers/gpu/drm/xe/xe_pcode.c
@@ -365,11 +365,17 @@ ALLOW_ERROR_INJECTION(xe_pcode_probe_early, ERRNO); /* See xe_pci_probe */
int xe_get_pcode_version(struct xe_device *xe, struct xe_pcode_version *version)
{
int ret = 0;
+ u32 guid;
guard(xe_pm_runtime)(xe);
- ret = xe_pmt_telem_read(xe->drm.dev,
- xe_mmio_read32(xe_root_tile_mmio(xe), BMG_PUNIT_TELEMETRY_GUID),
+ ret = xe_vsec_get_guid(xe, &guid);
+ if (ret) {
+ xe_warn(xe, "PMT device is not available: %d\n", ret);
+ return ret;
+ }
+
+ ret = xe_pmt_telem_read(xe->drm.dev, guid,
(u64 *)version, PUNIT_VERSION_OFFSET, sizeof(*version));
if (ret != sizeof(*version)) {
xe_warn(xe, "pcode version read from PMT failed, ret %pe\n", ERR_PTR(ret));
--
2.43.0
next prev parent reply other threads:[~2026-09-03 20:10 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-03 20:10 [PATCH v5 00/18] Crescent Island PMT support Michael J. Ruhl
2026-09-03 20:10 ` [PATCH v5 01/18] platform/x86/intel/pmt: complete pcidev to device update Michael J. Ruhl
2026-09-03 20:27 ` sashiko-bot
2026-09-03 20:10 ` [PATCH v5 02/18] platform/x86/intel/pmt: refactor rmw with a return value Michael J. Ruhl
2026-09-03 20:10 ` [PATCH v5 03/18] platform/x86/intel/pmt: refactor rc " Michael J. Ruhl
2026-09-03 20:19 ` sashiko-bot
2026-09-03 20:33 ` Ruhl, Michael J
2026-09-03 20:10 ` [PATCH v5 04/18] platform/x86/intel/pmt: Add register access callbacks Michael J. Ruhl
2026-09-03 20:10 ` [PATCH v5 05/18] platform/x86/intel/pmt: Do not remap when using callbacks Michael J. Ruhl
2026-09-03 20:24 ` sashiko-bot
2026-09-03 20:54 ` Ruhl, Michael J
2026-09-03 20:10 ` [PATCH v5 06/18] drm/xe/vsec: Do not register BMG PMT for VF Michael J. Ruhl
2026-09-03 20:33 ` sashiko-bot
2026-09-03 20:10 ` [PATCH v5 07/18] drm/xe/vsec: Correct locking order Michael J. Ruhl
2026-09-03 20:10 ` [PATCH v5 08/18] drm/xe/vsec: Use correct pm state get Michael J. Ruhl
2026-09-03 20:26 ` sashiko-bot
2026-09-03 20:55 ` Ruhl, Michael J
2026-09-03 20:10 ` [PATCH v5 09/18] drm/xe/vsec: Add DOC text for VSEC Michael J. Ruhl
2026-09-03 20:17 ` sashiko-bot
2026-09-03 20:34 ` Ruhl, Michael J
2026-09-03 20:10 ` [PATCH v5 10/18] drm/xe/vsec: Support possible hotplug exit Michael J. Ruhl
2026-09-03 20:10 ` [PATCH v5 11/18] drm/xe/vsec: Support Crescent Island PMT Michael J. Ruhl
2026-09-03 20:10 ` [PATCH v5 12/18] drm/xe/vsec: Refactor BattleMage PMT defines Michael J. Ruhl
2026-09-03 20:10 ` [PATCH v5 13/18] drm/xe/vsec: Crescent Island PMT decode Michael J. Ruhl
2026-09-03 20:10 ` [PATCH v5 14/18] drm/xe/vsec: Crescent Island PMT callbacks Michael J. Ruhl
2026-09-03 20:26 ` sashiko-bot
2026-09-03 20:10 ` [PATCH v5 15/18] drm/xe/vsec: Support late bind fw information Michael J. Ruhl
2026-09-03 20:28 ` sashiko-bot
2026-09-03 20:57 ` Ruhl, Michael J
2026-09-03 20:10 ` [PATCH v5 16/18] drm/xe/vsec: Add PMT GUID internal access Michael J. Ruhl
2026-09-04 15:14 ` Poosa, Karthik
2026-09-04 16:00 ` Ruhl, Michael J
2026-09-03 20:10 ` Michael J. Ruhl [this message]
2026-09-03 20:10 ` [PATCH v5 18/18] drm/xe/vsec: Refactor platform check Michael J. Ruhl
2026-09-03 20:17 ` ✗ CI.checkpatch: warning for Crescent Island PMT support (rev7) Patchwork
2026-09-03 20:18 ` ✗ CI.KUnit: failure " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260903201002.1064889-37-michael.j.ruhl@intel.com \
--to=michael.j.ruhl@intel.com \
--cc=airlied@gmail.com \
--cc=anoop.c.vijay@intel.com \
--cc=badal.nilawar@intel.com \
--cc=david.e.box@linux.intel.com \
--cc=hansg@kernel.org \
--cc=ilpo.jarvinen@linux.intel.com \
--cc=intel-xe@lists.freedesktop.org \
--cc=james.ausmus@intel.com \
--cc=karthik.poosa@intel.com \
--cc=matthew.brost@intel.com \
--cc=matthew.d.roper@intel.com \
--cc=platform-driver-x86@vger.kernel.org \
--cc=rodrigo.vivi@intel.com \
--cc=simona@ffwll.ch \
--cc=thomas.hellstrom@linux.intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).