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From: sashiko-bot@kernel.org
To: "Michael J. Ruhl" <michael.j.ruhl@intel.com>
Cc: intel-xe@lists.freedesktop.org
Subject: Re: [PATCH v5 08/18] drm/xe/vsec: Use correct pm state get
Date: Thu, 03 Sep 2026 20:26:36 +0000	[thread overview]
Message-ID: <20260903202636.B1C511F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260903201002.1064889-28-michael.j.ruhl@intel.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] Missing `.read_reg` and `.write_reg` callbacks in `xe_pmt_cb` leaves PMT crashlog control registers unprotected against accesses while the GPU is in D3cold.
--

commit a8bb406382664649dde97aed435f17b6cfd1536b
Author: Michael J. Ruhl <michael.j.ruhl@intel.com>

drm/xe/vsec: Use correct pm state get

This commit updates the PM runtime checks in the telemetry read path to ensure
the device is properly awakened when reading crashlog data, as crashlog needs
to be collected at all times. It also adds a check for the WATCHER capability
type for completeness.

> diff --git a/drivers/gpu/drm/xe/xe_vsec.c b/drivers/gpu/drm/xe/xe_vsec.c
> index dd7723ba6c1c2..468a221378faf 100644
> --- a/drivers/gpu/drm/xe/xe_vsec.c
> +++ b/drivers/gpu/drm/xe/xe_vsec.c
> @@ -158,9 +159,18 @@ int xe_pmt_telem_read(struct device *dev, u32 guid, u64 *data, loff_t user_offse
>  
>  	telem_addr += offset + user_offset;
>  
> -	/* indicate that we are not at an appropriate power level */
> -	if (!xe_pm_runtime_get_if_active(xe))
> -		return -ENODATA;
> +	/* Always allow crashlog. Telemetry, only when powered */
> +	switch (cap_type) {
> +	case CRASHLOG:
> +		xe_pm_runtime_get(xe);
> +		break;
> +	case TELEMETRY:
> +		if (!xe_pm_runtime_get_if_active(xe))
> +			return -ENODATA;
> +		break;
> +	case WATCHER:
> +		return -EINVAL;
> +	}

[Severity: High]
This is a pre-existing issue, but since this patch is addressing PM runtime
protection for the crashlog data path, it seems the control registers are still
left entirely unprotected.

While xe_pmt_telem_read() now handles PM state correctly for data reads,
xe_pmt_cb lacks .read_reg and .write_reg callbacks:

drivers/gpu/drm/xe/xe_vsec.c:
static struct pmt_callbacks xe_pmt_cb = {
	.read_telem = xe_pmt_telem_read,
};

When userspace accesses PMT crashlog control attributes (like enable, clear, or
trigger) via sysfs while the GPU is in D3cold, pmt_crashlog_read_reg() and
pmt_crashlog_rmw() fall back to direct MMIO access:

drivers/platform/x86/intel/pmt/crashlog.c:pmt_crashlog_read_reg() {
	...
	if (entry->pdata->cb && entry->pdata->cb->read_reg)
		return entry->pdata->cb->read_reg(entry->pdata->cb_data, offset, reg);
	*reg = readl(entry->disc_table + offset);
	...
}

Because the callbacks are NULL, the fallback access hits powered-down PCIe MMIO
space. Does this cause PCIe unsupported requests (UR) and lead to Advanced Error
Reporting (AER) panics, system freezes, or returning invalid data to userspace?

Could .read_reg and .write_reg callbacks be added to xe_pmt_cb to protect the
control registers during D3cold?

>  
>  	mutex_lock(&xe->pmt.lock);
>

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260903201002.1064889-20-michael.j.ruhl@intel.com?part=8

  reply	other threads:[~2026-09-03 20:26 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-03 20:10 [PATCH v5 00/18] Crescent Island PMT support Michael J. Ruhl
2026-09-03 20:10 ` [PATCH v5 01/18] platform/x86/intel/pmt: complete pcidev to device update Michael J. Ruhl
2026-09-03 20:27   ` sashiko-bot
2026-09-03 20:10 ` [PATCH v5 02/18] platform/x86/intel/pmt: refactor rmw with a return value Michael J. Ruhl
2026-09-03 20:10 ` [PATCH v5 03/18] platform/x86/intel/pmt: refactor rc " Michael J. Ruhl
2026-09-03 20:19   ` sashiko-bot
2026-09-03 20:33     ` Ruhl, Michael J
2026-09-03 20:10 ` [PATCH v5 04/18] platform/x86/intel/pmt: Add register access callbacks Michael J. Ruhl
2026-09-03 20:10 ` [PATCH v5 05/18] platform/x86/intel/pmt: Do not remap when using callbacks Michael J. Ruhl
2026-09-03 20:24   ` sashiko-bot
2026-09-03 20:54     ` Ruhl, Michael J
2026-09-03 20:10 ` [PATCH v5 06/18] drm/xe/vsec: Do not register BMG PMT for VF Michael J. Ruhl
2026-09-03 20:33   ` sashiko-bot
2026-09-03 20:10 ` [PATCH v5 07/18] drm/xe/vsec: Correct locking order Michael J. Ruhl
2026-09-03 20:10 ` [PATCH v5 08/18] drm/xe/vsec: Use correct pm state get Michael J. Ruhl
2026-09-03 20:26   ` sashiko-bot [this message]
2026-09-03 20:55     ` Ruhl, Michael J
2026-09-03 20:10 ` [PATCH v5 09/18] drm/xe/vsec: Add DOC text for VSEC Michael J. Ruhl
2026-09-03 20:17   ` sashiko-bot
2026-09-03 20:34     ` Ruhl, Michael J
2026-09-03 20:10 ` [PATCH v5 10/18] drm/xe/vsec: Support possible hotplug exit Michael J. Ruhl
2026-09-03 20:10 ` [PATCH v5 11/18] drm/xe/vsec: Support Crescent Island PMT Michael J. Ruhl
2026-09-03 20:10 ` [PATCH v5 12/18] drm/xe/vsec: Refactor BattleMage PMT defines Michael J. Ruhl
2026-09-03 20:10 ` [PATCH v5 13/18] drm/xe/vsec: Crescent Island PMT decode Michael J. Ruhl
2026-09-03 20:10 ` [PATCH v5 14/18] drm/xe/vsec: Crescent Island PMT callbacks Michael J. Ruhl
2026-09-03 20:26   ` sashiko-bot
2026-09-03 20:10 ` [PATCH v5 15/18] drm/xe/vsec: Support late bind fw information Michael J. Ruhl
2026-09-03 20:28   ` sashiko-bot
2026-09-03 20:57     ` Ruhl, Michael J
2026-09-03 20:10 ` [PATCH v5 16/18] drm/xe/vsec: Add PMT GUID internal access Michael J. Ruhl
2026-09-04 15:14   ` Poosa, Karthik
2026-09-04 16:00     ` Ruhl, Michael J
2026-09-03 20:10 ` [PATCH v5 17/18] drm/xe/vsec: Update PMT " Michael J. Ruhl
2026-09-03 20:10 ` [PATCH v5 18/18] drm/xe/vsec: Refactor platform check Michael J. Ruhl
2026-09-03 20:17 ` ✗ CI.checkpatch: warning for Crescent Island PMT support (rev7) Patchwork
2026-09-03 20:18 ` ✗ CI.KUnit: failure " Patchwork

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