From: Matthew Brost <matthew.brost@intel.com>
To: intel-xe@lists.freedesktop.org
Subject: [PATCH v5 17/25] drm/xe: Add device flag to enable PT mirroring across tiles
Date: Thu, 3 Sep 2026 19:21:59 -0700 [thread overview]
Message-ID: <20260904022207.3490018-18-matthew.brost@intel.com> (raw)
In-Reply-To: <20260904022207.3490018-1-matthew.brost@intel.com>
Some multi-tile devices may want to mirror page tables across tiles for
memory-bandwidth reasons, while others may not. Add a device flag that
allows enabling or disabling page-table mirroring across tiles.
Setting the flag to true (the existing behavior) on PVC, but both modes
have been tested and are working on PVC.
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Link: https://patch.msgid.link/20260228013501.106680-18-matthew.brost@intel.com
Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
---
drivers/gpu/drm/xe/xe_device_types.h | 2 ++
drivers/gpu/drm/xe/xe_migrate.c | 5 ++--
drivers/gpu/drm/xe/xe_pci.c | 2 ++
drivers/gpu/drm/xe/xe_pci_types.h | 3 ++-
drivers/gpu/drm/xe/xe_pt.c | 39 ++++++++++++++++++++++++++--
drivers/gpu/drm/xe/xe_vm.c | 37 +++++++++++++++++++++++---
drivers/gpu/drm/xe/xe_vm.h | 3 +++
7 files changed, 82 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index bc60833c39a7..997ac82fd571 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -224,6 +224,8 @@ struct xe_device {
u8 has_usm:1;
/** @info.has_64bit_timestamp: Device supports 64-bit timestamps */
u8 has_64bit_timestamp:1;
+ /** @info.has_pt_mirror: Device has PT mirroring across tiles */
+ u8 has_pt_mirror:1;
/** @info.is_dgfx: is discrete device */
u8 is_dgfx:1;
/** @info.needs_scratch: needs scratch page for oob prefetch to work */
diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
index f7e1a81434b2..471ae5741836 100644
--- a/drivers/gpu/drm/xe/xe_migrate.c
+++ b/drivers/gpu/drm/xe/xe_migrate.c
@@ -246,7 +246,8 @@ static void xe_migrate_prepare_vm(struct xe_tile *tile, struct xe_migrate *m,
struct xe_device *xe = tile_to_xe(tile);
u16 pat_index = xe_cache_pat_idx(xe, XE_CACHE_WB);
u8 id = tile->id;
- u32 num_entries = NUM_PT_SLOTS, num_level = vm->pt_root[id]->level;
+ u32 num_entries = NUM_PT_SLOTS, num_level =
+ xe_vm_pt_root(vm, id)->level;
#define VRAM_IDENTITY_MAP_PT_COUNT 4
u32 num_setup = num_level + VRAM_IDENTITY_MAP_PT_COUNT;
#undef VRAM_IDENTITY_MAP_PT_COUNT
@@ -258,7 +259,7 @@ static void xe_migrate_prepare_vm(struct xe_tile *tile, struct xe_migrate *m,
u64 l1_pt_ofs = xe_bo_size(bo) - 5 * XE_PAGE_SIZE;
entry = vm->pt_ops->pde_encode_bo(bo, l1_pt_ofs);
- xe_pt_write(xe, &vm->pt_root[id]->bo->vmap, 0, entry);
+ xe_pt_write(xe, &xe_vm_pt_root(vm, id)->bo->vmap, 0, entry);
map_ofs = (num_entries - num_setup) * XE_PAGE_SIZE;
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index ab4da1d9a9f1..d9030cb4f1ad 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -371,6 +371,7 @@ static const __maybe_unused struct xe_device_desc pvc_desc = {
.has_display = false,
.has_drm_ras = true,
.has_gsc_nvm = 1,
+ .has_pt_mirror = 1,
.has_heci_gscfi = 1,
.max_gt_per_tile = 1,
.max_remote_tiles = 1,
@@ -808,6 +809,7 @@ static int xe_info_init_early(struct xe_device *xe,
xe->info.has_mert = desc->has_mert;
xe->info.has_page_reclaim_hw_assist = desc->has_page_reclaim_hw_assist;
xe->info.has_pre_prod_wa = desc->has_pre_prod_wa;
+ xe->info.has_pt_mirror = desc->has_pt_mirror;
xe->info.has_pxp = desc->has_pxp;
xe->info.has_soc_remapper_sysctrl = desc->has_soc_remapper_sysctrl;
xe->info.has_soc_remapper_telem = desc->has_soc_remapper_telem;
diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
index fed509ff601e..71068cdb3558 100644
--- a/drivers/gpu/drm/xe/xe_pci_types.h
+++ b/drivers/gpu/drm/xe/xe_pci_types.h
@@ -52,8 +52,9 @@ struct xe_device_desc {
u8 has_mbx_power_limits:1;
u8 has_mbx_thermal_info:1;
u8 has_mert:1;
- u8 has_pre_prod_wa:1;
u8 has_page_reclaim_hw_assist:1;
+ u8 has_pre_prod_wa:1;
+ u8 has_pt_mirror:1;
u8 has_pxp:1;
u8 has_soc_remapper_sysctrl:1;
u8 has_soc_remapper_telem:1;
diff --git a/drivers/gpu/drm/xe/xe_pt.c b/drivers/gpu/drm/xe/xe_pt.c
index 05bbac6c2632..bf2cdef44179 100644
--- a/drivers/gpu/drm/xe/xe_pt.c
+++ b/drivers/gpu/drm/xe/xe_pt.c
@@ -812,7 +812,7 @@ xe_pt_stage_bind(struct xe_tile *tile, struct xe_vma *vma,
.wupd.entries = entries,
.clear_pt = clear_pt,
};
- struct xe_pt *pt = vm->pt_root[tile->id];
+ struct xe_pt *pt = xe_vm_pt_root(vm, tile->id);
int ret;
bool is_purged = false;
@@ -1005,6 +1005,11 @@ static int xe_pt_zap_ptes_entry(struct xe_ptw *parent, pgoff_t offset,
return 0;
}
+static bool pt_mirroring_disabled_for_tile(struct xe_vm *vm, u8 tile_id)
+{
+ return xe_vm_pt_root(vm, tile_id) != vm->pt_root[tile_id];
+}
+
static const struct xe_pt_walk_ops xe_pt_zap_ptes_ops = {
.pt_entry = xe_pt_zap_ptes_entry,
};
@@ -1046,6 +1051,9 @@ bool xe_pt_zap_ptes(struct xe_tile *tile, struct xe_vma *vma)
if (!(pt_mask & BIT(tile->id)))
return false;
+ if (pt_mirroring_disabled_for_tile(xe_vma_vm(vma), tile->id))
+ return true;
+
(void)xe_pt_walk_shared(&pt->base, pt->level, xe_vma_start(vma),
xe_vma_end(vma), &xe_walk.base);
@@ -1098,6 +1106,9 @@ bool xe_pt_zap_ptes_range(struct xe_tile *tile, struct xe_vm *vm,
if (!(pt_mask & BIT(tile->id)))
return false;
+ if (pt_mirroring_disabled_for_tile(vm, tile->id))
+ return true;
+
(void)xe_pt_walk_shared(&pt->base, pt->level, xe_svm_range_start(range),
xe_svm_range_end(range), &xe_walk.base);
@@ -1988,7 +1999,7 @@ static unsigned int xe_pt_stage_unbind(struct xe_tile *tile,
.wupd.entries = entries,
.prl = pt_update_op->prl,
};
- struct xe_pt *pt = vm->pt_root[tile->id];
+ struct xe_pt *pt = xe_vm_pt_root(vm, tile->id);
(void)xe_pt_walk_shared(&pt->base, pt->level, start, end,
&xe_walk.base);
@@ -2541,9 +2552,21 @@ int xe_pt_update_ops_prepare(struct xe_device *xe, struct xe_vma_ops *vops)
int id, err;
for_each_tile(tile, xe, id) {
+ struct xe_vm_pgtable_update_ops *pt_update_ops =
+ &vops->pt_update_ops[id];
+
if (!vops->pt_update_ops[id].num_ops)
continue;
+ if (pt_mirroring_disabled_for_tile(vops->vm, id)) {
+ struct xe_page_reclaim_list *prl = &pt_update_ops->prl;
+
+ /* Transfer root PT update ops PRL to current */
+ *prl = vops->pt_update_ops[0].prl;
+ xe_page_reclaim_entries_get(prl->entries);
+ continue;
+ }
+
err = __xe_pt_update_ops_prepare(tile, vops);
if (err)
return err;
@@ -2835,6 +2858,12 @@ xe_pt_update_ops_run(struct xe_device *xe, struct xe_vma_ops *vops)
struct xe_vm_pgtable_update_ops *pt_update_ops =
&vops->pt_update_ops[j];
+ if (pt_mirroring_disabled_for_tile(vm, j)) {
+ xe_tile_assert(tile, !get_current_op(pt_update_ops));
+ tile_mask |= BIT(tile->id);
+ continue;
+ }
+
for (i = 0; i < get_current_op(pt_update_ops); ++i) {
struct xe_vm_pgtable_update_op *pt_op =
to_pt_op(pt_update_ops, i);
@@ -2924,6 +2953,9 @@ void xe_pt_update_ops_fini(struct xe_device *xe, struct xe_vma_ops *vops)
if (!pt_update_ops->num_ops)
continue;
+ if (pt_mirroring_disabled_for_tile(vops->vm, id))
+ continue;
+
xe_page_reclaim_entries_put(pt_update_ops->prl.entries);
}
}
@@ -2948,6 +2980,9 @@ void xe_pt_update_ops_abort(struct xe_device *xe, struct xe_vma_ops *vops)
&vops->pt_update_ops[id];
int i;
+ if (pt_mirroring_disabled_for_tile(vops->vm, id))
+ continue;
+
for (i = pt_update_ops->num_ops - 1; i >= 0; --i) {
struct xe_vm_pgtable_update_op *pt_op =
to_pt_op(pt_update_ops, i);
diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
index fbfc42afef8b..795d0ebb1004 100644
--- a/drivers/gpu/drm/xe/xe_vm.c
+++ b/drivers/gpu/drm/xe/xe_vm.c
@@ -845,6 +845,14 @@ int xe_vm_rebind(struct xe_vm *vm, bool rebind_worker)
return err;
}
+static u8 adjust_rebind_tile_mask(struct xe_vm *vm, u8 tile_mask)
+{
+ if (vm->xe->info.has_pt_mirror)
+ return tile_mask;
+
+ return (0x1 << vm->xe->info.tile_count) - 1;
+}
+
struct dma_fence *xe_vma_rebind(struct xe_vm *vm, struct xe_vma *vma, u8 tile_mask)
{
struct dma_fence *fence = NULL;
@@ -861,7 +869,8 @@ struct dma_fence *xe_vma_rebind(struct xe_vm *vm, struct xe_vma *vma, u8 tile_ma
vops.flags |= XE_VMA_OPS_FLAG_SKIP_TLB_WAIT |
XE_VMA_OPS_FLAG_WAIT_VM_BOOKKEEP;
- err = xe_vm_ops_add_rebind(&vops, vma, tile_mask);
+ err = xe_vm_ops_add_rebind(&vops, vma,
+ adjust_rebind_tile_mask(vm, tile_mask));
if (err)
return ERR_PTR(err);
@@ -948,7 +957,8 @@ struct dma_fence *xe_vm_range_rebind(struct xe_vm *vm,
vops.flags |= XE_VMA_OPS_FLAG_SKIP_TLB_WAIT |
XE_VMA_OPS_FLAG_WAIT_VM_BOOKKEEP;
- err = xe_vm_ops_add_range_rebind(&vops, vma, range, tile_mask);
+ err = xe_vm_ops_add_range_rebind(&vops, vma, range,
+ adjust_rebind_tile_mask(vm, tile_mask));
if (err)
return ERR_PTR(err);
@@ -1738,7 +1748,8 @@ struct xe_vm *xe_vm_create(struct xe_device *xe, u32 flags, struct xe_file *xef)
for_each_tile(tile, xe, id) {
if (flags & XE_VM_FLAG_MIGRATION &&
- tile->id != XE_VM_FLAG_TILE_ID(flags))
+ tile->id != XE_VM_FLAG_TILE_ID(flags) &&
+ (vm->xe->info.has_pt_mirror || id))
continue;
vm->pt_root[id] = xe_pt_create(vm, tile, xe->info.vm_max_level,
@@ -2047,7 +2058,7 @@ struct xe_vm *xe_vm_lookup(struct xe_file *xef, u32 id)
u64 xe_vm_pdp4_descriptor(struct xe_vm *vm, struct xe_tile *tile)
{
- return vm->pt_ops->pde_encode_bo(vm->pt_root[tile->id]->bo, 0);
+ return vm->pt_ops->pde_encode_bo(xe_vm_pt_root(vm, tile->id)->bo, 0);
}
static struct xe_exec_queue *
@@ -5072,3 +5083,21 @@ void xe_vm_remove_exec_queue(struct xe_vm *vm, struct xe_exec_queue *q)
}
up_write(&vm->exec_queues.lock);
}
+
+/**
+ * xe_vm_pt_root() - Retrieve VM page-table root
+ * @vm: The VM.
+ * @tile_id: Tile ID
+ *
+ * Retrieve VM page-table root for a tile ID, used to abstract if PT mirroring is
+ * enabled across tiles.
+ *
+ * Return: VM page-table root for a tile ID
+ */
+struct xe_pt *xe_vm_pt_root(struct xe_vm *vm, u8 tile_id)
+{
+ if (vm->xe->info.has_pt_mirror)
+ return vm->pt_root[tile_id];
+
+ return vm->pt_root[0];
+}
diff --git a/drivers/gpu/drm/xe/xe_vm.h b/drivers/gpu/drm/xe/xe_vm.h
index c5b900f38ded..89c4f95984a2 100644
--- a/drivers/gpu/drm/xe/xe_vm.h
+++ b/drivers/gpu/drm/xe/xe_vm.h
@@ -436,4 +436,7 @@ static inline struct drm_exec *xe_vm_validation_exec(struct xe_vm *vm)
((READ_ONCE(tile_present) & ~READ_ONCE(tile_invalidated)) & BIT((tile)->id))
void xe_vma_mem_attr_copy(struct xe_vma_mem_attr *to, struct xe_vma_mem_attr *from);
+
+struct xe_pt *xe_vm_pt_root(struct xe_vm *vm, u8 tile_id);
+
#endif
--
2.34.1
next prev parent reply other threads:[~2026-09-04 2:22 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-04 2:21 [PATCH v5 00/25] CPU binds and ULLS on migration queue Matthew Brost
2026-09-04 2:21 ` [PATCH v5 01/25] drm/xe: Drop struct xe_migrate_pt_update argument from populate/clear vfuns Matthew Brost
2026-09-04 2:21 ` [PATCH v5 02/25] drm/xe: Add xe_migrate_update_pgtables_cpu_execute helper Matthew Brost
2026-09-04 2:37 ` sashiko-bot
2026-09-04 2:21 ` [PATCH v5 03/25] drm/xe: Decouple exec queue idle check from LRC Matthew Brost
2026-09-04 2:21 ` [PATCH v5 04/25] drm/xe: Add job count to GuC exec queue snapshot Matthew Brost
2026-09-04 2:21 ` [PATCH v5 05/25] drm/xe: Update xe_bo_put_deferred arguments to include writeback flag Matthew Brost
2026-09-04 2:44 ` sashiko-bot
2026-09-04 2:21 ` [PATCH v5 06/25] drm/xe: Add XE_BO_FLAG_PUT_VM_ASYNC Matthew Brost
2026-09-04 2:21 ` [PATCH v5 07/25] drm/xe: Update scheduler job layer to support PT jobs Matthew Brost
2026-09-04 2:21 ` [PATCH v5 08/25] drm/xe: Add helpers to access PT ops Matthew Brost
2026-09-04 2:21 ` [PATCH v5 09/25] drm/xe: Add struct xe_pt_job_ops Matthew Brost
2026-09-04 2:48 ` sashiko-bot
2026-09-04 2:21 ` [PATCH v5 10/25] drm/xe: Update GuC submission backend to run PT jobs Matthew Brost
2026-09-04 2:46 ` sashiko-bot
2026-09-04 2:21 ` [PATCH v5 11/25] drm/xe: Store level in struct xe_vm_pgtable_update Matthew Brost
2026-09-04 2:21 ` [PATCH v5 12/25] drm/xe: Don't use migrate exec queue for page fault binds Matthew Brost
2026-09-04 2:21 ` [PATCH v5 13/25] drm/xe: Enable CPU binds for jobs Matthew Brost
2026-09-04 2:51 ` sashiko-bot
2026-09-04 2:21 ` [PATCH v5 14/25] drm/xe: Remove unused arguments from xe_migrate_pt_update_ops Matthew Brost
2026-09-04 2:21 ` [PATCH v5 15/25] drm/xe: Make bind queues operate cross-tile Matthew Brost
2026-09-04 2:21 ` [PATCH v5 16/25] drm/xe: Add CPU bind layer Matthew Brost
2026-09-04 2:21 ` Matthew Brost [this message]
2026-09-04 2:43 ` [PATCH v5 17/25] drm/xe: Add device flag to enable PT mirroring across tiles sashiko-bot
2026-09-04 4:10 ` Matthew Brost
2026-09-04 2:22 ` [PATCH v5 18/25] drm/xe: Add xe_hw_engine_write_ring_tail Matthew Brost
2026-09-04 2:22 ` [PATCH v5 19/25] drm/xe: Add ULLS support to LRC Matthew Brost
2026-09-04 2:22 ` [PATCH v5 20/25] drm/xe: Add ULLS migration job support to migration layer Matthew Brost
2026-09-04 2:44 ` sashiko-bot
2026-09-04 4:11 ` Matthew Brost
2026-09-04 2:22 ` [PATCH v5 21/25] drm/xe: Add ULLS migration job support to ring ops Matthew Brost
2026-09-04 2:22 ` [PATCH v5 22/25] drm/xe: Add ULLS migration job support to GuC submission Matthew Brost
2026-09-04 2:49 ` sashiko-bot
2026-09-04 4:17 ` Matthew Brost
2026-09-04 2:22 ` [PATCH v5 23/25] drm/xe: Enter ULLS for migration jobs upon page fault or SVM prefetch Matthew Brost
2026-09-04 2:22 ` [PATCH v5 24/25] drm/xe: Add modparam to enable / disable ULLS on migrate queue Matthew Brost
2026-09-04 2:22 ` [PATCH v5 25/25] drm/xe: Document ULLS for migration jobs Matthew Brost
2026-09-04 2:29 ` ✗ CI.checkpatch: warning for CPU binds and ULLS on migration queue (rev7) Patchwork
2026-09-04 2:31 ` ✓ CI.KUnit: success " Patchwork
2026-09-04 3:08 ` ✓ Xe.CI.BAT: " Patchwork
2026-09-04 15:21 ` ✗ Xe.CI.FULL: failure " Patchwork
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