[PATCH 0/2] drm/xe: Add wa_14025941587 to xe2, xe3 and xe3p platforms

[PATCH 0/2] drm/xe: Add wa_14025941587 to xe2, xe3 and xe3p platforms

[tilak.tirumalesh.tangudu]

From: Tangudu Tilak Tirumalesh <tilak.tirumalesh.tangudu@intel.com>

This series adds Wa_14025941587 (minimum IDLEDLY floor) for Xe2, Xe3 and
Xe3p and hardens the shared adjust_idledly() helper it builds on.

Patch 1 fixes three pre-existing corner cases in adjust_idledly() that
can panic or misprogram RING_IDLEDLY.
(timestamp_base == 0 divide-by-zero, IDLE_WAIT_TIME == 0 underflow, and
u32 overflow in the tick<->ns conversions).

Patch 2 applies Wa_14025941587 on top of the hardened helper.

Patch1 v2:
Fix fourth issue by clamp with a floor (DIV_ROUND_DOWN_ULL) so the 
programmed delay stays strictly below maxcnt.

Patch2 v8:
Round up (DIV_ROUND_UP_ULL) the Wa_14025941587 minimum conversion instead,
so the tick-quantized delay cannot round back below 5 us.

Tangudu Tilak Tirumalesh (2):
  drm/xe: harden adjust_idledly() against divide-by-zero and overflow
  drm/xe: Add wa_14025941587 to xe2, xe3 and xe3p platforms

 drivers/gpu/drm/xe/xe_guc_ads.c    |  2 +-
 drivers/gpu/drm/xe/xe_hw_engine.c  | 75 +++++++++++++++++++++++++-----
 drivers/gpu/drm/xe/xe_wa_oob.rules |  2 +
 3 files changed, 67 insertions(+), 12 deletions(-)

-- 
2.46.0

[PATCH 1/2] drm/xe: harden adjust_idledly() against divide-by-zero and overflow

[tilak.tirumalesh.tangudu]

From: Tangudu Tilak Tirumalesh <tilak.tirumalesh.tangudu@intel.com>

adjust_idledly() has several corner-case issues flagged during review:

  1. If xe_gt_clock_init() failed to recognise the crystal clock,
     gt->info.timestamp_base is 0, which makes idledly_units_ps also 0.
     The subsequent DIV_ROUND_CLOSEST(..., idledly_units_ps) is then a
     divide-by-zero and panics the kernel.

  2. The tick-to-ns conversions are done in u32:
        idledly * idledly_units_ps, (maxcnt - 1) * 1000
     Both overflow u32 before DIV_ROUND_CLOSEST() sees them.

  3. If IDLE_WAIT_TIME reads back as 0, maxcnt evaluates to 0 and
     the maxcnt - 1 clamp wraps to 0xFFFFFFFF in u32.

  4. The register only stores whole ticks, so the clamped ns value has
     to be converted to ticks and back. DIV_ROUND_CLOSEST() can round
     that conversion up past maxcnt:

       maxcnt = 640 ns, one tick = 666664 ps

       clamp:        maxcnt - 1        = 639 ns
       ns -> ticks:  639000 / 666664   = 0.958 -> rounds to 1 tick
       tick -> ns:    1 * 666664 / 1000 = 667 ns

     667 ns is programmed into RING_IDLEDLY, but 667 >= maxcnt (640),
     so xe_gt_WARN_ON() fires again on every subsequent init.

Warn and return early if timestamp_base is 0 (the unknown-crystal path).
Do the conversions in u64 via the *_ULL() helpers so they cannot wrap.
Clamp with a floor (DIV_ROUND_DOWN_ULL) so the programmed delay stays
strictly below maxcnt, and guard the maxcnt == 0 case with a zero delay
while still writing RING_IDLEDLY so INHIBIT_SWITCH_UNTIL_PREEMPTED is
cleared.

Fixes: d2de4410a88f ("drm/xe: Apply Wa_16023105232")
Cc: stable@vger.kernel.org
Assisted-by: GitHub_Copilot:claude-opus-4.8
Signed-off-by: Tangudu Tilak Tirumalesh <tilak.tirumalesh.tangudu@intel.com>
---
 drivers/gpu/drm/xe/xe_hw_engine.c | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index 010499766fce..c86890e09b55 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -594,18 +594,26 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
 	bool inhibit_switch = 0;
 
 	if (!IS_SRIOV_VF(gt_to_xe(hwe->gt)) && XE_GT_WA(gt, 16023105232)) {
+		/* xe_gt_clock_init() zeroes timestamp_base on unknown crystal clock. */
+		if (!idledly_units_ps) {
+			xe_gt_warn(gt, "idledly WA skipped: timestamp_base is 0\n");
+			return;
+		}
+
 		idledly = xe_mmio_read32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base));
 		maxcnt = xe_mmio_read32(&gt->mmio, RING_PWRCTX_MAXCNT(hwe->mmio_base));
 
 		inhibit_switch = idledly & INHIBIT_SWITCH_UNTIL_PREEMPTED;
 		idledly = REG_FIELD_GET(IDLE_DELAY, idledly);
-		idledly = DIV_ROUND_CLOSEST(idledly * idledly_units_ps, 1000);
+		idledly = DIV_ROUND_CLOSEST_ULL((u64)idledly * idledly_units_ps, 1000);
 		maxcnt = REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt);
 		maxcnt *= maxcnt_units_ns;
 
 		if (xe_gt_WARN_ON(gt, idledly >= maxcnt || inhibit_switch)) {
-			idledly = DIV_ROUND_CLOSEST(((maxcnt - 1) * 1000),
-						    idledly_units_ps);
+			/* Floor below maxcnt; write 0 to still clear the inhibit bit. */
+			idledly = maxcnt ?
+				DIV_ROUND_DOWN_ULL((u64)(maxcnt - 1) * 1000,
+						   idledly_units_ps) : 0;
 			xe_mmio_write32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base), idledly);
 		}
 	}
-- 
2.46.0

Re: [PATCH 1/2] drm/xe: harden adjust_idledly() against divide-by-zero and overflow

[Belgaumkar, Vinay]

On 9/9/2026 9:18 AM, tilak.tirumalesh.tangudu@intel.com wrote:
> From: Tangudu Tilak Tirumalesh <tilak.tirumalesh.tangudu@intel.com>
>
> adjust_idledly() has several corner-case issues flagged during review:
>
>    1. If xe_gt_clock_init() failed to recognise the crystal clock,
>       gt->info.timestamp_base is 0, which makes idledly_units_ps also 0.
>       The subsequent DIV_ROUND_CLOSEST(..., idledly_units_ps) is then a
>       divide-by-zero and panics the kernel.
>
>    2. The tick-to-ns conversions are done in u32:
>          idledly * idledly_units_ps, (maxcnt - 1) * 1000
>       Both overflow u32 before DIV_ROUND_CLOSEST() sees them.
>
>    3. If IDLE_WAIT_TIME reads back as 0, maxcnt evaluates to 0 and
>       the maxcnt - 1 clamp wraps to 0xFFFFFFFF in u32.
>
>    4. The register only stores whole ticks, so the clamped ns value has
>       to be converted to ticks and back. DIV_ROUND_CLOSEST() can round
>       that conversion up past maxcnt:
>
>         maxcnt = 640 ns, one tick = 666664 ps
>
>         clamp:        maxcnt - 1        = 639 ns
>         ns -> ticks:  639000 / 666664   = 0.958 -> rounds to 1 tick
>         tick -> ns:    1 * 666664 / 1000 = 667 ns
>
>       667 ns is programmed into RING_IDLEDLY, but 667 >= maxcnt (640),
>       so xe_gt_WARN_ON() fires again on every subsequent init.
>
> Warn and return early if timestamp_base is 0 (the unknown-crystal path).
> Do the conversions in u64 via the *_ULL() helpers so they cannot wrap.
> Clamp with a floor (DIV_ROUND_DOWN_ULL) so the programmed delay stays
> strictly below maxcnt, and guard the maxcnt == 0 case with a zero delay
> while still writing RING_IDLEDLY so INHIBIT_SWITCH_UNTIL_PREEMPTED is
> cleared.
>
> Fixes: d2de4410a88f ("drm/xe: Apply Wa_16023105232")
> Cc: stable@vger.kernel.org
> Assisted-by: GitHub_Copilot:claude-opus-4.8
> Signed-off-by: Tangudu Tilak Tirumalesh <tilak.tirumalesh.tangudu@intel.com>
> ---
>   drivers/gpu/drm/xe/xe_hw_engine.c | 14 +++++++++++---
>   1 file changed, 11 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
> index 010499766fce..c86890e09b55 100644
> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
> @@ -594,18 +594,26 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
>   	bool inhibit_switch = 0;
>   
>   	if (!IS_SRIOV_VF(gt_to_xe(hwe->gt)) && XE_GT_WA(gt, 16023105232)) {
> +		/* xe_gt_clock_init() zeroes timestamp_base on unknown crystal clock. */
> +		if (!idledly_units_ps) {
> +			xe_gt_warn(gt, "idledly WA skipped: timestamp_base is 0\n");
There is already a xe_gt_warn in xe_gt_clock.c when timestamp_base is 
set to 0 in xe_gt_clock.c, so this is redundant. CI failures will happen 
if this is the case anyway.
> +			return;
> +		}
> +
>   		idledly = xe_mmio_read32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base));
>   		maxcnt = xe_mmio_read32(&gt->mmio, RING_PWRCTX_MAXCNT(hwe->mmio_base));
>   
>   		inhibit_switch = idledly & INHIBIT_SWITCH_UNTIL_PREEMPTED;
>   		idledly = REG_FIELD_GET(IDLE_DELAY, idledly);
> -		idledly = DIV_ROUND_CLOSEST(idledly * idledly_units_ps, 1000);
> +		idledly = DIV_ROUND_CLOSEST_ULL((u64)idledly * idledly_units_ps, 1000);
>   		maxcnt = REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt);
>   		maxcnt *= maxcnt_units_ns;
>   
>   		if (xe_gt_WARN_ON(gt, idledly >= maxcnt || inhibit_switch)) {
> -			idledly = DIV_ROUND_CLOSEST(((maxcnt - 1) * 1000),
> -						    idledly_units_ps);
> +			/* Floor below maxcnt; write 0 to still clear the inhibit bit. */
> +			idledly = maxcnt ?

shouldn't this be idledly >= maxcnt ?

Thanks,

Vinay.

> +				DIV_ROUND_DOWN_ULL((u64)(maxcnt - 1) * 1000,
> +						   idledly_units_ps) : 0;

>   			xe_mmio_write32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base), idledly);
>   		}
>   	}

RE: [PATCH 1/2] drm/xe: harden adjust_idledly() against divide-by-zero and overflow

[Tangudu, Tilak Tirumalesh]

> -----Original Message-----
> From: Belgaumkar, Vinay <vinay.belgaumkar@intel.com>
> Sent: 11 September 2026 23:09
> To: Tangudu, Tilak Tirumalesh <tilak.tirumalesh.tangudu@intel.com>;
> Upadhyay, Tejas <tejas.upadhyay@intel.com>; Sousa, Gustavo
> <gustavo.sousa@intel.com>; intel-xe@lists.freedesktop.org
> Subject: Re: [PATCH 1/2] drm/xe: harden adjust_idledly() against divide-by-
> zero and overflow
> 
> 
> On 9/9/2026 9:18 AM, tilak.tirumalesh.tangudu@intel.com wrote:
> > From: Tangudu Tilak Tirumalesh <tilak.tirumalesh.tangudu@intel.com>
> >
> > adjust_idledly() has several corner-case issues flagged during review:
> >
> >    1. If xe_gt_clock_init() failed to recognise the crystal clock,
> >       gt->info.timestamp_base is 0, which makes idledly_units_ps also 0.
> >       The subsequent DIV_ROUND_CLOSEST(..., idledly_units_ps) is then a
> >       divide-by-zero and panics the kernel.
> >
> >    2. The tick-to-ns conversions are done in u32:
> >          idledly * idledly_units_ps, (maxcnt - 1) * 1000
> >       Both overflow u32 before DIV_ROUND_CLOSEST() sees them.
> >
> >    3. If IDLE_WAIT_TIME reads back as 0, maxcnt evaluates to 0 and
> >       the maxcnt - 1 clamp wraps to 0xFFFFFFFF in u32.
> >
> >    4. The register only stores whole ticks, so the clamped ns value has
> >       to be converted to ticks and back. DIV_ROUND_CLOSEST() can round
> >       that conversion up past maxcnt:
> >
> >         maxcnt = 640 ns, one tick = 666664 ps
> >
> >         clamp:        maxcnt - 1        = 639 ns
> >         ns -> ticks:  639000 / 666664   = 0.958 -> rounds to 1 tick
> >         tick -> ns:    1 * 666664 / 1000 = 667 ns
> >
> >       667 ns is programmed into RING_IDLEDLY, but 667 >= maxcnt (640),
> >       so xe_gt_WARN_ON() fires again on every subsequent init.
> >
> > Warn and return early if timestamp_base is 0 (the unknown-crystal path).
> > Do the conversions in u64 via the *_ULL() helpers so they cannot wrap.
> > Clamp with a floor (DIV_ROUND_DOWN_ULL) so the programmed delay
> stays
> > strictly below maxcnt, and guard the maxcnt == 0 case with a zero
> > delay while still writing RING_IDLEDLY so
> > INHIBIT_SWITCH_UNTIL_PREEMPTED is cleared.
> >
> > Fixes: d2de4410a88f ("drm/xe: Apply Wa_16023105232")
> > Cc: stable@vger.kernel.org
> > Assisted-by: GitHub_Copilot:claude-opus-4.8
> > Signed-off-by: Tangudu Tilak Tirumalesh
> > <tilak.tirumalesh.tangudu@intel.com>
> > ---
> >   drivers/gpu/drm/xe/xe_hw_engine.c | 14 +++++++++++---
> >   1 file changed, 11 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c
> > b/drivers/gpu/drm/xe/xe_hw_engine.c
> > index 010499766fce..c86890e09b55 100644
> > --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> > +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
> > @@ -594,18 +594,26 @@ static void adjust_idledly(struct xe_hw_engine
> *hwe)
> >   	bool inhibit_switch = 0;
> >
> >   	if (!IS_SRIOV_VF(gt_to_xe(hwe->gt)) && XE_GT_WA(gt,
> 16023105232)) {
> > +		/* xe_gt_clock_init() zeroes timestamp_base on unknown
> crystal clock. */
> > +		if (!idledly_units_ps) {
> > +			xe_gt_warn(gt, "idledly WA skipped: timestamp_base
> is 0\n");
> There is already a xe_gt_warn in xe_gt_clock.c when timestamp_base is set to
> 0 in xe_gt_clock.c, so this is redundant. CI failures will happen if this is the
> case anyway.

I will make it silent and remove warn but "return" should stay right?
> > +			return;
> > +		}
> > +
> >   		idledly = xe_mmio_read32(&gt->mmio, RING_IDLEDLY(hwe-
> >mmio_base));
> >   		maxcnt = xe_mmio_read32(&gt->mmio,
> > RING_PWRCTX_MAXCNT(hwe->mmio_base));
> >
> >   		inhibit_switch = idledly &
> INHIBIT_SWITCH_UNTIL_PREEMPTED;
> >   		idledly = REG_FIELD_GET(IDLE_DELAY, idledly);
> > -		idledly = DIV_ROUND_CLOSEST(idledly * idledly_units_ps,
> 1000);
> > +		idledly = DIV_ROUND_CLOSEST_ULL((u64)idledly *
> idledly_units_ps,
> > +1000);
> >   		maxcnt = REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt);
> >   		maxcnt *= maxcnt_units_ns;
> >
> >   		if (xe_gt_WARN_ON(gt, idledly >= maxcnt || inhibit_switch)) {
> > -			idledly = DIV_ROUND_CLOSEST(((maxcnt - 1) * 1000),
> > -						    idledly_units_ps);
> > +			/* Floor below maxcnt; write 0 to still clear the inhibit
> bit. */
> > +			idledly = maxcnt ?
> 
> shouldn't this be idledly >= maxcnt ?
 idledly >= maxcnt  this is already in if guard 
the above check is for maxcnt zero case

> 
> Thanks,
> 
> Vinay.
> 
> > +				DIV_ROUND_DOWN_ULL((u64)(maxcnt - 1) *
> 1000,
> > +						   idledly_units_ps) : 0;
> 
> >   			xe_mmio_write32(&gt->mmio, RING_IDLEDLY(hwe-
> >mmio_base), idledly);
> >   		}
> >   	}

Re: [PATCH 1/2] drm/xe: harden adjust_idledly() against divide-by-zero and overflow

[Belgaumkar, Vinay]

On 9/11/2026 10:44 AM, Tangudu, Tilak Tirumalesh wrote:
>
>> -----Original Message-----
>> From: Belgaumkar, Vinay <vinay.belgaumkar@intel.com>
>> Sent: 11 September 2026 23:09
>> To: Tangudu, Tilak Tirumalesh <tilak.tirumalesh.tangudu@intel.com>;
>> Upadhyay, Tejas <tejas.upadhyay@intel.com>; Sousa, Gustavo
>> <gustavo.sousa@intel.com>; intel-xe@lists.freedesktop.org
>> Subject: Re: [PATCH 1/2] drm/xe: harden adjust_idledly() against divide-by-
>> zero and overflow
>>
>>
>> On 9/9/2026 9:18 AM, tilak.tirumalesh.tangudu@intel.com wrote:
>>> From: Tangudu Tilak Tirumalesh <tilak.tirumalesh.tangudu@intel.com>
>>>
>>> adjust_idledly() has several corner-case issues flagged during review:
>>>
>>>     1. If xe_gt_clock_init() failed to recognise the crystal clock,
>>>        gt->info.timestamp_base is 0, which makes idledly_units_ps also 0.
>>>        The subsequent DIV_ROUND_CLOSEST(..., idledly_units_ps) is then a
>>>        divide-by-zero and panics the kernel.
>>>
>>>     2. The tick-to-ns conversions are done in u32:
>>>           idledly * idledly_units_ps, (maxcnt - 1) * 1000
>>>        Both overflow u32 before DIV_ROUND_CLOSEST() sees them.
>>>
>>>     3. If IDLE_WAIT_TIME reads back as 0, maxcnt evaluates to 0 and
>>>        the maxcnt - 1 clamp wraps to 0xFFFFFFFF in u32.
>>>
>>>     4. The register only stores whole ticks, so the clamped ns value has
>>>        to be converted to ticks and back. DIV_ROUND_CLOSEST() can round
>>>        that conversion up past maxcnt:
>>>
>>>          maxcnt = 640 ns, one tick = 666664 ps
>>>
>>>          clamp:        maxcnt - 1        = 639 ns
>>>          ns -> ticks:  639000 / 666664   = 0.958 -> rounds to 1 tick
>>>          tick -> ns:    1 * 666664 / 1000 = 667 ns
>>>
>>>        667 ns is programmed into RING_IDLEDLY, but 667 >= maxcnt (640),
>>>        so xe_gt_WARN_ON() fires again on every subsequent init.
>>>
>>> Warn and return early if timestamp_base is 0 (the unknown-crystal path).
>>> Do the conversions in u64 via the *_ULL() helpers so they cannot wrap.
>>> Clamp with a floor (DIV_ROUND_DOWN_ULL) so the programmed delay
>> stays
>>> strictly below maxcnt, and guard the maxcnt == 0 case with a zero
>>> delay while still writing RING_IDLEDLY so
>>> INHIBIT_SWITCH_UNTIL_PREEMPTED is cleared.
>>>
>>> Fixes: d2de4410a88f ("drm/xe: Apply Wa_16023105232")
>>> Cc: stable@vger.kernel.org
>>> Assisted-by: GitHub_Copilot:claude-opus-4.8
>>> Signed-off-by: Tangudu Tilak Tirumalesh
>>> <tilak.tirumalesh.tangudu@intel.com>
>>> ---
>>>    drivers/gpu/drm/xe/xe_hw_engine.c | 14 +++++++++++---
>>>    1 file changed, 11 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c
>>> b/drivers/gpu/drm/xe/xe_hw_engine.c
>>> index 010499766fce..c86890e09b55 100644
>>> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
>>> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
>>> @@ -594,18 +594,26 @@ static void adjust_idledly(struct xe_hw_engine
>> *hwe)
>>>    	bool inhibit_switch = 0;
>>>
>>>    	if (!IS_SRIOV_VF(gt_to_xe(hwe->gt)) && XE_GT_WA(gt,
>> 16023105232)) {
>>> +		/* xe_gt_clock_init() zeroes timestamp_base on unknown
>> crystal clock. */
>>> +		if (!idledly_units_ps) {
>>> +			xe_gt_warn(gt, "idledly WA skipped: timestamp_base
>> is 0\n");
>> There is already a xe_gt_warn in xe_gt_clock.c when timestamp_base is set to
>> 0 in xe_gt_clock.c, so this is redundant. CI failures will happen if this is the
>> case anyway.
> I will make it silent and remove warn but "return" should stay right?
>>> +			return;
>>> +		}
>>> +
>>>    		idledly = xe_mmio_read32(&gt->mmio, RING_IDLEDLY(hwe-
>>> mmio_base));
>>>    		maxcnt = xe_mmio_read32(&gt->mmio,
>>> RING_PWRCTX_MAXCNT(hwe->mmio_base));
>>>
>>>    		inhibit_switch = idledly &
>> INHIBIT_SWITCH_UNTIL_PREEMPTED;
>>>    		idledly = REG_FIELD_GET(IDLE_DELAY, idledly);
>>> -		idledly = DIV_ROUND_CLOSEST(idledly * idledly_units_ps,
>> 1000);
>>> +		idledly = DIV_ROUND_CLOSEST_ULL((u64)idledly *
>> idledly_units_ps,
>>> +1000);
>>>    		maxcnt = REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt);
>>>    		maxcnt *= maxcnt_units_ns;
>>>
>>>    		if (xe_gt_WARN_ON(gt, idledly >= maxcnt || inhibit_switch)) {
>>> -			idledly = DIV_ROUND_CLOSEST(((maxcnt - 1) * 1000),
>>> -						    idledly_units_ps);
>>> +			/* Floor below maxcnt; write 0 to still clear the inhibit
>> bit. */
>>> +			idledly = maxcnt ?
>> shouldn't this be idledly >= maxcnt ?
>   idledly >= maxcnt  this is already in if guard
> the above check is for maxcnt zero case

ok, makes sense. LGTM.

Reviewed-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>

>
>> Thanks,
>>
>> Vinay.
>>
>>> +				DIV_ROUND_DOWN_ULL((u64)(maxcnt - 1) *
>> 1000,
>>> +						   idledly_units_ps) : 0;
>>>    			xe_mmio_write32(&gt->mmio, RING_IDLEDLY(hwe-
>>> mmio_base), idledly);
>>>    		}
>>>    	}

[PATCH 2/2] drm/xe: Add wa_14025941587 to xe2, xe3 and xe3p platforms

[tilak.tirumalesh.tangudu]

From: Tangudu Tilak Tirumalesh <tilak.tirumalesh.tangudu@intel.com>

Avoid programming the IDLEDLY timer to less than 5 microseconds.
Apply wa_14025941587 to Graphics Versions 20.01 to 35.11
and Media Versions 13.01 to 35.03

v2: Use xe_rtp_match_not_sriov_vf, move to local variable
    Remove warn and other knits            - Matt R

v3: Add verbose comment - Tejas

v4: Restore IDLE_DLY register on engine reset.
    Add it to GUC save-restore list. -Vivek

v5: Extend WA to Media Versions 13.01 to 35.03 - Vinay

v6: Avoid clearing inhibit switch - Bala
    Refactor code accordingly by adding idle_reg_val.

v7: Rebased with the divide-by-zero/overflow guards living in
    a separate hardening patch.

v8: Preserve the Wa_16023105232 floor (DIV_ROUND_DOWN_ULL) and the
    maxcnt == 0 guard from the hardening patch. Round up
    (DIV_ROUND_UP_ULL) the Wa_14025941587 minimum conversion instead,
    so the tick-quantized delay cannot round back below 5 us.

Assisted-by: GitHub_Copilot:claude-opus-4.8
Signed-off-by: Tangudu Tilak Tirumalesh <tilak.tirumalesh.tangudu@intel.com>
---
 drivers/gpu/drm/xe/xe_guc_ads.c    |  2 +-
 drivers/gpu/drm/xe/xe_hw_engine.c  | 69 ++++++++++++++++++++++++------
 drivers/gpu/drm/xe/xe_wa_oob.rules |  2 +
 3 files changed, 60 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
index ff8eee3831aa..58a3f6293ce4 100644
--- a/drivers/gpu/drm/xe/xe_guc_ads.c
+++ b/drivers/gpu/drm/xe/xe_guc_ads.c
@@ -864,7 +864,7 @@ static unsigned int guc_mmio_regset_write(struct xe_guc_ads *ads,
 		}
 	}
 
-	if (XE_GT_WA(hwe->gt, 16023105232))
+	if (XE_GT_WA(hwe->gt, 16023105232) || XE_GT_WA(hwe->gt, 14025941587))
 		guc_mmio_regset_write_one(ads, regset_map,
 					  RING_IDLEDLY(hwe->mmio_base),
 					  count++);
diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index c86890e09b55..37cd7fe38c2b 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -588,33 +588,78 @@ static void hw_engine_init_early(struct xe_gt *gt, struct xe_hw_engine *hwe,
 static void adjust_idledly(struct xe_hw_engine *hwe)
 {
 	struct xe_gt *gt = hwe->gt;
-	u32 idledly, maxcnt;
+	u32 idledly, idledly_reg_val, maxcnt;
 	u32 idledly_units_ps = 8 * gt->info.timestamp_base;
 	u32 maxcnt_units_ns = 640;
-	bool inhibit_switch = 0;
+	bool inhibit_switch = false;
+	bool wa_applied = false;
+	bool clamped_below_maxcnt = false;
+
+	if ((!IS_SRIOV_VF(gt_to_xe(hwe->gt)) && XE_GT_WA(gt, 16023105232)) ||
+	    XE_GT_WA(gt, 14025941587)) {
+		u32 mincnt_idledly_ns = 5000;
 
-	if (!IS_SRIOV_VF(gt_to_xe(hwe->gt)) && XE_GT_WA(gt, 16023105232)) {
 		/* xe_gt_clock_init() zeroes timestamp_base on unknown crystal clock. */
 		if (!idledly_units_ps) {
 			xe_gt_warn(gt, "idledly WA skipped: timestamp_base is 0\n");
 			return;
 		}
 
-		idledly = xe_mmio_read32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base));
+		idledly_reg_val = xe_mmio_read32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base));
 		maxcnt = xe_mmio_read32(&gt->mmio, RING_PWRCTX_MAXCNT(hwe->mmio_base));
 
-		inhibit_switch = idledly & INHIBIT_SWITCH_UNTIL_PREEMPTED;
-		idledly = REG_FIELD_GET(IDLE_DELAY, idledly);
+		inhibit_switch = idledly_reg_val & INHIBIT_SWITCH_UNTIL_PREEMPTED;
+		idledly = REG_FIELD_GET(IDLE_DELAY, idledly_reg_val);
 		idledly = DIV_ROUND_CLOSEST_ULL((u64)idledly * idledly_units_ps, 1000);
 		maxcnt = REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt);
 		maxcnt *= maxcnt_units_ns;
 
-		if (xe_gt_WARN_ON(gt, idledly >= maxcnt || inhibit_switch)) {
-			/* Floor below maxcnt; write 0 to still clear the inhibit bit. */
-			idledly = maxcnt ?
-				DIV_ROUND_DOWN_ULL((u64)(maxcnt - 1) * 1000,
-						   idledly_units_ps) : 0;
-			xe_mmio_write32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base), idledly);
+		/*
+		 * Wa_14025941587 is applied before Wa_16023105232, which has
+		 * higher priority; the two are not expected to conflict.
+		 */
+		if (XE_GT_WA(gt, 14025941587) &&
+		    idledly < mincnt_idledly_ns) {
+			idledly = mincnt_idledly_ns;
+			wa_applied = true;
+		}
+
+		if (XE_GT_WA(gt, 16023105232) &&
+		    xe_gt_WARN_ON(gt, idledly >= maxcnt || inhibit_switch)) {
+			/* maxcnt may be 0 if IDLE_WAIT_TIME is unprogrammed. */
+			idledly = maxcnt ? maxcnt - 1 : 0;
+			clamped_below_maxcnt = true;
+			wa_applied = true;
+			/* inhibit_switch override to keep
+			 * semantics of Wa_16023105232
+			 */
+			if (inhibit_switch)
+				idledly_reg_val &= ~INHIBIT_SWITCH_UNTIL_PREEMPTED;
+		}
+
+		if (wa_applied) {
+			u32 idledly_ticks;
+
+			/*
+			 * Wa_16023105232 requires idledly < maxcnt, so floor
+			 * that clamp; otherwise round up to guarantee the
+			 * Wa_14025941587 minimum survives tick quantization.
+			 */
+			if (clamped_below_maxcnt)
+				idledly_ticks = DIV_ROUND_DOWN_ULL((u64)idledly * 1000,
+								   idledly_units_ps);
+			else
+				idledly_ticks = DIV_ROUND_UP_ULL((u64)idledly * 1000,
+								 idledly_units_ps);
+
+			idledly_reg_val &= ~IDLE_DELAY;
+			idledly_reg_val |= REG_FIELD_PREP(IDLE_DELAY, idledly_ticks);
+			xe_gt_dbg(gt, "idledly %s: set %u max=%u inh=%u ts=%u\n",
+				  hwe->name, idledly, maxcnt,
+				  !!inhibit_switch, gt->info.timestamp_base);
+			xe_mmio_write32(&gt->mmio,
+					RING_IDLEDLY(hwe->mmio_base),
+					idledly_reg_val);
 		}
 	}
 }
diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
index dd69ad07f7a9..3001155f8d09 100644
--- a/drivers/gpu/drm/xe/xe_wa_oob.rules
+++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
@@ -72,3 +72,5 @@
 16029897822	MEDIA_VERSION(3500)
 		GRAPHICS_VERSION(3510)
 14027054324	GRAPHICS_VERSION(3511)
+14025941587	GRAPHICS_VERSION_RANGE(2001, 3511), FUNC(xe_rtp_match_not_sriov_vf)
+		MEDIA_VERSION_RANGE(1301, 3503), FUNC(xe_rtp_match_not_sriov_vf)
-- 
2.46.0

Re: [PATCH 2/2] drm/xe: Add wa_14025941587 to xe2, xe3 and xe3p platforms

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Tick quantization rounding up causes `idledly` to exceed `maxcnt`, triggering spurious kernel warnings and WA invariant violations.
--

commit d777113f52ced7ebda03cbb9155258701e427a45
Author: Tangudu Tilak Tirumalesh <tilak.tirumalesh.tangudu@intel.com>

drm/xe: Add wa_14025941587 to xe2, xe3 and xe3p platforms

This commit avoids programming the IDLEDLY timer to less than 5 microseconds.
It applies wa_14025941587 to Graphics Versions 20.01 to 35.11 and Media
Versions 13.01 to 35.03.

> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
> index c86890e09b555..37cd7fe38c2b5 100644
> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
[ ... ]
> @@ -588,33 +588,78 @@ static void hw_engine_init_early(struct xe_gt *gt, struct xe_hw_engine *hwe,
>  static void adjust_idledly(struct xe_hw_engine *hwe)
>  {
>  	struct xe_gt *gt = hwe->gt;
[ ... ]
> +		if (XE_GT_WA(gt, 16023105232) &&
> +		    xe_gt_WARN_ON(gt, idledly >= maxcnt || inhibit_switch)) {
                    ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

[Severity: Medium]
Will this warning spuriously fire on subsequent reads?

If maxcnt is unprogrammed (0), the two workarounds conflict entirely (one
forcing 5000, the other forcing 0), which would cause a WARN_ON and clamp
cycle on every reset.

Additionally, if maxcnt tightly bounds the 5000ns minimum, the tick
quantization rounding up below can push the delay time above maxcnt. On the
next engine reset or resume, this triggers this xe_gt_WARN_ON() and forces a
clamp, causing idledly to oscillate and violate the invariants of
Wa_16023105232.

> +			/* maxcnt may be 0 if IDLE_WAIT_TIME is unprogrammed. */
> +			idledly = maxcnt ? maxcnt - 1 : 0;
> +			clamped_below_maxcnt = true;
> +			wa_applied = true;
> +			/* inhibit_switch override to keep
> +			 * semantics of Wa_16023105232
> +			 */
> +			if (inhibit_switch)
> +				idledly_reg_val &= ~INHIBIT_SWITCH_UNTIL_PREEMPTED;
> +		}
> +
> +		if (wa_applied) {
> +			u32 idledly_ticks;
> +
> +			/*
> +			 * Wa_16023105232 requires idledly < maxcnt, so floor
> +			 * that clamp; otherwise round up to guarantee the
> +			 * Wa_14025941587 minimum survives tick quantization.
> +			 */
> +			if (clamped_below_maxcnt)
> +				idledly_ticks = DIV_ROUND_DOWN_ULL((u64)idledly * 1000,
> +								   idledly_units_ps);
> +			else
> +				idledly_ticks = DIV_ROUND_UP_ULL((u64)idledly * 1000,
> +								 idledly_units_ps);
                                                                 ^^^^^^^^^^^^^^^^^^

[Severity: Medium]
Does this ceiling division push the delay time above the maxcnt boundary?

When maxcnt is close to the 5000ns minimum (e.g. 5120ns), rounding up idledly
to ticks produces a delay (e.g. 5417ns) that exceeds maxcnt, storing a value
that will fail the Wa_16023105232 check on the next read.

> +
> +			idledly_reg_val &= ~IDLE_DELAY;
> +			idledly_reg_val |= REG_FIELD_PREP(IDLE_DELAY, idledly_ticks);

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260909161844.125147-1-tilak.tirumalesh.tangudu@intel.com?part=2

RE: [PATCH 2/2] drm/xe: Add wa_14025941587 to xe2, xe3 and xe3p platforms

[Tangudu, Tilak Tirumalesh]

> -----Original Message-----
> From: sashiko-bot@kernel.org <sashiko-bot@kernel.org>
> Sent: 09 September 2026 22:03
> To: Tangudu, Tilak Tirumalesh <tilak.tirumalesh.tangudu@intel.com>
> Cc: intel-xe@lists.freedesktop.org
> Subject: Re: [PATCH 2/2] drm/xe: Add wa_14025941587 to xe2, xe3 and xe3p
> platforms
> 
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to
> consider:
> - [Medium] Tick quantization rounding up causes `idledly` to exceed `maxcnt`,
> triggering spurious kernel warnings and WA invariant violations.
> --
> 
> commit d777113f52ced7ebda03cbb9155258701e427a45
> Author: Tangudu Tilak Tirumalesh <tilak.tirumalesh.tangudu@intel.com>
> 
> drm/xe: Add wa_14025941587 to xe2, xe3 and xe3p platforms
> 
> This commit avoids programming the IDLEDLY timer to less than 5
> microseconds.
> It applies wa_14025941587 to Graphics Versions 20.01 to 35.11 and Media
> Versions 13.01 to 35.03.
> 
> > diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c
> > b/drivers/gpu/drm/xe/xe_hw_engine.c
> > index c86890e09b555..37cd7fe38c2b5 100644
> > --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> > +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
> [ ... ]
> > @@ -588,33 +588,78 @@ static void hw_engine_init_early(struct xe_gt
> > *gt, struct xe_hw_engine *hwe,  static void adjust_idledly(struct
> > xe_hw_engine *hwe)  {
> >  	struct xe_gt *gt = hwe->gt;
> [ ... ]
> > +		if (XE_GT_WA(gt, 16023105232) &&
> > +		    xe_gt_WARN_ON(gt, idledly >= maxcnt || inhibit_switch)) {
>                     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
> 
> [Severity: Medium]
> Will this warning spuriously fire on subsequent reads?
> 
> If maxcnt is unprogrammed (0), the two workarounds conflict entirely (one
> forcing 5000, the other forcing 0), which would cause a WARN_ON and clamp
> cycle on every reset.
> 
> Additionally, if maxcnt tightly bounds the 5000ns minimum, the tick
> quantization rounding up below can push the delay time above maxcnt. On the
> next engine reset or resume, this triggers this xe_gt_WARN_ON() and forces a
> clamp, causing idledly to oscillate and violate the invariants of
> Wa_16023105232.
This condition is guarded by xe_gt_WARN_ON() inherited from the existing Wa_16023105232 hardening , it deliberately fires to surface an unexpected IDLE_WAIT_TIME == 0 register state rather than silently misprogramming the delay, and always resolves to a safe value (0, with the inhibit bit cleared) regardless of which workaround is active. On every platform this series targets, IDLE_WAIT_TIME is programmed to a non-zero value, so this path is not expected to be hit in practice. This condition is guarded by xe_gt_WARN_ON() inherited from the existing Wa_16023105232 hardening , it deliberately fires to surface an unexpected IDLE_WAIT_TIME == 0 register state rather than silently misprogramming the delay, and always resolves to a safe value (0, with the inhibit bit cleared) regardless of which workaround is active. On every platform this series targets, IDLE_WAIT_TIME is programmed to a non-zero value, so this path is not expected to be hit in practice.

> 
> > +			/* maxcnt may be 0 if IDLE_WAIT_TIME is
> unprogrammed. */
> > +			idledly = maxcnt ? maxcnt - 1 : 0;
> > +			clamped_below_maxcnt = true;
> > +			wa_applied = true;
> > +			/* inhibit_switch override to keep
> > +			 * semantics of Wa_16023105232
> > +			 */
> > +			if (inhibit_switch)
> > +				idledly_reg_val &=
> ~INHIBIT_SWITCH_UNTIL_PREEMPTED;
> > +		}
> > +
> > +		if (wa_applied) {
> > +			u32 idledly_ticks;
> > +
> > +			/*
> > +			 * Wa_16023105232 requires idledly < maxcnt, so floor
> > +			 * that clamp; otherwise round up to guarantee the
> > +			 * Wa_14025941587 minimum survives tick
> quantization.
> > +			 */
> > +			if (clamped_below_maxcnt)
> > +				idledly_ticks =
> DIV_ROUND_DOWN_ULL((u64)idledly * 1000,
> > +
> idledly_units_ps);
> > +			else
> > +				idledly_ticks =
> DIV_ROUND_UP_ULL((u64)idledly * 1000,
> > +
> idledly_units_ps);
>                                                                  ^^^^^^^^^^^^^^^^^^
> 
> [Severity: Medium]
> Does this ceiling division push the delay time above the maxcnt boundary?
> 
> When maxcnt is close to the 5000ns minimum (e.g. 5120ns), rounding up
> idledly to ticks produces a delay (e.g. 5417ns) that exceeds maxcnt, storing a
> value that will fail the Wa_16023105232 check on the next read.
> 
Rounding the 5 µs floor up to whole ticks could, in principle, land above maxcnt if maxcnt were close enough to the floor. In practice, on every platform this workaround is enabled for, IDLE_WAIT_TIME is programmed with enough margin above 5 µs that the two workarounds don't conflict

-Tilak

> > +
> > +			idledly_reg_val &= ~IDLE_DELAY;
> > +			idledly_reg_val |= REG_FIELD_PREP(IDLE_DELAY,
> idledly_ticks);
> 
> --
> Sashiko AI review · https://sashiko.dev/#/patchset/20260909161844.125147-1-
> tilak.tirumalesh.tangudu@intel.com?part=2

Re: [PATCH 2/2] drm/xe: Add wa_14025941587 to xe2, xe3 and xe3p platforms

[Belgaumkar, Vinay]

On 9/9/2026 9:18 AM, tilak.tirumalesh.tangudu@intel.com wrote:
> From: Tangudu Tilak Tirumalesh <tilak.tirumalesh.tangudu@intel.com>
>
> Avoid programming the IDLEDLY timer to less than 5 microseconds.
> Apply wa_14025941587 to Graphics Versions 20.01 to 35.11
> and Media Versions 13.01 to 35.03
>
> v2: Use xe_rtp_match_not_sriov_vf, move to local variable
>      Remove warn and other knits            - Matt R
>
> v3: Add verbose comment - Tejas
>
> v4: Restore IDLE_DLY register on engine reset.
>      Add it to GUC save-restore list. -Vivek
>
> v5: Extend WA to Media Versions 13.01 to 35.03 - Vinay
>
> v6: Avoid clearing inhibit switch - Bala
>      Refactor code accordingly by adding idle_reg_val.
>
> v7: Rebased with the divide-by-zero/overflow guards living in
>      a separate hardening patch.
>
> v8: Preserve the Wa_16023105232 floor (DIV_ROUND_DOWN_ULL) and the
>      maxcnt == 0 guard from the hardening patch. Round up
>      (DIV_ROUND_UP_ULL) the Wa_14025941587 minimum conversion instead,
>      so the tick-quantized delay cannot round back below 5 us.
>
> Assisted-by: GitHub_Copilot:claude-opus-4.8
> Signed-off-by: Tangudu Tilak Tirumalesh <tilak.tirumalesh.tangudu@intel.com>

LGTM,

Reviewed-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>

> ---
>   drivers/gpu/drm/xe/xe_guc_ads.c    |  2 +-
>   drivers/gpu/drm/xe/xe_hw_engine.c  | 69 ++++++++++++++++++++++++------
>   drivers/gpu/drm/xe/xe_wa_oob.rules |  2 +
>   3 files changed, 60 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
> index ff8eee3831aa..58a3f6293ce4 100644
> --- a/drivers/gpu/drm/xe/xe_guc_ads.c
> +++ b/drivers/gpu/drm/xe/xe_guc_ads.c
> @@ -864,7 +864,7 @@ static unsigned int guc_mmio_regset_write(struct xe_guc_ads *ads,
>   		}
>   	}
>   
> -	if (XE_GT_WA(hwe->gt, 16023105232))
> +	if (XE_GT_WA(hwe->gt, 16023105232) || XE_GT_WA(hwe->gt, 14025941587))
>   		guc_mmio_regset_write_one(ads, regset_map,
>   					  RING_IDLEDLY(hwe->mmio_base),
>   					  count++);
> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
> index c86890e09b55..37cd7fe38c2b 100644
> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
> @@ -588,33 +588,78 @@ static void hw_engine_init_early(struct xe_gt *gt, struct xe_hw_engine *hwe,
>   static void adjust_idledly(struct xe_hw_engine *hwe)
>   {
>   	struct xe_gt *gt = hwe->gt;
> -	u32 idledly, maxcnt;
> +	u32 idledly, idledly_reg_val, maxcnt;
>   	u32 idledly_units_ps = 8 * gt->info.timestamp_base;
>   	u32 maxcnt_units_ns = 640;
> -	bool inhibit_switch = 0;
> +	bool inhibit_switch = false;
> +	bool wa_applied = false;
> +	bool clamped_below_maxcnt = false;
> +
> +	if ((!IS_SRIOV_VF(gt_to_xe(hwe->gt)) && XE_GT_WA(gt, 16023105232)) ||
> +	    XE_GT_WA(gt, 14025941587)) {
> +		u32 mincnt_idledly_ns = 5000;
>   
> -	if (!IS_SRIOV_VF(gt_to_xe(hwe->gt)) && XE_GT_WA(gt, 16023105232)) {
>   		/* xe_gt_clock_init() zeroes timestamp_base on unknown crystal clock. */
>   		if (!idledly_units_ps) {
>   			xe_gt_warn(gt, "idledly WA skipped: timestamp_base is 0\n");
>   			return;
>   		}
>   
> -		idledly = xe_mmio_read32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base));
> +		idledly_reg_val = xe_mmio_read32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base));
>   		maxcnt = xe_mmio_read32(&gt->mmio, RING_PWRCTX_MAXCNT(hwe->mmio_base));
>   
> -		inhibit_switch = idledly & INHIBIT_SWITCH_UNTIL_PREEMPTED;
> -		idledly = REG_FIELD_GET(IDLE_DELAY, idledly);
> +		inhibit_switch = idledly_reg_val & INHIBIT_SWITCH_UNTIL_PREEMPTED;
> +		idledly = REG_FIELD_GET(IDLE_DELAY, idledly_reg_val);
>   		idledly = DIV_ROUND_CLOSEST_ULL((u64)idledly * idledly_units_ps, 1000);
>   		maxcnt = REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt);
>   		maxcnt *= maxcnt_units_ns;
>   
> -		if (xe_gt_WARN_ON(gt, idledly >= maxcnt || inhibit_switch)) {
> -			/* Floor below maxcnt; write 0 to still clear the inhibit bit. */
> -			idledly = maxcnt ?
> -				DIV_ROUND_DOWN_ULL((u64)(maxcnt - 1) * 1000,
> -						   idledly_units_ps) : 0;
> -			xe_mmio_write32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base), idledly);
> +		/*
> +		 * Wa_14025941587 is applied before Wa_16023105232, which has
> +		 * higher priority; the two are not expected to conflict.
> +		 */
> +		if (XE_GT_WA(gt, 14025941587) &&
> +		    idledly < mincnt_idledly_ns) {
> +			idledly = mincnt_idledly_ns;
> +			wa_applied = true;
> +		}
> +
> +		if (XE_GT_WA(gt, 16023105232) &&
> +		    xe_gt_WARN_ON(gt, idledly >= maxcnt || inhibit_switch)) {
> +			/* maxcnt may be 0 if IDLE_WAIT_TIME is unprogrammed. */
> +			idledly = maxcnt ? maxcnt - 1 : 0;
> +			clamped_below_maxcnt = true;
> +			wa_applied = true;
> +			/* inhibit_switch override to keep
> +			 * semantics of Wa_16023105232
> +			 */
> +			if (inhibit_switch)
> +				idledly_reg_val &= ~INHIBIT_SWITCH_UNTIL_PREEMPTED;
> +		}
> +
> +		if (wa_applied) {
> +			u32 idledly_ticks;
> +
> +			/*
> +			 * Wa_16023105232 requires idledly < maxcnt, so floor
> +			 * that clamp; otherwise round up to guarantee the
> +			 * Wa_14025941587 minimum survives tick quantization.
> +			 */
> +			if (clamped_below_maxcnt)
> +				idledly_ticks = DIV_ROUND_DOWN_ULL((u64)idledly * 1000,
> +								   idledly_units_ps);
> +			else
> +				idledly_ticks = DIV_ROUND_UP_ULL((u64)idledly * 1000,
> +								 idledly_units_ps);
> +
> +			idledly_reg_val &= ~IDLE_DELAY;
> +			idledly_reg_val |= REG_FIELD_PREP(IDLE_DELAY, idledly_ticks);
> +			xe_gt_dbg(gt, "idledly %s: set %u max=%u inh=%u ts=%u\n",
> +				  hwe->name, idledly, maxcnt,
> +				  !!inhibit_switch, gt->info.timestamp_base);
> +			xe_mmio_write32(&gt->mmio,
> +					RING_IDLEDLY(hwe->mmio_base),
> +					idledly_reg_val);
>   		}
>   	}
>   }
> diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
> index dd69ad07f7a9..3001155f8d09 100644
> --- a/drivers/gpu/drm/xe/xe_wa_oob.rules
> +++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
> @@ -72,3 +72,5 @@
>   16029897822	MEDIA_VERSION(3500)
>   		GRAPHICS_VERSION(3510)
>   14027054324	GRAPHICS_VERSION(3511)
> +14025941587	GRAPHICS_VERSION_RANGE(2001, 3511), FUNC(xe_rtp_match_not_sriov_vf)
> +		MEDIA_VERSION_RANGE(1301, 3503), FUNC(xe_rtp_match_not_sriov_vf)

✓ CI.KUnit: success for drm/xe: Add wa_14025941587 to xe2, xe3 and xe3p platforms (rev9)

[Patchwork]

== Series Details ==

Series: drm/xe: Add wa_14025941587 to xe2, xe3 and xe3p platforms (rev9)
URL   : https://patchwork.freedesktop.org/series/167706/
State : success

== Summary ==

+ trap cleanup EXIT
+ kunitconfigs=('/kernel/drivers/gpu/tests/.kunitconfig' '/kernel/drivers/gpu/drm/xe/.kunitconfig' '/kernel/drivers/gpu/drm/tests/.kunitconfig' '/kernel/drivers/gpu/drm/ttm/tests/.kunitconfig' '/kernel/drivers/dma-buf/.kunitconfig')
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/tests/.kunitconfig
[17:04:12] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[17:04:17] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[17:04:37] Starting KUnit Kernel (1/1)...
[17:04:37] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[17:04:37] ============= refcount_interrupt (4 subtests) ==============
[17:04:37] [PASSED] test_single_irq_change
[17:04:37] [PASSED] test_nested_irq_change
[17:04:37] [PASSED] test_multiple_irq_change
[17:04:37] [PASSED] test_irq_save
[17:04:37] =============== [PASSED] refcount_interrupt ================
[17:04:37] ================= gpu_buddy (14 subtests) ==================
[17:04:37] [PASSED] gpu_test_buddy_alloc_limit
[17:04:37] [PASSED] gpu_test_buddy_alloc_optimistic
[17:04:37] [PASSED] gpu_test_buddy_alloc_pessimistic
[17:04:37] [PASSED] gpu_test_buddy_alloc_pathological
[17:04:37] [PASSED] gpu_test_buddy_alloc_contiguous
[17:04:37] [PASSED] gpu_test_buddy_alloc_clear
[17:04:37] [PASSED] gpu_test_buddy_alloc_range
[17:04:37] [PASSED] gpu_test_buddy_alloc_range_bias
[17:04:38] [PASSED] gpu_test_buddy_fragmentation_performance
[17:04:39] [PASSED] gpu_test_buddy_dirty_tracker_performance
[17:04:39] [PASSED] gpu_test_buddy_alloc_exceeds_max_order
[17:04:39] [PASSED] gpu_test_buddy_offset_aligned_allocation
[17:04:39] [PASSED] gpu_test_buddy_subtree_offset_alignment_stress
[17:04:39] [PASSED] gpu_test_buddy_addr_to_block
[17:04:39] ==================== [PASSED] gpu_buddy ====================
[17:04:39] ============================================================
[17:04:39] Testing complete. Ran 18 tests: passed: 18
[17:04:39] Elapsed time: 26.674s total, 4.400s configuring, 20.357s building, 1.873s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/xe/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[17:04:39] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[17:04:41] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[17:05:15] Starting KUnit Kernel (1/1)...
[17:05:15] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[17:05:15] ============= refcount_interrupt (4 subtests) ==============
[17:05:15] [PASSED] test_single_irq_change
[17:05:15] [PASSED] test_nested_irq_change
[17:05:15] [PASSED] test_multiple_irq_change
[17:05:15] [PASSED] test_irq_save
[17:05:15] =============== [PASSED] refcount_interrupt ================
[17:05:15] ================== guc_buf (11 subtests) ===================
[17:05:15] [PASSED] test_smallest
[17:05:15] [PASSED] test_largest
[17:05:15] [PASSED] test_granular
[17:05:15] [PASSED] test_unique
[17:05:15] [PASSED] test_overlap
[17:05:15] [PASSED] test_reusable
[17:05:15] [PASSED] test_too_big
[17:05:15] [PASSED] test_flush
[17:05:15] [PASSED] test_lookup
[17:05:15] [PASSED] test_data
[17:05:15] [PASSED] test_class
[17:05:15] ===================== [PASSED] guc_buf =====================
[17:05:15] =================== guc_dbm (7 subtests) ===================
[17:05:15] [PASSED] test_empty
[17:05:15] [PASSED] test_default
[17:05:15] ======================== test_size  ========================
[17:05:15] [PASSED] 4
[17:05:15] [PASSED] 8
[17:05:15] [PASSED] 32
[17:05:15] [PASSED] 256
[17:05:15] ==================== [PASSED] test_size ====================
[17:05:15] ======================= test_reuse  ========================
[17:05:15] [PASSED] 4
[17:05:15] [PASSED] 8
[17:05:15] [PASSED] 32
[17:05:15] [PASSED] 256
[17:05:15] =================== [PASSED] test_reuse ====================
[17:05:15] =================== test_range_overlap  ====================
[17:05:15] [PASSED] 4
[17:05:15] [PASSED] 8
[17:05:15] [PASSED] 32
[17:05:15] [PASSED] 256
[17:05:15] =============== [PASSED] test_range_overlap ================
[17:05:15] =================== test_range_compact  ====================
[17:05:15] [PASSED] 4
[17:05:15] [PASSED] 8
[17:05:15] [PASSED] 32
[17:05:15] [PASSED] 256
[17:05:15] =============== [PASSED] test_range_compact ================
[17:05:15] ==================== test_range_spare  =====================
[17:05:15] [PASSED] 4
[17:05:15] [PASSED] 8
[17:05:15] [PASSED] 32
[17:05:15] [PASSED] 256
[17:05:15] ================ [PASSED] test_range_spare =================
[17:05:15] ===================== [PASSED] guc_dbm =====================
[17:05:15] =================== guc_idm (6 subtests) ===================
[17:05:15] [PASSED] bad_init
[17:05:15] [PASSED] no_init
[17:05:15] [PASSED] init_fini
[17:05:15] [PASSED] check_used
[17:05:15] [PASSED] check_quota
[17:05:15] [PASSED] check_all
[17:05:15] ===================== [PASSED] guc_idm =====================
[17:05:15] =============== guc_klv_helpers (9 subtests) ===============
[17:05:15] [PASSED] test_count
[17:05:15] [PASSED] test_encode_u32
[17:05:15] [PASSED] test_encode_u64
[17:05:15] [PASSED] test_encode_string
[17:05:15] [PASSED] test_encode_object_raw
[17:05:15] [PASSED] test_encode_object_klv
[17:05:15] [PASSED] test_encode_object_nested
[17:05:15] [PASSED] test_encode_object_basic
[17:05:15] [PASSED] test_print
[17:05:15] ================= [PASSED] guc_klv_helpers =================
[17:05:15] =================== xe_log (4 subtests) ====================
[17:05:15] [PASSED] demo_cper
[17:05:15] [PASSED] demo_dmesg
[17:05:15] ======================= test_dmesg  ========================
[17:05:15] [PASSED] test_fatal
[17:05:15] [PASSED] test_fatal_tile
[17:05:15] [PASSED] test_fatal_gt
[17:05:15] [PASSED] test_fatal_comp
[17:05:15] [PASSED] test_fatal_comp_tile
[17:05:15] [PASSED] test_fatal_comp_gt
[17:05:15] [PASSED] test_fatal_all
[17:05:15] [PASSED] test_recoverable
[17:05:15] [PASSED] test_recoverable_tile
[17:05:15] [PASSED] test_recoverable_gt
[17:05:15] [PASSED] test_recoverable_comp
[17:05:15] [PASSED] test_recoverable_comp_tile
[17:05:15] [PASSED] test_recoverable_comp_gt
[17:05:15] [PASSED] test_recoverable_all
[17:05:15] [PASSED] test_info
[17:05:15] [PASSED] test_info_tile
[17:05:15] [PASSED] test_info_gt
[17:05:15] [PASSED] test_info_err
[17:05:15] [PASSED] test_info_comp
[17:05:15] [PASSED] test_info_comp_tile
[17:05:15] [PASSED] test_info_comp_gt
[17:05:15] [PASSED] test_info_all
[17:05:15] [PASSED] test_hw_fatal
[17:05:15] [PASSED] test_hw_recoverable
[17:05:15] [PASSED] test_hw_corrected
[17:05:15] [PASSED] test_hw_informational
[17:05:15] =================== [PASSED] test_dmesg ====================
[17:05:15] ====================== test_invalid  =======================
[17:05:15] [SKIPPED] no-component no-location no-warn (requires CONFIG_DRM_XE_DEBUG)
[17:05:15] [SKIPPED] reserved location (requires CONFIG_DRM_XE_DEBUG)
[17:05:15] [SKIPPED] unknown location (requires CONFIG_DRM_XE_DEBUG)
[17:05:15] [SKIPPED] nonzero-device-id location (requires CONFIG_DRM_XE_DEBUG)
[17:05:15] [SKIPPED] invalid-tile-id location (requires CONFIG_DRM_XE_DEBUG)
[17:05:15] [SKIPPED] invalid-gt-id location (requires CONFIG_DRM_XE_DEBUG)
[17:05:15] [SKIPPED] unknown component class (requires CONFIG_DRM_XE_DEBUG)
[17:05:15] [SKIPPED] unknown system component (requires CONFIG_DRM_XE_DEBUG)
[17:05:15] [SKIPPED] unknown hardware component (requires CONFIG_DRM_XE_DEBUG)
[17:05:15] [SKIPPED] unknown component and location (requires CONFIG_DRM_XE_DEBUG)
[17:05:15] ================== [SKIPPED] test_invalid ==================
[17:05:15] ===================== [PASSED] xe_log ======================
[17:05:15] ================== no_relay (3 subtests) ===================
[17:05:15] [PASSED] xe_drops_guc2pf_if_not_ready
[17:05:15] [PASSED] xe_drops_guc2vf_if_not_ready
[17:05:15] [PASSED] xe_rejects_send_if_not_ready
[17:05:15] ==================== [PASSED] no_relay =====================
[17:05:15] ================== pf_relay (14 subtests) ==================
[17:05:15] [PASSED] pf_rejects_guc2pf_too_short
[17:05:15] [PASSED] pf_rejects_guc2pf_too_long
[17:05:15] [PASSED] pf_rejects_guc2pf_no_payload
[17:05:15] [PASSED] pf_fails_no_payload
[17:05:15] [PASSED] pf_fails_bad_origin
[17:05:15] [PASSED] pf_fails_bad_type
[17:05:15] [PASSED] pf_txn_reports_error
[17:05:15] [PASSED] pf_txn_sends_pf2guc
[17:05:15] [PASSED] pf_sends_pf2guc
[17:05:15] [SKIPPED] pf_loopback_nop (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[17:05:15] [SKIPPED] pf_loopback_echo (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[17:05:15] [SKIPPED] pf_loopback_fail (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[17:05:15] [SKIPPED] pf_loopback_busy (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[17:05:15] [SKIPPED] pf_loopback_retry (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[17:05:15] ==================== [PASSED] pf_relay =====================
[17:05:15] ================== vf_relay (3 subtests) ===================
[17:05:15] [PASSED] vf_rejects_guc2vf_too_short
[17:05:15] [PASSED] vf_rejects_guc2vf_too_long
[17:05:15] [PASSED] vf_rejects_guc2vf_no_payload
[17:05:15] ==================== [PASSED] vf_relay =====================
[17:05:15] ================ pf_gt_config (9 subtests) =================
[17:05:15] [PASSED] fair_contexts_1vf
[17:05:15] [PASSED] fair_doorbells_1vf
[17:05:15] [PASSED] fair_ggtt_1vf
[17:05:15] ====================== fair_vram_1vf  ======================
[17:05:15] [PASSED] 3.50 GiB
[17:05:15] [PASSED] 11.5 GiB
[17:05:15] [PASSED] 15.5 GiB
[17:05:15] [PASSED] 31.5 GiB
[17:05:15] [PASSED] 63.5 GiB
[17:05:15] [PASSED] 1.91 GiB
[17:05:15] ================== [PASSED] fair_vram_1vf ==================
[17:05:15] ================ fair_vram_1vf_admin_only  =================
[17:05:15] [PASSED] 3.50 GiB
[17:05:15] [PASSED] 11.5 GiB
[17:05:15] [PASSED] 15.5 GiB
[17:05:15] [PASSED] 31.5 GiB
[17:05:15] [PASSED] 63.5 GiB
[17:05:15] [PASSED] 1.91 GiB
[17:05:15] ============ [PASSED] fair_vram_1vf_admin_only =============
[17:05:15] ====================== fair_contexts  ======================
[17:05:15] [PASSED] 1 VF
[17:05:15] [PASSED] 2 VFs
[17:05:15] [PASSED] 3 VFs
[17:05:15] [PASSED] 4 VFs
[17:05:15] [PASSED] 5 VFs
[17:05:15] [PASSED] 6 VFs
[17:05:15] [PASSED] 7 VFs
[17:05:15] [PASSED] 8 VFs
[17:05:15] [PASSED] 9 VFs
[17:05:15] [PASSED] 10 VFs
[17:05:15] [PASSED] 11 VFs
[17:05:15] [PASSED] 12 VFs
[17:05:15] [PASSED] 13 VFs
[17:05:15] [PASSED] 14 VFs
[17:05:15] [PASSED] 15 VFs
[17:05:15] [PASSED] 16 VFs
[17:05:15] [PASSED] 17 VFs
[17:05:15] [PASSED] 18 VFs
[17:05:15] [PASSED] 19 VFs
[17:05:15] [PASSED] 20 VFs
[17:05:15] [PASSED] 21 VFs
[17:05:15] [PASSED] 22 VFs
[17:05:15] [PASSED] 23 VFs
[17:05:15] [PASSED] 24 VFs
[17:05:15] [PASSED] 25 VFs
[17:05:15] [PASSED] 26 VFs
[17:05:15] [PASSED] 27 VFs
[17:05:15] [PASSED] 28 VFs
[17:05:15] [PASSED] 29 VFs
[17:05:15] [PASSED] 30 VFs
[17:05:15] [PASSED] 31 VFs
[17:05:15] [PASSED] 32 VFs
[17:05:15] [PASSED] 33 VFs
[17:05:15] [PASSED] 34 VFs
[17:05:15] [PASSED] 35 VFs
[17:05:15] [PASSED] 36 VFs
[17:05:15] [PASSED] 37 VFs
[17:05:15] [PASSED] 38 VFs
[17:05:15] [PASSED] 39 VFs
[17:05:15] [PASSED] 40 VFs
[17:05:15] [PASSED] 41 VFs
[17:05:15] [PASSED] 42 VFs
[17:05:15] [PASSED] 43 VFs
[17:05:15] [PASSED] 44 VFs
[17:05:15] [PASSED] 45 VFs
[17:05:15] [PASSED] 46 VFs
[17:05:15] [PASSED] 47 VFs
[17:05:15] [PASSED] 48 VFs
[17:05:15] [PASSED] 49 VFs
[17:05:15] [PASSED] 50 VFs
[17:05:15] [PASSED] 51 VFs
[17:05:15] [PASSED] 52 VFs
[17:05:15] [PASSED] 53 VFs
[17:05:15] [PASSED] 54 VFs
[17:05:15] [PASSED] 55 VFs
[17:05:15] [PASSED] 56 VFs
[17:05:15] [PASSED] 57 VFs
[17:05:15] [PASSED] 58 VFs
[17:05:15] [PASSED] 59 VFs
[17:05:15] [PASSED] 60 VFs
[17:05:15] [PASSED] 61 VFs
[17:05:15] [PASSED] 62 VFs
[17:05:15] [PASSED] 63 VFs
[17:05:15] ================== [PASSED] fair_contexts ==================
[17:05:15] ===================== fair_doorbells  ======================
[17:05:15] [PASSED] 1 VF
[17:05:15] [PASSED] 2 VFs
[17:05:15] [PASSED] 3 VFs
[17:05:15] [PASSED] 4 VFs
[17:05:15] [PASSED] 5 VFs
[17:05:15] [PASSED] 6 VFs
[17:05:15] [PASSED] 7 VFs
[17:05:15] [PASSED] 8 VFs
[17:05:15] [PASSED] 9 VFs
[17:05:15] [PASSED] 10 VFs
[17:05:15] [PASSED] 11 VFs
[17:05:15] [PASSED] 12 VFs
[17:05:15] [PASSED] 13 VFs
[17:05:15] [PASSED] 14 VFs
[17:05:15] [PASSED] 15 VFs
[17:05:15] [PASSED] 16 VFs
[17:05:15] [PASSED] 17 VFs
[17:05:15] [PASSED] 18 VFs
[17:05:15] [PASSED] 19 VFs
[17:05:15] [PASSED] 20 VFs
[17:05:15] [PASSED] 21 VFs
[17:05:15] [PASSED] 22 VFs
[17:05:15] [PASSED] 23 VFs
[17:05:15] [PASSED] 24 VFs
[17:05:15] [PASSED] 25 VFs
[17:05:15] [PASSED] 26 VFs
[17:05:15] [PASSED] 27 VFs
[17:05:15] [PASSED] 28 VFs
[17:05:15] [PASSED] 29 VFs
[17:05:15] [PASSED] 30 VFs
[17:05:15] [PASSED] 31 VFs
[17:05:15] [PASSED] 32 VFs
[17:05:15] [PASSED] 33 VFs
[17:05:15] [PASSED] 34 VFs
[17:05:15] [PASSED] 35 VFs
[17:05:15] [PASSED] 36 VFs
[17:05:15] [PASSED] 37 VFs
[17:05:15] [PASSED] 38 VFs
[17:05:15] [PASSED] 39 VFs
[17:05:15] [PASSED] 40 VFs
[17:05:15] [PASSED] 41 VFs
[17:05:15] [PASSED] 42 VFs
[17:05:15] [PASSED] 43 VFs
[17:05:15] [PASSED] 44 VFs
[17:05:15] [PASSED] 45 VFs
[17:05:15] [PASSED] 46 VFs
[17:05:15] [PASSED] 47 VFs
[17:05:15] [PASSED] 48 VFs
[17:05:15] [PASSED] 49 VFs
[17:05:15] [PASSED] 50 VFs
[17:05:15] [PASSED] 51 VFs
[17:05:15] [PASSED] 52 VFs
[17:05:15] [PASSED] 53 VFs
[17:05:15] [PASSED] 54 VFs
[17:05:15] [PASSED] 55 VFs
[17:05:15] [PASSED] 56 VFs
[17:05:15] [PASSED] 57 VFs
[17:05:15] [PASSED] 58 VFs
[17:05:15] [PASSED] 59 VFs
[17:05:15] [PASSED] 60 VFs
[17:05:15] [PASSED] 61 VFs
[17:05:15] [PASSED] 62 VFs
[17:05:15] [PASSED] 63 VFs
[17:05:15] ================= [PASSED] fair_doorbells ==================
[17:05:15] ======================== fair_ggtt  ========================
[17:05:15] [PASSED] 1 VF
[17:05:15] [PASSED] 2 VFs
[17:05:15] [PASSED] 3 VFs
[17:05:15] [PASSED] 4 VFs
[17:05:15] [PASSED] 5 VFs
[17:05:15] [PASSED] 6 VFs
[17:05:15] [PASSED] 7 VFs
[17:05:15] [PASSED] 8 VFs
[17:05:15] [PASSED] 9 VFs
[17:05:15] [PASSED] 10 VFs
[17:05:15] [PASSED] 11 VFs
[17:05:15] [PASSED] 12 VFs
[17:05:15] [PASSED] 13 VFs
[17:05:15] [PASSED] 14 VFs
[17:05:15] [PASSED] 15 VFs
[17:05:15] [PASSED] 16 VFs
[17:05:15] [PASSED] 17 VFs
[17:05:15] [PASSED] 18 VFs
[17:05:15] [PASSED] 19 VFs
[17:05:15] [PASSED] 20 VFs
[17:05:15] [PASSED] 21 VFs
[17:05:15] [PASSED] 22 VFs
[17:05:15] [PASSED] 23 VFs
[17:05:15] [PASSED] 24 VFs
[17:05:15] [PASSED] 25 VFs
[17:05:15] [PASSED] 26 VFs
[17:05:15] [PASSED] 27 VFs
[17:05:15] [PASSED] 28 VFs
[17:05:15] [PASSED] 29 VFs
[17:05:15] [PASSED] 30 VFs
[17:05:15] [PASSED] 31 VFs
[17:05:15] [PASSED] 32 VFs
[17:05:15] [PASSED] 33 VFs
[17:05:15] [PASSED] 34 VFs
[17:05:15] [PASSED] 35 VFs
[17:05:15] [PASSED] 36 VFs
[17:05:15] [PASSED] 37 VFs
[17:05:15] [PASSED] 38 VFs
[17:05:15] [PASSED] 39 VFs
[17:05:15] [PASSED] 40 VFs
[17:05:15] [PASSED] 41 VFs
[17:05:15] [PASSED] 42 VFs
[17:05:15] [PASSED] 43 VFs
[17:05:15] [PASSED] 44 VFs
[17:05:15] [PASSED] 45 VFs
[17:05:15] [PASSED] 46 VFs
[17:05:15] [PASSED] 47 VFs
[17:05:15] [PASSED] 48 VFs
[17:05:15] [PASSED] 49 VFs
[17:05:15] [PASSED] 50 VFs
[17:05:15] [PASSED] 51 VFs
[17:05:15] [PASSED] 52 VFs
[17:05:15] [PASSED] 53 VFs
[17:05:15] [PASSED] 54 VFs
[17:05:15] [PASSED] 55 VFs
[17:05:15] [PASSED] 56 VFs
[17:05:15] [PASSED] 57 VFs
[17:05:15] [PASSED] 58 VFs
[17:05:15] [PASSED] 59 VFs
[17:05:15] [PASSED] 60 VFs
[17:05:15] [PASSED] 61 VFs
[17:05:15] [PASSED] 62 VFs
[17:05:15] [PASSED] 63 VFs
[17:05:15] ==================== [PASSED] fair_ggtt ====================
[17:05:15] ======================== fair_vram  ========================
[17:05:15] [PASSED] 1 VF
[17:05:15] [PASSED] 2 VFs
[17:05:15] [PASSED] 3 VFs
[17:05:15] [PASSED] 4 VFs
[17:05:15] [PASSED] 5 VFs
[17:05:15] [PASSED] 6 VFs
[17:05:15] [PASSED] 7 VFs
[17:05:15] [PASSED] 8 VFs
[17:05:15] [PASSED] 9 VFs
[17:05:15] [PASSED] 10 VFs
[17:05:15] [PASSED] 11 VFs
[17:05:15] [PASSED] 12 VFs
[17:05:15] [PASSED] 13 VFs
[17:05:15] [PASSED] 14 VFs
[17:05:15] [PASSED] 15 VFs
[17:05:15] [PASSED] 16 VFs
[17:05:15] [PASSED] 17 VFs
[17:05:15] [PASSED] 18 VFs
[17:05:15] [PASSED] 19 VFs
[17:05:15] [PASSED] 20 VFs
[17:05:15] [PASSED] 21 VFs
[17:05:15] [PASSED] 22 VFs
[17:05:15] [PASSED] 23 VFs
[17:05:15] [PASSED] 24 VFs
[17:05:15] [PASSED] 25 VFs
[17:05:15] [PASSED] 26 VFs
[17:05:15] [PASSED] 27 VFs
[17:05:15] [PASSED] 28 VFs
[17:05:15] [PASSED] 29 VFs
[17:05:15] [PASSED] 30 VFs
[17:05:15] [PASSED] 31 VFs
[17:05:15] [PASSED] 32 VFs
[17:05:15] [PASSED] 33 VFs
[17:05:15] [PASSED] 34 VFs
[17:05:15] [PASSED] 35 VFs
[17:05:15] [PASSED] 36 VFs
[17:05:15] [PASSED] 37 VFs
[17:05:15] [PASSED] 38 VFs
[17:05:15] [PASSED] 39 VFs
[17:05:15] [PASSED] 40 VFs
[17:05:15] [PASSED] 41 VFs
[17:05:15] [PASSED] 42 VFs
[17:05:15] [PASSED] 43 VFs
[17:05:15] [PASSED] 44 VFs
[17:05:15] [PASSED] 45 VFs
[17:05:15] [PASSED] 46 VFs
[17:05:15] [PASSED] 47 VFs
[17:05:15] [PASSED] 48 VFs
[17:05:15] [PASSED] 49 VFs
[17:05:15] [PASSED] 50 VFs
[17:05:15] [PASSED] 51 VFs
[17:05:15] [PASSED] 52 VFs
[17:05:15] [PASSED] 53 VFs
[17:05:15] [PASSED] 54 VFs
[17:05:15] [PASSED] 55 VFs
[17:05:15] [PASSED] 56 VFs
[17:05:15] [PASSED] 57 VFs
[17:05:15] [PASSED] 58 VFs
[17:05:15] [PASSED] 59 VFs
[17:05:15] [PASSED] 60 VFs
[17:05:15] [PASSED] 61 VFs
[17:05:15] [PASSED] 62 VFs
[17:05:15] [PASSED] 63 VFs
[17:05:15] ==================== [PASSED] fair_vram ====================
[17:05:15] ================== [PASSED] pf_gt_config ===================
[17:05:15] ===================== lmtt (1 subtest) =====================
[17:05:15] ======================== test_ops  =========================
[17:05:15] [PASSED] 2-level
[17:05:15] [PASSED] multi-level
[17:05:15] ==================== [PASSED] test_ops =====================
[17:05:15] ====================== [PASSED] lmtt =======================
[17:05:15] ================= sriov_packet (1 subtest) =================
[17:05:15] [PASSED] test_descriptor_init
[17:05:15] ================== [PASSED] sriov_packet ===================
[17:05:15] ================= pf_service (11 subtests) =================
[17:05:15] [PASSED] pf_negotiate_any
[17:05:15] [PASSED] pf_negotiate_base_match
[17:05:15] [PASSED] pf_negotiate_base_newer
[17:05:15] [PASSED] pf_negotiate_base_next
[17:05:15] [SKIPPED] pf_negotiate_base_older (no older minor)
[17:05:15] [PASSED] pf_negotiate_base_prev
[17:05:15] [PASSED] pf_negotiate_latest_match
[17:05:15] [PASSED] pf_negotiate_latest_newer
[17:05:15] [PASSED] pf_negotiate_latest_next
[17:05:15] [SKIPPED] pf_negotiate_latest_older (no older minor)
[17:05:15] [SKIPPED] pf_negotiate_latest_prev (no prev major)
[17:05:15] =================== [PASSED] pf_service ====================
[17:05:15] ================= xe_guc_g2g (2 subtests) ==================
[17:05:15] ============== xe_live_guc_g2g_kunit_default  ==============
[17:05:15] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[17:05:15] ============== xe_live_guc_g2g_kunit_allmem  ===============
[17:05:15] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[17:05:15] =================== [SKIPPED] xe_guc_g2g ===================
[17:05:15] =================== xe_mocs (2 subtests) ===================
[17:05:15] ================ xe_live_mocs_kernel_kunit  ================
[17:05:15] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[17:05:15] ================ xe_live_mocs_reset_kunit  =================
[17:05:15] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[17:05:15] ==================== [SKIPPED] xe_mocs =====================
[17:05:15] ================= xe_migrate (2 subtests) ==================
[17:05:15] ================= xe_migrate_sanity_kunit  =================
[17:05:15] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[17:05:15] ================== xe_validate_ccs_kunit  ==================
[17:05:15] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[17:05:15] =================== [SKIPPED] xe_migrate ===================
[17:05:15] ================== xe_dma_buf (1 subtest) ==================
[17:05:15] ==================== xe_dma_buf_kunit  =====================
[17:05:15] ================ [SKIPPED] xe_dma_buf_kunit ================
[17:05:15] =================== [SKIPPED] xe_dma_buf ===================
[17:05:15] ================= xe_bo_shrink (1 subtest) =================
[17:05:15] =================== xe_bo_shrink_kunit  ====================
[17:05:15] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[17:05:15] ================== [SKIPPED] xe_bo_shrink ==================
[17:05:15] ==================== xe_bo (2 subtests) ====================
[17:05:15] ================== xe_ccs_migrate_kunit  ===================
[17:05:15] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[17:05:15] ==================== xe_bo_evict_kunit  ====================
[17:05:15] =============== [SKIPPED] xe_bo_evict_kunit ================
[17:05:15] ===================== [SKIPPED] xe_bo ======================
[17:05:15] =================== xe_any (9 subtests) ====================
[17:05:15] [PASSED] test_to_xe
[17:05:15] [PASSED] test_to_dev
[17:05:15] [PASSED] test_to_pdev
[17:05:15] [PASSED] test_to_drm
[17:05:15] [PASSED] test_if_pdev
[17:05:15] [PASSED] test_if_xe
[17:05:15] [PASSED] test_if_tile
[17:05:15] [PASSED] test_if_gt
[17:05:15] [PASSED] test_to_id
[17:05:15] ===================== [PASSED] xe_any ======================
[17:05:15] ==================== args (13 subtests) ====================
[17:05:15] [PASSED] count_args_test
[17:05:15] [PASSED] call_args_example
[17:05:15] [PASSED] call_args_test
[17:05:15] [PASSED] drop_first_arg_example
[17:05:15] [PASSED] drop_first_arg_test
[17:05:15] [PASSED] first_arg_example
[17:05:15] [PASSED] first_arg_test
[17:05:15] [PASSED] last_arg_example
[17:05:15] [PASSED] last_arg_test
[17:05:15] [PASSED] pick_arg_example
[17:05:15] [PASSED] if_args_example
[17:05:15] [PASSED] if_args_test
[17:05:15] [PASSED] sep_comma_example
[17:05:15] ====================== [PASSED] args =======================
[17:05:15] =================== xe_pci (3 subtests) ====================
[17:05:15] ==================== check_graphics_ip  ====================
[17:05:15] [PASSED] 12.00 Xe_LP
[17:05:15] [PASSED] 12.10 Xe_LP+
[17:05:15] [PASSED] 12.55 Xe_HPG
[17:05:15] [PASSED] 12.60 Xe_HPC
[17:05:15] [PASSED] 12.70 Xe_LPG
[17:05:15] [PASSED] 12.71 Xe_LPG
[17:05:15] [PASSED] 12.74 Xe_LPG+
[17:05:15] [PASSED] 20.01 Xe2_HPG
[17:05:15] [PASSED] 20.02 Xe2_HPG
[17:05:15] [PASSED] 20.04 Xe2_LPG
[17:05:15] [PASSED] 30.00 Xe3_LPG
[17:05:15] [PASSED] 30.01 Xe3_LPG
[17:05:15] [PASSED] 30.03 Xe3_LPG
[17:05:15] [PASSED] 30.04 Xe3_LPG
[17:05:15] [PASSED] 30.05 Xe3_LPG
[17:05:15] [PASSED] 35.10 Xe3p_LPG
[17:05:15] [PASSED] 35.11 Xe3p_XPC
[17:05:15] ================ [PASSED] check_graphics_ip ================
[17:05:15] ===================== check_media_ip  ======================
[17:05:15] [PASSED] 12.00 Xe_M
[17:05:15] [PASSED] 12.55 Xe_HPM
[17:05:15] [PASSED] 13.00 Xe_LPM+
[17:05:15] [PASSED] 13.01 Xe2_HPM
[17:05:15] [PASSED] 20.00 Xe2_LPM
[17:05:15] [PASSED] 30.00 Xe3_LPM
[17:05:15] [PASSED] 30.02 Xe3_LPM
[17:05:15] [PASSED] 35.00 Xe3p_LPM
[17:05:15] [PASSED] 35.03 Xe3p_HPM
[17:05:15] ================= [PASSED] check_media_ip ==================
[17:05:15] =================== check_platform_desc  ===================
[17:05:15] [PASSED] 0x9A60 (TIGERLAKE)
[17:05:15] [PASSED] 0x9A68 (TIGERLAKE)
[17:05:15] [PASSED] 0x9A70 (TIGERLAKE)
[17:05:15] [PASSED] 0x9A40 (TIGERLAKE)
[17:05:15] [PASSED] 0x9A49 (TIGERLAKE)
[17:05:15] [PASSED] 0x9A59 (TIGERLAKE)
[17:05:15] [PASSED] 0x9A78 (TIGERLAKE)
[17:05:15] [PASSED] 0x9AC0 (TIGERLAKE)
[17:05:15] [PASSED] 0x9AC9 (TIGERLAKE)
[17:05:15] [PASSED] 0x9AD9 (TIGERLAKE)
[17:05:15] [PASSED] 0x9AF8 (TIGERLAKE)
[17:05:15] [PASSED] 0x4C80 (ROCKETLAKE)
[17:05:15] [PASSED] 0x4C8A (ROCKETLAKE)
[17:05:15] [PASSED] 0x4C8B (ROCKETLAKE)
[17:05:15] [PASSED] 0x4C8C (ROCKETLAKE)
[17:05:15] [PASSED] 0x4C90 (ROCKETLAKE)
[17:05:15] [PASSED] 0x4C9A (ROCKETLAKE)
[17:05:15] [PASSED] 0x4680 (ALDERLAKE_S)
[17:05:15] [PASSED] 0x4682 (ALDERLAKE_S)
[17:05:15] [PASSED] 0x4688 (ALDERLAKE_S)
[17:05:15] [PASSED] 0x468A (ALDERLAKE_S)
[17:05:15] [PASSED] 0x468B (ALDERLAKE_S)
[17:05:15] [PASSED] 0x4690 (ALDERLAKE_S)
[17:05:15] [PASSED] 0x4692 (ALDERLAKE_S)
[17:05:15] [PASSED] 0x4693 (ALDERLAKE_S)
[17:05:15] [PASSED] 0x46A0 (ALDERLAKE_P)
[17:05:15] [PASSED] 0x46A1 (ALDERLAKE_P)
[17:05:15] [PASSED] 0x46A2 (ALDERLAKE_P)
[17:05:15] [PASSED] 0x46A3 (ALDERLAKE_P)
[17:05:15] [PASSED] 0x46A6 (ALDERLAKE_P)
[17:05:15] [PASSED] 0x46A8 (ALDERLAKE_P)
[17:05:15] [PASSED] 0x46AA (ALDERLAKE_P)
[17:05:15] [PASSED] 0x462A (ALDERLAKE_P)
[17:05:15] [PASSED] 0x4626 (ALDERLAKE_P)
[17:05:15] [PASSED] 0x4628 (ALDERLAKE_P)
[17:05:15] [PASSED] 0x46B0 (ALDERLAKE_P)
[17:05:15] [PASSED] 0x46B1 (ALDERLAKE_P)
[17:05:15] [PASSED] 0x46B2 (ALDERLAKE_P)
[17:05:15] [PASSED] 0x46B3 (ALDERLAKE_P)
[17:05:15] [PASSED] 0x46C0 (ALDERLAKE_P)
[17:05:15] [PASSED] 0x46C1 (ALDERLAKE_P)
[17:05:15] [PASSED] 0x46C2 (ALDERLAKE_P)
[17:05:15] [PASSED] 0x46C3 (ALDERLAKE_P)
[17:05:15] [PASSED] 0x46D0 (ALDERLAKE_N)
[17:05:15] [PASSED] 0x46D1 (ALDERLAKE_N)
[17:05:15] [PASSED] 0x46D2 (ALDERLAKE_N)
[17:05:15] [PASSED] 0x46D3 (ALDERLAKE_N)
[17:05:15] [PASSED] 0x46D4 (ALDERLAKE_N)
[17:05:15] [PASSED] 0xA721 (ALDERLAKE_P)
[17:05:15] [PASSED] 0xA7A1 (ALDERLAKE_P)
[17:05:15] [PASSED] 0xA7A9 (ALDERLAKE_P)
[17:05:15] [PASSED] 0xA7AC (ALDERLAKE_P)
[17:05:15] [PASSED] 0xA7AD (ALDERLAKE_P)
[17:05:15] [PASSED] 0xA720 (ALDERLAKE_P)
[17:05:15] [PASSED] 0xA7A0 (ALDERLAKE_P)
[17:05:15] [PASSED] 0xA7A8 (ALDERLAKE_P)
[17:05:15] [PASSED] 0xA7AA (ALDERLAKE_P)
[17:05:15] [PASSED] 0xA7AB (ALDERLAKE_P)
[17:05:15] [PASSED] 0xA780 (ALDERLAKE_S)
[17:05:15] [PASSED] 0xA781 (ALDERLAKE_S)
[17:05:15] [PASSED] 0xA782 (ALDERLAKE_S)
[17:05:15] [PASSED] 0xA783 (ALDERLAKE_S)
[17:05:15] [PASSED] 0xA788 (ALDERLAKE_S)
[17:05:15] [PASSED] 0xA789 (ALDERLAKE_S)
[17:05:15] [PASSED] 0xA78A (ALDERLAKE_S)
[17:05:15] [PASSED] 0xA78B (ALDERLAKE_S)
[17:05:15] [PASSED] 0x4905 (DG1)
[17:05:15] [PASSED] 0x4906 (DG1)
[17:05:15] [PASSED] 0x4907 (DG1)
[17:05:15] [PASSED] 0x4908 (DG1)
[17:05:15] [PASSED] 0x4909 (DG1)
[17:05:15] [PASSED] 0x56C0 (DG2)
[17:05:15] [PASSED] 0x56C2 (DG2)
[17:05:15] [PASSED] 0x56C1 (DG2)
[17:05:15] [PASSED] 0x7D51 (METEORLAKE)
[17:05:15] [PASSED] 0x7DD1 (METEORLAKE)
[17:05:15] [PASSED] 0x7D41 (METEORLAKE)
[17:05:15] [PASSED] 0x7D67 (METEORLAKE)
[17:05:15] [PASSED] 0xB640 (METEORLAKE)
[17:05:15] [PASSED] 0x56A0 (DG2)
[17:05:15] [PASSED] 0x56A1 (DG2)
[17:05:15] [PASSED] 0x56A2 (DG2)
[17:05:15] [PASSED] 0x56BE (DG2)
[17:05:15] [PASSED] 0x56BF (DG2)
[17:05:15] [PASSED] 0x5690 (DG2)
[17:05:15] [PASSED] 0x5691 (DG2)
[17:05:15] [PASSED] 0x5692 (DG2)
[17:05:15] [PASSED] 0x56A5 (DG2)
[17:05:15] [PASSED] 0x56A6 (DG2)
[17:05:15] [PASSED] 0x56B0 (DG2)
[17:05:15] [PASSED] 0x56B1 (DG2)
[17:05:15] [PASSED] 0x56BA (DG2)
[17:05:15] [PASSED] 0x56BB (DG2)
[17:05:15] [PASSED] 0x56BC (DG2)
[17:05:15] [PASSED] 0x56BD (DG2)
[17:05:15] [PASSED] 0x5693 (DG2)
[17:05:15] [PASSED] 0x5694 (DG2)
[17:05:15] [PASSED] 0x5695 (DG2)
[17:05:15] [PASSED] 0x56A3 (DG2)
[17:05:15] [PASSED] 0x56A4 (DG2)
[17:05:15] [PASSED] 0x56B2 (DG2)
[17:05:15] [PASSED] 0x56B3 (DG2)
[17:05:15] [PASSED] 0x5696 (DG2)
[17:05:15] [PASSED] 0x5697 (DG2)
[17:05:15] [PASSED] 0xB69 (PVC)
[17:05:15] [PASSED] 0xB6E (PVC)
[17:05:15] [PASSED] 0xBD4 (PVC)
[17:05:15] [PASSED] 0xBD5 (PVC)
[17:05:15] [PASSED] 0xBD6 (PVC)
[17:05:15] [PASSED] 0xBD7 (PVC)
[17:05:15] [PASSED] 0xBD8 (PVC)
[17:05:15] [PASSED] 0xBD9 (PVC)
[17:05:15] [PASSED] 0xBDA (PVC)
[17:05:15] [PASSED] 0xBDB (PVC)
[17:05:15] [PASSED] 0xBE0 (PVC)
[17:05:15] [PASSED] 0xBE1 (PVC)
[17:05:15] [PASSED] 0xBE5 (PVC)
[17:05:15] [PASSED] 0x7D40 (METEORLAKE)
[17:05:15] [PASSED] 0x7D45 (METEORLAKE)
[17:05:15] [PASSED] 0x7D55 (METEORLAKE)
[17:05:15] [PASSED] 0x7D60 (METEORLAKE)
[17:05:15] [PASSED] 0x7DD5 (METEORLAKE)
[17:05:15] [PASSED] 0x6420 (LUNARLAKE)
[17:05:15] [PASSED] 0x64A0 (LUNARLAKE)
[17:05:15] [PASSED] 0x64B0 (LUNARLAKE)
[17:05:15] [PASSED] 0xE202 (BATTLEMAGE)
[17:05:15] [PASSED] 0xE209 (BATTLEMAGE)
[17:05:15] [PASSED] 0xE20B (BATTLEMAGE)
[17:05:15] [PASSED] 0xE20C (BATTLEMAGE)
[17:05:15] [PASSED] 0xE20D (BATTLEMAGE)
[17:05:15] [PASSED] 0xE210 (BATTLEMAGE)
[17:05:15] [PASSED] 0xE211 (BATTLEMAGE)
[17:05:15] [PASSED] 0xE212 (BATTLEMAGE)
[17:05:15] [PASSED] 0xE216 (BATTLEMAGE)
[17:05:15] [PASSED] 0xE220 (BATTLEMAGE)
[17:05:15] [PASSED] 0xE221 (BATTLEMAGE)
[17:05:15] [PASSED] 0xE222 (BATTLEMAGE)
[17:05:15] [PASSED] 0xE223 (BATTLEMAGE)
[17:05:15] [PASSED] 0xB080 (PANTHERLAKE)
[17:05:15] [PASSED] 0xB081 (PANTHERLAKE)
[17:05:15] [PASSED] 0xB082 (PANTHERLAKE)
[17:05:15] [PASSED] 0xB083 (PANTHERLAKE)
[17:05:15] [PASSED] 0xB084 (PANTHERLAKE)
[17:05:15] [PASSED] 0xB085 (PANTHERLAKE)
[17:05:15] [PASSED] 0xB086 (PANTHERLAKE)
[17:05:15] [PASSED] 0xB087 (PANTHERLAKE)
[17:05:15] [PASSED] 0xB08F (PANTHERLAKE)
[17:05:15] [PASSED] 0xB090 (PANTHERLAKE)
[17:05:15] [PASSED] 0xB0A0 (PANTHERLAKE)
[17:05:15] [PASSED] 0xB0B0 (PANTHERLAKE)
[17:05:15] [PASSED] 0xFD80 (PANTHERLAKE)
[17:05:15] [PASSED] 0xFD81 (PANTHERLAKE)
[17:05:15] [PASSED] 0xD740 (NOVALAKE_S)
[17:05:15] [PASSED] 0xD741 (NOVALAKE_S)
[17:05:15] [PASSED] 0xD742 (NOVALAKE_S)
[17:05:15] [PASSED] 0xD743 (NOVALAKE_S)
[17:05:15] [PASSED] 0xD745 (NOVALAKE_S)
[17:05:15] [PASSED] 0xD74A (NOVALAKE_S)
[17:05:15] [PASSED] 0xD74B (NOVALAKE_S)
[17:05:15] [PASSED] 0x674C (CRESCENTISLAND)
[17:05:15] [PASSED] 0x674D (CRESCENTISLAND)
[17:05:15] [PASSED] 0x674E (CRESCENTISLAND)
[17:05:15] [PASSED] 0x674F (CRESCENTISLAND)
[17:05:15] [PASSED] 0x6750 (CRESCENTISLAND)
[17:05:15] [PASSED] 0xD750 (NOVALAKE_P)
[17:05:15] [PASSED] 0xD751 (NOVALAKE_P)
[17:05:15] [PASSED] 0xD752 (NOVALAKE_P)
[17:05:15] [PASSED] 0xD753 (NOVALAKE_P)
[17:05:15] [PASSED] 0xD754 (NOVALAKE_P)
[17:05:15] [PASSED] 0xD755 (NOVALAKE_P)
[17:05:15] [PASSED] 0xD756 (NOVALAKE_P)
[17:05:15] [PASSED] 0xD757 (NOVALAKE_P)
[17:05:15] [PASSED] 0xD75F (NOVALAKE_P)
[17:05:15] =============== [PASSED] check_platform_desc ===============
[17:05:15] ===================== [PASSED] xe_pci ======================
[17:05:15] ============= xe_rtp_tables_test (5 subtests) ==============
[17:05:15] ================== xe_rtp_table_gt_test  ===================
[17:05:15] [PASSED] gt_was/14011060649
[17:05:15] [PASSED] gt_was/14011059788
[17:05:15] [PASSED] gt_was/14015795083
[17:05:15] [PASSED] gt_was/16021867713
[17:05:15] [PASSED] gt_was/14019449301
[17:05:15] [PASSED] gt_was/16028005424
[17:05:15] [PASSED] gt_was/14026578760
[17:05:15] [PASSED] gt_was/1409420604
[17:05:15] [PASSED] gt_was/1408615072
[17:05:15] [PASSED] gt_was/22010523718
[17:05:15] [PASSED] gt_was/14011006942
[17:05:15] [PASSED] gt_was/14014830051
[17:05:15] [PASSED] gt_was/18018781329
[17:05:15] [PASSED] gt_was/1509235366
[17:05:15] [PASSED] gt_was/18018781329
[17:05:15] [PASSED] gt_was/16016694945
[17:05:15] [PASSED] gt_was/14018575942
[17:05:15] [PASSED] gt_was/22016670082
[17:05:15] [PASSED] gt_was/22016670082
[17:05:15] [PASSED] gt_was/14017421178
[17:05:15] [PASSED] gt_was/16025250150
[17:05:15] [PASSED] gt_was/14021871409
[17:05:15] [PASSED] gt_was/16021865536
[17:05:15] [PASSED] gt_was/14021486841
[17:05:15] [PASSED] gt_was/14025160223
[17:05:15] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[17:05:15] [PASSED] gt_was/14025635424
[17:05:15] [PASSED] gt_was/16028005424
[17:05:15] ============== [PASSED] xe_rtp_table_gt_test ===============
[17:05:15] ================== xe_rtp_table_gt_test  ===================
[17:05:15] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[17:05:15] [PASSED] gt_tunings/Tuning: 32B Access Enable
[17:05:15] [PASSED] gt_tunings/Tuning: L3 cache
[17:05:15] [PASSED] gt_tunings/Tuning: L3 cache - media
[17:05:15] [PASSED] gt_tunings/Tuning: Compression Overfetch
[17:05:15] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[17:05:15] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[17:05:15] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[17:05:15] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[17:05:15] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[17:05:15] [PASSED] gt_tunings/Tuning: Stateless compression control
[17:05:15] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[17:05:15] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[17:05:15] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[17:05:15] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[17:05:15] ============== [PASSED] xe_rtp_table_gt_test ===============
[17:05:15] ================== xe_rtp_table_oob_test  ==================
[17:05:15] [PASSED] oob_was/1607983814
[17:05:15] [PASSED] oob_was/16010904313
[17:05:15] [PASSED] oob_was/18022495364
[17:05:15] [PASSED] oob_was/22012773006
[17:05:15] [PASSED] oob_was/14014475959
[17:05:15] [PASSED] oob_was/22011391025
[17:05:15] [PASSED] oob_was/22012727170
[17:05:15] [PASSED] oob_was/22012727685
[17:05:15] [PASSED] oob_was/22016596838
[17:05:15] [PASSED] oob_was/18020744125
[17:05:15] [PASSED] oob_was/1409600907
[17:05:15] [PASSED] oob_was/22014953428
[17:05:15] [PASSED] oob_was/16017236439
[17:05:15] [PASSED] oob_was/14019821291
[17:05:15] [PASSED] oob_was/14015076503
[17:05:15] [PASSED] oob_was/14018913170
[17:05:15] [PASSED] oob_was/14018094691
[17:05:15] [PASSED] oob_was/18024947630
[17:05:15] [PASSED] oob_was/16022287689
[17:05:15] [PASSED] oob_was/13011645652
[17:05:15] [PASSED] oob_was/14022293748
[17:05:15] [PASSED] oob_was/22019794406
[17:05:15] [PASSED] oob_was/22019338487
[17:05:15] [PASSED] oob_was/16023588340
[17:05:15] [PASSED] oob_was/14019789679
[17:05:15] [PASSED] oob_was/14022866841
[17:05:15] [PASSED] oob_was/16021333562
[17:05:15] [PASSED] oob_was/14016712196
[17:05:15] [PASSED] oob_was/14015568240
[17:05:15] [PASSED] oob_was/18013179988
[17:05:15] [PASSED] oob_was/1508761755
[17:05:15] [PASSED] oob_was/16023105232
[17:05:15] [PASSED] oob_was/16026508708
[17:05:15] [PASSED] oob_was/14020001231
[17:05:15] [PASSED] oob_was/16023683509
[17:05:15] [PASSED] oob_was/14025515070
[17:05:15] [PASSED] oob_was/15015404425_disable
[17:05:15] [PASSED] oob_was/16026007364
[17:05:15] [PASSED] oob_was/14020316580
[17:05:15] [PASSED] oob_was/14025883347
[17:05:15] [PASSED] oob_was/16029380221
[17:05:15] [PASSED] oob_was/22022079272
[17:05:15] [PASSED] oob_was/16029897822
[17:05:15] [PASSED] oob_was/14027054324
[17:05:15] [PASSED] oob_was/14025941587
[17:05:15] ============== [PASSED] xe_rtp_table_oob_test ==============
[17:05:15] ================ xe_rtp_table_dev_oob_test  ================
[17:05:15] [PASSED] device_oob_was/22010954014
[17:05:15] [PASSED] device_oob_was/15015404425
[17:05:15] [PASSED] device_oob_was/22019338487_display
[17:05:15] [PASSED] device_oob_was/14022085890
[17:05:15] [PASSED] device_oob_was/14026539277
[17:05:15] [PASSED] device_oob_was/14026633728
[17:05:15] [PASSED] device_oob_was/14026746987
[17:05:15] [PASSED] device_oob_was/14026779378
[17:05:15] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[17:05:15] ========== xe_rtp_table_missing_upper_bound_test  ==========
[17:05:15] [PASSED] register_whitelist/WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865
[17:05:15] [PASSED] register_whitelist/1508744258, 14012131227, 1808121037
[17:05:15] [PASSED] register_whitelist/1806527549
[17:05:15] [PASSED] register_whitelist/allow_read_ctx_timestamp
[17:05:15] [PASSED] register_whitelist/allow_read_queue_timestamp
[17:05:15] [PASSED] register_whitelist/16014440446
[17:05:15] [PASSED] register_whitelist/16017236439
[17:05:15] [PASSED] register_whitelist/16020183090
[17:05:15] [PASSED] register_whitelist/14024997852
[17:05:15] [PASSED] register_whitelist/14024997852
[17:05:15] ====== [PASSED] xe_rtp_table_missing_upper_bound_test ======
[17:05:15] =============== [PASSED] xe_rtp_tables_test ================
[17:05:15] =================== xe_rtp (3 subtests) ====================
[17:05:15] =================== xe_rtp_rules_tests  ====================
[17:05:15] [PASSED] no
[17:05:15] [PASSED] yes
[17:05:15] [PASSED] no-and-no
[17:05:15] [PASSED] no-and-yes
[17:05:15] [PASSED] yes-and-no
[17:05:15] [PASSED] yes-and-yes
[17:05:15] [PASSED] no-or-no
[17:05:15] [PASSED] no-or-yes
[17:05:15] [PASSED] yes-or-no
[17:05:15] [PASSED] yes-or-yes
[17:05:15] [PASSED] no-yes-or-yes-no
[17:05:15] [PASSED] no-yes-or-yes-yes
[17:05:15] [PASSED] yes-yes-or-no-yes
[17:05:15] [PASSED] yes-yes-or-yes-yes
[17:05:15] [PASSED] no-no-or-yes-or-no
[17:05:15] [PASSED] or
[17:05:15] [PASSED] or-yes
[17:05:15] [PASSED] or-no
[17:05:15] [PASSED] yes-or
[17:05:15] [PASSED] no-or
[17:05:15] [PASSED] no-or-or-yes
[17:05:15] [PASSED] yes-or-or-no
[17:05:15] [PASSED] no-or-or-no
[17:05:15] [PASSED] missing-context-engine-class
[17:05:15] [PASSED] missing-context-engine-class-or-yes
[17:05:15] [PASSED] missing-context-engine-class-or-or-yes
[17:05:15] =============== [PASSED] xe_rtp_rules_tests ================
[17:05:15] =============== xe_rtp_process_to_sr_tests  ================
[17:05:15] [PASSED] coalesce-same-reg
[17:05:15] [PASSED] coalesce-same-reg-literal-and-func
[17:05:15] [PASSED] no-match-no-add
[17:05:15] [PASSED] two-regs-two-entries
[17:05:15] [PASSED] clr-one-set-other
[17:05:15] [PASSED] set-field
[17:05:15] [PASSED] conflict-duplicate
[17:05:15] [PASSED] conflict-not-disjoint
[17:05:15] [PASSED] conflict-not-disjoint-literal-and-func
[17:05:15] [PASSED] conflict-reg-type
[17:05:15] [PASSED] bad-mcr-reg-forced-to-regular
[17:05:15] [PASSED] bad-regular-reg-forced-to-mcr
[17:05:15] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[17:05:15] ================== xe_rtp_process_tests  ===================
[17:05:15] [PASSED] active1
[17:05:15] [PASSED] active2
[17:05:15] [PASSED] active-inactive
[17:05:15] [PASSED] inactive-active
[17:05:15] [PASSED] inactive-active-inactive
[17:05:15] [PASSED] inactive-inactive-inactive
[17:05:15] ============== [PASSED] xe_rtp_process_tests ===============
[17:05:15] ===================== [PASSED] xe_rtp ======================
[17:05:15] ==================== xe_wa (1 subtest) =====================
[17:05:15] ======================== xe_wa_gt  =========================
[17:05:15] [PASSED] TIGERLAKE B0
[17:05:15] [PASSED] DG1 A0
[17:05:15] [PASSED] DG1 B0
[17:05:15] [PASSED] ALDERLAKE_S A0
[17:05:15] [PASSED] ALDERLAKE_S B0
[17:05:15] [PASSED] ALDERLAKE_S C0
[17:05:15] [PASSED] ALDERLAKE_S D0
[17:05:15] [PASSED] ALDERLAKE_P A0
[17:05:15] [PASSED] ALDERLAKE_P B0
[17:05:15] [PASSED] ALDERLAKE_P C0
[17:05:15] [PASSED] ALDERLAKE_S RPLS D0
[17:05:15] [PASSED] ALDERLAKE_P RPLU E0
[17:05:15] [PASSED] DG2 G10 C0
[17:05:15] [PASSED] DG2 G11 B1
[17:05:15] [PASSED] DG2 G12 A1
[17:05:15] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[17:05:15] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[17:05:15] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[17:05:15] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[17:05:15] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[17:05:15] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[17:05:15] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[17:05:15] ==================== [PASSED] xe_wa_gt =====================
[17:05:15] ====================== [PASSED] xe_wa ======================
[17:05:15] ============================================================
[17:05:15] Testing complete. Ran 794 tests: passed: 766, skipped: 28
[17:05:15] Elapsed time: 36.129s total, 1.818s configuring, 33.595s building, 0.702s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[17:05:15] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[17:05:17] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[17:05:42] Starting KUnit Kernel (1/1)...
[17:05:42] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[17:05:42] ============= refcount_interrupt (4 subtests) ==============
[17:05:42] [PASSED] test_single_irq_change
[17:05:42] [PASSED] test_nested_irq_change
[17:05:42] [PASSED] test_multiple_irq_change
[17:05:42] [PASSED] test_irq_save
[17:05:42] =============== [PASSED] refcount_interrupt ================
[17:05:42] ============ drm_test_pick_cmdline (2 subtests) ============
[17:05:42] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[17:05:42] =============== drm_test_pick_cmdline_named  ===============
[17:05:42] [PASSED] NTSC
[17:05:42] [PASSED] NTSC-J
[17:05:42] [PASSED] PAL
[17:05:42] [PASSED] PAL-M
[17:05:42] =========== [PASSED] drm_test_pick_cmdline_named ===========
[17:05:42] ============== [PASSED] drm_test_pick_cmdline ==============
[17:05:42] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[17:05:42] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[17:05:42] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[17:05:42] =========== drm_validate_clone_mode (2 subtests) ===========
[17:05:42] ============== drm_test_check_in_clone_mode  ===============
[17:05:42] [PASSED] in_clone_mode
[17:05:42] [PASSED] not_in_clone_mode
[17:05:42] ========== [PASSED] drm_test_check_in_clone_mode ===========
[17:05:42] =============== drm_test_check_valid_clones  ===============
[17:05:42] [PASSED] not_in_clone_mode
[17:05:42] [PASSED] valid_clone
[17:05:42] [PASSED] invalid_clone
[17:05:42] =========== [PASSED] drm_test_check_valid_clones ===========
[17:05:42] ============= [PASSED] drm_validate_clone_mode =============
[17:05:42] ============= drm_validate_modeset (1 subtest) =============
[17:05:42] [PASSED] drm_test_check_connector_changed_modeset
[17:05:42] ============== [PASSED] drm_validate_modeset ===============
[17:05:42] ====== drm_test_bridge_get_current_state (1 subtest) =======
[17:05:42] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[17:05:42] ======== [PASSED] drm_test_bridge_get_current_state ========
[17:05:42] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[17:05:42] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[17:05:42] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[17:05:42] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[17:05:42] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[17:05:42] ============== drm_bridge_alloc (2 subtests) ===============
[17:05:42] [PASSED] drm_test_drm_bridge_alloc_basic
[17:05:42] [PASSED] drm_test_drm_bridge_alloc_get_put
[17:05:42] ================ [PASSED] drm_bridge_alloc =================
[17:05:42] ============= drm_bridge_bus_fmt (5 subtests) ==============
[17:05:42] [PASSED] drm_test_bridge_rgb_yuv_rgb
[17:05:42] [PASSED] drm_test_bridge_must_convert_to_yuv444
[17:05:42] [PASSED] drm_test_bridge_hdmi_auto_rgb
[17:05:42] [PASSED] drm_test_bridge_auto_first
[17:05:42] [PASSED] drm_test_bridge_rgb_yuv_no_path
[17:05:42] =============== [PASSED] drm_bridge_bus_fmt ================
[17:05:42] ============= drm_cmdline_parser (40 subtests) =============
[17:05:42] [PASSED] drm_test_cmdline_force_d_only
[17:05:42] [PASSED] drm_test_cmdline_force_D_only_dvi
[17:05:42] [PASSED] drm_test_cmdline_force_D_only_hdmi
[17:05:42] [PASSED] drm_test_cmdline_force_D_only_not_digital
[17:05:42] [PASSED] drm_test_cmdline_force_e_only
[17:05:42] [PASSED] drm_test_cmdline_res
[17:05:42] [PASSED] drm_test_cmdline_res_vesa
[17:05:42] [PASSED] drm_test_cmdline_res_vesa_rblank
[17:05:42] [PASSED] drm_test_cmdline_res_rblank
[17:05:42] [PASSED] drm_test_cmdline_res_bpp
[17:05:42] [PASSED] drm_test_cmdline_res_refresh
[17:05:42] [PASSED] drm_test_cmdline_res_bpp_refresh
[17:05:42] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[17:05:42] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[17:05:42] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[17:05:42] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[17:05:42] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[17:05:42] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[17:05:42] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[17:05:42] [PASSED] drm_test_cmdline_res_margins_force_on
[17:05:42] [PASSED] drm_test_cmdline_res_vesa_margins
[17:05:42] [PASSED] drm_test_cmdline_name
[17:05:42] [PASSED] drm_test_cmdline_name_bpp
[17:05:42] [PASSED] drm_test_cmdline_name_option
[17:05:42] [PASSED] drm_test_cmdline_name_bpp_option
[17:05:42] [PASSED] drm_test_cmdline_rotate_0
[17:05:42] [PASSED] drm_test_cmdline_rotate_90
[17:05:42] [PASSED] drm_test_cmdline_rotate_180
[17:05:42] [PASSED] drm_test_cmdline_rotate_270
[17:05:42] [PASSED] drm_test_cmdline_hmirror
[17:05:42] [PASSED] drm_test_cmdline_vmirror
[17:05:42] [PASSED] drm_test_cmdline_margin_options
[17:05:42] [PASSED] drm_test_cmdline_multiple_options
[17:05:42] [PASSED] drm_test_cmdline_bpp_extra_and_option
[17:05:42] [PASSED] drm_test_cmdline_extra_and_option
[17:05:42] [PASSED] drm_test_cmdline_freestanding_options
[17:05:42] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[17:05:42] [PASSED] drm_test_cmdline_panel_orientation
[17:05:42] ================ drm_test_cmdline_invalid  =================
[17:05:42] [PASSED] margin_only
[17:05:42] [PASSED] interlace_only
[17:05:42] [PASSED] res_missing_x
[17:05:42] [PASSED] res_missing_y
[17:05:42] [PASSED] res_bad_y
[17:05:42] [PASSED] res_missing_y_bpp
[17:05:42] [PASSED] res_bad_bpp
[17:05:42] [PASSED] res_bad_refresh
[17:05:42] [PASSED] res_bpp_refresh_force_on_off
[17:05:42] [PASSED] res_invalid_mode
[17:05:42] [PASSED] res_bpp_wrong_place_mode
[17:05:42] [PASSED] name_bpp_refresh
[17:05:42] [PASSED] name_refresh
[17:05:42] [PASSED] name_refresh_wrong_mode
[17:05:42] [PASSED] name_refresh_invalid_mode
[17:05:42] [PASSED] rotate_multiple
[17:05:42] [PASSED] rotate_invalid_val
[17:05:42] [PASSED] rotate_truncated
[17:05:42] [PASSED] invalid_option
[17:05:42] [PASSED] invalid_tv_option
[17:05:42] [PASSED] truncated_tv_option
[17:05:42] ============ [PASSED] drm_test_cmdline_invalid =============
[17:05:42] =============== drm_test_cmdline_tv_options  ===============
[17:05:42] [PASSED] NTSC
[17:05:42] [PASSED] NTSC_443
[17:05:42] [PASSED] NTSC_J
[17:05:42] [PASSED] PAL
[17:05:42] [PASSED] PAL_M
[17:05:42] [PASSED] PAL_N
[17:05:42] [PASSED] SECAM
[17:05:42] [PASSED] MONO_525
[17:05:42] [PASSED] MONO_625
[17:05:42] =========== [PASSED] drm_test_cmdline_tv_options ===========
[17:05:42] =============== [PASSED] drm_cmdline_parser ================
[17:05:42] ========== drmm_connector_hdmi_init (20 subtests) ==========
[17:05:42] [PASSED] drm_test_connector_hdmi_init_valid
[17:05:42] [PASSED] drm_test_connector_hdmi_init_bpc_8
[17:05:42] [PASSED] drm_test_connector_hdmi_init_bpc_10
[17:05:42] [PASSED] drm_test_connector_hdmi_init_bpc_12
[17:05:42] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[17:05:42] [PASSED] drm_test_connector_hdmi_init_bpc_null
[17:05:42] [PASSED] drm_test_connector_hdmi_init_formats_empty
[17:05:42] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[17:05:42] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[17:05:42] [PASSED] supported_formats=0x9 yuv420_allowed=1
[17:05:42] [PASSED] supported_formats=0x9 yuv420_allowed=0
[17:05:42] [PASSED] supported_formats=0x5 yuv420_allowed=1
[17:05:42] [PASSED] supported_formats=0x5 yuv420_allowed=0
[17:05:42] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[17:05:42] [PASSED] drm_test_connector_hdmi_init_null_ddc
[17:05:42] [PASSED] drm_test_connector_hdmi_init_null_product
[17:05:42] [PASSED] drm_test_connector_hdmi_init_null_vendor
[17:05:42] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[17:05:42] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[17:05:42] [PASSED] drm_test_connector_hdmi_init_product_valid
[17:05:42] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[17:05:42] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[17:05:42] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[17:05:42] ========= drm_test_connector_hdmi_init_type_valid  =========
[17:05:42] [PASSED] HDMI-A
[17:05:42] [PASSED] HDMI-B
[17:05:42] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[17:05:42] ======== drm_test_connector_hdmi_init_type_invalid  ========
[17:05:42] [PASSED] Unknown
[17:05:42] [PASSED] VGA
[17:05:42] [PASSED] DVI-I
[17:05:42] [PASSED] DVI-D
[17:05:42] [PASSED] DVI-A
[17:05:42] [PASSED] Composite
[17:05:42] [PASSED] SVIDEO
[17:05:42] [PASSED] LVDS
[17:05:42] [PASSED] Component
[17:05:42] [PASSED] DIN
[17:05:42] [PASSED] DP
[17:05:42] [PASSED] TV
[17:05:42] [PASSED] eDP
[17:05:42] [PASSED] Virtual
[17:05:42] [PASSED] DSI
[17:05:42] [PASSED] DPI
[17:05:42] [PASSED] Writeback
[17:05:42] [PASSED] SPI
[17:05:42] [PASSED] USB
[17:05:42] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[17:05:42] ============ [PASSED] drmm_connector_hdmi_init =============
[17:05:42] ============= drmm_connector_init (3 subtests) =============
[17:05:42] [PASSED] drm_test_drmm_connector_init
[17:05:42] [PASSED] drm_test_drmm_connector_init_null_ddc
[17:05:42] ========= drm_test_drmm_connector_init_type_valid  =========
[17:05:42] [PASSED] Unknown
[17:05:42] [PASSED] VGA
[17:05:42] [PASSED] DVI-I
[17:05:42] [PASSED] DVI-D
[17:05:42] [PASSED] DVI-A
[17:05:42] [PASSED] Composite
[17:05:42] [PASSED] SVIDEO
[17:05:42] [PASSED] LVDS
[17:05:42] [PASSED] Component
[17:05:42] [PASSED] DIN
[17:05:42] [PASSED] DP
[17:05:42] [PASSED] HDMI-A
[17:05:42] [PASSED] HDMI-B
[17:05:42] [PASSED] TV
[17:05:42] [PASSED] eDP
[17:05:42] [PASSED] Virtual
[17:05:42] [PASSED] DSI
[17:05:42] [PASSED] DPI
[17:05:42] [PASSED] Writeback
[17:05:42] [PASSED] SPI
[17:05:42] [PASSED] USB
[17:05:42] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[17:05:42] =============== [PASSED] drmm_connector_init ===============
[17:05:42] ========= drm_connector_dynamic_init (6 subtests) ==========
[17:05:42] [PASSED] drm_test_drm_connector_dynamic_init
[17:05:42] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[17:05:42] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[17:05:42] [PASSED] drm_test_drm_connector_dynamic_init_properties
[17:05:42] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[17:05:42] [PASSED] Unknown
[17:05:42] [PASSED] VGA
[17:05:42] [PASSED] DVI-I
[17:05:42] [PASSED] DVI-D
[17:05:42] [PASSED] DVI-A
[17:05:42] [PASSED] Composite
[17:05:42] [PASSED] SVIDEO
[17:05:42] [PASSED] LVDS
[17:05:42] [PASSED] Component
[17:05:42] [PASSED] DIN
[17:05:42] [PASSED] DP
[17:05:42] [PASSED] HDMI-A
[17:05:42] [PASSED] HDMI-B
[17:05:42] [PASSED] TV
[17:05:42] [PASSED] eDP
[17:05:42] [PASSED] Virtual
[17:05:42] [PASSED] DSI
[17:05:42] [PASSED] DPI
[17:05:42] [PASSED] Writeback
[17:05:42] [PASSED] SPI
[17:05:42] [PASSED] USB
[17:05:42] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[17:05:42] ======== drm_test_drm_connector_dynamic_init_name  =========
[17:05:42] [PASSED] Unknown
[17:05:42] [PASSED] VGA
[17:05:42] [PASSED] DVI-I
[17:05:42] [PASSED] DVI-D
[17:05:42] [PASSED] DVI-A
[17:05:42] [PASSED] Composite
[17:05:42] [PASSED] SVIDEO
[17:05:42] [PASSED] LVDS
[17:05:42] [PASSED] Component
[17:05:42] [PASSED] DIN
[17:05:42] [PASSED] DP
[17:05:42] [PASSED] HDMI-A
[17:05:42] [PASSED] HDMI-B
[17:05:42] [PASSED] TV
[17:05:42] [PASSED] eDP
[17:05:42] [PASSED] Virtual
[17:05:42] [PASSED] DSI
[17:05:42] [PASSED] DPI
[17:05:42] [PASSED] Writeback
[17:05:42] [PASSED] SPI
[17:05:42] [PASSED] USB
[17:05:42] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[17:05:42] =========== [PASSED] drm_connector_dynamic_init ============
[17:05:42] ==== drm_connector_dynamic_register_early (4 subtests) =====
[17:05:42] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[17:05:42] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[17:05:42] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[17:05:42] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[17:05:42] ====== [PASSED] drm_connector_dynamic_register_early =======
[17:05:42] ======= drm_connector_dynamic_register (7 subtests) ========
[17:05:42] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[17:05:42] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[17:05:42] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[17:05:42] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[17:05:42] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[17:05:42] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[17:05:42] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[17:05:42] ========= [PASSED] drm_connector_dynamic_register ==========
[17:05:42] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[17:05:42] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[17:05:42] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[17:05:42] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[17:05:42] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[17:05:42] ========== drm_test_get_tv_mode_from_name_valid  ===========
[17:05:42] [PASSED] NTSC
[17:05:42] [PASSED] NTSC-443
[17:05:42] [PASSED] NTSC-J
[17:05:42] [PASSED] PAL
[17:05:42] [PASSED] PAL-M
[17:05:42] [PASSED] PAL-N
[17:05:42] [PASSED] SECAM
[17:05:42] [PASSED] Mono
[17:05:42] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[17:05:42] [PASSED] drm_test_get_tv_mode_from_name_truncated
[17:05:42] ============ [PASSED] drm_get_tv_mode_from_name ============
[17:05:42] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[17:05:42] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[17:05:42] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[17:05:42] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[17:05:42] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[17:05:42] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[17:05:42] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[17:05:42] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[17:05:42] [PASSED] VIC 96
[17:05:42] [PASSED] VIC 97
[17:05:42] [PASSED] VIC 101
[17:05:42] [PASSED] VIC 102
[17:05:42] [PASSED] VIC 106
[17:05:42] [PASSED] VIC 107
[17:05:42] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[17:05:42] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[17:05:42] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[17:05:42] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[17:05:42] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[17:05:42] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[17:05:42] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[17:05:42] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[17:05:42] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[17:05:42] [PASSED] Automatic
[17:05:42] [PASSED] Full
[17:05:42] [PASSED] Limited 16:235
[17:05:42] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[17:05:42] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[17:05:42] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[17:05:42] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[17:05:42] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[17:05:42] [PASSED] RGB
[17:05:42] [PASSED] YUV 4:2:0
[17:05:42] [PASSED] YUV 4:2:2
[17:05:42] [PASSED] YUV 4:4:4
[17:05:42] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[17:05:42] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[17:05:42] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[17:05:42] ============= drm_damage_helper (21 subtests) ==============
[17:05:42] [PASSED] drm_test_damage_iter_no_damage
[17:05:42] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[17:05:42] [PASSED] drm_test_damage_iter_no_damage_src_moved
[17:05:42] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[17:05:42] [PASSED] drm_test_damage_iter_no_damage_not_visible
[17:05:42] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[17:05:42] [PASSED] drm_test_damage_iter_no_damage_no_fb
[17:05:42] [PASSED] drm_test_damage_iter_simple_damage
[17:05:42] [PASSED] drm_test_damage_iter_single_damage
[17:05:42] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[17:05:42] [PASSED] drm_test_damage_iter_single_damage_outside_src
[17:05:42] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[17:05:42] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[17:05:42] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[17:05:42] [PASSED] drm_test_damage_iter_single_damage_src_moved
[17:05:42] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[17:05:42] [PASSED] drm_test_damage_iter_damage
[17:05:42] [PASSED] drm_test_damage_iter_damage_one_intersect
[17:05:42] [PASSED] drm_test_damage_iter_damage_one_outside
[17:05:42] [PASSED] drm_test_damage_iter_damage_src_moved
[17:05:42] [PASSED] drm_test_damage_iter_damage_not_visible
[17:05:42] ================ [PASSED] drm_damage_helper ================
[17:05:42] ============== drm_dp_mst_helper (3 subtests) ==============
[17:05:42] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[17:05:42] [PASSED] Clock 154000 BPP 30 DSC disabled
[17:05:42] [PASSED] Clock 234000 BPP 30 DSC disabled
[17:05:42] [PASSED] Clock 297000 BPP 24 DSC disabled
[17:05:42] [PASSED] Clock 332880 BPP 24 DSC enabled
[17:05:42] [PASSED] Clock 324540 BPP 24 DSC enabled
[17:05:42] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[17:05:42] ============== drm_test_dp_mst_calc_pbn_div  ===============
[17:05:42] [PASSED] Link rate 2000000 lane count 4
[17:05:42] [PASSED] Link rate 2000000 lane count 2
[17:05:42] [PASSED] Link rate 2000000 lane count 1
[17:05:42] [PASSED] Link rate 1350000 lane count 4
[17:05:42] [PASSED] Link rate 1350000 lane count 2
[17:05:42] [PASSED] Link rate 1350000 lane count 1
[17:05:42] [PASSED] Link rate 1000000 lane count 4
[17:05:42] [PASSED] Link rate 1000000 lane count 2
[17:05:42] [PASSED] Link rate 1000000 lane count 1
[17:05:42] [PASSED] Link rate 810000 lane count 4
[17:05:42] [PASSED] Link rate 810000 lane count 2
[17:05:42] [PASSED] Link rate 810000 lane count 1
[17:05:42] [PASSED] Link rate 540000 lane count 4
[17:05:42] [PASSED] Link rate 540000 lane count 2
[17:05:42] [PASSED] Link rate 540000 lane count 1
[17:05:42] [PASSED] Link rate 270000 lane count 4
[17:05:42] [PASSED] Link rate 270000 lane count 2
[17:05:42] [PASSED] Link rate 270000 lane count 1
[17:05:42] [PASSED] Link rate 162000 lane count 4
[17:05:42] [PASSED] Link rate 162000 lane count 2
[17:05:42] [PASSED] Link rate 162000 lane count 1
[17:05:42] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[17:05:42] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[17:05:42] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[17:05:42] [PASSED] DP_POWER_UP_PHY with port number
[17:05:42] [PASSED] DP_POWER_DOWN_PHY with port number
[17:05:42] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[17:05:42] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[17:05:42] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[17:05:42] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[17:05:42] [PASSED] DP_QUERY_PAYLOAD with port number
[17:05:42] [PASSED] DP_QUERY_PAYLOAD with VCPI
[17:05:42] [PASSED] DP_REMOTE_DPCD_READ with port number
[17:05:42] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[17:05:42] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[17:05:42] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[17:05:42] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[17:05:42] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[17:05:42] [PASSED] DP_REMOTE_I2C_READ with port number
[17:05:42] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[17:05:42] [PASSED] DP_REMOTE_I2C_READ with transactions array
[17:05:42] [PASSED] DP_REMOTE_I2C_WRITE with port number
[17:05:42] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[17:05:42] [PASSED] DP_REMOTE_I2C_WRITE with data array
[17:05:42] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[17:05:42] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[17:05:42] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[17:05:42] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[17:05:42] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[17:05:42] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[17:05:42] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[17:05:42] ================ [PASSED] drm_dp_mst_helper ================
[17:05:42] ================== drm_exec (7 subtests) ===================
[17:05:42] [PASSED] sanitycheck
[17:05:42] [PASSED] test_lock
[17:05:42] [PASSED] test_lock_unlock
[17:05:42] [PASSED] test_duplicates
[17:05:42] [PASSED] test_prepare
[17:05:42] [PASSED] test_prepare_array
[17:05:42] [PASSED] test_multiple_loops
[17:05:42] ==================== [PASSED] drm_exec =====================
[17:05:42] =========== drm_format_helper_test (17 subtests) ===========
[17:05:42] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[17:05:42] [PASSED] single_pixel_source_buffer
[17:05:42] [PASSED] single_pixel_clip_rectangle
[17:05:42] [PASSED] well_known_colors
[17:05:42] [PASSED] destination_pitch
[17:05:42] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[17:05:42] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[17:05:42] [PASSED] single_pixel_source_buffer
[17:05:42] [PASSED] single_pixel_clip_rectangle
[17:05:42] [PASSED] well_known_colors
[17:05:42] [PASSED] destination_pitch
[17:05:42] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[17:05:42] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[17:05:42] [PASSED] single_pixel_source_buffer
[17:05:42] [PASSED] single_pixel_clip_rectangle
[17:05:42] [PASSED] well_known_colors
[17:05:42] [PASSED] destination_pitch
[17:05:42] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[17:05:42] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[17:05:42] [PASSED] single_pixel_source_buffer
[17:05:42] [PASSED] single_pixel_clip_rectangle
[17:05:42] [PASSED] well_known_colors
[17:05:42] [PASSED] destination_pitch
[17:05:42] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[17:05:42] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[17:05:42] [PASSED] single_pixel_source_buffer
[17:05:42] [PASSED] single_pixel_clip_rectangle
[17:05:42] [PASSED] well_known_colors
[17:05:42] [PASSED] destination_pitch
[17:05:42] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[17:05:42] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[17:05:42] [PASSED] single_pixel_source_buffer
[17:05:42] [PASSED] single_pixel_clip_rectangle
[17:05:42] [PASSED] well_known_colors
[17:05:42] [PASSED] destination_pitch
[17:05:42] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[17:05:42] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[17:05:42] [PASSED] single_pixel_source_buffer
[17:05:42] [PASSED] single_pixel_clip_rectangle
[17:05:42] [PASSED] well_known_colors
[17:05:42] [PASSED] destination_pitch
[17:05:42] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[17:05:42] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[17:05:42] [PASSED] single_pixel_source_buffer
[17:05:42] [PASSED] single_pixel_clip_rectangle
[17:05:42] [PASSED] well_known_colors
[17:05:42] [PASSED] destination_pitch
[17:05:42] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[17:05:42] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[17:05:42] [PASSED] single_pixel_source_buffer
[17:05:42] [PASSED] single_pixel_clip_rectangle
[17:05:42] [PASSED] well_known_colors
[17:05:42] [PASSED] destination_pitch
[17:05:42] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[17:05:42] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[17:05:42] [PASSED] single_pixel_source_buffer
[17:05:42] [PASSED] single_pixel_clip_rectangle
[17:05:42] [PASSED] well_known_colors
[17:05:42] [PASSED] destination_pitch
[17:05:42] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[17:05:42] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[17:05:42] [PASSED] single_pixel_source_buffer
[17:05:42] [PASSED] single_pixel_clip_rectangle
[17:05:42] [PASSED] well_known_colors
[17:05:42] [PASSED] destination_pitch
[17:05:42] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[17:05:42] ============== drm_test_fb_xrgb8888_to_mono  ===============
[17:05:42] [PASSED] single_pixel_source_buffer
[17:05:42] [PASSED] single_pixel_clip_rectangle
[17:05:42] [PASSED] well_known_colors
[17:05:42] [PASSED] destination_pitch
[17:05:42] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[17:05:42] ==================== drm_test_fb_swab  =====================
[17:05:42] [PASSED] single_pixel_source_buffer
[17:05:42] [PASSED] single_pixel_clip_rectangle
[17:05:42] [PASSED] well_known_colors
[17:05:42] [PASSED] destination_pitch
[17:05:42] ================ [PASSED] drm_test_fb_swab =================
[17:05:42] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[17:05:42] [PASSED] single_pixel_source_buffer
[17:05:42] [PASSED] single_pixel_clip_rectangle
[17:05:42] [PASSED] well_known_colors
[17:05:42] [PASSED] destination_pitch
[17:05:42] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[17:05:42] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[17:05:42] [PASSED] single_pixel_source_buffer
[17:05:42] [PASSED] single_pixel_clip_rectangle
[17:05:42] [PASSED] well_known_colors
[17:05:42] [PASSED] destination_pitch
[17:05:42] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[17:05:42] ================= drm_test_fb_clip_offset  =================
[17:05:42] [PASSED] pass through
[17:05:42] [PASSED] horizontal offset
[17:05:42] [PASSED] vertical offset
[17:05:42] [PASSED] horizontal and vertical offset
[17:05:42] [PASSED] horizontal offset (custom pitch)
[17:05:42] [PASSED] vertical offset (custom pitch)
[17:05:42] [PASSED] horizontal and vertical offset (custom pitch)
[17:05:42] ============= [PASSED] drm_test_fb_clip_offset =============
[17:05:42] =================== drm_test_fb_memcpy  ====================
[17:05:42] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[17:05:42] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[17:05:42] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[17:05:42] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[17:05:42] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[17:05:42] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[17:05:42] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[17:05:42] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[17:05:42] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[17:05:42] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[17:05:42] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[17:05:42] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[17:05:42] =============== [PASSED] drm_test_fb_memcpy ================
[17:05:42] ============= [PASSED] drm_format_helper_test ==============
[17:05:42] ================= drm_format (18 subtests) =================
[17:05:42] [PASSED] drm_test_format_block_width_invalid
[17:05:42] [PASSED] drm_test_format_block_width_one_plane
[17:05:42] [PASSED] drm_test_format_block_width_two_plane
[17:05:42] [PASSED] drm_test_format_block_width_three_plane
[17:05:42] [PASSED] drm_test_format_block_width_tiled
[17:05:42] [PASSED] drm_test_format_block_height_invalid
[17:05:42] [PASSED] drm_test_format_block_height_one_plane
[17:05:42] [PASSED] drm_test_format_block_height_two_plane
[17:05:42] [PASSED] drm_test_format_block_height_three_plane
[17:05:42] [PASSED] drm_test_format_block_height_tiled
[17:05:42] [PASSED] drm_test_format_min_pitch_invalid
[17:05:42] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[17:05:42] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[17:05:42] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[17:05:42] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[17:05:42] [PASSED] drm_test_format_min_pitch_two_plane
[17:05:42] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[17:05:42] [PASSED] drm_test_format_min_pitch_tiled
[17:05:42] =================== [PASSED] drm_format ====================
[17:05:42] ============== drm_framebuffer (10 subtests) ===============
[17:05:42] ========== drm_test_framebuffer_check_src_coords  ==========
[17:05:42] [PASSED] Success: source fits into fb
[17:05:42] [PASSED] Fail: overflowing fb with x-axis coordinate
[17:05:42] [PASSED] Fail: overflowing fb with y-axis coordinate
[17:05:42] [PASSED] Fail: overflowing fb with source width
[17:05:42] [PASSED] Fail: overflowing fb with source height
[17:05:42] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[17:05:42] [PASSED] drm_test_framebuffer_cleanup
[17:05:42] =============== drm_test_framebuffer_create  ===============
[17:05:42] [PASSED] ABGR8888 normal sizes
[17:05:42] [PASSED] ABGR8888 max sizes
[17:05:42] [PASSED] ABGR8888 pitch greater than min required
[17:05:42] [PASSED] ABGR8888 pitch less than min required
[17:05:42] [PASSED] ABGR8888 Invalid width
[17:05:42] [PASSED] ABGR8888 Invalid buffer handle
[17:05:42] [PASSED] No pixel format
[17:05:42] [PASSED] ABGR8888 Width 0
[17:05:42] [PASSED] ABGR8888 Height 0
[17:05:42] [PASSED] ABGR8888 Out of bound height * pitch combination
[17:05:42] [PASSED] ABGR8888 Large buffer offset
[17:05:42] [PASSED] ABGR8888 Buffer offset for inexistent plane
[17:05:42] [PASSED] ABGR8888 Invalid flag
[17:05:42] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[17:05:42] [PASSED] ABGR8888 Valid buffer modifier
[17:05:42] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[17:05:42] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[17:05:42] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[17:05:42] [PASSED] NV12 Normal sizes
[17:05:42] [PASSED] NV12 Max sizes
[17:05:42] [PASSED] NV12 Invalid pitch
[17:05:42] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[17:05:42] [PASSED] NV12 different  modifier per-plane
[17:05:42] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[17:05:42] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[17:05:42] [PASSED] NV12 Modifier for inexistent plane
[17:05:42] [PASSED] NV12 Handle for inexistent plane
[17:05:42] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[17:05:42] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[17:05:42] [PASSED] YVU420 Normal sizes
[17:05:42] [PASSED] YVU420 Max sizes
[17:05:42] [PASSED] YVU420 Invalid pitch
[17:05:42] [PASSED] YVU420 Different pitches
[17:05:42] [PASSED] YVU420 Different buffer offsets/pitches
[17:05:42] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[17:05:42] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[17:05:42] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[17:05:42] [PASSED] YVU420 Valid modifier
[17:05:42] [PASSED] YVU420 Different modifiers per plane
[17:05:42] [PASSED] YVU420 Modifier for inexistent plane
[17:05:42] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[17:05:42] [PASSED] X0L2 Normal sizes
[17:05:42] [PASSED] X0L2 Max sizes
[17:05:42] [PASSED] X0L2 Invalid pitch
[17:05:42] [PASSED] X0L2 Pitch greater than minimum required
[17:05:42] [PASSED] X0L2 Handle for inexistent plane
[17:05:42] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[17:05:42] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[17:05:42] [PASSED] X0L2 Valid modifier
[17:05:42] [PASSED] X0L2 Modifier for inexistent plane
[17:05:42] =========== [PASSED] drm_test_framebuffer_create ===========
[17:05:42] [PASSED] drm_test_framebuffer_free
[17:05:42] [PASSED] drm_test_framebuffer_init
[17:05:42] [PASSED] drm_test_framebuffer_init_bad_format
[17:05:42] [PASSED] drm_test_framebuffer_init_dev_mismatch
[17:05:42] [PASSED] drm_test_framebuffer_lookup
[17:05:42] [PASSED] drm_test_framebuffer_lookup_inexistent
[17:05:42] [PASSED] drm_test_framebuffer_modifiers_not_supported
[17:05:42] ================= [PASSED] drm_framebuffer =================
[17:05:42] ================ drm_gem_shmem (8 subtests) ================
[17:05:42] [PASSED] drm_gem_shmem_test_obj_create
[17:05:42] [PASSED] drm_gem_shmem_test_obj_create_private
[17:05:42] [PASSED] drm_gem_shmem_test_pin_pages
[17:05:42] [PASSED] drm_gem_shmem_test_vmap
[17:05:42] [PASSED] drm_gem_shmem_test_get_sg_table
[17:05:42] [PASSED] drm_gem_shmem_test_get_pages_sgt
[17:05:42] [PASSED] drm_gem_shmem_test_madvise
[17:05:42] [PASSED] drm_gem_shmem_test_purge
[17:05:42] ================== [PASSED] drm_gem_shmem ==================
[17:05:42] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[17:05:42] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[17:05:42] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[17:05:42] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[17:05:42] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[17:05:42] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[17:05:42] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[17:05:42] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[17:05:42] [PASSED] Automatic
[17:05:42] [PASSED] Full
[17:05:42] [PASSED] Limited 16:235
[17:05:42] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[17:05:42] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[17:05:42] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[17:05:42] [PASSED] drm_test_check_disable_connector
[17:05:42] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[17:05:42] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[17:05:42] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[17:05:42] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[17:05:42] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[17:05:42] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[17:05:42] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[17:05:42] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[17:05:42] [PASSED] drm_test_check_output_bpc_dvi
[17:05:42] [PASSED] drm_test_check_output_bpc_format_vic_1
[17:05:42] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[17:05:42] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[17:05:42] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[17:05:42] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[17:05:42] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[17:05:42] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[17:05:42] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[17:05:42] ============ drm_test_check_hdmi_color_format  =============
[17:05:42] [PASSED] AUTO -> RGB
[17:05:42] [PASSED] YCBCR422 -> YUV422
[17:05:42] [PASSED] YCBCR420 -> YUV420
[17:05:42] [PASSED] YCBCR444 -> YUV444
[17:05:42] [PASSED] RGB -> RGB
[17:05:42] ======== [PASSED] drm_test_check_hdmi_color_format =========
[17:05:42] ======== drm_test_check_hdmi_color_format_420_only  ========
[17:05:42] [PASSED] RGB should fail
[17:05:42] [PASSED] YUV444 should fail
[17:05:42] [PASSED] YUV422 should fail
[17:05:42] [PASSED] YUV420 should work
[17:05:42] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[17:05:42] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[17:05:42] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[17:05:42] [PASSED] drm_test_check_broadcast_rgb_value
[17:05:42] [PASSED] drm_test_check_bpc_8_value
[17:05:42] [PASSED] drm_test_check_bpc_10_value
[17:05:42] [PASSED] drm_test_check_bpc_12_value
[17:05:42] [PASSED] drm_test_check_format_value
[17:05:42] [PASSED] drm_test_check_tmds_char_value
[17:05:42] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[17:05:42] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[17:05:42] [PASSED] drm_test_check_mode_valid
[17:05:42] [PASSED] drm_test_check_mode_valid_reject
[17:05:42] [PASSED] drm_test_check_mode_valid_reject_rate
[17:05:42] [PASSED] drm_test_check_mode_valid_reject_max_clock
[17:05:42] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[17:05:42] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[17:05:42] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[17:05:42] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[17:05:42] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[17:05:42] [PASSED] drm_test_check_infoframes
[17:05:42] [PASSED] drm_test_check_reject_avi_infoframe
[17:05:42] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[17:05:42] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[17:05:42] [PASSED] drm_test_check_reject_audio_infoframe
[17:05:42] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[17:05:42] ================= drm_managed (2 subtests) =================
[17:05:42] [PASSED] drm_test_managed_release_action
[17:05:42] [PASSED] drm_test_managed_run_action
[17:05:42] =================== [PASSED] drm_managed ===================
[17:05:42] =================== drm_mm (6 subtests) ====================
[17:05:42] [PASSED] drm_test_mm_init
[17:05:42] [PASSED] drm_test_mm_debug
[17:05:42] [PASSED] drm_test_mm_align32
[17:05:42] [PASSED] drm_test_mm_align64
[17:05:42] [PASSED] drm_test_mm_lowest
[17:05:42] [PASSED] drm_test_mm_highest
[17:05:42] ===================== [PASSED] drm_mm ======================
[17:05:42] ============= drm_modes_analog_tv (5 subtests) =============
[17:05:42] [PASSED] drm_test_modes_analog_tv_mono_576i
[17:05:42] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[17:05:42] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[17:05:42] [PASSED] drm_test_modes_analog_tv_pal_576i
[17:05:42] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[17:05:42] =============== [PASSED] drm_modes_analog_tv ===============
[17:05:42] ============== drm_plane_helper (2 subtests) ===============
[17:05:42] =============== drm_test_check_plane_state  ================
[17:05:42] [PASSED] clipping_simple
[17:05:42] [PASSED] clipping_rotate_reflect
[17:05:42] [PASSED] positioning_simple
[17:05:42] [PASSED] upscaling
[17:05:42] [PASSED] downscaling
[17:05:42] [PASSED] rounding1
[17:05:42] [PASSED] rounding2
[17:05:42] [PASSED] rounding3
[17:05:42] [PASSED] rounding4
[17:05:42] =========== [PASSED] drm_test_check_plane_state ============
[17:05:42] =========== drm_test_check_invalid_plane_state  ============
[17:05:42] [PASSED] positioning_invalid
[17:05:42] [PASSED] upscaling_invalid
[17:05:42] [PASSED] downscaling_invalid
[17:05:42] ======= [PASSED] drm_test_check_invalid_plane_state ========
[17:05:42] ================ [PASSED] drm_plane_helper =================
[17:05:42] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[17:05:42] ====== drm_test_connector_helper_tv_get_modes_check  =======
[17:05:42] [PASSED] None
[17:05:42] [PASSED] PAL
[17:05:42] [PASSED] NTSC
[17:05:42] [PASSED] Both, NTSC Default
[17:05:42] [PASSED] Both, PAL Default
[17:05:42] [PASSED] Both, NTSC Default, with PAL on command-line
[17:05:42] [PASSED] Both, PAL Default, with NTSC on command-line
[17:05:42] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[17:05:42] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[17:05:42] ================== drm_rect (9 subtests) ===================
[17:05:42] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[17:05:42] [PASSED] drm_test_rect_clip_scaled_not_clipped
[17:05:42] [PASSED] drm_test_rect_clip_scaled_clipped
[17:05:42] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[17:05:42] ================= drm_test_rect_intersect  =================
[17:05:42] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[17:05:42] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[17:05:42] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[17:05:42] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[17:05:42] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[17:05:42] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[17:05:42] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[17:05:42] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[17:05:42] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[17:05:42] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[17:05:42] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[17:05:42] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[17:05:42] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[17:05:42] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[17:05:42] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[17:05:42] ============= [PASSED] drm_test_rect_intersect =============
[17:05:42] ================ drm_test_rect_calc_hscale  ================
[17:05:42] [PASSED] normal use
[17:05:42] [PASSED] out of max range
[17:05:42] [PASSED] out of min range
[17:05:42] [PASSED] zero dst
[17:05:42] [PASSED] negative src
[17:05:42] [PASSED] negative dst
[17:05:42] ============ [PASSED] drm_test_rect_calc_hscale ============
[17:05:42] ================ drm_test_rect_calc_vscale  ================
[17:05:42] [PASSED] normal use
[17:05:42] [PASSED] out of max range
[17:05:42] [PASSED] out of min range
[17:05:42] [PASSED] zero dst
[17:05:42] [PASSED] negative src
[17:05:42] [PASSED] negative dst
[17:05:42] ============ [PASSED] drm_test_rect_calc_vscale ============
[17:05:42] ================== drm_test_rect_rotate  ===================
[17:05:42] [PASSED] reflect-x
[17:05:42] [PASSED] reflect-y
[17:05:42] [PASSED] rotate-0
[17:05:42] [PASSED] rotate-90
[17:05:42] [PASSED] rotate-180
[17:05:42] [PASSED] rotate-270
[17:05:42] ============== [PASSED] drm_test_rect_rotate ===============
[17:05:42] ================ drm_test_rect_rotate_inv  =================
[17:05:42] [PASSED] reflect-x
[17:05:42] [PASSED] reflect-y
[17:05:42] [PASSED] rotate-0
[17:05:42] [PASSED] rotate-90
[17:05:42] [PASSED] rotate-180
[17:05:42] [PASSED] rotate-270
[17:05:42] ============ [PASSED] drm_test_rect_rotate_inv =============
[17:05:42] ==================== [PASSED] drm_rect =====================
[17:05:42] ============ drm_sysfb_modeset_test (1 subtest) ============
[17:05:42] ============ drm_test_sysfb_build_fourcc_list  =============
[17:05:42] [PASSED] no native formats
[17:05:42] [PASSED] XRGB8888 as native format
[17:05:42] [PASSED] remove duplicates
[17:05:42] [PASSED] convert alpha formats
[17:05:42] [PASSED] random formats
[17:05:42] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[17:05:42] ============= [PASSED] drm_sysfb_modeset_test ==============
[17:05:42] ================== drm_fixp (2 subtests) ===================
[17:05:42] [PASSED] drm_test_int2fixp
[17:05:42] [PASSED] drm_test_sm2fixp
[17:05:42] ==================== [PASSED] drm_fixp =====================
[17:05:42] ============================================================
[17:05:42] Testing complete. Ran 641 tests: passed: 641
[17:05:42] Elapsed time: 26.936s total, 1.808s configuring, 24.910s building, 0.196s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[17:05:43] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[17:05:44] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[17:05:54] Starting KUnit Kernel (1/1)...
[17:05:54] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[17:05:54] ============= refcount_interrupt (4 subtests) ==============
[17:05:54] [PASSED] test_single_irq_change
[17:05:54] [PASSED] test_nested_irq_change
[17:05:54] [PASSED] test_multiple_irq_change
[17:05:54] [PASSED] test_irq_save
[17:05:54] =============== [PASSED] refcount_interrupt ================
[17:05:54] ================= ttm_device (5 subtests) ==================
[17:05:54] [PASSED] ttm_device_init_basic
[17:05:54] [PASSED] ttm_device_init_multiple
[17:05:54] [PASSED] ttm_device_fini_basic
[17:05:54] [PASSED] ttm_device_init_no_vma_man
[17:05:54] ================== ttm_device_init_pools  ==================
[17:05:54] [PASSED] No DMA allocations, no DMA32 required
[17:05:54] [PASSED] DMA allocations, DMA32 required
[17:05:54] [PASSED] No DMA allocations, DMA32 required
[17:05:54] [PASSED] DMA allocations, no DMA32 required
[17:05:54] ============== [PASSED] ttm_device_init_pools ==============
[17:05:54] =================== [PASSED] ttm_device ====================
[17:05:54] ================== ttm_pool (8 subtests) ===================
[17:05:54] ================== ttm_pool_alloc_basic  ===================
[17:05:54] [PASSED] One page
[17:05:54] [PASSED] More than one page
[17:05:54] [PASSED] Above the allocation limit
[17:05:54] [PASSED] One page, with coherent DMA mappings enabled
[17:05:54] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[17:05:54] ============== [PASSED] ttm_pool_alloc_basic ===============
[17:05:54] ============== ttm_pool_alloc_basic_dma_addr  ==============
[17:05:54] [PASSED] One page
[17:05:54] [PASSED] More than one page
[17:05:54] [PASSED] Above the allocation limit
[17:05:54] [PASSED] One page, with coherent DMA mappings enabled
[17:05:54] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[17:05:54] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[17:05:54] [PASSED] ttm_pool_alloc_order_caching_match
[17:05:54] [PASSED] ttm_pool_alloc_caching_mismatch
[17:05:54] [PASSED] ttm_pool_alloc_order_mismatch
[17:05:54] [PASSED] ttm_pool_free_dma_alloc
[17:05:54] [PASSED] ttm_pool_free_no_dma_alloc
[17:05:54] [PASSED] ttm_pool_fini_basic
[17:05:54] ==================== [PASSED] ttm_pool =====================
[17:05:54] ================ ttm_resource (8 subtests) =================
[17:05:54] ================= ttm_resource_init_basic  =================
[17:05:54] [PASSED] Init resource in TTM_PL_SYSTEM
[17:05:54] [PASSED] Init resource in TTM_PL_VRAM
[17:05:54] [PASSED] Init resource in a private placement
[17:05:54] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[17:05:54] ============= [PASSED] ttm_resource_init_basic =============
[17:05:54] [PASSED] ttm_resource_init_pinned
[17:05:54] [PASSED] ttm_resource_fini_basic
[17:05:54] [PASSED] ttm_resource_manager_init_basic
[17:05:54] [PASSED] ttm_resource_manager_usage_basic
[17:05:54] [PASSED] ttm_resource_manager_set_used_basic
[17:05:54] [PASSED] ttm_sys_man_alloc_basic
[17:05:54] [PASSED] ttm_sys_man_free_basic
[17:05:54] ================== [PASSED] ttm_resource ===================
[17:05:54] =================== ttm_tt (15 subtests) ===================
[17:05:54] ==================== ttm_tt_init_basic  ====================
[17:05:54] [PASSED] Page-aligned size
[17:05:54] [PASSED] Extra pages requested
[17:05:54] ================ [PASSED] ttm_tt_init_basic ================
[17:05:54] [PASSED] ttm_tt_init_misaligned
[17:05:54] [PASSED] ttm_tt_fini_basic
[17:05:54] [PASSED] ttm_tt_fini_sg
[17:05:54] [PASSED] ttm_tt_fini_shmem
[17:05:54] [PASSED] ttm_tt_create_basic
[17:05:54] [PASSED] ttm_tt_create_invalid_bo_type
[17:05:54] [PASSED] ttm_tt_create_ttm_exists
[17:05:54] [PASSED] ttm_tt_create_failed
[17:05:54] [PASSED] ttm_tt_destroy_basic
[17:05:54] [PASSED] ttm_tt_populate_null_ttm
[17:05:54] [PASSED] ttm_tt_populate_populated_ttm
[17:05:54] [PASSED] ttm_tt_unpopulate_basic
[17:05:54] [PASSED] ttm_tt_unpopulate_empty_ttm
[17:05:54] [PASSED] ttm_tt_swapin_basic
[17:05:54] ===================== [PASSED] ttm_tt ======================
[17:05:54] =================== ttm_bo (14 subtests) ===================
[17:05:54] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[17:05:54] [PASSED] Cannot be interrupted and sleeps
[17:05:54] [PASSED] Cannot be interrupted, locks straight away
[17:05:54] [PASSED] Can be interrupted, sleeps
[17:05:54] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[17:05:54] [PASSED] ttm_bo_reserve_locked_no_sleep
[17:05:54] [PASSED] ttm_bo_reserve_no_wait_ticket
[17:05:54] [PASSED] ttm_bo_reserve_double_resv
[17:05:54] [PASSED] ttm_bo_reserve_interrupted
[17:05:54] [PASSED] ttm_bo_reserve_deadlock
[17:05:54] [PASSED] ttm_bo_unreserve_basic
[17:05:54] [PASSED] ttm_bo_unreserve_pinned
[17:05:54] [PASSED] ttm_bo_unreserve_bulk
[17:05:54] [PASSED] ttm_bo_fini_basic
[17:05:54] [PASSED] ttm_bo_fini_shared_resv
[17:05:54] [PASSED] ttm_bo_pin_basic
[17:05:54] [PASSED] ttm_bo_pin_unpin_resource
[17:05:54] [PASSED] ttm_bo_multiple_pin_one_unpin
[17:05:54] ===================== [PASSED] ttm_bo ======================
[17:05:54] ============== ttm_bo_validate (22 subtests) ===============
[17:05:54] ============== ttm_bo_init_reserved_sys_man  ===============
[17:05:54] [PASSED] Buffer object for userspace
[17:05:54] [PASSED] Kernel buffer object
[17:05:54] [PASSED] Shared buffer object
[17:05:54] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[17:05:54] ============== ttm_bo_init_reserved_mock_man  ==============
[17:05:54] [PASSED] Buffer object for userspace
[17:05:54] [PASSED] Kernel buffer object
[17:05:54] [PASSED] Shared buffer object
[17:05:54] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[17:05:54] [PASSED] ttm_bo_init_reserved_resv
[17:05:54] ================== ttm_bo_validate_basic  ==================
[17:05:54] [PASSED] Buffer object for userspace
[17:05:54] [PASSED] Kernel buffer object
[17:05:54] [PASSED] Shared buffer object
[17:05:54] ============== [PASSED] ttm_bo_validate_basic ==============
[17:05:54] [PASSED] ttm_bo_validate_invalid_placement
[17:05:54] ============= ttm_bo_validate_same_placement  ==============
[17:05:54] [PASSED] System manager
[17:05:54] [PASSED] VRAM manager
[17:05:54] ========= [PASSED] ttm_bo_validate_same_placement ==========
[17:05:54] [PASSED] ttm_bo_validate_failed_alloc
[17:05:54] [PASSED] ttm_bo_validate_pinned
[17:05:54] [PASSED] ttm_bo_validate_busy_placement
[17:05:54] ================ ttm_bo_validate_multihop  =================
[17:05:54] [PASSED] Buffer object for userspace
[17:05:54] [PASSED] Kernel buffer object
[17:05:54] [PASSED] Shared buffer object
[17:05:54] ============ [PASSED] ttm_bo_validate_multihop =============
[17:05:54] ========== ttm_bo_validate_no_placement_signaled  ==========
[17:05:54] [PASSED] Buffer object in system domain, no page vector
[17:05:54] [PASSED] Buffer object in system domain with an existing page vector
[17:05:54] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[17:05:54] ======== ttm_bo_validate_no_placement_not_signaled  ========
[17:05:54] [PASSED] Buffer object for userspace
[17:05:54] [PASSED] Kernel buffer object
[17:05:54] [PASSED] Shared buffer object
[17:05:54] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[17:05:54] [PASSED] ttm_bo_validate_move_fence_signaled
[17:05:54] ========= ttm_bo_validate_move_fence_not_signaled  =========
[17:05:54] [PASSED] Waits for GPU
[17:05:54] [PASSED] Tries to lock straight away
[17:05:54] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[17:05:54] [PASSED] ttm_bo_validate_swapout
[17:05:54] [PASSED] ttm_bo_validate_happy_evict
[17:05:54] [PASSED] ttm_bo_validate_all_pinned_evict
[17:05:54] [PASSED] ttm_bo_validate_allowed_only_evict
[17:05:54] [PASSED] ttm_bo_validate_deleted_evict
[17:05:54] [PASSED] ttm_bo_validate_busy_domain_evict
[17:05:54] [PASSED] ttm_bo_validate_evict_gutting
[17:05:54] [PASSED] ttm_bo_validate_recrusive_evict
[17:05:54] ================= [PASSED] ttm_bo_validate =================
[17:05:54] ============================================================
[17:05:54] Testing complete. Ran 106 tests: passed: 106
[17:05:54] Elapsed time: 11.945s total, 1.764s configuring, 9.966s building, 0.180s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/dma-buf/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/dma-buf/.kunitconfig
[17:05:55] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[17:05:56] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[17:06:05] Starting KUnit Kernel (1/1)...
[17:06:05] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[17:06:05] ============= refcount_interrupt (4 subtests) ==============
[17:06:05] [PASSED] test_single_irq_change
[17:06:05] [PASSED] test_nested_irq_change
[17:06:05] [PASSED] test_multiple_irq_change
[17:06:05] [PASSED] test_irq_save
[17:06:05] =============== [PASSED] refcount_interrupt ================
[17:06:05] =============== dma-buf-fence (12 subtests) ================
[17:06:05] [PASSED] test_sanitycheck
[17:06:05] [PASSED] test_signaling
[17:06:05] [PASSED] test_add_callback
[17:06:05] [PASSED] test_late_add_callback
[17:06:05] [PASSED] test_rm_callback
[17:06:05] [PASSED] test_late_rm_callback
[17:06:05] [PASSED] test_status
[17:06:05] [PASSED] test_error
[17:06:05] [PASSED] test_wait
[17:06:05] [PASSED] test_wait_timeout
[17:06:05] [PASSED] test_stub
[17:06:05] [SKIPPED] test_race_signal_callback (requires at least 2 CPUs)
[17:06:05] ================== [PASSED] dma-buf-fence ==================
[17:06:05] ============ dma-buf-fence-chain (11 subtests) =============
[17:06:05] [PASSED] test_sanitycheck
[17:06:05] [PASSED] test_find_seqno
[17:06:05] [PASSED] test_find_signaled
[17:06:05] [PASSED] test_find_out_of_order
[17:06:10] [PASSED] test_find_gap
[17:06:10] [PASSED] test_find_race
[17:06:10] [PASSED] test_signal_forward
[17:06:10] [PASSED] test_signal_backward
[17:06:10] [PASSED] test_wait_forward
[17:06:10] [PASSED] test_wait_backward
[17:06:10] [PASSED] test_wait_random
[17:06:10] =============== [PASSED] dma-buf-fence-chain ===============
[17:06:10] ============ dma-buf-fence-unwrap (10 subtests) ============
[17:06:10] [PASSED] test_sanitycheck
[17:06:10] [PASSED] test_unwrap_array
[17:06:10] [PASSED] test_unwrap_chain
[17:06:10] [PASSED] test_unwrap_chain_array
[17:06:10] [PASSED] test_unwrap_merge
[17:06:10] [PASSED] test_unwrap_merge_duplicate
[17:06:10] [PASSED] test_unwrap_merge_seqno
[17:06:10] [PASSED] test_unwrap_merge_order
[17:06:10] [PASSED] test_unwrap_merge_complex
[17:06:10] [PASSED] test_unwrap_merge_complex_seqno
[17:06:10] ============== [PASSED] dma-buf-fence-unwrap ===============
[17:06:10] ================ dma-buf-resv (5 subtests) =================
[17:06:10] [PASSED] test_sanitycheck
[17:06:10] ===================== test_signaling  ======================
[17:06:10] [PASSED] kernel
[17:06:10] [PASSED] write
[17:06:10] [PASSED] read
[17:06:10] [PASSED] bookkeep
[17:06:10] ================= [PASSED] test_signaling ==================
[17:06:10] ====================== test_for_each  ======================
[17:06:10] [PASSED] kernel
[17:06:10] [PASSED] write
[17:06:10] [PASSED] read
[17:06:10] [PASSED] bookkeep
[17:06:10] ================== [PASSED] test_for_each ==================
[17:06:10] ================= test_for_each_unlocked  ==================
[17:06:10] [PASSED] kernel
[17:06:10] [PASSED] write
[17:06:10] [PASSED] read
[17:06:10] [PASSED] bookkeep
[17:06:10] ============= [PASSED] test_for_each_unlocked ==============
[17:06:10] ===================== test_get_fences  =====================
[17:06:10] [PASSED] kernel
[17:06:10] [PASSED] write
[17:06:10] [PASSED] read
[17:06:10] [PASSED] bookkeep
[17:06:10] ================= [PASSED] test_get_fences =================
[17:06:10] ================== [PASSED] dma-buf-resv ===================
[17:06:10] ============================================================
[17:06:10] Testing complete. Ran 54 tests: passed: 53, skipped: 1
[17:06:10] Elapsed time: 15.824s total, 1.804s configuring, 8.698s building, 5.275s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for drm/xe: Add wa_14025941587 to xe2, xe3 and xe3p platforms (rev9)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 1928 bytes --]

== Series Details ==

Series: drm/xe: Add wa_14025941587 to xe2, xe3 and xe3p platforms (rev9)
URL   : https://patchwork.freedesktop.org/series/167706/
State : success

== Summary ==

CI Bug Log - changes from xe-5715-0d30bc4f35590b6353a77f23e397ab2168b69673_BAT -> xe-pw-167706v9_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (13 -> 13)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-167706v9_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@xe_waitfence@engine:
    - bat-ptl-2:          [PASS][1] -> [FAIL][2] ([Intel XE#9109])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5715-0d30bc4f35590b6353a77f23e397ab2168b69673/bat-ptl-2/igt@xe_waitfence@engine.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/bat-ptl-2/igt@xe_waitfence@engine.html

  * igt@xe_waitfence@reltime:
    - bat-ptl-2:          [PASS][3] -> [FAIL][4] ([Intel XE#9115])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5715-0d30bc4f35590b6353a77f23e397ab2168b69673/bat-ptl-2/igt@xe_waitfence@reltime.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/bat-ptl-2/igt@xe_waitfence@reltime.html

  
  [Intel XE#9109]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9109
  [Intel XE#9115]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9115


Build changes
-------------

  * Linux: xe-5715-0d30bc4f35590b6353a77f23e397ab2168b69673 -> xe-pw-167706v9

  IGT_9088: 55a88d20e327d5c440cd3f3d661684fb83f29027 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-5715-0d30bc4f35590b6353a77f23e397ab2168b69673: 0d30bc4f35590b6353a77f23e397ab2168b69673
  xe-pw-167706v9: 167706v9

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/index.html

[-- Attachment #2: Type: text/html, Size: 2527 bytes --]

✓ Xe.CI.FULL: success for drm/xe: Add wa_14025941587 to xe2, xe3 and xe3p platforms (rev9)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 58191 bytes --]

== Series Details ==

Series: drm/xe: Add wa_14025941587 to xe2, xe3 and xe3p platforms (rev9)
URL   : https://patchwork.freedesktop.org/series/167706/
State : success

== Summary ==

CI Bug Log - changes from xe-5715-0d30bc4f35590b6353a77f23e397ab2168b69673_FULL -> xe-pw-167706v9_FULL
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-167706v9_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
    - shard-lnl:          NOTRUN -> [SKIP][1] ([Intel XE#3279])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-7/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html

  * igt@kms_big_fb@4-tiled-16bpp-rotate-270:
    - shard-bmg:          NOTRUN -> [SKIP][2] ([Intel XE#2327])
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-bmg-9/igt@kms_big_fb@4-tiled-16bpp-rotate-270.html

  * igt@kms_big_fb@4-tiled-8bpp-rotate-180:
    - shard-lnl:          NOTRUN -> [ABORT][3] ([Intel XE#4760])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-1/igt@kms_big_fb@4-tiled-8bpp-rotate-180.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-lnl:          NOTRUN -> [SKIP][4] ([Intel XE#1407]) +6 other tests skip
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-4/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
    - shard-lnl:          NOTRUN -> [SKIP][5] ([Intel XE#3658] / [Intel XE#7360])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-7/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html

  * igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-lnl:          NOTRUN -> [SKIP][6] ([Intel XE#7059] / [Intel XE#7085])
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-7/igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_big_fb@y-tiled-16bpp-rotate-0:
    - shard-bmg:          NOTRUN -> [SKIP][7] ([Intel XE#1124]) +3 other tests skip
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-bmg-4/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-lnl:          NOTRUN -> [SKIP][8] ([Intel XE#1124]) +11 other tests skip
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-7/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_bw@connected-linear-tiling-2-displays-target-3840x2160p:
    - shard-lnl:          NOTRUN -> [SKIP][9] ([Intel XE#7679])
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-2/igt@kms_bw@connected-linear-tiling-2-displays-target-3840x2160p.html

  * igt@kms_bw@connected-linear-tiling-4-displays-target-2160x1440p:
    - shard-lnl:          NOTRUN -> [SKIP][10] ([Intel XE#8365]) +1 other test skip
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-4/igt@kms_bw@connected-linear-tiling-4-displays-target-2160x1440p.html

  * igt@kms_bw@linear-tiling-2-displays-target-2560x1440p:
    - shard-lnl:          NOTRUN -> [SKIP][11] ([Intel XE#367])
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-7/igt@kms_bw@linear-tiling-2-displays-target-2560x1440p.html

  * igt@kms_bw@linear-tiling-4-displays-target-3840x2160p:
    - shard-bmg:          NOTRUN -> [SKIP][12] ([Intel XE#367]) +1 other test skip
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-bmg-4/igt@kms_bw@linear-tiling-4-displays-target-3840x2160p.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-a-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][13] ([Intel XE#2669] / [Intel XE#3433] / [Intel XE#7389]) +3 other tests skip
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-2/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-a-edp-1.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc:
    - shard-lnl:          NOTRUN -> [SKIP][14] ([Intel XE#3432]) +2 other tests skip
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-8/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc:
    - shard-bmg:          NOTRUN -> [SKIP][15] ([Intel XE#2887]) +2 other tests skip
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-bmg-9/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc.html

  * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs:
    - shard-lnl:          NOTRUN -> [SKIP][16] ([Intel XE#2887]) +17 other tests skip
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-7/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs.html

  * igt@kms_chamelium_audio@hdmi-audio-after-suspend:
    - shard-lnl:          NOTRUN -> [SKIP][17] ([Intel XE#2252])
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-4/igt@kms_chamelium_audio@hdmi-audio-after-suspend.html

  * igt@kms_chamelium_color@ctm-max:
    - shard-lnl:          NOTRUN -> [SKIP][18] ([Intel XE#306] / [Intel XE#7358]) +2 other tests skip
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-7/igt@kms_chamelium_color@ctm-max.html

  * igt@kms_chamelium_color_pipeline@plane-lut1d-lut1d:
    - shard-bmg:          NOTRUN -> [SKIP][19] ([Intel XE#7358])
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-bmg-9/igt@kms_chamelium_color_pipeline@plane-lut1d-lut1d.html

  * igt@kms_chamelium_color_pipeline@plane-lut1d-pre-ctm3x4:
    - shard-lnl:          NOTRUN -> [SKIP][20] ([Intel XE#7358])
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-8/igt@kms_chamelium_color_pipeline@plane-lut1d-pre-ctm3x4.html

  * igt@kms_chamelium_hpd@dp-hpd-enable-disable-mode:
    - shard-lnl:          NOTRUN -> [SKIP][21] ([Intel XE#373]) +7 other tests skip
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-7/igt@kms_chamelium_hpd@dp-hpd-enable-disable-mode.html

  * igt@kms_chamelium_hpd@hdmi-hpd-storm:
    - shard-bmg:          NOTRUN -> [SKIP][22] ([Intel XE#2252])
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-bmg-4/igt@kms_chamelium_hpd@hdmi-hpd-storm.html

  * igt@kms_chamelium_sharpness_filter@filter-basic:
    - shard-lnl:          NOTRUN -> [SKIP][23] ([Intel XE#6507])
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-2/igt@kms_chamelium_sharpness_filter@filter-basic.html

  * igt@kms_content_protection@content-type-change:
    - shard-lnl:          NOTRUN -> [SKIP][24] ([Intel XE#7642]) +2 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-4/igt@kms_content_protection@content-type-change.html

  * igt@kms_content_protection@dp-mst-type-1:
    - shard-lnl:          NOTRUN -> [SKIP][25] ([Intel XE#307] / [Intel XE#6974]) +1 other test skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-7/igt@kms_content_protection@dp-mst-type-1.html

  * igt@kms_cursor_crc@cursor-offscreen-512x512:
    - shard-lnl:          NOTRUN -> [SKIP][26] ([Intel XE#2321] / [Intel XE#7355]) +1 other test skip
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-7/igt@kms_cursor_crc@cursor-offscreen-512x512.html

  * igt@kms_cursor_crc@cursor-sliding-64x21:
    - shard-lnl:          NOTRUN -> [SKIP][27] ([Intel XE#1424]) +7 other tests skip
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-7/igt@kms_cursor_crc@cursor-sliding-64x21.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-legacy:
    - shard-lnl:          NOTRUN -> [SKIP][28] ([Intel XE#309] / [Intel XE#7343]) +4 other tests skip
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-7/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html

  * igt@kms_dp_link_training@uhbr-mst:
    - shard-lnl:          NOTRUN -> [SKIP][29] ([Intel XE#4354] / [Intel XE#7386])
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-7/igt@kms_dp_link_training@uhbr-mst.html

  * igt@kms_dp_link_training@uhbr-sst:
    - shard-lnl:          NOTRUN -> [SKIP][30] ([Intel XE#4354] / [Intel XE#5870])
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-8/igt@kms_dp_link_training@uhbr-sst.html

  * igt@kms_dsc@dsc-fractional-bpp-ultrajoiner:
    - shard-lnl:          NOTRUN -> [SKIP][31] ([Intel XE#8265]) +4 other tests skip
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-7/igt@kms_dsc@dsc-fractional-bpp-ultrajoiner.html

  * igt@kms_feature_discovery@dp-mst:
    - shard-bmg:          NOTRUN -> [SKIP][32] ([Intel XE#2375])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-bmg-4/igt@kms_feature_discovery@dp-mst.html

  * igt@kms_feature_discovery@hdr:
    - shard-lnl:          NOTRUN -> [SKIP][33] ([Intel XE#8586])
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-4/igt@kms_feature_discovery@hdr.html

  * igt@kms_flip@2x-blocking-absolute-wf_vblank-interruptible:
    - shard-lnl:          NOTRUN -> [SKIP][34] ([Intel XE#1421]) +6 other tests skip
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-7/igt@kms_flip@2x-blocking-absolute-wf_vblank-interruptible.html

  * igt@kms_flip@2x-dpms-vs-vblank-race@ad-dp2-hdmi-a3:
    - shard-bmg:          [PASS][35] -> [FAIL][36] ([Intel XE#3098]) +1 other test fail
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5715-0d30bc4f35590b6353a77f23e397ab2168b69673/shard-bmg-4/igt@kms_flip@2x-dpms-vs-vblank-race@ad-dp2-hdmi-a3.html
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-bmg-6/igt@kms_flip@2x-dpms-vs-vblank-race@ad-dp2-hdmi-a3.html

  * igt@kms_flip@flip-vs-expired-vblank@a-edp1:
    - shard-lnl:          NOTRUN -> [FAIL][37] ([Intel XE#301]) +1 other test fail
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling:
    - shard-bmg:          NOTRUN -> [SKIP][38] ([Intel XE#7178] / [Intel XE#7349])
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-bmg-9/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling:
    - shard-lnl:          NOTRUN -> [SKIP][39] ([Intel XE#1397] / [Intel XE#1745] / [Intel XE#7385] / [Intel XE#9144])
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-7/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling@pipe-a-default-mode:
    - shard-lnl:          NOTRUN -> [SKIP][40] ([Intel XE#1397] / [Intel XE#7385] / [Intel XE#9144])
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-7/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling:
    - shard-lnl:          NOTRUN -> [SKIP][41] ([Intel XE#7178] / [Intel XE#7351]) +5 other tests skip
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-8/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-p016-linear-to-p016-linear-reflect-x:
    - shard-lnl:          NOTRUN -> [SKIP][42] ([Intel XE#7179])
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-7/igt@kms_flip_scaled_crc@flip-p016-linear-to-p016-linear-reflect-x.html

  * igt@kms_frontbuffer_tracking@drrshdr-2p-primscrn-pri-indfb-draw-mmap-wc:
    - shard-lnl:          NOTRUN -> [SKIP][43] ([Intel XE#7905]) +62 other tests skip
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-4/igt@kms_frontbuffer_tracking@drrshdr-2p-primscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@drrshdr-slowdraw:
    - shard-bmg:          NOTRUN -> [SKIP][44] ([Intel XE#2311]) +15 other tests skip
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-bmg-4/igt@kms_frontbuffer_tracking@drrshdr-slowdraw.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][45] ([Intel XE#4141]) +3 other tests skip
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-bmg-9/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-blt:
    - shard-lnl:          NOTRUN -> [SKIP][46] ([Intel XE#656] / [Intel XE#7905]) +46 other tests skip
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-abgr161616f-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][47] ([Intel XE#7061] / [Intel XE#7356])
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-bmg-9/igt@kms_frontbuffer_tracking@fbc-abgr161616f-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-1p-offscreen-pri-indfb-draw-blt:
    - shard-lnl:          NOTRUN -> [SKIP][48] ([Intel XE#6312]) +25 other tests skip
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-4/igt@kms_frontbuffer_tracking@fbcdrrs-1p-offscreen-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-blt:
    - shard-lnl:          NOTRUN -> [SKIP][49] ([Intel XE#6312] / [Intel XE#651]) +10 other tests skip
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-4/igt@kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-tiling-y:
    - shard-lnl:          NOTRUN -> [SKIP][50] ([Intel XE#1469] / [Intel XE#7399])
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-7/igt@kms_frontbuffer_tracking@fbcdrrs-tiling-y.html

  * igt@kms_frontbuffer_tracking@fbchdr-abgr161616f-draw-mmap-wc:
    - shard-lnl:          NOTRUN -> [SKIP][51] ([Intel XE#7061]) +3 other tests skip
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-7/igt@kms_frontbuffer_tracking@fbchdr-abgr161616f-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-abgr161616f-draw-mmap-wc:
    - shard-lnl:          NOTRUN -> [SKIP][52] ([Intel XE#7061] / [Intel XE#7356]) +4 other tests skip
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-4/igt@kms_frontbuffer_tracking@fbcpsr-abgr161616f-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary:
    - shard-bmg:          NOTRUN -> [SKIP][53] ([Intel XE#2313]) +19 other tests skip
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-bmg-9/igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary.html

  * igt@kms_frontbuffer_tracking@psrhdr-1p-primscrn-indfb-plflip-blt:
    - shard-lnl:          NOTRUN -> [SKIP][54] ([Intel XE#7865]) +30 other tests skip
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-4/igt@kms_frontbuffer_tracking@psrhdr-1p-primscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@psrhdr-argb161616f-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][55] ([Intel XE#7061]) +1 other test skip
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-bmg-9/igt@kms_frontbuffer_tracking@psrhdr-argb161616f-draw-render.html

  * igt@kms_hdmi_inject@inject-audio:
    - shard-lnl:          NOTRUN -> [SKIP][56] ([Intel XE#1470] / [Intel XE#2853])
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-7/igt@kms_hdmi_inject@inject-audio.html

  * igt@kms_hdr@invalid-hdr:
    - shard-bmg:          [PASS][57] -> [SKIP][58] ([Intel XE#1503])
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5715-0d30bc4f35590b6353a77f23e397ab2168b69673/shard-bmg-8/igt@kms_hdr@invalid-hdr.html
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-bmg-1/igt@kms_hdr@invalid-hdr.html

  * igt@kms_hdr@static-toggle-dpms:
    - shard-lnl:          NOTRUN -> [SKIP][59] ([Intel XE#1503]) +1 other test skip
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-7/igt@kms_hdr@static-toggle-dpms.html

  * igt@kms_joiner@basic-max-non-joiner:
    - shard-lnl:          NOTRUN -> [SKIP][60] ([Intel XE#4298] / [Intel XE#5873])
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-2/igt@kms_joiner@basic-max-non-joiner.html

  * igt@kms_joiner@basic-ultra-joiner:
    - shard-lnl:          NOTRUN -> [SKIP][61] ([Intel XE#6900] / [Intel XE#7362])
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-7/igt@kms_joiner@basic-ultra-joiner.html

  * igt@kms_joiner@invalid-modeset-big-joiner:
    - shard-lnl:          NOTRUN -> [SKIP][62] ([Intel XE#6901])
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-4/igt@kms_joiner@invalid-modeset-big-joiner.html

  * igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-cc-modifier:
    - shard-lnl:          NOTRUN -> [SKIP][63] ([Intel XE#7283]) +6 other tests skip
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-4/igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-cc-modifier.html

  * igt@kms_plane@pixel-format-4-tiled-lnl-ccs-modifier-source-clamping:
    - shard-bmg:          NOTRUN -> [SKIP][64] ([Intel XE#7283]) +1 other test skip
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-bmg-9/igt@kms_plane@pixel-format-4-tiled-lnl-ccs-modifier-source-clamping.html

  * igt@kms_plane@pixel-format-4-tiled-lnl-ccs-modifier@pipe-a-plane-5:
    - shard-lnl:          NOTRUN -> [SKIP][65] ([Intel XE#8303]) +1 other test skip
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-7/igt@kms_plane@pixel-format-4-tiled-lnl-ccs-modifier@pipe-a-plane-5.html

  * igt@kms_plane_lowres@tiling-4@pipe-b-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][66] ([Intel XE#599] / [Intel XE#7382]) +7 other tests skip
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-8/igt@kms_plane_lowres@tiling-4@pipe-b-edp-1.html

  * igt@kms_plane_multiple@2x-tiling-4:
    - shard-lnl:          NOTRUN -> [SKIP][67] ([Intel XE#4596] / [Intel XE#5854])
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-7/igt@kms_plane_multiple@2x-tiling-4.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-b:
    - shard-lnl:          NOTRUN -> [SKIP][68] ([Intel XE#2763] / [Intel XE#6886]) +15 other tests skip
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-7/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-b.html

  * igt@kms_pm_dc@dc3co-framedrop-check@pr-xrgb8888:
    - shard-bmg:          NOTRUN -> [SKIP][69] ([Intel XE#8395] / [Intel XE#8396]) +1 other test skip
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-bmg-9/igt@kms_pm_dc@dc3co-framedrop-check@pr-xrgb8888.html

  * igt@kms_pm_dc@dc3co-framedrop-check@psr2-yuv420:
    - shard-bmg:          NOTRUN -> [SKIP][70] ([Intel XE#8396]) +1 other test skip
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-bmg-9/igt@kms_pm_dc@dc3co-framedrop-check@psr2-yuv420.html

  * igt@kms_pm_rpm@dpms-mode-unset-lpsp:
    - shard-bmg:          NOTRUN -> [SKIP][71] ([Intel XE#1439] / [Intel XE#7402] / [Intel XE#836])
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-bmg-9/igt@kms_pm_rpm@dpms-mode-unset-lpsp.html

  * igt@kms_pm_rpm@dpms-mode-unset-non-lpsp:
    - shard-lnl:          NOTRUN -> [SKIP][72] ([Intel XE#1439] / [Intel XE#7402] / [Intel XE#836])
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-7/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html

  * igt@kms_psr2_sf@fbc-pr-plane-move-sf-dmg-area:
    - shard-lnl:          NOTRUN -> [SKIP][73] ([Intel XE#2893] / [Intel XE#7304]) +4 other tests skip
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-8/igt@kms_psr2_sf@fbc-pr-plane-move-sf-dmg-area.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf@pipe-a-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][74] ([Intel XE#4608]) +1 other test skip
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-4/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf@pipe-a-edp-1.html

  * igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area:
    - shard-lnl:          NOTRUN -> [SKIP][75] ([Intel XE#2893] / [Intel XE#4608] / [Intel XE#7304]) +1 other test skip
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-7/igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area.html

  * igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area@pipe-b-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][76] ([Intel XE#4608] / [Intel XE#7304]) +1 other test skip
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-7/igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area@pipe-b-edp-1.html

  * igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf:
    - shard-bmg:          NOTRUN -> [SKIP][77] ([Intel XE#1489]) +1 other test skip
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-bmg-4/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf.html

  * igt@kms_psr2_su@page_flip-xrgb8888:
    - shard-bmg:          NOTRUN -> [SKIP][78] ([Intel XE#2387] / [Intel XE#7429])
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-bmg-9/igt@kms_psr2_su@page_flip-xrgb8888.html

  * igt@kms_psr@fbc-psr2-suspend:
    - shard-lnl:          NOTRUN -> [SKIP][79] ([Intel XE#1406] / [Intel XE#7345])
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-7/igt@kms_psr@fbc-psr2-suspend.html

  * igt@kms_psr@fbc-psr2-suspend@edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][80] ([Intel XE#1406] / [Intel XE#4609] / [Intel XE#7345])
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-7/igt@kms_psr@fbc-psr2-suspend@edp-1.html

  * igt@kms_psr@pr-primary-blt:
    - shard-lnl:          NOTRUN -> [SKIP][81] ([Intel XE#1406]) +7 other tests skip
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-8/igt@kms_psr@pr-primary-blt.html

  * igt@kms_psr@psr-sprite-plane-onoff:
    - shard-bmg:          NOTRUN -> [SKIP][82] ([Intel XE#2234] / [Intel XE#2850]) +3 other tests skip
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-bmg-4/igt@kms_psr@psr-sprite-plane-onoff.html

  * igt@kms_rotation_crc@primary-4-tiled-reflect-x-180:
    - shard-lnl:          NOTRUN -> [SKIP][83] ([Intel XE#3414] / [Intel XE#3904] / [Intel XE#7342])
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-7/igt@kms_rotation_crc@primary-4-tiled-reflect-x-180.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
    - shard-bmg:          NOTRUN -> [SKIP][84] ([Intel XE#2330] / [Intel XE#5813])
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-bmg-9/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html

  * igt@kms_setmode@invalid-clone-single-crtc:
    - shard-lnl:          NOTRUN -> [SKIP][85] ([Intel XE#1435] / [Intel XE#9142]) +1 other test skip
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-7/igt@kms_setmode@invalid-clone-single-crtc.html

  * igt@kms_sharpness_filter@filter-basic:
    - shard-bmg:          NOTRUN -> [SKIP][86] ([Intel XE#6503]) +1 other test skip
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-bmg-4/igt@kms_sharpness_filter@filter-basic.html

  * igt@kms_tv_load_detect@load-detect:
    - shard-lnl:          NOTRUN -> [SKIP][87] ([Intel XE#330] / [Intel XE#5857])
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-7/igt@kms_tv_load_detect@load-detect.html

  * igt@kms_vrr@flipline:
    - shard-bmg:          NOTRUN -> [SKIP][88] ([Intel XE#1499]) +1 other test skip
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-bmg-9/igt@kms_vrr@flipline.html

  * igt@kms_vrr@lobf-dc3co:
    - shard-lnl:          NOTRUN -> [SKIP][89] ([Intel XE#8397])
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-8/igt@kms_vrr@lobf-dc3co.html

  * igt@kms_vrr@negative-basic:
    - shard-lnl:          NOTRUN -> [SKIP][90] ([Intel XE#1499])
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-2/igt@kms_vrr@negative-basic.html

  * igt@xe_ccs@vm-bind-decompress:
    - shard-lnl:          NOTRUN -> [SKIP][91] ([Intel XE#7644])
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-8/igt@xe_ccs@vm-bind-decompress.html

  * igt@xe_compute@ccs-mode-basic:
    - shard-lnl:          NOTRUN -> [SKIP][92] ([Intel XE#1447] / [Intel XE#7471])
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-7/igt@xe_compute@ccs-mode-basic.html

  * igt@xe_compute_preempt@compute-preempt-many-vram-evict:
    - shard-lnl:          NOTRUN -> [SKIP][93] ([Intel XE#5191] / [Intel XE#7316] / [Intel XE#7346])
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-7/igt@xe_compute_preempt@compute-preempt-many-vram-evict.html

  * igt@xe_cw_post_sync@walker-post-sync:
    - shard-lnl:          NOTRUN -> [SKIP][94] ([Intel XE#8608])
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-2/igt@xe_cw_post_sync@walker-post-sync.html

  * igt@xe_evict@evict-beng-mixed-many-threads-small:
    - shard-bmg:          [PASS][95] -> [INCOMPLETE][96] ([Intel XE#6321] / [Intel XE#8355])
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5715-0d30bc4f35590b6353a77f23e397ab2168b69673/shard-bmg-2/igt@xe_evict@evict-beng-mixed-many-threads-small.html
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-bmg-3/igt@xe_evict@evict-beng-mixed-many-threads-small.html

  * igt@xe_evict@evict-beng-threads-large-multi-vm:
    - shard-lnl:          NOTRUN -> [SKIP][97] ([Intel XE#6540] / [Intel XE#688]) +11 other tests skip
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-7/igt@xe_evict@evict-beng-threads-large-multi-vm.html

  * igt@xe_exec_balancer@once-virtual-rebind:
    - shard-lnl:          NOTRUN -> [SKIP][98] ([Intel XE#7482]) +25 other tests skip
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-4/igt@xe_exec_balancer@once-virtual-rebind.html

  * igt@xe_exec_basic@multigpu-no-exec-basic:
    - shard-lnl:          NOTRUN -> [SKIP][99] ([Intel XE#1392]) +10 other tests skip
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-7/igt@xe_exec_basic@multigpu-no-exec-basic.html

  * igt@xe_exec_basic@multigpu-no-exec-basic-defer-bind:
    - shard-bmg:          NOTRUN -> [SKIP][100] ([Intel XE#2322] / [Intel XE#7372])
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-bmg-9/igt@xe_exec_basic@multigpu-no-exec-basic-defer-bind.html

  * igt@xe_exec_fault_mode@once-multi-queue-userptr-invalidate-race-imm:
    - shard-lnl:          NOTRUN -> [SKIP][101] ([Intel XE#8374]) +16 other tests skip
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-2/igt@xe_exec_fault_mode@once-multi-queue-userptr-invalidate-race-imm.html

  * igt@xe_exec_fault_mode@twice-multi-queue-userptr-imm:
    - shard-bmg:          NOTRUN -> [SKIP][102] ([Intel XE#8374]) +2 other tests skip
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-bmg-4/igt@xe_exec_fault_mode@twice-multi-queue-userptr-imm.html

  * igt@xe_exec_mix_modes@exec-multi-queue-spinner-interrupted-lr:
    - shard-lnl:          NOTRUN -> [SKIP][103] ([Intel XE#9003])
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-7/igt@xe_exec_mix_modes@exec-multi-queue-spinner-interrupted-lr.html

  * igt@xe_exec_multi_queue@many-queues-preempt-mode-fault-userptr-invalidate:
    - shard-lnl:          NOTRUN -> [SKIP][104] ([Intel XE#8364]) +37 other tests skip
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-7/igt@xe_exec_multi_queue@many-queues-preempt-mode-fault-userptr-invalidate.html

  * igt@xe_exec_multi_queue@two-queues-preempt-mode-dyn-priority-smem:
    - shard-bmg:          NOTRUN -> [SKIP][105] ([Intel XE#8364]) +7 other tests skip
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-bmg-9/igt@xe_exec_multi_queue@two-queues-preempt-mode-dyn-priority-smem.html

  * igt@xe_exec_reset@multi-queue-cancel:
    - shard-bmg:          NOTRUN -> [SKIP][106] ([Intel XE#8369])
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-bmg-9/igt@xe_exec_reset@multi-queue-cancel.html

  * igt@xe_exec_reset@multi-queue-long-spin-reuse-many-queue-switch:
    - shard-lnl:          NOTRUN -> [SKIP][107] ([Intel XE#8369]) +1 other test skip
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-4/igt@xe_exec_reset@multi-queue-long-spin-reuse-many-queue-switch.html

  * igt@xe_exec_threads@threads-hang-fd-userptr-invalidate-race:
    - shard-lnl:          NOTRUN -> [FAIL][108] ([Intel XE#9096])
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-7/igt@xe_exec_threads@threads-hang-fd-userptr-invalidate-race.html

  * igt@xe_exec_threads@threads-hang-userptr-invalidate-race:
    - shard-bmg:          [PASS][109] -> [FAIL][110] ([Intel XE#9096])
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5715-0d30bc4f35590b6353a77f23e397ab2168b69673/shard-bmg-5/igt@xe_exec_threads@threads-hang-userptr-invalidate-race.html
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-bmg-5/igt@xe_exec_threads@threads-hang-userptr-invalidate-race.html

  * igt@xe_exec_threads@threads-multi-queue-mixed-fd-userptr-invalidate:
    - shard-lnl:          NOTRUN -> [SKIP][111] ([Intel XE#8378]) +7 other tests skip
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-7/igt@xe_exec_threads@threads-multi-queue-mixed-fd-userptr-invalidate.html

  * igt@xe_exec_threads@threads-multi-queue-mixed-userptr-rebind:
    - shard-bmg:          NOTRUN -> [SKIP][112] ([Intel XE#8378]) +1 other test skip
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-bmg-9/igt@xe_exec_threads@threads-multi-queue-mixed-userptr-rebind.html

  * igt@xe_live_ktest@xe_eudebug:
    - shard-lnl:          NOTRUN -> [SKIP][113] ([Intel XE#2833])
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-8/igt@xe_live_ktest@xe_eudebug.html

  * igt@xe_media_fill@media-fill:
    - shard-lnl:          NOTRUN -> [SKIP][114] ([Intel XE#560] / [Intel XE#7321] / [Intel XE#7453])
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-2/igt@xe_media_fill@media-fill.html

  * igt@xe_mmap@pci-membarrier-bad-pagesize:
    - shard-lnl:          NOTRUN -> [SKIP][115] ([Intel XE#5100] / [Intel XE#7322] / [Intel XE#7408])
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-8/igt@xe_mmap@pci-membarrier-bad-pagesize.html

  * igt@xe_mmap@small-bar:
    - shard-bmg:          NOTRUN -> [SKIP][116] ([Intel XE#586] / [Intel XE#7323] / [Intel XE#7384])
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-bmg-9/igt@xe_mmap@small-bar.html

  * igt@xe_mmap@vram:
    - shard-lnl:          NOTRUN -> [SKIP][117] ([Intel XE#1416])
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-4/igt@xe_mmap@vram.html

  * igt@xe_module_load@load:
    - shard-lnl:          ([PASS][118], [PASS][119], [PASS][120], [PASS][121], [PASS][122], [PASS][123], [PASS][124], [PASS][125], [PASS][126], [PASS][127], [PASS][128], [PASS][129], [PASS][130], [PASS][131], [PASS][132], [PASS][133], [PASS][134], [PASS][135], [PASS][136]) -> ([SKIP][137], [PASS][138], [PASS][139], [PASS][140], [PASS][141], [PASS][142], [PASS][143], [PASS][144], [PASS][145], [PASS][146], [PASS][147], [PASS][148], [PASS][149], [PASS][150], [PASS][151], [PASS][152], [PASS][153], [PASS][154], [PASS][155], [PASS][156]) ([Intel XE#378] / [Intel XE#7405])
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5715-0d30bc4f35590b6353a77f23e397ab2168b69673/shard-lnl-7/igt@xe_module_load@load.html
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5715-0d30bc4f35590b6353a77f23e397ab2168b69673/shard-lnl-8/igt@xe_module_load@load.html
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5715-0d30bc4f35590b6353a77f23e397ab2168b69673/shard-lnl-4/igt@xe_module_load@load.html
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5715-0d30bc4f35590b6353a77f23e397ab2168b69673/shard-lnl-2/igt@xe_module_load@load.html
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5715-0d30bc4f35590b6353a77f23e397ab2168b69673/shard-lnl-4/igt@xe_module_load@load.html
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5715-0d30bc4f35590b6353a77f23e397ab2168b69673/shard-lnl-2/igt@xe_module_load@load.html
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5715-0d30bc4f35590b6353a77f23e397ab2168b69673/shard-lnl-2/igt@xe_module_load@load.html
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5715-0d30bc4f35590b6353a77f23e397ab2168b69673/shard-lnl-4/igt@xe_module_load@load.html
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5715-0d30bc4f35590b6353a77f23e397ab2168b69673/shard-lnl-8/igt@xe_module_load@load.html
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5715-0d30bc4f35590b6353a77f23e397ab2168b69673/shard-lnl-8/igt@xe_module_load@load.html
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5715-0d30bc4f35590b6353a77f23e397ab2168b69673/shard-lnl-7/igt@xe_module_load@load.html
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5715-0d30bc4f35590b6353a77f23e397ab2168b69673/shard-lnl-1/igt@xe_module_load@load.html
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5715-0d30bc4f35590b6353a77f23e397ab2168b69673/shard-lnl-1/igt@xe_module_load@load.html
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5715-0d30bc4f35590b6353a77f23e397ab2168b69673/shard-lnl-7/igt@xe_module_load@load.html
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5715-0d30bc4f35590b6353a77f23e397ab2168b69673/shard-lnl-1/igt@xe_module_load@load.html
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5715-0d30bc4f35590b6353a77f23e397ab2168b69673/shard-lnl-7/igt@xe_module_load@load.html
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5715-0d30bc4f35590b6353a77f23e397ab2168b69673/shard-lnl-1/igt@xe_module_load@load.html
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5715-0d30bc4f35590b6353a77f23e397ab2168b69673/shard-lnl-8/igt@xe_module_load@load.html
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5715-0d30bc4f35590b6353a77f23e397ab2168b69673/shard-lnl-2/igt@xe_module_load@load.html
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-7/igt@xe_module_load@load.html
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-7/igt@xe_module_load@load.html
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-7/igt@xe_module_load@load.html
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-1/igt@xe_module_load@load.html
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-4/igt@xe_module_load@load.html
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-7/igt@xe_module_load@load.html
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-2/igt@xe_module_load@load.html
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-1/igt@xe_module_load@load.html
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-1/igt@xe_module_load@load.html
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-1/igt@xe_module_load@load.html
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-8/igt@xe_module_load@load.html
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-8/igt@xe_module_load@load.html
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-7/igt@xe_module_load@load.html
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-2/igt@xe_module_load@load.html
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-8/igt@xe_module_load@load.html
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-4/igt@xe_module_load@load.html
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-4/igt@xe_module_load@load.html
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-4/igt@xe_module_load@load.html
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-2/igt@xe_module_load@load.html
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-2/igt@xe_module_load@load.html

  * igt@xe_multigpu_svm@mgpu-migration-basic:
    - shard-lnl:          NOTRUN -> [SKIP][157] ([Intel XE#6964]) +2 other tests skip
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-4/igt@xe_multigpu_svm@mgpu-migration-basic.html

  * igt@xe_multigpu_svm@mgpu-xgpu-access-basic:
    - shard-bmg:          NOTRUN -> [SKIP][158] ([Intel XE#6964])
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-bmg-9/igt@xe_multigpu_svm@mgpu-xgpu-access-basic.html

  * igt@xe_page_reclaim@prl-max-entries:
    - shard-lnl:          NOTRUN -> [SKIP][159] ([Intel XE#7793]) +3 other tests skip
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-2/igt@xe_page_reclaim@prl-max-entries.html

  * igt@xe_pat@pat-index-xehpc:
    - shard-lnl:          NOTRUN -> [SKIP][160] ([Intel XE#1420] / [Intel XE#2838] / [Intel XE#7590])
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-4/igt@xe_pat@pat-index-xehpc.html

  * igt@xe_pat@pat-sw-hw-reset-compare:
    - shard-lnl:          NOTRUN -> [FAIL][161] ([Intel XE#7695])
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-7/igt@xe_pat@pat-sw-hw-reset-compare.html

  * igt@xe_pat@xa-app-transient-media-on:
    - shard-bmg:          NOTRUN -> [SKIP][162] ([Intel XE#7590])
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-bmg-9/igt@xe_pat@xa-app-transient-media-on.html

  * igt@xe_pm@d3cold-i2c:
    - shard-lnl:          NOTRUN -> [SKIP][163] ([Intel XE#5694] / [Intel XE#7370])
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-2/igt@xe_pm@d3cold-i2c.html

  * igt@xe_pm@d3cold-mmap-system:
    - shard-lnl:          NOTRUN -> [SKIP][164] ([Intel XE#2284] / [Intel XE#366] / [Intel XE#7370])
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-7/igt@xe_pm@d3cold-mmap-system.html

  * igt@xe_pm@s3-basic-exec:
    - shard-lnl:          NOTRUN -> [SKIP][165] ([Intel XE#584] / [Intel XE#7369])
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-7/igt@xe_pm@s3-basic-exec.html

  * igt@xe_prefetch_fault@l2-prefetch-fault-svm:
    - shard-lnl:          NOTRUN -> [SKIP][166] ([Intel XE#8815])
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-7/igt@xe_prefetch_fault@l2-prefetch-fault-svm.html

  * igt@xe_pxp@pxp-stale-queue-post-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][167] ([Intel XE#4733] / [Intel XE#7417])
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-bmg-4/igt@xe_pxp@pxp-stale-queue-post-suspend.html

  * igt@xe_query@multigpu-query-cs-cycles:
    - shard-bmg:          NOTRUN -> [SKIP][168] ([Intel XE#944])
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-bmg-9/igt@xe_query@multigpu-query-cs-cycles.html

  * igt@xe_query@multigpu-query-uc-fw-version-guc:
    - shard-lnl:          NOTRUN -> [SKIP][169] ([Intel XE#944]) +2 other tests skip
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-7/igt@xe_query@multigpu-query-uc-fw-version-guc.html

  * igt@xe_sriov_admin@preempt-timeout-write-readback-vfs-disabled:
    - shard-lnl:          NOTRUN -> [SKIP][170] ([Intel XE#7174])
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-7/igt@xe_sriov_admin@preempt-timeout-write-readback-vfs-disabled.html

  * igt@xe_sriov_auto_provisioning@fair-allocation:
    - shard-lnl:          NOTRUN -> [SKIP][171] ([Intel XE#4130] / [Intel XE#7366])
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-8/igt@xe_sriov_auto_provisioning@fair-allocation.html

  * igt@xe_sriov_scheduling@nonpreempt-engine-resets-normal-priority:
    - shard-lnl:          NOTRUN -> [SKIP][172] ([Intel XE#8339]) +1 other test skip
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-8/igt@xe_sriov_scheduling@nonpreempt-engine-resets-normal-priority.html

  * igt@xe_sriov_vram@vf-access-beyond:
    - shard-lnl:          NOTRUN -> [SKIP][173] ([Intel XE#6376] / [Intel XE#7330] / [Intel XE#7422]) +1 other test skip
   [173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-4/igt@xe_sriov_vram@vf-access-beyond.html

  * igt@xe_vm@overcommit-fault-vram-lr:
    - shard-lnl:          NOTRUN -> [SKIP][174] ([Intel XE#7892])
   [174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-2/igt@xe_vm@overcommit-fault-vram-lr.html

  
#### Possible fixes ####

  * igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size:
    - shard-bmg:          [DMESG-WARN][175] ([Intel XE#8329]) -> [PASS][176]
   [175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5715-0d30bc4f35590b6353a77f23e397ab2168b69673/shard-bmg-2/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html
   [176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-bmg-10/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
    - shard-lnl:          [FAIL][177] ([Intel XE#301]) -> [PASS][178]
   [177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5715-0d30bc4f35590b6353a77f23e397ab2168b69673/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
   [178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html

  * igt@xe_exec_threads@threads-hang-fd-userptr-invalidate-race:
    - shard-bmg:          [FAIL][179] ([Intel XE#9096]) -> [PASS][180]
   [179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5715-0d30bc4f35590b6353a77f23e397ab2168b69673/shard-bmg-5/igt@xe_exec_threads@threads-hang-fd-userptr-invalidate-race.html
   [180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-bmg-5/igt@xe_exec_threads@threads-hang-fd-userptr-invalidate-race.html

  * igt@xe_fault_injection@vm-bind-fail-xe_sync_entry_parse:
    - shard-bmg:          [ABORT][181] ([Intel XE#8007]) -> [PASS][182] +1 other test pass
   [181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5715-0d30bc4f35590b6353a77f23e397ab2168b69673/shard-bmg-9/igt@xe_fault_injection@vm-bind-fail-xe_sync_entry_parse.html
   [182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-bmg-9/igt@xe_fault_injection@vm-bind-fail-xe_sync_entry_parse.html

  
#### Warnings ####

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-bmg:          [SKIP][183] ([Intel XE#2509] / [Intel XE#7437]) -> [SKIP][184] ([Intel XE#2426] / [Intel XE#5848])
   [183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5715-0d30bc4f35590b6353a77f23e397ab2168b69673/shard-bmg-4/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-bmg-6/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@xe_exec_reset@gt-reset-fault-injection:
    - shard-lnl:          [ABORT][185] ([Intel XE#9145]) -> [DMESG-WARN][186] ([Intel XE#9130])
   [185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5715-0d30bc4f35590b6353a77f23e397ab2168b69673/shard-lnl-2/igt@xe_exec_reset@gt-reset-fault-injection.html
   [186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/shard-lnl-1/igt@xe_exec_reset@gt-reset-fault-injection.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1397
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
  [Intel XE#1416]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1416
  [Intel XE#1420]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1420
  [Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
  [Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
  [Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
  [Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
  [Intel XE#1447]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1447
  [Intel XE#1469]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1469
  [Intel XE#1470]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1470
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2330
  [Intel XE#2375]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2375
  [Intel XE#2387]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2387
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
  [Intel XE#2669]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2669
  [Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
  [Intel XE#2833]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2833
  [Intel XE#2838]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2838
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2853]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2853
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/307
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#3098]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3098
  [Intel XE#3279]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3279
  [Intel XE#330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/330
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
  [Intel XE#3433]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3433
  [Intel XE#3658]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3658
  [Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#4130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4130
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4298]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4298
  [Intel XE#4354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4354
  [Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
  [Intel XE#4608]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4608
  [Intel XE#4609]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4609
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#4760]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4760
  [Intel XE#5100]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5100
  [Intel XE#5191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5191
  [Intel XE#560]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/560
  [Intel XE#5694]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5694
  [Intel XE#5813]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5813
  [Intel XE#584]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/584
  [Intel XE#5848]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5848
  [Intel XE#5854]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5854
  [Intel XE#5857]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5857
  [Intel XE#586]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/586
  [Intel XE#5870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5870
  [Intel XE#5873]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5873
  [Intel XE#599]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/599
  [Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
  [Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
  [Intel XE#6376]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6376
  [Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
  [Intel XE#6507]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6507
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#6540]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6540
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#6886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6886
  [Intel XE#6900]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6900
  [Intel XE#6901]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6901
  [Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
  [Intel XE#6974]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6974
  [Intel XE#7059]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7059
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7085]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7085
  [Intel XE#7174]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7174
  [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
  [Intel XE#7179]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7179
  [Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
  [Intel XE#7304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7304
  [Intel XE#7316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7316
  [Intel XE#7321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7321
  [Intel XE#7322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7322
  [Intel XE#7323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7323
  [Intel XE#7330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7330
  [Intel XE#7342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7342
  [Intel XE#7343]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7343
  [Intel XE#7345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7345
  [Intel XE#7346]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7346
  [Intel XE#7349]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7349
  [Intel XE#7351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7351
  [Intel XE#7355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7355
  [Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
  [Intel XE#7358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7358
  [Intel XE#7360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7360
  [Intel XE#7362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7362
  [Intel XE#7366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7366
  [Intel XE#7369]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7369
  [Intel XE#7370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7370
  [Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
  [Intel XE#7382]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7382
  [Intel XE#7384]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7384
  [Intel XE#7385]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7385
  [Intel XE#7386]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7386
  [Intel XE#7389]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7389
  [Intel XE#7399]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7399
  [Intel XE#7402]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7402
  [Intel XE#7405]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7405
  [Intel XE#7408]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7408
  [Intel XE#7417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7417
  [Intel XE#7422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7422
  [Intel XE#7429]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7429
  [Intel XE#7437]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7437
  [Intel XE#7453]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7453
  [Intel XE#7471]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7471
  [Intel XE#7482]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7482
  [Intel XE#7590]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7590
  [Intel XE#7642]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7642
  [Intel XE#7644]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7644
  [Intel XE#7679]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7679
  [Intel XE#7695]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7695
  [Intel XE#7793]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7793
  [Intel XE#7865]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7865
  [Intel XE#7892]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7892
  [Intel XE#7905]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7905
  [Intel XE#8007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8007
  [Intel XE#8265]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8265
  [Intel XE#8303]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8303
  [Intel XE#8329]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8329
  [Intel XE#8339]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8339
  [Intel XE#8355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8355
  [Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
  [Intel XE#8364]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8364
  [Intel XE#8365]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8365
  [Intel XE#8369]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8369
  [Intel XE#8374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8374
  [Intel XE#8378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8378
  [Intel XE#8395]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8395
  [Intel XE#8396]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8396
  [Intel XE#8397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8397
  [Intel XE#8586]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8586
  [Intel XE#8608]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8608
  [Intel XE#8815]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8815
  [Intel XE#9003]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9003
  [Intel XE#9096]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9096
  [Intel XE#9130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9130
  [Intel XE#9142]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9142
  [Intel XE#9144]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9144
  [Intel XE#9145]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9145
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * Linux: xe-5715-0d30bc4f35590b6353a77f23e397ab2168b69673 -> xe-pw-167706v9

  IGT_9088: 55a88d20e327d5c440cd3f3d661684fb83f29027 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-5715-0d30bc4f35590b6353a77f23e397ab2168b69673: 0d30bc4f35590b6353a77f23e397ab2168b69673
  xe-pw-167706v9: 167706v9

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167706v9/index.html

[-- Attachment #2: Type: text/html, Size: 65228 bytes --]

[PATCH 0/2] drm/xe: Add wa_14025941587 to xe2, xe3 and xe3p platforms

[tilak.tirumalesh.tangudu]

From: Tangudu Tilak Tirumalesh <tilak.tirumalesh.tangudu@intel.com>

This series adds Wa_14025941587 (minimum IDLEDLY floor) for Xe2, Xe3 and
Xe3p and hardens the shared adjust_idledly() helper it builds on.

Patch 1 fixes three pre-existing corner cases in adjust_idledly() that
can panic or misprogram RING_IDLEDLY.
(timestamp_base == 0 divide-by-zero, IDLE_WAIT_TIME == 0 underflow, and
u32 overflow in the tick<->ns conversions).

Patch 2 applies Wa_14025941587 on top of the hardened helper.

Patch1 v2:
Avoid redundant warn for unknown crystal clock.

Patch2 v8:
Round up (DIV_ROUND_UP_ULL) the Wa_14025941587 minimum conversion instead,
so the tick-quantized delay cannot round back below 5 us.

Tangudu Tilak Tirumalesh (2):
  drm/xe: harden adjust_idledly() against divide-by-zero and overflow
  drm/xe: Add wa_14025941587 to xe2, xe3 and xe3p platforms

 drivers/gpu/drm/xe/xe_guc_ads.c    |  2 +-
 drivers/gpu/drm/xe/xe_hw_engine.c  | 73 +++++++++++++++++++++++++-----
 drivers/gpu/drm/xe/xe_wa_oob.rules |  2 +
 3 files changed, 65 insertions(+), 12 deletions(-)

-- 
2.46.0

[PATCH 2/2] drm/xe: Add wa_14025941587 to xe2, xe3 and xe3p platforms

[tilak.tirumalesh.tangudu]

From: Tangudu Tilak Tirumalesh <tilak.tirumalesh.tangudu@intel.com>

Avoid programming the IDLEDLY timer to less than 5 microseconds.
Apply wa_14025941587 to Graphics Versions 20.01 to 35.11
and Media Versions 13.01 to 35.03

v2: Use xe_rtp_match_not_sriov_vf, move to local variable
    Remove warn and other knits            - Matt R

v3: Add verbose comment - Tejas

v4: Restore IDLE_DLY register on engine reset.
    Add it to GUC save-restore list. -Vivek

v5: Extend WA to Media Versions 13.01 to 35.03 - Vinay

v6: Avoid clearing inhibit switch - Bala
    Refactor code accordingly by adding idle_reg_val.

v7: Rebased with the divide-by-zero/overflow guards living in
    a separate hardening patch.

v8: Preserve the Wa_16023105232 floor (DIV_ROUND_DOWN_ULL) and the
    maxcnt == 0 guard from the hardening patch. Round up
    (DIV_ROUND_UP_ULL) the Wa_14025941587 minimum conversion instead,
    so the tick-quantized delay cannot round back below 5 us.

Assisted-by: GitHub_Copilot:claude-opus-4.8
Signed-off-by: Tangudu Tilak Tirumalesh <tilak.tirumalesh.tangudu@intel.com>
Reviewed-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
---
 drivers/gpu/drm/xe/xe_guc_ads.c    |  2 +-
 drivers/gpu/drm/xe/xe_hw_engine.c  | 69 ++++++++++++++++++++++++------
 drivers/gpu/drm/xe/xe_wa_oob.rules |  2 +
 3 files changed, 60 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
index ff8eee3831aa..58a3f6293ce4 100644
--- a/drivers/gpu/drm/xe/xe_guc_ads.c
+++ b/drivers/gpu/drm/xe/xe_guc_ads.c
@@ -864,7 +864,7 @@ static unsigned int guc_mmio_regset_write(struct xe_guc_ads *ads,
 		}
 	}
 
-	if (XE_GT_WA(hwe->gt, 16023105232))
+	if (XE_GT_WA(hwe->gt, 16023105232) || XE_GT_WA(hwe->gt, 14025941587))
 		guc_mmio_regset_write_one(ads, regset_map,
 					  RING_IDLEDLY(hwe->mmio_base),
 					  count++);
diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index e5e761c33fa6..a0c29aacbbfe 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -588,31 +588,76 @@ static void hw_engine_init_early(struct xe_gt *gt, struct xe_hw_engine *hwe,
 static void adjust_idledly(struct xe_hw_engine *hwe)
 {
 	struct xe_gt *gt = hwe->gt;
-	u32 idledly, maxcnt;
+	u32 idledly, idledly_reg_val, maxcnt;
 	u32 idledly_units_ps = 8 * gt->info.timestamp_base;
 	u32 maxcnt_units_ns = 640;
-	bool inhibit_switch = 0;
+	bool inhibit_switch = false;
+	bool wa_applied = false;
+	bool clamped_below_maxcnt = false;
+
+	if ((!IS_SRIOV_VF(gt_to_xe(hwe->gt)) && XE_GT_WA(gt, 16023105232)) ||
+	    XE_GT_WA(gt, 14025941587)) {
+		u32 mincnt_idledly_ns = 5000;
 
-	if (!IS_SRIOV_VF(gt_to_xe(hwe->gt)) && XE_GT_WA(gt, 16023105232)) {
 		/* xe_gt_clock_init() warns and zeroes timestamp_base on unknown crystal clock. */
 		if (!idledly_units_ps)
 			return;
 
-		idledly = xe_mmio_read32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base));
+		idledly_reg_val = xe_mmio_read32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base));
 		maxcnt = xe_mmio_read32(&gt->mmio, RING_PWRCTX_MAXCNT(hwe->mmio_base));
 
-		inhibit_switch = idledly & INHIBIT_SWITCH_UNTIL_PREEMPTED;
-		idledly = REG_FIELD_GET(IDLE_DELAY, idledly);
+		inhibit_switch = idledly_reg_val & INHIBIT_SWITCH_UNTIL_PREEMPTED;
+		idledly = REG_FIELD_GET(IDLE_DELAY, idledly_reg_val);
 		idledly = DIV_ROUND_CLOSEST_ULL((u64)idledly * idledly_units_ps, 1000);
 		maxcnt = REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt);
 		maxcnt *= maxcnt_units_ns;
 
-		if (xe_gt_WARN_ON(gt, idledly >= maxcnt || inhibit_switch)) {
-			/* Floor below maxcnt; write 0 to still clear the inhibit bit. */
-			idledly = maxcnt ?
-				DIV_ROUND_DOWN_ULL((u64)(maxcnt - 1) * 1000,
-						   idledly_units_ps) : 0;
-			xe_mmio_write32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base), idledly);
+		/*
+		 * Wa_14025941587 is applied before Wa_16023105232, which has
+		 * higher priority; the two are not expected to conflict.
+		 */
+		if (XE_GT_WA(gt, 14025941587) &&
+		    idledly < mincnt_idledly_ns) {
+			idledly = mincnt_idledly_ns;
+			wa_applied = true;
+		}
+
+		if (XE_GT_WA(gt, 16023105232) &&
+		    xe_gt_WARN_ON(gt, idledly >= maxcnt || inhibit_switch)) {
+			/* maxcnt may be 0 if IDLE_WAIT_TIME is unprogrammed. */
+			idledly = maxcnt ? maxcnt - 1 : 0;
+			clamped_below_maxcnt = true;
+			wa_applied = true;
+			/* inhibit_switch override to keep
+			 * semantics of Wa_16023105232
+			 */
+			if (inhibit_switch)
+				idledly_reg_val &= ~INHIBIT_SWITCH_UNTIL_PREEMPTED;
+		}
+
+		if (wa_applied) {
+			u32 idledly_ticks;
+
+			/*
+			 * Wa_16023105232 requires idledly < maxcnt, so floor
+			 * that clamp; otherwise round up to guarantee the
+			 * Wa_14025941587 minimum survives tick quantization.
+			 */
+			if (clamped_below_maxcnt)
+				idledly_ticks = DIV_ROUND_DOWN_ULL((u64)idledly * 1000,
+								   idledly_units_ps);
+			else
+				idledly_ticks = DIV_ROUND_UP_ULL((u64)idledly * 1000,
+								 idledly_units_ps);
+
+			idledly_reg_val &= ~IDLE_DELAY;
+			idledly_reg_val |= REG_FIELD_PREP(IDLE_DELAY, idledly_ticks);
+			xe_gt_dbg(gt, "idledly %s: set %u max=%u inh=%u ts=%u\n",
+				  hwe->name, idledly, maxcnt,
+				  !!inhibit_switch, gt->info.timestamp_base);
+			xe_mmio_write32(&gt->mmio,
+					RING_IDLEDLY(hwe->mmio_base),
+					idledly_reg_val);
 		}
 	}
 }
diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
index dd69ad07f7a9..3001155f8d09 100644
--- a/drivers/gpu/drm/xe/xe_wa_oob.rules
+++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
@@ -72,3 +72,5 @@
 16029897822	MEDIA_VERSION(3500)
 		GRAPHICS_VERSION(3510)
 14027054324	GRAPHICS_VERSION(3511)
+14025941587	GRAPHICS_VERSION_RANGE(2001, 3511), FUNC(xe_rtp_match_not_sriov_vf)
+		MEDIA_VERSION_RANGE(1301, 3503), FUNC(xe_rtp_match_not_sriov_vf)
-- 
2.46.0

Re: [PATCH 2/2] drm/xe: Add wa_14025941587 to xe2, xe3 and xe3p platforms

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] xe: tick quantization bypasses Wa_16023105232 upper bound check
--

commit 0bd0a59b09bd7c0fa136c7d141c58df4e531535b
Author: Tangudu Tilak Tirumalesh <tilak.tirumalesh.tangudu@intel.com>

    drm/xe: Add wa_14025941587 to xe2, xe3 and xe3p platforms
    
    Avoid programming the IDLEDLY timer to less than 5 microseconds.
    Apply wa_14025941587 to Graphics Versions 20.01 to 35.11
    and Media Versions 13.01 to 35.03

> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
> index e5e761c33fa68..a0c29aacbbfe1 100644
> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
[ ... ]
> @@ -588,31 +588,76 @@ static void hw_engine_init_early(struct xe_gt *gt, struct xe_hw_engine *hwe,
>  static void adjust_idledly(struct xe_hw_engine *hwe)
>  {
[ ... ]
> +		if (XE_GT_WA(gt, 16023105232) &&
> +		    xe_gt_WARN_ON(gt, idledly >= maxcnt || inhibit_switch)) {

[Severity: Medium]
Does this upper bound check fail to account for the subsequent tick
quantization?

If maxcnt is slightly larger than the 5000ns minimum (e.g., 5120ns),
the idledly >= maxcnt check will evaluate to false and the value won't
be clamped.

> +			/* maxcnt may be 0 if IDLE_WAIT_TIME is unprogrammed. */
> +			idledly = maxcnt ? maxcnt - 1 : 0;
> +			clamped_below_maxcnt = true;
> +			wa_applied = true;
> +			/* inhibit_switch override to keep
> +			 * semantics of Wa_16023105232
> +			 */
> +			if (inhibit_switch)
> +				idledly_reg_val &= ~INHIBIT_SWITCH_UNTIL_PREEMPTED;
> +		}
> +
> +		if (wa_applied) {
> +			u32 idledly_ticks;
> +
> +			/*
> +			 * Wa_16023105232 requires idledly < maxcnt, so floor
> +			 * that clamp; otherwise round up to guarantee the
> +			 * Wa_14025941587 minimum survives tick quantization.
> +			 */
> +			if (clamped_below_maxcnt)
> +				idledly_ticks = DIV_ROUND_DOWN_ULL((u64)idledly * 1000,
> +								   idledly_units_ps);
> +			else
> +				idledly_ticks = DIV_ROUND_UP_ULL((u64)idledly * 1000,
> +								 idledly_units_ps);

[Severity: Medium]
Will this round-up push the programmed delay above maxcnt, silently
violating Wa_16023105232?

If the check above bypassed clamping (because 5000 < 5120), we take the else
branch here. Using DIV_ROUND_UP_ULL, 5000ns can round up by an extra tick. For
instance, on a 19.2MHz clock (416.66ns per tick), 5000ns rounds up to 13 ticks
(5416ns).

Since 5416ns > 5120ns, the programmed IDLE_DELAY will end up exceeding
IDLE_WAIT_TIME in the hardware.

> +
> +			idledly_reg_val &= ~IDLE_DELAY;
> +			idledly_reg_val |= REG_FIELD_PREP(IDLE_DELAY, idledly_ticks);

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260915111314.564847-1-tilak.tirumalesh.tangudu@intel.com?part=2

RE: [PATCH 2/2] drm/xe: Add wa_14025941587 to xe2, xe3 and xe3p platforms

[Tangudu, Tilak Tirumalesh]

> -----Original Message-----
> From: sashiko-bot@kernel.org <sashiko-bot@kernel.org>
> Sent: 15 September 2026 16:55
> To: Tangudu, Tilak Tirumalesh <tilak.tirumalesh.tangudu@intel.com>
> Cc: intel-xe@lists.freedesktop.org
> Subject: Re: [PATCH 2/2] drm/xe: Add wa_14025941587 to xe2, xe3 and xe3p
> platforms
> 
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s)
> to consider:
> - [Medium] xe: tick quantization bypasses Wa_16023105232 upper bound
> check
> --
> 
> commit 0bd0a59b09bd7c0fa136c7d141c58df4e531535b
> Author: Tangudu Tilak Tirumalesh <tilak.tirumalesh.tangudu@intel.com>
> 
>     drm/xe: Add wa_14025941587 to xe2, xe3 and xe3p platforms
> 
>     Avoid programming the IDLEDLY timer to less than 5 microseconds.
>     Apply wa_14025941587 to Graphics Versions 20.01 to 35.11
>     and Media Versions 13.01 to 35.03
> 
> > diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c
> > b/drivers/gpu/drm/xe/xe_hw_engine.c
> > index e5e761c33fa68..a0c29aacbbfe1 100644
> > --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> > +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
> [ ... ]
> > @@ -588,31 +588,76 @@ static void hw_engine_init_early(struct xe_gt
> > *gt, struct xe_hw_engine *hwe,  static void adjust_idledly(struct
> > xe_hw_engine *hwe)  {
> [ ... ]
> > +		if (XE_GT_WA(gt, 16023105232) &&
> > +		    xe_gt_WARN_ON(gt, idledly >= maxcnt || inhibit_switch)) {
> 
> [Severity: Medium]
> Does this upper bound check fail to account for the subsequent tick
> quantization?
> 
> If maxcnt is slightly larger than the 5000ns minimum (e.g., 5120ns), the idledly
> >= maxcnt check will evaluate to false and the value won't be clamped.

The idledly >= maxcnt comparison is done in the nanosecond domain, and Wa_16023105232 is intentionally checked
after the Wa_14025941587 minimum so it retains priority. The missed-clamp case only arises if IDLE_WAIT_TIME is
configured within about one tick of the 5 µs floor — a configuration these platforms don't use, so it isn't 
reachable here

> 
> > +			/* maxcnt may be 0 if IDLE_WAIT_TIME is
> unprogrammed. */
> > +			idledly = maxcnt ? maxcnt - 1 : 0;
> > +			clamped_below_maxcnt = true;
> > +			wa_applied = true;
> > +			/* inhibit_switch override to keep
> > +			 * semantics of Wa_16023105232
> > +			 */
> > +			if (inhibit_switch)
> > +				idledly_reg_val &=
> ~INHIBIT_SWITCH_UNTIL_PREEMPTED;
> > +		}
> > +
> > +		if (wa_applied) {
> > +			u32 idledly_ticks;
> > +
> > +			/*
> > +			 * Wa_16023105232 requires idledly < maxcnt, so
> floor
> > +			 * that clamp; otherwise round up to guarantee the
> > +			 * Wa_14025941587 minimum survives tick
> quantization.
> > +			 */
> > +			if (clamped_below_maxcnt)
> > +				idledly_ticks =
> DIV_ROUND_DOWN_ULL((u64)idledly * 1000,
> > +
> idledly_units_ps);
> > +			else
> > +				idledly_ticks =
> DIV_ROUND_UP_ULL((u64)idledly * 1000,
> > +
> idledly_units_ps);
> 
> [Severity: Medium]
> Will this round-up push the programmed delay above maxcnt, silently
> violating Wa_16023105232?
> 
> If the check above bypassed clamping (because 5000 < 5120), we take the else
> branch here. Using DIV_ROUND_UP_ULL, 5000ns can round up by an extra
> tick. For instance, on a 19.2MHz clock (416.66ns per tick), 5000ns rounds up
> to 13 ticks (5416ns).
> 
> Since 5416ns > 5120ns, the programmed IDLE_DELAY will end up exceeding
> IDLE_WAIT_TIME in the hardware.

Right that DIV_ROUND_UP_ULL bumps 5000 ns to the next whole tick — the round-up is deliberate so the Wa_14025941587  5 µs minimum survives tick quantization rather than dropping below it. 
This can only exceed IDLE_WAIT_TIME if  IDLE_WAIT_TIME itself sits within one tick of 5 µs, which is the same precondition as the previous comment and  not a configuration these platforms use.
 So it can't violate Wa_16023105232 in practice.


> 
> > +
> > +			idledly_reg_val &= ~IDLE_DELAY;
> > +			idledly_reg_val |= REG_FIELD_PREP(IDLE_DELAY,
> idledly_ticks);
> 
> --
> Sashiko AI review · https://sashiko.dev/#/patchset/20260915111314.564847-
> 1-tilak.tirumalesh.tangudu@intel.com?part=2

[PATCH 0/2] drm/xe: Add wa_14025941587 to xe2, xe3 and xe3p platforms

[tilak.tirumalesh.tangudu]

From: Tangudu Tilak Tirumalesh <tilak.tirumalesh.tangudu@intel.com>

This series adds Wa_14025941587 (minimum IDLEDLY floor) for Xe2, Xe3 and
Xe3p and hardens the shared adjust_idledly() helper it builds on.

Patch 1 fixes three pre-existing corner cases in adjust_idledly() that
can panic or misprogram RING_IDLEDLY.
(timestamp_base == 0 divide-by-zero, IDLE_WAIT_TIME == 0 underflow, and
u32 overflow in the tick<->ns conversions).

Patch 2 applies Wa_14025941587 on top of the hardened helper.

Tangudu Tilak Tirumalesh (2):
  drm/xe: harden adjust_idledly() against divide-by-zero and overflow
  drm/xe: Add wa_14025941587 to xe2, xe3 and xe3p platforms

 drivers/gpu/drm/xe/xe_guc_ads.c    |  2 +-
 drivers/gpu/drm/xe/xe_hw_engine.c  | 65 +++++++++++++++++++++++++-----
 drivers/gpu/drm/xe/xe_wa_oob.rules |  2 +
 3 files changed, 57 insertions(+), 12 deletions(-)

-- 
2.46.0

[PATCH 2/2] drm/xe: Add wa_14025941587 to xe2, xe3 and xe3p platforms

[tilak.tirumalesh.tangudu]

From: Tangudu Tilak Tirumalesh <tilak.tirumalesh.tangudu@intel.com>

Avoid programming the IDLEDLY timer to less than 5 microseconds.
Apply wa_14025941587 to Graphics Versions 20.01 to 35.11
and Media Versions 13.01 to 35.03

v2: Use xe_rtp_match_not_sriov_vf, move to local variable
    Remove warn and other knits            - Matt R

v3: Add verbose comment - Tejas

v4: Restore IDLE_DLY register on engine reset.
    Add it to GUC save-restore list. -Vivek

v5: Extend WA to Media Versions 13.01 to 35.03 - Vinay

v6: Avoid clearing inhibit switch - Bala
    Refactor code accordingly by adding idle_reg_val.

v7: Rebased with the divide-by-zero/overflow guards living in
    a separate hardening patch.

Signed-off-by: Tangudu Tilak Tirumalesh <tilak.tirumalesh.tangudu@intel.com>
Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
---
 drivers/gpu/drm/xe/xe_guc_ads.c    |  2 +-
 drivers/gpu/drm/xe/xe_hw_engine.c  | 52 ++++++++++++++++++++++++------
 drivers/gpu/drm/xe/xe_wa_oob.rules |  2 ++
 3 files changed, 45 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
index ff8eee3831aa..58a3f6293ce4 100644
--- a/drivers/gpu/drm/xe/xe_guc_ads.c
+++ b/drivers/gpu/drm/xe/xe_guc_ads.c
@@ -864,7 +864,7 @@ static unsigned int guc_mmio_regset_write(struct xe_guc_ads *ads,
 		}
 	}
 
-	if (XE_GT_WA(hwe->gt, 16023105232))
+	if (XE_GT_WA(hwe->gt, 16023105232) || XE_GT_WA(hwe->gt, 14025941587))
 		guc_mmio_regset_write_one(ads, regset_map,
 					  RING_IDLEDLY(hwe->mmio_base),
 					  count++);
diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index 6ffb0ece0561..033740c34aa6 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -588,23 +588,27 @@ static void hw_engine_init_early(struct xe_gt *gt, struct xe_hw_engine *hwe,
 static void adjust_idledly(struct xe_hw_engine *hwe)
 {
 	struct xe_gt *gt = hwe->gt;
-	u32 idledly, maxcnt;
+	u32 idledly, idledly_reg_val, maxcnt;
 	u32 idledly_units_ps = 8 * gt->info.timestamp_base;
 	u32 maxcnt_units_ns = 640;
-	bool inhibit_switch = 0;
+	bool inhibit_switch = false;
+	bool wa_applied = false;
+
+	if ((!IS_SRIOV_VF(gt_to_xe(hwe->gt)) && XE_GT_WA(gt, 16023105232)) ||
+	    XE_GT_WA(gt, 14025941587)) {
+		u32 mincnt_idledly_ns = 5000;
 
-	if (!IS_SRIOV_VF(gt_to_xe(hwe->gt)) && XE_GT_WA(gt, 16023105232)) {
 		/* xe_gt_clock_init() zeroes timestamp_base on unknown crystal clock. */
 		if (!idledly_units_ps) {
 			xe_gt_warn(gt, "idledly WA skipped: timestamp_base is 0\n");
 			return;
 		}
 
-		idledly = xe_mmio_read32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base));
+		idledly_reg_val = xe_mmio_read32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base));
 		maxcnt = xe_mmio_read32(&gt->mmio, RING_PWRCTX_MAXCNT(hwe->mmio_base));
 
-		inhibit_switch = idledly & INHIBIT_SWITCH_UNTIL_PREEMPTED;
-		idledly = REG_FIELD_GET(IDLE_DELAY, idledly);
+		inhibit_switch = idledly_reg_val & INHIBIT_SWITCH_UNTIL_PREEMPTED;
+		idledly = REG_FIELD_GET(IDLE_DELAY, idledly_reg_val);
 		idledly = DIV_ROUND_CLOSEST_ULL((u64)idledly * idledly_units_ps, 1000);
 		maxcnt = REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt);
 
@@ -614,10 +618,38 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
 
 		maxcnt *= maxcnt_units_ns;
 
-		if (xe_gt_WARN_ON(gt, idledly >= maxcnt || inhibit_switch)) {
-			idledly = DIV_ROUND_CLOSEST_ULL((u64)(maxcnt - 1) * 1000,
-							idledly_units_ps);
-			xe_mmio_write32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base), idledly);
+		/* Wa_14025941587: applied prior to Wa_16023105232,
+		 * as the latter has higher priority, although conflict
+		 * is not expected.
+		 */
+		if (XE_GT_WA(gt, 14025941587) &&
+		    idledly < mincnt_idledly_ns) {
+			idledly = mincnt_idledly_ns;
+			wa_applied = true;
+		}
+
+		if (XE_GT_WA(gt, 16023105232) &&
+		    xe_gt_WARN_ON(gt, idledly >= maxcnt || inhibit_switch)) {
+			idledly = (maxcnt - 1);
+			wa_applied = true;
+			/* inhibit_switch override to keep
+			 * semantics of Wa_16023105232
+			 */
+			if (inhibit_switch)
+				idledly_reg_val &= ~INHIBIT_SWITCH_UNTIL_PREEMPTED;
+		}
+
+		if (wa_applied) {
+			idledly_reg_val &= ~IDLE_DELAY;
+			idledly_reg_val |= REG_FIELD_PREP(IDLE_DELAY,
+						DIV_ROUND_CLOSEST_ULL((u64)idledly * 1000,
+								      idledly_units_ps));
+			xe_gt_dbg(gt, "idledly %s: set %u max=%u inh=%u ts=%u\n",
+				  hwe->name, idledly, maxcnt,
+				  !!inhibit_switch, gt->info.timestamp_base);
+			xe_mmio_write32(&gt->mmio,
+					RING_IDLEDLY(hwe->mmio_base),
+					idledly_reg_val);
 		}
 	}
 }
diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
index dd69ad07f7a9..3001155f8d09 100644
--- a/drivers/gpu/drm/xe/xe_wa_oob.rules
+++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
@@ -72,3 +72,5 @@
 16029897822	MEDIA_VERSION(3500)
 		GRAPHICS_VERSION(3510)
 14027054324	GRAPHICS_VERSION(3511)
+14025941587	GRAPHICS_VERSION_RANGE(2001, 3511), FUNC(xe_rtp_match_not_sriov_vf)
+		MEDIA_VERSION_RANGE(1301, 3503), FUNC(xe_rtp_match_not_sriov_vf)
-- 
2.46.0

Re: [PATCH 2/2] drm/xe: Add wa_14025941587 to xe2, xe3 and xe3p platforms

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] Early return when maxcnt is 0 silently bypasses Wa_14025941587
- [Medium] Mutated idledly variable causes spurious WARN_ON and violates WA 14025941587 constraint
--

commit ca2474376ef20b3f47a408b5ebe9a4945d93d22c
Author: Tangudu Tilak Tirumalesh <tilak.tirumalesh.tangudu@intel.com>

drm/xe: Add wa_14025941587 to xe2, xe3 and xe3p platforms

Avoid programming the IDLEDLY timer to less than 5 microseconds.
Apply wa_14025941587 to Graphics Versions 20.01 to 35.11
and Media Versions 13.01 to 35.03

> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
> index 6ffb0ece05612..033740c34aa66 100644
> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
[ ... ]
> @@ -614,10 +618,38 @@ static void adjust_idledly(struct xe_hw_engine *hwe)
>  
>  		maxcnt *= maxcnt_units_ns;
>  
> -		if (xe_gt_WARN_ON(gt, idledly >= maxcnt || inhibit_switch)) {
> -			idledly = DIV_ROUND_CLOSEST_ULL((u64)(maxcnt - 1) * 1000,
> -							idledly_units_ps);
> -			xe_mmio_write32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base), idledly);

[Severity: Medium]
In adjust_idledly(), there is an existing check just before this hunk:

	maxcnt = REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt);

	if (!maxcnt)
		return;

If maxcnt evaluates to 0, the function executes an early return. Does this
unintentionally bypass the new Wa_14025941587 workaround added below,
skipping the 5 microsecond limit enforcement if the initial maxcnt from the
hardware happens to be 0?

> +		/* Wa_14025941587: applied prior to Wa_16023105232,
> +		 * as the latter has higher priority, although conflict
> +		 * is not expected.
> +		 */
> +		if (XE_GT_WA(gt, 14025941587) &&
> +		    idledly < mincnt_idledly_ns) {
> +			idledly = mincnt_idledly_ns;
> +			wa_applied = true;
> +		}
> +
> +		if (XE_GT_WA(gt, 16023105232) &&
> +		    xe_gt_WARN_ON(gt, idledly >= maxcnt || inhibit_switch)) {
> +			idledly = (maxcnt - 1);

[Severity: Medium]
Can this sequence trigger a spurious WARN_ON and violate the 5000ns minimum?

If the original idledly is less than 5000ns, WA 14025941587 mutates idledly
to 5000. Immediately after, if maxcnt happens to be 5000 or less (e.g. 4480),
the WARN_ON will trigger because it evaluates the mutated idledly
(5000 >= 4480), even if the original hardware value was safe (e.g.
2000 < 4480). 

Following the WARN_ON, idledly is then set to maxcnt - 1 (e.g. 4479), which
silently breaks the 5000ns minimum required by Wa_14025941587.

Should the second workaround evaluate the original hardware state rather than
the software-mutated value?

> +			wa_applied = true;
> +			/* inhibit_switch override to keep
> +			 * semantics of Wa_16023105232
> +			 */
> +			if (inhibit_switch)
> +				idledly_reg_val &= ~INHIBIT_SWITCH_UNTIL_PREEMPTED;
> +		}

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260909072540.99303-1-tilak.tirumalesh.tangudu@intel.com?part=2