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From: Jani Nikula <jani.nikula@intel.com>
To: Animesh Manna <animesh.manna@intel.com>,
	intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Cc: uma.shankar@intel.com, dibin.moolakadan.subrahmanian@intel.com,
	Animesh Manna <animesh.manna@intel.com>
Subject: Re: [PATCH v4 01/13] drm/i915/cmtg: Add intel_cmtg_is_allowed() for CMTG
Date: Tue, 14 Apr 2026 16:31:21 +0300	[thread overview]
Message-ID: <26027f9989a2f963236ac3a41d69ca910d4e7069@intel.com> (raw)
In-Reply-To: <20260412103712.4021213-2-animesh.manna@intel.com>

On Sun, 12 Apr 2026, Animesh Manna <animesh.manna@intel.com> wrote:
> CMTG will be enabled only with DC3co, so add a separate function
> intel_cmtg_is_allowed() to check the prerequisites for enabling CMTG.
> DC3co will be enabled in a separate patch.
>
> v2:
> - Remove separate flag for DC3co from crtc_state. [Uma, Dibin]
>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cmtg.c | 15 +++++++++++++++
>  drivers/gpu/drm/i915/display/intel_cmtg.h |  2 ++
>  2 files changed, 17 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index e1fdc6fe9762..1debed43cf2c 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -16,6 +16,7 @@
>  #include "intel_display_device.h"
>  #include "intel_display_power.h"
>  #include "intel_display_regs.h"
> +#include "intel_display_types.h"
>  
>  /**
>   * DOC: Common Primary Timing Generator (CMTG)
> @@ -185,3 +186,17 @@ void intel_cmtg_sanitize(struct intel_display *display)
>  
>  	intel_cmtg_disable(display, &cmtg_config);
>  }
> +
> +bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +	struct i915_power_domains *power_domains = &display->power.domains;
> +
> +	if ((cpu_transcoder == TRANSCODER_A || cpu_transcoder == TRANSCODER_B) &&
> +	    DISPLAY_VER(display) == 35 && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
> +	    power_domains->target_dc_state == DC_STATE_EN_DC3CO)

intel_cmtg.c has no business accessing struct i915_power_domains members
directly. It belongs to intel_display_power.c.

BR,
Jani.

> +		return true;
> +
> +	return false;
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
> index ba62199adaa2..7692cc98cf87 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> @@ -7,7 +7,9 @@
>  #define __INTEL_CMTG_H__
>  
>  struct intel_display;
> +struct intel_crtc_state;
>  
>  void intel_cmtg_sanitize(struct intel_display *display);
> +bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state);
>  
>  #endif /* __INTEL_CMTG_H__ */

-- 
Jani Nikula, Intel

  reply	other threads:[~2026-04-14 13:31 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-04-12 10:36 [PATCH v4 00/13] CMTG enablement Animesh Manna
2026-04-12 10:37 ` [PATCH v4 01/13] drm/i915/cmtg: Add intel_cmtg_is_allowed() for CMTG Animesh Manna
2026-04-14 13:31   ` Jani Nikula [this message]
2026-04-12 10:37 ` [PATCH v4 02/13] drm/i915/cmtg: Set CMTG clock select Animesh Manna
2026-04-12 10:37 ` [PATCH v4 03/13] drm/i915/cmtg: Set timings for CMTG Animesh Manna
2026-04-14 13:33   ` Jani Nikula
2026-04-17  6:03     ` Manna, Animesh
2026-04-17 10:26       ` Ville Syrjälä
2026-04-23  4:37         ` Manna, Animesh
2026-04-23  4:55         ` Manna, Animesh
2026-04-23 10:51           ` Ville Syrjälä
2026-04-23 11:07             ` Manna, Animesh
2026-04-12 10:37 ` [PATCH v4 04/13] drm/i915/cmtg: Program VRR registers of CMTG Animesh Manna
2026-04-12 10:37 ` [PATCH v4 05/13] drm/i915/cmtg: Set transcoder mn for CMTG Animesh Manna
2026-04-12 10:37 ` [PATCH v4 06/13] drm/i915/cmtg: Add hook to enable CMTG with sync to port Animesh Manna
2026-04-12 10:37 ` [PATCH v4 07/13] drm/i915/cmtg: Add a hook to make eDP transcoder secondary Animesh Manna
2026-04-12 10:37 ` [PATCH v4 08/13] drm/i915/cmtg: Split CMTG support check from intel_cmtg_is_allowed() Animesh Manna
2026-04-12 10:37 ` [PATCH v4 09/13] drm/i915/cmtg: Modify existing hook to disable CMTG Animesh Manna
2026-04-12 10:37 ` [PATCH v4 10/13] drm/i915/cmtg: Add trigger to enable/disable cmtg Animesh Manna
2026-04-12 10:37 ` [PATCH v4 11/13] drm/i915/cmtg: Add CMTG interrupt handling Animesh Manna
2026-04-12 10:37 ` [PATCH v4 12/13] drm/i915/cmtg: Disable CMTG if dc3co is not allowed Animesh Manna
2026-04-12 10:37 ` [PATCH v4 13/13] drm/i915/cmtg: Set target_dc_state flag for lobf/psr2/pr-alpm Animesh Manna
2026-04-13 12:19   ` Dibin Moolakadan Subrahmanian
2026-04-12 11:16 ` ✓ CI.KUnit: success for CMTG enablement (rev5) Patchwork
2026-04-12 12:05 ` ✓ Xe.CI.BAT: " Patchwork
2026-04-12 13:01 ` ✗ Xe.CI.FULL: failure " Patchwork

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