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* [PATCH v2] drm/xe/xe2hpg: Add Wa_16025250150
@ 2025-03-25 13:44 Aradhya Bhatia
  2025-03-25 14:17 ` ✓ CI.Patch_applied: success for drm/xe/xe2hpg: Add Wa_16025250150 (rev2) Patchwork
                   ` (14 more replies)
  0 siblings, 15 replies; 18+ messages in thread
From: Aradhya Bhatia @ 2025-03-25 13:44 UTC (permalink / raw)
  To: Matt Roper
  Cc: Intel XE List, Ayaz A Siddiqui, Tejas Upadhyay,
	Himal Prasad Ghimiray, Aradhya Bhatia

Add Wa_16025250150 for the Xe2_HPG (graphics version: 20.01) platforms.
It is a permanent workaround, and applicable on all the steppings.

Reviewed-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Signed-off-by: Aradhya Bhatia <aradhya.bhatia@intel.com>
---
Changes in v2:
  - Define the reg as MCR (XE_REG_MCR instead of XE_REG), as suggested by
    Tejas Upadhyay.
  - Add R-b tag (Tejas Upadhyay).
  - v1: https://lore.kernel.org/all/20250325064434.970748-1-aradhya.bhatia@intel.com/

---
 drivers/gpu/drm/xe/regs/xe_gt_regs.h | 12 ++++++++++++
 drivers/gpu/drm/xe/xe_wa.c           | 12 ++++++++++++
 2 files changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index da1f198ac107..58f4218c2569 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -392,6 +392,18 @@
 #define XEHP_L3NODEARBCFG			XE_REG_MCR(0xb0b4)
 #define   XEHP_LNESPARE				REG_BIT(19)
 
+#define LSN_VC_REG2				XE_REG_MCR(0xb0c8)
+#define   LSN_LNI_WGT_MASK			REG_GENMASK(31, 28)
+#define   LSN_LNI_WGT(value)			REG_FIELD_PREP(LSN_LNI_WGT_MASK, value)
+#define   LSN_LNE_WGT_MASK			REG_GENMASK(27, 24)
+#define   LSN_LNE_WGT(value)			REG_FIELD_PREP(LSN_LNE_WGT_MASK, value)
+#define   LSN_DIM_X_WGT_MASK			REG_GENMASK(23, 20)
+#define   LSN_DIM_X_WGT(value)			REG_FIELD_PREP(LSN_DIM_X_WGT_MASK, value)
+#define   LSN_DIM_Y_WGT_MASK			REG_GENMASK(19, 16)
+#define   LSN_DIM_Y_WGT(value)			REG_FIELD_PREP(LSN_DIM_Y_WGT_MASK, value)
+#define   LSN_DIM_Z_WGT_MASK			REG_GENMASK(15, 12)
+#define   LSN_DIM_Z_WGT(value)			REG_FIELD_PREP(LSN_DIM_Z_WGT_MASK, value)
+
 #define L3SQCREG2				XE_REG_MCR(0xb104)
 #define   COMPMEMRD256BOVRFETCHEN		REG_BIT(20)
 
diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index 24f644c0a673..6f6563cc7430 100644
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -230,6 +230,18 @@ static const struct xe_rtp_entry_sr gt_was[] = {
 	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
 	},
 
+	/* Xe2_HPG */
+
+	{ XE_RTP_NAME("16025250150"),
+	  XE_RTP_RULES(GRAPHICS_VERSION(2001)),
+	  XE_RTP_ACTIONS(SET(LSN_VC_REG2,
+			     LSN_LNI_WGT(1) |
+			     LSN_LNE_WGT(1) |
+			     LSN_DIM_X_WGT(1) |
+			     LSN_DIM_Y_WGT(1) |
+			     LSN_DIM_Z_WGT(1)))
+	},
+
 	/* Xe2_HPM */
 
 	{ XE_RTP_NAME("16021867713"),

base-commit: 9a42bdcde0f77b2c1e947e283cc3b267b1ce2056
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 18+ messages in thread

end of thread, other threads:[~2025-04-03  4:52 UTC | newest]

Thread overview: 18+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-03-25 13:44 [PATCH v2] drm/xe/xe2hpg: Add Wa_16025250150 Aradhya Bhatia
2025-03-25 14:17 ` ✓ CI.Patch_applied: success for drm/xe/xe2hpg: Add Wa_16025250150 (rev2) Patchwork
2025-03-25 14:17 ` ✓ CI.checkpatch: " Patchwork
2025-03-25 14:19 ` ✓ CI.KUnit: " Patchwork
2025-03-25 14:35 ` ✓ CI.Build: " Patchwork
2025-03-25 14:37 ` ✓ CI.Hooks: " Patchwork
2025-03-25 14:39 ` ✓ CI.checksparse: " Patchwork
2025-03-25 20:28 ` ✗ Xe.CI.Full: failure " Patchwork
2025-03-27 14:36 ` ✓ CI.Patch_applied: success " Patchwork
2025-03-27 14:36 ` ✓ CI.checkpatch: " Patchwork
2025-03-27 14:37 ` ✓ CI.KUnit: " Patchwork
2025-03-27 14:54 ` ✓ CI.Build: " Patchwork
2025-03-27 14:56 ` ✓ CI.Hooks: " Patchwork
2025-03-27 14:57 ` ✓ CI.checksparse: " Patchwork
2025-03-27 15:18 ` ✗ Xe.CI.BAT: failure " Patchwork
2025-04-03  4:52   ` Aradhya Bhatia
2025-03-27 23:29 ` ✗ Xe.CI.Full: " Patchwork
2025-03-28  6:36   ` Aradhya Bhatia

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