Re: [PATCH v7 11/24] drm/xe: Flush L3 when flushing render cache

["Souza, Jose" <jose.souza@intel.com>]

On Fri, 2025-06-27 at 14:33 +0100, Tvrtko Ursulin wrote:
> I915 sets PIPE_CONTROL_FLUSH_L3 (bit 27) when flushing render caches but
> interesting thing is Tigerlake PRM lists that bit as reserved.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
> ---
> Is xe missing this? Or has this been wrong for so long in i915? Or is this
> an undocumented bit?
> ---
>  drivers/gpu/drm/xe/instructions/xe_gpu_commands.h |  1 +
>  drivers/gpu/drm/xe/xe_ring_ops.c                  | 10 ++++++++++
>  2 files changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/instructions/xe_gpu_commands.h b/drivers/gpu/drm/xe/instructions/xe_gpu_commands.h
> index 78c0e87dbd37..27892984403c 100644
> --- a/drivers/gpu/drm/xe/instructions/xe_gpu_commands.h
> +++ b/drivers/gpu/drm/xe/instructions/xe_gpu_commands.h
> @@ -47,6 +47,7 @@
>  
>  #define   PIPE_CONTROL_COMMAND_CACHE_INVALIDATE		(1<<29)
>  #define   PIPE_CONTROL_TILE_CACHE_FLUSH			(1<<28)
> +#define   PIPE_CONTROL_FLUSH_L3                         (1<<27)

On spec this bit is Protected Memory Disable. I think what you want is bit 30.

>  #define   PIPE_CONTROL_AMFS_FLUSH			(1<<25)
>  #define   PIPE_CONTROL_GLOBAL_GTT_IVB			(1<<24)
>  #define   PIPE_CONTROL_LRI_POST_SYNC			BIT(23)
> diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
> index a1289f086191..8f655b6fe913 100644
> --- a/drivers/gpu/drm/xe/xe_ring_ops.c
> +++ b/drivers/gpu/drm/xe/xe_ring_ops.c
> @@ -197,6 +197,16 @@ static int emit_render_cache_flush(struct xe_sched_job *job, u32 *dw, int i)
>  	if (XE_WA(gt, 1409600907))
>  		flags |= PIPE_CONTROL_DEPTH_STALL;
>  
> +	/*
> +	 * L3 fabric flush is needed for AUX CCS invalidation
> +	 * which happens as part of pipe-control so we can
> +	 * ignore PIPE_CONTROL_FLUSH_L3. Also PIPE_CONTROL_FLUSH_L3
> +	 * deals with Protected Memory which is not needed for
> +	 * AUX CCS invalidation and lead to unwanted side effects.
> +	 */
> +	if (GRAPHICS_VERx100(xe) < 1270)
> +		flags |= PIPE_CONTROL_FLUSH_L3;
> +
>  	if (lacks_render)
>  		flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS;
>  	else if (job->q->class == XE_ENGINE_CLASS_COMPUTE)