Re: [PATCH v2] drm/i915/irq: add ilk_display_irq_reset()

[Jani Nikula <jani.nikula@intel.com>]

On Thu, 18 Sep 2025, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Thu, Sep 18, 2025 at 03:41:24PM +0300, Jani Nikula wrote:
>> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>> index ab65402bc6bf..af2b43679b1b 100644
>> --- a/drivers/gpu/drm/i915/i915_irq.c
>> +++ b/drivers/gpu/drm/i915/i915_irq.c
>> @@ -656,22 +656,9 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
>>  static void ilk_irq_reset(struct drm_i915_private *dev_priv)
>>  {
>>  	struct intel_display *display = dev_priv->display;
>> -	struct intel_uncore *uncore = &dev_priv->uncore;
>> -
>> -	gen2_irq_reset(uncore, DE_IRQ_REGS);
>> -	display->irq.ilk_de_imr_mask = ~0u;
>> -
>> -	if (GRAPHICS_VER(dev_priv) == 7)
>> -		intel_uncore_write(uncore, GEN7_ERR_INT, 0xffffffff);
>> -
>> -	if (IS_HASWELL(dev_priv)) {
>> -		intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
>> -		intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
>> -	}
>>  
>>  	gen5_gt_irq_reset(to_gt(dev_priv));
>> -
>> -	ibx_display_irq_reset(display);
>> +	ilk_display_irq_reset(display);
>
> The master interrupt enable bit is in DEIER, so we really should
> reset that first. I suppose we could just do the entire display
> irq reset before the gt stuff (ie. effectively just move the pch
> irq reset ahead of the gt irq reset).

Thanks for catching this. I had a glance at other irq reset functions,
which seemed to have gt before display, but I just didn't put deeper
thought into why and what's different.

v3 on the list.


-- 
Jani Nikula, Intel