[PATCH V6 0/4] drm/xe/xe3p_lpg: L2 flush optimization

[PATCH V6 0/4] drm/xe/xe3p_lpg: L2 flush optimization

[Tejas Upadhyay]

The optimization involves two key changes:

Hardware-assisted Transient Display Flush:
The new hardware can automatically manage the flushing of "transient"
display data from the L2 cache. This eliminates the need for manual
(software-driven) transient display (TD) flushes by the driver,
simplifying the code and likely improving efficiency.

Transient Application (App) Cacheline Management:
The hardware gains the ability to flush transient application cache
lines more efficiently. The patch handles the necessary integration
to utilize this new functionality and manages manual flushing where
it is still required, ensuring data coherency and optimizing
performance.

Additional handling due to L2 flush optimization:
1. Need to flush cachelines manually via async tlb flush for internal/shrinker bo
2. Define coh_mode 2way for differentiating coherency modes
3. Add restrictions for userptr, svm/madvise and dmabuf to use either 2WAY or XA+1WAY
   pat settings


Tejas Upadhyay (4):
  drm/xe/xe3p_lpg: flush shrinker bo cachelines manually
  drm/xe/pat: define coh_mode 2way
  drm/xe/xe3p_lpg: Restrict UAPI to enable L2 flush optimization
  drm/xe/xe3p: Skip TD flush

 drivers/gpu/drm/xe/xe_bo.c         |  7 ++++++-
 drivers/gpu/drm/xe/xe_device.c     | 31 ++++++++++++++++++++++++++++++
 drivers/gpu/drm/xe/xe_device.h     |  1 +
 drivers/gpu/drm/xe/xe_guc.c        |  3 +++
 drivers/gpu/drm/xe/xe_guc_fwif.h   |  1 +
 drivers/gpu/drm/xe/xe_pat.c        | 14 +++++++-------
 drivers/gpu/drm/xe/xe_pat.h        |  5 +++--
 drivers/gpu/drm/xe/xe_vm.c         | 10 +++++++++-
 drivers/gpu/drm/xe/xe_vm_madvise.c | 25 +++++++++++++++++++++++-
 include/uapi/drm/xe_drm.h          |  4 +++-
 10 files changed, 88 insertions(+), 13 deletions(-)

-- 
2.52.0

[PATCH V6 1/4] drm/xe/xe3p_lpg: flush shrinker bo cachelines manually

[Tejas Upadhyay]

XA, new pat_index introduced post xe3p_lpg, is memory shared between the
CPU and GPU is treated differently from other GPU memory when the Media
engine is power-gated.

XA is *always* flushed, like at the end-of-submssion (and maybe other
places), just that internally as an optimisation hw doesn't need to make
that a full flush (which will also include XA) when Media is
off/powergated, since it doesn't need to worry about GT caches vs Media
coherency, and only CPU vs GPU coherency, so can make that flush a
targeted XA flush, since stuff tagged with XA now means it's shared with
the CPU. The main implication is that we now need to somehow flush non-XA
before freeing system memory pages, otherwise dirty cachelines could be
flushed after the free (like if Media suddenly turns on and does a full
flush)

V4: Add comments for L2 flush path
V3(Thomas/MattA/MattR): Restrict userptr with non-xa, then no need to
                        flush manually
V2(MattA): Expand commit description

Reviewed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
---
 drivers/gpu/drm/xe/xe_bo.c     |  7 ++++++-
 drivers/gpu/drm/xe/xe_device.c | 23 +++++++++++++++++++++++
 drivers/gpu/drm/xe/xe_device.h |  1 +
 3 files changed, 30 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_bo.c b/drivers/gpu/drm/xe/xe_bo.c
index d6c2cb959cdd..9e44cdda13cd 100644
--- a/drivers/gpu/drm/xe/xe_bo.c
+++ b/drivers/gpu/drm/xe/xe_bo.c
@@ -689,7 +689,12 @@ static int xe_bo_trigger_rebind(struct xe_device *xe, struct xe_bo *bo,
 
 		if (!xe_vm_in_fault_mode(vm)) {
 			drm_gpuvm_bo_evict(vm_bo, true);
-			continue;
+			/*
+			 * L2 cache may not be flushed, so ensure that is done in
+			 * xe_vm_invalidate_vma() below
+			 */
+			if (!xe_device_is_l2_flush_optimized(xe))
+				continue;
 		}
 
 		if (!idle) {
diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index 4b68a2d55651..94c9f17da4b4 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -1097,6 +1097,29 @@ static void tdf_request_sync(struct xe_device *xe)
 	}
 }
 
+/**
+ * xe_device_is_l2_flush_optimized - if L2 flush is optimized by HW
+ * @xe: The device to check.
+ *
+ * Return: true if the HW device optimizing L2 flush, false otherwise.
+ */
+bool xe_device_is_l2_flush_optimized(struct xe_device *xe)
+{
+	/* XA is *always* flushed, like at the end-of-submssion (and maybe other
+	 * places), just that internally as an optimisation hw doesn't need to make
+	 * that a full flush (which will also include XA) when Media is
+	 * off/powergated, since it doesn't need to worry about GT caches vs Media
+	 * coherency, and only CPU vs GPU coherency, so can make that flush a
+	 * targeted XA flush, since stuff tagged with XA now means it's shared with
+	 * the CPU. The main implication is that we now need to somehow flush non-XA before
+	 * freeing system memory pages, otherwise dirty cachelines could be flushed after the free
+	 * (like if Media suddenly turns on and does a full flush)
+	 */
+	if (GRAPHICS_VER(xe) >= 35 && !IS_DGFX(xe))
+		return true;
+	return false;
+}
+
 void xe_device_l2_flush(struct xe_device *xe)
 {
 	struct xe_gt *gt;
diff --git a/drivers/gpu/drm/xe/xe_device.h b/drivers/gpu/drm/xe/xe_device.h
index 39464650533b..dfbf96e12d2e 100644
--- a/drivers/gpu/drm/xe/xe_device.h
+++ b/drivers/gpu/drm/xe/xe_device.h
@@ -184,6 +184,7 @@ void xe_device_snapshot_print(struct xe_device *xe, struct drm_printer *p);
 u64 xe_device_canonicalize_addr(struct xe_device *xe, u64 address);
 u64 xe_device_uncanonicalize_addr(struct xe_device *xe, u64 address);
 
+bool xe_device_is_l2_flush_optimized(struct xe_device *xe);
 void xe_device_td_flush(struct xe_device *xe);
 void xe_device_l2_flush(struct xe_device *xe);
 
-- 
2.52.0

[PATCH V6 2/4] drm/xe/pat: define coh_mode 2way

[Tejas Upadhyay]

Defining 2way (two-way coherency) is critical for
Xe3p_LPG (Nova Lake P) platforms to support L2 flush
optimization safely.

This mode allows the driver to skip certain manual cache
flushes (L2 flush optimization) without risking memory
corruption because the hardware ensures the most recent
data is visible to both entities.

Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
---
 drivers/gpu/drm/xe/xe_pat.c        | 14 +++++++-------
 drivers/gpu/drm/xe/xe_pat.h        |  5 +++--
 drivers/gpu/drm/xe/xe_vm.c         |  2 +-
 drivers/gpu/drm/xe/xe_vm_madvise.c |  2 +-
 4 files changed, 12 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_pat.c b/drivers/gpu/drm/xe/xe_pat.c
index f840d9a58740..bf581afd4d60 100644
--- a/drivers/gpu/drm/xe/xe_pat.c
+++ b/drivers/gpu/drm/xe/xe_pat.c
@@ -92,7 +92,7 @@ struct xe_pat_ops {
 };
 
 static const struct xe_pat_table_entry xelp_pat_table[] = {
-	[0] = { XELP_PAT_WB, XE_COH_AT_LEAST_1WAY },
+	[0] = { XELP_PAT_WB, XE_COH_1WAY },
 	[1] = { XELP_PAT_WC, XE_COH_NONE },
 	[2] = { XELP_PAT_WT, XE_COH_NONE },
 	[3] = { XELP_PAT_UC, XE_COH_NONE },
@@ -102,19 +102,19 @@ static const struct xe_pat_table_entry xehpc_pat_table[] = {
 	[0] = { XELP_PAT_UC, XE_COH_NONE },
 	[1] = { XELP_PAT_WC, XE_COH_NONE },
 	[2] = { XELP_PAT_WT, XE_COH_NONE },
-	[3] = { XELP_PAT_WB, XE_COH_AT_LEAST_1WAY },
+	[3] = { XELP_PAT_WB, XE_COH_1WAY },
 	[4] = { XEHPC_PAT_CLOS(1) | XELP_PAT_WT, XE_COH_NONE },
-	[5] = { XEHPC_PAT_CLOS(1) | XELP_PAT_WB, XE_COH_AT_LEAST_1WAY },
+	[5] = { XEHPC_PAT_CLOS(1) | XELP_PAT_WB, XE_COH_1WAY },
 	[6] = { XEHPC_PAT_CLOS(2) | XELP_PAT_WT, XE_COH_NONE },
-	[7] = { XEHPC_PAT_CLOS(2) | XELP_PAT_WB, XE_COH_AT_LEAST_1WAY },
+	[7] = { XEHPC_PAT_CLOS(2) | XELP_PAT_WB, XE_COH_1WAY },
 };
 
 static const struct xe_pat_table_entry xelpg_pat_table[] = {
 	[0] = { XELPG_PAT_0_WB, XE_COH_NONE },
 	[1] = { XELPG_PAT_1_WT, XE_COH_NONE },
 	[2] = { XELPG_PAT_3_UC, XE_COH_NONE },
-	[3] = { XELPG_PAT_0_WB | XELPG_2_COH_1W, XE_COH_AT_LEAST_1WAY },
-	[4] = { XELPG_PAT_0_WB | XELPG_3_COH_2W, XE_COH_AT_LEAST_1WAY },
+	[3] = { XELPG_PAT_0_WB | XELPG_2_COH_1W, XE_COH_1WAY },
+	[4] = { XELPG_PAT_0_WB | XELPG_3_COH_2W, XE_COH_2WAY },
 };
 
 /*
@@ -147,7 +147,7 @@ static const struct xe_pat_table_entry xelpg_pat_table[] = {
 			REG_FIELD_PREP(XE2_L3_POLICY, l3_policy) | \
 			REG_FIELD_PREP(XE2_L4_POLICY, l4_policy) | \
 			REG_FIELD_PREP(XE2_COH_MODE, __coh_mode), \
-		.coh_mode = __coh_mode ? XE_COH_AT_LEAST_1WAY : XE_COH_NONE, \
+		.coh_mode = __coh_mode ? __coh_mode : XE_COH_NONE, \
 		.valid = 1 \
 	}
 
diff --git a/drivers/gpu/drm/xe/xe_pat.h b/drivers/gpu/drm/xe/xe_pat.h
index c7e2a53d8cee..a1e287c08f57 100644
--- a/drivers/gpu/drm/xe/xe_pat.h
+++ b/drivers/gpu/drm/xe/xe_pat.h
@@ -28,8 +28,9 @@ struct xe_pat_table_entry {
 	/**
 	 * @coh_mode: The GPU coherency mode that @value maps to.
 	 */
-#define XE_COH_NONE          1
-#define XE_COH_AT_LEAST_1WAY 2
+#define XE_COH_NONE		1
+#define XE_COH_1WAY		2
+#define XE_COH_2WAY		3
 	u16 coh_mode;
 
 	/**
diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
index 550208ef63f8..da0ce0b3704c 100644
--- a/drivers/gpu/drm/xe/xe_vm.c
+++ b/drivers/gpu/drm/xe/xe_vm.c
@@ -3456,7 +3456,7 @@ static int vm_bind_ioctl_check_args(struct xe_device *xe, struct xe_vm *vm,
 			goto free_bind_ops;
 		}
 
-		if (XE_WARN_ON(coh_mode > XE_COH_AT_LEAST_1WAY)) {
+		if (XE_WARN_ON(coh_mode > XE_COH_2WAY)) {
 			err = -EINVAL;
 			goto free_bind_ops;
 		}
diff --git a/drivers/gpu/drm/xe/xe_vm_madvise.c b/drivers/gpu/drm/xe/xe_vm_madvise.c
index 0c92fed6c6a6..07169586e35f 100644
--- a/drivers/gpu/drm/xe/xe_vm_madvise.c
+++ b/drivers/gpu/drm/xe/xe_vm_madvise.c
@@ -301,7 +301,7 @@ static bool madvise_args_are_sane(struct xe_device *xe, const struct drm_xe_madv
 		if (XE_IOCTL_DBG(xe, !coh_mode))
 			return false;
 
-		if (XE_WARN_ON(coh_mode > XE_COH_AT_LEAST_1WAY))
+		if (XE_WARN_ON(coh_mode > XE_COH_2WAY))
 			return false;
 
 		if (XE_IOCTL_DBG(xe, args->pat_index.pad))
-- 
2.52.0

[PATCH V6 3/4] drm/xe/xe3p_lpg: Restrict UAPI to enable L2 flush optimization

[Tejas Upadhyay]

When set, starting xe3p_lpg, the L2 flush optimization
feature will control whether L2 is in Persistent or
Transient mode through monitoring of media activity.

To enable L2 flush optimization include new feature flag
GUC_CTL_ENABLE_L2FLUSH_OPT for Novalake platforms when
media type is detected.

Tighten UAPI validation to restrict userptr, svm and
dmabuf mappings to be either 2WAY or XA+1WAY

V5(Thomas): logic correction
V4(MattA): Modify uapi doc and commit
V3(MattA): check valid op and pat_index value
V2(MattA): validate dma-buf bos and madvise pat-index

Acked-by: José Roberto de Souza <jose.souza@intel.com>
Acked-by: Michal Mrozek <michal.mrozek@intel.com>
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
---
 drivers/gpu/drm/xe/xe_guc.c        |  3 +++
 drivers/gpu/drm/xe/xe_guc_fwif.h   |  1 +
 drivers/gpu/drm/xe/xe_vm.c         |  8 ++++++++
 drivers/gpu/drm/xe/xe_vm_madvise.c | 23 +++++++++++++++++++++++
 include/uapi/drm/xe_drm.h          |  4 +++-
 5 files changed, 38 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index 54d2fc780127..43dc4353206f 100644
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -98,6 +98,9 @@ static u32 guc_ctl_feature_flags(struct xe_guc *guc)
 	if (xe_guc_using_main_gamctrl_queues(guc))
 		flags |= GUC_CTL_MAIN_GAMCTRL_QUEUES;
 
+	if (GRAPHICS_VER(xe) >= 35 && !IS_DGFX(xe) && xe_gt_is_media_type(guc_to_gt(guc)))
+		flags |= GUC_CTL_ENABLE_L2FLUSH_OPT;
+
 	return flags;
 }
 
diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h b/drivers/gpu/drm/xe/xe_guc_fwif.h
index bb8f71d38611..b73fae063fac 100644
--- a/drivers/gpu/drm/xe/xe_guc_fwif.h
+++ b/drivers/gpu/drm/xe/xe_guc_fwif.h
@@ -67,6 +67,7 @@ struct guc_update_exec_queue_policy {
 #define   GUC_CTL_ENABLE_PSMI_LOGGING	BIT(7)
 #define   GUC_CTL_MAIN_GAMCTRL_QUEUES	BIT(9)
 #define   GUC_CTL_DISABLE_SCHEDULER	BIT(14)
+#define   GUC_CTL_ENABLE_L2FLUSH_OPT	BIT(15)
 
 #define GUC_CTL_DEBUG			3
 #define   GUC_LOG_VERBOSITY		REG_GENMASK(1, 0)
diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
index da0ce0b3704c..0b236e08c158 100644
--- a/drivers/gpu/drm/xe/xe_vm.c
+++ b/drivers/gpu/drm/xe/xe_vm.c
@@ -3481,6 +3481,10 @@ static int vm_bind_ioctl_check_args(struct xe_device *xe, struct xe_vm *vm,
 				 op == DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
 		    XE_IOCTL_DBG(xe, coh_mode == XE_COH_NONE &&
 				 op == DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
+		    XE_IOCTL_DBG(xe, xe_device_is_l2_flush_optimized(xe) &&
+				 (op == DRM_XE_VM_BIND_OP_MAP_USERPTR ||
+				  is_cpu_addr_mirror) &&
+				 (pat_index != 19 && coh_mode != XE_COH_2WAY)) ||
 		    XE_IOCTL_DBG(xe, comp_en &&
 				 op == DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
 		    XE_IOCTL_DBG(xe, op == DRM_XE_VM_BIND_OP_MAP_USERPTR &&
@@ -3615,6 +3619,10 @@ static int xe_vm_bind_ioctl_validate_bo(struct xe_device *xe, struct xe_bo *bo,
 	if (XE_IOCTL_DBG(xe, bo->ttm.base.import_attach && comp_en))
 		return -EINVAL;
 
+	if (XE_IOCTL_DBG(xe, bo->ttm.base.import_attach && xe_device_is_l2_flush_optimized(xe) &&
+			 (pat_index != 19 && coh_mode != XE_COH_2WAY)))
+		return -EINVAL;
+
 	/* If a BO is protected it can only be mapped if the key is still valid */
 	if ((bind_flags & DRM_XE_VM_BIND_FLAG_CHECK_PXP) && xe_bo_is_protected(bo) &&
 	    op != DRM_XE_VM_BIND_OP_UNMAP && op != DRM_XE_VM_BIND_OP_UNMAP_ALL)
diff --git a/drivers/gpu/drm/xe/xe_vm_madvise.c b/drivers/gpu/drm/xe/xe_vm_madvise.c
index 07169586e35f..376c014239ee 100644
--- a/drivers/gpu/drm/xe/xe_vm_madvise.c
+++ b/drivers/gpu/drm/xe/xe_vm_madvise.c
@@ -411,6 +411,7 @@ int xe_vm_madvise_ioctl(struct drm_device *dev, void *data, struct drm_file *fil
 	struct xe_vmas_in_madvise_range madvise_range = {.addr = args->start,
 							 .range =  args->range, };
 	struct xe_madvise_details details;
+	u16 pat_index, coh_mode;
 	struct xe_vm *vm;
 	struct drm_exec exec;
 	int err, attr_type;
@@ -447,6 +448,17 @@ int xe_vm_madvise_ioctl(struct drm_device *dev, void *data, struct drm_file *fil
 	if (err || !madvise_range.num_vmas)
 		goto madv_fini;
 
+	if (args->type == DRM_XE_MEM_RANGE_ATTR_PAT) {
+		pat_index = array_index_nospec(args->pat_index.val, xe->pat.n_entries);
+		coh_mode = xe_pat_index_get_coh_mode(xe, pat_index);
+		if (XE_IOCTL_DBG(xe, madvise_range.has_svm_userptr_vmas &&
+				 xe_device_is_l2_flush_optimized(xe) &&
+				 (pat_index != 19 && coh_mode != XE_COH_2WAY))) {
+			err = -EINVAL;
+			goto madv_fini;
+		}
+	}
+
 	if (madvise_range.has_bo_vmas) {
 		if (args->type == DRM_XE_MEM_RANGE_ATTR_ATOMIC) {
 			if (!check_bo_args_are_sane(vm, madvise_range.vmas,
@@ -464,6 +476,17 @@ int xe_vm_madvise_ioctl(struct drm_device *dev, void *data, struct drm_file *fil
 
 				if (!bo)
 					continue;
+
+				if (args->type == DRM_XE_MEM_RANGE_ATTR_PAT) {
+					if (XE_IOCTL_DBG(xe, bo->ttm.base.import_attach &&
+							 xe_device_is_l2_flush_optimized(xe) &&
+							 (pat_index != 19 &&
+							  coh_mode != XE_COH_2WAY))) {
+						err = -EINVAL;
+						goto err_fini;
+					}
+				}
+
 				err = drm_exec_lock_obj(&exec, &bo->ttm.base);
 				drm_exec_retry_on_contention(&exec);
 				if (err)
diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
index ef2565048bdf..862fed3cf1ed 100644
--- a/include/uapi/drm/xe_drm.h
+++ b/include/uapi/drm/xe_drm.h
@@ -1103,7 +1103,9 @@ struct drm_xe_vm_bind_op {
 	 * incoherent GT access is possible.
 	 *
 	 * Note: For userptr and externally imported dma-buf the kernel expects
-	 * either 1WAY or 2WAY for the @pat_index.
+	 * either 1WAY or 2WAY for the @pat_index. Starting from NVL-P, for
+	 * userptr, svm, madvise and externally imported dma-buf the kernel expects
+	 * either 2WAY or 1WAY and XA @pat_index.
 	 *
 	 * For DRM_XE_VM_BIND_FLAG_NULL bindings there are no KMD restrictions
 	 * on the @pat_index. For such mappings there is no actual memory being
-- 
2.52.0

Re: [PATCH V6 3/4] drm/xe/xe3p_lpg: Restrict UAPI to enable L2 flush optimization

[Thomas Hellström]

On Thu, 2026-03-05 at 17:49 +0530, Tejas Upadhyay wrote:
> When set, starting xe3p_lpg, the L2 flush optimization
> feature will control whether L2 is in Persistent or
> Transient mode through monitoring of media activity.
> 
> To enable L2 flush optimization include new feature flag
> GUC_CTL_ENABLE_L2FLUSH_OPT for Novalake platforms when
> media type is detected.
> 
> Tighten UAPI validation to restrict userptr, svm and
> dmabuf mappings to be either 2WAY or XA+1WAY
> 
> V5(Thomas): logic correction
> V4(MattA): Modify uapi doc and commit
> V3(MattA): check valid op and pat_index value
> V2(MattA): validate dma-buf bos and madvise pat-index
> 
> Acked-by: José Roberto de Souza <jose.souza@intel.com>
> Acked-by: Michal Mrozek <michal.mrozek@intel.com>
> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>

Reviewed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>

> ---
>  drivers/gpu/drm/xe/xe_guc.c        |  3 +++
>  drivers/gpu/drm/xe/xe_guc_fwif.h   |  1 +
>  drivers/gpu/drm/xe/xe_vm.c         |  8 ++++++++
>  drivers/gpu/drm/xe/xe_vm_madvise.c | 23 +++++++++++++++++++++++
>  include/uapi/drm/xe_drm.h          |  4 +++-
>  5 files changed, 38 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_guc.c
> b/drivers/gpu/drm/xe/xe_guc.c
> index 54d2fc780127..43dc4353206f 100644
> --- a/drivers/gpu/drm/xe/xe_guc.c
> +++ b/drivers/gpu/drm/xe/xe_guc.c
> @@ -98,6 +98,9 @@ static u32 guc_ctl_feature_flags(struct xe_guc
> *guc)
>  	if (xe_guc_using_main_gamctrl_queues(guc))
>  		flags |= GUC_CTL_MAIN_GAMCTRL_QUEUES;
>  
> +	if (GRAPHICS_VER(xe) >= 35 && !IS_DGFX(xe) &&
> xe_gt_is_media_type(guc_to_gt(guc)))
> +		flags |= GUC_CTL_ENABLE_L2FLUSH_OPT;
> +
>  	return flags;
>  }
>  
> diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h
> b/drivers/gpu/drm/xe/xe_guc_fwif.h
> index bb8f71d38611..b73fae063fac 100644
> --- a/drivers/gpu/drm/xe/xe_guc_fwif.h
> +++ b/drivers/gpu/drm/xe/xe_guc_fwif.h
> @@ -67,6 +67,7 @@ struct guc_update_exec_queue_policy {
>  #define   GUC_CTL_ENABLE_PSMI_LOGGING	BIT(7)
>  #define   GUC_CTL_MAIN_GAMCTRL_QUEUES	BIT(9)
>  #define   GUC_CTL_DISABLE_SCHEDULER	BIT(14)
> +#define   GUC_CTL_ENABLE_L2FLUSH_OPT	BIT(15)
>  
>  #define GUC_CTL_DEBUG			3
>  #define   GUC_LOG_VERBOSITY		REG_GENMASK(1, 0)
> diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
> index da0ce0b3704c..0b236e08c158 100644
> --- a/drivers/gpu/drm/xe/xe_vm.c
> +++ b/drivers/gpu/drm/xe/xe_vm.c
> @@ -3481,6 +3481,10 @@ static int vm_bind_ioctl_check_args(struct
> xe_device *xe, struct xe_vm *vm,
>  				 op ==
> DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
>  		    XE_IOCTL_DBG(xe, coh_mode == XE_COH_NONE &&
>  				 op ==
> DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
> +		    XE_IOCTL_DBG(xe,
> xe_device_is_l2_flush_optimized(xe) &&
> +				 (op ==
> DRM_XE_VM_BIND_OP_MAP_USERPTR ||
> +				  is_cpu_addr_mirror) &&
> +				 (pat_index != 19 && coh_mode !=
> XE_COH_2WAY)) ||
>  		    XE_IOCTL_DBG(xe, comp_en &&
>  				 op ==
> DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
>  		    XE_IOCTL_DBG(xe, op ==
> DRM_XE_VM_BIND_OP_MAP_USERPTR &&
> @@ -3615,6 +3619,10 @@ static int xe_vm_bind_ioctl_validate_bo(struct
> xe_device *xe, struct xe_bo *bo,
>  	if (XE_IOCTL_DBG(xe, bo->ttm.base.import_attach && comp_en))
>  		return -EINVAL;
>  
> +	if (XE_IOCTL_DBG(xe, bo->ttm.base.import_attach &&
> xe_device_is_l2_flush_optimized(xe) &&
> +			 (pat_index != 19 && coh_mode !=
> XE_COH_2WAY)))
> +		return -EINVAL;
> +
>  	/* If a BO is protected it can only be mapped if the key is
> still valid */
>  	if ((bind_flags & DRM_XE_VM_BIND_FLAG_CHECK_PXP) &&
> xe_bo_is_protected(bo) &&
>  	    op != DRM_XE_VM_BIND_OP_UNMAP && op !=
> DRM_XE_VM_BIND_OP_UNMAP_ALL)
> diff --git a/drivers/gpu/drm/xe/xe_vm_madvise.c
> b/drivers/gpu/drm/xe/xe_vm_madvise.c
> index 07169586e35f..376c014239ee 100644
> --- a/drivers/gpu/drm/xe/xe_vm_madvise.c
> +++ b/drivers/gpu/drm/xe/xe_vm_madvise.c
> @@ -411,6 +411,7 @@ int xe_vm_madvise_ioctl(struct drm_device *dev,
> void *data, struct drm_file *fil
>  	struct xe_vmas_in_madvise_range madvise_range = {.addr =
> args->start,
>  							 .range = 
> args->range, };
>  	struct xe_madvise_details details;
> +	u16 pat_index, coh_mode;
>  	struct xe_vm *vm;
>  	struct drm_exec exec;
>  	int err, attr_type;
> @@ -447,6 +448,17 @@ int xe_vm_madvise_ioctl(struct drm_device *dev,
> void *data, struct drm_file *fil
>  	if (err || !madvise_range.num_vmas)
>  		goto madv_fini;
>  
> +	if (args->type == DRM_XE_MEM_RANGE_ATTR_PAT) {
> +		pat_index = array_index_nospec(args->pat_index.val,
> xe->pat.n_entries);
> +		coh_mode = xe_pat_index_get_coh_mode(xe, pat_index);
> +		if (XE_IOCTL_DBG(xe,
> madvise_range.has_svm_userptr_vmas &&
> +				 xe_device_is_l2_flush_optimized(xe)
> &&
> +				 (pat_index != 19 && coh_mode !=
> XE_COH_2WAY))) {
> +			err = -EINVAL;
> +			goto madv_fini;
> +		}
> +	}
> +
>  	if (madvise_range.has_bo_vmas) {
>  		if (args->type == DRM_XE_MEM_RANGE_ATTR_ATOMIC) {
>  			if (!check_bo_args_are_sane(vm,
> madvise_range.vmas,
> @@ -464,6 +476,17 @@ int xe_vm_madvise_ioctl(struct drm_device *dev,
> void *data, struct drm_file *fil
>  
>  				if (!bo)
>  					continue;
> +
> +				if (args->type ==
> DRM_XE_MEM_RANGE_ATTR_PAT) {
> +					if (XE_IOCTL_DBG(xe, bo-
> >ttm.base.import_attach &&
> +							
> xe_device_is_l2_flush_optimized(xe) &&
> +							 (pat_index
> != 19 &&
> +							  coh_mode
> != XE_COH_2WAY))) {
> +						err = -EINVAL;
> +						goto err_fini;
> +					}
> +				}
> +
>  				err = drm_exec_lock_obj(&exec, &bo-
> >ttm.base);
>  				drm_exec_retry_on_contention(&exec);
>  				if (err)
> diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
> index ef2565048bdf..862fed3cf1ed 100644
> --- a/include/uapi/drm/xe_drm.h
> +++ b/include/uapi/drm/xe_drm.h
> @@ -1103,7 +1103,9 @@ struct drm_xe_vm_bind_op {
>  	 * incoherent GT access is possible.
>  	 *
>  	 * Note: For userptr and externally imported dma-buf the
> kernel expects
> -	 * either 1WAY or 2WAY for the @pat_index.
> +	 * either 1WAY or 2WAY for the @pat_index. Starting from
> NVL-P, for
> +	 * userptr, svm, madvise and externally imported dma-buf the
> kernel expects
> +	 * either 2WAY or 1WAY and XA @pat_index.
>  	 *
>  	 * For DRM_XE_VM_BIND_FLAG_NULL bindings there are no KMD
> restrictions
>  	 * on the @pat_index. For such mappings there is no actual
> memory being

Re: [PATCH V6 3/4] drm/xe/xe3p_lpg: Restrict UAPI to enable L2 flush optimization

[Matthew Auld]

On 05/03/2026 12:19, Tejas Upadhyay wrote:
> When set, starting xe3p_lpg, the L2 flush optimization
> feature will control whether L2 is in Persistent or
> Transient mode through monitoring of media activity.
> 
> To enable L2 flush optimization include new feature flag
> GUC_CTL_ENABLE_L2FLUSH_OPT for Novalake platforms when
> media type is detected.
> 
> Tighten UAPI validation to restrict userptr, svm and
> dmabuf mappings to be either 2WAY or XA+1WAY
> 
> V5(Thomas): logic correction
> V4(MattA): Modify uapi doc and commit
> V3(MattA): check valid op and pat_index value
> V2(MattA): validate dma-buf bos and madvise pat-index
> 
> Acked-by: José Roberto de Souza <jose.souza@intel.com>
> Acked-by: Michal Mrozek <michal.mrozek@intel.com>
> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
> ---
>   drivers/gpu/drm/xe/xe_guc.c        |  3 +++
>   drivers/gpu/drm/xe/xe_guc_fwif.h   |  1 +
>   drivers/gpu/drm/xe/xe_vm.c         |  8 ++++++++
>   drivers/gpu/drm/xe/xe_vm_madvise.c | 23 +++++++++++++++++++++++
>   include/uapi/drm/xe_drm.h          |  4 +++-
>   5 files changed, 38 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
> index 54d2fc780127..43dc4353206f 100644
> --- a/drivers/gpu/drm/xe/xe_guc.c
> +++ b/drivers/gpu/drm/xe/xe_guc.c
> @@ -98,6 +98,9 @@ static u32 guc_ctl_feature_flags(struct xe_guc *guc)
>   	if (xe_guc_using_main_gamctrl_queues(guc))
>   		flags |= GUC_CTL_MAIN_GAMCTRL_QUEUES;
>   
> +	if (GRAPHICS_VER(xe) >= 35 && !IS_DGFX(xe) && xe_gt_is_media_type(guc_to_gt(guc)))
> +		flags |= GUC_CTL_ENABLE_L2FLUSH_OPT;

Pending whether we also need this on primary GT or not. Since it sounded 
like it would also need to know whether to do a targeted or full flush 
based on current Media status, and it's unclear if here we are meant to 
opt into that for every GT/GuC instance vs just the Media GuC.

Reviewed-by: Matthew Auld <matthew.auld@intel.com>

> +
>   	return flags;
>   }
>   
> diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h b/drivers/gpu/drm/xe/xe_guc_fwif.h
> index bb8f71d38611..b73fae063fac 100644
> --- a/drivers/gpu/drm/xe/xe_guc_fwif.h
> +++ b/drivers/gpu/drm/xe/xe_guc_fwif.h
> @@ -67,6 +67,7 @@ struct guc_update_exec_queue_policy {
>   #define   GUC_CTL_ENABLE_PSMI_LOGGING	BIT(7)
>   #define   GUC_CTL_MAIN_GAMCTRL_QUEUES	BIT(9)
>   #define   GUC_CTL_DISABLE_SCHEDULER	BIT(14)
> +#define   GUC_CTL_ENABLE_L2FLUSH_OPT	BIT(15)
>   
>   #define GUC_CTL_DEBUG			3
>   #define   GUC_LOG_VERBOSITY		REG_GENMASK(1, 0)
> diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
> index da0ce0b3704c..0b236e08c158 100644
> --- a/drivers/gpu/drm/xe/xe_vm.c
> +++ b/drivers/gpu/drm/xe/xe_vm.c
> @@ -3481,6 +3481,10 @@ static int vm_bind_ioctl_check_args(struct xe_device *xe, struct xe_vm *vm,
>   				 op == DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
>   		    XE_IOCTL_DBG(xe, coh_mode == XE_COH_NONE &&
>   				 op == DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
> +		    XE_IOCTL_DBG(xe, xe_device_is_l2_flush_optimized(xe) &&
> +				 (op == DRM_XE_VM_BIND_OP_MAP_USERPTR ||
> +				  is_cpu_addr_mirror) &&
> +				 (pat_index != 19 && coh_mode != XE_COH_2WAY)) ||
>   		    XE_IOCTL_DBG(xe, comp_en &&
>   				 op == DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
>   		    XE_IOCTL_DBG(xe, op == DRM_XE_VM_BIND_OP_MAP_USERPTR &&
> @@ -3615,6 +3619,10 @@ static int xe_vm_bind_ioctl_validate_bo(struct xe_device *xe, struct xe_bo *bo,
>   	if (XE_IOCTL_DBG(xe, bo->ttm.base.import_attach && comp_en))
>   		return -EINVAL;
>   
> +	if (XE_IOCTL_DBG(xe, bo->ttm.base.import_attach && xe_device_is_l2_flush_optimized(xe) &&
> +			 (pat_index != 19 && coh_mode != XE_COH_2WAY)))
> +		return -EINVAL;
> +
>   	/* If a BO is protected it can only be mapped if the key is still valid */
>   	if ((bind_flags & DRM_XE_VM_BIND_FLAG_CHECK_PXP) && xe_bo_is_protected(bo) &&
>   	    op != DRM_XE_VM_BIND_OP_UNMAP && op != DRM_XE_VM_BIND_OP_UNMAP_ALL)
> diff --git a/drivers/gpu/drm/xe/xe_vm_madvise.c b/drivers/gpu/drm/xe/xe_vm_madvise.c
> index 07169586e35f..376c014239ee 100644
> --- a/drivers/gpu/drm/xe/xe_vm_madvise.c
> +++ b/drivers/gpu/drm/xe/xe_vm_madvise.c
> @@ -411,6 +411,7 @@ int xe_vm_madvise_ioctl(struct drm_device *dev, void *data, struct drm_file *fil
>   	struct xe_vmas_in_madvise_range madvise_range = {.addr = args->start,
>   							 .range =  args->range, };
>   	struct xe_madvise_details details;
> +	u16 pat_index, coh_mode;
>   	struct xe_vm *vm;
>   	struct drm_exec exec;
>   	int err, attr_type;
> @@ -447,6 +448,17 @@ int xe_vm_madvise_ioctl(struct drm_device *dev, void *data, struct drm_file *fil
>   	if (err || !madvise_range.num_vmas)
>   		goto madv_fini;
>   
> +	if (args->type == DRM_XE_MEM_RANGE_ATTR_PAT) {
> +		pat_index = array_index_nospec(args->pat_index.val, xe->pat.n_entries);
> +		coh_mode = xe_pat_index_get_coh_mode(xe, pat_index);
> +		if (XE_IOCTL_DBG(xe, madvise_range.has_svm_userptr_vmas &&
> +				 xe_device_is_l2_flush_optimized(xe) &&
> +				 (pat_index != 19 && coh_mode != XE_COH_2WAY))) {
> +			err = -EINVAL;
> +			goto madv_fini;
> +		}
> +	}
> +
>   	if (madvise_range.has_bo_vmas) {
>   		if (args->type == DRM_XE_MEM_RANGE_ATTR_ATOMIC) {
>   			if (!check_bo_args_are_sane(vm, madvise_range.vmas,
> @@ -464,6 +476,17 @@ int xe_vm_madvise_ioctl(struct drm_device *dev, void *data, struct drm_file *fil
>   
>   				if (!bo)
>   					continue;
> +
> +				if (args->type == DRM_XE_MEM_RANGE_ATTR_PAT) {
> +					if (XE_IOCTL_DBG(xe, bo->ttm.base.import_attach &&
> +							 xe_device_is_l2_flush_optimized(xe) &&
> +							 (pat_index != 19 &&
> +							  coh_mode != XE_COH_2WAY))) {
> +						err = -EINVAL;
> +						goto err_fini;
> +					}
> +				}
> +
>   				err = drm_exec_lock_obj(&exec, &bo->ttm.base);
>   				drm_exec_retry_on_contention(&exec);
>   				if (err)
> diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
> index ef2565048bdf..862fed3cf1ed 100644
> --- a/include/uapi/drm/xe_drm.h
> +++ b/include/uapi/drm/xe_drm.h
> @@ -1103,7 +1103,9 @@ struct drm_xe_vm_bind_op {
>   	 * incoherent GT access is possible.
>   	 *
>   	 * Note: For userptr and externally imported dma-buf the kernel expects
> -	 * either 1WAY or 2WAY for the @pat_index.
> +	 * either 1WAY or 2WAY for the @pat_index. Starting from NVL-P, for
> +	 * userptr, svm, madvise and externally imported dma-buf the kernel expects
> +	 * either 2WAY or 1WAY and XA @pat_index.
>   	 *
>   	 * For DRM_XE_VM_BIND_FLAG_NULL bindings there are no KMD restrictions
>   	 * on the @pat_index. For such mappings there is no actual memory being

RE: [PATCH V6 3/4] drm/xe/xe3p_lpg: Restrict UAPI to enable L2 flush optimization

[Upadhyay, Tejas]

> -----Original Message-----
> From: Auld, Matthew <matthew.auld@intel.com>
> Sent: 05 March 2026 19:30
> To: Upadhyay, Tejas <tejas.upadhyay@intel.com>; intel-
> xe@lists.freedesktop.org
> Cc: thomas.hellstrom@linux.intel.com; Zhang, Carl <carl.zhang@intel.com>;
> Souza, Jose <jose.souza@intel.com>; Mrozek, Michal
> <michal.mrozek@intel.com>
> Subject: Re: [PATCH V6 3/4] drm/xe/xe3p_lpg: Restrict UAPI to enable L2 flush
> optimization
> 
> On 05/03/2026 12:19, Tejas Upadhyay wrote:
> > When set, starting xe3p_lpg, the L2 flush optimization feature will
> > control whether L2 is in Persistent or Transient mode through
> > monitoring of media activity.
> >
> > To enable L2 flush optimization include new feature flag
> > GUC_CTL_ENABLE_L2FLUSH_OPT for Novalake platforms when media type is
> > detected.
> >
> > Tighten UAPI validation to restrict userptr, svm and dmabuf mappings
> > to be either 2WAY or XA+1WAY
> >
> > V5(Thomas): logic correction
> > V4(MattA): Modify uapi doc and commit
> > V3(MattA): check valid op and pat_index value
> > V2(MattA): validate dma-buf bos and madvise pat-index
> >
> > Acked-by: José Roberto de Souza <jose.souza@intel.com>
> > Acked-by: Michal Mrozek <michal.mrozek@intel.com>
> > Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
> > ---
> >   drivers/gpu/drm/xe/xe_guc.c        |  3 +++
> >   drivers/gpu/drm/xe/xe_guc_fwif.h   |  1 +
> >   drivers/gpu/drm/xe/xe_vm.c         |  8 ++++++++
> >   drivers/gpu/drm/xe/xe_vm_madvise.c | 23 +++++++++++++++++++++++
> >   include/uapi/drm/xe_drm.h          |  4 +++-
> >   5 files changed, 38 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
> > index 54d2fc780127..43dc4353206f 100644
> > --- a/drivers/gpu/drm/xe/xe_guc.c
> > +++ b/drivers/gpu/drm/xe/xe_guc.c
> > @@ -98,6 +98,9 @@ static u32 guc_ctl_feature_flags(struct xe_guc *guc)
> >   	if (xe_guc_using_main_gamctrl_queues(guc))
> >   		flags |= GUC_CTL_MAIN_GAMCTRL_QUEUES;
> >
> > +	if (GRAPHICS_VER(xe) >= 35 && !IS_DGFX(xe) &&
> xe_gt_is_media_type(guc_to_gt(guc)))
> > +		flags |= GUC_CTL_ENABLE_L2FLUSH_OPT;
> 
> Pending whether we also need this on primary GT or not. Since it sounded like
> it would also need to know whether to do a targeted or full flush based on
> current Media status, and it's unclear if here we are meant to opt into that for
> every GT/GuC instance vs just the Media GuC.

By default media is on, so full flush is in place. Setting media off will be controlled by media GuC thus optimization will be controlled by media GuC only so enable on media GT only. Right? @Ceraolo Spurio, Daniele @Young, Dawson H @Li, Yaodong

Tejas
> 
> Reviewed-by: Matthew Auld <matthew.auld@intel.com>
> 
> > +
> >   	return flags;
> >   }
> >
> > diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h
> > b/drivers/gpu/drm/xe/xe_guc_fwif.h
> > index bb8f71d38611..b73fae063fac 100644
> > --- a/drivers/gpu/drm/xe/xe_guc_fwif.h
> > +++ b/drivers/gpu/drm/xe/xe_guc_fwif.h
> > @@ -67,6 +67,7 @@ struct guc_update_exec_queue_policy {
> >   #define   GUC_CTL_ENABLE_PSMI_LOGGING	BIT(7)
> >   #define   GUC_CTL_MAIN_GAMCTRL_QUEUES	BIT(9)
> >   #define   GUC_CTL_DISABLE_SCHEDULER	BIT(14)
> > +#define   GUC_CTL_ENABLE_L2FLUSH_OPT	BIT(15)
> >
> >   #define GUC_CTL_DEBUG			3
> >   #define   GUC_LOG_VERBOSITY		REG_GENMASK(1, 0)
> > diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
> > index da0ce0b3704c..0b236e08c158 100644
> > --- a/drivers/gpu/drm/xe/xe_vm.c
> > +++ b/drivers/gpu/drm/xe/xe_vm.c
> > @@ -3481,6 +3481,10 @@ static int vm_bind_ioctl_check_args(struct
> xe_device *xe, struct xe_vm *vm,
> >   				 op ==
> DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
> >   		    XE_IOCTL_DBG(xe, coh_mode == XE_COH_NONE &&
> >   				 op ==
> DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
> > +		    XE_IOCTL_DBG(xe, xe_device_is_l2_flush_optimized(xe) &&
> > +				 (op ==
> DRM_XE_VM_BIND_OP_MAP_USERPTR ||
> > +				  is_cpu_addr_mirror) &&
> > +				 (pat_index != 19 && coh_mode !=
> XE_COH_2WAY)) ||
> >   		    XE_IOCTL_DBG(xe, comp_en &&
> >   				 op ==
> DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
> >   		    XE_IOCTL_DBG(xe, op ==
> DRM_XE_VM_BIND_OP_MAP_USERPTR && @@
> > -3615,6 +3619,10 @@ static int xe_vm_bind_ioctl_validate_bo(struct
> xe_device *xe, struct xe_bo *bo,
> >   	if (XE_IOCTL_DBG(xe, bo->ttm.base.import_attach && comp_en))
> >   		return -EINVAL;
> >
> > +	if (XE_IOCTL_DBG(xe, bo->ttm.base.import_attach &&
> xe_device_is_l2_flush_optimized(xe) &&
> > +			 (pat_index != 19 && coh_mode != XE_COH_2WAY)))
> > +		return -EINVAL;
> > +
> >   	/* If a BO is protected it can only be mapped if the key is still valid */
> >   	if ((bind_flags & DRM_XE_VM_BIND_FLAG_CHECK_PXP) &&
> xe_bo_is_protected(bo) &&
> >   	    op != DRM_XE_VM_BIND_OP_UNMAP && op !=
> > DRM_XE_VM_BIND_OP_UNMAP_ALL) diff --git
> > a/drivers/gpu/drm/xe/xe_vm_madvise.c
> > b/drivers/gpu/drm/xe/xe_vm_madvise.c
> > index 07169586e35f..376c014239ee 100644
> > --- a/drivers/gpu/drm/xe/xe_vm_madvise.c
> > +++ b/drivers/gpu/drm/xe/xe_vm_madvise.c
> > @@ -411,6 +411,7 @@ int xe_vm_madvise_ioctl(struct drm_device *dev,
> void *data, struct drm_file *fil
> >   	struct xe_vmas_in_madvise_range madvise_range = {.addr = args-
> >start,
> >   							 .range =  args->range,
> };
> >   	struct xe_madvise_details details;
> > +	u16 pat_index, coh_mode;
> >   	struct xe_vm *vm;
> >   	struct drm_exec exec;
> >   	int err, attr_type;
> > @@ -447,6 +448,17 @@ int xe_vm_madvise_ioctl(struct drm_device *dev,
> void *data, struct drm_file *fil
> >   	if (err || !madvise_range.num_vmas)
> >   		goto madv_fini;
> >
> > +	if (args->type == DRM_XE_MEM_RANGE_ATTR_PAT) {
> > +		pat_index = array_index_nospec(args->pat_index.val, xe-
> >pat.n_entries);
> > +		coh_mode = xe_pat_index_get_coh_mode(xe, pat_index);
> > +		if (XE_IOCTL_DBG(xe, madvise_range.has_svm_userptr_vmas
> &&
> > +				 xe_device_is_l2_flush_optimized(xe) &&
> > +				 (pat_index != 19 && coh_mode !=
> XE_COH_2WAY))) {
> > +			err = -EINVAL;
> > +			goto madv_fini;
> > +		}
> > +	}
> > +
> >   	if (madvise_range.has_bo_vmas) {
> >   		if (args->type == DRM_XE_MEM_RANGE_ATTR_ATOMIC) {
> >   			if (!check_bo_args_are_sane(vm,
> madvise_range.vmas, @@ -464,6
> > +476,17 @@ int xe_vm_madvise_ioctl(struct drm_device *dev, void *data,
> > struct drm_file *fil
> >
> >   				if (!bo)
> >   					continue;
> > +
> > +				if (args->type ==
> DRM_XE_MEM_RANGE_ATTR_PAT) {
> > +					if (XE_IOCTL_DBG(xe, bo-
> >ttm.base.import_attach &&
> > +
> xe_device_is_l2_flush_optimized(xe) &&
> > +							 (pat_index != 19 &&
> > +							  coh_mode !=
> XE_COH_2WAY))) {
> > +						err = -EINVAL;
> > +						goto err_fini;
> > +					}
> > +				}
> > +
> >   				err = drm_exec_lock_obj(&exec, &bo-
> >ttm.base);
> >   				drm_exec_retry_on_contention(&exec);
> >   				if (err)
> > diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
> > index ef2565048bdf..862fed3cf1ed 100644
> > --- a/include/uapi/drm/xe_drm.h
> > +++ b/include/uapi/drm/xe_drm.h
> > @@ -1103,7 +1103,9 @@ struct drm_xe_vm_bind_op {
> >   	 * incoherent GT access is possible.
> >   	 *
> >   	 * Note: For userptr and externally imported dma-buf the kernel
> expects
> > -	 * either 1WAY or 2WAY for the @pat_index.
> > +	 * either 1WAY or 2WAY for the @pat_index. Starting from NVL-P, for
> > +	 * userptr, svm, madvise and externally imported dma-buf the kernel
> expects
> > +	 * either 2WAY or 1WAY and XA @pat_index.
> >   	 *
> >   	 * For DRM_XE_VM_BIND_FLAG_NULL bindings there are no KMD
> restrictions
> >   	 * on the @pat_index. For such mappings there is no actual memory
> > being

RE: [PATCH V6 3/4] drm/xe/xe3p_lpg: Restrict UAPI to enable L2 flush optimization

[Zhang, Carl]

My understanding:
1. GuC uses a timer to monitor media activity status. The mode becomes active only when no media tasks have been detected for 5 seconds. From the media perspective, this allows legacy behavior to be maintained without requiring any changes.
2. The media UMD only needs to set usage hints to gmmlib, which then manages the PAT index. Therefore, the UMD itself should not require changes—only gmmlib needs to be updated to return PAT index 19 on NVL for imported surfaces.
My open is:
1. In some applications (e.g., ChromeOS), memory is allocated centrally (possibly by minigbm) and then shared across different components. If there are no media tasks, the system operates in persistent mode. However, based on current interfaces, imported memory should be configured as transient + 1-way coherency. This raises a question: if this memory is used exclusively by compute (not media), is this the expected behavior?
2. For userptr memory that is used by only one component, I believe 1-way coherency should be sufficient?

Thanks
Carl

> -----Original Message-----
> From: Auld, Matthew <matthew.auld@intel.com>
> Sent: Thursday, March 5, 2026 10:00 PM
> To: Upadhyay, Tejas <tejas.upadhyay@intel.com>; intel-
> xe@lists.freedesktop.org
> Cc: thomas.hellstrom@linux.intel.com; Zhang, Carl <carl.zhang@intel.com>;
> Souza, Jose <jose.souza@intel.com>; Mrozek, Michal
> <michal.mrozek@intel.com>
> Subject: Re: [PATCH V6 3/4] drm/xe/xe3p_lpg: Restrict UAPI to enable L2 flush
> optimization
> 
> On 05/03/2026 12:19, Tejas Upadhyay wrote:
> > When set, starting xe3p_lpg, the L2 flush optimization feature will
> > control whether L2 is in Persistent or Transient mode through
> > monitoring of media activity.
> >
> > To enable L2 flush optimization include new feature flag
> > GUC_CTL_ENABLE_L2FLUSH_OPT for Novalake platforms when media type
> is
> > detected.
> >
> > Tighten UAPI validation to restrict userptr, svm and dmabuf mappings
> > to be either 2WAY or XA+1WAY
> >
> > V5(Thomas): logic correction
> > V4(MattA): Modify uapi doc and commit
> > V3(MattA): check valid op and pat_index value
> > V2(MattA): validate dma-buf bos and madvise pat-index
> >
> > Acked-by: José Roberto de Souza <jose.souza@intel.com>
> > Acked-by: Michal Mrozek <michal.mrozek@intel.com>
> > Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
> > ---
> >   drivers/gpu/drm/xe/xe_guc.c        |  3 +++
> >   drivers/gpu/drm/xe/xe_guc_fwif.h   |  1 +
> >   drivers/gpu/drm/xe/xe_vm.c         |  8 ++++++++
> >   drivers/gpu/drm/xe/xe_vm_madvise.c | 23 +++++++++++++++++++++++
> >   include/uapi/drm/xe_drm.h          |  4 +++-
> >   5 files changed, 38 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
> > index 54d2fc780127..43dc4353206f 100644
> > --- a/drivers/gpu/drm/xe/xe_guc.c
> > +++ b/drivers/gpu/drm/xe/xe_guc.c
> > @@ -98,6 +98,9 @@ static u32 guc_ctl_feature_flags(struct xe_guc *guc)
> >   	if (xe_guc_using_main_gamctrl_queues(guc))
> >   		flags |= GUC_CTL_MAIN_GAMCTRL_QUEUES;
> >
> > +	if (GRAPHICS_VER(xe) >= 35 && !IS_DGFX(xe) &&
> xe_gt_is_media_type(guc_to_gt(guc)))
> > +		flags |= GUC_CTL_ENABLE_L2FLUSH_OPT;
> 
> Pending whether we also need this on primary GT or not. Since it sounded
> like it would also need to know whether to do a targeted or full flush based
> on current Media status, and it's unclear if here we are meant to opt into that
> for every GT/GuC instance vs just the Media GuC.
> 
> Reviewed-by: Matthew Auld <matthew.auld@intel.com>
> 
> > +
> >   	return flags;
> >   }
> >
> > diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h
> > b/drivers/gpu/drm/xe/xe_guc_fwif.h
> > index bb8f71d38611..b73fae063fac 100644
> > --- a/drivers/gpu/drm/xe/xe_guc_fwif.h
> > +++ b/drivers/gpu/drm/xe/xe_guc_fwif.h
> > @@ -67,6 +67,7 @@ struct guc_update_exec_queue_policy {
> >   #define   GUC_CTL_ENABLE_PSMI_LOGGING	BIT(7)
> >   #define   GUC_CTL_MAIN_GAMCTRL_QUEUES	BIT(9)
> >   #define   GUC_CTL_DISABLE_SCHEDULER	BIT(14)
> > +#define   GUC_CTL_ENABLE_L2FLUSH_OPT	BIT(15)
> >
> >   #define GUC_CTL_DEBUG			3
> >   #define   GUC_LOG_VERBOSITY		REG_GENMASK(1, 0)
> > diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
> > index da0ce0b3704c..0b236e08c158 100644
> > --- a/drivers/gpu/drm/xe/xe_vm.c
> > +++ b/drivers/gpu/drm/xe/xe_vm.c
> > @@ -3481,6 +3481,10 @@ static int vm_bind_ioctl_check_args(struct
> xe_device *xe, struct xe_vm *vm,
> >   				 op ==
> DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
> >   		    XE_IOCTL_DBG(xe, coh_mode == XE_COH_NONE &&
> >   				 op ==
> DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
> > +		    XE_IOCTL_DBG(xe, xe_device_is_l2_flush_optimized(xe) &&
> > +				 (op ==
> DRM_XE_VM_BIND_OP_MAP_USERPTR ||
> > +				  is_cpu_addr_mirror) &&
> > +				 (pat_index != 19 && coh_mode !=
> XE_COH_2WAY)) ||
> >   		    XE_IOCTL_DBG(xe, comp_en &&
> >   				 op ==
> DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
> >   		    XE_IOCTL_DBG(xe, op ==
> DRM_XE_VM_BIND_OP_MAP_USERPTR && @@
> > -3615,6 +3619,10 @@ static int xe_vm_bind_ioctl_validate_bo(struct
> xe_device *xe, struct xe_bo *bo,
> >   	if (XE_IOCTL_DBG(xe, bo->ttm.base.import_attach && comp_en))
> >   		return -EINVAL;
> >
> > +	if (XE_IOCTL_DBG(xe, bo->ttm.base.import_attach &&
> xe_device_is_l2_flush_optimized(xe) &&
> > +			 (pat_index != 19 && coh_mode != XE_COH_2WAY)))
> > +		return -EINVAL;
> > +
> >   	/* If a BO is protected it can only be mapped if the key is still valid */
> >   	if ((bind_flags & DRM_XE_VM_BIND_FLAG_CHECK_PXP) &&
> xe_bo_is_protected(bo) &&
> >   	    op != DRM_XE_VM_BIND_OP_UNMAP && op !=
> > DRM_XE_VM_BIND_OP_UNMAP_ALL) diff --git
> > a/drivers/gpu/drm/xe/xe_vm_madvise.c
> > b/drivers/gpu/drm/xe/xe_vm_madvise.c
> > index 07169586e35f..376c014239ee 100644
> > --- a/drivers/gpu/drm/xe/xe_vm_madvise.c
> > +++ b/drivers/gpu/drm/xe/xe_vm_madvise.c
> > @@ -411,6 +411,7 @@ int xe_vm_madvise_ioctl(struct drm_device *dev,
> void *data, struct drm_file *fil
> >   	struct xe_vmas_in_madvise_range madvise_range = {.addr = args-
> >start,
> >   							 .range =  args-
> >range, };
> >   	struct xe_madvise_details details;
> > +	u16 pat_index, coh_mode;
> >   	struct xe_vm *vm;
> >   	struct drm_exec exec;
> >   	int err, attr_type;
> > @@ -447,6 +448,17 @@ int xe_vm_madvise_ioctl(struct drm_device *dev,
> void *data, struct drm_file *fil
> >   	if (err || !madvise_range.num_vmas)
> >   		goto madv_fini;
> >
> > +	if (args->type == DRM_XE_MEM_RANGE_ATTR_PAT) {
> > +		pat_index = array_index_nospec(args->pat_index.val, xe-
> >pat.n_entries);
> > +		coh_mode = xe_pat_index_get_coh_mode(xe, pat_index);
> > +		if (XE_IOCTL_DBG(xe, madvise_range.has_svm_userptr_vmas
> &&
> > +				 xe_device_is_l2_flush_optimized(xe) &&
> > +				 (pat_index != 19 && coh_mode !=
> XE_COH_2WAY))) {
> > +			err = -EINVAL;
> > +			goto madv_fini;
> > +		}
> > +	}
> > +
> >   	if (madvise_range.has_bo_vmas) {
> >   		if (args->type == DRM_XE_MEM_RANGE_ATTR_ATOMIC) {
> >   			if (!check_bo_args_are_sane(vm,
> madvise_range.vmas, @@ -464,6
> > +476,17 @@ int xe_vm_madvise_ioctl(struct drm_device *dev, void *data,
> > struct drm_file *fil
> >
> >   				if (!bo)
> >   					continue;
> > +
> > +				if (args->type ==
> DRM_XE_MEM_RANGE_ATTR_PAT) {
> > +					if (XE_IOCTL_DBG(xe, bo-
> >ttm.base.import_attach &&
> > +
> xe_device_is_l2_flush_optimized(xe) &&
> > +							 (pat_index != 19 &&
> > +							  coh_mode !=
> XE_COH_2WAY))) {
> > +						err = -EINVAL;
> > +						goto err_fini;
> > +					}
> > +				}
> > +
> >   				err = drm_exec_lock_obj(&exec, &bo-
> >ttm.base);
> >   				drm_exec_retry_on_contention(&exec);
> >   				if (err)
> > diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
> > index ef2565048bdf..862fed3cf1ed 100644
> > --- a/include/uapi/drm/xe_drm.h
> > +++ b/include/uapi/drm/xe_drm.h
> > @@ -1103,7 +1103,9 @@ struct drm_xe_vm_bind_op {
> >   	 * incoherent GT access is possible.
> >   	 *
> >   	 * Note: For userptr and externally imported dma-buf the kernel
> expects
> > -	 * either 1WAY or 2WAY for the @pat_index.
> > +	 * either 1WAY or 2WAY for the @pat_index. Starting from NVL-P, for
> > +	 * userptr, svm, madvise and externally imported dma-buf the kernel
> expects
> > +	 * either 2WAY or 1WAY and XA @pat_index.
> >   	 *
> >   	 * For DRM_XE_VM_BIND_FLAG_NULL bindings there are no KMD
> restrictions
> >   	 * on the @pat_index. For such mappings there is no actual memory
> > being

RE: [PATCH V6 3/4] drm/xe/xe3p_lpg: Restrict UAPI to enable L2 flush optimization

[Upadhyay, Tejas]

> -----Original Message-----
> From: Zhang, Carl <carl.zhang@intel.com>
> Sent: 06 March 2026 12:42
> To: Auld, Matthew <matthew.auld@intel.com>; Upadhyay, Tejas
> <tejas.upadhyay@intel.com>; intel-xe@lists.freedesktop.org
> Cc: thomas.hellstrom@linux.intel.com; Souza, Jose <jose.souza@intel.com>;
> Mrozek, Michal <michal.mrozek@intel.com>
> Subject: RE: [PATCH V6 3/4] drm/xe/xe3p_lpg: Restrict UAPI to enable L2 flush
> optimization
> 
> My understanding:
> 1. GuC uses a timer to monitor media activity status. The mode becomes
> active only when no media tasks have been detected for 5 seconds. From the
> media perspective, this allows legacy behavior to be maintained without
> requiring any changes.
> 2. The media UMD only needs to set usage hints to gmmlib, which then
> manages the PAT index. Therefore, the UMD itself should not require
> changes—only gmmlib needs to be updated to return PAT index 19 on NVL for
> imported surfaces.
> My open is:
> 1. In some applications (e.g., ChromeOS), memory is allocated centrally
> (possibly by minigbm) and then shared across different components. If there
> are no media tasks, the system operates in persistent mode. However, based
> on current interfaces, imported memory should be configured as transient + 1-
> way coherency. This raises a question: if this memory is used exclusively by
> compute (not media), is this the expected behavior?
> 2. For userptr memory that is used by only one component, I believe 1-way
> coherency should be sufficient?

As a kernel, how would it know in which order component will use memory. For example we have media only and submits something, kernel would allow since media (so no PAT restrictions), so optimization will not be active in GuC. Later some compute component (allowed without PAT restrictions) by other UMD started activity, flush optimization will be OFF and then previous media component becomes inactive. Now flush optimization turned ON by GuC, and compute component may have stale memory as full flush isn’t happening if right PAT isn’t used.

Tejas
> 
> Thanks
> Carl
> 
> > -----Original Message-----
> > From: Auld, Matthew <matthew.auld@intel.com>
> > Sent: Thursday, March 5, 2026 10:00 PM
> > To: Upadhyay, Tejas <tejas.upadhyay@intel.com>; intel-
> > xe@lists.freedesktop.org
> > Cc: thomas.hellstrom@linux.intel.com; Zhang, Carl
> > <carl.zhang@intel.com>; Souza, Jose <jose.souza@intel.com>; Mrozek,
> > Michal <michal.mrozek@intel.com>
> > Subject: Re: [PATCH V6 3/4] drm/xe/xe3p_lpg: Restrict UAPI to enable
> > L2 flush optimization
> >
> > On 05/03/2026 12:19, Tejas Upadhyay wrote:
> > > When set, starting xe3p_lpg, the L2 flush optimization feature will
> > > control whether L2 is in Persistent or Transient mode through
> > > monitoring of media activity.
> > >
> > > To enable L2 flush optimization include new feature flag
> > > GUC_CTL_ENABLE_L2FLUSH_OPT for Novalake platforms when media type
> > is
> > > detected.
> > >
> > > Tighten UAPI validation to restrict userptr, svm and dmabuf mappings
> > > to be either 2WAY or XA+1WAY
> > >
> > > V5(Thomas): logic correction
> > > V4(MattA): Modify uapi doc and commit
> > > V3(MattA): check valid op and pat_index value
> > > V2(MattA): validate dma-buf bos and madvise pat-index
> > >
> > > Acked-by: José Roberto de Souza <jose.souza@intel.com>
> > > Acked-by: Michal Mrozek <michal.mrozek@intel.com>
> > > Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
> > > ---
> > >   drivers/gpu/drm/xe/xe_guc.c        |  3 +++
> > >   drivers/gpu/drm/xe/xe_guc_fwif.h   |  1 +
> > >   drivers/gpu/drm/xe/xe_vm.c         |  8 ++++++++
> > >   drivers/gpu/drm/xe/xe_vm_madvise.c | 23
> +++++++++++++++++++++++
> > >   include/uapi/drm/xe_drm.h          |  4 +++-
> > >   5 files changed, 38 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/xe/xe_guc.c
> > > b/drivers/gpu/drm/xe/xe_guc.c index 54d2fc780127..43dc4353206f
> > > 100644
> > > --- a/drivers/gpu/drm/xe/xe_guc.c
> > > +++ b/drivers/gpu/drm/xe/xe_guc.c
> > > @@ -98,6 +98,9 @@ static u32 guc_ctl_feature_flags(struct xe_guc *guc)
> > >   	if (xe_guc_using_main_gamctrl_queues(guc))
> > >   		flags |= GUC_CTL_MAIN_GAMCTRL_QUEUES;
> > >
> > > +	if (GRAPHICS_VER(xe) >= 35 && !IS_DGFX(xe) &&
> > xe_gt_is_media_type(guc_to_gt(guc)))
> > > +		flags |= GUC_CTL_ENABLE_L2FLUSH_OPT;
> >
> > Pending whether we also need this on primary GT or not. Since it
> > sounded like it would also need to know whether to do a targeted or
> > full flush based on current Media status, and it's unclear if here we
> > are meant to opt into that for every GT/GuC instance vs just the Media GuC.
> >
> > Reviewed-by: Matthew Auld <matthew.auld@intel.com>
> >
> > > +
> > >   	return flags;
> > >   }
> > >
> > > diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h
> > > b/drivers/gpu/drm/xe/xe_guc_fwif.h
> > > index bb8f71d38611..b73fae063fac 100644
> > > --- a/drivers/gpu/drm/xe/xe_guc_fwif.h
> > > +++ b/drivers/gpu/drm/xe/xe_guc_fwif.h
> > > @@ -67,6 +67,7 @@ struct guc_update_exec_queue_policy {
> > >   #define   GUC_CTL_ENABLE_PSMI_LOGGING	BIT(7)
> > >   #define   GUC_CTL_MAIN_GAMCTRL_QUEUES	BIT(9)
> > >   #define   GUC_CTL_DISABLE_SCHEDULER	BIT(14)
> > > +#define   GUC_CTL_ENABLE_L2FLUSH_OPT	BIT(15)
> > >
> > >   #define GUC_CTL_DEBUG			3
> > >   #define   GUC_LOG_VERBOSITY		REG_GENMASK(1, 0)
> > > diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
> > > index da0ce0b3704c..0b236e08c158 100644
> > > --- a/drivers/gpu/drm/xe/xe_vm.c
> > > +++ b/drivers/gpu/drm/xe/xe_vm.c
> > > @@ -3481,6 +3481,10 @@ static int vm_bind_ioctl_check_args(struct
> > xe_device *xe, struct xe_vm *vm,
> > >   				 op ==
> > DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
> > >   		    XE_IOCTL_DBG(xe, coh_mode == XE_COH_NONE &&
> > >   				 op ==
> > DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
> > > +		    XE_IOCTL_DBG(xe, xe_device_is_l2_flush_optimized(xe) &&
> > > +				 (op ==
> > DRM_XE_VM_BIND_OP_MAP_USERPTR ||
> > > +				  is_cpu_addr_mirror) &&
> > > +				 (pat_index != 19 && coh_mode !=
> > XE_COH_2WAY)) ||
> > >   		    XE_IOCTL_DBG(xe, comp_en &&
> > >   				 op ==
> > DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
> > >   		    XE_IOCTL_DBG(xe, op ==
> > DRM_XE_VM_BIND_OP_MAP_USERPTR && @@
> > > -3615,6 +3619,10 @@ static int xe_vm_bind_ioctl_validate_bo(struct
> > xe_device *xe, struct xe_bo *bo,
> > >   	if (XE_IOCTL_DBG(xe, bo->ttm.base.import_attach && comp_en))
> > >   		return -EINVAL;
> > >
> > > +	if (XE_IOCTL_DBG(xe, bo->ttm.base.import_attach &&
> > xe_device_is_l2_flush_optimized(xe) &&
> > > +			 (pat_index != 19 && coh_mode != XE_COH_2WAY)))
> > > +		return -EINVAL;
> > > +
> > >   	/* If a BO is protected it can only be mapped if the key is still valid */
> > >   	if ((bind_flags & DRM_XE_VM_BIND_FLAG_CHECK_PXP) &&
> > xe_bo_is_protected(bo) &&
> > >   	    op != DRM_XE_VM_BIND_OP_UNMAP && op !=
> > > DRM_XE_VM_BIND_OP_UNMAP_ALL) diff --git
> > > a/drivers/gpu/drm/xe/xe_vm_madvise.c
> > > b/drivers/gpu/drm/xe/xe_vm_madvise.c
> > > index 07169586e35f..376c014239ee 100644
> > > --- a/drivers/gpu/drm/xe/xe_vm_madvise.c
> > > +++ b/drivers/gpu/drm/xe/xe_vm_madvise.c
> > > @@ -411,6 +411,7 @@ int xe_vm_madvise_ioctl(struct drm_device *dev,
> > void *data, struct drm_file *fil
> > >   	struct xe_vmas_in_madvise_range madvise_range = {.addr = args-
> > >start,
> > >   							 .range =  args-
> > >range, };
> > >   	struct xe_madvise_details details;
> > > +	u16 pat_index, coh_mode;
> > >   	struct xe_vm *vm;
> > >   	struct drm_exec exec;
> > >   	int err, attr_type;
> > > @@ -447,6 +448,17 @@ int xe_vm_madvise_ioctl(struct drm_device
> *dev,
> > void *data, struct drm_file *fil
> > >   	if (err || !madvise_range.num_vmas)
> > >   		goto madv_fini;
> > >
> > > +	if (args->type == DRM_XE_MEM_RANGE_ATTR_PAT) {
> > > +		pat_index = array_index_nospec(args->pat_index.val, xe-
> > >pat.n_entries);
> > > +		coh_mode = xe_pat_index_get_coh_mode(xe, pat_index);
> > > +		if (XE_IOCTL_DBG(xe, madvise_range.has_svm_userptr_vmas
> > &&
> > > +				 xe_device_is_l2_flush_optimized(xe) &&
> > > +				 (pat_index != 19 && coh_mode !=
> > XE_COH_2WAY))) {
> > > +			err = -EINVAL;
> > > +			goto madv_fini;
> > > +		}
> > > +	}
> > > +
> > >   	if (madvise_range.has_bo_vmas) {
> > >   		if (args->type == DRM_XE_MEM_RANGE_ATTR_ATOMIC) {
> > >   			if (!check_bo_args_are_sane(vm,
> > madvise_range.vmas, @@ -464,6
> > > +476,17 @@ int xe_vm_madvise_ioctl(struct drm_device *dev, void
> > > +*data,
> > > struct drm_file *fil
> > >
> > >   				if (!bo)
> > >   					continue;
> > > +
> > > +				if (args->type ==
> > DRM_XE_MEM_RANGE_ATTR_PAT) {
> > > +					if (XE_IOCTL_DBG(xe, bo-
> > >ttm.base.import_attach &&
> > > +
> > xe_device_is_l2_flush_optimized(xe) &&
> > > +							 (pat_index != 19 &&
> > > +							  coh_mode !=
> > XE_COH_2WAY))) {
> > > +						err = -EINVAL;
> > > +						goto err_fini;
> > > +					}
> > > +				}
> > > +
> > >   				err = drm_exec_lock_obj(&exec, &bo-
> ttm.base);
> > >   				drm_exec_retry_on_contention(&exec);
> > >   				if (err)
> > > diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
> > >index ef2565048bdf..862fed3cf1ed 100644
> > > --- a/include/uapi/drm/xe_drm.h
> > > +++ b/include/uapi/drm/xe_drm.h
> > > @@ -1103,7 +1103,9 @@ struct drm_xe_vm_bind_op {
> > >   	 * incoherent GT access is possible.
> > >   	 *
> > >   	 * Note: For userptr and externally imported dma-buf the kernel
> > expects
> > > -	 * either 1WAY or 2WAY for the @pat_index.
> > > +	 * either 1WAY or 2WAY for the @pat_index. Starting from NVL-P, for
> > > +	 * userptr, svm, madvise and externally imported dma-buf the
> > > +kernel
> > expects
> > > +	 * either 2WAY or 1WAY and XA @pat_index.
> > >   	 *
> > >   	 * For DRM_XE_VM_BIND_FLAG_NULL bindings there are no KMD
> > restrictions
> > >   	 * on the @pat_index. For such mappings there is no actual memory
> > > being

Re: [PATCH V6 3/4] drm/xe/xe3p_lpg: Restrict UAPI to enable L2 flush optimization

[Matthew Auld]

On 06/03/2026 07:11, Zhang, Carl wrote:
> My understanding:
> 1. GuC uses a timer to monitor media activity status. The mode becomes active only when no media tasks have been detected for 5 seconds. From the media perspective, this allows legacy behavior to be maintained without requiring any changes.
> 2. The media UMD only needs to set usage hints to gmmlib, which then manages the PAT index. Therefore, the UMD itself should not require changes—only gmmlib needs to be updated to return PAT index 19 on NVL for imported surfaces.
> My open is:
> 1. In some applications (e.g., ChromeOS), memory is allocated centrally (possibly by minigbm) and then shared across different components. If there are no media tasks, the system operates in persistent mode. However, based on current interfaces, imported memory should be configured as transient + 1-way coherency. This raises a question: if this memory is used exclusively by compute (not media), is this the expected behavior?

2way is also allowed.

> 2. For userptr memory that is used by only one component, I believe 1-way coherency should be sufficient?

I think for 1) and 2), it mostly comes down to CPU/host <-> GPU 
coherency, right? If you don't use 2WAY or XA, userspace would now have 
to manually handle the coherency, in case in "persistent" mode. It 
doesn't matter if there is just one component/app, the coherency issue 
would still be there.

For example, for 2) if you only use 1way without XA, then AFAIK you now 
need manual flushing, if GPU side is cached and CPU is expecting to see 
coherent view. Like say GPU writes something and CPU later reads it. The 
1-way here would just ensure that GPU snoops the CPU caches on the first 
access. But if it then gets cached on GPU side, there is now no 
guaranteed flush when that GPU job is complete, when in "persistent" mode.

So assumption was that for userptr, the memory comes from the host, and 
access is likely shared with CPU/host, so seems reasonable you would 
want XA or 2WAY. For foreign imported memory you are likely sharing with 
host or some other device/driver, so seems reasonable you would probably 
want XA or 2WAY.

We can drop the restrictions, if userspace really needs it, but it would 
be up to userspace to deal with all the CPU/host vs GPU coherency fun, 
if applicable. The restrictions do simplify things a little on the KMD 
side, plus the validation angle in IGT.

> 
> Thanks
> Carl
> 
>> -----Original Message-----
>> From: Auld, Matthew <matthew.auld@intel.com>
>> Sent: Thursday, March 5, 2026 10:00 PM
>> To: Upadhyay, Tejas <tejas.upadhyay@intel.com>; intel-
>> xe@lists.freedesktop.org
>> Cc: thomas.hellstrom@linux.intel.com; Zhang, Carl <carl.zhang@intel.com>;
>> Souza, Jose <jose.souza@intel.com>; Mrozek, Michal
>> <michal.mrozek@intel.com>
>> Subject: Re: [PATCH V6 3/4] drm/xe/xe3p_lpg: Restrict UAPI to enable L2 flush
>> optimization
>>
>> On 05/03/2026 12:19, Tejas Upadhyay wrote:
>>> When set, starting xe3p_lpg, the L2 flush optimization feature will
>>> control whether L2 is in Persistent or Transient mode through
>>> monitoring of media activity.
>>>
>>> To enable L2 flush optimization include new feature flag
>>> GUC_CTL_ENABLE_L2FLUSH_OPT for Novalake platforms when media type
>> is
>>> detected.
>>>
>>> Tighten UAPI validation to restrict userptr, svm and dmabuf mappings
>>> to be either 2WAY or XA+1WAY
>>>
>>> V5(Thomas): logic correction
>>> V4(MattA): Modify uapi doc and commit
>>> V3(MattA): check valid op and pat_index value
>>> V2(MattA): validate dma-buf bos and madvise pat-index
>>>
>>> Acked-by: José Roberto de Souza <jose.souza@intel.com>
>>> Acked-by: Michal Mrozek <michal.mrozek@intel.com>
>>> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
>>> ---
>>>    drivers/gpu/drm/xe/xe_guc.c        |  3 +++
>>>    drivers/gpu/drm/xe/xe_guc_fwif.h   |  1 +
>>>    drivers/gpu/drm/xe/xe_vm.c         |  8 ++++++++
>>>    drivers/gpu/drm/xe/xe_vm_madvise.c | 23 +++++++++++++++++++++++
>>>    include/uapi/drm/xe_drm.h          |  4 +++-
>>>    5 files changed, 38 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
>>> index 54d2fc780127..43dc4353206f 100644
>>> --- a/drivers/gpu/drm/xe/xe_guc.c
>>> +++ b/drivers/gpu/drm/xe/xe_guc.c
>>> @@ -98,6 +98,9 @@ static u32 guc_ctl_feature_flags(struct xe_guc *guc)
>>>    	if (xe_guc_using_main_gamctrl_queues(guc))
>>>    		flags |= GUC_CTL_MAIN_GAMCTRL_QUEUES;
>>>
>>> +	if (GRAPHICS_VER(xe) >= 35 && !IS_DGFX(xe) &&
>> xe_gt_is_media_type(guc_to_gt(guc)))
>>> +		flags |= GUC_CTL_ENABLE_L2FLUSH_OPT;
>>
>> Pending whether we also need this on primary GT or not. Since it sounded
>> like it would also need to know whether to do a targeted or full flush based
>> on current Media status, and it's unclear if here we are meant to opt into that
>> for every GT/GuC instance vs just the Media GuC.
>>
>> Reviewed-by: Matthew Auld <matthew.auld@intel.com>
>>
>>> +
>>>    	return flags;
>>>    }
>>>
>>> diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h
>>> b/drivers/gpu/drm/xe/xe_guc_fwif.h
>>> index bb8f71d38611..b73fae063fac 100644
>>> --- a/drivers/gpu/drm/xe/xe_guc_fwif.h
>>> +++ b/drivers/gpu/drm/xe/xe_guc_fwif.h
>>> @@ -67,6 +67,7 @@ struct guc_update_exec_queue_policy {
>>>    #define   GUC_CTL_ENABLE_PSMI_LOGGING	BIT(7)
>>>    #define   GUC_CTL_MAIN_GAMCTRL_QUEUES	BIT(9)
>>>    #define   GUC_CTL_DISABLE_SCHEDULER	BIT(14)
>>> +#define   GUC_CTL_ENABLE_L2FLUSH_OPT	BIT(15)
>>>
>>>    #define GUC_CTL_DEBUG			3
>>>    #define   GUC_LOG_VERBOSITY		REG_GENMASK(1, 0)
>>> diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
>>> index da0ce0b3704c..0b236e08c158 100644
>>> --- a/drivers/gpu/drm/xe/xe_vm.c
>>> +++ b/drivers/gpu/drm/xe/xe_vm.c
>>> @@ -3481,6 +3481,10 @@ static int vm_bind_ioctl_check_args(struct
>> xe_device *xe, struct xe_vm *vm,
>>>    				 op ==
>> DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
>>>    		    XE_IOCTL_DBG(xe, coh_mode == XE_COH_NONE &&
>>>    				 op ==
>> DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
>>> +		    XE_IOCTL_DBG(xe, xe_device_is_l2_flush_optimized(xe) &&
>>> +				 (op ==
>> DRM_XE_VM_BIND_OP_MAP_USERPTR ||
>>> +				  is_cpu_addr_mirror) &&
>>> +				 (pat_index != 19 && coh_mode !=
>> XE_COH_2WAY)) ||
>>>    		    XE_IOCTL_DBG(xe, comp_en &&
>>>    				 op ==
>> DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
>>>    		    XE_IOCTL_DBG(xe, op ==
>> DRM_XE_VM_BIND_OP_MAP_USERPTR && @@
>>> -3615,6 +3619,10 @@ static int xe_vm_bind_ioctl_validate_bo(struct
>> xe_device *xe, struct xe_bo *bo,
>>>    	if (XE_IOCTL_DBG(xe, bo->ttm.base.import_attach && comp_en))
>>>    		return -EINVAL;
>>>
>>> +	if (XE_IOCTL_DBG(xe, bo->ttm.base.import_attach &&
>> xe_device_is_l2_flush_optimized(xe) &&
>>> +			 (pat_index != 19 && coh_mode != XE_COH_2WAY)))
>>> +		return -EINVAL;
>>> +
>>>    	/* If a BO is protected it can only be mapped if the key is still valid */
>>>    	if ((bind_flags & DRM_XE_VM_BIND_FLAG_CHECK_PXP) &&
>> xe_bo_is_protected(bo) &&
>>>    	    op != DRM_XE_VM_BIND_OP_UNMAP && op !=
>>> DRM_XE_VM_BIND_OP_UNMAP_ALL) diff --git
>>> a/drivers/gpu/drm/xe/xe_vm_madvise.c
>>> b/drivers/gpu/drm/xe/xe_vm_madvise.c
>>> index 07169586e35f..376c014239ee 100644
>>> --- a/drivers/gpu/drm/xe/xe_vm_madvise.c
>>> +++ b/drivers/gpu/drm/xe/xe_vm_madvise.c
>>> @@ -411,6 +411,7 @@ int xe_vm_madvise_ioctl(struct drm_device *dev,
>> void *data, struct drm_file *fil
>>>    	struct xe_vmas_in_madvise_range madvise_range = {.addr = args-
>>> start,
>>>    							 .range =  args-
>>> range, };
>>>    	struct xe_madvise_details details;
>>> +	u16 pat_index, coh_mode;
>>>    	struct xe_vm *vm;
>>>    	struct drm_exec exec;
>>>    	int err, attr_type;
>>> @@ -447,6 +448,17 @@ int xe_vm_madvise_ioctl(struct drm_device *dev,
>> void *data, struct drm_file *fil
>>>    	if (err || !madvise_range.num_vmas)
>>>    		goto madv_fini;
>>>
>>> +	if (args->type == DRM_XE_MEM_RANGE_ATTR_PAT) {
>>> +		pat_index = array_index_nospec(args->pat_index.val, xe-
>>> pat.n_entries);
>>> +		coh_mode = xe_pat_index_get_coh_mode(xe, pat_index);
>>> +		if (XE_IOCTL_DBG(xe, madvise_range.has_svm_userptr_vmas
>> &&
>>> +				 xe_device_is_l2_flush_optimized(xe) &&
>>> +				 (pat_index != 19 && coh_mode !=
>> XE_COH_2WAY))) {
>>> +			err = -EINVAL;
>>> +			goto madv_fini;
>>> +		}
>>> +	}
>>> +
>>>    	if (madvise_range.has_bo_vmas) {
>>>    		if (args->type == DRM_XE_MEM_RANGE_ATTR_ATOMIC) {
>>>    			if (!check_bo_args_are_sane(vm,
>> madvise_range.vmas, @@ -464,6
>>> +476,17 @@ int xe_vm_madvise_ioctl(struct drm_device *dev, void *data,
>>> struct drm_file *fil
>>>
>>>    				if (!bo)
>>>    					continue;
>>> +
>>> +				if (args->type ==
>> DRM_XE_MEM_RANGE_ATTR_PAT) {
>>> +					if (XE_IOCTL_DBG(xe, bo-
>>> ttm.base.import_attach &&
>>> +
>> xe_device_is_l2_flush_optimized(xe) &&
>>> +							 (pat_index != 19 &&
>>> +							  coh_mode !=
>> XE_COH_2WAY))) {
>>> +						err = -EINVAL;
>>> +						goto err_fini;
>>> +					}
>>> +				}
>>> +
>>>    				err = drm_exec_lock_obj(&exec, &bo-
>>> ttm.base);
>>>    				drm_exec_retry_on_contention(&exec);
>>>    				if (err)
>>> diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
>>> index ef2565048bdf..862fed3cf1ed 100644
>>> --- a/include/uapi/drm/xe_drm.h
>>> +++ b/include/uapi/drm/xe_drm.h
>>> @@ -1103,7 +1103,9 @@ struct drm_xe_vm_bind_op {
>>>    	 * incoherent GT access is possible.
>>>    	 *
>>>    	 * Note: For userptr and externally imported dma-buf the kernel
>> expects
>>> -	 * either 1WAY or 2WAY for the @pat_index.
>>> +	 * either 1WAY or 2WAY for the @pat_index. Starting from NVL-P, for
>>> +	 * userptr, svm, madvise and externally imported dma-buf the kernel
>> expects
>>> +	 * either 2WAY or 1WAY and XA @pat_index.
>>>    	 *
>>>    	 * For DRM_XE_VM_BIND_FLAG_NULL bindings there are no KMD
>> restrictions
>>>    	 * on the @pat_index. For such mappings there is no actual memory
>>> being
> 

RE: [PATCH V6 3/4] drm/xe/xe3p_lpg: Restrict UAPI to enable L2 flush optimization

[Zhang, Carl]

> -----Original Message-----
> From: Auld, Matthew <matthew.auld@intel.com>
> Sent: Friday, March 6, 2026 6:09 PM
> To: Zhang, Carl <carl.zhang@intel.com>; Upadhyay, Tejas
> <tejas.upadhyay@intel.com>; intel-xe@lists.freedesktop.org
> Cc: thomas.hellstrom@linux.intel.com; Souza, Jose <jose.souza@intel.com>;
> Mrozek, Michal <michal.mrozek@intel.com>
> Subject: Re: [PATCH V6 3/4] drm/xe/xe3p_lpg: Restrict UAPI to enable L2 flush
> optimization
> 
> On 06/03/2026 07:11, Zhang, Carl wrote:
> > My understanding:
> > 1. GuC uses a timer to monitor media activity status. The mode becomes
> active only when no media tasks have been detected for 5 seconds. From the
> media perspective, this allows legacy behavior to be maintained without
> requiring any changes.
> > 2. The media UMD only needs to set usage hints to gmmlib, which then
> manages the PAT index. Therefore, the UMD itself should not require
> changes—only gmmlib needs to be updated to return PAT index 19 on NVL for
> imported surfaces.
> > My open is:
> > 1. In some applications (e.g., ChromeOS), memory is allocated centrally
> (possibly by minigbm) and then shared across different components. If there
> are no media tasks, the system operates in persistent mode. However, based
> on current interfaces, imported memory should be configured as transient +
> 1-way coherency. This raises a question: if this memory is used exclusively by
> compute (not media), is this the expected behavior?
> 
> 2way is also allowed.
>
 
But 2way is slower than 1 way , right?

> > 2. For userptr memory that is used by only one component, I believe 1-way
> coherency should be sufficient?
> 
> I think for 1) and 2), it mostly comes down to CPU/host <-> GPU coherency,
> right? If you don't use 2WAY or XA, userspace would now have to manually
> handle the coherency, in case in "persistent" mode. It doesn't matter if there
> is just one component/app, the coherency issue would still be there.
> 
For Media (vdbox, vebox), does not use L2 cache,  so, if it is userptr
1-way is enough, just need snoop cpu cache. 

> For example, for 2) if you only use 1way without XA, then AFAIK you now
> need manual flushing, if GPU side is cached and CPU is expecting to see
> coherent view. Like say GPU writes something and CPU later reads it. The 1-
> way here would just ensure that GPU snoops the CPU caches on the first
> access. But if it then gets cached on GPU side, there is now no guaranteed
> flush when that GPU job is complete, when in "persistent" mode.
> 
a. my understanding , L2 is used only for RCS and VCS. Not for VCS and VECS.
Please correct me if there is any misunderstanding.  So, if one external resource
is only used by media . never be used by CCS RCS. whether we should still have
such limitation.

b. if there is media task, seems it cant be "persistent" mode. Of course, maybe,
it is "persistent" mode, then media task comes, it turns to "transient" mode.
But the data is still in cache , not flushed.  for this case, I agree that any resource 
used firstly by CCS or RCS then shared it to media, it should be set to 2-way or
1-way + XA. 

> So assumption was that for userptr, the memory comes from the host, and
> access is likely shared with CPU/host, so seems reasonable you would want
> XA or 2WAY. For foreign imported memory you are likely sharing with host or
> some other device/driver, so seems reasonable you would probably want XA
> or 2WAY.
> 
> We can drop the restrictions, if userspace really needs it, but it would be up to
> userspace to deal with all the CPU/host vs GPU coherency fun, if applicable.
> The restrictions do simplify things a little on the KMD side, plus the validation
> angle in IGT.
> 
I am thinking whether it is too strict.  There is different useagecases.

> >
> > Thanks
> > Carl
> >
> >> -----Original Message-----
> >> From: Auld, Matthew <matthew.auld@intel.com>
> >> Sent: Thursday, March 5, 2026 10:00 PM
> >> To: Upadhyay, Tejas <tejas.upadhyay@intel.com>; intel-
> >> xe@lists.freedesktop.org
> >> Cc: thomas.hellstrom@linux.intel.com; Zhang, Carl
> <carl.zhang@intel.com>;
> >> Souza, Jose <jose.souza@intel.com>; Mrozek, Michal
> >> <michal.mrozek@intel.com>
> >> Subject: Re: [PATCH V6 3/4] drm/xe/xe3p_lpg: Restrict UAPI to enable L2
> flush
> >> optimization
> >>
> >> On 05/03/2026 12:19, Tejas Upadhyay wrote:
> >>> When set, starting xe3p_lpg, the L2 flush optimization feature will
> >>> control whether L2 is in Persistent or Transient mode through
> >>> monitoring of media activity.
> >>>
> >>> To enable L2 flush optimization include new feature flag
> >>> GUC_CTL_ENABLE_L2FLUSH_OPT for Novalake platforms when media
> type
> >> is
> >>> detected.
> >>>
> >>> Tighten UAPI validation to restrict userptr, svm and dmabuf mappings
> >>> to be either 2WAY or XA+1WAY
> >>>
> >>> V5(Thomas): logic correction
> >>> V4(MattA): Modify uapi doc and commit
> >>> V3(MattA): check valid op and pat_index value
> >>> V2(MattA): validate dma-buf bos and madvise pat-index
> >>>
> >>> Acked-by: José Roberto de Souza <jose.souza@intel.com>
> >>> Acked-by: Michal Mrozek <michal.mrozek@intel.com>
> >>> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
> >>> ---
> >>>    drivers/gpu/drm/xe/xe_guc.c        |  3 +++
> >>>    drivers/gpu/drm/xe/xe_guc_fwif.h   |  1 +
> >>>    drivers/gpu/drm/xe/xe_vm.c         |  8 ++++++++
> >>>    drivers/gpu/drm/xe/xe_vm_madvise.c | 23 +++++++++++++++++++++++
> >>>    include/uapi/drm/xe_drm.h          |  4 +++-
> >>>    5 files changed, 38 insertions(+), 1 deletion(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
> >>> index 54d2fc780127..43dc4353206f 100644
> >>> --- a/drivers/gpu/drm/xe/xe_guc.c
> >>> +++ b/drivers/gpu/drm/xe/xe_guc.c
> >>> @@ -98,6 +98,9 @@ static u32 guc_ctl_feature_flags(struct xe_guc *guc)
> >>>    	if (xe_guc_using_main_gamctrl_queues(guc))
> >>>    		flags |= GUC_CTL_MAIN_GAMCTRL_QUEUES;
> >>>
> >>> +	if (GRAPHICS_VER(xe) >= 35 && !IS_DGFX(xe) &&
> >> xe_gt_is_media_type(guc_to_gt(guc)))
> >>> +		flags |= GUC_CTL_ENABLE_L2FLUSH_OPT;
> >>
> >> Pending whether we also need this on primary GT or not. Since it sounded
> >> like it would also need to know whether to do a targeted or full flush
> based
> >> on current Media status, and it's unclear if here we are meant to opt into
> that
> >> for every GT/GuC instance vs just the Media GuC.
> >>
> >> Reviewed-by: Matthew Auld <matthew.auld@intel.com>
> >>
> >>> +
> >>>    	return flags;
> >>>    }
> >>>
> >>> diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h
> >>> b/drivers/gpu/drm/xe/xe_guc_fwif.h
> >>> index bb8f71d38611..b73fae063fac 100644
> >>> --- a/drivers/gpu/drm/xe/xe_guc_fwif.h
> >>> +++ b/drivers/gpu/drm/xe/xe_guc_fwif.h
> >>> @@ -67,6 +67,7 @@ struct guc_update_exec_queue_policy {
> >>>    #define   GUC_CTL_ENABLE_PSMI_LOGGING	BIT(7)
> >>>    #define   GUC_CTL_MAIN_GAMCTRL_QUEUES	BIT(9)
> >>>    #define   GUC_CTL_DISABLE_SCHEDULER	BIT(14)
> >>> +#define   GUC_CTL_ENABLE_L2FLUSH_OPT	BIT(15)
> >>>
> >>>    #define GUC_CTL_DEBUG			3
> >>>    #define   GUC_LOG_VERBOSITY		REG_GENMASK(1, 0)
> >>> diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
> >>> index da0ce0b3704c..0b236e08c158 100644
> >>> --- a/drivers/gpu/drm/xe/xe_vm.c
> >>> +++ b/drivers/gpu/drm/xe/xe_vm.c
> >>> @@ -3481,6 +3481,10 @@ static int vm_bind_ioctl_check_args(struct
> >> xe_device *xe, struct xe_vm *vm,
> >>>    				 op ==
> >> DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
> >>>    		    XE_IOCTL_DBG(xe, coh_mode == XE_COH_NONE &&
> >>>    				 op ==
> >> DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
> >>> +		    XE_IOCTL_DBG(xe, xe_device_is_l2_flush_optimized(xe) &&
> >>> +				 (op ==
> >> DRM_XE_VM_BIND_OP_MAP_USERPTR ||
> >>> +				  is_cpu_addr_mirror) &&
> >>> +				 (pat_index != 19 && coh_mode !=
> >> XE_COH_2WAY)) ||
> >>>    		    XE_IOCTL_DBG(xe, comp_en &&
> >>>    				 op ==
> >> DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
> >>>    		    XE_IOCTL_DBG(xe, op ==
> >> DRM_XE_VM_BIND_OP_MAP_USERPTR && @@
> >>> -3615,6 +3619,10 @@ static int xe_vm_bind_ioctl_validate_bo(struct
> >> xe_device *xe, struct xe_bo *bo,
> >>>    	if (XE_IOCTL_DBG(xe, bo->ttm.base.import_attach && comp_en))
> >>>    		return -EINVAL;
> >>>
> >>> +	if (XE_IOCTL_DBG(xe, bo->ttm.base.import_attach &&
> >> xe_device_is_l2_flush_optimized(xe) &&
> >>> +			 (pat_index != 19 && coh_mode != XE_COH_2WAY)))
> >>> +		return -EINVAL;
> >>> +
> >>>    	/* If a BO is protected it can only be mapped if the key is still valid */
> >>>    	if ((bind_flags & DRM_XE_VM_BIND_FLAG_CHECK_PXP) &&
> >> xe_bo_is_protected(bo) &&
> >>>    	    op != DRM_XE_VM_BIND_OP_UNMAP && op !=
> >>> DRM_XE_VM_BIND_OP_UNMAP_ALL) diff --git
> >>> a/drivers/gpu/drm/xe/xe_vm_madvise.c
> >>> b/drivers/gpu/drm/xe/xe_vm_madvise.c
> >>> index 07169586e35f..376c014239ee 100644
> >>> --- a/drivers/gpu/drm/xe/xe_vm_madvise.c
> >>> +++ b/drivers/gpu/drm/xe/xe_vm_madvise.c
> >>> @@ -411,6 +411,7 @@ int xe_vm_madvise_ioctl(struct drm_device *dev,
> >> void *data, struct drm_file *fil
> >>>    	struct xe_vmas_in_madvise_range madvise_range = {.addr = args-
> >>> start,
> >>>    							 .range =  args-
> >>> range, };
> >>>    	struct xe_madvise_details details;
> >>> +	u16 pat_index, coh_mode;
> >>>    	struct xe_vm *vm;
> >>>    	struct drm_exec exec;
> >>>    	int err, attr_type;
> >>> @@ -447,6 +448,17 @@ int xe_vm_madvise_ioctl(struct drm_device
> *dev,
> >> void *data, struct drm_file *fil
> >>>    	if (err || !madvise_range.num_vmas)
> >>>    		goto madv_fini;
> >>>
> >>> +	if (args->type == DRM_XE_MEM_RANGE_ATTR_PAT) {
> >>> +		pat_index = array_index_nospec(args->pat_index.val, xe-
> >>> pat.n_entries);
> >>> +		coh_mode = xe_pat_index_get_coh_mode(xe, pat_index);
> >>> +		if (XE_IOCTL_DBG(xe, madvise_range.has_svm_userptr_vmas
> >> &&
> >>> +				 xe_device_is_l2_flush_optimized(xe) &&
> >>> +				 (pat_index != 19 && coh_mode !=
> >> XE_COH_2WAY))) {
> >>> +			err = -EINVAL;
> >>> +			goto madv_fini;
> >>> +		}
> >>> +	}
> >>> +
> >>>    	if (madvise_range.has_bo_vmas) {
> >>>    		if (args->type == DRM_XE_MEM_RANGE_ATTR_ATOMIC) {
> >>>    			if (!check_bo_args_are_sane(vm,
> >> madvise_range.vmas, @@ -464,6
> >>> +476,17 @@ int xe_vm_madvise_ioctl(struct drm_device *dev, void
> *data,
> >>> struct drm_file *fil
> >>>
> >>>    				if (!bo)
> >>>    					continue;
> >>> +
> >>> +				if (args->type ==
> >> DRM_XE_MEM_RANGE_ATTR_PAT) {
> >>> +					if (XE_IOCTL_DBG(xe, bo-
> >>> ttm.base.import_attach &&
> >>> +
> >> xe_device_is_l2_flush_optimized(xe) &&
> >>> +							 (pat_index != 19 &&
> >>> +							  coh_mode !=
> >> XE_COH_2WAY))) {
> >>> +						err = -EINVAL;
> >>> +						goto err_fini;
> >>> +					}
> >>> +				}
> >>> +
> >>>    				err = drm_exec_lock_obj(&exec, &bo-
> >>> ttm.base);
> >>>    				drm_exec_retry_on_contention(&exec);
> >>>    				if (err)
> >>> diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
> >>> index ef2565048bdf..862fed3cf1ed 100644
> >>> --- a/include/uapi/drm/xe_drm.h
> >>> +++ b/include/uapi/drm/xe_drm.h
> >>> @@ -1103,7 +1103,9 @@ struct drm_xe_vm_bind_op {
> >>>    	 * incoherent GT access is possible.
> >>>    	 *
> >>>    	 * Note: For userptr and externally imported dma-buf the kernel
> >> expects
> >>> -	 * either 1WAY or 2WAY for the @pat_index.
> >>> +	 * either 1WAY or 2WAY for the @pat_index. Starting from NVL-P, for
> >>> +	 * userptr, svm, madvise and externally imported dma-buf the kernel
> >> expects
> >>> +	 * either 2WAY or 1WAY and XA @pat_index.
> >>>    	 *
> >>>    	 * For DRM_XE_VM_BIND_FLAG_NULL bindings there are no KMD
> >> restrictions
> >>>    	 * on the @pat_index. For such mappings there is no actual memory
> >>> being
> >

Re: [PATCH V6 3/4] drm/xe/xe3p_lpg: Restrict UAPI to enable L2 flush optimization

[Matthew Auld]

On 09/03/2026 15:29, Zhang, Carl wrote:
> 
> 
>> -----Original Message-----
>> From: Auld, Matthew <matthew.auld@intel.com>
>> Sent: Friday, March 6, 2026 6:09 PM
>> To: Zhang, Carl <carl.zhang@intel.com>; Upadhyay, Tejas
>> <tejas.upadhyay@intel.com>; intel-xe@lists.freedesktop.org
>> Cc: thomas.hellstrom@linux.intel.com; Souza, Jose <jose.souza@intel.com>;
>> Mrozek, Michal <michal.mrozek@intel.com>
>> Subject: Re: [PATCH V6 3/4] drm/xe/xe3p_lpg: Restrict UAPI to enable L2 flush
>> optimization
>>
>> On 06/03/2026 07:11, Zhang, Carl wrote:
>>> My understanding:
>>> 1. GuC uses a timer to monitor media activity status. The mode becomes
>> active only when no media tasks have been detected for 5 seconds. From the
>> media perspective, this allows legacy behavior to be maintained without
>> requiring any changes.
>>> 2. The media UMD only needs to set usage hints to gmmlib, which then
>> manages the PAT index. Therefore, the UMD itself should not require
>> changes—only gmmlib needs to be updated to return PAT index 19 on NVL for
>> imported surfaces.
>>> My open is:
>>> 1. In some applications (e.g., ChromeOS), memory is allocated centrally
>> (possibly by minigbm) and then shared across different components. If there
>> are no media tasks, the system operates in persistent mode. However, based
>> on current interfaces, imported memory should be configured as transient +
>> 1-way coherency. This raises a question: if this memory is used exclusively by
>> compute (not media), is this the expected behavior?
>>
>> 2way is also allowed.
>>
>   
> But 2way is slower than 1 way , right?

Likely it would be, I think. But for Media only, not sure.

> 
>>> 2. For userptr memory that is used by only one component, I believe 1-way
>> coherency should be sufficient?
>>
>> I think for 1) and 2), it mostly comes down to CPU/host <-> GPU coherency,
>> right? If you don't use 2WAY or XA, userspace would now have to manually
>> handle the coherency, in case in "persistent" mode. It doesn't matter if there
>> is just one component/app, the coherency issue would still be there.
>>
> For Media (vdbox, vebox), does not use L2 cache,  so, if it is userptr
> 1-way is enough, just need snoop cpu cache.
> 
>> For example, for 2) if you only use 1way without XA, then AFAIK you now
>> need manual flushing, if GPU side is cached and CPU is expecting to see
>> coherent view. Like say GPU writes something and CPU later reads it. The 1-
>> way here would just ensure that GPU snoops the CPU caches on the first
>> access. But if it then gets cached on GPU side, there is now no guaranteed
>> flush when that GPU job is complete, when in "persistent" mode.
>>
> a. my understanding , L2 is used only for RCS and VCS. Not for VCS and VECS.
> Please correct me if there is any misunderstanding.  So, if one external resource
> is only used by media . never be used by CCS RCS. whether we should still have
> such limitation.

Yeah, that matches my understanding. It sounded like Media access does 
not go via l2, so I assume goes directly to system memory. Hence why l2 
needs to be fully flushed if sharing something with Media (which is 
assumed whenever Media is currently turned on).

> 
> b. if there is media task, seems it cant be "persistent" mode. Of course, maybe,
> it is "persistent" mode, then media task comes, it turns to "transient" mode.
> But the data is still in cache , not flushed.  for this case, I agree that any resource
> used firstly by CCS or RCS then shared it to media, it should be set to 2-way or
> 1-way + XA.
> 
>> So assumption was that for userptr, the memory comes from the host, and
>> access is likely shared with CPU/host, so seems reasonable you would want
>> XA or 2WAY. For foreign imported memory you are likely sharing with host or
>> some other device/driver, so seems reasonable you would probably want XA
>> or 2WAY.
>>
>> We can drop the restrictions, if userspace really needs it, but it would be up to
>> userspace to deal with all the CPU/host vs GPU coherency fun, if applicable.
>> The restrictions do simplify things a little on the KMD side, plus the validation
>> angle in IGT.
>>
> I am thinking whether it is too strict.  There is different useagecases.

Do you know which index(s) you would pick instead, for Media only cases? 
I think that is the only edge case you are concerned with here?

Is it not the case that if you are only submitting within Media and it 
if it doesn't actually use l2, wouldn't the XA and l2 cache mode stuff 
be a no-op anyway, since the access from Media side never goes through l2?

Do you know which index that we don't allow, would give 
different/preferred behaviour for Media only case?

> 
>>>
>>> Thanks
>>> Carl
>>>
>>>> -----Original Message-----
>>>> From: Auld, Matthew <matthew.auld@intel.com>
>>>> Sent: Thursday, March 5, 2026 10:00 PM
>>>> To: Upadhyay, Tejas <tejas.upadhyay@intel.com>; intel-
>>>> xe@lists.freedesktop.org
>>>> Cc: thomas.hellstrom@linux.intel.com; Zhang, Carl
>> <carl.zhang@intel.com>;
>>>> Souza, Jose <jose.souza@intel.com>; Mrozek, Michal
>>>> <michal.mrozek@intel.com>
>>>> Subject: Re: [PATCH V6 3/4] drm/xe/xe3p_lpg: Restrict UAPI to enable L2
>> flush
>>>> optimization
>>>>
>>>> On 05/03/2026 12:19, Tejas Upadhyay wrote:
>>>>> When set, starting xe3p_lpg, the L2 flush optimization feature will
>>>>> control whether L2 is in Persistent or Transient mode through
>>>>> monitoring of media activity.
>>>>>
>>>>> To enable L2 flush optimization include new feature flag
>>>>> GUC_CTL_ENABLE_L2FLUSH_OPT for Novalake platforms when media
>> type
>>>> is
>>>>> detected.
>>>>>
>>>>> Tighten UAPI validation to restrict userptr, svm and dmabuf mappings
>>>>> to be either 2WAY or XA+1WAY
>>>>>
>>>>> V5(Thomas): logic correction
>>>>> V4(MattA): Modify uapi doc and commit
>>>>> V3(MattA): check valid op and pat_index value
>>>>> V2(MattA): validate dma-buf bos and madvise pat-index
>>>>>
>>>>> Acked-by: José Roberto de Souza <jose.souza@intel.com>
>>>>> Acked-by: Michal Mrozek <michal.mrozek@intel.com>
>>>>> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
>>>>> ---
>>>>>     drivers/gpu/drm/xe/xe_guc.c        |  3 +++
>>>>>     drivers/gpu/drm/xe/xe_guc_fwif.h   |  1 +
>>>>>     drivers/gpu/drm/xe/xe_vm.c         |  8 ++++++++
>>>>>     drivers/gpu/drm/xe/xe_vm_madvise.c | 23 +++++++++++++++++++++++
>>>>>     include/uapi/drm/xe_drm.h          |  4 +++-
>>>>>     5 files changed, 38 insertions(+), 1 deletion(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
>>>>> index 54d2fc780127..43dc4353206f 100644
>>>>> --- a/drivers/gpu/drm/xe/xe_guc.c
>>>>> +++ b/drivers/gpu/drm/xe/xe_guc.c
>>>>> @@ -98,6 +98,9 @@ static u32 guc_ctl_feature_flags(struct xe_guc *guc)
>>>>>     	if (xe_guc_using_main_gamctrl_queues(guc))
>>>>>     		flags |= GUC_CTL_MAIN_GAMCTRL_QUEUES;
>>>>>
>>>>> +	if (GRAPHICS_VER(xe) >= 35 && !IS_DGFX(xe) &&
>>>> xe_gt_is_media_type(guc_to_gt(guc)))
>>>>> +		flags |= GUC_CTL_ENABLE_L2FLUSH_OPT;
>>>>
>>>> Pending whether we also need this on primary GT or not. Since it sounded
>>>> like it would also need to know whether to do a targeted or full flush
>> based
>>>> on current Media status, and it's unclear if here we are meant to opt into
>> that
>>>> for every GT/GuC instance vs just the Media GuC.
>>>>
>>>> Reviewed-by: Matthew Auld <matthew.auld@intel.com>
>>>>
>>>>> +
>>>>>     	return flags;
>>>>>     }
>>>>>
>>>>> diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h
>>>>> b/drivers/gpu/drm/xe/xe_guc_fwif.h
>>>>> index bb8f71d38611..b73fae063fac 100644
>>>>> --- a/drivers/gpu/drm/xe/xe_guc_fwif.h
>>>>> +++ b/drivers/gpu/drm/xe/xe_guc_fwif.h
>>>>> @@ -67,6 +67,7 @@ struct guc_update_exec_queue_policy {
>>>>>     #define   GUC_CTL_ENABLE_PSMI_LOGGING	BIT(7)
>>>>>     #define   GUC_CTL_MAIN_GAMCTRL_QUEUES	BIT(9)
>>>>>     #define   GUC_CTL_DISABLE_SCHEDULER	BIT(14)
>>>>> +#define   GUC_CTL_ENABLE_L2FLUSH_OPT	BIT(15)
>>>>>
>>>>>     #define GUC_CTL_DEBUG			3
>>>>>     #define   GUC_LOG_VERBOSITY		REG_GENMASK(1, 0)
>>>>> diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
>>>>> index da0ce0b3704c..0b236e08c158 100644
>>>>> --- a/drivers/gpu/drm/xe/xe_vm.c
>>>>> +++ b/drivers/gpu/drm/xe/xe_vm.c
>>>>> @@ -3481,6 +3481,10 @@ static int vm_bind_ioctl_check_args(struct
>>>> xe_device *xe, struct xe_vm *vm,
>>>>>     				 op ==
>>>> DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
>>>>>     		    XE_IOCTL_DBG(xe, coh_mode == XE_COH_NONE &&
>>>>>     				 op ==
>>>> DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
>>>>> +		    XE_IOCTL_DBG(xe, xe_device_is_l2_flush_optimized(xe) &&
>>>>> +				 (op ==
>>>> DRM_XE_VM_BIND_OP_MAP_USERPTR ||
>>>>> +				  is_cpu_addr_mirror) &&
>>>>> +				 (pat_index != 19 && coh_mode !=
>>>> XE_COH_2WAY)) ||
>>>>>     		    XE_IOCTL_DBG(xe, comp_en &&
>>>>>     				 op ==
>>>> DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
>>>>>     		    XE_IOCTL_DBG(xe, op ==
>>>> DRM_XE_VM_BIND_OP_MAP_USERPTR && @@
>>>>> -3615,6 +3619,10 @@ static int xe_vm_bind_ioctl_validate_bo(struct
>>>> xe_device *xe, struct xe_bo *bo,
>>>>>     	if (XE_IOCTL_DBG(xe, bo->ttm.base.import_attach && comp_en))
>>>>>     		return -EINVAL;
>>>>>
>>>>> +	if (XE_IOCTL_DBG(xe, bo->ttm.base.import_attach &&
>>>> xe_device_is_l2_flush_optimized(xe) &&
>>>>> +			 (pat_index != 19 && coh_mode != XE_COH_2WAY)))
>>>>> +		return -EINVAL;
>>>>> +
>>>>>     	/* If a BO is protected it can only be mapped if the key is still valid */
>>>>>     	if ((bind_flags & DRM_XE_VM_BIND_FLAG_CHECK_PXP) &&
>>>> xe_bo_is_protected(bo) &&
>>>>>     	    op != DRM_XE_VM_BIND_OP_UNMAP && op !=
>>>>> DRM_XE_VM_BIND_OP_UNMAP_ALL) diff --git
>>>>> a/drivers/gpu/drm/xe/xe_vm_madvise.c
>>>>> b/drivers/gpu/drm/xe/xe_vm_madvise.c
>>>>> index 07169586e35f..376c014239ee 100644
>>>>> --- a/drivers/gpu/drm/xe/xe_vm_madvise.c
>>>>> +++ b/drivers/gpu/drm/xe/xe_vm_madvise.c
>>>>> @@ -411,6 +411,7 @@ int xe_vm_madvise_ioctl(struct drm_device *dev,
>>>> void *data, struct drm_file *fil
>>>>>     	struct xe_vmas_in_madvise_range madvise_range = {.addr = args-
>>>>> start,
>>>>>     							 .range =  args-
>>>>> range, };
>>>>>     	struct xe_madvise_details details;
>>>>> +	u16 pat_index, coh_mode;
>>>>>     	struct xe_vm *vm;
>>>>>     	struct drm_exec exec;
>>>>>     	int err, attr_type;
>>>>> @@ -447,6 +448,17 @@ int xe_vm_madvise_ioctl(struct drm_device
>> *dev,
>>>> void *data, struct drm_file *fil
>>>>>     	if (err || !madvise_range.num_vmas)
>>>>>     		goto madv_fini;
>>>>>
>>>>> +	if (args->type == DRM_XE_MEM_RANGE_ATTR_PAT) {
>>>>> +		pat_index = array_index_nospec(args->pat_index.val, xe-
>>>>> pat.n_entries);
>>>>> +		coh_mode = xe_pat_index_get_coh_mode(xe, pat_index);
>>>>> +		if (XE_IOCTL_DBG(xe, madvise_range.has_svm_userptr_vmas
>>>> &&
>>>>> +				 xe_device_is_l2_flush_optimized(xe) &&
>>>>> +				 (pat_index != 19 && coh_mode !=
>>>> XE_COH_2WAY))) {
>>>>> +			err = -EINVAL;
>>>>> +			goto madv_fini;
>>>>> +		}
>>>>> +	}
>>>>> +
>>>>>     	if (madvise_range.has_bo_vmas) {
>>>>>     		if (args->type == DRM_XE_MEM_RANGE_ATTR_ATOMIC) {
>>>>>     			if (!check_bo_args_are_sane(vm,
>>>> madvise_range.vmas, @@ -464,6
>>>>> +476,17 @@ int xe_vm_madvise_ioctl(struct drm_device *dev, void
>> *data,
>>>>> struct drm_file *fil
>>>>>
>>>>>     				if (!bo)
>>>>>     					continue;
>>>>> +
>>>>> +				if (args->type ==
>>>> DRM_XE_MEM_RANGE_ATTR_PAT) {
>>>>> +					if (XE_IOCTL_DBG(xe, bo-
>>>>> ttm.base.import_attach &&
>>>>> +
>>>> xe_device_is_l2_flush_optimized(xe) &&
>>>>> +							 (pat_index != 19 &&
>>>>> +							  coh_mode !=
>>>> XE_COH_2WAY))) {
>>>>> +						err = -EINVAL;
>>>>> +						goto err_fini;
>>>>> +					}
>>>>> +				}
>>>>> +
>>>>>     				err = drm_exec_lock_obj(&exec, &bo-
>>>>> ttm.base);
>>>>>     				drm_exec_retry_on_contention(&exec);
>>>>>     				if (err)
>>>>> diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
>>>>> index ef2565048bdf..862fed3cf1ed 100644
>>>>> --- a/include/uapi/drm/xe_drm.h
>>>>> +++ b/include/uapi/drm/xe_drm.h
>>>>> @@ -1103,7 +1103,9 @@ struct drm_xe_vm_bind_op {
>>>>>     	 * incoherent GT access is possible.
>>>>>     	 *
>>>>>     	 * Note: For userptr and externally imported dma-buf the kernel
>>>> expects
>>>>> -	 * either 1WAY or 2WAY for the @pat_index.
>>>>> +	 * either 1WAY or 2WAY for the @pat_index. Starting from NVL-P, for
>>>>> +	 * userptr, svm, madvise and externally imported dma-buf the kernel
>>>> expects
>>>>> +	 * either 2WAY or 1WAY and XA @pat_index.
>>>>>     	 *
>>>>>     	 * For DRM_XE_VM_BIND_FLAG_NULL bindings there are no KMD
>>>> restrictions
>>>>>     	 * on the @pat_index. For such mappings there is no actual memory
>>>>> being
>>>
> 

Re: [PATCH V6 3/4] drm/xe/xe3p_lpg: Restrict UAPI to enable L2 flush optimization

[Thomas Hellström]

On Mon, 2026-03-09 at 17:22 +0000, Matthew Auld wrote:
> On 09/03/2026 15:29, Zhang, Carl wrote:
> > 
> > 
> > > -----Original Message-----
> > > From: Auld, Matthew <matthew.auld@intel.com>
> > > Sent: Friday, March 6, 2026 6:09 PM
> > > To: Zhang, Carl <carl.zhang@intel.com>; Upadhyay, Tejas
> > > <tejas.upadhyay@intel.com>; intel-xe@lists.freedesktop.org
> > > Cc: thomas.hellstrom@linux.intel.com; Souza, Jose
> > > <jose.souza@intel.com>;
> > > Mrozek, Michal <michal.mrozek@intel.com>
> > > Subject: Re: [PATCH V6 3/4] drm/xe/xe3p_lpg: Restrict UAPI to
> > > enable L2 flush
> > > optimization
> > > 
> > > On 06/03/2026 07:11, Zhang, Carl wrote:
> > > > My understanding:
> > > > 1. GuC uses a timer to monitor media activity status. The mode
> > > > becomes
> > > active only when no media tasks have been detected for 5 seconds.
> > > From the
> > > media perspective, this allows legacy behavior to be maintained
> > > without
> > > requiring any changes.
> > > > 2. The media UMD only needs to set usage hints to gmmlib, which
> > > > then
> > > manages the PAT index. Therefore, the UMD itself should not
> > > require
> > > changes—only gmmlib needs to be updated to return PAT index 19 on
> > > NVL for
> > > imported surfaces.
> > > > My open is:
> > > > 1. In some applications (e.g., ChromeOS), memory is allocated
> > > > centrally
> > > (possibly by minigbm) and then shared across different
> > > components. If there
> > > are no media tasks, the system operates in persistent mode.
> > > However, based
> > > on current interfaces, imported memory should be configured as
> > > transient +
> > > 1-way coherency. This raises a question: if this memory is used
> > > exclusively by
> > > compute (not media), is this the expected behavior?
> > > 
> > > 2way is also allowed.
> > > 
> >   
> > But 2way is slower than 1 way , right?
> 
> Likely it would be, I think. But for Media only, not sure.
> 
> > 
> > > > 2. For userptr memory that is used by only one component, I
> > > > believe 1-way
> > > coherency should be sufficient?
> > > 
> > > I think for 1) and 2), it mostly comes down to CPU/host <-> GPU
> > > coherency,
> > > right? If you don't use 2WAY or XA, userspace would now have to
> > > manually
> > > handle the coherency, in case in "persistent" mode. It doesn't
> > > matter if there
> > > is just one component/app, the coherency issue would still be
> > > there.
> > > 
> > For Media (vdbox, vebox), does not use L2 cache,  so, if it is
> > userptr
> > 1-way is enough, just need snoop cpu cache.
> > 
> > > For example, for 2) if you only use 1way without XA, then AFAIK
> > > you now
> > > need manual flushing, if GPU side is cached and CPU is expecting
> > > to see
> > > coherent view. Like say GPU writes something and CPU later reads
> > > it. The 1-
> > > way here would just ensure that GPU snoops the CPU caches on the
> > > first
> > > access. But if it then gets cached on GPU side, there is now no
> > > guaranteed
> > > flush when that GPU job is complete, when in "persistent" mode.
> > > 
> > a. my understanding , L2 is used only for RCS and VCS. Not for VCS
> > and VECS.
> > Please correct me if there is any misunderstanding.  So, if one
> > external resource
> > is only used by media . never be used by CCS RCS. whether we should
> > still have
> > such limitation.
> 
> Yeah, that matches my understanding. It sounded like Media access
> does 
> not go via l2, so I assume goes directly to system memory. Hence why
> l2 
> needs to be fully flushed if sharing something with Media (which is 
> assumed whenever Media is currently turned on).
> 
> > 
> > b. if there is media task, seems it cant be "persistent" mode. Of
> > course, maybe,
> > it is "persistent" mode, then media task comes, it turns to
> > "transient" mode.
> > But the data is still in cache , not flushed.  for this case, I
> > agree that any resource
> > used firstly by CCS or RCS then shared it to media, it should be
> > set to 2-way or
> > 1-way + XA.
> > 
> > > So assumption was that for userptr, the memory comes from the
> > > host, and
> > > access is likely shared with CPU/host, so seems reasonable you
> > > would want
> > > XA or 2WAY. For foreign imported memory you are likely sharing
> > > with host or
> > > some other device/driver, so seems reasonable you would probably
> > > want XA
> > > or 2WAY.
> > > 
> > > We can drop the restrictions, if userspace really needs it, but
> > > it would be up to
> > > userspace to deal with all the CPU/host vs GPU coherency fun, if
> > > applicable.
> > > The restrictions do simplify things a little on the KMD side,
> > > plus the validation
> > > angle in IGT.
> > > 
> > I am thinking whether it is too strict.  There is different
> > useagecases.
> 
> Do you know which index(s) you would pick instead, for Media only
> cases? 
> I think that is the only edge case you are concerned with here?
> 
> Is it not the case that if you are only submitting within Media and
> it 
> if it doesn't actually use l2, wouldn't the XA and l2 cache mode
> stuff 
> be a no-op anyway, since the access from Media side never goes
> through l2?

I was wondering whether that could actually be the case as well.

/Thomas


> 
> Do you know which index that we don't allow, would give 
> different/preferred behaviour for Media only case?
> 
> > 
> > > > 
> > > > Thanks
> > > > Carl
> > > > 
> > > > > -----Original Message-----
> > > > > From: Auld, Matthew <matthew.auld@intel.com>
> > > > > Sent: Thursday, March 5, 2026 10:00 PM
> > > > > To: Upadhyay, Tejas <tejas.upadhyay@intel.com>; intel-
> > > > > xe@lists.freedesktop.org
> > > > > Cc: thomas.hellstrom@linux.intel.com; Zhang, Carl
> > > <carl.zhang@intel.com>;
> > > > > Souza, Jose <jose.souza@intel.com>; Mrozek, Michal
> > > > > <michal.mrozek@intel.com>
> > > > > Subject: Re: [PATCH V6 3/4] drm/xe/xe3p_lpg: Restrict UAPI to
> > > > > enable L2
> > > flush
> > > > > optimization
> > > > > 
> > > > > On 05/03/2026 12:19, Tejas Upadhyay wrote:
> > > > > > When set, starting xe3p_lpg, the L2 flush optimization
> > > > > > feature will
> > > > > > control whether L2 is in Persistent or Transient mode
> > > > > > through
> > > > > > monitoring of media activity.
> > > > > > 
> > > > > > To enable L2 flush optimization include new feature flag
> > > > > > GUC_CTL_ENABLE_L2FLUSH_OPT for Novalake platforms when
> > > > > > media
> > > type
> > > > > is
> > > > > > detected.
> > > > > > 
> > > > > > Tighten UAPI validation to restrict userptr, svm and dmabuf
> > > > > > mappings
> > > > > > to be either 2WAY or XA+1WAY
> > > > > > 
> > > > > > V5(Thomas): logic correction
> > > > > > V4(MattA): Modify uapi doc and commit
> > > > > > V3(MattA): check valid op and pat_index value
> > > > > > V2(MattA): validate dma-buf bos and madvise pat-index
> > > > > > 
> > > > > > Acked-by: José Roberto de Souza <jose.souza@intel.com>
> > > > > > Acked-by: Michal Mrozek <michal.mrozek@intel.com>
> > > > > > Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
> > > > > > ---
> > > > > >     drivers/gpu/drm/xe/xe_guc.c        |  3 +++
> > > > > >     drivers/gpu/drm/xe/xe_guc_fwif.h   |  1 +
> > > > > >     drivers/gpu/drm/xe/xe_vm.c         |  8 ++++++++
> > > > > >     drivers/gpu/drm/xe/xe_vm_madvise.c | 23
> > > > > > +++++++++++++++++++++++
> > > > > >     include/uapi/drm/xe_drm.h          |  4 +++-
> > > > > >     5 files changed, 38 insertions(+), 1 deletion(-)
> > > > > > 
> > > > > > diff --git a/drivers/gpu/drm/xe/xe_guc.c
> > > > > > b/drivers/gpu/drm/xe/xe_guc.c
> > > > > > index 54d2fc780127..43dc4353206f 100644
> > > > > > --- a/drivers/gpu/drm/xe/xe_guc.c
> > > > > > +++ b/drivers/gpu/drm/xe/xe_guc.c
> > > > > > @@ -98,6 +98,9 @@ static u32 guc_ctl_feature_flags(struct
> > > > > > xe_guc *guc)
> > > > > >     	if (xe_guc_using_main_gamctrl_queues(guc))
> > > > > >     		flags |= GUC_CTL_MAIN_GAMCTRL_QUEUES;
> > > > > > 
> > > > > > +	if (GRAPHICS_VER(xe) >= 35 && !IS_DGFX(xe) &&
> > > > > xe_gt_is_media_type(guc_to_gt(guc)))
> > > > > > +		flags |= GUC_CTL_ENABLE_L2FLUSH_OPT;
> > > > > 
> > > > > Pending whether we also need this on primary GT or not. Since
> > > > > it sounded
> > > > > like it would also need to know whether to do a targeted or
> > > > > full flush
> > > based
> > > > > on current Media status, and it's unclear if here we are
> > > > > meant to opt into
> > > that
> > > > > for every GT/GuC instance vs just the Media GuC.
> > > > > 
> > > > > Reviewed-by: Matthew Auld <matthew.auld@intel.com>
> > > > > 
> > > > > > +
> > > > > >     	return flags;
> > > > > >     }
> > > > > > 
> > > > > > diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h
> > > > > > b/drivers/gpu/drm/xe/xe_guc_fwif.h
> > > > > > index bb8f71d38611..b73fae063fac 100644
> > > > > > --- a/drivers/gpu/drm/xe/xe_guc_fwif.h
> > > > > > +++ b/drivers/gpu/drm/xe/xe_guc_fwif.h
> > > > > > @@ -67,6 +67,7 @@ struct guc_update_exec_queue_policy {
> > > > > >     #define   GUC_CTL_ENABLE_PSMI_LOGGING	BIT(7)
> > > > > >     #define   GUC_CTL_MAIN_GAMCTRL_QUEUES	BIT(9)
> > > > > >     #define   GUC_CTL_DISABLE_SCHEDULER	BIT(14)
> > > > > > +#define   GUC_CTL_ENABLE_L2FLUSH_OPT	BIT(15)
> > > > > > 
> > > > > >     #define GUC_CTL_DEBUG			3
> > > > > >     #define   GUC_LOG_VERBOSITY		REG_GENMASK(1, 0)
> > > > > > diff --git a/drivers/gpu/drm/xe/xe_vm.c
> > > > > > b/drivers/gpu/drm/xe/xe_vm.c
> > > > > > index da0ce0b3704c..0b236e08c158 100644
> > > > > > --- a/drivers/gpu/drm/xe/xe_vm.c
> > > > > > +++ b/drivers/gpu/drm/xe/xe_vm.c
> > > > > > @@ -3481,6 +3481,10 @@ static int
> > > > > > vm_bind_ioctl_check_args(struct
> > > > > xe_device *xe, struct xe_vm *vm,
> > > > > >     				 op ==
> > > > > DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
> > > > > >     		    XE_IOCTL_DBG(xe, coh_mode ==
> > > > > > XE_COH_NONE &&
> > > > > >     				 op ==
> > > > > DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
> > > > > > +		    XE_IOCTL_DBG(xe,
> > > > > > xe_device_is_l2_flush_optimized(xe) &&
> > > > > > +				 (op ==
> > > > > DRM_XE_VM_BIND_OP_MAP_USERPTR ||
> > > > > > +				  is_cpu_addr_mirror) &&
> > > > > > +				 (pat_index != 19 &&
> > > > > > coh_mode !=
> > > > > XE_COH_2WAY)) ||
> > > > > >     		    XE_IOCTL_DBG(xe, comp_en &&
> > > > > >     				 op ==
> > > > > DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
> > > > > >     		    XE_IOCTL_DBG(xe, op ==
> > > > > DRM_XE_VM_BIND_OP_MAP_USERPTR && @@
> > > > > > -3615,6 +3619,10 @@ static int
> > > > > > xe_vm_bind_ioctl_validate_bo(struct
> > > > > xe_device *xe, struct xe_bo *bo,
> > > > > >     	if (XE_IOCTL_DBG(xe, bo->ttm.base.import_attach &&
> > > > > > comp_en))
> > > > > >     		return -EINVAL;
> > > > > > 
> > > > > > +	if (XE_IOCTL_DBG(xe, bo->ttm.base.import_attach &&
> > > > > xe_device_is_l2_flush_optimized(xe) &&
> > > > > > +			 (pat_index != 19 && coh_mode !=
> > > > > > XE_COH_2WAY)))
> > > > > > +		return -EINVAL;
> > > > > > +
> > > > > >     	/* If a BO is protected it can only be mapped if
> > > > > > the key is still valid */
> > > > > >     	if ((bind_flags & DRM_XE_VM_BIND_FLAG_CHECK_PXP)
> > > > > > &&
> > > > > xe_bo_is_protected(bo) &&
> > > > > >     	    op != DRM_XE_VM_BIND_OP_UNMAP && op !=
> > > > > > DRM_XE_VM_BIND_OP_UNMAP_ALL) diff --git
> > > > > > a/drivers/gpu/drm/xe/xe_vm_madvise.c
> > > > > > b/drivers/gpu/drm/xe/xe_vm_madvise.c
> > > > > > index 07169586e35f..376c014239ee 100644
> > > > > > --- a/drivers/gpu/drm/xe/xe_vm_madvise.c
> > > > > > +++ b/drivers/gpu/drm/xe/xe_vm_madvise.c
> > > > > > @@ -411,6 +411,7 @@ int xe_vm_madvise_ioctl(struct
> > > > > > drm_device *dev,
> > > > > void *data, struct drm_file *fil
> > > > > >     	struct xe_vmas_in_madvise_range madvise_range =
> > > > > > {.addr = args-
> > > > > > start,
> > > > > >     							
> > > > > > .range =  args-
> > > > > > range, };
> > > > > >     	struct xe_madvise_details details;
> > > > > > +	u16 pat_index, coh_mode;
> > > > > >     	struct xe_vm *vm;
> > > > > >     	struct drm_exec exec;
> > > > > >     	int err, attr_type;
> > > > > > @@ -447,6 +448,17 @@ int xe_vm_madvise_ioctl(struct
> > > > > > drm_device
> > > *dev,
> > > > > void *data, struct drm_file *fil
> > > > > >     	if (err || !madvise_range.num_vmas)
> > > > > >     		goto madv_fini;
> > > > > > 
> > > > > > +	if (args->type == DRM_XE_MEM_RANGE_ATTR_PAT) {
> > > > > > +		pat_index = array_index_nospec(args-
> > > > > > >pat_index.val, xe-
> > > > > > pat.n_entries);
> > > > > > +		coh_mode = xe_pat_index_get_coh_mode(xe,
> > > > > > pat_index);
> > > > > > +		if (XE_IOCTL_DBG(xe,
> > > > > > madvise_range.has_svm_userptr_vmas
> > > > > &&
> > > > > > +				
> > > > > > xe_device_is_l2_flush_optimized(xe) &&
> > > > > > +				 (pat_index != 19 &&
> > > > > > coh_mode !=
> > > > > XE_COH_2WAY))) {
> > > > > > +			err = -EINVAL;
> > > > > > +			goto madv_fini;
> > > > > > +		}
> > > > > > +	}
> > > > > > +
> > > > > >     	if (madvise_range.has_bo_vmas) {
> > > > > >     		if (args->type ==
> > > > > > DRM_XE_MEM_RANGE_ATTR_ATOMIC) {
> > > > > >     			if (!check_bo_args_are_sane(vm,
> > > > > madvise_range.vmas, @@ -464,6
> > > > > > +476,17 @@ int xe_vm_madvise_ioctl(struct drm_device *dev,
> > > > > > void
> > > *data,
> > > > > > struct drm_file *fil
> > > > > > 
> > > > > >     				if (!bo)
> > > > > >     					continue;
> > > > > > +
> > > > > > +				if (args->type ==
> > > > > DRM_XE_MEM_RANGE_ATTR_PAT) {
> > > > > > +					if
> > > > > > (XE_IOCTL_DBG(xe, bo-
> > > > > > ttm.base.import_attach &&
> > > > > > +
> > > > > xe_device_is_l2_flush_optimized(xe) &&
> > > > > > +							
> > > > > > (pat_index != 19 &&
> > > > > > +							 
> > > > > > coh_mode !=
> > > > > XE_COH_2WAY))) {
> > > > > > +						err = -
> > > > > > EINVAL;
> > > > > > +						goto
> > > > > > err_fini;
> > > > > > +					}
> > > > > > +				}
> > > > > > +
> > > > > >     				err =
> > > > > > drm_exec_lock_obj(&exec, &bo-
> > > > > > ttm.base);
> > > > > >     				drm_exec_retry_on_contenti
> > > > > > on(&exec);
> > > > > >     				if (err)
> > > > > > diff --git a/include/uapi/drm/xe_drm.h
> > > > > > b/include/uapi/drm/xe_drm.h
> > > > > > index ef2565048bdf..862fed3cf1ed 100644
> > > > > > --- a/include/uapi/drm/xe_drm.h
> > > > > > +++ b/include/uapi/drm/xe_drm.h
> > > > > > @@ -1103,7 +1103,9 @@ struct drm_xe_vm_bind_op {
> > > > > >     	 * incoherent GT access is possible.
> > > > > >     	 *
> > > > > >     	 * Note: For userptr and externally imported dma-
> > > > > > buf the kernel
> > > > > expects
> > > > > > -	 * either 1WAY or 2WAY for the @pat_index.
> > > > > > +	 * either 1WAY or 2WAY for the @pat_index.
> > > > > > Starting from NVL-P, for
> > > > > > +	 * userptr, svm, madvise and externally imported
> > > > > > dma-buf the kernel
> > > > > expects
> > > > > > +	 * either 2WAY or 1WAY and XA @pat_index.
> > > > > >     	 *
> > > > > >     	 * For DRM_XE_VM_BIND_FLAG_NULL bindings there are
> > > > > > no KMD
> > > > > restrictions
> > > > > >     	 * on the @pat_index. For such mappings there is
> > > > > > no actual memory
> > > > > > being
> > > > 
> > 

RE: [PATCH V6 3/4] drm/xe/xe3p_lpg: Restrict UAPI to enable L2 flush optimization

[Zhang, Carl]

Acked-by: Carl Zhang

> -----Original Message-----
> From: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> Sent: Tuesday, March 10, 2026 1:30 AM
> To: Auld, Matthew <matthew.auld@intel.com>; Zhang, Carl
> <carl.zhang@intel.com>; Upadhyay, Tejas <tejas.upadhyay@intel.com>; intel-
> xe@lists.freedesktop.org
> Cc: Souza, Jose <jose.souza@intel.com>; Mrozek, Michal
> <michal.mrozek@intel.com>
> Subject: Re: [PATCH V6 3/4] drm/xe/xe3p_lpg: Restrict UAPI to enable L2 flush
> optimization
> 
> On Mon, 2026-03-09 at 17:22 +0000, Matthew Auld wrote:
> > On 09/03/2026 15:29, Zhang, Carl wrote:
> > >
> > >
> > > > -----Original Message-----
> > > > From: Auld, Matthew <matthew.auld@intel.com>
> > > > Sent: Friday, March 6, 2026 6:09 PM
> > > > To: Zhang, Carl <carl.zhang@intel.com>; Upadhyay, Tejas
> > > > <tejas.upadhyay@intel.com>; intel-xe@lists.freedesktop.org
> > > > Cc: thomas.hellstrom@linux.intel.com; Souza, Jose
> > > > <jose.souza@intel.com>; Mrozek, Michal <michal.mrozek@intel.com>
> > > > Subject: Re: [PATCH V6 3/4] drm/xe/xe3p_lpg: Restrict UAPI to
> > > > enable L2 flush optimization
> > > >
> > > > On 06/03/2026 07:11, Zhang, Carl wrote:
> > > > > My understanding:
> > > > > 1. GuC uses a timer to monitor media activity status. The mode
> > > > > becomes
> > > > active only when no media tasks have been detected for 5 seconds.
> > > > From the
> > > > media perspective, this allows legacy behavior to be maintained
> > > > without requiring any changes.
> > > > > 2. The media UMD only needs to set usage hints to gmmlib, which
> > > > > then
> > > > manages the PAT index. Therefore, the UMD itself should not
> > > > require changes—only gmmlib needs to be updated to return PAT
> > > > index 19 on NVL for imported surfaces.
> > > > > My open is:
> > > > > 1. In some applications (e.g., ChromeOS), memory is allocated
> > > > > centrally
> > > > (possibly by minigbm) and then shared across different components.
> > > > If there are no media tasks, the system operates in persistent
> > > > mode.
> > > > However, based
> > > > on current interfaces, imported memory should be configured as
> > > > transient + 1-way coherency. This raises a question: if this
> > > > memory is used exclusively by compute (not media), is this the
> > > > expected behavior?
> > > >
> > > > 2way is also allowed.
> > > >
> > >
> > > But 2way is slower than 1 way , right?
> >
> > Likely it would be, I think. But for Media only, not sure.
> >
> > >
> > > > > 2. For userptr memory that is used by only one component, I
> > > > > believe 1-way
> > > > coherency should be sufficient?
> > > >
> > > > I think for 1) and 2), it mostly comes down to CPU/host <-> GPU
> > > > coherency, right? If you don't use 2WAY or XA, userspace would now
> > > > have to manually handle the coherency, in case in "persistent"
> > > > mode. It doesn't matter if there is just one component/app, the
> > > > coherency issue would still be there.
> > > >
> > > For Media (vdbox, vebox), does not use L2 cache,  so, if it is
> > > userptr 1-way is enough, just need snoop cpu cache.
> > >
> > > > For example, for 2) if you only use 1way without XA, then AFAIK
> > > > you now need manual flushing, if GPU side is cached and CPU is
> > > > expecting to see coherent view. Like say GPU writes something and
> > > > CPU later reads it. The 1- way here would just ensure that GPU
> > > > snoops the CPU caches on the first access. But if it then gets
> > > > cached on GPU side, there is now no guaranteed flush when that GPU
> > > > job is complete, when in "persistent" mode.
> > > >
> > > a. my understanding , L2 is used only for RCS and VCS. Not for VCS
> > > and VECS.
> > > Please correct me if there is any misunderstanding.  So, if one
> > > external resource is only used by media . never be used by CCS RCS.
> > > whether we should still have such limitation.
> >
> > Yeah, that matches my understanding. It sounded like Media access does
> > not go via l2, so I assume goes directly to system memory. Hence why
> > l2
> > needs to be fully flushed if sharing something with Media (which is
> > assumed whenever Media is currently turned on).
> >
> > >
> > > b. if there is media task, seems it cant be "persistent" mode. Of
> > > course, maybe, it is "persistent" mode, then media task comes, it
> > > turns to "transient" mode.
> > > But the data is still in cache , not flushed.  for this case, I
> > > agree that any resource used firstly by CCS or RCS then shared it to
> > > media, it should be set to 2-way or 1-way + XA.
> > >
> > > > So assumption was that for userptr, the memory comes from the
> > > > host, and access is likely shared with CPU/host, so seems
> > > > reasonable you would want XA or 2WAY. For foreign imported memory
> > > > you are likely sharing with host or some other device/driver, so
> > > > seems reasonable you would probably want XA or 2WAY.
> > > >
> > > > We can drop the restrictions, if userspace really needs it, but it
> > > > would be up to userspace to deal with all the CPU/host vs GPU
> > > > coherency fun, if applicable.
> > > > The restrictions do simplify things a little on the KMD side, plus
> > > > the validation angle in IGT.
> > > >
> > > I am thinking whether it is too strict.  There is different
> > > useagecases.
> >
> > Do you know which index(s) you would pick instead, for Media only
> > cases?
> > I think that is the only edge case you are concerned with here?
> >
> > Is it not the case that if you are only submitting within Media and it
> > if it doesn't actually use l2, wouldn't the XA and l2 cache mode stuff
> > be a no-op anyway, since the access from Media side never goes through
> > l2?
> 
> I was wondering whether that could actually be the case as well.
> 
> /Thomas
> 
> 
> >
> > Do you know which index that we don't allow, would give
> > different/preferred behaviour for Media only case?
> >
> > >
> > > > >
> > > > > Thanks
> > > > > Carl
> > > > >
> > > > > > -----Original Message-----
> > > > > > From: Auld, Matthew <matthew.auld@intel.com>
> > > > > > Sent: Thursday, March 5, 2026 10:00 PM
> > > > > > To: Upadhyay, Tejas <tejas.upadhyay@intel.com>; intel-
> > > > > > xe@lists.freedesktop.org
> > > > > > Cc: thomas.hellstrom@linux.intel.com; Zhang, Carl
> > > > <carl.zhang@intel.com>;
> > > > > > Souza, Jose <jose.souza@intel.com>; Mrozek, Michal
> > > > > > <michal.mrozek@intel.com>
> > > > > > Subject: Re: [PATCH V6 3/4] drm/xe/xe3p_lpg: Restrict UAPI to
> > > > > > enable L2
> > > > flush
> > > > > > optimization
> > > > > >
> > > > > > On 05/03/2026 12:19, Tejas Upadhyay wrote:
> > > > > > > When set, starting xe3p_lpg, the L2 flush optimization
> > > > > > > feature will control whether L2 is in Persistent or
> > > > > > > Transient mode through monitoring of media activity.
> > > > > > >
> > > > > > > To enable L2 flush optimization include new feature flag
> > > > > > > GUC_CTL_ENABLE_L2FLUSH_OPT for Novalake platforms when
> media
> > > > type
> > > > > > is
> > > > > > > detected.
> > > > > > >
> > > > > > > Tighten UAPI validation to restrict userptr, svm and dmabuf
> > > > > > > mappings to be either 2WAY or XA+1WAY
> > > > > > >
> > > > > > > V5(Thomas): logic correction
> > > > > > > V4(MattA): Modify uapi doc and commit
> > > > > > > V3(MattA): check valid op and pat_index value
> > > > > > > V2(MattA): validate dma-buf bos and madvise pat-index
> > > > > > >
> > > > > > > Acked-by: José Roberto de Souza <jose.souza@intel.com>
> > > > > > > Acked-by: Michal Mrozek <michal.mrozek@intel.com>
> > > > > > > Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
> > > > > > > ---
> > > > > > >     drivers/gpu/drm/xe/xe_guc.c        |  3 +++
> > > > > > >     drivers/gpu/drm/xe/xe_guc_fwif.h   |  1 +
> > > > > > >     drivers/gpu/drm/xe/xe_vm.c         |  8 ++++++++
> > > > > > >     drivers/gpu/drm/xe/xe_vm_madvise.c | 23
> > > > > > > +++++++++++++++++++++++
> > > > > > >     include/uapi/drm/xe_drm.h          |  4 +++-
> > > > > > >     5 files changed, 38 insertions(+), 1 deletion(-)
> > > > > > >
> > > > > > > diff --git a/drivers/gpu/drm/xe/xe_guc.c
> > > > > > > b/drivers/gpu/drm/xe/xe_guc.c index
> > > > > > > 54d2fc780127..43dc4353206f 100644
> > > > > > > --- a/drivers/gpu/drm/xe/xe_guc.c
> > > > > > > +++ b/drivers/gpu/drm/xe/xe_guc.c
> > > > > > > @@ -98,6 +98,9 @@ static u32 guc_ctl_feature_flags(struct
> > > > > > > xe_guc *guc)
> > > > > > >     	if (xe_guc_using_main_gamctrl_queues(guc))
> > > > > > >     		flags |= GUC_CTL_MAIN_GAMCTRL_QUEUES;
> > > > > > >
> > > > > > > +	if (GRAPHICS_VER(xe) >= 35 && !IS_DGFX(xe) &&
> > > > > > xe_gt_is_media_type(guc_to_gt(guc)))
> > > > > > > +		flags |= GUC_CTL_ENABLE_L2FLUSH_OPT;
> > > > > >
> > > > > > Pending whether we also need this on primary GT or not. Since
> > > > > > it sounded like it would also need to know whether to do a
> > > > > > targeted or full flush
> > > > based
> > > > > > on current Media status, and it's unclear if here we are meant
> > > > > > to opt into
> > > > that
> > > > > > for every GT/GuC instance vs just the Media GuC.
> > > > > >
> > > > > > Reviewed-by: Matthew Auld <matthew.auld@intel.com>
> > > > > >
> > > > > > > +
> > > > > > >     	return flags;
> > > > > > >     }
> > > > > > >
> > > > > > > diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h
> > > > > > > b/drivers/gpu/drm/xe/xe_guc_fwif.h
> > > > > > > index bb8f71d38611..b73fae063fac 100644
> > > > > > > --- a/drivers/gpu/drm/xe/xe_guc_fwif.h
> > > > > > > +++ b/drivers/gpu/drm/xe/xe_guc_fwif.h
> > > > > > > @@ -67,6 +67,7 @@ struct guc_update_exec_queue_policy {
> > > > > > >     #define   GUC_CTL_ENABLE_PSMI_LOGGING	BIT(7)
> > > > > > >     #define   GUC_CTL_MAIN_GAMCTRL_QUEUES	BIT(9)
> > > > > > >     #define   GUC_CTL_DISABLE_SCHEDULER	BIT(14)
> > > > > > > +#define   GUC_CTL_ENABLE_L2FLUSH_OPT	BIT(15)
> > > > > > >
> > > > > > >     #define GUC_CTL_DEBUG			3
> > > > > > >     #define   GUC_LOG_VERBOSITY		REG_GENMASK(1, 0)
> > > > > > > diff --git a/drivers/gpu/drm/xe/xe_vm.c
> > > > > > > b/drivers/gpu/drm/xe/xe_vm.c index
> > > > > > > da0ce0b3704c..0b236e08c158 100644
> > > > > > > --- a/drivers/gpu/drm/xe/xe_vm.c
> > > > > > > +++ b/drivers/gpu/drm/xe/xe_vm.c
> > > > > > > @@ -3481,6 +3481,10 @@ static int
> > > > > > > vm_bind_ioctl_check_args(struct
> > > > > > xe_device *xe, struct xe_vm *vm,
> > > > > > >     				 op ==
> > > > > > DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
> > > > > > >     		    XE_IOCTL_DBG(xe, coh_mode == XE_COH_NONE
> &&
> > > > > > >     				 op ==
> > > > > > DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
> > > > > > > +		    XE_IOCTL_DBG(xe,
> > > > > > > xe_device_is_l2_flush_optimized(xe) &&
> > > > > > > +				 (op ==
> > > > > > DRM_XE_VM_BIND_OP_MAP_USERPTR ||
> > > > > > > +				  is_cpu_addr_mirror) &&
> > > > > > > +				 (pat_index != 19 &&
> > > > > > > coh_mode !=
> > > > > > XE_COH_2WAY)) ||
> > > > > > >     		    XE_IOCTL_DBG(xe, comp_en &&
> > > > > > >     				 op ==
> > > > > > DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
> > > > > > >     		    XE_IOCTL_DBG(xe, op ==
> > > > > > DRM_XE_VM_BIND_OP_MAP_USERPTR && @@
> > > > > > > -3615,6 +3619,10 @@ static int
> > > > > > > xe_vm_bind_ioctl_validate_bo(struct
> > > > > > xe_device *xe, struct xe_bo *bo,
> > > > > > >     	if (XE_IOCTL_DBG(xe, bo->ttm.base.import_attach &&
> > > > > > > comp_en))
> > > > > > >     		return -EINVAL;
> > > > > > >
> > > > > > > +	if (XE_IOCTL_DBG(xe, bo->ttm.base.import_attach &&
> > > > > > xe_device_is_l2_flush_optimized(xe) &&
> > > > > > > +			 (pat_index != 19 && coh_mode !=
> > > > > > > XE_COH_2WAY)))
> > > > > > > +		return -EINVAL;
> > > > > > > +
> > > > > > >     	/* If a BO is protected it can only be mapped if the
> > > > > > > key is still valid */
> > > > > > >     	if ((bind_flags & DRM_XE_VM_BIND_FLAG_CHECK_PXP) &&
> > > > > > xe_bo_is_protected(bo) &&
> > > > > > >     	    op != DRM_XE_VM_BIND_OP_UNMAP && op !=
> > > > > > > DRM_XE_VM_BIND_OP_UNMAP_ALL) diff --git
> > > > > > > a/drivers/gpu/drm/xe/xe_vm_madvise.c
> > > > > > > b/drivers/gpu/drm/xe/xe_vm_madvise.c
> > > > > > > index 07169586e35f..376c014239ee 100644
> > > > > > > --- a/drivers/gpu/drm/xe/xe_vm_madvise.c
> > > > > > > +++ b/drivers/gpu/drm/xe/xe_vm_madvise.c
> > > > > > > @@ -411,6 +411,7 @@ int xe_vm_madvise_ioctl(struct
> > > > > > > drm_device *dev,
> > > > > > void *data, struct drm_file *fil
> > > > > > >     	struct xe_vmas_in_madvise_range madvise_range = {.addr
> > > > > > > = args- start,
> > > > > > >
> > > > > > > .range =  args-
> > > > > > > range, };
> > > > > > >     	struct xe_madvise_details details;
> > > > > > > +	u16 pat_index, coh_mode;
> > > > > > >     	struct xe_vm *vm;
> > > > > > >     	struct drm_exec exec;
> > > > > > >     	int err, attr_type;
> > > > > > > @@ -447,6 +448,17 @@ int xe_vm_madvise_ioctl(struct
> > > > > > > drm_device
> > > > *dev,
> > > > > > void *data, struct drm_file *fil
> > > > > > >     	if (err || !madvise_range.num_vmas)
> > > > > > >     		goto madv_fini;
> > > > > > >
> > > > > > > +	if (args->type == DRM_XE_MEM_RANGE_ATTR_PAT) {
> > > > > > > +		pat_index = array_index_nospec(args-
> > > > > > > >pat_index.val, xe-
> > > > > > > pat.n_entries);
> > > > > > > +		coh_mode = xe_pat_index_get_coh_mode(xe,
> > > > > > > pat_index);
> > > > > > > +		if (XE_IOCTL_DBG(xe,
> > > > > > > madvise_range.has_svm_userptr_vmas
> > > > > > &&
> > > > > > > +
> > > > > > > xe_device_is_l2_flush_optimized(xe) &&
> > > > > > > +				 (pat_index != 19 &&
> > > > > > > coh_mode !=
> > > > > > XE_COH_2WAY))) {
> > > > > > > +			err = -EINVAL;
> > > > > > > +			goto madv_fini;
> > > > > > > +		}
> > > > > > > +	}
> > > > > > > +
> > > > > > >     	if (madvise_range.has_bo_vmas) {
> > > > > > >     		if (args->type ==
> > > > > > > DRM_XE_MEM_RANGE_ATTR_ATOMIC) {
> > > > > > >     			if (!check_bo_args_are_sane(vm,
> > > > > > madvise_range.vmas, @@ -464,6
> > > > > > > +476,17 @@ int xe_vm_madvise_ioctl(struct drm_device *dev,
> > > > > > > void
> > > > *data,
> > > > > > > struct drm_file *fil
> > > > > > >
> > > > > > >     				if (!bo)
> > > > > > >     					continue;
> > > > > > > +
> > > > > > > +				if (args->type ==
> > > > > > DRM_XE_MEM_RANGE_ATTR_PAT) {
> > > > > > > +					if
> > > > > > > (XE_IOCTL_DBG(xe, bo-
> > > > > > > ttm.base.import_attach &&
> > > > > > > +
> > > > > > xe_device_is_l2_flush_optimized(xe) &&
> > > > > > > +
> > > > > > > (pat_index != 19 &&
> > > > > > > +
> > > > > > > coh_mode !=
> > > > > > XE_COH_2WAY))) {
> > > > > > > +						err = -
> > > > > > > EINVAL;
> > > > > > > +						goto
> > > > > > > err_fini;
> > > > > > > +					}
> > > > > > > +				}
> > > > > > > +
> > > > > > >     				err =
> > > > > > > drm_exec_lock_obj(&exec, &bo- ttm.base);
> > > > > > >     				drm_exec_retry_on_contenti
> on(&exec);
> > > > > > >     				if (err)
> > > > > > > diff --git a/include/uapi/drm/xe_drm.h
> > > > > > > b/include/uapi/drm/xe_drm.h index ef2565048bdf..862fed3cf1ed
> > > > > > > 100644
> > > > > > > --- a/include/uapi/drm/xe_drm.h
> > > > > > > +++ b/include/uapi/drm/xe_drm.h
> > > > > > > @@ -1103,7 +1103,9 @@ struct drm_xe_vm_bind_op {
> > > > > > >     	 * incoherent GT access is possible.
> > > > > > >     	 *
> > > > > > >     	 * Note: For userptr and externally imported dma- buf
> > > > > > > the kernel
> > > > > > expects
> > > > > > > -	 * either 1WAY or 2WAY for the @pat_index.
> > > > > > > +	 * either 1WAY or 2WAY for the @pat_index.
> > > > > > > Starting from NVL-P, for
> > > > > > > +	 * userptr, svm, madvise and externally imported
> > > > > > > dma-buf the kernel
> > > > > > expects
> > > > > > > +	 * either 2WAY or 1WAY and XA @pat_index.
> > > > > > >     	 *
> > > > > > >     	 * For DRM_XE_VM_BIND_FLAG_NULL bindings there are no
> > > > > > > KMD
> > > > > > restrictions
> > > > > > >     	 * on the @pat_index. For such mappings there is no
> > > > > > > actual memory being
> > > > >
> > >

[PATCH V6 4/4] drm/xe/xe3p: Skip TD flush

[Tejas Upadhyay]

Xe3p has HW ability to do transient display flush so the xe driver can
enable this HW feature by default and skip the software TD flush.

Bspec: 60002
Reviewed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
---
 drivers/gpu/drm/xe/xe_device.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index 94c9f17da4b4..0dca20133b94 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -1166,6 +1166,14 @@ void xe_device_td_flush(struct xe_device *xe)
 {
 	struct xe_gt *root_gt;
 
+	/*
+	 * From Xe3p onward the HW takes care of flush of TD entries also along
+	 * with flushing XA entries, which will be at the usual sync points,
+	 * like at the end of submission, so no manual flush is needed here.
+	 */
+	if (GRAPHICS_VER(xe) >= 35)
+		return;
+
 	if (!IS_DGFX(xe) || GRAPHICS_VER(xe) < 20)
 		return;
 
-- 
2.52.0

✓ CI.KUnit: success for drm/xe/xe3p_lpg: L2 flush optimization (rev7)

[Patchwork]

== Series Details ==

Series: drm/xe/xe3p_lpg: L2 flush optimization (rev7)
URL   : https://patchwork.freedesktop.org/series/158017/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[12:14:47] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[12:14:51] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[12:15:22] Starting KUnit Kernel (1/1)...
[12:15:22] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[12:15:22] ================== guc_buf (11 subtests) ===================
[12:15:22] [PASSED] test_smallest
[12:15:22] [PASSED] test_largest
[12:15:22] [PASSED] test_granular
[12:15:22] [PASSED] test_unique
[12:15:22] [PASSED] test_overlap
[12:15:22] [PASSED] test_reusable
[12:15:22] [PASSED] test_too_big
[12:15:22] [PASSED] test_flush
[12:15:22] [PASSED] test_lookup
[12:15:22] [PASSED] test_data
[12:15:22] [PASSED] test_class
[12:15:22] ===================== [PASSED] guc_buf =====================
[12:15:22] =================== guc_dbm (7 subtests) ===================
[12:15:22] [PASSED] test_empty
[12:15:22] [PASSED] test_default
[12:15:22] ======================== test_size  ========================
[12:15:22] [PASSED] 4
[12:15:22] [PASSED] 8
[12:15:22] [PASSED] 32
[12:15:22] [PASSED] 256
[12:15:22] ==================== [PASSED] test_size ====================
[12:15:22] ======================= test_reuse  ========================
[12:15:22] [PASSED] 4
[12:15:22] [PASSED] 8
[12:15:22] [PASSED] 32
[12:15:22] [PASSED] 256
[12:15:22] =================== [PASSED] test_reuse ====================
[12:15:22] =================== test_range_overlap  ====================
[12:15:22] [PASSED] 4
[12:15:22] [PASSED] 8
[12:15:22] [PASSED] 32
[12:15:22] [PASSED] 256
[12:15:22] =============== [PASSED] test_range_overlap ================
[12:15:22] =================== test_range_compact  ====================
[12:15:22] [PASSED] 4
[12:15:22] [PASSED] 8
[12:15:22] [PASSED] 32
[12:15:22] [PASSED] 256
[12:15:22] =============== [PASSED] test_range_compact ================
[12:15:22] ==================== test_range_spare  =====================
[12:15:22] [PASSED] 4
[12:15:22] [PASSED] 8
[12:15:22] [PASSED] 32
[12:15:22] [PASSED] 256
[12:15:22] ================ [PASSED] test_range_spare =================
[12:15:22] ===================== [PASSED] guc_dbm =====================
[12:15:22] =================== guc_idm (6 subtests) ===================
[12:15:22] [PASSED] bad_init
[12:15:22] [PASSED] no_init
[12:15:22] [PASSED] init_fini
[12:15:22] [PASSED] check_used
[12:15:22] [PASSED] check_quota
[12:15:22] [PASSED] check_all
[12:15:22] ===================== [PASSED] guc_idm =====================
[12:15:22] ================== no_relay (3 subtests) ===================
[12:15:22] [PASSED] xe_drops_guc2pf_if_not_ready
[12:15:22] [PASSED] xe_drops_guc2vf_if_not_ready
[12:15:22] [PASSED] xe_rejects_send_if_not_ready
[12:15:22] ==================== [PASSED] no_relay =====================
[12:15:22] ================== pf_relay (14 subtests) ==================
[12:15:22] [PASSED] pf_rejects_guc2pf_too_short
[12:15:22] [PASSED] pf_rejects_guc2pf_too_long
[12:15:22] [PASSED] pf_rejects_guc2pf_no_payload
[12:15:22] [PASSED] pf_fails_no_payload
[12:15:22] [PASSED] pf_fails_bad_origin
[12:15:22] [PASSED] pf_fails_bad_type
[12:15:22] [PASSED] pf_txn_reports_error
[12:15:22] [PASSED] pf_txn_sends_pf2guc
[12:15:22] [PASSED] pf_sends_pf2guc
[12:15:22] [SKIPPED] pf_loopback_nop
[12:15:22] [SKIPPED] pf_loopback_echo
[12:15:22] [SKIPPED] pf_loopback_fail
[12:15:22] [SKIPPED] pf_loopback_busy
[12:15:22] [SKIPPED] pf_loopback_retry
[12:15:22] ==================== [PASSED] pf_relay =====================
[12:15:22] ================== vf_relay (3 subtests) ===================
[12:15:22] [PASSED] vf_rejects_guc2vf_too_short
[12:15:22] [PASSED] vf_rejects_guc2vf_too_long
[12:15:22] [PASSED] vf_rejects_guc2vf_no_payload
[12:15:22] ==================== [PASSED] vf_relay =====================
[12:15:22] ================ pf_gt_config (9 subtests) =================
[12:15:22] [PASSED] fair_contexts_1vf
[12:15:22] [PASSED] fair_doorbells_1vf
[12:15:22] [PASSED] fair_ggtt_1vf
[12:15:22] ====================== fair_vram_1vf  ======================
[12:15:22] [PASSED] 3.50 GiB
[12:15:22] [PASSED] 11.5 GiB
[12:15:22] [PASSED] 15.5 GiB
[12:15:22] [PASSED] 31.5 GiB
[12:15:22] [PASSED] 63.5 GiB
[12:15:22] [PASSED] 1.91 GiB
[12:15:22] ================== [PASSED] fair_vram_1vf ==================
[12:15:22] ================ fair_vram_1vf_admin_only  =================
[12:15:22] [PASSED] 3.50 GiB
[12:15:22] [PASSED] 11.5 GiB
[12:15:22] [PASSED] 15.5 GiB
[12:15:22] [PASSED] 31.5 GiB
[12:15:22] [PASSED] 63.5 GiB
[12:15:22] [PASSED] 1.91 GiB
[12:15:22] ============ [PASSED] fair_vram_1vf_admin_only =============
[12:15:22] ====================== fair_contexts  ======================
[12:15:22] [PASSED] 1 VF
[12:15:22] [PASSED] 2 VFs
[12:15:22] [PASSED] 3 VFs
[12:15:22] [PASSED] 4 VFs
[12:15:22] [PASSED] 5 VFs
[12:15:22] [PASSED] 6 VFs
[12:15:22] [PASSED] 7 VFs
[12:15:22] [PASSED] 8 VFs
[12:15:22] [PASSED] 9 VFs
[12:15:22] [PASSED] 10 VFs
[12:15:22] [PASSED] 11 VFs
[12:15:22] [PASSED] 12 VFs
[12:15:22] [PASSED] 13 VFs
[12:15:22] [PASSED] 14 VFs
[12:15:22] [PASSED] 15 VFs
[12:15:22] [PASSED] 16 VFs
[12:15:22] [PASSED] 17 VFs
[12:15:22] [PASSED] 18 VFs
[12:15:22] [PASSED] 19 VFs
[12:15:22] [PASSED] 20 VFs
[12:15:22] [PASSED] 21 VFs
[12:15:22] [PASSED] 22 VFs
[12:15:22] [PASSED] 23 VFs
[12:15:22] [PASSED] 24 VFs
[12:15:22] [PASSED] 25 VFs
[12:15:22] [PASSED] 26 VFs
[12:15:22] [PASSED] 27 VFs
[12:15:22] [PASSED] 28 VFs
[12:15:22] [PASSED] 29 VFs
[12:15:22] [PASSED] 30 VFs
[12:15:22] [PASSED] 31 VFs
[12:15:22] [PASSED] 32 VFs
[12:15:22] [PASSED] 33 VFs
[12:15:22] [PASSED] 34 VFs
[12:15:22] [PASSED] 35 VFs
[12:15:22] [PASSED] 36 VFs
[12:15:22] [PASSED] 37 VFs
[12:15:22] [PASSED] 38 VFs
[12:15:22] [PASSED] 39 VFs
[12:15:22] [PASSED] 40 VFs
[12:15:22] [PASSED] 41 VFs
[12:15:22] [PASSED] 42 VFs
[12:15:22] [PASSED] 43 VFs
[12:15:22] [PASSED] 44 VFs
[12:15:22] [PASSED] 45 VFs
[12:15:22] [PASSED] 46 VFs
[12:15:22] [PASSED] 47 VFs
[12:15:22] [PASSED] 48 VFs
[12:15:22] [PASSED] 49 VFs
[12:15:22] [PASSED] 50 VFs
[12:15:22] [PASSED] 51 VFs
[12:15:22] [PASSED] 52 VFs
[12:15:22] [PASSED] 53 VFs
[12:15:22] [PASSED] 54 VFs
[12:15:22] [PASSED] 55 VFs
[12:15:22] [PASSED] 56 VFs
[12:15:22] [PASSED] 57 VFs
[12:15:22] [PASSED] 58 VFs
[12:15:22] [PASSED] 59 VFs
[12:15:22] [PASSED] 60 VFs
[12:15:22] [PASSED] 61 VFs
[12:15:22] [PASSED] 62 VFs
[12:15:22] [PASSED] 63 VFs
[12:15:22] ================== [PASSED] fair_contexts ==================
[12:15:22] ===================== fair_doorbells  ======================
[12:15:22] [PASSED] 1 VF
[12:15:22] [PASSED] 2 VFs
[12:15:22] [PASSED] 3 VFs
[12:15:22] [PASSED] 4 VFs
[12:15:22] [PASSED] 5 VFs
[12:15:22] [PASSED] 6 VFs
[12:15:22] [PASSED] 7 VFs
[12:15:22] [PASSED] 8 VFs
[12:15:22] [PASSED] 9 VFs
[12:15:22] [PASSED] 10 VFs
[12:15:22] [PASSED] 11 VFs
[12:15:22] [PASSED] 12 VFs
[12:15:22] [PASSED] 13 VFs
[12:15:22] [PASSED] 14 VFs
[12:15:22] [PASSED] 15 VFs
[12:15:22] [PASSED] 16 VFs
[12:15:22] [PASSED] 17 VFs
[12:15:22] [PASSED] 18 VFs
[12:15:22] [PASSED] 19 VFs
[12:15:22] [PASSED] 20 VFs
[12:15:22] [PASSED] 21 VFs
[12:15:22] [PASSED] 22 VFs
[12:15:22] [PASSED] 23 VFs
[12:15:22] [PASSED] 24 VFs
[12:15:22] [PASSED] 25 VFs
[12:15:22] [PASSED] 26 VFs
[12:15:22] [PASSED] 27 VFs
[12:15:22] [PASSED] 28 VFs
[12:15:22] [PASSED] 29 VFs
[12:15:22] [PASSED] 30 VFs
[12:15:22] [PASSED] 31 VFs
[12:15:22] [PASSED] 32 VFs
[12:15:22] [PASSED] 33 VFs
[12:15:22] [PASSED] 34 VFs
[12:15:22] [PASSED] 35 VFs
[12:15:22] [PASSED] 36 VFs
[12:15:22] [PASSED] 37 VFs
[12:15:22] [PASSED] 38 VFs
[12:15:22] [PASSED] 39 VFs
[12:15:22] [PASSED] 40 VFs
[12:15:22] [PASSED] 41 VFs
[12:15:22] [PASSED] 42 VFs
[12:15:22] [PASSED] 43 VFs
[12:15:22] [PASSED] 44 VFs
[12:15:22] [PASSED] 45 VFs
[12:15:22] [PASSED] 46 VFs
[12:15:22] [PASSED] 47 VFs
[12:15:22] [PASSED] 48 VFs
[12:15:22] [PASSED] 49 VFs
[12:15:22] [PASSED] 50 VFs
[12:15:22] [PASSED] 51 VFs
[12:15:22] [PASSED] 52 VFs
[12:15:22] [PASSED] 53 VFs
[12:15:22] [PASSED] 54 VFs
[12:15:22] [PASSED] 55 VFs
[12:15:22] [PASSED] 56 VFs
[12:15:22] [PASSED] 57 VFs
[12:15:22] [PASSED] 58 VFs
[12:15:22] [PASSED] 59 VFs
[12:15:22] [PASSED] 60 VFs
[12:15:22] [PASSED] 61 VFs
[12:15:22] [PASSED] 62 VFs
[12:15:22] [PASSED] 63 VFs
[12:15:22] ================= [PASSED] fair_doorbells ==================
[12:15:22] ======================== fair_ggtt  ========================
[12:15:22] [PASSED] 1 VF
[12:15:22] [PASSED] 2 VFs
[12:15:22] [PASSED] 3 VFs
[12:15:22] [PASSED] 4 VFs
[12:15:22] [PASSED] 5 VFs
[12:15:22] [PASSED] 6 VFs
[12:15:22] [PASSED] 7 VFs
[12:15:22] [PASSED] 8 VFs
[12:15:22] [PASSED] 9 VFs
[12:15:22] [PASSED] 10 VFs
[12:15:22] [PASSED] 11 VFs
[12:15:22] [PASSED] 12 VFs
[12:15:22] [PASSED] 13 VFs
[12:15:22] [PASSED] 14 VFs
[12:15:22] [PASSED] 15 VFs
[12:15:22] [PASSED] 16 VFs
[12:15:22] [PASSED] 17 VFs
[12:15:22] [PASSED] 18 VFs
[12:15:22] [PASSED] 19 VFs
[12:15:22] [PASSED] 20 VFs
[12:15:22] [PASSED] 21 VFs
[12:15:22] [PASSED] 22 VFs
[12:15:22] [PASSED] 23 VFs
[12:15:22] [PASSED] 24 VFs
[12:15:22] [PASSED] 25 VFs
[12:15:22] [PASSED] 26 VFs
[12:15:22] [PASSED] 27 VFs
[12:15:22] [PASSED] 28 VFs
[12:15:22] [PASSED] 29 VFs
[12:15:22] [PASSED] 30 VFs
[12:15:22] [PASSED] 31 VFs
[12:15:22] [PASSED] 32 VFs
[12:15:22] [PASSED] 33 VFs
[12:15:22] [PASSED] 34 VFs
[12:15:22] [PASSED] 35 VFs
[12:15:22] [PASSED] 36 VFs
[12:15:22] [PASSED] 37 VFs
[12:15:22] [PASSED] 38 VFs
[12:15:22] [PASSED] 39 VFs
[12:15:22] [PASSED] 40 VFs
[12:15:22] [PASSED] 41 VFs
[12:15:22] [PASSED] 42 VFs
[12:15:22] [PASSED] 43 VFs
[12:15:22] [PASSED] 44 VFs
[12:15:22] [PASSED] 45 VFs
[12:15:22] [PASSED] 46 VFs
[12:15:22] [PASSED] 47 VFs
[12:15:22] [PASSED] 48 VFs
[12:15:22] [PASSED] 49 VFs
[12:15:22] [PASSED] 50 VFs
[12:15:22] [PASSED] 51 VFs
[12:15:22] [PASSED] 52 VFs
[12:15:22] [PASSED] 53 VFs
[12:15:22] [PASSED] 54 VFs
[12:15:22] [PASSED] 55 VFs
[12:15:22] [PASSED] 56 VFs
[12:15:22] [PASSED] 57 VFs
[12:15:22] [PASSED] 58 VFs
[12:15:22] [PASSED] 59 VFs
[12:15:22] [PASSED] 60 VFs
[12:15:22] [PASSED] 61 VFs
[12:15:22] [PASSED] 62 VFs
[12:15:22] [PASSED] 63 VFs
[12:15:22] ==================== [PASSED] fair_ggtt ====================
[12:15:22] ======================== fair_vram  ========================
[12:15:22] [PASSED] 1 VF
[12:15:22] [PASSED] 2 VFs
[12:15:22] [PASSED] 3 VFs
[12:15:22] [PASSED] 4 VFs
[12:15:22] [PASSED] 5 VFs
[12:15:22] [PASSED] 6 VFs
[12:15:22] [PASSED] 7 VFs
[12:15:22] [PASSED] 8 VFs
[12:15:22] [PASSED] 9 VFs
[12:15:22] [PASSED] 10 VFs
[12:15:22] [PASSED] 11 VFs
[12:15:22] [PASSED] 12 VFs
[12:15:22] [PASSED] 13 VFs
[12:15:22] [PASSED] 14 VFs
[12:15:22] [PASSED] 15 VFs
[12:15:22] [PASSED] 16 VFs
[12:15:22] [PASSED] 17 VFs
[12:15:22] [PASSED] 18 VFs
[12:15:22] [PASSED] 19 VFs
[12:15:22] [PASSED] 20 VFs
[12:15:22] [PASSED] 21 VFs
[12:15:22] [PASSED] 22 VFs
[12:15:22] [PASSED] 23 VFs
[12:15:22] [PASSED] 24 VFs
[12:15:22] [PASSED] 25 VFs
[12:15:22] [PASSED] 26 VFs
[12:15:22] [PASSED] 27 VFs
[12:15:22] [PASSED] 28 VFs
[12:15:22] [PASSED] 29 VFs
[12:15:22] [PASSED] 30 VFs
[12:15:22] [PASSED] 31 VFs
[12:15:22] [PASSED] 32 VFs
[12:15:22] [PASSED] 33 VFs
[12:15:22] [PASSED] 34 VFs
[12:15:22] [PASSED] 35 VFs
[12:15:22] [PASSED] 36 VFs
[12:15:22] [PASSED] 37 VFs
[12:15:22] [PASSED] 38 VFs
[12:15:22] [PASSED] 39 VFs
[12:15:22] [PASSED] 40 VFs
[12:15:22] [PASSED] 41 VFs
[12:15:22] [PASSED] 42 VFs
[12:15:22] [PASSED] 43 VFs
[12:15:22] [PASSED] 44 VFs
[12:15:22] [PASSED] 45 VFs
[12:15:22] [PASSED] 46 VFs
[12:15:22] [PASSED] 47 VFs
[12:15:22] [PASSED] 48 VFs
[12:15:22] [PASSED] 49 VFs
[12:15:22] [PASSED] 50 VFs
[12:15:22] [PASSED] 51 VFs
[12:15:22] [PASSED] 52 VFs
[12:15:22] [PASSED] 53 VFs
[12:15:22] [PASSED] 54 VFs
[12:15:22] [PASSED] 55 VFs
[12:15:22] [PASSED] 56 VFs
[12:15:22] [PASSED] 57 VFs
[12:15:22] [PASSED] 58 VFs
[12:15:22] [PASSED] 59 VFs
[12:15:22] [PASSED] 60 VFs
[12:15:22] [PASSED] 61 VFs
[12:15:22] [PASSED] 62 VFs
[12:15:22] [PASSED] 63 VFs
[12:15:22] ==================== [PASSED] fair_vram ====================
[12:15:22] ================== [PASSED] pf_gt_config ===================
[12:15:22] ===================== lmtt (1 subtest) =====================
[12:15:22] ======================== test_ops  =========================
[12:15:22] [PASSED] 2-level
[12:15:22] [PASSED] multi-level
[12:15:22] ==================== [PASSED] test_ops =====================
[12:15:22] ====================== [PASSED] lmtt =======================
[12:15:22] ================= pf_service (11 subtests) =================
[12:15:22] [PASSED] pf_negotiate_any
[12:15:22] [PASSED] pf_negotiate_base_match
[12:15:22] [PASSED] pf_negotiate_base_newer
[12:15:22] [PASSED] pf_negotiate_base_next
[12:15:22] [SKIPPED] pf_negotiate_base_older
[12:15:22] [PASSED] pf_negotiate_base_prev
[12:15:22] [PASSED] pf_negotiate_latest_match
[12:15:22] [PASSED] pf_negotiate_latest_newer
[12:15:22] [PASSED] pf_negotiate_latest_next
[12:15:22] [SKIPPED] pf_negotiate_latest_older
[12:15:22] [SKIPPED] pf_negotiate_latest_prev
[12:15:22] =================== [PASSED] pf_service ====================
[12:15:22] ================= xe_guc_g2g (2 subtests) ==================
[12:15:22] ============== xe_live_guc_g2g_kunit_default  ==============
[12:15:22] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[12:15:22] ============== xe_live_guc_g2g_kunit_allmem  ===============
[12:15:22] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[12:15:22] =================== [SKIPPED] xe_guc_g2g ===================
[12:15:22] =================== xe_mocs (2 subtests) ===================
[12:15:22] ================ xe_live_mocs_kernel_kunit  ================
[12:15:22] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[12:15:22] ================ xe_live_mocs_reset_kunit  =================
[12:15:22] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[12:15:22] ==================== [SKIPPED] xe_mocs =====================
[12:15:22] ================= xe_migrate (2 subtests) ==================
[12:15:22] ================= xe_migrate_sanity_kunit  =================
[12:15:22] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[12:15:22] ================== xe_validate_ccs_kunit  ==================
[12:15:22] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[12:15:22] =================== [SKIPPED] xe_migrate ===================
[12:15:22] ================== xe_dma_buf (1 subtest) ==================
[12:15:22] ==================== xe_dma_buf_kunit  =====================
[12:15:22] ================ [SKIPPED] xe_dma_buf_kunit ================
[12:15:22] =================== [SKIPPED] xe_dma_buf ===================
[12:15:22] ================= xe_bo_shrink (1 subtest) =================
[12:15:22] =================== xe_bo_shrink_kunit  ====================
[12:15:22] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[12:15:22] ================== [SKIPPED] xe_bo_shrink ==================
[12:15:22] ==================== xe_bo (2 subtests) ====================
[12:15:22] ================== xe_ccs_migrate_kunit  ===================
[12:15:22] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[12:15:22] ==================== xe_bo_evict_kunit  ====================
[12:15:22] =============== [SKIPPED] xe_bo_evict_kunit ================
[12:15:22] ===================== [SKIPPED] xe_bo ======================
[12:15:22] ==================== args (13 subtests) ====================
[12:15:22] [PASSED] count_args_test
[12:15:22] [PASSED] call_args_example
[12:15:22] [PASSED] call_args_test
[12:15:22] [PASSED] drop_first_arg_example
[12:15:22] [PASSED] drop_first_arg_test
[12:15:22] [PASSED] first_arg_example
[12:15:22] [PASSED] first_arg_test
[12:15:22] [PASSED] last_arg_example
[12:15:22] [PASSED] last_arg_test
[12:15:22] [PASSED] pick_arg_example
[12:15:22] [PASSED] if_args_example
[12:15:22] [PASSED] if_args_test
[12:15:22] [PASSED] sep_comma_example
[12:15:22] ====================== [PASSED] args =======================
[12:15:22] =================== xe_pci (3 subtests) ====================
[12:15:22] ==================== check_graphics_ip  ====================
[12:15:22] [PASSED] 12.00 Xe_LP
[12:15:22] [PASSED] 12.10 Xe_LP+
[12:15:22] [PASSED] 12.55 Xe_HPG
[12:15:22] [PASSED] 12.60 Xe_HPC
[12:15:22] [PASSED] 12.70 Xe_LPG
[12:15:22] [PASSED] 12.71 Xe_LPG
[12:15:22] [PASSED] 12.74 Xe_LPG+
[12:15:22] [PASSED] 20.01 Xe2_HPG
[12:15:22] [PASSED] 20.02 Xe2_HPG
[12:15:22] [PASSED] 20.04 Xe2_LPG
[12:15:22] [PASSED] 30.00 Xe3_LPG
[12:15:22] [PASSED] 30.01 Xe3_LPG
[12:15:22] [PASSED] 30.03 Xe3_LPG
[12:15:22] [PASSED] 30.04 Xe3_LPG
[12:15:22] [PASSED] 30.05 Xe3_LPG
[12:15:22] [PASSED] 35.10 Xe3p_LPG
[12:15:22] [PASSED] 35.11 Xe3p_XPC
[12:15:22] ================ [PASSED] check_graphics_ip ================
[12:15:22] ===================== check_media_ip  ======================
[12:15:22] [PASSED] 12.00 Xe_M
[12:15:22] [PASSED] 12.55 Xe_HPM
[12:15:22] [PASSED] 13.00 Xe_LPM+
[12:15:22] [PASSED] 13.01 Xe2_HPM
[12:15:22] [PASSED] 20.00 Xe2_LPM
[12:15:22] [PASSED] 30.00 Xe3_LPM
[12:15:22] [PASSED] 30.02 Xe3_LPM
[12:15:22] [PASSED] 35.00 Xe3p_LPM
[12:15:22] [PASSED] 35.03 Xe3p_HPM
[12:15:22] ================= [PASSED] check_media_ip ==================
[12:15:22] =================== check_platform_desc  ===================
[12:15:22] [PASSED] 0x9A60 (TIGERLAKE)
[12:15:22] [PASSED] 0x9A68 (TIGERLAKE)
[12:15:22] [PASSED] 0x9A70 (TIGERLAKE)
[12:15:22] [PASSED] 0x9A40 (TIGERLAKE)
[12:15:22] [PASSED] 0x9A49 (TIGERLAKE)
[12:15:22] [PASSED] 0x9A59 (TIGERLAKE)
[12:15:22] [PASSED] 0x9A78 (TIGERLAKE)
[12:15:22] [PASSED] 0x9AC0 (TIGERLAKE)
[12:15:22] [PASSED] 0x9AC9 (TIGERLAKE)
[12:15:22] [PASSED] 0x9AD9 (TIGERLAKE)
[12:15:22] [PASSED] 0x9AF8 (TIGERLAKE)
[12:15:22] [PASSED] 0x4C80 (ROCKETLAKE)
[12:15:22] [PASSED] 0x4C8A (ROCKETLAKE)
[12:15:22] [PASSED] 0x4C8B (ROCKETLAKE)
[12:15:22] [PASSED] 0x4C8C (ROCKETLAKE)
[12:15:22] [PASSED] 0x4C90 (ROCKETLAKE)
[12:15:22] [PASSED] 0x4C9A (ROCKETLAKE)
[12:15:22] [PASSED] 0x4680 (ALDERLAKE_S)
[12:15:22] [PASSED] 0x4682 (ALDERLAKE_S)
[12:15:22] [PASSED] 0x4688 (ALDERLAKE_S)
[12:15:22] [PASSED] 0x468A (ALDERLAKE_S)
[12:15:22] [PASSED] 0x468B (ALDERLAKE_S)
[12:15:22] [PASSED] 0x4690 (ALDERLAKE_S)
[12:15:22] [PASSED] 0x4692 (ALDERLAKE_S)
[12:15:22] [PASSED] 0x4693 (ALDERLAKE_S)
[12:15:22] [PASSED] 0x46A0 (ALDERLAKE_P)
[12:15:22] [PASSED] 0x46A1 (ALDERLAKE_P)
[12:15:22] [PASSED] 0x46A2 (ALDERLAKE_P)
[12:15:22] [PASSED] 0x46A3 (ALDERLAKE_P)
[12:15:22] [PASSED] 0x46A6 (ALDERLAKE_P)
[12:15:22] [PASSED] 0x46A8 (ALDERLAKE_P)
[12:15:22] [PASSED] 0x46AA (ALDERLAKE_P)
[12:15:22] [PASSED] 0x462A (ALDERLAKE_P)
[12:15:22] [PASSED] 0x4626 (ALDERLAKE_P)
[12:15:22] [PASSED] 0x4628 (ALDERLAKE_P)
[12:15:22] [PASSED] 0x46B0 (ALDERLAKE_P)
[12:15:22] [PASSED] 0x46B1 (ALDERLAKE_P)
[12:15:22] [PASSED] 0x46B2 (ALDERLAKE_P)
[12:15:22] [PASSED] 0x46B3 (ALDERLAKE_P)
[12:15:22] [PASSED] 0x46C0 (ALDERLAKE_P)
[12:15:22] [PASSED] 0x46C1 (ALDERLAKE_P)
[12:15:22] [PASSED] 0x46C2 (ALDERLAKE_P)
[12:15:22] [PASSED] 0x46C3 (ALDERLAKE_P)
[12:15:22] [PASSED] 0x46D0 (ALDERLAKE_N)
[12:15:22] [PASSED] 0x46D1 (ALDERLAKE_N)
[12:15:22] [PASSED] 0x46D2 (ALDERLAKE_N)
[12:15:22] [PASSED] 0x46D3 (ALDERLAKE_N)
[12:15:22] [PASSED] 0x46D4 (ALDERLAKE_N)
[12:15:22] [PASSED] 0xA721 (ALDERLAKE_P)
[12:15:22] [PASSED] 0xA7A1 (ALDERLAKE_P)
[12:15:22] [PASSED] 0xA7A9 (ALDERLAKE_P)
[12:15:22] [PASSED] 0xA7AC (ALDERLAKE_P)
[12:15:22] [PASSED] 0xA7AD (ALDERLAKE_P)
[12:15:22] [PASSED] 0xA720 (ALDERLAKE_P)
[12:15:22] [PASSED] 0xA7A0 (ALDERLAKE_P)
[12:15:22] [PASSED] 0xA7A8 (ALDERLAKE_P)
[12:15:22] [PASSED] 0xA7AA (ALDERLAKE_P)
[12:15:22] [PASSED] 0xA7AB (ALDERLAKE_P)
[12:15:22] [PASSED] 0xA780 (ALDERLAKE_S)
[12:15:22] [PASSED] 0xA781 (ALDERLAKE_S)
[12:15:22] [PASSED] 0xA782 (ALDERLAKE_S)
[12:15:22] [PASSED] 0xA783 (ALDERLAKE_S)
[12:15:22] [PASSED] 0xA788 (ALDERLAKE_S)
[12:15:22] [PASSED] 0xA789 (ALDERLAKE_S)
[12:15:22] [PASSED] 0xA78A (ALDERLAKE_S)
[12:15:22] [PASSED] 0xA78B (ALDERLAKE_S)
[12:15:22] [PASSED] 0x4905 (DG1)
[12:15:22] [PASSED] 0x4906 (DG1)
[12:15:22] [PASSED] 0x4907 (DG1)
[12:15:22] [PASSED] 0x4908 (DG1)
[12:15:22] [PASSED] 0x4909 (DG1)
[12:15:22] [PASSED] 0x56C0 (DG2)
[12:15:22] [PASSED] 0x56C2 (DG2)
[12:15:22] [PASSED] 0x56C1 (DG2)
[12:15:22] [PASSED] 0x7D51 (METEORLAKE)
[12:15:22] [PASSED] 0x7DD1 (METEORLAKE)
[12:15:22] [PASSED] 0x7D41 (METEORLAKE)
[12:15:22] [PASSED] 0x7D67 (METEORLAKE)
[12:15:22] [PASSED] 0xB640 (METEORLAKE)
[12:15:22] [PASSED] 0x56A0 (DG2)
[12:15:22] [PASSED] 0x56A1 (DG2)
[12:15:22] [PASSED] 0x56A2 (DG2)
[12:15:22] [PASSED] 0x56BE (DG2)
[12:15:22] [PASSED] 0x56BF (DG2)
[12:15:22] [PASSED] 0x5690 (DG2)
[12:15:22] [PASSED] 0x5691 (DG2)
[12:15:22] [PASSED] 0x5692 (DG2)
[12:15:22] [PASSED] 0x56A5 (DG2)
[12:15:22] [PASSED] 0x56A6 (DG2)
[12:15:22] [PASSED] 0x56B0 (DG2)
[12:15:22] [PASSED] 0x56B1 (DG2)
[12:15:22] [PASSED] 0x56BA (DG2)
[12:15:22] [PASSED] 0x56BB (DG2)
[12:15:22] [PASSED] 0x56BC (DG2)
[12:15:22] [PASSED] 0x56BD (DG2)
[12:15:22] [PASSED] 0x5693 (DG2)
[12:15:22] [PASSED] 0x5694 (DG2)
[12:15:22] [PASSED] 0x5695 (DG2)
[12:15:22] [PASSED] 0x56A3 (DG2)
[12:15:22] [PASSED] 0x56A4 (DG2)
[12:15:22] [PASSED] 0x56B2 (DG2)
[12:15:22] [PASSED] 0x56B3 (DG2)
[12:15:22] [PASSED] 0x5696 (DG2)
[12:15:22] [PASSED] 0x5697 (DG2)
[12:15:22] [PASSED] 0xB69 (PVC)
[12:15:22] [PASSED] 0xB6E (PVC)
[12:15:22] [PASSED] 0xBD4 (PVC)
[12:15:22] [PASSED] 0xBD5 (PVC)
[12:15:22] [PASSED] 0xBD6 (PVC)
[12:15:22] [PASSED] 0xBD7 (PVC)
[12:15:22] [PASSED] 0xBD8 (PVC)
[12:15:22] [PASSED] 0xBD9 (PVC)
[12:15:22] [PASSED] 0xBDA (PVC)
[12:15:22] [PASSED] 0xBDB (PVC)
[12:15:22] [PASSED] 0xBE0 (PVC)
[12:15:22] [PASSED] 0xBE1 (PVC)
[12:15:22] [PASSED] 0xBE5 (PVC)
[12:15:22] [PASSED] 0x7D40 (METEORLAKE)
[12:15:22] [PASSED] 0x7D45 (METEORLAKE)
[12:15:22] [PASSED] 0x7D55 (METEORLAKE)
[12:15:22] [PASSED] 0x7D60 (METEORLAKE)
[12:15:22] [PASSED] 0x7DD5 (METEORLAKE)
[12:15:22] [PASSED] 0x6420 (LUNARLAKE)
[12:15:22] [PASSED] 0x64A0 (LUNARLAKE)
[12:15:22] [PASSED] 0x64B0 (LUNARLAKE)
[12:15:22] [PASSED] 0xE202 (BATTLEMAGE)
[12:15:22] [PASSED] 0xE209 (BATTLEMAGE)
[12:15:22] [PASSED] 0xE20B (BATTLEMAGE)
[12:15:22] [PASSED] 0xE20C (BATTLEMAGE)
[12:15:22] [PASSED] 0xE20D (BATTLEMAGE)
[12:15:22] [PASSED] 0xE210 (BATTLEMAGE)
[12:15:22] [PASSED] 0xE211 (BATTLEMAGE)
[12:15:22] [PASSED] 0xE212 (BATTLEMAGE)
[12:15:22] [PASSED] 0xE216 (BATTLEMAGE)
[12:15:22] [PASSED] 0xE220 (BATTLEMAGE)
[12:15:22] [PASSED] 0xE221 (BATTLEMAGE)
[12:15:22] [PASSED] 0xE222 (BATTLEMAGE)
[12:15:22] [PASSED] 0xE223 (BATTLEMAGE)
[12:15:22] [PASSED] 0xB080 (PANTHERLAKE)
[12:15:22] [PASSED] 0xB081 (PANTHERLAKE)
[12:15:22] [PASSED] 0xB082 (PANTHERLAKE)
[12:15:22] [PASSED] 0xB083 (PANTHERLAKE)
[12:15:22] [PASSED] 0xB084 (PANTHERLAKE)
[12:15:22] [PASSED] 0xB085 (PANTHERLAKE)
[12:15:22] [PASSED] 0xB086 (PANTHERLAKE)
[12:15:22] [PASSED] 0xB087 (PANTHERLAKE)
[12:15:22] [PASSED] 0xB08F (PANTHERLAKE)
[12:15:22] [PASSED] 0xB090 (PANTHERLAKE)
[12:15:22] [PASSED] 0xB0A0 (PANTHERLAKE)
[12:15:22] [PASSED] 0xB0B0 (PANTHERLAKE)
[12:15:22] [PASSED] 0xFD80 (PANTHERLAKE)
[12:15:22] [PASSED] 0xFD81 (PANTHERLAKE)
[12:15:22] [PASSED] 0xD740 (NOVALAKE_S)
[12:15:22] [PASSED] 0xD741 (NOVALAKE_S)
[12:15:22] [PASSED] 0xD742 (NOVALAKE_S)
[12:15:22] [PASSED] 0xD743 (NOVALAKE_S)
[12:15:22] [PASSED] 0xD744 (NOVALAKE_S)
[12:15:22] [PASSED] 0xD745 (NOVALAKE_S)
[12:15:22] [PASSED] 0x674C (CRESCENTISLAND)
[12:15:22] [PASSED] 0xD750 (NOVALAKE_P)
[12:15:22] [PASSED] 0xD751 (NOVALAKE_P)
[12:15:22] [PASSED] 0xD752 (NOVALAKE_P)
[12:15:22] [PASSED] 0xD753 (NOVALAKE_P)
[12:15:22] [PASSED] 0xD754 (NOVALAKE_P)
[12:15:22] [PASSED] 0xD755 (NOVALAKE_P)
[12:15:22] [PASSED] 0xD756 (NOVALAKE_P)
[12:15:22] [PASSED] 0xD757 (NOVALAKE_P)
[12:15:22] [PASSED] 0xD75F (NOVALAKE_P)
[12:15:22] =============== [PASSED] check_platform_desc ===============
[12:15:22] ===================== [PASSED] xe_pci ======================
[12:15:22] =================== xe_rtp (2 subtests) ====================
[12:15:22] =============== xe_rtp_process_to_sr_tests  ================
[12:15:22] [PASSED] coalesce-same-reg
[12:15:22] [PASSED] no-match-no-add
[12:15:22] [PASSED] match-or
[12:15:22] [PASSED] match-or-xfail
[12:15:22] [PASSED] no-match-no-add-multiple-rules
[12:15:22] [PASSED] two-regs-two-entries
[12:15:22] [PASSED] clr-one-set-other
[12:15:22] [PASSED] set-field
[12:15:22] [PASSED] conflict-duplicate
stty: 'standard input': Inappropriate ioctl for device
[12:15:22] [PASSED] conflict-not-disjoint
[12:15:22] [PASSED] conflict-reg-type
[12:15:22] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[12:15:22] ================== xe_rtp_process_tests  ===================
[12:15:22] [PASSED] active1
[12:15:22] [PASSED] active2
[12:15:22] [PASSED] active-inactive
[12:15:22] [PASSED] inactive-active
[12:15:22] [PASSED] inactive-1st_or_active-inactive
[12:15:22] [PASSED] inactive-2nd_or_active-inactive
[12:15:22] [PASSED] inactive-last_or_active-inactive
[12:15:22] [PASSED] inactive-no_or_active-inactive
[12:15:22] ============== [PASSED] xe_rtp_process_tests ===============
[12:15:22] ===================== [PASSED] xe_rtp ======================
[12:15:22] ==================== xe_wa (1 subtest) =====================
[12:15:22] ======================== xe_wa_gt  =========================
[12:15:22] [PASSED] TIGERLAKE B0
[12:15:22] [PASSED] DG1 A0
[12:15:22] [PASSED] DG1 B0
[12:15:22] [PASSED] ALDERLAKE_S A0
[12:15:22] [PASSED] ALDERLAKE_S B0
[12:15:22] [PASSED] ALDERLAKE_S C0
[12:15:22] [PASSED] ALDERLAKE_S D0
[12:15:22] [PASSED] ALDERLAKE_P A0
[12:15:22] [PASSED] ALDERLAKE_P B0
[12:15:22] [PASSED] ALDERLAKE_P C0
[12:15:22] [PASSED] ALDERLAKE_S RPLS D0
[12:15:22] [PASSED] ALDERLAKE_P RPLU E0
[12:15:22] [PASSED] DG2 G10 C0
[12:15:22] [PASSED] DG2 G11 B1
[12:15:22] [PASSED] DG2 G12 A1
[12:15:22] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[12:15:22] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[12:15:22] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[12:15:22] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[12:15:22] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[12:15:22] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[12:15:22] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[12:15:22] ==================== [PASSED] xe_wa_gt =====================
[12:15:22] ====================== [PASSED] xe_wa ======================
[12:15:22] ============================================================
[12:15:22] Testing complete. Ran 597 tests: passed: 579, skipped: 18
[12:15:22] Elapsed time: 35.460s total, 4.263s configuring, 30.530s building, 0.624s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[12:15:22] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[12:15:24] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[12:15:48] Starting KUnit Kernel (1/1)...
[12:15:48] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[12:15:48] ============ drm_test_pick_cmdline (2 subtests) ============
[12:15:48] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[12:15:48] =============== drm_test_pick_cmdline_named  ===============
[12:15:48] [PASSED] NTSC
[12:15:48] [PASSED] NTSC-J
[12:15:48] [PASSED] PAL
[12:15:48] [PASSED] PAL-M
[12:15:48] =========== [PASSED] drm_test_pick_cmdline_named ===========
[12:15:48] ============== [PASSED] drm_test_pick_cmdline ==============
[12:15:48] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[12:15:48] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[12:15:48] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[12:15:48] =========== drm_validate_clone_mode (2 subtests) ===========
[12:15:48] ============== drm_test_check_in_clone_mode  ===============
[12:15:48] [PASSED] in_clone_mode
[12:15:48] [PASSED] not_in_clone_mode
[12:15:48] ========== [PASSED] drm_test_check_in_clone_mode ===========
[12:15:48] =============== drm_test_check_valid_clones  ===============
[12:15:48] [PASSED] not_in_clone_mode
[12:15:48] [PASSED] valid_clone
[12:15:48] [PASSED] invalid_clone
[12:15:48] =========== [PASSED] drm_test_check_valid_clones ===========
[12:15:48] ============= [PASSED] drm_validate_clone_mode =============
[12:15:48] ============= drm_validate_modeset (1 subtest) =============
[12:15:48] [PASSED] drm_test_check_connector_changed_modeset
[12:15:48] ============== [PASSED] drm_validate_modeset ===============
[12:15:48] ====== drm_test_bridge_get_current_state (2 subtests) ======
[12:15:48] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[12:15:48] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[12:15:48] ======== [PASSED] drm_test_bridge_get_current_state ========
[12:15:48] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[12:15:48] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[12:15:48] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[12:15:48] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[12:15:48] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[12:15:48] ============== drm_bridge_alloc (2 subtests) ===============
[12:15:48] [PASSED] drm_test_drm_bridge_alloc_basic
[12:15:48] [PASSED] drm_test_drm_bridge_alloc_get_put
[12:15:48] ================ [PASSED] drm_bridge_alloc =================
[12:15:48] ============= drm_cmdline_parser (40 subtests) =============
[12:15:48] [PASSED] drm_test_cmdline_force_d_only
[12:15:48] [PASSED] drm_test_cmdline_force_D_only_dvi
[12:15:48] [PASSED] drm_test_cmdline_force_D_only_hdmi
[12:15:48] [PASSED] drm_test_cmdline_force_D_only_not_digital
[12:15:48] [PASSED] drm_test_cmdline_force_e_only
[12:15:48] [PASSED] drm_test_cmdline_res
[12:15:48] [PASSED] drm_test_cmdline_res_vesa
[12:15:48] [PASSED] drm_test_cmdline_res_vesa_rblank
[12:15:48] [PASSED] drm_test_cmdline_res_rblank
[12:15:48] [PASSED] drm_test_cmdline_res_bpp
[12:15:48] [PASSED] drm_test_cmdline_res_refresh
[12:15:48] [PASSED] drm_test_cmdline_res_bpp_refresh
[12:15:48] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[12:15:48] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[12:15:48] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[12:15:48] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[12:15:48] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[12:15:48] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[12:15:48] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[12:15:48] [PASSED] drm_test_cmdline_res_margins_force_on
[12:15:48] [PASSED] drm_test_cmdline_res_vesa_margins
[12:15:48] [PASSED] drm_test_cmdline_name
[12:15:48] [PASSED] drm_test_cmdline_name_bpp
[12:15:48] [PASSED] drm_test_cmdline_name_option
[12:15:48] [PASSED] drm_test_cmdline_name_bpp_option
[12:15:48] [PASSED] drm_test_cmdline_rotate_0
[12:15:48] [PASSED] drm_test_cmdline_rotate_90
[12:15:48] [PASSED] drm_test_cmdline_rotate_180
[12:15:48] [PASSED] drm_test_cmdline_rotate_270
[12:15:48] [PASSED] drm_test_cmdline_hmirror
[12:15:48] [PASSED] drm_test_cmdline_vmirror
[12:15:48] [PASSED] drm_test_cmdline_margin_options
[12:15:48] [PASSED] drm_test_cmdline_multiple_options
[12:15:48] [PASSED] drm_test_cmdline_bpp_extra_and_option
[12:15:48] [PASSED] drm_test_cmdline_extra_and_option
[12:15:48] [PASSED] drm_test_cmdline_freestanding_options
[12:15:48] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[12:15:48] [PASSED] drm_test_cmdline_panel_orientation
[12:15:48] ================ drm_test_cmdline_invalid  =================
[12:15:48] [PASSED] margin_only
[12:15:48] [PASSED] interlace_only
[12:15:48] [PASSED] res_missing_x
[12:15:48] [PASSED] res_missing_y
[12:15:48] [PASSED] res_bad_y
[12:15:48] [PASSED] res_missing_y_bpp
[12:15:48] [PASSED] res_bad_bpp
[12:15:48] [PASSED] res_bad_refresh
[12:15:48] [PASSED] res_bpp_refresh_force_on_off
[12:15:48] [PASSED] res_invalid_mode
[12:15:48] [PASSED] res_bpp_wrong_place_mode
[12:15:48] [PASSED] name_bpp_refresh
[12:15:48] [PASSED] name_refresh
[12:15:48] [PASSED] name_refresh_wrong_mode
[12:15:48] [PASSED] name_refresh_invalid_mode
[12:15:48] [PASSED] rotate_multiple
[12:15:48] [PASSED] rotate_invalid_val
[12:15:48] [PASSED] rotate_truncated
[12:15:48] [PASSED] invalid_option
[12:15:48] [PASSED] invalid_tv_option
[12:15:48] [PASSED] truncated_tv_option
[12:15:48] ============ [PASSED] drm_test_cmdline_invalid =============
[12:15:48] =============== drm_test_cmdline_tv_options  ===============
[12:15:48] [PASSED] NTSC
[12:15:48] [PASSED] NTSC_443
[12:15:48] [PASSED] NTSC_J
[12:15:48] [PASSED] PAL
[12:15:48] [PASSED] PAL_M
[12:15:48] [PASSED] PAL_N
[12:15:48] [PASSED] SECAM
[12:15:48] [PASSED] MONO_525
[12:15:48] [PASSED] MONO_625
[12:15:48] =========== [PASSED] drm_test_cmdline_tv_options ===========
[12:15:48] =============== [PASSED] drm_cmdline_parser ================
[12:15:48] ========== drmm_connector_hdmi_init (20 subtests) ==========
[12:15:48] [PASSED] drm_test_connector_hdmi_init_valid
[12:15:48] [PASSED] drm_test_connector_hdmi_init_bpc_8
[12:15:48] [PASSED] drm_test_connector_hdmi_init_bpc_10
[12:15:48] [PASSED] drm_test_connector_hdmi_init_bpc_12
[12:15:48] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[12:15:48] [PASSED] drm_test_connector_hdmi_init_bpc_null
[12:15:48] [PASSED] drm_test_connector_hdmi_init_formats_empty
[12:15:48] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[12:15:48] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[12:15:48] [PASSED] supported_formats=0x9 yuv420_allowed=1
[12:15:48] [PASSED] supported_formats=0x9 yuv420_allowed=0
[12:15:48] [PASSED] supported_formats=0x3 yuv420_allowed=1
[12:15:48] [PASSED] supported_formats=0x3 yuv420_allowed=0
[12:15:48] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[12:15:48] [PASSED] drm_test_connector_hdmi_init_null_ddc
[12:15:48] [PASSED] drm_test_connector_hdmi_init_null_product
[12:15:48] [PASSED] drm_test_connector_hdmi_init_null_vendor
[12:15:48] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[12:15:48] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[12:15:48] [PASSED] drm_test_connector_hdmi_init_product_valid
[12:15:48] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[12:15:48] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[12:15:48] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[12:15:48] ========= drm_test_connector_hdmi_init_type_valid  =========
[12:15:48] [PASSED] HDMI-A
[12:15:48] [PASSED] HDMI-B
[12:15:48] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[12:15:48] ======== drm_test_connector_hdmi_init_type_invalid  ========
[12:15:48] [PASSED] Unknown
[12:15:48] [PASSED] VGA
[12:15:48] [PASSED] DVI-I
[12:15:48] [PASSED] DVI-D
[12:15:48] [PASSED] DVI-A
[12:15:48] [PASSED] Composite
[12:15:48] [PASSED] SVIDEO
[12:15:48] [PASSED] LVDS
[12:15:48] [PASSED] Component
[12:15:48] [PASSED] DIN
[12:15:48] [PASSED] DP
[12:15:48] [PASSED] TV
[12:15:48] [PASSED] eDP
[12:15:48] [PASSED] Virtual
[12:15:48] [PASSED] DSI
[12:15:48] [PASSED] DPI
[12:15:48] [PASSED] Writeback
[12:15:48] [PASSED] SPI
[12:15:48] [PASSED] USB
[12:15:48] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[12:15:48] ============ [PASSED] drmm_connector_hdmi_init =============
[12:15:48] ============= drmm_connector_init (3 subtests) =============
[12:15:48] [PASSED] drm_test_drmm_connector_init
[12:15:48] [PASSED] drm_test_drmm_connector_init_null_ddc
[12:15:48] ========= drm_test_drmm_connector_init_type_valid  =========
[12:15:48] [PASSED] Unknown
[12:15:48] [PASSED] VGA
[12:15:48] [PASSED] DVI-I
[12:15:48] [PASSED] DVI-D
[12:15:48] [PASSED] DVI-A
[12:15:48] [PASSED] Composite
[12:15:48] [PASSED] SVIDEO
[12:15:48] [PASSED] LVDS
[12:15:48] [PASSED] Component
[12:15:48] [PASSED] DIN
[12:15:48] [PASSED] DP
[12:15:48] [PASSED] HDMI-A
[12:15:48] [PASSED] HDMI-B
[12:15:48] [PASSED] TV
[12:15:48] [PASSED] eDP
[12:15:48] [PASSED] Virtual
[12:15:48] [PASSED] DSI
[12:15:48] [PASSED] DPI
[12:15:48] [PASSED] Writeback
[12:15:48] [PASSED] SPI
[12:15:48] [PASSED] USB
[12:15:48] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[12:15:48] =============== [PASSED] drmm_connector_init ===============
[12:15:48] ========= drm_connector_dynamic_init (6 subtests) ==========
[12:15:48] [PASSED] drm_test_drm_connector_dynamic_init
[12:15:48] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[12:15:48] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[12:15:48] [PASSED] drm_test_drm_connector_dynamic_init_properties
[12:15:48] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[12:15:48] [PASSED] Unknown
[12:15:48] [PASSED] VGA
[12:15:48] [PASSED] DVI-I
[12:15:48] [PASSED] DVI-D
[12:15:48] [PASSED] DVI-A
[12:15:48] [PASSED] Composite
[12:15:48] [PASSED] SVIDEO
[12:15:48] [PASSED] LVDS
[12:15:48] [PASSED] Component
[12:15:48] [PASSED] DIN
[12:15:48] [PASSED] DP
[12:15:48] [PASSED] HDMI-A
[12:15:48] [PASSED] HDMI-B
[12:15:48] [PASSED] TV
[12:15:48] [PASSED] eDP
[12:15:48] [PASSED] Virtual
[12:15:48] [PASSED] DSI
[12:15:48] [PASSED] DPI
[12:15:48] [PASSED] Writeback
[12:15:48] [PASSED] SPI
[12:15:48] [PASSED] USB
[12:15:48] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[12:15:48] ======== drm_test_drm_connector_dynamic_init_name  =========
[12:15:48] [PASSED] Unknown
[12:15:48] [PASSED] VGA
[12:15:48] [PASSED] DVI-I
[12:15:48] [PASSED] DVI-D
[12:15:48] [PASSED] DVI-A
[12:15:48] [PASSED] Composite
[12:15:48] [PASSED] SVIDEO
[12:15:48] [PASSED] LVDS
[12:15:48] [PASSED] Component
[12:15:48] [PASSED] DIN
[12:15:48] [PASSED] DP
[12:15:48] [PASSED] HDMI-A
[12:15:48] [PASSED] HDMI-B
[12:15:48] [PASSED] TV
[12:15:48] [PASSED] eDP
[12:15:48] [PASSED] Virtual
[12:15:48] [PASSED] DSI
[12:15:48] [PASSED] DPI
[12:15:48] [PASSED] Writeback
[12:15:48] [PASSED] SPI
[12:15:48] [PASSED] USB
[12:15:48] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[12:15:48] =========== [PASSED] drm_connector_dynamic_init ============
[12:15:48] ==== drm_connector_dynamic_register_early (4 subtests) =====
[12:15:48] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[12:15:48] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[12:15:48] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[12:15:48] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[12:15:48] ====== [PASSED] drm_connector_dynamic_register_early =======
[12:15:48] ======= drm_connector_dynamic_register (7 subtests) ========
[12:15:48] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[12:15:48] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[12:15:48] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[12:15:48] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[12:15:48] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[12:15:48] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[12:15:48] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[12:15:48] ========= [PASSED] drm_connector_dynamic_register ==========
[12:15:48] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[12:15:48] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[12:15:48] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[12:15:48] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[12:15:48] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[12:15:48] ========== drm_test_get_tv_mode_from_name_valid  ===========
[12:15:48] [PASSED] NTSC
[12:15:48] [PASSED] NTSC-443
[12:15:48] [PASSED] NTSC-J
[12:15:48] [PASSED] PAL
[12:15:48] [PASSED] PAL-M
[12:15:48] [PASSED] PAL-N
[12:15:48] [PASSED] SECAM
[12:15:48] [PASSED] Mono
[12:15:48] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[12:15:48] [PASSED] drm_test_get_tv_mode_from_name_truncated
[12:15:48] ============ [PASSED] drm_get_tv_mode_from_name ============
[12:15:48] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[12:15:48] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[12:15:48] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[12:15:48] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[12:15:48] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[12:15:48] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[12:15:48] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[12:15:48] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[12:15:48] [PASSED] VIC 96
[12:15:48] [PASSED] VIC 97
[12:15:48] [PASSED] VIC 101
[12:15:48] [PASSED] VIC 102
[12:15:48] [PASSED] VIC 106
[12:15:48] [PASSED] VIC 107
[12:15:48] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[12:15:48] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[12:15:48] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[12:15:48] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[12:15:48] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[12:15:48] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[12:15:48] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[12:15:48] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[12:15:48] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[12:15:48] [PASSED] Automatic
[12:15:48] [PASSED] Full
[12:15:48] [PASSED] Limited 16:235
[12:15:48] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[12:15:48] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[12:15:48] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[12:15:48] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[12:15:48] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[12:15:48] [PASSED] RGB
[12:15:48] [PASSED] YUV 4:2:0
[12:15:48] [PASSED] YUV 4:2:2
[12:15:48] [PASSED] YUV 4:4:4
[12:15:48] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[12:15:48] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[12:15:48] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[12:15:48] ============= drm_damage_helper (21 subtests) ==============
[12:15:48] [PASSED] drm_test_damage_iter_no_damage
[12:15:48] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[12:15:48] [PASSED] drm_test_damage_iter_no_damage_src_moved
[12:15:48] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[12:15:48] [PASSED] drm_test_damage_iter_no_damage_not_visible
[12:15:48] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[12:15:48] [PASSED] drm_test_damage_iter_no_damage_no_fb
[12:15:48] [PASSED] drm_test_damage_iter_simple_damage
[12:15:48] [PASSED] drm_test_damage_iter_single_damage
[12:15:48] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[12:15:48] [PASSED] drm_test_damage_iter_single_damage_outside_src
[12:15:48] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[12:15:48] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[12:15:48] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[12:15:48] [PASSED] drm_test_damage_iter_single_damage_src_moved
[12:15:48] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[12:15:48] [PASSED] drm_test_damage_iter_damage
[12:15:48] [PASSED] drm_test_damage_iter_damage_one_intersect
[12:15:48] [PASSED] drm_test_damage_iter_damage_one_outside
[12:15:48] [PASSED] drm_test_damage_iter_damage_src_moved
[12:15:48] [PASSED] drm_test_damage_iter_damage_not_visible
[12:15:48] ================ [PASSED] drm_damage_helper ================
[12:15:48] ============== drm_dp_mst_helper (3 subtests) ==============
[12:15:48] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[12:15:48] [PASSED] Clock 154000 BPP 30 DSC disabled
[12:15:48] [PASSED] Clock 234000 BPP 30 DSC disabled
[12:15:48] [PASSED] Clock 297000 BPP 24 DSC disabled
[12:15:48] [PASSED] Clock 332880 BPP 24 DSC enabled
[12:15:48] [PASSED] Clock 324540 BPP 24 DSC enabled
[12:15:48] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[12:15:48] ============== drm_test_dp_mst_calc_pbn_div  ===============
[12:15:48] [PASSED] Link rate 2000000 lane count 4
[12:15:48] [PASSED] Link rate 2000000 lane count 2
[12:15:48] [PASSED] Link rate 2000000 lane count 1
[12:15:48] [PASSED] Link rate 1350000 lane count 4
[12:15:48] [PASSED] Link rate 1350000 lane count 2
[12:15:48] [PASSED] Link rate 1350000 lane count 1
[12:15:48] [PASSED] Link rate 1000000 lane count 4
[12:15:48] [PASSED] Link rate 1000000 lane count 2
[12:15:48] [PASSED] Link rate 1000000 lane count 1
[12:15:48] [PASSED] Link rate 810000 lane count 4
[12:15:48] [PASSED] Link rate 810000 lane count 2
[12:15:48] [PASSED] Link rate 810000 lane count 1
[12:15:48] [PASSED] Link rate 540000 lane count 4
[12:15:48] [PASSED] Link rate 540000 lane count 2
[12:15:48] [PASSED] Link rate 540000 lane count 1
[12:15:48] [PASSED] Link rate 270000 lane count 4
[12:15:48] [PASSED] Link rate 270000 lane count 2
[12:15:48] [PASSED] Link rate 270000 lane count 1
[12:15:48] [PASSED] Link rate 162000 lane count 4
[12:15:48] [PASSED] Link rate 162000 lane count 2
[12:15:48] [PASSED] Link rate 162000 lane count 1
[12:15:48] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[12:15:48] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[12:15:48] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[12:15:48] [PASSED] DP_POWER_UP_PHY with port number
[12:15:48] [PASSED] DP_POWER_DOWN_PHY with port number
[12:15:48] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[12:15:48] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[12:15:48] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[12:15:48] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[12:15:48] [PASSED] DP_QUERY_PAYLOAD with port number
[12:15:48] [PASSED] DP_QUERY_PAYLOAD with VCPI
[12:15:48] [PASSED] DP_REMOTE_DPCD_READ with port number
[12:15:48] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[12:15:48] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[12:15:48] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[12:15:48] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[12:15:48] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[12:15:48] [PASSED] DP_REMOTE_I2C_READ with port number
[12:15:48] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[12:15:48] [PASSED] DP_REMOTE_I2C_READ with transactions array
[12:15:48] [PASSED] DP_REMOTE_I2C_WRITE with port number
[12:15:48] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[12:15:48] [PASSED] DP_REMOTE_I2C_WRITE with data array
[12:15:48] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[12:15:48] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[12:15:48] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[12:15:48] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[12:15:48] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[12:15:48] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[12:15:48] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[12:15:48] ================ [PASSED] drm_dp_mst_helper ================
[12:15:48] ================== drm_exec (7 subtests) ===================
[12:15:48] [PASSED] sanitycheck
[12:15:48] [PASSED] test_lock
[12:15:48] [PASSED] test_lock_unlock
[12:15:48] [PASSED] test_duplicates
[12:15:48] [PASSED] test_prepare
[12:15:48] [PASSED] test_prepare_array
[12:15:48] [PASSED] test_multiple_loops
[12:15:48] ==================== [PASSED] drm_exec =====================
[12:15:48] =========== drm_format_helper_test (17 subtests) ===========
[12:15:48] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[12:15:48] [PASSED] single_pixel_source_buffer
[12:15:48] [PASSED] single_pixel_clip_rectangle
[12:15:48] [PASSED] well_known_colors
[12:15:48] [PASSED] destination_pitch
[12:15:48] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[12:15:48] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[12:15:48] [PASSED] single_pixel_source_buffer
[12:15:48] [PASSED] single_pixel_clip_rectangle
[12:15:48] [PASSED] well_known_colors
[12:15:48] [PASSED] destination_pitch
[12:15:48] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[12:15:48] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[12:15:48] [PASSED] single_pixel_source_buffer
[12:15:48] [PASSED] single_pixel_clip_rectangle
[12:15:48] [PASSED] well_known_colors
[12:15:48] [PASSED] destination_pitch
[12:15:48] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[12:15:48] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[12:15:48] [PASSED] single_pixel_source_buffer
[12:15:48] [PASSED] single_pixel_clip_rectangle
[12:15:48] [PASSED] well_known_colors
[12:15:48] [PASSED] destination_pitch
[12:15:48] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[12:15:48] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[12:15:48] [PASSED] single_pixel_source_buffer
[12:15:48] [PASSED] single_pixel_clip_rectangle
[12:15:48] [PASSED] well_known_colors
[12:15:48] [PASSED] destination_pitch
[12:15:48] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[12:15:48] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[12:15:48] [PASSED] single_pixel_source_buffer
[12:15:48] [PASSED] single_pixel_clip_rectangle
[12:15:48] [PASSED] well_known_colors
[12:15:48] [PASSED] destination_pitch
[12:15:48] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[12:15:48] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[12:15:48] [PASSED] single_pixel_source_buffer
[12:15:48] [PASSED] single_pixel_clip_rectangle
[12:15:48] [PASSED] well_known_colors
[12:15:48] [PASSED] destination_pitch
[12:15:48] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[12:15:48] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[12:15:48] [PASSED] single_pixel_source_buffer
[12:15:48] [PASSED] single_pixel_clip_rectangle
[12:15:48] [PASSED] well_known_colors
[12:15:48] [PASSED] destination_pitch
[12:15:48] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[12:15:48] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[12:15:48] [PASSED] single_pixel_source_buffer
[12:15:48] [PASSED] single_pixel_clip_rectangle
[12:15:48] [PASSED] well_known_colors
[12:15:48] [PASSED] destination_pitch
[12:15:48] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[12:15:48] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[12:15:48] [PASSED] single_pixel_source_buffer
[12:15:48] [PASSED] single_pixel_clip_rectangle
[12:15:48] [PASSED] well_known_colors
[12:15:48] [PASSED] destination_pitch
[12:15:48] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[12:15:48] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[12:15:48] [PASSED] single_pixel_source_buffer
[12:15:48] [PASSED] single_pixel_clip_rectangle
[12:15:48] [PASSED] well_known_colors
[12:15:48] [PASSED] destination_pitch
[12:15:48] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[12:15:48] ============== drm_test_fb_xrgb8888_to_mono  ===============
[12:15:48] [PASSED] single_pixel_source_buffer
[12:15:48] [PASSED] single_pixel_clip_rectangle
[12:15:48] [PASSED] well_known_colors
[12:15:48] [PASSED] destination_pitch
[12:15:48] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[12:15:48] ==================== drm_test_fb_swab  =====================
[12:15:48] [PASSED] single_pixel_source_buffer
[12:15:48] [PASSED] single_pixel_clip_rectangle
[12:15:48] [PASSED] well_known_colors
[12:15:48] [PASSED] destination_pitch
[12:15:48] ================ [PASSED] drm_test_fb_swab =================
[12:15:48] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[12:15:48] [PASSED] single_pixel_source_buffer
[12:15:48] [PASSED] single_pixel_clip_rectangle
[12:15:48] [PASSED] well_known_colors
[12:15:48] [PASSED] destination_pitch
[12:15:48] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[12:15:48] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[12:15:48] [PASSED] single_pixel_source_buffer
[12:15:48] [PASSED] single_pixel_clip_rectangle
[12:15:48] [PASSED] well_known_colors
[12:15:48] [PASSED] destination_pitch
[12:15:48] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[12:15:48] ================= drm_test_fb_clip_offset  =================
[12:15:48] [PASSED] pass through
[12:15:48] [PASSED] horizontal offset
[12:15:48] [PASSED] vertical offset
[12:15:48] [PASSED] horizontal and vertical offset
[12:15:48] [PASSED] horizontal offset (custom pitch)
[12:15:48] [PASSED] vertical offset (custom pitch)
[12:15:48] [PASSED] horizontal and vertical offset (custom pitch)
[12:15:48] ============= [PASSED] drm_test_fb_clip_offset =============
[12:15:49] =================== drm_test_fb_memcpy  ====================
[12:15:49] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[12:15:49] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[12:15:49] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[12:15:49] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[12:15:49] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[12:15:49] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[12:15:49] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[12:15:49] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[12:15:49] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[12:15:49] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[12:15:49] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[12:15:49] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[12:15:49] =============== [PASSED] drm_test_fb_memcpy ================
[12:15:49] ============= [PASSED] drm_format_helper_test ==============
[12:15:49] ================= drm_format (18 subtests) =================
[12:15:49] [PASSED] drm_test_format_block_width_invalid
[12:15:49] [PASSED] drm_test_format_block_width_one_plane
[12:15:49] [PASSED] drm_test_format_block_width_two_plane
[12:15:49] [PASSED] drm_test_format_block_width_three_plane
[12:15:49] [PASSED] drm_test_format_block_width_tiled
[12:15:49] [PASSED] drm_test_format_block_height_invalid
[12:15:49] [PASSED] drm_test_format_block_height_one_plane
[12:15:49] [PASSED] drm_test_format_block_height_two_plane
[12:15:49] [PASSED] drm_test_format_block_height_three_plane
[12:15:49] [PASSED] drm_test_format_block_height_tiled
[12:15:49] [PASSED] drm_test_format_min_pitch_invalid
[12:15:49] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[12:15:49] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[12:15:49] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[12:15:49] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[12:15:49] [PASSED] drm_test_format_min_pitch_two_plane
[12:15:49] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[12:15:49] [PASSED] drm_test_format_min_pitch_tiled
[12:15:49] =================== [PASSED] drm_format ====================
[12:15:49] ============== drm_framebuffer (10 subtests) ===============
[12:15:49] ========== drm_test_framebuffer_check_src_coords  ==========
[12:15:49] [PASSED] Success: source fits into fb
[12:15:49] [PASSED] Fail: overflowing fb with x-axis coordinate
[12:15:49] [PASSED] Fail: overflowing fb with y-axis coordinate
[12:15:49] [PASSED] Fail: overflowing fb with source width
[12:15:49] [PASSED] Fail: overflowing fb with source height
[12:15:49] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[12:15:49] [PASSED] drm_test_framebuffer_cleanup
[12:15:49] =============== drm_test_framebuffer_create  ===============
[12:15:49] [PASSED] ABGR8888 normal sizes
[12:15:49] [PASSED] ABGR8888 max sizes
[12:15:49] [PASSED] ABGR8888 pitch greater than min required
[12:15:49] [PASSED] ABGR8888 pitch less than min required
[12:15:49] [PASSED] ABGR8888 Invalid width
[12:15:49] [PASSED] ABGR8888 Invalid buffer handle
[12:15:49] [PASSED] No pixel format
[12:15:49] [PASSED] ABGR8888 Width 0
[12:15:49] [PASSED] ABGR8888 Height 0
[12:15:49] [PASSED] ABGR8888 Out of bound height * pitch combination
[12:15:49] [PASSED] ABGR8888 Large buffer offset
[12:15:49] [PASSED] ABGR8888 Buffer offset for inexistent plane
[12:15:49] [PASSED] ABGR8888 Invalid flag
[12:15:49] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[12:15:49] [PASSED] ABGR8888 Valid buffer modifier
[12:15:49] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[12:15:49] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[12:15:49] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[12:15:49] [PASSED] NV12 Normal sizes
[12:15:49] [PASSED] NV12 Max sizes
[12:15:49] [PASSED] NV12 Invalid pitch
[12:15:49] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[12:15:49] [PASSED] NV12 different  modifier per-plane
[12:15:49] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[12:15:49] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[12:15:49] [PASSED] NV12 Modifier for inexistent plane
[12:15:49] [PASSED] NV12 Handle for inexistent plane
[12:15:49] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[12:15:49] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[12:15:49] [PASSED] YVU420 Normal sizes
[12:15:49] [PASSED] YVU420 Max sizes
[12:15:49] [PASSED] YVU420 Invalid pitch
[12:15:49] [PASSED] YVU420 Different pitches
[12:15:49] [PASSED] YVU420 Different buffer offsets/pitches
[12:15:49] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[12:15:49] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[12:15:49] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[12:15:49] [PASSED] YVU420 Valid modifier
[12:15:49] [PASSED] YVU420 Different modifiers per plane
[12:15:49] [PASSED] YVU420 Modifier for inexistent plane
[12:15:49] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[12:15:49] [PASSED] X0L2 Normal sizes
[12:15:49] [PASSED] X0L2 Max sizes
[12:15:49] [PASSED] X0L2 Invalid pitch
[12:15:49] [PASSED] X0L2 Pitch greater than minimum required
[12:15:49] [PASSED] X0L2 Handle for inexistent plane
[12:15:49] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[12:15:49] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[12:15:49] [PASSED] X0L2 Valid modifier
[12:15:49] [PASSED] X0L2 Modifier for inexistent plane
[12:15:49] =========== [PASSED] drm_test_framebuffer_create ===========
[12:15:49] [PASSED] drm_test_framebuffer_free
[12:15:49] [PASSED] drm_test_framebuffer_init
[12:15:49] [PASSED] drm_test_framebuffer_init_bad_format
[12:15:49] [PASSED] drm_test_framebuffer_init_dev_mismatch
[12:15:49] [PASSED] drm_test_framebuffer_lookup
[12:15:49] [PASSED] drm_test_framebuffer_lookup_inexistent
[12:15:49] [PASSED] drm_test_framebuffer_modifiers_not_supported
[12:15:49] ================= [PASSED] drm_framebuffer =================
[12:15:49] ================ drm_gem_shmem (8 subtests) ================
[12:15:49] [PASSED] drm_gem_shmem_test_obj_create
[12:15:49] [PASSED] drm_gem_shmem_test_obj_create_private
[12:15:49] [PASSED] drm_gem_shmem_test_pin_pages
[12:15:49] [PASSED] drm_gem_shmem_test_vmap
[12:15:49] [PASSED] drm_gem_shmem_test_get_sg_table
[12:15:49] [PASSED] drm_gem_shmem_test_get_pages_sgt
[12:15:49] [PASSED] drm_gem_shmem_test_madvise
[12:15:49] [PASSED] drm_gem_shmem_test_purge
[12:15:49] ================== [PASSED] drm_gem_shmem ==================
[12:15:49] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[12:15:49] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[12:15:49] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[12:15:49] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[12:15:49] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[12:15:49] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[12:15:49] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[12:15:49] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[12:15:49] [PASSED] Automatic
[12:15:49] [PASSED] Full
[12:15:49] [PASSED] Limited 16:235
[12:15:49] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[12:15:49] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[12:15:49] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[12:15:49] [PASSED] drm_test_check_disable_connector
[12:15:49] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[12:15:49] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[12:15:49] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[12:15:49] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[12:15:49] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[12:15:49] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[12:15:49] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[12:15:49] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[12:15:49] [PASSED] drm_test_check_output_bpc_dvi
[12:15:49] [PASSED] drm_test_check_output_bpc_format_vic_1
[12:15:49] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[12:15:49] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[12:15:49] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[12:15:49] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[12:15:49] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[12:15:49] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[12:15:49] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[12:15:49] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[12:15:49] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[12:15:49] [PASSED] drm_test_check_broadcast_rgb_value
[12:15:49] [PASSED] drm_test_check_bpc_8_value
[12:15:49] [PASSED] drm_test_check_bpc_10_value
[12:15:49] [PASSED] drm_test_check_bpc_12_value
[12:15:49] [PASSED] drm_test_check_format_value
[12:15:49] [PASSED] drm_test_check_tmds_char_value
[12:15:49] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[12:15:49] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[12:15:49] [PASSED] drm_test_check_mode_valid
[12:15:49] [PASSED] drm_test_check_mode_valid_reject
[12:15:49] [PASSED] drm_test_check_mode_valid_reject_rate
[12:15:49] [PASSED] drm_test_check_mode_valid_reject_max_clock
[12:15:49] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[12:15:49] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[12:15:49] [PASSED] drm_test_check_infoframes
[12:15:49] [PASSED] drm_test_check_reject_avi_infoframe
[12:15:49] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[12:15:49] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[12:15:49] [PASSED] drm_test_check_reject_audio_infoframe
[12:15:49] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[12:15:49] ================= drm_managed (2 subtests) =================
[12:15:49] [PASSED] drm_test_managed_release_action
[12:15:49] [PASSED] drm_test_managed_run_action
[12:15:49] =================== [PASSED] drm_managed ===================
[12:15:49] =================== drm_mm (6 subtests) ====================
[12:15:49] [PASSED] drm_test_mm_init
[12:15:49] [PASSED] drm_test_mm_debug
[12:15:49] [PASSED] drm_test_mm_align32
[12:15:49] [PASSED] drm_test_mm_align64
[12:15:49] [PASSED] drm_test_mm_lowest
[12:15:49] [PASSED] drm_test_mm_highest
[12:15:49] ===================== [PASSED] drm_mm ======================
[12:15:49] ============= drm_modes_analog_tv (5 subtests) =============
[12:15:49] [PASSED] drm_test_modes_analog_tv_mono_576i
[12:15:49] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[12:15:49] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[12:15:49] [PASSED] drm_test_modes_analog_tv_pal_576i
[12:15:49] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[12:15:49] =============== [PASSED] drm_modes_analog_tv ===============
[12:15:49] ============== drm_plane_helper (2 subtests) ===============
[12:15:49] =============== drm_test_check_plane_state  ================
[12:15:49] [PASSED] clipping_simple
[12:15:49] [PASSED] clipping_rotate_reflect
[12:15:49] [PASSED] positioning_simple
[12:15:49] [PASSED] upscaling
[12:15:49] [PASSED] downscaling
[12:15:49] [PASSED] rounding1
[12:15:49] [PASSED] rounding2
[12:15:49] [PASSED] rounding3
[12:15:49] [PASSED] rounding4
[12:15:49] =========== [PASSED] drm_test_check_plane_state ============
[12:15:49] =========== drm_test_check_invalid_plane_state  ============
[12:15:49] [PASSED] positioning_invalid
[12:15:49] [PASSED] upscaling_invalid
[12:15:49] [PASSED] downscaling_invalid
[12:15:49] ======= [PASSED] drm_test_check_invalid_plane_state ========
[12:15:49] ================ [PASSED] drm_plane_helper =================
[12:15:49] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[12:15:49] ====== drm_test_connector_helper_tv_get_modes_check  =======
[12:15:49] [PASSED] None
[12:15:49] [PASSED] PAL
[12:15:49] [PASSED] NTSC
[12:15:49] [PASSED] Both, NTSC Default
[12:15:49] [PASSED] Both, PAL Default
[12:15:49] [PASSED] Both, NTSC Default, with PAL on command-line
[12:15:49] [PASSED] Both, PAL Default, with NTSC on command-line
[12:15:49] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[12:15:49] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[12:15:49] ================== drm_rect (9 subtests) ===================
[12:15:49] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[12:15:49] [PASSED] drm_test_rect_clip_scaled_not_clipped
[12:15:49] [PASSED] drm_test_rect_clip_scaled_clipped
[12:15:49] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[12:15:49] ================= drm_test_rect_intersect  =================
[12:15:49] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[12:15:49] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[12:15:49] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[12:15:49] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[12:15:49] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[12:15:49] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[12:15:49] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[12:15:49] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[12:15:49] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[12:15:49] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[12:15:49] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[12:15:49] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[12:15:49] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[12:15:49] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[12:15:49] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[12:15:49] ============= [PASSED] drm_test_rect_intersect =============
[12:15:49] ================ drm_test_rect_calc_hscale  ================
[12:15:49] [PASSED] normal use
[12:15:49] [PASSED] out of max range
[12:15:49] [PASSED] out of min range
[12:15:49] [PASSED] zero dst
[12:15:49] [PASSED] negative src
[12:15:49] [PASSED] negative dst
[12:15:49] ============ [PASSED] drm_test_rect_calc_hscale ============
[12:15:49] ================ drm_test_rect_calc_vscale  ================
[12:15:49] [PASSED] normal use
[12:15:49] [PASSED] out of max range
[12:15:49] [PASSED] out of min range
[12:15:49] [PASSED] zero dst
[12:15:49] [PASSED] negative src
[12:15:49] [PASSED] negative dst
stty: 'standard input': Inappropriate ioctl for device
[12:15:49] ============ [PASSED] drm_test_rect_calc_vscale ============
[12:15:49] ================== drm_test_rect_rotate  ===================
[12:15:49] [PASSED] reflect-x
[12:15:49] [PASSED] reflect-y
[12:15:49] [PASSED] rotate-0
[12:15:49] [PASSED] rotate-90
[12:15:49] [PASSED] rotate-180
[12:15:49] [PASSED] rotate-270
[12:15:49] ============== [PASSED] drm_test_rect_rotate ===============
[12:15:49] ================ drm_test_rect_rotate_inv  =================
[12:15:49] [PASSED] reflect-x
[12:15:49] [PASSED] reflect-y
[12:15:49] [PASSED] rotate-0
[12:15:49] [PASSED] rotate-90
[12:15:49] [PASSED] rotate-180
[12:15:49] [PASSED] rotate-270
[12:15:49] ============ [PASSED] drm_test_rect_rotate_inv =============
[12:15:49] ==================== [PASSED] drm_rect =====================
[12:15:49] ============ drm_sysfb_modeset_test (1 subtest) ============
[12:15:49] ============ drm_test_sysfb_build_fourcc_list  =============
[12:15:49] [PASSED] no native formats
[12:15:49] [PASSED] XRGB8888 as native format
[12:15:49] [PASSED] remove duplicates
[12:15:49] [PASSED] convert alpha formats
[12:15:49] [PASSED] random formats
[12:15:49] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[12:15:49] ============= [PASSED] drm_sysfb_modeset_test ==============
[12:15:49] ================== drm_fixp (2 subtests) ===================
[12:15:49] [PASSED] drm_test_int2fixp
[12:15:49] [PASSED] drm_test_sm2fixp
[12:15:49] ==================== [PASSED] drm_fixp =====================
[12:15:49] ============================================================
[12:15:49] Testing complete. Ran 621 tests: passed: 621
[12:15:49] Elapsed time: 26.087s total, 1.737s configuring, 24.182s building, 0.166s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[12:15:49] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[12:15:50] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[12:16:00] Starting KUnit Kernel (1/1)...
[12:16:00] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[12:16:00] ================= ttm_device (5 subtests) ==================
[12:16:00] [PASSED] ttm_device_init_basic
[12:16:00] [PASSED] ttm_device_init_multiple
[12:16:00] [PASSED] ttm_device_fini_basic
[12:16:00] [PASSED] ttm_device_init_no_vma_man
[12:16:00] ================== ttm_device_init_pools  ==================
[12:16:00] [PASSED] No DMA allocations, no DMA32 required
[12:16:00] [PASSED] DMA allocations, DMA32 required
[12:16:00] [PASSED] No DMA allocations, DMA32 required
[12:16:00] [PASSED] DMA allocations, no DMA32 required
[12:16:00] ============== [PASSED] ttm_device_init_pools ==============
[12:16:00] =================== [PASSED] ttm_device ====================
[12:16:00] ================== ttm_pool (8 subtests) ===================
[12:16:00] ================== ttm_pool_alloc_basic  ===================
[12:16:00] [PASSED] One page
[12:16:00] [PASSED] More than one page
[12:16:00] [PASSED] Above the allocation limit
[12:16:00] [PASSED] One page, with coherent DMA mappings enabled
[12:16:00] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[12:16:00] ============== [PASSED] ttm_pool_alloc_basic ===============
[12:16:00] ============== ttm_pool_alloc_basic_dma_addr  ==============
[12:16:00] [PASSED] One page
[12:16:00] [PASSED] More than one page
[12:16:00] [PASSED] Above the allocation limit
[12:16:00] [PASSED] One page, with coherent DMA mappings enabled
[12:16:00] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[12:16:00] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[12:16:00] [PASSED] ttm_pool_alloc_order_caching_match
[12:16:00] [PASSED] ttm_pool_alloc_caching_mismatch
[12:16:00] [PASSED] ttm_pool_alloc_order_mismatch
[12:16:00] [PASSED] ttm_pool_free_dma_alloc
[12:16:00] [PASSED] ttm_pool_free_no_dma_alloc
[12:16:00] [PASSED] ttm_pool_fini_basic
[12:16:00] ==================== [PASSED] ttm_pool =====================
[12:16:00] ================ ttm_resource (8 subtests) =================
[12:16:00] ================= ttm_resource_init_basic  =================
[12:16:00] [PASSED] Init resource in TTM_PL_SYSTEM
[12:16:00] [PASSED] Init resource in TTM_PL_VRAM
[12:16:00] [PASSED] Init resource in a private placement
[12:16:00] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[12:16:00] ============= [PASSED] ttm_resource_init_basic =============
[12:16:00] [PASSED] ttm_resource_init_pinned
[12:16:00] [PASSED] ttm_resource_fini_basic
[12:16:00] [PASSED] ttm_resource_manager_init_basic
[12:16:00] [PASSED] ttm_resource_manager_usage_basic
[12:16:00] [PASSED] ttm_resource_manager_set_used_basic
[12:16:00] [PASSED] ttm_sys_man_alloc_basic
[12:16:00] [PASSED] ttm_sys_man_free_basic
[12:16:00] ================== [PASSED] ttm_resource ===================
[12:16:00] =================== ttm_tt (15 subtests) ===================
[12:16:00] ==================== ttm_tt_init_basic  ====================
[12:16:00] [PASSED] Page-aligned size
[12:16:00] [PASSED] Extra pages requested
[12:16:00] ================ [PASSED] ttm_tt_init_basic ================
[12:16:00] [PASSED] ttm_tt_init_misaligned
[12:16:00] [PASSED] ttm_tt_fini_basic
[12:16:00] [PASSED] ttm_tt_fini_sg
[12:16:00] [PASSED] ttm_tt_fini_shmem
[12:16:00] [PASSED] ttm_tt_create_basic
[12:16:00] [PASSED] ttm_tt_create_invalid_bo_type
[12:16:00] [PASSED] ttm_tt_create_ttm_exists
[12:16:00] [PASSED] ttm_tt_create_failed
[12:16:00] [PASSED] ttm_tt_destroy_basic
[12:16:00] [PASSED] ttm_tt_populate_null_ttm
[12:16:00] [PASSED] ttm_tt_populate_populated_ttm
[12:16:00] [PASSED] ttm_tt_unpopulate_basic
[12:16:00] [PASSED] ttm_tt_unpopulate_empty_ttm
[12:16:00] [PASSED] ttm_tt_swapin_basic
[12:16:00] ===================== [PASSED] ttm_tt ======================
[12:16:00] =================== ttm_bo (14 subtests) ===================
[12:16:00] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[12:16:00] [PASSED] Cannot be interrupted and sleeps
[12:16:00] [PASSED] Cannot be interrupted, locks straight away
[12:16:00] [PASSED] Can be interrupted, sleeps
[12:16:00] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[12:16:00] [PASSED] ttm_bo_reserve_locked_no_sleep
[12:16:00] [PASSED] ttm_bo_reserve_no_wait_ticket
[12:16:00] [PASSED] ttm_bo_reserve_double_resv
[12:16:00] [PASSED] ttm_bo_reserve_interrupted
[12:16:00] [PASSED] ttm_bo_reserve_deadlock
[12:16:00] [PASSED] ttm_bo_unreserve_basic
[12:16:00] [PASSED] ttm_bo_unreserve_pinned
[12:16:00] [PASSED] ttm_bo_unreserve_bulk
[12:16:00] [PASSED] ttm_bo_fini_basic
[12:16:00] [PASSED] ttm_bo_fini_shared_resv
[12:16:00] [PASSED] ttm_bo_pin_basic
[12:16:00] [PASSED] ttm_bo_pin_unpin_resource
[12:16:00] [PASSED] ttm_bo_multiple_pin_one_unpin
[12:16:00] ===================== [PASSED] ttm_bo ======================
[12:16:00] ============== ttm_bo_validate (21 subtests) ===============
[12:16:00] ============== ttm_bo_init_reserved_sys_man  ===============
[12:16:00] [PASSED] Buffer object for userspace
[12:16:00] [PASSED] Kernel buffer object
[12:16:00] [PASSED] Shared buffer object
[12:16:00] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[12:16:00] ============== ttm_bo_init_reserved_mock_man  ==============
[12:16:00] [PASSED] Buffer object for userspace
[12:16:00] [PASSED] Kernel buffer object
[12:16:00] [PASSED] Shared buffer object
[12:16:00] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[12:16:00] [PASSED] ttm_bo_init_reserved_resv
[12:16:00] ================== ttm_bo_validate_basic  ==================
[12:16:00] [PASSED] Buffer object for userspace
[12:16:00] [PASSED] Kernel buffer object
[12:16:00] [PASSED] Shared buffer object
[12:16:00] ============== [PASSED] ttm_bo_validate_basic ==============
[12:16:00] [PASSED] ttm_bo_validate_invalid_placement
[12:16:00] ============= ttm_bo_validate_same_placement  ==============
[12:16:00] [PASSED] System manager
[12:16:00] [PASSED] VRAM manager
[12:16:00] ========= [PASSED] ttm_bo_validate_same_placement ==========
[12:16:00] [PASSED] ttm_bo_validate_failed_alloc
[12:16:00] [PASSED] ttm_bo_validate_pinned
[12:16:00] [PASSED] ttm_bo_validate_busy_placement
[12:16:00] ================ ttm_bo_validate_multihop  =================
[12:16:00] [PASSED] Buffer object for userspace
[12:16:00] [PASSED] Kernel buffer object
[12:16:00] [PASSED] Shared buffer object
[12:16:00] ============ [PASSED] ttm_bo_validate_multihop =============
[12:16:00] ========== ttm_bo_validate_no_placement_signaled  ==========
[12:16:00] [PASSED] Buffer object in system domain, no page vector
[12:16:00] [PASSED] Buffer object in system domain with an existing page vector
[12:16:00] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[12:16:00] ======== ttm_bo_validate_no_placement_not_signaled  ========
[12:16:00] [PASSED] Buffer object for userspace
[12:16:00] [PASSED] Kernel buffer object
[12:16:00] [PASSED] Shared buffer object
[12:16:00] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[12:16:00] [PASSED] ttm_bo_validate_move_fence_signaled
[12:16:00] ========= ttm_bo_validate_move_fence_not_signaled  =========
[12:16:00] [PASSED] Waits for GPU
[12:16:00] [PASSED] Tries to lock straight away
[12:16:00] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[12:16:00] [PASSED] ttm_bo_validate_happy_evict
[12:16:00] [PASSED] ttm_bo_validate_all_pinned_evict
[12:16:00] [PASSED] ttm_bo_validate_allowed_only_evict
[12:16:00] [PASSED] ttm_bo_validate_deleted_evict
[12:16:00] [PASSED] ttm_bo_validate_busy_domain_evict
[12:16:00] [PASSED] ttm_bo_validate_evict_gutting
[12:16:00] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[12:16:00] ================= [PASSED] ttm_bo_validate =================
[12:16:00] ============================================================
[12:16:00] Testing complete. Ran 101 tests: passed: 101
[12:16:00] Elapsed time: 11.335s total, 1.719s configuring, 9.400s building, 0.187s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for drm/xe/xe3p_lpg: L2 flush optimization (rev7)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 959 bytes --]

== Series Details ==

Series: drm/xe/xe3p_lpg: L2 flush optimization (rev7)
URL   : https://patchwork.freedesktop.org/series/158017/
State : success

== Summary ==

CI Bug Log - changes from xe-4674-a48305e6a2e6a1ed90df374101dd29542c105d8f_BAT -> xe-pw-158017v7_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (15 -> 15)
------------------------------

  No changes in participating hosts


Changes
-------

  No changes found


Build changes
-------------

  * Linux: xe-4674-a48305e6a2e6a1ed90df374101dd29542c105d8f -> xe-pw-158017v7

  IGT_8782: eac3b04d1f76b82ac3a183fb293c44e9185d8dba @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-4674-a48305e6a2e6a1ed90df374101dd29542c105d8f: a48305e6a2e6a1ed90df374101dd29542c105d8f
  xe-pw-158017v7: 158017v7

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v7/index.html

[-- Attachment #2: Type: text/html, Size: 1507 bytes --]

✓ Xe.CI.FULL: success for drm/xe/xe3p_lpg: L2 flush optimization (rev7)

[Patchwork]

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== Series Details ==

Series: drm/xe/xe3p_lpg: L2 flush optimization (rev7)
URL   : https://patchwork.freedesktop.org/series/158017/
State : success

== Summary ==

CI Bug Log - changes from xe-4674-a48305e6a2e6a1ed90df374101dd29542c105d8f_FULL -> xe-pw-158017v7_FULL
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-158017v7_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_async_flips@alternate-sync-async-flip-atomic:
    - shard-bmg:          [PASS][1] -> [FAIL][2] ([Intel XE#3718] / [Intel XE#6078]) +1 other test fail
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4674-a48305e6a2e6a1ed90df374101dd29542c105d8f/shard-bmg-9/igt@kms_async_flips@alternate-sync-async-flip-atomic.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v7/shard-bmg-1/igt@kms_async_flips@alternate-sync-async-flip-atomic.html

  * igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-d-dp-2:
    - shard-bmg:          [PASS][3] -> [FAIL][4] ([Intel XE#6078])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4674-a48305e6a2e6a1ed90df374101dd29542c105d8f/shard-bmg-9/igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-d-dp-2.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v7/shard-bmg-1/igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-d-dp-2.html

  * igt@kms_big_fb@4-tiled-32bpp-rotate-90:
    - shard-bmg:          NOTRUN -> [SKIP][5] ([Intel XE#2327]) +2 other tests skip
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v7/shard-bmg-5/igt@kms_big_fb@4-tiled-32bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-32bpp-rotate-180:
    - shard-bmg:          NOTRUN -> [SKIP][6] ([Intel XE#1124]) +1 other test skip
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v7/shard-bmg-5/igt@kms_big_fb@yf-tiled-32bpp-rotate-180.html

  * igt@kms_bw@linear-tiling-3-displays-2160x1440p:
    - shard-bmg:          NOTRUN -> [SKIP][7] ([Intel XE#367] / [Intel XE#7354])
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v7/shard-bmg-5/igt@kms_bw@linear-tiling-3-displays-2160x1440p.html

  * igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs-cc:
    - shard-bmg:          NOTRUN -> [SKIP][8] ([Intel XE#2887]) +2 other tests skip
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v7/shard-bmg-5/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs-cc.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][9] ([Intel XE#3432]) +1 other test skip
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v7/shard-bmg-1/igt@kms_ccs@crc-primary-suspend-y-tiled-ccs.html

  * igt@kms_chamelium_frames@hdmi-aspect-ratio:
    - shard-bmg:          NOTRUN -> [SKIP][10] ([Intel XE#2252]) +1 other test skip
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v7/shard-bmg-5/igt@kms_chamelium_frames@hdmi-aspect-ratio.html

  * igt@kms_cursor_crc@cursor-rapid-movement-128x42:
    - shard-bmg:          NOTRUN -> [SKIP][11] ([Intel XE#2320])
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v7/shard-bmg-5/igt@kms_cursor_crc@cursor-rapid-movement-128x42.html

  * igt@kms_feature_discovery@chamelium:
    - shard-bmg:          NOTRUN -> [SKIP][12] ([Intel XE#2372] / [Intel XE#7359])
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v7/shard-bmg-5/igt@kms_feature_discovery@chamelium.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling:
    - shard-bmg:          NOTRUN -> [SKIP][13] ([Intel XE#7178] / [Intel XE#7351])
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v7/shard-bmg-5/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][14] ([Intel XE#2311]) +7 other tests skip
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v7/shard-bmg-5/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][15] ([Intel XE#4141])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v7/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-abgr161616f-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][16] ([Intel XE#7061] / [Intel XE#7356])
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v7/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcdrrs-abgr161616f-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-2p-pri-indfb-multidraw:
    - shard-bmg:          NOTRUN -> [SKIP][17] ([Intel XE#2313]) +7 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v7/shard-bmg-5/igt@kms_frontbuffer_tracking@psr-2p-pri-indfb-multidraw.html

  * igt@kms_plane@pixel-format-y-tiled-modifier-source-clamping:
    - shard-bmg:          NOTRUN -> [SKIP][18] ([Intel XE#7283]) +1 other test skip
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v7/shard-bmg-5/igt@kms_plane@pixel-format-y-tiled-modifier-source-clamping.html

  * igt@kms_pm_rpm@dpms-lpsp:
    - shard-bmg:          NOTRUN -> [SKIP][19] ([Intel XE#1439] / [Intel XE#3141] / [Intel XE#7383] / [Intel XE#836])
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v7/shard-bmg-5/igt@kms_pm_rpm@dpms-lpsp.html

  * igt@kms_psr2_sf@fbc-pr-overlay-plane-update-sf-dmg-area:
    - shard-bmg:          NOTRUN -> [SKIP][20] ([Intel XE#1489]) +1 other test skip
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v7/shard-bmg-5/igt@kms_psr2_sf@fbc-pr-overlay-plane-update-sf-dmg-area.html

  * igt@kms_psr@psr2-no-drrs:
    - shard-bmg:          NOTRUN -> [SKIP][21] ([Intel XE#2234] / [Intel XE#2850]) +3 other tests skip
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v7/shard-bmg-5/igt@kms_psr@psr2-no-drrs.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-180:
    - shard-bmg:          NOTRUN -> [SKIP][22] ([Intel XE#2330] / [Intel XE#5813])
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v7/shard-bmg-5/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html

  * igt@kms_setmode@basic@pipe-b-hdmi-a-3:
    - shard-bmg:          [PASS][23] -> [FAIL][24] ([Intel XE#6361])
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4674-a48305e6a2e6a1ed90df374101dd29542c105d8f/shard-bmg-9/igt@kms_setmode@basic@pipe-b-hdmi-a-3.html
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v7/shard-bmg-1/igt@kms_setmode@basic@pipe-b-hdmi-a-3.html

  * igt@kms_sharpness_filter@filter-scaler-downscale:
    - shard-bmg:          NOTRUN -> [SKIP][25] ([Intel XE#6503])
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v7/shard-bmg-5/igt@kms_sharpness_filter@filter-scaler-downscale.html

  * igt@xe_eudebug@basic-vm-bind-extended-discovery:
    - shard-bmg:          NOTRUN -> [SKIP][26] ([Intel XE#4837])
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v7/shard-bmg-5/igt@xe_eudebug@basic-vm-bind-extended-discovery.html

  * igt@xe_eudebug_online@pagefault-read-stress:
    - shard-lnl:          NOTRUN -> [SKIP][27] ([Intel XE#6665])
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v7/shard-lnl-4/igt@xe_eudebug_online@pagefault-read-stress.html

  * igt@xe_eudebug_online@single-step:
    - shard-bmg:          NOTRUN -> [SKIP][28] ([Intel XE#4837] / [Intel XE#6665]) +1 other test skip
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v7/shard-bmg-5/igt@xe_eudebug_online@single-step.html

  * igt@xe_eudebug_sriov@deny-sriov:
    - shard-bmg:          NOTRUN -> [SKIP][29] ([Intel XE#5793] / [Intel XE#7320] / [Intel XE#7464])
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v7/shard-bmg-5/igt@xe_eudebug_sriov@deny-sriov.html

  * igt@xe_evict@evict-mixed-many-threads-small:
    - shard-bmg:          [PASS][30] -> [INCOMPLETE][31] ([Intel XE#6321])
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4674-a48305e6a2e6a1ed90df374101dd29542c105d8f/shard-bmg-6/igt@xe_evict@evict-mixed-many-threads-small.html
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v7/shard-bmg-10/igt@xe_evict@evict-mixed-many-threads-small.html

  * igt@xe_exec_balancer@many-virtual-userptr-invalidate-race:
    - shard-lnl:          NOTRUN -> [SKIP][32] ([Intel XE#7482])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v7/shard-lnl-4/igt@xe_exec_balancer@many-virtual-userptr-invalidate-race.html

  * igt@xe_exec_basic@multigpu-once-basic-defer-bind:
    - shard-bmg:          NOTRUN -> [SKIP][33] ([Intel XE#2322] / [Intel XE#7372]) +2 other tests skip
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v7/shard-bmg-5/igt@xe_exec_basic@multigpu-once-basic-defer-bind.html

  * igt@xe_exec_fault_mode@many-execqueues-multi-queue-userptr-invalidate:
    - shard-lnl:          NOTRUN -> [SKIP][34] ([Intel XE#7136])
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v7/shard-lnl-4/igt@xe_exec_fault_mode@many-execqueues-multi-queue-userptr-invalidate.html

  * igt@xe_exec_fault_mode@twice-multi-queue-userptr-invalidate-race:
    - shard-bmg:          NOTRUN -> [SKIP][35] ([Intel XE#7136]) +2 other tests skip
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v7/shard-bmg-5/igt@xe_exec_fault_mode@twice-multi-queue-userptr-invalidate-race.html

  * igt@xe_exec_multi_queue@few-execs-preempt-mode-close-fd-smem:
    - shard-bmg:          NOTRUN -> [SKIP][36] ([Intel XE#6874]) +6 other tests skip
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v7/shard-bmg-5/igt@xe_exec_multi_queue@few-execs-preempt-mode-close-fd-smem.html

  * igt@xe_exec_threads@threads-multi-queue-cm-fd-userptr-rebind:
    - shard-bmg:          NOTRUN -> [SKIP][37] ([Intel XE#7138]) +1 other test skip
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v7/shard-bmg-5/igt@xe_exec_threads@threads-multi-queue-cm-fd-userptr-rebind.html

  * igt@xe_exec_threads@threads-multi-queue-userptr-rebind-err:
    - shard-lnl:          NOTRUN -> [SKIP][38] ([Intel XE#7138])
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v7/shard-lnl-4/igt@xe_exec_threads@threads-multi-queue-userptr-rebind-err.html

  * igt@xe_media_fill@media-fill:
    - shard-bmg:          NOTRUN -> [SKIP][39] ([Intel XE#2459] / [Intel XE#2596] / [Intel XE#7321] / [Intel XE#7453])
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v7/shard-bmg-5/igt@xe_media_fill@media-fill.html

  * igt@xe_mmap@vram:
    - shard-lnl:          NOTRUN -> [SKIP][40] ([Intel XE#1416])
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v7/shard-lnl-4/igt@xe_mmap@vram.html

  * igt@xe_multigpu_svm@mgpu-migration-basic:
    - shard-bmg:          NOTRUN -> [SKIP][41] ([Intel XE#6964])
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v7/shard-bmg-5/igt@xe_multigpu_svm@mgpu-migration-basic.html

  * igt@xe_pat@pat-index-xelpg:
    - shard-bmg:          NOTRUN -> [SKIP][42] ([Intel XE#2236])
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v7/shard-bmg-5/igt@xe_pat@pat-index-xelpg.html

  * igt@xe_query@multigpu-query-cs-cycles:
    - shard-bmg:          NOTRUN -> [SKIP][43] ([Intel XE#944])
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v7/shard-bmg-5/igt@xe_query@multigpu-query-cs-cycles.html

  
#### Possible fixes ####

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp2:
    - shard-bmg:          [FAIL][44] ([Intel XE#7545]) -> [PASS][45] +1 other test pass
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4674-a48305e6a2e6a1ed90df374101dd29542c105d8f/shard-bmg-1/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp2.html
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v7/shard-bmg-3/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp2.html

  * igt@kms_flip@flip-vs-expired-vblank@c-edp1:
    - shard-lnl:          [FAIL][46] ([Intel XE#301] / [Intel XE#3149]) -> [PASS][47] +1 other test pass
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4674-a48305e6a2e6a1ed90df374101dd29542c105d8f/shard-lnl-6/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v7/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html

  * igt@kms_hdr@invalid-hdr:
    - shard-bmg:          [SKIP][48] ([Intel XE#1503]) -> [PASS][49]
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4674-a48305e6a2e6a1ed90df374101dd29542c105d8f/shard-bmg-9/igt@kms_hdr@invalid-hdr.html
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v7/shard-bmg-3/igt@kms_hdr@invalid-hdr.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1416]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1416
  [Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2236]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2236
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2330
  [Intel XE#2372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2372
  [Intel XE#2459]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2459
  [Intel XE#2596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2596
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#3141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3141
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#3718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3718
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#5793]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5793
  [Intel XE#5813]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5813
  [Intel XE#6078]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6078
  [Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
  [Intel XE#6361]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6361
  [Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
  [Intel XE#6665]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6665
  [Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
  [Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7136
  [Intel XE#7138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7138
  [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
  [Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
  [Intel XE#7320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7320
  [Intel XE#7321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7321
  [Intel XE#7351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7351
  [Intel XE#7354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7354
  [Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
  [Intel XE#7359]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7359
  [Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
  [Intel XE#7383]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7383
  [Intel XE#7453]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7453
  [Intel XE#7464]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7464
  [Intel XE#7482]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7482
  [Intel XE#7545]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7545
  [Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * Linux: xe-4674-a48305e6a2e6a1ed90df374101dd29542c105d8f -> xe-pw-158017v7

  IGT_8782: eac3b04d1f76b82ac3a183fb293c44e9185d8dba @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-4674-a48305e6a2e6a1ed90df374101dd29542c105d8f: a48305e6a2e6a1ed90df374101dd29542c105d8f
  xe-pw-158017v7: 158017v7

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v7/index.html

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