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* [PATCH 1/2] drm/i915/cx0: Clear response ready & error bit
@ 2026-01-22  4:48 Suraj Kandpal
  2026-01-22  4:48 ` [PATCH 2/2] drm/i915/cx0: Rename intel_clear_response_ready flag Suraj Kandpal
                   ` (4 more replies)
  0 siblings, 5 replies; 6+ messages in thread
From: Suraj Kandpal @ 2026-01-22  4:48 UTC (permalink / raw)
  To: intel-xe, intel-gfx
  Cc: ankit.k.nautiyal, Suraj Kandpal, Gustavo Sousa,
	Michał Grzelak

Clear the response ready and error bit of PORT_P2M_MESSAGE_BUS_STATUS
before writing the transaction pending bit of
PORT_M2P_MSGBUS_CTL as that is a hard requirement. If not done
we find that the PHY hangs since it ends up in a weird state if left
idle for more than 1 hour.

Bspec: 65101
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Reviewed-by: Michał Grzelak <michal.grzelak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 4f56a370102d..ff74f64eb970 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -223,6 +223,8 @@ static int __intel_cx0_read_once(struct intel_encoder *encoder,
 		return -ETIMEDOUT;
 	}
 
+	intel_clear_response_ready_flag(encoder, lane);
+
 	intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
 		       XELPDP_PORT_M2P_TRANSACTION_PENDING |
 		       XELPDP_PORT_M2P_COMMAND_READ |
@@ -294,6 +296,8 @@ static int __intel_cx0_write_once(struct intel_encoder *encoder,
 		return -ETIMEDOUT;
 	}
 
+	intel_clear_response_ready_flag(encoder, lane);
+
 	intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
 		       XELPDP_PORT_M2P_TRANSACTION_PENDING |
 		       (committed ? XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED :
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2026-03-13 15:41 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-01-22  4:48 [PATCH 1/2] drm/i915/cx0: Clear response ready & error bit Suraj Kandpal
2026-01-22  4:48 ` [PATCH 2/2] drm/i915/cx0: Rename intel_clear_response_ready flag Suraj Kandpal
2026-01-22  5:10 ` ✓ CI.KUnit: success for series starting with [1/2] drm/i915/cx0: Clear response ready & error bit Patchwork
2026-01-22  5:50 ` ✓ Xe.CI.BAT: " Patchwork
2026-01-22 16:47 ` ✗ Xe.CI.Full: failure " Patchwork
2026-03-13 15:41 ` [PATCH 1/2] " Jani Nikula

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