* [PATCH v3 0/2] drm/i915/display: Enable system cache support for FBC
@ 2025-11-23 16:01 Vinod Govindapillai
2025-11-23 16:01 ` [PATCH v3 1/2] drm/i915/display: Use a sub-struct for fbc operations in intel_display Vinod Govindapillai
` (5 more replies)
0 siblings, 6 replies; 14+ messages in thread
From: Vinod Govindapillai @ 2025-11-23 16:01 UTC (permalink / raw)
To: intel-xe, intel-gfx
Cc: vinod.govindapillai, matthew.d.roper, gustavo.sousa,
ville.syrjala, jani.nikula
Use system cacheability configuration register to assign a reserved
area in system cache for FBC
Vinod Govindapillai (2):
drm/i915/display: Use a sub-struct for fbc operations in intel_display
drm/i915/xe3p_lpd: Enable display use of system cache for FBC
drivers/gpu/drm/i915/display/i9xx_plane.c | 2 +-
.../gpu/drm/i915/display/intel_display_core.h | 8 +-
.../drm/i915/display/intel_display_device.h | 1 +
drivers/gpu/drm/i915/display/intel_fbc.c | 99 ++++++++++++++++++-
drivers/gpu/drm/i915/display/intel_fbc_regs.h | 10 ++
.../drm/i915/display/skl_universal_plane.c | 2 +-
6 files changed, 116 insertions(+), 6 deletions(-)
--
2.43.0
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v3 1/2] drm/i915/display: Use a sub-struct for fbc operations in intel_display
2025-11-23 16:01 [PATCH v3 0/2] drm/i915/display: Enable system cache support for FBC Vinod Govindapillai
@ 2025-11-23 16:01 ` Vinod Govindapillai
2025-11-24 10:54 ` Jani Nikula
2025-11-23 16:01 ` [PATCH v3 2/2] drm/i915/xe3p_lpd: Enable display use of system cache for FBC Vinod Govindapillai
` (4 subsequent siblings)
5 siblings, 1 reply; 14+ messages in thread
From: Vinod Govindapillai @ 2025-11-23 16:01 UTC (permalink / raw)
To: intel-xe, intel-gfx
Cc: vinod.govindapillai, matthew.d.roper, gustavo.sousa,
ville.syrjala, jani.nikula
As FBC can utilze the system cache in xe3p_lpd onwards, we need
a way to track which fbc instance is utilizing this cache. So we
would need to extend the intel_display with such a functionality.
Introduce a new fbc substruct and move the current fbc instance
array into that. Then the following patch can utilize this to
introduce functionaity to configure and track the system cache
usage by the fbc instance.
Suggested-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 2 +-
drivers/gpu/drm/i915/display/intel_display_core.h | 5 ++++-
drivers/gpu/drm/i915/display/intel_fbc.c | 6 +++---
drivers/gpu/drm/i915/display/skl_universal_plane.c | 2 +-
4 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 51ccc6bd5f21..2c40bc632b3d 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -134,7 +134,7 @@ static struct intel_fbc *i9xx_plane_fbc(struct intel_display *display,
enum i9xx_plane_id i9xx_plane)
{
if (i9xx_plane_has_fbc(display, i9xx_plane))
- return display->fbc[INTEL_FBC_A];
+ return display->fbc.instances[INTEL_FBC_A];
else
return NULL;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 9b36654b593d..58325f530670 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -398,6 +398,10 @@ struct intel_display {
const struct dram_info *info;
} dram;
+ struct {
+ struct intel_fbc *instances[I915_MAX_FBCS];
+ } fbc;
+
struct {
/* list of fbdev register on this device */
struct intel_fbdev *fbdev;
@@ -615,7 +619,6 @@ struct intel_display {
struct drm_dp_tunnel_mgr *dp_tunnel_mgr;
struct intel_audio audio;
struct intel_dpll_global dpll;
- struct intel_fbc *fbc[I915_MAX_FBCS];
struct intel_frontbuffer_tracking fb_tracking;
struct intel_hotplug hotplug;
struct intel_opregion *opregion;
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index d9cab25d414a..dcdfcff80de3 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -69,7 +69,7 @@
#define for_each_intel_fbc(__display, __fbc, __fbc_id) \
for_each_fbc_id((__display), (__fbc_id)) \
- for_each_if((__fbc) = (__display)->fbc[(__fbc_id)])
+ for_each_if((__fbc) = (__display)->fbc.instances[(__fbc_id)])
struct intel_fbc_funcs {
void (*activate)(struct intel_fbc *fbc);
@@ -2211,7 +2211,7 @@ void intel_fbc_init(struct intel_display *display)
display->params.enable_fbc);
for_each_fbc_id(display, fbc_id)
- display->fbc[fbc_id] = intel_fbc_create(display, fbc_id);
+ display->fbc.instances[fbc_id] = intel_fbc_create(display, fbc_id);
}
/**
@@ -2330,7 +2330,7 @@ void intel_fbc_debugfs_register(struct intel_display *display)
{
struct intel_fbc *fbc;
- fbc = display->fbc[INTEL_FBC_A];
+ fbc = display->fbc.instances[INTEL_FBC_A];
if (fbc)
intel_fbc_debugfs_add(fbc, display->drm->debugfs_root);
}
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 89c8003ccfe7..48af74963e74 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -2444,7 +2444,7 @@ static struct intel_fbc *skl_plane_fbc(struct intel_display *display,
enum intel_fbc_id fbc_id = skl_fbc_id_for_pipe(pipe);
if (skl_plane_has_fbc(display, fbc_id, plane_id))
- return display->fbc[fbc_id];
+ return display->fbc.instances[fbc_id];
else
return NULL;
}
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v3 2/2] drm/i915/xe3p_lpd: Enable display use of system cache for FBC
2025-11-23 16:01 [PATCH v3 0/2] drm/i915/display: Enable system cache support for FBC Vinod Govindapillai
2025-11-23 16:01 ` [PATCH v3 1/2] drm/i915/display: Use a sub-struct for fbc operations in intel_display Vinod Govindapillai
@ 2025-11-23 16:01 ` Vinod Govindapillai
2025-11-24 11:27 ` Jani Nikula
2025-11-24 16:25 ` Jani Nikula
2025-11-25 0:28 ` ✗ CI.checkpatch: warning for drm/i915/display: Enable system cache support " Patchwork
` (3 subsequent siblings)
5 siblings, 2 replies; 14+ messages in thread
From: Vinod Govindapillai @ 2025-11-23 16:01 UTC (permalink / raw)
To: intel-xe, intel-gfx
Cc: vinod.govindapillai, matthew.d.roper, gustavo.sousa,
ville.syrjala, jani.nikula
One of the FBC instances can utilize the reserved area of SoC
level cache for the fbc transactions to benefit reduced memory
system power especially in idle scenarios. Reserved area of the
system cache can be assigned to an fbc instance by configuring
the cacheability configuration register with offset of the
compressed frame buffer in stolen memoty of that fbc. There is
a limit to this reserved area which is programmable and for
xe3p_lpd the limit is defined as 2MB.
v2: - better to track fbc sys cache usage from intel_display level,
sanitize the cacheability config register on probe (Matt)
- limit this for integrated graphics solutions, confirmed that
no default value set for cache range by hw (Gustavo)
v3: - changes related to the use of fbc substruct in intel_display
- use intel_de_write() instead of intel_rmw() by hardcoding the
default value fields
Bspec: 68881, 74722
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
---
.../gpu/drm/i915/display/intel_display_core.h | 3 +
.../drm/i915/display/intel_display_device.h | 1 +
drivers/gpu/drm/i915/display/intel_fbc.c | 93 +++++++++++++++++++
drivers/gpu/drm/i915/display/intel_fbc_regs.h | 10 ++
4 files changed, 107 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 58325f530670..f557c9293d33 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -400,6 +400,9 @@ struct intel_display {
struct {
struct intel_fbc *instances[I915_MAX_FBCS];
+
+ /* xe3p_lpd+ : FBC instance utlizing the system cache */
+ enum intel_fbc_id sys_cache_id;
} fbc;
struct {
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index b559ef43d547..b74cb69ccc85 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -173,6 +173,7 @@ struct intel_display_platforms {
#define HAS_DSC_MST(__display) (DISPLAY_VER(__display) >= 12 && HAS_DSC(__display))
#define HAS_FBC(__display) (DISPLAY_RUNTIME_INFO(__display)->fbc_mask != 0)
#define HAS_FBC_DIRTY_RECT(__display) (DISPLAY_VER(__display) >= 30)
+#define HAS_FBC_SYS_CACHE(__display) (DISPLAY_VER(__display) >= 35 && !(__display)->platform.dgfx)
#define HAS_FPGA_DBG_UNCLAIMED(__display) (DISPLAY_INFO(__display)->has_fpga_dbg)
#define HAS_FW_BLC(__display) (DISPLAY_VER(__display) >= 3)
#define HAS_GMBUS_BURST_READ(__display) (DISPLAY_VER(__display) >= 10 || (__display)->platform.kabylake)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index dcdfcff80de3..d7e913792518 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -71,6 +71,10 @@
for_each_fbc_id((__display), (__fbc_id)) \
for_each_if((__fbc) = (__display)->fbc.instances[(__fbc_id)])
+#define SYS_CACHE_FBC_INSTANCE_NONE I915_MAX_FBCS
+#define IS_SYS_CACHE_FBC_INSTANCE_NONE(__display) ((__display)->fbc.sys_cache_id == SYS_CACHE_FBC_INSTANCE_NONE)
+#define IS_SYS_CACHE_FBC_INSTANCE_EQUALS(__display, id) ((__display)->fbc.sys_cache_id == (id))
+
struct intel_fbc_funcs {
void (*activate)(struct intel_fbc *fbc);
void (*deactivate)(struct intel_fbc *fbc);
@@ -941,6 +945,79 @@ static void intel_fbc_program_workarounds(struct intel_fbc *fbc)
fbc_compressor_clkgate_disable_wa(fbc, true);
}
+static void xe3p_lpd_fbc_set_sys_cache_fbc_id(struct intel_display *display,
+ enum intel_fbc_id fbc_id)
+{
+ display->fbc.sys_cache_id = fbc_id;
+}
+
+static void xe3p_lpd_fbc_commit_sys_cache_usage(struct intel_display *display,
+ u32 reg)
+{
+ intel_de_write(display, XE3P_LPD_FBC_SYS_CACHE_USAGE_CFG, reg);
+}
+
+static int xe3p_lpd_fbc_get_cache_limit(void)
+{
+ /* Default 2MB for xe3p_lpd */
+ return 2 * 1024 * 1024;
+}
+
+static void xe3p_lpd_fbc_clear_sys_cache_usage(struct intel_display *display)
+{
+ /* Clear all the fields except the default fields */
+ u32 default_fields = FBC_SYS_CACHE_READ_ENABLE;
+
+ xe3p_lpd_fbc_commit_sys_cache_usage(display, default_fields);
+
+ /* Mark that no FBC instance utilize the system cache */
+ xe3p_lpd_fbc_set_sys_cache_fbc_id(display, SYS_CACHE_FBC_INSTANCE_NONE);
+}
+
+static void xe3p_lpd_fbc_set_sys_cache_usage(const struct intel_fbc *fbc)
+{
+ struct intel_display *display = fbc->display;
+ /* limit to be configured to the register in 64k byte chunks */
+ int range = xe3p_lpd_fbc_get_cache_limit() / (64 * 1024);
+ /* offset to be configured to the register in 4K byte chunks */
+ int offset = i915_gem_stolen_node_offset(fbc->compressed_fb) / (4 * 1024);
+ /* Cache read enable is enabled by default */
+ u32 usage = FBC_SYS_CACHE_TAG_USE_RES_SPACE |
+ FBC_SYS_CACHEABLE_RANGE(range) |
+ FBC_SYS_CACHE_START_BASE(offset) |
+ FBC_SYS_CACHE_READ_ENABLE;
+
+ lockdep_assert_held(&fbc->lock);
+
+ xe3p_lpd_fbc_commit_sys_cache_usage(display, usage);
+
+ xe3p_lpd_fbc_set_sys_cache_fbc_id(display, fbc->id);
+}
+
+static void xe3p_lpd_fbc_update_sys_cache_usage(const struct intel_fbc *fbc,
+ bool set)
+{
+ struct intel_display *display = fbc->display;
+
+ lockdep_assert_held(&fbc->lock);
+
+ /* system cache for fbc already reserved */
+ if (set && !IS_SYS_CACHE_FBC_INSTANCE_NONE(display))
+ return;
+
+ /* cannot clear if "fbc" did not reserve the cache */
+ if (!set && !IS_SYS_CACHE_FBC_INSTANCE_EQUALS(display, fbc->id))
+ return;
+
+ if (set)
+ xe3p_lpd_fbc_set_sys_cache_usage(fbc);
+ else
+ xe3p_lpd_fbc_clear_sys_cache_usage(display);
+
+ drm_dbg_kms(display->drm, "System cacheability usage for FBC[%d] %s\n",
+ fbc->id, set ? "configured" : "cleared");
+}
+
static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc)
{
if (WARN_ON(intel_fbc_hw_is_active(fbc)))
@@ -967,6 +1044,9 @@ void intel_fbc_cleanup(struct intel_display *display)
kfree(fbc);
}
+
+ if (HAS_FBC_SYS_CACHE(display))
+ xe3p_lpd_fbc_clear_sys_cache_usage(display);
}
static bool i8xx_fbc_stride_is_valid(const struct intel_plane_state *plane_state)
@@ -1780,6 +1860,9 @@ static void __intel_fbc_disable(struct intel_fbc *fbc)
__intel_fbc_cleanup_cfb(fbc);
+ if (HAS_FBC_SYS_CACHE(display))
+ xe3p_lpd_fbc_update_sys_cache_usage(fbc, false);
+
/* wa_18038517565 Enable DPFC clock gating after FBC disable */
if (display->platform.dg2 || DISPLAY_VER(display) >= 14)
fbc_compressor_clkgate_disable_wa(fbc, false);
@@ -1972,6 +2055,9 @@ static void __intel_fbc_enable(struct intel_atomic_state *state,
intel_fbc_program_workarounds(fbc);
intel_fbc_program_cfb(fbc);
+
+ if (HAS_FBC_SYS_CACHE(display))
+ xe3p_lpd_fbc_update_sys_cache_usage(fbc, true);
}
/**
@@ -2212,6 +2298,9 @@ void intel_fbc_init(struct intel_display *display)
for_each_fbc_id(display, fbc_id)
display->fbc.instances[fbc_id] = intel_fbc_create(display, fbc_id);
+
+ /* Mark that no FBC instance is using the system cache */
+ xe3p_lpd_fbc_set_sys_cache_fbc_id(display, SYS_CACHE_FBC_INSTANCE_NONE);
}
/**
@@ -2231,6 +2320,10 @@ void intel_fbc_sanitize(struct intel_display *display)
if (intel_fbc_hw_is_active(fbc))
intel_fbc_hw_deactivate(fbc);
}
+
+ /* Ensure the sys cache usage register gets cleared */
+ if (HAS_FBC_SYS_CACHE(display))
+ xe3p_lpd_fbc_clear_sys_cache_usage(display);
}
static int intel_fbc_debugfs_status_show(struct seq_file *m, void *unused)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc_regs.h b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
index b1d0161a3196..d2d889fa4bed 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
@@ -126,4 +126,14 @@
#define FBC_REND_NUKE REG_BIT(2)
#define FBC_REND_CACHE_CLEAN REG_BIT(1)
+#define XE3P_LPD_FBC_SYS_CACHE_USAGE_CFG _MMIO(0x1344E0)
+#define FBC_SYS_CACHE_START_BASE_MASK REG_GENMASK(31, 16)
+#define FBC_SYS_CACHE_START_BASE(base) REG_FIELD_PREP(FBC_SYS_CACHE_START_BASE_MASK, (base))
+#define FBC_SYS_CACHEABLE_RANGE_MASK REG_GENMASK(15, 4)
+#define FBC_SYS_CACHEABLE_RANGE(range) REG_FIELD_PREP(FBC_SYS_CACHEABLE_RANGE_MASK, (range))
+#define FBC_SYS_CACHE_TAG_MASK REG_GENMASK(3, 2)
+#define FBC_SYS_CACHE_TAG_DONT_CACHE REG_FIELD_PREP(FBC_SYS_CACHE_TAG_MASK, 0)
+#define FBC_SYS_CACHE_TAG_USE_RES_SPACE REG_FIELD_PREP(FBC_SYS_CACHE_TAG_MASK, 3)
+#define FBC_SYS_CACHE_READ_ENABLE REG_BIT(0)
+
#endif /* __INTEL_FBC_REGS__ */
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH v3 1/2] drm/i915/display: Use a sub-struct for fbc operations in intel_display
2025-11-23 16:01 ` [PATCH v3 1/2] drm/i915/display: Use a sub-struct for fbc operations in intel_display Vinod Govindapillai
@ 2025-11-24 10:54 ` Jani Nikula
0 siblings, 0 replies; 14+ messages in thread
From: Jani Nikula @ 2025-11-24 10:54 UTC (permalink / raw)
To: Vinod Govindapillai, intel-xe, intel-gfx
Cc: vinod.govindapillai, matthew.d.roper, gustavo.sousa,
ville.syrjala
On Sun, 23 Nov 2025, Vinod Govindapillai <vinod.govindapillai@intel.com> wrote:
> As FBC can utilze the system cache in xe3p_lpd onwards, we need
*utilize
> a way to track which fbc instance is utilizing this cache. So we
> would need to extend the intel_display with such a functionality.
> Introduce a new fbc substruct and move the current fbc instance
> array into that. Then the following patch can utilize this to
> introduce functionaity to configure and track the system cache
> usage by the fbc instance.
In general, please don't refer to "patches" in commit messages. Just
consider reading this commit message a year from now, wondering what
"the following patch" might refer to.
No need to resend for this.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> Suggested-by: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> ---
> drivers/gpu/drm/i915/display/i9xx_plane.c | 2 +-
> drivers/gpu/drm/i915/display/intel_display_core.h | 5 ++++-
> drivers/gpu/drm/i915/display/intel_fbc.c | 6 +++---
> drivers/gpu/drm/i915/display/skl_universal_plane.c | 2 +-
> 4 files changed, 9 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
> index 51ccc6bd5f21..2c40bc632b3d 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_plane.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
> @@ -134,7 +134,7 @@ static struct intel_fbc *i9xx_plane_fbc(struct intel_display *display,
> enum i9xx_plane_id i9xx_plane)
> {
> if (i9xx_plane_has_fbc(display, i9xx_plane))
> - return display->fbc[INTEL_FBC_A];
> + return display->fbc.instances[INTEL_FBC_A];
> else
> return NULL;
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
> index 9b36654b593d..58325f530670 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> @@ -398,6 +398,10 @@ struct intel_display {
> const struct dram_info *info;
> } dram;
>
> + struct {
> + struct intel_fbc *instances[I915_MAX_FBCS];
> + } fbc;
> +
> struct {
> /* list of fbdev register on this device */
> struct intel_fbdev *fbdev;
> @@ -615,7 +619,6 @@ struct intel_display {
> struct drm_dp_tunnel_mgr *dp_tunnel_mgr;
> struct intel_audio audio;
> struct intel_dpll_global dpll;
> - struct intel_fbc *fbc[I915_MAX_FBCS];
> struct intel_frontbuffer_tracking fb_tracking;
> struct intel_hotplug hotplug;
> struct intel_opregion *opregion;
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index d9cab25d414a..dcdfcff80de3 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -69,7 +69,7 @@
>
> #define for_each_intel_fbc(__display, __fbc, __fbc_id) \
> for_each_fbc_id((__display), (__fbc_id)) \
> - for_each_if((__fbc) = (__display)->fbc[(__fbc_id)])
> + for_each_if((__fbc) = (__display)->fbc.instances[(__fbc_id)])
>
> struct intel_fbc_funcs {
> void (*activate)(struct intel_fbc *fbc);
> @@ -2211,7 +2211,7 @@ void intel_fbc_init(struct intel_display *display)
> display->params.enable_fbc);
>
> for_each_fbc_id(display, fbc_id)
> - display->fbc[fbc_id] = intel_fbc_create(display, fbc_id);
> + display->fbc.instances[fbc_id] = intel_fbc_create(display, fbc_id);
> }
>
> /**
> @@ -2330,7 +2330,7 @@ void intel_fbc_debugfs_register(struct intel_display *display)
> {
> struct intel_fbc *fbc;
>
> - fbc = display->fbc[INTEL_FBC_A];
> + fbc = display->fbc.instances[INTEL_FBC_A];
> if (fbc)
> intel_fbc_debugfs_add(fbc, display->drm->debugfs_root);
> }
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 89c8003ccfe7..48af74963e74 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -2444,7 +2444,7 @@ static struct intel_fbc *skl_plane_fbc(struct intel_display *display,
> enum intel_fbc_id fbc_id = skl_fbc_id_for_pipe(pipe);
>
> if (skl_plane_has_fbc(display, fbc_id, plane_id))
> - return display->fbc[fbc_id];
> + return display->fbc.instances[fbc_id];
> else
> return NULL;
> }
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v3 2/2] drm/i915/xe3p_lpd: Enable display use of system cache for FBC
2025-11-23 16:01 ` [PATCH v3 2/2] drm/i915/xe3p_lpd: Enable display use of system cache for FBC Vinod Govindapillai
@ 2025-11-24 11:27 ` Jani Nikula
2025-11-24 13:32 ` Govindapillai, Vinod
2025-11-24 16:25 ` Jani Nikula
1 sibling, 1 reply; 14+ messages in thread
From: Jani Nikula @ 2025-11-24 11:27 UTC (permalink / raw)
To: Vinod Govindapillai, intel-xe, intel-gfx
Cc: vinod.govindapillai, matthew.d.roper, gustavo.sousa,
ville.syrjala
On Sun, 23 Nov 2025, Vinod Govindapillai <vinod.govindapillai@intel.com> wrote:
> One of the FBC instances can utilize the reserved area of SoC
> level cache for the fbc transactions to benefit reduced memory
> system power especially in idle scenarios. Reserved area of the
> system cache can be assigned to an fbc instance by configuring
> the cacheability configuration register with offset of the
> compressed frame buffer in stolen memoty of that fbc. There is
> a limit to this reserved area which is programmable and for
> xe3p_lpd the limit is defined as 2MB.
>
> v2: - better to track fbc sys cache usage from intel_display level,
> sanitize the cacheability config register on probe (Matt)
> - limit this for integrated graphics solutions, confirmed that
> no default value set for cache range by hw (Gustavo)
>
> v3: - changes related to the use of fbc substruct in intel_display
> - use intel_de_write() instead of intel_rmw() by hardcoding the
> default value fields
>
I think overall the implementation feels a bit overwhelming. I mean
there are so many functions, so many checks, to the point of being
excessive.
Some comments inline.
> Bspec: 68881, 74722
> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> ---
> .../gpu/drm/i915/display/intel_display_core.h | 3 +
> .../drm/i915/display/intel_display_device.h | 1 +
> drivers/gpu/drm/i915/display/intel_fbc.c | 93 +++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_fbc_regs.h | 10 ++
> 4 files changed, 107 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
> index 58325f530670..f557c9293d33 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> @@ -400,6 +400,9 @@ struct intel_display {
>
> struct {
> struct intel_fbc *instances[I915_MAX_FBCS];
> +
> + /* xe3p_lpd+ : FBC instance utlizing the system cache */
Please no space before :, *utilizing
> + enum intel_fbc_id sys_cache_id;
> } fbc;
>
> struct {
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
> index b559ef43d547..b74cb69ccc85 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> @@ -173,6 +173,7 @@ struct intel_display_platforms {
> #define HAS_DSC_MST(__display) (DISPLAY_VER(__display) >= 12 && HAS_DSC(__display))
> #define HAS_FBC(__display) (DISPLAY_RUNTIME_INFO(__display)->fbc_mask != 0)
> #define HAS_FBC_DIRTY_RECT(__display) (DISPLAY_VER(__display) >= 30)
> +#define HAS_FBC_SYS_CACHE(__display) (DISPLAY_VER(__display) >= 35 && !(__display)->platform.dgfx)
> #define HAS_FPGA_DBG_UNCLAIMED(__display) (DISPLAY_INFO(__display)->has_fpga_dbg)
> #define HAS_FW_BLC(__display) (DISPLAY_VER(__display) >= 3)
> #define HAS_GMBUS_BURST_READ(__display) (DISPLAY_VER(__display) >= 10 || (__display)->platform.kabylake)
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index dcdfcff80de3..d7e913792518 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -71,6 +71,10 @@
> for_each_fbc_id((__display), (__fbc_id)) \
> for_each_if((__fbc) = (__display)->fbc.instances[(__fbc_id)])
>
> +#define SYS_CACHE_FBC_INSTANCE_NONE I915_MAX_FBCS
> +#define IS_SYS_CACHE_FBC_INSTANCE_NONE(__display) ((__display)->fbc.sys_cache_id == SYS_CACHE_FBC_INSTANCE_NONE)
The only user of this has !IS_SYS_CACHE_FBC_INSTANCE_NONE(display)
i.e. "if not none".
Would be more useful to check if it's "set" or "valid", and avoid the
double negative. And use a shorter name. Maybe a static inline function.
But I'm not even sure the display->fbc.sys_cache_id needs to be
abstracted away. It's not a complicated thing, and, more importantly,
it's all within the same file. If outside access was needed, yes,
abstract, but here, not convinced.
Maybe:
if (fbc_sys_cache_id_valid(display->fbc.sys_cache_id))
I also don't think *all* of these functions should be prefixed with
xe3p_lpd_ because that's a monster, and makes all of this difficult to
read.
> +#define IS_SYS_CACHE_FBC_INSTANCE_EQUALS(__display, id) ((__display)->fbc.sys_cache_id == (id))
I think this feels cumbersome. Why not just check
if (display->fbc.sys_cache_id == id)
inline, and it's obvious?
> +
> struct intel_fbc_funcs {
> void (*activate)(struct intel_fbc *fbc);
> void (*deactivate)(struct intel_fbc *fbc);
> @@ -941,6 +945,79 @@ static void intel_fbc_program_workarounds(struct intel_fbc *fbc)
> fbc_compressor_clkgate_disable_wa(fbc, true);
> }
>
> +static void xe3p_lpd_fbc_set_sys_cache_fbc_id(struct intel_display *display,
> + enum intel_fbc_id fbc_id)
> +{
> + display->fbc.sys_cache_id = fbc_id;
> +}
Again, I'm not sure if this function is really needed. Just inline?
> +
> +static void xe3p_lpd_fbc_commit_sys_cache_usage(struct intel_display *display,
> + u32 reg)
> +{
> + intel_de_write(display, XE3P_LPD_FBC_SYS_CACHE_USAGE_CFG, reg);
> +}
Not sure if this is needed. Just inline?
> +
> +static int xe3p_lpd_fbc_get_cache_limit(void)
> +{
> + /* Default 2MB for xe3p_lpd */
> + return 2 * 1024 * 1024;
> +}
Ditto. Especially odd how this multiplies and the user the divides by 64
* 1024.
> +
> +static void xe3p_lpd_fbc_clear_sys_cache_usage(struct intel_display *display)
> +{
> + /* Clear all the fields except the default fields */
> + u32 default_fields = FBC_SYS_CACHE_READ_ENABLE;
> +
> + xe3p_lpd_fbc_commit_sys_cache_usage(display, default_fields);
> +
> + /* Mark that no FBC instance utilize the system cache */
> + xe3p_lpd_fbc_set_sys_cache_fbc_id(display, SYS_CACHE_FBC_INSTANCE_NONE);
> +}
My point above is that this function only calls wrappers and really does
nothing itself. It's too many layers for a simple thing.
fbc_sys_cache_disable()?
> +
> +static void xe3p_lpd_fbc_set_sys_cache_usage(const struct intel_fbc *fbc)
> +{
> + struct intel_display *display = fbc->display;
> + /* limit to be configured to the register in 64k byte chunks */
> + int range = xe3p_lpd_fbc_get_cache_limit() / (64 * 1024);
> + /* offset to be configured to the register in 4K byte chunks */
> + int offset = i915_gem_stolen_node_offset(fbc->compressed_fb) / (4 * 1024);
> + /* Cache read enable is enabled by default */
> + u32 usage = FBC_SYS_CACHE_TAG_USE_RES_SPACE |
> + FBC_SYS_CACHEABLE_RANGE(range) |
> + FBC_SYS_CACHE_START_BASE(offset) |
> + FBC_SYS_CACHE_READ_ENABLE;
> +
> + lockdep_assert_held(&fbc->lock);
> +
> + xe3p_lpd_fbc_commit_sys_cache_usage(display, usage);
> +
> + xe3p_lpd_fbc_set_sys_cache_fbc_id(display, fbc->id);
> +}
Ditto.
fbc_sys_cache_enable()?
> +
> +static void xe3p_lpd_fbc_update_sys_cache_usage(const struct intel_fbc *fbc,
> + bool set)
> +{
> + struct intel_display *display = fbc->display;
> +
> + lockdep_assert_held(&fbc->lock);
> +
> + /* system cache for fbc already reserved */
> + if (set && !IS_SYS_CACHE_FBC_INSTANCE_NONE(display))
> + return;
> +
> + /* cannot clear if "fbc" did not reserve the cache */
> + if (!set && !IS_SYS_CACHE_FBC_INSTANCE_EQUALS(display, fbc->id))
> + return;
> +
> + if (set)
> + xe3p_lpd_fbc_set_sys_cache_usage(fbc);
> + else
> + xe3p_lpd_fbc_clear_sys_cache_usage(display);
> +
> + drm_dbg_kms(display->drm, "System cacheability usage for FBC[%d] %s\n",
> + fbc->id, set ? "configured" : "cleared");
> +}
Most of this function is two separate paths based on the parameter. I
think it would benefit from actually being two separate functions. So
why not just merge this with xe3p_lpd_fbc_set_sys_cache_usage() and
xe3p_lpd_fbc_clear_sys_cache_usage()?
> +
> static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc)
> {
> if (WARN_ON(intel_fbc_hw_is_active(fbc)))
> @@ -967,6 +1044,9 @@ void intel_fbc_cleanup(struct intel_display *display)
>
> kfree(fbc);
> }
> +
> + if (HAS_FBC_SYS_CACHE(display))
> + xe3p_lpd_fbc_clear_sys_cache_usage(display);
I don't think this should check for HAS_FBC_SYS_CACHE(). I think
internally the function being called should check if sys cache has been
set. And make sure it's only set on where it's available.
> }
>
> static bool i8xx_fbc_stride_is_valid(const struct intel_plane_state *plane_state)
> @@ -1780,6 +1860,9 @@ static void __intel_fbc_disable(struct intel_fbc *fbc)
>
> __intel_fbc_cleanup_cfb(fbc);
>
> + if (HAS_FBC_SYS_CACHE(display))
> + xe3p_lpd_fbc_update_sys_cache_usage(fbc, false);
> +
Ditto. I'm also not sure why some places call the version with params,
and some others the version without params.
> /* wa_18038517565 Enable DPFC clock gating after FBC disable */
> if (display->platform.dg2 || DISPLAY_VER(display) >= 14)
> fbc_compressor_clkgate_disable_wa(fbc, false);
> @@ -1972,6 +2055,9 @@ static void __intel_fbc_enable(struct intel_atomic_state *state,
>
> intel_fbc_program_workarounds(fbc);
> intel_fbc_program_cfb(fbc);
> +
> + if (HAS_FBC_SYS_CACHE(display))
> + xe3p_lpd_fbc_update_sys_cache_usage(fbc, true);
xe3p_lpd_fbc_update_sys_cache_usage() is the function that should check
for HAS_FBC_SYS_CACHE() in one place.
Well, maybe it should be renamed fbc_sys_cache_enable().
> }
>
> /**
> @@ -2212,6 +2298,9 @@ void intel_fbc_init(struct intel_display *display)
>
> for_each_fbc_id(display, fbc_id)
> display->fbc.instances[fbc_id] = intel_fbc_create(display, fbc_id);
> +
> + /* Mark that no FBC instance is using the system cache */
> + xe3p_lpd_fbc_set_sys_cache_fbc_id(display, SYS_CACHE_FBC_INSTANCE_NONE);
> }
>
> /**
> @@ -2231,6 +2320,10 @@ void intel_fbc_sanitize(struct intel_display *display)
> if (intel_fbc_hw_is_active(fbc))
> intel_fbc_hw_deactivate(fbc);
> }
> +
> + /* Ensure the sys cache usage register gets cleared */
> + if (HAS_FBC_SYS_CACHE(display))
> + xe3p_lpd_fbc_clear_sys_cache_usage(display);
Ditto about checking for valid sys cache inside, not
HAS_FBC_SYS_CACHE().
> }
>
> static int intel_fbc_debugfs_status_show(struct seq_file *m, void *unused)
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc_regs.h b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> index b1d0161a3196..d2d889fa4bed 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> @@ -126,4 +126,14 @@
> #define FBC_REND_NUKE REG_BIT(2)
> #define FBC_REND_CACHE_CLEAN REG_BIT(1)
>
> +#define XE3P_LPD_FBC_SYS_CACHE_USAGE_CFG _MMIO(0x1344E0)
> +#define FBC_SYS_CACHE_START_BASE_MASK REG_GENMASK(31, 16)
> +#define FBC_SYS_CACHE_START_BASE(base) REG_FIELD_PREP(FBC_SYS_CACHE_START_BASE_MASK, (base))
> +#define FBC_SYS_CACHEABLE_RANGE_MASK REG_GENMASK(15, 4)
> +#define FBC_SYS_CACHEABLE_RANGE(range) REG_FIELD_PREP(FBC_SYS_CACHEABLE_RANGE_MASK, (range))
> +#define FBC_SYS_CACHE_TAG_MASK REG_GENMASK(3, 2)
> +#define FBC_SYS_CACHE_TAG_DONT_CACHE REG_FIELD_PREP(FBC_SYS_CACHE_TAG_MASK, 0)
> +#define FBC_SYS_CACHE_TAG_USE_RES_SPACE REG_FIELD_PREP(FBC_SYS_CACHE_TAG_MASK, 3)
> +#define FBC_SYS_CACHE_READ_ENABLE REG_BIT(0)
> +
> #endif /* __INTEL_FBC_REGS__ */
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v3 2/2] drm/i915/xe3p_lpd: Enable display use of system cache for FBC
2025-11-24 11:27 ` Jani Nikula
@ 2025-11-24 13:32 ` Govindapillai, Vinod
2025-11-24 16:23 ` Jani Nikula
0 siblings, 1 reply; 14+ messages in thread
From: Govindapillai, Vinod @ 2025-11-24 13:32 UTC (permalink / raw)
To: intel-xe@lists.freedesktop.org, Nikula, Jani,
intel-gfx@lists.freedesktop.org
Cc: Sousa, Gustavo, Roper, Matthew D, Syrjala, Ville
Hi Jani,
Thanks for the input.. replies inline...
On Mon, 2025-11-24 at 13:27 +0200, Jani Nikula wrote:
> On Sun, 23 Nov 2025, Vinod Govindapillai
> <vinod.govindapillai@intel.com> wrote:
> > One of the FBC instances can utilize the reserved area of SoC
> > level cache for the fbc transactions to benefit reduced memory
> > system power especially in idle scenarios. Reserved area of the
> > system cache can be assigned to an fbc instance by configuring
> > the cacheability configuration register with offset of the
> > compressed frame buffer in stolen memoty of that fbc. There is
> > a limit to this reserved area which is programmable and for
> > xe3p_lpd the limit is defined as 2MB.
> >
> > v2: - better to track fbc sys cache usage from intel_display level,
> > sanitize the cacheability config register on probe (Matt)
> > - limit this for integrated graphics solutions, confirmed that
> > no default value set for cache range by hw (Gustavo)
> >
> > v3: - changes related to the use of fbc substruct in intel_display
> > - use intel_de_write() instead of intel_rmw() by hardcoding the
> > default value fields
> >
>
> I think overall the implementation feels a bit overwhelming. I mean
> there are so many functions, so many checks, to the point of being
> excessive.
>
> Some comments inline.
>
> > Bspec: 68881, 74722
> > Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> > ---
> > .../gpu/drm/i915/display/intel_display_core.h | 3 +
> > .../drm/i915/display/intel_display_device.h | 1 +
> > drivers/gpu/drm/i915/display/intel_fbc.c | 93
> > +++++++++++++++++++
> > drivers/gpu/drm/i915/display/intel_fbc_regs.h | 10 ++
> > 4 files changed, 107 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
> > b/drivers/gpu/drm/i915/display/intel_display_core.h
> > index 58325f530670..f557c9293d33 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> > @@ -400,6 +400,9 @@ struct intel_display {
> >
> > struct {
> > struct intel_fbc *instances[I915_MAX_FBCS];
> > +
> > + /* xe3p_lpd+ : FBC instance utlizing the system
> > cache */
>
> Please no space before :, *utilizing
>
> > + enum intel_fbc_id sys_cache_id;
> > } fbc;
> >
> > struct {
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h
> > b/drivers/gpu/drm/i915/display/intel_display_device.h
> > index b559ef43d547..b74cb69ccc85 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> > @@ -173,6 +173,7 @@ struct intel_display_platforms {
> > #define HAS_DSC_MST(__display) (DISPLAY_VER(__display) >=
> > 12 && HAS_DSC(__display))
> > #define
> > HAS_FBC(__display) (DISPLAY_RUNTIME_INFO(__display)->fbc_mask != 0)
> > #define HAS_FBC_DIRTY_RECT(__display) (DISPLAY_VER(__display) >=
> > 30)
> > +#define HAS_FBC_SYS_CACHE(__display) (DISPLAY_VER(__display) >=
> > 35 && !(__display)->platform.dgfx)
> > #define
> > HAS_FPGA_DBG_UNCLAIMED(__display) (DISPLAY_INFO(__display)->has_fpga_dbg)
> > #define HAS_FW_BLC(__display) (DISPLAY_VER(__display) >=
> > 3)
> > #define
> > HAS_GMBUS_BURST_READ(__display) (DISPLAY_VER(__display) >= 10 || (__display)->platform.kabylake)
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> > b/drivers/gpu/drm/i915/display/intel_fbc.c
> > index dcdfcff80de3..d7e913792518 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > @@ -71,6 +71,10 @@
> > for_each_fbc_id((__display), (__fbc_id)) \
> > for_each_if((__fbc) = (__display)-
> > >fbc.instances[(__fbc_id)])
> >
> > +#define
> > SYS_CACHE_FBC_INSTANCE_NONE I915_MAX_FBCS
> > +#define
> > IS_SYS_CACHE_FBC_INSTANCE_NONE(__display) ((__display)->fbc.sys_cache_id==SYS_CACHE_FBC_INSTANCE_NONE)
>
> The only user of this has !IS_SYS_CACHE_FBC_INSTANCE_NONE(display)
> i.e. "if not none".
>
> Would be more useful to check if it's "set" or "valid", and avoid the
> double negative. And use a shorter name. Maybe a static inline
> function.
>
> But I'm not even sure the display->fbc.sys_cache_id needs to be
> abstracted away. It's not a complicated thing, and, more importantly,
> it's all within the same file. If outside access was needed, yes,
> abstract, but here, not convinced.
>
> Maybe:
>
> if (fbc_sys_cache_id_valid(display->fbc.sys_cache_id))
>
> I also don't think *all* of these functions should be prefixed with
> xe3p_lpd_ because that's a monster, and makes all of this difficult
> to
> read.
>
> > +#define IS_SYS_CACHE_FBC_INSTANCE_EQUALS(__display,
> > id) ((__display)->fbc.sys_cache_id == (id))
>
> I think this feels cumbersome. Why not just check
>
> if (display->fbc.sys_cache_id == id)
>
> inline, and it's obvious?
>
> > +
> > struct intel_fbc_funcs {
> > void (*activate)(struct intel_fbc *fbc);
> > void (*deactivate)(struct intel_fbc *fbc);
> > @@ -941,6 +945,79 @@ static void
> > intel_fbc_program_workarounds(struct intel_fbc *fbc)
> > fbc_compressor_clkgate_disable_wa(fbc, true);
> > }
> >
> > +static void xe3p_lpd_fbc_set_sys_cache_fbc_id(struct intel_display
> > *display,
> > + enum intel_fbc_id
> > fbc_id)
> > +{
> > + display->fbc.sys_cache_id = fbc_id;
> > +}
>
> Again, I'm not sure if this function is really needed. Just inline?
Ack for the above suggestions. About the function naming, yeah it is
indeed bit complex, but was following the functions names being
followed in this file. Should it be prefixed with nvl /intel or just
fbc? instead? Any suggestion?
>
> > +
> > +static void xe3p_lpd_fbc_commit_sys_cache_usage(struct
> > intel_display *display,
> > + u32 reg)
> > +{
> > + intel_de_write(display, XE3P_LPD_FBC_SYS_CACHE_USAGE_CFG,
> > reg);
> > +}
>
> Not sure if this is needed. Just inline?
Two paths update this register - setting up the cache for a fbc and
clearing it. Also soon there is going to be a workaround implemented
which we need to disable the read cache enable bit which is set on by
default. So I was thinking of intercept here and apply the wa
if (intel_display_wa(display, xxxx))
reg &= ~FBC_SYS_CACHE_READ_ENABLE;
>
> > +
> > +static int xe3p_lpd_fbc_get_cache_limit(void)
> > +{
> > + /* Default 2MB for xe3p_lpd */
> > + return 2 * 1024 * 1024;
> > +}
>
> Ditto. Especially odd how this multiplies and the user the divides by
> 64
> * 1024.
Initially from HAS my understanding was that this was supposed to be
set by a pre-os fw and driver dont modify this field. And this can
change per platform. But from the recent logs fro, these fields are set
as 0 and has to be programmed by the driver. (I am clarifying this with
the HW team). Anyway, this need to be variated per platform. In some
other component such 2MB was hard coded like this. So thought of
adopting that. Any suggestion?
> > +
> > +static void xe3p_lpd_fbc_clear_sys_cache_usage(struct
> > intel_display *display)
> > +{
> > + /* Clear all the fields except the default fields */
> > + u32 default_fields = FBC_SYS_CACHE_READ_ENABLE;
> > +
> > + xe3p_lpd_fbc_commit_sys_cache_usage(display,
> > default_fields);
> > +
> > + /* Mark that no FBC instance utilize the system cache */
> > + xe3p_lpd_fbc_set_sys_cache_fbc_id(display,
> > SYS_CACHE_FBC_INSTANCE_NONE);
> > +}
>
> My point above is that this function only calls wrappers and really
> does
> nothing itself. It's too many layers for a simple thing.
>
> fbc_sys_cache_disable()?
>
> > +
> > +static void xe3p_lpd_fbc_set_sys_cache_usage(const struct
> > intel_fbc *fbc)
> > +{
> > + struct intel_display *display = fbc->display;
> > + /* limit to be configured to the register in 64k byte
> > chunks */
> > + int range = xe3p_lpd_fbc_get_cache_limit() / (64 * 1024);
> > + /* offset to be configured to the register in 4K byte
> > chunks */
> > + int offset = i915_gem_stolen_node_offset(fbc-
> > >compressed_fb) / (4 * 1024);
> > + /* Cache read enable is enabled by default */
> > + u32 usage = FBC_SYS_CACHE_TAG_USE_RES_SPACE |
> > + FBC_SYS_CACHEABLE_RANGE(range) |
> > + FBC_SYS_CACHE_START_BASE(offset) |
> > + FBC_SYS_CACHE_READ_ENABLE;
> > +
> > + lockdep_assert_held(&fbc->lock);
> > +
> > + xe3p_lpd_fbc_commit_sys_cache_usage(display, usage);
> > +
> > + xe3p_lpd_fbc_set_sys_cache_fbc_id(display, fbc->id);
> > +}
>
> Ditto.
>
> fbc_sys_cache_enable()?
>
> > +
> > +static void xe3p_lpd_fbc_update_sys_cache_usage(const struct
> > intel_fbc *fbc,
> > + bool set)
> > +{
> > + struct intel_display *display = fbc->display;
> > +
> > + lockdep_assert_held(&fbc->lock);
> > +
> > + /* system cache for fbc already reserved */
> > + if (set && !IS_SYS_CACHE_FBC_INSTANCE_NONE(display))
> > + return;
> > +
> > + /* cannot clear if "fbc" did not reserve the cache */
> > + if (!set && !IS_SYS_CACHE_FBC_INSTANCE_EQUALS(display,
> > fbc->id))
> > + return;
> > +
> > + if (set)
> > + xe3p_lpd_fbc_set_sys_cache_usage(fbc);
> > + else
> > + xe3p_lpd_fbc_clear_sys_cache_usage(display);
> > +
> > + drm_dbg_kms(display->drm, "System cacheability usage for
> > FBC[%d] %s\n",
> > + fbc->id, set ? "configured" : "cleared");
> > +}
>
> Most of this function is two separate paths based on the parameter. I
> think it would benefit from actually being two separate functions. So
> why not just merge this with xe3p_lpd_fbc_set_sys_cache_usage() and
> xe3p_lpd_fbc_clear_sys_cache_usage()?
Actually there are three paths to update this register (two separate
path to clear this register)
1. As part of enable FBC - depends on the fbc instance (with fbc mutex
taken). If sys_cache is not reserved by any other instance.
2. As part of disable FBC - depends on the fbc instance to avoid
clearing if this fbc didnt reserve the cache space. (with fbc mutex
taken)
3. Clear this register as part of sanitize call (upon setup_hw_state()
calls upon probe and resume) and intel_fbc_cleanup() upon module
removal. Not depend on the fbc instance.
So something like this make sense?
fbc_program_sys_cache(u32 reg)
{
intel_de_write(reg)
}
fbc_sys_cache_reset(display)
{
if (!HAS_FBC_SYS_CACHE())
return
fbc_program_sys_cache(0)
fbc.sys_cache_id = SYS_CACHE_FBC_INSTANCE_NONE
}
fbc_sys_cache_disable(fbc)
{
if (!HAS_FBC_SYS_CACHE())
return
if (fbc.sys_cache_id != fbc->id)
return;
fbc_sys_cache_reset(display)
}
fbc_sys_cache_enable(fbc)
{
if (!HAS_FBC_SYS_CACHE())
return
if (fbc.sys_cache_id != SYS_CACHE_FBC_INSTANCE_NONE)
return;
fbc_program_sys_cache(val)
fbc.sys_cache_id = fbc-->id
}
intel_fbc_enable() will call fbc_sys_cache_enable(fbc)
__intel_fbc_disable() will call fbc_sys_cache_disable(fbc)
and
intel_fbc_cleanup() and intel_fbc_sanitize() will call
fbc_sys_cache_reset(display) as a general cleanup for this register.
>
> > +
> > static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc)
> > {
> > if (WARN_ON(intel_fbc_hw_is_active(fbc)))
> > @@ -967,6 +1044,9 @@ void intel_fbc_cleanup(struct intel_display
> > *display)
> >
> > kfree(fbc);
> > }
> > +
> > + if (HAS_FBC_SYS_CACHE(display))
> > + xe3p_lpd_fbc_clear_sys_cache_usage(display);
>
> I don't think this should check for HAS_FBC_SYS_CACHE(). I think
> internally the function being called should check if sys cache has
> been
> set. And make sure it's only set on where it's available.
>
> > }
> >
> > static bool i8xx_fbc_stride_is_valid(const struct
> > intel_plane_state *plane_state)
> > @@ -1780,6 +1860,9 @@ static void __intel_fbc_disable(struct
> > intel_fbc *fbc)
> >
> > __intel_fbc_cleanup_cfb(fbc);
> >
> > + if (HAS_FBC_SYS_CACHE(display))
> > + xe3p_lpd_fbc_update_sys_cache_usage(fbc, false);
> > +
>
> Ditto. I'm also not sure why some places call the version with
> params,
> and some others the version without params.
>
> > /* wa_18038517565 Enable DPFC clock gating after FBC
> > disable */
> > if (display->platform.dg2 || DISPLAY_VER(display) >= 14)
> > fbc_compressor_clkgate_disable_wa(fbc, false);
> > @@ -1972,6 +2055,9 @@ static void __intel_fbc_enable(struct
> > intel_atomic_state *state,
> >
> > intel_fbc_program_workarounds(fbc);
> > intel_fbc_program_cfb(fbc);
> > +
> > + if (HAS_FBC_SYS_CACHE(display))
> > + xe3p_lpd_fbc_update_sys_cache_usage(fbc, true);
>
> xe3p_lpd_fbc_update_sys_cache_usage() is the function that should
> check
> for HAS_FBC_SYS_CACHE() in one place.
>
> Well, maybe it should be renamed fbc_sys_cache_enable().
>
> > }
> >
> > /**
> > @@ -2212,6 +2298,9 @@ void intel_fbc_init(struct intel_display
> > *display)
> >
> > for_each_fbc_id(display, fbc_id)
> > display->fbc.instances[fbc_id] =
> > intel_fbc_create(display, fbc_id);
> > +
> > + /* Mark that no FBC instance is using the system cache */
> > + xe3p_lpd_fbc_set_sys_cache_fbc_id(display,
> > SYS_CACHE_FBC_INSTANCE_NONE);
> > }
> >
> > /**
> > @@ -2231,6 +2320,10 @@ void intel_fbc_sanitize(struct intel_display
> > *display)
> > if (intel_fbc_hw_is_active(fbc))
> > intel_fbc_hw_deactivate(fbc);
> > }
> > +
> > + /* Ensure the sys cache usage register gets cleared */
> > + if (HAS_FBC_SYS_CACHE(display))
> > + xe3p_lpd_fbc_clear_sys_cache_usage(display);
>
> Ditto about checking for valid sys cache inside, not
> HAS_FBC_SYS_CACHE().
>
> > }
> >
> > static int intel_fbc_debugfs_status_show(struct seq_file *m, void
> > *unused)
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> > b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> > index b1d0161a3196..d2d889fa4bed 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> > @@ -126,4 +126,14 @@
> > #define FBC_REND_NUKE REG_BIT(2)
> > #define FBC_REND_CACHE_CLEAN REG_BIT(1)
> >
> > +#define XE3P_LPD_FBC_SYS_CACHE_USAGE_CFG _MMIO(0x1344E0)
> > +#define
> > FBC_SYS_CACHE_START_BASE_MASK REG_GENMASK(31, 16)
> > +#define
> > FBC_SYS_CACHE_START_BASE(base) REG_FIELD_PREP(FBC_SYS_CACHE_START_BASE_MASK,(base))
> > +#define FBC_SYS_CACHEABLE_RANGE_MASK REG_GENMASK(15, 4)
> > +#define
> > FBC_SYS_CACHEABLE_RANGE(range) REG_FIELD_PREP(FBC_SYS_CACHEABLE_RANGE_MASK,(range))
> > +#define FBC_SYS_CACHE_TAG_MASK REG_GENMASK(3, 2)
> > +#define
> > FBC_SYS_CACHE_TAG_DONT_CACHE REG_FIELD_PREP(FBC_SYS_CACHE_TAG_MASK,0)
> > +#define
> > FBC_SYS_CACHE_TAG_USE_RES_SPACE REG_FIELD_PREP(FBC_SYS_CACHE_TAG_MASK,3)
> > +#define FBC_SYS_CACHE_READ_ENABLE REG_BIT(0)
> > +
> > #endif /* __INTEL_FBC_REGS__ */
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v3 2/2] drm/i915/xe3p_lpd: Enable display use of system cache for FBC
2025-11-24 13:32 ` Govindapillai, Vinod
@ 2025-11-24 16:23 ` Jani Nikula
0 siblings, 0 replies; 14+ messages in thread
From: Jani Nikula @ 2025-11-24 16:23 UTC (permalink / raw)
To: Govindapillai, Vinod, intel-xe@lists.freedesktop.org,
intel-gfx@lists.freedesktop.org
Cc: Sousa, Gustavo, Roper, Matthew D, Syrjala, Ville
On Mon, 24 Nov 2025, "Govindapillai, Vinod" <vinod.govindapillai@intel.com> wrote:
> Hi Jani,
>
> Thanks for the input.. replies inline...
>
> On Mon, 2025-11-24 at 13:27 +0200, Jani Nikula wrote:
>> On Sun, 23 Nov 2025, Vinod Govindapillai
>> <vinod.govindapillai@intel.com> wrote:
>> > One of the FBC instances can utilize the reserved area of SoC
>> > level cache for the fbc transactions to benefit reduced memory
>> > system power especially in idle scenarios. Reserved area of the
>> > system cache can be assigned to an fbc instance by configuring
>> > the cacheability configuration register with offset of the
>> > compressed frame buffer in stolen memoty of that fbc. There is
>> > a limit to this reserved area which is programmable and for
>> > xe3p_lpd the limit is defined as 2MB.
>> >
>> > v2: - better to track fbc sys cache usage from intel_display level,
>> > sanitize the cacheability config register on probe (Matt)
>> > - limit this for integrated graphics solutions, confirmed that
>> > no default value set for cache range by hw (Gustavo)
>> >
>> > v3: - changes related to the use of fbc substruct in intel_display
>> > - use intel_de_write() instead of intel_rmw() by hardcoding the
>> > default value fields
>> >
>>
>> I think overall the implementation feels a bit overwhelming. I mean
>> there are so many functions, so many checks, to the point of being
>> excessive.
>>
>> Some comments inline.
>>
>> > Bspec: 68881, 74722
>> > Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
>> > ---
>> > .../gpu/drm/i915/display/intel_display_core.h | 3 +
>> > .../drm/i915/display/intel_display_device.h | 1 +
>> > drivers/gpu/drm/i915/display/intel_fbc.c | 93
>> > +++++++++++++++++++
>> > drivers/gpu/drm/i915/display/intel_fbc_regs.h | 10 ++
>> > 4 files changed, 107 insertions(+)
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
>> > b/drivers/gpu/drm/i915/display/intel_display_core.h
>> > index 58325f530670..f557c9293d33 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_display_core.h
>> > +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
>> > @@ -400,6 +400,9 @@ struct intel_display {
>> >
>> > struct {
>> > struct intel_fbc *instances[I915_MAX_FBCS];
>> > +
>> > + /* xe3p_lpd+ : FBC instance utlizing the system
>> > cache */
>>
>> Please no space before :, *utilizing
>>
>> > + enum intel_fbc_id sys_cache_id;
>> > } fbc;
>> >
>> > struct {
>> > diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h
>> > b/drivers/gpu/drm/i915/display/intel_display_device.h
>> > index b559ef43d547..b74cb69ccc85 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_display_device.h
>> > +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
>> > @@ -173,6 +173,7 @@ struct intel_display_platforms {
>> > #define HAS_DSC_MST(__display) (DISPLAY_VER(__display) >=
>> > 12 && HAS_DSC(__display))
>> > #define
>> > HAS_FBC(__display) (DISPLAY_RUNTIME_INFO(__display)->fbc_mask != 0)
>> > #define HAS_FBC_DIRTY_RECT(__display) (DISPLAY_VER(__display) >=
>> > 30)
>> > +#define HAS_FBC_SYS_CACHE(__display) (DISPLAY_VER(__display) >=
>> > 35 && !(__display)->platform.dgfx)
>> > #define
>> > HAS_FPGA_DBG_UNCLAIMED(__display) (DISPLAY_INFO(__display)->has_fpga_dbg)
>> > #define HAS_FW_BLC(__display) (DISPLAY_VER(__display) >=
>> > 3)
>> > #define
>> > HAS_GMBUS_BURST_READ(__display) (DISPLAY_VER(__display) >= 10 || (__display)->platform.kabylake)
>> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
>> > b/drivers/gpu/drm/i915/display/intel_fbc.c
>> > index dcdfcff80de3..d7e913792518 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
>> > @@ -71,6 +71,10 @@
>> > for_each_fbc_id((__display), (__fbc_id)) \
>> > for_each_if((__fbc) = (__display)-
>> > >fbc.instances[(__fbc_id)])
>> >
>> > +#define
>> > SYS_CACHE_FBC_INSTANCE_NONE I915_MAX_FBCS
>> > +#define
>> > IS_SYS_CACHE_FBC_INSTANCE_NONE(__display) ((__display)->fbc.sys_cache_id==SYS_CACHE_FBC_INSTANCE_NONE)
>>
>> The only user of this has !IS_SYS_CACHE_FBC_INSTANCE_NONE(display)
>> i.e. "if not none".
>>
>> Would be more useful to check if it's "set" or "valid", and avoid the
>> double negative. And use a shorter name. Maybe a static inline
>> function.
>>
>> But I'm not even sure the display->fbc.sys_cache_id needs to be
>> abstracted away. It's not a complicated thing, and, more importantly,
>> it's all within the same file. If outside access was needed, yes,
>> abstract, but here, not convinced.
>>
>> Maybe:
>>
>> if (fbc_sys_cache_id_valid(display->fbc.sys_cache_id))
>>
>> I also don't think *all* of these functions should be prefixed with
>> xe3p_lpd_ because that's a monster, and makes all of this difficult
>> to
>> read.
>>
>> > +#define IS_SYS_CACHE_FBC_INSTANCE_EQUALS(__display,
>> > id) ((__display)->fbc.sys_cache_id == (id))
>>
>> I think this feels cumbersome. Why not just check
>>
>> if (display->fbc.sys_cache_id == id)
>>
>> inline, and it's obvious?
>>
>> > +
>> > struct intel_fbc_funcs {
>> > void (*activate)(struct intel_fbc *fbc);
>> > void (*deactivate)(struct intel_fbc *fbc);
>> > @@ -941,6 +945,79 @@ static void
>> > intel_fbc_program_workarounds(struct intel_fbc *fbc)
>> > fbc_compressor_clkgate_disable_wa(fbc, true);
>> > }
>> >
>> > +static void xe3p_lpd_fbc_set_sys_cache_fbc_id(struct intel_display
>> > *display,
>> > + enum intel_fbc_id
>> > fbc_id)
>> > +{
>> > + display->fbc.sys_cache_id = fbc_id;
>> > +}
>>
>> Again, I'm not sure if this function is really needed. Just inline?
>
> Ack for the above suggestions. About the function naming, yeah it is
> indeed bit complex, but was following the functions names being
> followed in this file. Should it be prefixed with nvl /intel or just
> fbc? instead? Any suggestion?
I would honestly just go with fbc_sys_cache_ for all of them. We don't
have to prefix everything in the world with a platform that started a
new feature.
It's different when you deviate from existing functionality for a
platform, and need different implementations for different platforms.
>
>>
>> > +
>> > +static void xe3p_lpd_fbc_commit_sys_cache_usage(struct
>> > intel_display *display,
>> > + u32 reg)
>> > +{
>> > + intel_de_write(display, XE3P_LPD_FBC_SYS_CACHE_USAGE_CFG,
>> > reg);
>> > +}
>>
>> Not sure if this is needed. Just inline?
>
> Two paths update this register - setting up the cache for a fbc and
> clearing it. Also soon there is going to be a workaround implemented
> which we need to disable the read cache enable bit which is set on by
> default. So I was thinking of intercept here and apply the wa
>
> if (intel_display_wa(display, xxxx))
> reg &= ~FBC_SYS_CACHE_READ_ENABLE;
>
>>
>> > +
>> > +static int xe3p_lpd_fbc_get_cache_limit(void)
>> > +{
>> > + /* Default 2MB for xe3p_lpd */
>> > + return 2 * 1024 * 1024;
>> > +}
>>
>> Ditto. Especially odd how this multiplies and the user the divides by
>> 64
>> * 1024.
>
> Initially from HAS my understanding was that this was supposed to be
> set by a pre-os fw and driver dont modify this field. And this can
> change per platform. But from the recent logs fro, these fields are set
> as 0 and has to be programmed by the driver. (I am clarifying this with
> the HW team). Anyway, this need to be variated per platform. In some
> other component such 2MB was hard coded like this. So thought of
> adopting that. Any suggestion?
Okay. But if the function needs to do platform deviation, you'll need to
pass display to it.
>
>
>> > +
>> > +static void xe3p_lpd_fbc_clear_sys_cache_usage(struct
>> > intel_display *display)
>> > +{
>> > + /* Clear all the fields except the default fields */
>> > + u32 default_fields = FBC_SYS_CACHE_READ_ENABLE;
>> > +
>> > + xe3p_lpd_fbc_commit_sys_cache_usage(display,
>> > default_fields);
>> > +
>> > + /* Mark that no FBC instance utilize the system cache */
>> > + xe3p_lpd_fbc_set_sys_cache_fbc_id(display,
>> > SYS_CACHE_FBC_INSTANCE_NONE);
>> > +}
>>
>> My point above is that this function only calls wrappers and really
>> does
>> nothing itself. It's too many layers for a simple thing.
>>
>> fbc_sys_cache_disable()?
>>
>> > +
>> > +static void xe3p_lpd_fbc_set_sys_cache_usage(const struct
>> > intel_fbc *fbc)
>> > +{
>> > + struct intel_display *display = fbc->display;
>> > + /* limit to be configured to the register in 64k byte
>> > chunks */
>> > + int range = xe3p_lpd_fbc_get_cache_limit() / (64 * 1024);
>> > + /* offset to be configured to the register in 4K byte
>> > chunks */
>> > + int offset = i915_gem_stolen_node_offset(fbc-
>> > >compressed_fb) / (4 * 1024);
>> > + /* Cache read enable is enabled by default */
>> > + u32 usage = FBC_SYS_CACHE_TAG_USE_RES_SPACE |
>> > + FBC_SYS_CACHEABLE_RANGE(range) |
>> > + FBC_SYS_CACHE_START_BASE(offset) |
>> > + FBC_SYS_CACHE_READ_ENABLE;
>> > +
>> > + lockdep_assert_held(&fbc->lock);
>> > +
>> > + xe3p_lpd_fbc_commit_sys_cache_usage(display, usage);
>> > +
>> > + xe3p_lpd_fbc_set_sys_cache_fbc_id(display, fbc->id);
>> > +}
>>
>> Ditto.
>>
>> fbc_sys_cache_enable()?
>>
>> > +
>> > +static void xe3p_lpd_fbc_update_sys_cache_usage(const struct
>> > intel_fbc *fbc,
>> > + bool set)
>> > +{
>> > + struct intel_display *display = fbc->display;
>> > +
>> > + lockdep_assert_held(&fbc->lock);
>> > +
>> > + /* system cache for fbc already reserved */
>> > + if (set && !IS_SYS_CACHE_FBC_INSTANCE_NONE(display))
>> > + return;
>> > +
>> > + /* cannot clear if "fbc" did not reserve the cache */
>> > + if (!set && !IS_SYS_CACHE_FBC_INSTANCE_EQUALS(display,
>> > fbc->id))
>> > + return;
>> > +
>> > + if (set)
>> > + xe3p_lpd_fbc_set_sys_cache_usage(fbc);
>> > + else
>> > + xe3p_lpd_fbc_clear_sys_cache_usage(display);
>> > +
>> > + drm_dbg_kms(display->drm, "System cacheability usage for
>> > FBC[%d] %s\n",
>> > + fbc->id, set ? "configured" : "cleared");
>> > +}
>>
>> Most of this function is two separate paths based on the parameter. I
>> think it would benefit from actually being two separate functions. So
>> why not just merge this with xe3p_lpd_fbc_set_sys_cache_usage() and
>> xe3p_lpd_fbc_clear_sys_cache_usage()?
>
> Actually there are three paths to update this register (two separate
> path to clear this register)
>
> 1. As part of enable FBC - depends on the fbc instance (with fbc mutex
> taken). If sys_cache is not reserved by any other instance.
>
> 2. As part of disable FBC - depends on the fbc instance to avoid
> clearing if this fbc didnt reserve the cache space. (with fbc mutex
> taken)
>
> 3. Clear this register as part of sanitize call (upon setup_hw_state()
> calls upon probe and resume) and intel_fbc_cleanup() upon module
> removal. Not depend on the fbc instance.
Shouldn't fbc have been disabled by the time of module removal? I think
the per fbc disable should've been called already, no?
I think you could add a drm_WARN_ON(fbc.sys_cache_id !=
SYS_CACHE_FBC_INSTANCE_NONE) in the module removal path instead.
Btw that could also be renamed FBC_SYS_CACHE_ID_NONE or something.
> So something like this make sense?
>
> fbc_program_sys_cache(u32 reg)
> {
> intel_de_write(reg)
> }
I'm personally not a fan of "program" in pretty much any function
naming. What does it mean to program something? Isn't the whole driver
programming the hardare?
Just fbc_sys_cache_write()?
> fbc_sys_cache_reset(display)
> {
> if (!HAS_FBC_SYS_CACHE())
> return
>
> fbc_program_sys_cache(0)
> fbc.sys_cache_id = SYS_CACHE_FBC_INSTANCE_NONE
> }
>
> fbc_sys_cache_disable(fbc)
> {
> if (!HAS_FBC_SYS_CACHE())
> return
You don't need this check, because...
>
> if (fbc.sys_cache_id != fbc->id)
> return;
...this will catch the same conditions.
>
> fbc_sys_cache_reset(display)
> }
>
> fbc_sys_cache_enable(fbc)
> {
> if (!HAS_FBC_SYS_CACHE())
> return
>
> if (fbc.sys_cache_id != SYS_CACHE_FBC_INSTANCE_NONE)
> return;
>
> fbc_program_sys_cache(val)
>
> fbc.sys_cache_id = fbc-->id
> }
>
> intel_fbc_enable() will call fbc_sys_cache_enable(fbc)
>
> __intel_fbc_disable() will call fbc_sys_cache_disable(fbc)
>
> and
>
> intel_fbc_cleanup() and intel_fbc_sanitize() will call
> fbc_sys_cache_reset(display) as a general cleanup for this register.
Overall sounds better, but I'll probably need to see the patches to
grasp it.
The fbc debugfs should also have the info on whether the instance is
using the sys cache.
BR,
Jani.
>
>
>
>>
>> > +
>> > static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc)
>> > {
>> > if (WARN_ON(intel_fbc_hw_is_active(fbc)))
>> > @@ -967,6 +1044,9 @@ void intel_fbc_cleanup(struct intel_display
>> > *display)
>> >
>> > kfree(fbc);
>> > }
>> > +
>> > + if (HAS_FBC_SYS_CACHE(display))
>> > + xe3p_lpd_fbc_clear_sys_cache_usage(display);
>>
>> I don't think this should check for HAS_FBC_SYS_CACHE(). I think
>> internally the function being called should check if sys cache has
>> been
>> set. And make sure it's only set on where it's available.
>>
>> > }
>> >
>> > static bool i8xx_fbc_stride_is_valid(const struct
>> > intel_plane_state *plane_state)
>> > @@ -1780,6 +1860,9 @@ static void __intel_fbc_disable(struct
>> > intel_fbc *fbc)
>> >
>> > __intel_fbc_cleanup_cfb(fbc);
>> >
>> > + if (HAS_FBC_SYS_CACHE(display))
>> > + xe3p_lpd_fbc_update_sys_cache_usage(fbc, false);
>> > +
>>
>> Ditto. I'm also not sure why some places call the version with
>> params,
>> and some others the version without params.
>>
>> > /* wa_18038517565 Enable DPFC clock gating after FBC
>> > disable */
>> > if (display->platform.dg2 || DISPLAY_VER(display) >= 14)
>> > fbc_compressor_clkgate_disable_wa(fbc, false);
>> > @@ -1972,6 +2055,9 @@ static void __intel_fbc_enable(struct
>> > intel_atomic_state *state,
>> >
>> > intel_fbc_program_workarounds(fbc);
>> > intel_fbc_program_cfb(fbc);
>> > +
>> > + if (HAS_FBC_SYS_CACHE(display))
>> > + xe3p_lpd_fbc_update_sys_cache_usage(fbc, true);
>>
>> xe3p_lpd_fbc_update_sys_cache_usage() is the function that should
>> check
>> for HAS_FBC_SYS_CACHE() in one place.
>>
>> Well, maybe it should be renamed fbc_sys_cache_enable().
>>
>> > }
>> >
>> > /**
>> > @@ -2212,6 +2298,9 @@ void intel_fbc_init(struct intel_display
>> > *display)
>> >
>> > for_each_fbc_id(display, fbc_id)
>> > display->fbc.instances[fbc_id] =
>> > intel_fbc_create(display, fbc_id);
>> > +
>> > + /* Mark that no FBC instance is using the system cache */
>> > + xe3p_lpd_fbc_set_sys_cache_fbc_id(display,
>> > SYS_CACHE_FBC_INSTANCE_NONE);
>> > }
>> >
>> > /**
>> > @@ -2231,6 +2320,10 @@ void intel_fbc_sanitize(struct intel_display
>> > *display)
>> > if (intel_fbc_hw_is_active(fbc))
>> > intel_fbc_hw_deactivate(fbc);
>> > }
>> > +
>> > + /* Ensure the sys cache usage register gets cleared */
>> > + if (HAS_FBC_SYS_CACHE(display))
>> > + xe3p_lpd_fbc_clear_sys_cache_usage(display);
>>
>> Ditto about checking for valid sys cache inside, not
>> HAS_FBC_SYS_CACHE().
>>
>> > }
>> >
>> > static int intel_fbc_debugfs_status_show(struct seq_file *m, void
>> > *unused)
>> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc_regs.h
>> > b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
>> > index b1d0161a3196..d2d889fa4bed 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_fbc_regs.h
>> > +++ b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
>> > @@ -126,4 +126,14 @@
>> > #define FBC_REND_NUKE REG_BIT(2)
>> > #define FBC_REND_CACHE_CLEAN REG_BIT(1)
>> >
>> > +#define XE3P_LPD_FBC_SYS_CACHE_USAGE_CFG _MMIO(0x1344E0)
>> > +#define
>> > FBC_SYS_CACHE_START_BASE_MASK REG_GENMASK(31, 16)
>> > +#define
>> > FBC_SYS_CACHE_START_BASE(base) REG_FIELD_PREP(FBC_SYS_CACHE_START_BASE_MASK,(base))
>> > +#define FBC_SYS_CACHEABLE_RANGE_MASK REG_GENMASK(15, 4)
>> > +#define
>> > FBC_SYS_CACHEABLE_RANGE(range) REG_FIELD_PREP(FBC_SYS_CACHEABLE_RANGE_MASK,(range))
>> > +#define FBC_SYS_CACHE_TAG_MASK REG_GENMASK(3, 2)
>> > +#define
>> > FBC_SYS_CACHE_TAG_DONT_CACHE REG_FIELD_PREP(FBC_SYS_CACHE_TAG_MASK,0)
>> > +#define
>> > FBC_SYS_CACHE_TAG_USE_RES_SPACE REG_FIELD_PREP(FBC_SYS_CACHE_TAG_MASK,3)
>> > +#define FBC_SYS_CACHE_READ_ENABLE REG_BIT(0)
>> > +
>> > #endif /* __INTEL_FBC_REGS__ */
>>
>
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v3 2/2] drm/i915/xe3p_lpd: Enable display use of system cache for FBC
2025-11-23 16:01 ` [PATCH v3 2/2] drm/i915/xe3p_lpd: Enable display use of system cache for FBC Vinod Govindapillai
2025-11-24 11:27 ` Jani Nikula
@ 2025-11-24 16:25 ` Jani Nikula
2025-11-25 8:56 ` Govindapillai, Vinod
1 sibling, 1 reply; 14+ messages in thread
From: Jani Nikula @ 2025-11-24 16:25 UTC (permalink / raw)
To: Vinod Govindapillai, intel-xe, intel-gfx
Cc: vinod.govindapillai, matthew.d.roper, gustavo.sousa,
ville.syrjala
On Sun, 23 Nov 2025, Vinod Govindapillai <vinod.govindapillai@intel.com> wrote:
> One of the FBC instances can utilize the reserved area of SoC
> level cache for the fbc transactions to benefit reduced memory
> system power especially in idle scenarios. Reserved area of the
> system cache can be assigned to an fbc instance by configuring
> the cacheability configuration register with offset of the
> compressed frame buffer in stolen memoty of that fbc. There is
> a limit to this reserved area which is programmable and for
> xe3p_lpd the limit is defined as 2MB.
>
> v2: - better to track fbc sys cache usage from intel_display level,
> sanitize the cacheability config register on probe (Matt)
> - limit this for integrated graphics solutions, confirmed that
> no default value set for cache range by hw (Gustavo)
>
> v3: - changes related to the use of fbc substruct in intel_display
> - use intel_de_write() instead of intel_rmw() by hardcoding the
> default value fields
Overall issue: The fbc mutexes are per fbc instance, but nothing
protects display->fbc.sys_cache_id.
BR,
Jani.
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 14+ messages in thread
* ✗ CI.checkpatch: warning for drm/i915/display: Enable system cache support for FBC
2025-11-23 16:01 [PATCH v3 0/2] drm/i915/display: Enable system cache support for FBC Vinod Govindapillai
2025-11-23 16:01 ` [PATCH v3 1/2] drm/i915/display: Use a sub-struct for fbc operations in intel_display Vinod Govindapillai
2025-11-23 16:01 ` [PATCH v3 2/2] drm/i915/xe3p_lpd: Enable display use of system cache for FBC Vinod Govindapillai
@ 2025-11-25 0:28 ` Patchwork
2025-11-25 0:29 ` ✓ CI.KUnit: success " Patchwork
` (2 subsequent siblings)
5 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2025-11-25 0:28 UTC (permalink / raw)
To: Govindapillai, Vinod; +Cc: intel-xe
== Series Details ==
Series: drm/i915/display: Enable system cache support for FBC
URL : https://patchwork.freedesktop.org/series/157944/
State : warning
== Summary ==
+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
2de9a3901bc28757c7906b454717b64e2a214021
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit c2fcf91b270ff733835efa238caf5422cbb71553
Author: Vinod Govindapillai <vinod.govindapillai@intel.com>
Date: Sun Nov 23 18:01:27 2025 +0200
drm/i915/xe3p_lpd: Enable display use of system cache for FBC
One of the FBC instances can utilize the reserved area of SoC
level cache for the fbc transactions to benefit reduced memory
system power especially in idle scenarios. Reserved area of the
system cache can be assigned to an fbc instance by configuring
the cacheability configuration register with offset of the
compressed frame buffer in stolen memoty of that fbc. There is
a limit to this reserved area which is programmable and for
xe3p_lpd the limit is defined as 2MB.
v2: - better to track fbc sys cache usage from intel_display level,
sanitize the cacheability config register on probe (Matt)
- limit this for integrated graphics solutions, confirmed that
no default value set for cache range by hw (Gustavo)
v3: - changes related to the use of fbc substruct in intel_display
- use intel_de_write() instead of intel_rmw() by hardcoding the
default value fields
Bspec: 68881, 74722
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
+ /mt/dim checkpatch c701e79730169fab373fba7e759497d755fac592 drm-intel
670ae5f498a7 drm/i915/display: Use a sub-struct for fbc operations in intel_display
c2fcf91b270f drm/i915/xe3p_lpd: Enable display use of system cache for FBC
-:49: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#49: FILE: drivers/gpu/drm/i915/display/intel_display_device.h:176:
+#define HAS_FBC_SYS_CACHE(__display) (DISPLAY_VER(__display) >= 35 && !(__display)->platform.dgfx)
-:49: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__display' - possible side-effects?
#49: FILE: drivers/gpu/drm/i915/display/intel_display_device.h:176:
+#define HAS_FBC_SYS_CACHE(__display) (DISPLAY_VER(__display) >= 35 && !(__display)->platform.dgfx)
-:62: WARNING:LONG_LINE: line length of 118 exceeds 100 columns
#62: FILE: drivers/gpu/drm/i915/display/intel_fbc.c:75:
+#define IS_SYS_CACHE_FBC_INSTANCE_NONE(__display) ((__display)->fbc.sys_cache_id == SYS_CACHE_FBC_INSTANCE_NONE)
-:209: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#209: FILE: drivers/gpu/drm/i915/display/intel_fbc_regs.h:131:
+#define FBC_SYS_CACHE_START_BASE(base) REG_FIELD_PREP(FBC_SYS_CACHE_START_BASE_MASK, (base))
-:211: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#211: FILE: drivers/gpu/drm/i915/display/intel_fbc_regs.h:133:
+#define FBC_SYS_CACHEABLE_RANGE(range) REG_FIELD_PREP(FBC_SYS_CACHEABLE_RANGE_MASK, (range))
total: 0 errors, 4 warnings, 1 checks, 165 lines checked
^ permalink raw reply [flat|nested] 14+ messages in thread
* ✓ CI.KUnit: success for drm/i915/display: Enable system cache support for FBC
2025-11-23 16:01 [PATCH v3 0/2] drm/i915/display: Enable system cache support for FBC Vinod Govindapillai
` (2 preceding siblings ...)
2025-11-25 0:28 ` ✗ CI.checkpatch: warning for drm/i915/display: Enable system cache support " Patchwork
@ 2025-11-25 0:29 ` Patchwork
2025-11-25 1:07 ` ✓ Xe.CI.BAT: " Patchwork
2025-11-25 3:06 ` ✗ Xe.CI.Full: failure " Patchwork
5 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2025-11-25 0:29 UTC (permalink / raw)
To: Govindapillai, Vinod; +Cc: intel-xe
== Series Details ==
Series: drm/i915/display: Enable system cache support for FBC
URL : https://patchwork.freedesktop.org/series/157944/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[00:28:10] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[00:28:14] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[00:28:45] Starting KUnit Kernel (1/1)...
[00:28:45] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[00:28:45] ================== guc_buf (11 subtests) ===================
[00:28:45] [PASSED] test_smallest
[00:28:45] [PASSED] test_largest
[00:28:45] [PASSED] test_granular
[00:28:45] [PASSED] test_unique
[00:28:45] [PASSED] test_overlap
[00:28:45] [PASSED] test_reusable
[00:28:45] [PASSED] test_too_big
[00:28:45] [PASSED] test_flush
[00:28:45] [PASSED] test_lookup
[00:28:45] [PASSED] test_data
[00:28:45] [PASSED] test_class
[00:28:45] ===================== [PASSED] guc_buf =====================
[00:28:45] =================== guc_dbm (7 subtests) ===================
[00:28:45] [PASSED] test_empty
[00:28:45] [PASSED] test_default
[00:28:45] ======================== test_size ========================
[00:28:45] [PASSED] 4
[00:28:45] [PASSED] 8
[00:28:45] [PASSED] 32
[00:28:45] [PASSED] 256
[00:28:45] ==================== [PASSED] test_size ====================
[00:28:45] ======================= test_reuse ========================
[00:28:45] [PASSED] 4
[00:28:45] [PASSED] 8
[00:28:45] [PASSED] 32
[00:28:45] [PASSED] 256
[00:28:45] =================== [PASSED] test_reuse ====================
[00:28:45] =================== test_range_overlap ====================
[00:28:45] [PASSED] 4
[00:28:45] [PASSED] 8
[00:28:45] [PASSED] 32
[00:28:45] [PASSED] 256
[00:28:45] =============== [PASSED] test_range_overlap ================
[00:28:45] =================== test_range_compact ====================
[00:28:45] [PASSED] 4
[00:28:45] [PASSED] 8
[00:28:45] [PASSED] 32
[00:28:45] [PASSED] 256
[00:28:45] =============== [PASSED] test_range_compact ================
[00:28:45] ==================== test_range_spare =====================
[00:28:45] [PASSED] 4
[00:28:45] [PASSED] 8
[00:28:45] [PASSED] 32
[00:28:45] [PASSED] 256
[00:28:45] ================ [PASSED] test_range_spare =================
[00:28:45] ===================== [PASSED] guc_dbm =====================
[00:28:45] =================== guc_idm (6 subtests) ===================
[00:28:45] [PASSED] bad_init
[00:28:45] [PASSED] no_init
[00:28:45] [PASSED] init_fini
[00:28:45] [PASSED] check_used
[00:28:45] [PASSED] check_quota
[00:28:45] [PASSED] check_all
[00:28:45] ===================== [PASSED] guc_idm =====================
[00:28:45] ================== no_relay (3 subtests) ===================
[00:28:45] [PASSED] xe_drops_guc2pf_if_not_ready
[00:28:45] [PASSED] xe_drops_guc2vf_if_not_ready
[00:28:45] [PASSED] xe_rejects_send_if_not_ready
[00:28:45] ==================== [PASSED] no_relay =====================
[00:28:45] ================== pf_relay (14 subtests) ==================
[00:28:45] [PASSED] pf_rejects_guc2pf_too_short
[00:28:45] [PASSED] pf_rejects_guc2pf_too_long
[00:28:45] [PASSED] pf_rejects_guc2pf_no_payload
[00:28:45] [PASSED] pf_fails_no_payload
[00:28:45] [PASSED] pf_fails_bad_origin
[00:28:45] [PASSED] pf_fails_bad_type
[00:28:45] [PASSED] pf_txn_reports_error
[00:28:45] [PASSED] pf_txn_sends_pf2guc
[00:28:45] [PASSED] pf_sends_pf2guc
[00:28:45] [SKIPPED] pf_loopback_nop
[00:28:45] [SKIPPED] pf_loopback_echo
[00:28:45] [SKIPPED] pf_loopback_fail
[00:28:45] [SKIPPED] pf_loopback_busy
[00:28:45] [SKIPPED] pf_loopback_retry
[00:28:45] ==================== [PASSED] pf_relay =====================
[00:28:45] ================== vf_relay (3 subtests) ===================
[00:28:45] [PASSED] vf_rejects_guc2vf_too_short
[00:28:45] [PASSED] vf_rejects_guc2vf_too_long
[00:28:45] [PASSED] vf_rejects_guc2vf_no_payload
[00:28:45] ==================== [PASSED] vf_relay =====================
[00:28:45] ================ pf_gt_config (6 subtests) =================
[00:28:45] [PASSED] fair_contexts_1vf
[00:28:45] [PASSED] fair_doorbells_1vf
[00:28:45] [PASSED] fair_ggtt_1vf
[00:28:45] ====================== fair_contexts ======================
[00:28:45] [PASSED] 1 VF
[00:28:45] [PASSED] 2 VFs
[00:28:45] [PASSED] 3 VFs
[00:28:45] [PASSED] 4 VFs
[00:28:45] [PASSED] 5 VFs
[00:28:45] [PASSED] 6 VFs
[00:28:45] [PASSED] 7 VFs
[00:28:45] [PASSED] 8 VFs
[00:28:45] [PASSED] 9 VFs
[00:28:45] [PASSED] 10 VFs
[00:28:45] [PASSED] 11 VFs
[00:28:45] [PASSED] 12 VFs
[00:28:45] [PASSED] 13 VFs
[00:28:45] [PASSED] 14 VFs
[00:28:45] [PASSED] 15 VFs
[00:28:45] [PASSED] 16 VFs
[00:28:45] [PASSED] 17 VFs
[00:28:45] [PASSED] 18 VFs
[00:28:45] [PASSED] 19 VFs
[00:28:45] [PASSED] 20 VFs
[00:28:45] [PASSED] 21 VFs
[00:28:45] [PASSED] 22 VFs
[00:28:45] [PASSED] 23 VFs
[00:28:45] [PASSED] 24 VFs
[00:28:45] [PASSED] 25 VFs
[00:28:45] [PASSED] 26 VFs
[00:28:45] [PASSED] 27 VFs
[00:28:45] [PASSED] 28 VFs
[00:28:45] [PASSED] 29 VFs
[00:28:45] [PASSED] 30 VFs
[00:28:45] [PASSED] 31 VFs
[00:28:45] [PASSED] 32 VFs
[00:28:45] [PASSED] 33 VFs
[00:28:45] [PASSED] 34 VFs
[00:28:45] [PASSED] 35 VFs
[00:28:45] [PASSED] 36 VFs
[00:28:45] [PASSED] 37 VFs
[00:28:45] [PASSED] 38 VFs
[00:28:45] [PASSED] 39 VFs
[00:28:45] [PASSED] 40 VFs
[00:28:45] [PASSED] 41 VFs
[00:28:45] [PASSED] 42 VFs
[00:28:45] [PASSED] 43 VFs
[00:28:45] [PASSED] 44 VFs
[00:28:45] [PASSED] 45 VFs
[00:28:45] [PASSED] 46 VFs
[00:28:45] [PASSED] 47 VFs
[00:28:45] [PASSED] 48 VFs
[00:28:45] [PASSED] 49 VFs
[00:28:45] [PASSED] 50 VFs
[00:28:45] [PASSED] 51 VFs
[00:28:45] [PASSED] 52 VFs
[00:28:45] [PASSED] 53 VFs
[00:28:45] [PASSED] 54 VFs
[00:28:45] [PASSED] 55 VFs
[00:28:45] [PASSED] 56 VFs
[00:28:45] [PASSED] 57 VFs
[00:28:45] [PASSED] 58 VFs
[00:28:45] [PASSED] 59 VFs
[00:28:45] [PASSED] 60 VFs
[00:28:45] [PASSED] 61 VFs
[00:28:45] [PASSED] 62 VFs
[00:28:45] [PASSED] 63 VFs
[00:28:45] ================== [PASSED] fair_contexts ==================
[00:28:45] ===================== fair_doorbells ======================
[00:28:45] [PASSED] 1 VF
[00:28:45] [PASSED] 2 VFs
[00:28:45] [PASSED] 3 VFs
[00:28:45] [PASSED] 4 VFs
[00:28:45] [PASSED] 5 VFs
[00:28:45] [PASSED] 6 VFs
[00:28:45] [PASSED] 7 VFs
[00:28:45] [PASSED] 8 VFs
[00:28:45] [PASSED] 9 VFs
[00:28:45] [PASSED] 10 VFs
[00:28:45] [PASSED] 11 VFs
[00:28:45] [PASSED] 12 VFs
[00:28:45] [PASSED] 13 VFs
[00:28:45] [PASSED] 14 VFs
[00:28:45] [PASSED] 15 VFs
[00:28:45] [PASSED] 16 VFs
[00:28:45] [PASSED] 17 VFs
[00:28:45] [PASSED] 18 VFs
[00:28:45] [PASSED] 19 VFs
[00:28:45] [PASSED] 20 VFs
[00:28:45] [PASSED] 21 VFs
[00:28:45] [PASSED] 22 VFs
[00:28:45] [PASSED] 23 VFs
[00:28:45] [PASSED] 24 VFs
[00:28:45] [PASSED] 25 VFs
[00:28:45] [PASSED] 26 VFs
[00:28:45] [PASSED] 27 VFs
[00:28:45] [PASSED] 28 VFs
[00:28:45] [PASSED] 29 VFs
[00:28:45] [PASSED] 30 VFs
[00:28:45] [PASSED] 31 VFs
[00:28:45] [PASSED] 32 VFs
[00:28:45] [PASSED] 33 VFs
[00:28:45] [PASSED] 34 VFs
[00:28:45] [PASSED] 35 VFs
[00:28:45] [PASSED] 36 VFs
[00:28:45] [PASSED] 37 VFs
[00:28:45] [PASSED] 38 VFs
[00:28:45] [PASSED] 39 VFs
[00:28:45] [PASSED] 40 VFs
[00:28:45] [PASSED] 41 VFs
[00:28:45] [PASSED] 42 VFs
[00:28:45] [PASSED] 43 VFs
[00:28:45] [PASSED] 44 VFs
[00:28:45] [PASSED] 45 VFs
[00:28:45] [PASSED] 46 VFs
[00:28:45] [PASSED] 47 VFs
[00:28:45] [PASSED] 48 VFs
[00:28:45] [PASSED] 49 VFs
[00:28:45] [PASSED] 50 VFs
[00:28:45] [PASSED] 51 VFs
[00:28:45] [PASSED] 52 VFs
[00:28:45] [PASSED] 53 VFs
[00:28:45] [PASSED] 54 VFs
[00:28:45] [PASSED] 55 VFs
[00:28:45] [PASSED] 56 VFs
[00:28:45] [PASSED] 57 VFs
[00:28:45] [PASSED] 58 VFs
[00:28:45] [PASSED] 59 VFs
[00:28:45] [PASSED] 60 VFs
[00:28:45] [PASSED] 61 VFs
[00:28:45] [PASSED] 62 VFs
[00:28:45] [PASSED] 63 VFs
[00:28:45] ================= [PASSED] fair_doorbells ==================
[00:28:45] ======================== fair_ggtt ========================
[00:28:45] [PASSED] 1 VF
[00:28:45] [PASSED] 2 VFs
[00:28:45] [PASSED] 3 VFs
[00:28:45] [PASSED] 4 VFs
[00:28:45] [PASSED] 5 VFs
[00:28:45] [PASSED] 6 VFs
[00:28:45] [PASSED] 7 VFs
[00:28:45] [PASSED] 8 VFs
[00:28:45] [PASSED] 9 VFs
[00:28:45] [PASSED] 10 VFs
[00:28:45] [PASSED] 11 VFs
[00:28:45] [PASSED] 12 VFs
[00:28:45] [PASSED] 13 VFs
[00:28:45] [PASSED] 14 VFs
[00:28:45] [PASSED] 15 VFs
[00:28:45] [PASSED] 16 VFs
[00:28:45] [PASSED] 17 VFs
[00:28:45] [PASSED] 18 VFs
[00:28:45] [PASSED] 19 VFs
[00:28:45] [PASSED] 20 VFs
[00:28:45] [PASSED] 21 VFs
[00:28:45] [PASSED] 22 VFs
[00:28:45] [PASSED] 23 VFs
[00:28:45] [PASSED] 24 VFs
[00:28:45] [PASSED] 25 VFs
[00:28:45] [PASSED] 26 VFs
[00:28:45] [PASSED] 27 VFs
[00:28:45] [PASSED] 28 VFs
[00:28:45] [PASSED] 29 VFs
[00:28:45] [PASSED] 30 VFs
[00:28:45] [PASSED] 31 VFs
[00:28:45] [PASSED] 32 VFs
[00:28:45] [PASSED] 33 VFs
[00:28:45] [PASSED] 34 VFs
[00:28:45] [PASSED] 35 VFs
[00:28:45] [PASSED] 36 VFs
[00:28:45] [PASSED] 37 VFs
[00:28:45] [PASSED] 38 VFs
[00:28:45] [PASSED] 39 VFs
[00:28:45] [PASSED] 40 VFs
[00:28:45] [PASSED] 41 VFs
[00:28:45] [PASSED] 42 VFs
[00:28:45] [PASSED] 43 VFs
[00:28:45] [PASSED] 44 VFs
[00:28:46] [PASSED] 45 VFs
[00:28:46] [PASSED] 46 VFs
[00:28:46] [PASSED] 47 VFs
[00:28:46] [PASSED] 48 VFs
[00:28:46] [PASSED] 49 VFs
[00:28:46] [PASSED] 50 VFs
[00:28:46] [PASSED] 51 VFs
[00:28:46] [PASSED] 52 VFs
[00:28:46] [PASSED] 53 VFs
[00:28:46] [PASSED] 54 VFs
[00:28:46] [PASSED] 55 VFs
[00:28:46] [PASSED] 56 VFs
[00:28:46] [PASSED] 57 VFs
[00:28:46] [PASSED] 58 VFs
[00:28:46] [PASSED] 59 VFs
[00:28:46] [PASSED] 60 VFs
[00:28:46] [PASSED] 61 VFs
[00:28:46] [PASSED] 62 VFs
[00:28:46] [PASSED] 63 VFs
[00:28:46] ==================== [PASSED] fair_ggtt ====================
[00:28:46] ================== [PASSED] pf_gt_config ===================
[00:28:46] ===================== lmtt (1 subtest) =====================
[00:28:46] ======================== test_ops =========================
[00:28:46] [PASSED] 2-level
[00:28:46] [PASSED] multi-level
[00:28:46] ==================== [PASSED] test_ops =====================
[00:28:46] ====================== [PASSED] lmtt =======================
[00:28:46] ================= pf_service (11 subtests) =================
[00:28:46] [PASSED] pf_negotiate_any
[00:28:46] [PASSED] pf_negotiate_base_match
[00:28:46] [PASSED] pf_negotiate_base_newer
[00:28:46] [PASSED] pf_negotiate_base_next
[00:28:46] [SKIPPED] pf_negotiate_base_older
[00:28:46] [PASSED] pf_negotiate_base_prev
[00:28:46] [PASSED] pf_negotiate_latest_match
[00:28:46] [PASSED] pf_negotiate_latest_newer
[00:28:46] [PASSED] pf_negotiate_latest_next
[00:28:46] [SKIPPED] pf_negotiate_latest_older
[00:28:46] [SKIPPED] pf_negotiate_latest_prev
[00:28:46] =================== [PASSED] pf_service ====================
[00:28:46] ================= xe_guc_g2g (2 subtests) ==================
[00:28:46] ============== xe_live_guc_g2g_kunit_default ==============
[00:28:46] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[00:28:46] ============== xe_live_guc_g2g_kunit_allmem ===============
[00:28:46] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[00:28:46] =================== [SKIPPED] xe_guc_g2g ===================
[00:28:46] =================== xe_mocs (2 subtests) ===================
[00:28:46] ================ xe_live_mocs_kernel_kunit ================
[00:28:46] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[00:28:46] ================ xe_live_mocs_reset_kunit =================
[00:28:46] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[00:28:46] ==================== [SKIPPED] xe_mocs =====================
[00:28:46] ================= xe_migrate (2 subtests) ==================
[00:28:46] ================= xe_migrate_sanity_kunit =================
[00:28:46] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[00:28:46] ================== xe_validate_ccs_kunit ==================
[00:28:46] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[00:28:46] =================== [SKIPPED] xe_migrate ===================
[00:28:46] ================== xe_dma_buf (1 subtest) ==================
[00:28:46] ==================== xe_dma_buf_kunit =====================
[00:28:46] ================ [SKIPPED] xe_dma_buf_kunit ================
[00:28:46] =================== [SKIPPED] xe_dma_buf ===================
[00:28:46] ================= xe_bo_shrink (1 subtest) =================
[00:28:46] =================== xe_bo_shrink_kunit ====================
[00:28:46] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[00:28:46] ================== [SKIPPED] xe_bo_shrink ==================
[00:28:46] ==================== xe_bo (2 subtests) ====================
[00:28:46] ================== xe_ccs_migrate_kunit ===================
[00:28:46] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[00:28:46] ==================== xe_bo_evict_kunit ====================
[00:28:46] =============== [SKIPPED] xe_bo_evict_kunit ================
[00:28:46] ===================== [SKIPPED] xe_bo ======================
[00:28:46] ==================== args (11 subtests) ====================
[00:28:46] [PASSED] count_args_test
[00:28:46] [PASSED] call_args_example
[00:28:46] [PASSED] call_args_test
[00:28:46] [PASSED] drop_first_arg_example
[00:28:46] [PASSED] drop_first_arg_test
[00:28:46] [PASSED] first_arg_example
[00:28:46] [PASSED] first_arg_test
[00:28:46] [PASSED] last_arg_example
[00:28:46] [PASSED] last_arg_test
[00:28:46] [PASSED] pick_arg_example
[00:28:46] [PASSED] sep_comma_example
[00:28:46] ====================== [PASSED] args =======================
[00:28:46] =================== xe_pci (3 subtests) ====================
[00:28:46] ==================== check_graphics_ip ====================
[00:28:46] [PASSED] 12.00 Xe_LP
[00:28:46] [PASSED] 12.10 Xe_LP+
[00:28:46] [PASSED] 12.55 Xe_HPG
[00:28:46] [PASSED] 12.60 Xe_HPC
[00:28:46] [PASSED] 12.70 Xe_LPG
[00:28:46] [PASSED] 12.71 Xe_LPG
[00:28:46] [PASSED] 12.74 Xe_LPG+
[00:28:46] [PASSED] 20.01 Xe2_HPG
[00:28:46] [PASSED] 20.02 Xe2_HPG
[00:28:46] [PASSED] 20.04 Xe2_LPG
[00:28:46] [PASSED] 30.00 Xe3_LPG
[00:28:46] [PASSED] 30.01 Xe3_LPG
[00:28:46] [PASSED] 30.03 Xe3_LPG
[00:28:46] [PASSED] 30.04 Xe3_LPG
[00:28:46] [PASSED] 30.05 Xe3_LPG
[00:28:46] [PASSED] 35.11 Xe3p_XPC
[00:28:46] ================ [PASSED] check_graphics_ip ================
[00:28:46] ===================== check_media_ip ======================
[00:28:46] [PASSED] 12.00 Xe_M
[00:28:46] [PASSED] 12.55 Xe_HPM
[00:28:46] [PASSED] 13.00 Xe_LPM+
[00:28:46] [PASSED] 13.01 Xe2_HPM
[00:28:46] [PASSED] 20.00 Xe2_LPM
[00:28:46] [PASSED] 30.00 Xe3_LPM
[00:28:46] [PASSED] 30.02 Xe3_LPM
[00:28:46] [PASSED] 35.00 Xe3p_LPM
[00:28:46] [PASSED] 35.03 Xe3p_HPM
[00:28:46] ================= [PASSED] check_media_ip ==================
[00:28:46] =================== check_platform_desc ===================
[00:28:46] [PASSED] 0x9A60 (TIGERLAKE)
[00:28:46] [PASSED] 0x9A68 (TIGERLAKE)
[00:28:46] [PASSED] 0x9A70 (TIGERLAKE)
[00:28:46] [PASSED] 0x9A40 (TIGERLAKE)
[00:28:46] [PASSED] 0x9A49 (TIGERLAKE)
[00:28:46] [PASSED] 0x9A59 (TIGERLAKE)
[00:28:46] [PASSED] 0x9A78 (TIGERLAKE)
[00:28:46] [PASSED] 0x9AC0 (TIGERLAKE)
[00:28:46] [PASSED] 0x9AC9 (TIGERLAKE)
[00:28:46] [PASSED] 0x9AD9 (TIGERLAKE)
[00:28:46] [PASSED] 0x9AF8 (TIGERLAKE)
[00:28:46] [PASSED] 0x4C80 (ROCKETLAKE)
[00:28:46] [PASSED] 0x4C8A (ROCKETLAKE)
[00:28:46] [PASSED] 0x4C8B (ROCKETLAKE)
[00:28:46] [PASSED] 0x4C8C (ROCKETLAKE)
[00:28:46] [PASSED] 0x4C90 (ROCKETLAKE)
[00:28:46] [PASSED] 0x4C9A (ROCKETLAKE)
[00:28:46] [PASSED] 0x4680 (ALDERLAKE_S)
[00:28:46] [PASSED] 0x4682 (ALDERLAKE_S)
[00:28:46] [PASSED] 0x4688 (ALDERLAKE_S)
[00:28:46] [PASSED] 0x468A (ALDERLAKE_S)
[00:28:46] [PASSED] 0x468B (ALDERLAKE_S)
[00:28:46] [PASSED] 0x4690 (ALDERLAKE_S)
[00:28:46] [PASSED] 0x4692 (ALDERLAKE_S)
[00:28:46] [PASSED] 0x4693 (ALDERLAKE_S)
[00:28:46] [PASSED] 0x46A0 (ALDERLAKE_P)
[00:28:46] [PASSED] 0x46A1 (ALDERLAKE_P)
[00:28:46] [PASSED] 0x46A2 (ALDERLAKE_P)
[00:28:46] [PASSED] 0x46A3 (ALDERLAKE_P)
[00:28:46] [PASSED] 0x46A6 (ALDERLAKE_P)
[00:28:46] [PASSED] 0x46A8 (ALDERLAKE_P)
[00:28:46] [PASSED] 0x46AA (ALDERLAKE_P)
[00:28:46] [PASSED] 0x462A (ALDERLAKE_P)
[00:28:46] [PASSED] 0x4626 (ALDERLAKE_P)
[00:28:46] [PASSED] 0x4628 (ALDERLAKE_P)
[00:28:46] [PASSED] 0x46B0 (ALDERLAKE_P)
stty: 'standard input': Inappropriate ioctl for device
[00:28:46] [PASSED] 0x46B1 (ALDERLAKE_P)
[00:28:46] [PASSED] 0x46B2 (ALDERLAKE_P)
[00:28:46] [PASSED] 0x46B3 (ALDERLAKE_P)
[00:28:46] [PASSED] 0x46C0 (ALDERLAKE_P)
[00:28:46] [PASSED] 0x46C1 (ALDERLAKE_P)
[00:28:46] [PASSED] 0x46C2 (ALDERLAKE_P)
[00:28:46] [PASSED] 0x46C3 (ALDERLAKE_P)
[00:28:46] [PASSED] 0x46D0 (ALDERLAKE_N)
[00:28:46] [PASSED] 0x46D1 (ALDERLAKE_N)
[00:28:46] [PASSED] 0x46D2 (ALDERLAKE_N)
[00:28:46] [PASSED] 0x46D3 (ALDERLAKE_N)
[00:28:46] [PASSED] 0x46D4 (ALDERLAKE_N)
[00:28:46] [PASSED] 0xA721 (ALDERLAKE_P)
[00:28:46] [PASSED] 0xA7A1 (ALDERLAKE_P)
[00:28:46] [PASSED] 0xA7A9 (ALDERLAKE_P)
[00:28:46] [PASSED] 0xA7AC (ALDERLAKE_P)
[00:28:46] [PASSED] 0xA7AD (ALDERLAKE_P)
[00:28:46] [PASSED] 0xA720 (ALDERLAKE_P)
[00:28:46] [PASSED] 0xA7A0 (ALDERLAKE_P)
[00:28:46] [PASSED] 0xA7A8 (ALDERLAKE_P)
[00:28:46] [PASSED] 0xA7AA (ALDERLAKE_P)
[00:28:46] [PASSED] 0xA7AB (ALDERLAKE_P)
[00:28:46] [PASSED] 0xA780 (ALDERLAKE_S)
[00:28:46] [PASSED] 0xA781 (ALDERLAKE_S)
[00:28:46] [PASSED] 0xA782 (ALDERLAKE_S)
[00:28:46] [PASSED] 0xA783 (ALDERLAKE_S)
[00:28:46] [PASSED] 0xA788 (ALDERLAKE_S)
[00:28:46] [PASSED] 0xA789 (ALDERLAKE_S)
[00:28:46] [PASSED] 0xA78A (ALDERLAKE_S)
[00:28:46] [PASSED] 0xA78B (ALDERLAKE_S)
[00:28:46] [PASSED] 0x4905 (DG1)
[00:28:46] [PASSED] 0x4906 (DG1)
[00:28:46] [PASSED] 0x4907 (DG1)
[00:28:46] [PASSED] 0x4908 (DG1)
[00:28:46] [PASSED] 0x4909 (DG1)
[00:28:46] [PASSED] 0x56C0 (DG2)
[00:28:46] [PASSED] 0x56C2 (DG2)
[00:28:46] [PASSED] 0x56C1 (DG2)
[00:28:46] [PASSED] 0x7D51 (METEORLAKE)
[00:28:46] [PASSED] 0x7DD1 (METEORLAKE)
[00:28:46] [PASSED] 0x7D41 (METEORLAKE)
[00:28:46] [PASSED] 0x7D67 (METEORLAKE)
[00:28:46] [PASSED] 0xB640 (METEORLAKE)
[00:28:46] [PASSED] 0x56A0 (DG2)
[00:28:46] [PASSED] 0x56A1 (DG2)
[00:28:46] [PASSED] 0x56A2 (DG2)
[00:28:46] [PASSED] 0x56BE (DG2)
[00:28:46] [PASSED] 0x56BF (DG2)
[00:28:46] [PASSED] 0x5690 (DG2)
[00:28:46] [PASSED] 0x5691 (DG2)
[00:28:46] [PASSED] 0x5692 (DG2)
[00:28:46] [PASSED] 0x56A5 (DG2)
[00:28:46] [PASSED] 0x56A6 (DG2)
[00:28:46] [PASSED] 0x56B0 (DG2)
[00:28:46] [PASSED] 0x56B1 (DG2)
[00:28:46] [PASSED] 0x56BA (DG2)
[00:28:46] [PASSED] 0x56BB (DG2)
[00:28:46] [PASSED] 0x56BC (DG2)
[00:28:46] [PASSED] 0x56BD (DG2)
[00:28:46] [PASSED] 0x5693 (DG2)
[00:28:46] [PASSED] 0x5694 (DG2)
[00:28:46] [PASSED] 0x5695 (DG2)
[00:28:46] [PASSED] 0x56A3 (DG2)
[00:28:46] [PASSED] 0x56A4 (DG2)
[00:28:46] [PASSED] 0x56B2 (DG2)
[00:28:46] [PASSED] 0x56B3 (DG2)
[00:28:46] [PASSED] 0x5696 (DG2)
[00:28:46] [PASSED] 0x5697 (DG2)
[00:28:46] [PASSED] 0xB69 (PVC)
[00:28:46] [PASSED] 0xB6E (PVC)
[00:28:46] [PASSED] 0xBD4 (PVC)
[00:28:46] [PASSED] 0xBD5 (PVC)
[00:28:46] [PASSED] 0xBD6 (PVC)
[00:28:46] [PASSED] 0xBD7 (PVC)
[00:28:46] [PASSED] 0xBD8 (PVC)
[00:28:46] [PASSED] 0xBD9 (PVC)
[00:28:46] [PASSED] 0xBDA (PVC)
[00:28:46] [PASSED] 0xBDB (PVC)
[00:28:46] [PASSED] 0xBE0 (PVC)
[00:28:46] [PASSED] 0xBE1 (PVC)
[00:28:46] [PASSED] 0xBE5 (PVC)
[00:28:46] [PASSED] 0x7D40 (METEORLAKE)
[00:28:46] [PASSED] 0x7D45 (METEORLAKE)
[00:28:46] [PASSED] 0x7D55 (METEORLAKE)
[00:28:46] [PASSED] 0x7D60 (METEORLAKE)
[00:28:46] [PASSED] 0x7DD5 (METEORLAKE)
[00:28:46] [PASSED] 0x6420 (LUNARLAKE)
[00:28:46] [PASSED] 0x64A0 (LUNARLAKE)
[00:28:46] [PASSED] 0x64B0 (LUNARLAKE)
[00:28:46] [PASSED] 0xE202 (BATTLEMAGE)
[00:28:46] [PASSED] 0xE209 (BATTLEMAGE)
[00:28:46] [PASSED] 0xE20B (BATTLEMAGE)
[00:28:46] [PASSED] 0xE20C (BATTLEMAGE)
[00:28:46] [PASSED] 0xE20D (BATTLEMAGE)
[00:28:46] [PASSED] 0xE210 (BATTLEMAGE)
[00:28:46] [PASSED] 0xE211 (BATTLEMAGE)
[00:28:46] [PASSED] 0xE212 (BATTLEMAGE)
[00:28:46] [PASSED] 0xE216 (BATTLEMAGE)
[00:28:46] [PASSED] 0xE220 (BATTLEMAGE)
[00:28:46] [PASSED] 0xE221 (BATTLEMAGE)
[00:28:46] [PASSED] 0xE222 (BATTLEMAGE)
[00:28:46] [PASSED] 0xE223 (BATTLEMAGE)
[00:28:46] [PASSED] 0xB080 (PANTHERLAKE)
[00:28:46] [PASSED] 0xB081 (PANTHERLAKE)
[00:28:46] [PASSED] 0xB082 (PANTHERLAKE)
[00:28:46] [PASSED] 0xB083 (PANTHERLAKE)
[00:28:46] [PASSED] 0xB084 (PANTHERLAKE)
[00:28:46] [PASSED] 0xB085 (PANTHERLAKE)
[00:28:46] [PASSED] 0xB086 (PANTHERLAKE)
[00:28:46] [PASSED] 0xB087 (PANTHERLAKE)
[00:28:46] [PASSED] 0xB08F (PANTHERLAKE)
[00:28:46] [PASSED] 0xB090 (PANTHERLAKE)
[00:28:46] [PASSED] 0xB0A0 (PANTHERLAKE)
[00:28:46] [PASSED] 0xB0B0 (PANTHERLAKE)
[00:28:46] [PASSED] 0xD740 (NOVALAKE_S)
[00:28:46] [PASSED] 0xD741 (NOVALAKE_S)
[00:28:46] [PASSED] 0xD742 (NOVALAKE_S)
[00:28:46] [PASSED] 0xD743 (NOVALAKE_S)
[00:28:46] [PASSED] 0xD744 (NOVALAKE_S)
[00:28:46] [PASSED] 0xD745 (NOVALAKE_S)
[00:28:46] [PASSED] 0x674C (CRESCENTISLAND)
[00:28:46] [PASSED] 0xFD80 (PANTHERLAKE)
[00:28:46] [PASSED] 0xFD81 (PANTHERLAKE)
[00:28:46] =============== [PASSED] check_platform_desc ===============
[00:28:46] ===================== [PASSED] xe_pci ======================
[00:28:46] =================== xe_rtp (2 subtests) ====================
[00:28:46] =============== xe_rtp_process_to_sr_tests ================
[00:28:46] [PASSED] coalesce-same-reg
[00:28:46] [PASSED] no-match-no-add
[00:28:46] [PASSED] match-or
[00:28:46] [PASSED] match-or-xfail
[00:28:46] [PASSED] no-match-no-add-multiple-rules
[00:28:46] [PASSED] two-regs-two-entries
[00:28:46] [PASSED] clr-one-set-other
[00:28:46] [PASSED] set-field
[00:28:46] [PASSED] conflict-duplicate
[00:28:46] [PASSED] conflict-not-disjoint
[00:28:46] [PASSED] conflict-reg-type
[00:28:46] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[00:28:46] ================== xe_rtp_process_tests ===================
[00:28:46] [PASSED] active1
[00:28:46] [PASSED] active2
[00:28:46] [PASSED] active-inactive
[00:28:46] [PASSED] inactive-active
[00:28:46] [PASSED] inactive-1st_or_active-inactive
[00:28:46] [PASSED] inactive-2nd_or_active-inactive
[00:28:46] [PASSED] inactive-last_or_active-inactive
[00:28:46] [PASSED] inactive-no_or_active-inactive
[00:28:46] ============== [PASSED] xe_rtp_process_tests ===============
[00:28:46] ===================== [PASSED] xe_rtp ======================
[00:28:46] ==================== xe_wa (1 subtest) =====================
[00:28:46] ======================== xe_wa_gt =========================
[00:28:46] [PASSED] TIGERLAKE B0
[00:28:46] [PASSED] DG1 A0
[00:28:46] [PASSED] DG1 B0
[00:28:46] [PASSED] ALDERLAKE_S A0
[00:28:46] [PASSED] ALDERLAKE_S B0
[00:28:46] [PASSED] ALDERLAKE_S C0
[00:28:46] [PASSED] ALDERLAKE_S D0
[00:28:46] [PASSED] ALDERLAKE_P A0
[00:28:46] [PASSED] ALDERLAKE_P B0
[00:28:46] [PASSED] ALDERLAKE_P C0
[00:28:46] [PASSED] ALDERLAKE_S RPLS D0
[00:28:46] [PASSED] ALDERLAKE_P RPLU E0
[00:28:46] [PASSED] DG2 G10 C0
[00:28:46] [PASSED] DG2 G11 B1
[00:28:46] [PASSED] DG2 G12 A1
[00:28:46] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[00:28:46] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[00:28:46] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[00:28:46] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[00:28:46] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[00:28:46] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[00:28:46] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[00:28:46] ==================== [PASSED] xe_wa_gt =====================
[00:28:46] ====================== [PASSED] xe_wa ======================
[00:28:46] ============================================================
[00:28:46] Testing complete. Ran 510 tests: passed: 492, skipped: 18
[00:28:46] Elapsed time: 35.826s total, 4.256s configuring, 31.104s building, 0.458s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[00:28:46] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[00:28:47] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[00:29:12] Starting KUnit Kernel (1/1)...
[00:29:12] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[00:29:13] ============ drm_test_pick_cmdline (2 subtests) ============
[00:29:13] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[00:29:13] =============== drm_test_pick_cmdline_named ===============
[00:29:13] [PASSED] NTSC
[00:29:13] [PASSED] NTSC-J
[00:29:13] [PASSED] PAL
[00:29:13] [PASSED] PAL-M
[00:29:13] =========== [PASSED] drm_test_pick_cmdline_named ===========
[00:29:13] ============== [PASSED] drm_test_pick_cmdline ==============
[00:29:13] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[00:29:13] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[00:29:13] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[00:29:13] =========== drm_validate_clone_mode (2 subtests) ===========
[00:29:13] ============== drm_test_check_in_clone_mode ===============
[00:29:13] [PASSED] in_clone_mode
[00:29:13] [PASSED] not_in_clone_mode
[00:29:13] ========== [PASSED] drm_test_check_in_clone_mode ===========
[00:29:13] =============== drm_test_check_valid_clones ===============
[00:29:13] [PASSED] not_in_clone_mode
[00:29:13] [PASSED] valid_clone
[00:29:13] [PASSED] invalid_clone
[00:29:13] =========== [PASSED] drm_test_check_valid_clones ===========
[00:29:13] ============= [PASSED] drm_validate_clone_mode =============
[00:29:13] ============= drm_validate_modeset (1 subtest) =============
[00:29:13] [PASSED] drm_test_check_connector_changed_modeset
[00:29:13] ============== [PASSED] drm_validate_modeset ===============
[00:29:13] ====== drm_test_bridge_get_current_state (2 subtests) ======
[00:29:13] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[00:29:13] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[00:29:13] ======== [PASSED] drm_test_bridge_get_current_state ========
[00:29:13] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[00:29:13] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[00:29:13] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[00:29:13] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[00:29:13] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[00:29:13] ============== drm_bridge_alloc (2 subtests) ===============
[00:29:13] [PASSED] drm_test_drm_bridge_alloc_basic
[00:29:13] [PASSED] drm_test_drm_bridge_alloc_get_put
[00:29:13] ================ [PASSED] drm_bridge_alloc =================
[00:29:13] ================== drm_buddy (8 subtests) ==================
[00:29:13] [PASSED] drm_test_buddy_alloc_limit
[00:29:13] [PASSED] drm_test_buddy_alloc_optimistic
[00:29:13] [PASSED] drm_test_buddy_alloc_pessimistic
[00:29:13] [PASSED] drm_test_buddy_alloc_pathological
[00:29:13] [PASSED] drm_test_buddy_alloc_contiguous
[00:29:13] [PASSED] drm_test_buddy_alloc_clear
[00:29:13] [PASSED] drm_test_buddy_alloc_range_bias
[00:29:13] [PASSED] drm_test_buddy_fragmentation_performance
[00:29:13] ==================== [PASSED] drm_buddy ====================
[00:29:13] ============= drm_cmdline_parser (40 subtests) =============
[00:29:13] [PASSED] drm_test_cmdline_force_d_only
[00:29:13] [PASSED] drm_test_cmdline_force_D_only_dvi
[00:29:13] [PASSED] drm_test_cmdline_force_D_only_hdmi
[00:29:13] [PASSED] drm_test_cmdline_force_D_only_not_digital
[00:29:13] [PASSED] drm_test_cmdline_force_e_only
[00:29:13] [PASSED] drm_test_cmdline_res
[00:29:13] [PASSED] drm_test_cmdline_res_vesa
[00:29:13] [PASSED] drm_test_cmdline_res_vesa_rblank
[00:29:13] [PASSED] drm_test_cmdline_res_rblank
[00:29:13] [PASSED] drm_test_cmdline_res_bpp
[00:29:13] [PASSED] drm_test_cmdline_res_refresh
[00:29:13] [PASSED] drm_test_cmdline_res_bpp_refresh
[00:29:13] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[00:29:13] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[00:29:13] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[00:29:13] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[00:29:13] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[00:29:13] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[00:29:13] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[00:29:13] [PASSED] drm_test_cmdline_res_margins_force_on
[00:29:13] [PASSED] drm_test_cmdline_res_vesa_margins
[00:29:13] [PASSED] drm_test_cmdline_name
[00:29:13] [PASSED] drm_test_cmdline_name_bpp
[00:29:13] [PASSED] drm_test_cmdline_name_option
[00:29:13] [PASSED] drm_test_cmdline_name_bpp_option
[00:29:13] [PASSED] drm_test_cmdline_rotate_0
[00:29:13] [PASSED] drm_test_cmdline_rotate_90
[00:29:13] [PASSED] drm_test_cmdline_rotate_180
[00:29:13] [PASSED] drm_test_cmdline_rotate_270
[00:29:13] [PASSED] drm_test_cmdline_hmirror
[00:29:13] [PASSED] drm_test_cmdline_vmirror
[00:29:13] [PASSED] drm_test_cmdline_margin_options
[00:29:13] [PASSED] drm_test_cmdline_multiple_options
[00:29:13] [PASSED] drm_test_cmdline_bpp_extra_and_option
[00:29:13] [PASSED] drm_test_cmdline_extra_and_option
[00:29:13] [PASSED] drm_test_cmdline_freestanding_options
[00:29:13] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[00:29:13] [PASSED] drm_test_cmdline_panel_orientation
[00:29:13] ================ drm_test_cmdline_invalid =================
[00:29:13] [PASSED] margin_only
[00:29:13] [PASSED] interlace_only
[00:29:13] [PASSED] res_missing_x
[00:29:13] [PASSED] res_missing_y
[00:29:13] [PASSED] res_bad_y
[00:29:13] [PASSED] res_missing_y_bpp
[00:29:13] [PASSED] res_bad_bpp
[00:29:13] [PASSED] res_bad_refresh
[00:29:13] [PASSED] res_bpp_refresh_force_on_off
[00:29:13] [PASSED] res_invalid_mode
[00:29:13] [PASSED] res_bpp_wrong_place_mode
[00:29:13] [PASSED] name_bpp_refresh
[00:29:13] [PASSED] name_refresh
[00:29:13] [PASSED] name_refresh_wrong_mode
[00:29:13] [PASSED] name_refresh_invalid_mode
[00:29:13] [PASSED] rotate_multiple
[00:29:13] [PASSED] rotate_invalid_val
[00:29:13] [PASSED] rotate_truncated
[00:29:13] [PASSED] invalid_option
[00:29:13] [PASSED] invalid_tv_option
[00:29:13] [PASSED] truncated_tv_option
[00:29:13] ============ [PASSED] drm_test_cmdline_invalid =============
[00:29:13] =============== drm_test_cmdline_tv_options ===============
[00:29:13] [PASSED] NTSC
[00:29:13] [PASSED] NTSC_443
[00:29:13] [PASSED] NTSC_J
[00:29:13] [PASSED] PAL
[00:29:13] [PASSED] PAL_M
[00:29:13] [PASSED] PAL_N
[00:29:13] [PASSED] SECAM
[00:29:13] [PASSED] MONO_525
[00:29:13] [PASSED] MONO_625
[00:29:13] =========== [PASSED] drm_test_cmdline_tv_options ===========
[00:29:13] =============== [PASSED] drm_cmdline_parser ================
[00:29:13] ========== drmm_connector_hdmi_init (20 subtests) ==========
[00:29:13] [PASSED] drm_test_connector_hdmi_init_valid
[00:29:13] [PASSED] drm_test_connector_hdmi_init_bpc_8
[00:29:13] [PASSED] drm_test_connector_hdmi_init_bpc_10
[00:29:13] [PASSED] drm_test_connector_hdmi_init_bpc_12
[00:29:13] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[00:29:13] [PASSED] drm_test_connector_hdmi_init_bpc_null
[00:29:13] [PASSED] drm_test_connector_hdmi_init_formats_empty
[00:29:13] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[00:29:13] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[00:29:13] [PASSED] supported_formats=0x9 yuv420_allowed=1
[00:29:13] [PASSED] supported_formats=0x9 yuv420_allowed=0
[00:29:13] [PASSED] supported_formats=0x3 yuv420_allowed=1
[00:29:13] [PASSED] supported_formats=0x3 yuv420_allowed=0
[00:29:13] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[00:29:13] [PASSED] drm_test_connector_hdmi_init_null_ddc
[00:29:13] [PASSED] drm_test_connector_hdmi_init_null_product
[00:29:13] [PASSED] drm_test_connector_hdmi_init_null_vendor
[00:29:13] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[00:29:13] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[00:29:13] [PASSED] drm_test_connector_hdmi_init_product_valid
[00:29:13] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[00:29:13] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[00:29:13] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[00:29:13] ========= drm_test_connector_hdmi_init_type_valid =========
[00:29:13] [PASSED] HDMI-A
[00:29:13] [PASSED] HDMI-B
[00:29:13] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[00:29:13] ======== drm_test_connector_hdmi_init_type_invalid ========
[00:29:13] [PASSED] Unknown
[00:29:13] [PASSED] VGA
[00:29:13] [PASSED] DVI-I
[00:29:13] [PASSED] DVI-D
[00:29:13] [PASSED] DVI-A
[00:29:13] [PASSED] Composite
[00:29:13] [PASSED] SVIDEO
[00:29:13] [PASSED] LVDS
[00:29:13] [PASSED] Component
[00:29:13] [PASSED] DIN
[00:29:13] [PASSED] DP
[00:29:13] [PASSED] TV
[00:29:13] [PASSED] eDP
[00:29:13] [PASSED] Virtual
[00:29:13] [PASSED] DSI
[00:29:13] [PASSED] DPI
[00:29:13] [PASSED] Writeback
[00:29:13] [PASSED] SPI
[00:29:13] [PASSED] USB
[00:29:13] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[00:29:13] ============ [PASSED] drmm_connector_hdmi_init =============
[00:29:13] ============= drmm_connector_init (3 subtests) =============
[00:29:13] [PASSED] drm_test_drmm_connector_init
[00:29:13] [PASSED] drm_test_drmm_connector_init_null_ddc
[00:29:13] ========= drm_test_drmm_connector_init_type_valid =========
[00:29:13] [PASSED] Unknown
[00:29:13] [PASSED] VGA
[00:29:13] [PASSED] DVI-I
[00:29:13] [PASSED] DVI-D
[00:29:13] [PASSED] DVI-A
[00:29:13] [PASSED] Composite
[00:29:13] [PASSED] SVIDEO
[00:29:13] [PASSED] LVDS
[00:29:13] [PASSED] Component
[00:29:13] [PASSED] DIN
[00:29:13] [PASSED] DP
[00:29:13] [PASSED] HDMI-A
[00:29:13] [PASSED] HDMI-B
[00:29:13] [PASSED] TV
[00:29:13] [PASSED] eDP
[00:29:13] [PASSED] Virtual
[00:29:13] [PASSED] DSI
[00:29:13] [PASSED] DPI
[00:29:13] [PASSED] Writeback
[00:29:13] [PASSED] SPI
[00:29:13] [PASSED] USB
[00:29:13] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[00:29:13] =============== [PASSED] drmm_connector_init ===============
[00:29:13] ========= drm_connector_dynamic_init (6 subtests) ==========
[00:29:13] [PASSED] drm_test_drm_connector_dynamic_init
[00:29:13] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[00:29:13] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[00:29:13] [PASSED] drm_test_drm_connector_dynamic_init_properties
[00:29:13] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[00:29:13] [PASSED] Unknown
[00:29:13] [PASSED] VGA
[00:29:13] [PASSED] DVI-I
[00:29:13] [PASSED] DVI-D
[00:29:13] [PASSED] DVI-A
[00:29:13] [PASSED] Composite
[00:29:13] [PASSED] SVIDEO
[00:29:13] [PASSED] LVDS
[00:29:13] [PASSED] Component
[00:29:13] [PASSED] DIN
[00:29:13] [PASSED] DP
[00:29:13] [PASSED] HDMI-A
[00:29:13] [PASSED] HDMI-B
[00:29:13] [PASSED] TV
[00:29:13] [PASSED] eDP
[00:29:13] [PASSED] Virtual
[00:29:13] [PASSED] DSI
[00:29:13] [PASSED] DPI
[00:29:13] [PASSED] Writeback
[00:29:13] [PASSED] SPI
[00:29:13] [PASSED] USB
[00:29:13] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[00:29:13] ======== drm_test_drm_connector_dynamic_init_name =========
[00:29:13] [PASSED] Unknown
[00:29:13] [PASSED] VGA
[00:29:13] [PASSED] DVI-I
[00:29:13] [PASSED] DVI-D
[00:29:13] [PASSED] DVI-A
[00:29:13] [PASSED] Composite
[00:29:13] [PASSED] SVIDEO
[00:29:13] [PASSED] LVDS
[00:29:13] [PASSED] Component
[00:29:13] [PASSED] DIN
[00:29:13] [PASSED] DP
[00:29:13] [PASSED] HDMI-A
[00:29:13] [PASSED] HDMI-B
[00:29:13] [PASSED] TV
[00:29:13] [PASSED] eDP
[00:29:13] [PASSED] Virtual
[00:29:13] [PASSED] DSI
[00:29:13] [PASSED] DPI
[00:29:13] [PASSED] Writeback
[00:29:13] [PASSED] SPI
[00:29:13] [PASSED] USB
[00:29:13] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[00:29:13] =========== [PASSED] drm_connector_dynamic_init ============
[00:29:13] ==== drm_connector_dynamic_register_early (4 subtests) =====
[00:29:13] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[00:29:13] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[00:29:13] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[00:29:13] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[00:29:13] ====== [PASSED] drm_connector_dynamic_register_early =======
[00:29:13] ======= drm_connector_dynamic_register (7 subtests) ========
[00:29:13] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[00:29:13] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[00:29:13] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[00:29:13] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[00:29:13] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[00:29:13] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[00:29:13] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[00:29:13] ========= [PASSED] drm_connector_dynamic_register ==========
[00:29:13] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[00:29:13] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[00:29:13] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[00:29:13] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[00:29:13] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[00:29:13] ========== drm_test_get_tv_mode_from_name_valid ===========
[00:29:13] [PASSED] NTSC
[00:29:13] [PASSED] NTSC-443
[00:29:13] [PASSED] NTSC-J
[00:29:13] [PASSED] PAL
[00:29:13] [PASSED] PAL-M
[00:29:13] [PASSED] PAL-N
[00:29:13] [PASSED] SECAM
[00:29:13] [PASSED] Mono
[00:29:13] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[00:29:13] [PASSED] drm_test_get_tv_mode_from_name_truncated
[00:29:13] ============ [PASSED] drm_get_tv_mode_from_name ============
[00:29:13] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[00:29:13] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[00:29:13] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[00:29:13] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[00:29:13] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[00:29:13] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[00:29:13] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[00:29:13] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[00:29:13] [PASSED] VIC 96
[00:29:13] [PASSED] VIC 97
[00:29:13] [PASSED] VIC 101
[00:29:13] [PASSED] VIC 102
[00:29:13] [PASSED] VIC 106
[00:29:13] [PASSED] VIC 107
[00:29:13] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[00:29:13] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[00:29:13] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[00:29:13] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[00:29:13] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[00:29:13] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[00:29:13] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[00:29:13] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[00:29:13] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[00:29:13] [PASSED] Automatic
[00:29:13] [PASSED] Full
[00:29:13] [PASSED] Limited 16:235
[00:29:13] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[00:29:13] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[00:29:13] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[00:29:13] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[00:29:13] === drm_test_drm_hdmi_connector_get_output_format_name ====
[00:29:13] [PASSED] RGB
[00:29:13] [PASSED] YUV 4:2:0
[00:29:13] [PASSED] YUV 4:2:2
[00:29:13] [PASSED] YUV 4:4:4
[00:29:13] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[00:29:13] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[00:29:13] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[00:29:13] ============= drm_damage_helper (21 subtests) ==============
[00:29:13] [PASSED] drm_test_damage_iter_no_damage
[00:29:13] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[00:29:13] [PASSED] drm_test_damage_iter_no_damage_src_moved
[00:29:13] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[00:29:13] [PASSED] drm_test_damage_iter_no_damage_not_visible
[00:29:13] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[00:29:13] [PASSED] drm_test_damage_iter_no_damage_no_fb
[00:29:13] [PASSED] drm_test_damage_iter_simple_damage
[00:29:13] [PASSED] drm_test_damage_iter_single_damage
[00:29:13] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[00:29:13] [PASSED] drm_test_damage_iter_single_damage_outside_src
[00:29:13] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[00:29:13] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[00:29:13] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[00:29:13] [PASSED] drm_test_damage_iter_single_damage_src_moved
[00:29:13] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[00:29:13] [PASSED] drm_test_damage_iter_damage
[00:29:13] [PASSED] drm_test_damage_iter_damage_one_intersect
[00:29:13] [PASSED] drm_test_damage_iter_damage_one_outside
[00:29:13] [PASSED] drm_test_damage_iter_damage_src_moved
[00:29:13] [PASSED] drm_test_damage_iter_damage_not_visible
[00:29:13] ================ [PASSED] drm_damage_helper ================
[00:29:13] ============== drm_dp_mst_helper (3 subtests) ==============
[00:29:13] ============== drm_test_dp_mst_calc_pbn_mode ==============
[00:29:13] [PASSED] Clock 154000 BPP 30 DSC disabled
[00:29:13] [PASSED] Clock 234000 BPP 30 DSC disabled
[00:29:13] [PASSED] Clock 297000 BPP 24 DSC disabled
[00:29:13] [PASSED] Clock 332880 BPP 24 DSC enabled
[00:29:13] [PASSED] Clock 324540 BPP 24 DSC enabled
[00:29:13] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[00:29:13] ============== drm_test_dp_mst_calc_pbn_div ===============
[00:29:13] [PASSED] Link rate 2000000 lane count 4
[00:29:13] [PASSED] Link rate 2000000 lane count 2
[00:29:13] [PASSED] Link rate 2000000 lane count 1
[00:29:13] [PASSED] Link rate 1350000 lane count 4
[00:29:13] [PASSED] Link rate 1350000 lane count 2
[00:29:13] [PASSED] Link rate 1350000 lane count 1
[00:29:13] [PASSED] Link rate 1000000 lane count 4
[00:29:13] [PASSED] Link rate 1000000 lane count 2
[00:29:13] [PASSED] Link rate 1000000 lane count 1
[00:29:13] [PASSED] Link rate 810000 lane count 4
[00:29:13] [PASSED] Link rate 810000 lane count 2
[00:29:13] [PASSED] Link rate 810000 lane count 1
[00:29:13] [PASSED] Link rate 540000 lane count 4
[00:29:13] [PASSED] Link rate 540000 lane count 2
[00:29:13] [PASSED] Link rate 540000 lane count 1
[00:29:13] [PASSED] Link rate 270000 lane count 4
[00:29:13] [PASSED] Link rate 270000 lane count 2
[00:29:13] [PASSED] Link rate 270000 lane count 1
[00:29:13] [PASSED] Link rate 162000 lane count 4
[00:29:13] [PASSED] Link rate 162000 lane count 2
[00:29:13] [PASSED] Link rate 162000 lane count 1
[00:29:13] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[00:29:13] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[00:29:13] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[00:29:13] [PASSED] DP_POWER_UP_PHY with port number
[00:29:13] [PASSED] DP_POWER_DOWN_PHY with port number
[00:29:13] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[00:29:13] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[00:29:13] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[00:29:13] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[00:29:13] [PASSED] DP_QUERY_PAYLOAD with port number
[00:29:13] [PASSED] DP_QUERY_PAYLOAD with VCPI
[00:29:13] [PASSED] DP_REMOTE_DPCD_READ with port number
[00:29:13] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[00:29:13] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[00:29:13] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[00:29:13] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[00:29:13] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[00:29:13] [PASSED] DP_REMOTE_I2C_READ with port number
[00:29:13] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[00:29:13] [PASSED] DP_REMOTE_I2C_READ with transactions array
[00:29:13] [PASSED] DP_REMOTE_I2C_WRITE with port number
[00:29:13] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[00:29:13] [PASSED] DP_REMOTE_I2C_WRITE with data array
[00:29:13] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[00:29:13] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[00:29:13] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[00:29:13] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[00:29:13] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[00:29:13] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[00:29:13] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[00:29:13] ================ [PASSED] drm_dp_mst_helper ================
[00:29:13] ================== drm_exec (7 subtests) ===================
[00:29:13] [PASSED] sanitycheck
[00:29:13] [PASSED] test_lock
[00:29:13] [PASSED] test_lock_unlock
[00:29:13] [PASSED] test_duplicates
[00:29:13] [PASSED] test_prepare
[00:29:13] [PASSED] test_prepare_array
[00:29:13] [PASSED] test_multiple_loops
[00:29:13] ==================== [PASSED] drm_exec =====================
[00:29:13] =========== drm_format_helper_test (17 subtests) ===========
[00:29:13] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[00:29:13] [PASSED] single_pixel_source_buffer
[00:29:13] [PASSED] single_pixel_clip_rectangle
[00:29:13] [PASSED] well_known_colors
[00:29:13] [PASSED] destination_pitch
[00:29:13] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[00:29:13] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[00:29:13] [PASSED] single_pixel_source_buffer
[00:29:13] [PASSED] single_pixel_clip_rectangle
[00:29:13] [PASSED] well_known_colors
[00:29:13] [PASSED] destination_pitch
[00:29:13] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[00:29:13] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[00:29:13] [PASSED] single_pixel_source_buffer
[00:29:13] [PASSED] single_pixel_clip_rectangle
[00:29:13] [PASSED] well_known_colors
[00:29:13] [PASSED] destination_pitch
[00:29:13] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[00:29:13] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[00:29:13] [PASSED] single_pixel_source_buffer
[00:29:13] [PASSED] single_pixel_clip_rectangle
[00:29:13] [PASSED] well_known_colors
[00:29:13] [PASSED] destination_pitch
[00:29:13] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[00:29:13] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[00:29:13] [PASSED] single_pixel_source_buffer
[00:29:13] [PASSED] single_pixel_clip_rectangle
[00:29:13] [PASSED] well_known_colors
[00:29:13] [PASSED] destination_pitch
[00:29:13] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[00:29:13] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[00:29:13] [PASSED] single_pixel_source_buffer
[00:29:13] [PASSED] single_pixel_clip_rectangle
[00:29:13] [PASSED] well_known_colors
[00:29:13] [PASSED] destination_pitch
[00:29:13] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[00:29:13] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[00:29:13] [PASSED] single_pixel_source_buffer
[00:29:13] [PASSED] single_pixel_clip_rectangle
[00:29:13] [PASSED] well_known_colors
[00:29:13] [PASSED] destination_pitch
[00:29:13] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[00:29:13] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[00:29:13] [PASSED] single_pixel_source_buffer
[00:29:13] [PASSED] single_pixel_clip_rectangle
[00:29:13] [PASSED] well_known_colors
[00:29:13] [PASSED] destination_pitch
[00:29:13] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[00:29:13] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[00:29:13] [PASSED] single_pixel_source_buffer
[00:29:13] [PASSED] single_pixel_clip_rectangle
[00:29:13] [PASSED] well_known_colors
[00:29:13] [PASSED] destination_pitch
[00:29:13] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[00:29:13] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[00:29:13] [PASSED] single_pixel_source_buffer
[00:29:13] [PASSED] single_pixel_clip_rectangle
[00:29:13] [PASSED] well_known_colors
[00:29:13] [PASSED] destination_pitch
[00:29:13] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[00:29:13] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[00:29:13] [PASSED] single_pixel_source_buffer
[00:29:13] [PASSED] single_pixel_clip_rectangle
[00:29:13] [PASSED] well_known_colors
[00:29:13] [PASSED] destination_pitch
[00:29:13] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[00:29:13] ============== drm_test_fb_xrgb8888_to_mono ===============
[00:29:13] [PASSED] single_pixel_source_buffer
[00:29:13] [PASSED] single_pixel_clip_rectangle
[00:29:13] [PASSED] well_known_colors
[00:29:13] [PASSED] destination_pitch
[00:29:13] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[00:29:13] ==================== drm_test_fb_swab =====================
[00:29:13] [PASSED] single_pixel_source_buffer
[00:29:13] [PASSED] single_pixel_clip_rectangle
[00:29:13] [PASSED] well_known_colors
[00:29:13] [PASSED] destination_pitch
[00:29:13] ================ [PASSED] drm_test_fb_swab =================
[00:29:13] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[00:29:13] [PASSED] single_pixel_source_buffer
[00:29:13] [PASSED] single_pixel_clip_rectangle
[00:29:13] [PASSED] well_known_colors
[00:29:13] [PASSED] destination_pitch
[00:29:13] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[00:29:13] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[00:29:13] [PASSED] single_pixel_source_buffer
[00:29:13] [PASSED] single_pixel_clip_rectangle
[00:29:13] [PASSED] well_known_colors
[00:29:13] [PASSED] destination_pitch
[00:29:13] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[00:29:13] ================= drm_test_fb_clip_offset =================
[00:29:13] [PASSED] pass through
[00:29:13] [PASSED] horizontal offset
[00:29:13] [PASSED] vertical offset
[00:29:13] [PASSED] horizontal and vertical offset
[00:29:13] [PASSED] horizontal offset (custom pitch)
[00:29:13] [PASSED] vertical offset (custom pitch)
[00:29:13] [PASSED] horizontal and vertical offset (custom pitch)
[00:29:13] ============= [PASSED] drm_test_fb_clip_offset =============
[00:29:13] =================== drm_test_fb_memcpy ====================
[00:29:13] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[00:29:13] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[00:29:13] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[00:29:13] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[00:29:13] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[00:29:13] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[00:29:13] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[00:29:13] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[00:29:13] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[00:29:13] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[00:29:13] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[00:29:13] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[00:29:13] =============== [PASSED] drm_test_fb_memcpy ================
[00:29:13] ============= [PASSED] drm_format_helper_test ==============
[00:29:13] ================= drm_format (18 subtests) =================
[00:29:13] [PASSED] drm_test_format_block_width_invalid
[00:29:13] [PASSED] drm_test_format_block_width_one_plane
[00:29:13] [PASSED] drm_test_format_block_width_two_plane
[00:29:13] [PASSED] drm_test_format_block_width_three_plane
[00:29:13] [PASSED] drm_test_format_block_width_tiled
[00:29:13] [PASSED] drm_test_format_block_height_invalid
[00:29:13] [PASSED] drm_test_format_block_height_one_plane
[00:29:13] [PASSED] drm_test_format_block_height_two_plane
[00:29:13] [PASSED] drm_test_format_block_height_three_plane
[00:29:13] [PASSED] drm_test_format_block_height_tiled
[00:29:13] [PASSED] drm_test_format_min_pitch_invalid
[00:29:13] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[00:29:13] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[00:29:13] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[00:29:13] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[00:29:13] [PASSED] drm_test_format_min_pitch_two_plane
[00:29:13] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[00:29:13] [PASSED] drm_test_format_min_pitch_tiled
[00:29:13] =================== [PASSED] drm_format ====================
[00:29:13] ============== drm_framebuffer (10 subtests) ===============
[00:29:13] ========== drm_test_framebuffer_check_src_coords ==========
[00:29:13] [PASSED] Success: source fits into fb
[00:29:13] [PASSED] Fail: overflowing fb with x-axis coordinate
[00:29:13] [PASSED] Fail: overflowing fb with y-axis coordinate
[00:29:13] [PASSED] Fail: overflowing fb with source width
[00:29:13] [PASSED] Fail: overflowing fb with source height
[00:29:13] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[00:29:13] [PASSED] drm_test_framebuffer_cleanup
[00:29:13] =============== drm_test_framebuffer_create ===============
[00:29:13] [PASSED] ABGR8888 normal sizes
[00:29:13] [PASSED] ABGR8888 max sizes
[00:29:13] [PASSED] ABGR8888 pitch greater than min required
[00:29:13] [PASSED] ABGR8888 pitch less than min required
[00:29:13] [PASSED] ABGR8888 Invalid width
[00:29:13] [PASSED] ABGR8888 Invalid buffer handle
[00:29:13] [PASSED] No pixel format
[00:29:13] [PASSED] ABGR8888 Width 0
[00:29:13] [PASSED] ABGR8888 Height 0
[00:29:13] [PASSED] ABGR8888 Out of bound height * pitch combination
[00:29:13] [PASSED] ABGR8888 Large buffer offset
[00:29:13] [PASSED] ABGR8888 Buffer offset for inexistent plane
[00:29:13] [PASSED] ABGR8888 Invalid flag
[00:29:13] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[00:29:13] [PASSED] ABGR8888 Valid buffer modifier
[00:29:13] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[00:29:13] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[00:29:13] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[00:29:13] [PASSED] NV12 Normal sizes
[00:29:13] [PASSED] NV12 Max sizes
[00:29:13] [PASSED] NV12 Invalid pitch
[00:29:13] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[00:29:13] [PASSED] NV12 different modifier per-plane
[00:29:13] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[00:29:13] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[00:29:13] [PASSED] NV12 Modifier for inexistent plane
[00:29:13] [PASSED] NV12 Handle for inexistent plane
[00:29:13] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[00:29:13] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[00:29:13] [PASSED] YVU420 Normal sizes
[00:29:13] [PASSED] YVU420 Max sizes
[00:29:13] [PASSED] YVU420 Invalid pitch
[00:29:13] [PASSED] YVU420 Different pitches
[00:29:13] [PASSED] YVU420 Different buffer offsets/pitches
[00:29:13] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[00:29:13] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[00:29:13] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[00:29:13] [PASSED] YVU420 Valid modifier
[00:29:13] [PASSED] YVU420 Different modifiers per plane
[00:29:13] [PASSED] YVU420 Modifier for inexistent plane
[00:29:13] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[00:29:13] [PASSED] X0L2 Normal sizes
[00:29:13] [PASSED] X0L2 Max sizes
[00:29:13] [PASSED] X0L2 Invalid pitch
[00:29:13] [PASSED] X0L2 Pitch greater than minimum required
[00:29:13] [PASSED] X0L2 Handle for inexistent plane
[00:29:13] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[00:29:13] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[00:29:13] [PASSED] X0L2 Valid modifier
[00:29:13] [PASSED] X0L2 Modifier for inexistent plane
[00:29:13] =========== [PASSED] drm_test_framebuffer_create ===========
[00:29:13] [PASSED] drm_test_framebuffer_free
[00:29:13] [PASSED] drm_test_framebuffer_init
[00:29:13] [PASSED] drm_test_framebuffer_init_bad_format
[00:29:13] [PASSED] drm_test_framebuffer_init_dev_mismatch
[00:29:13] [PASSED] drm_test_framebuffer_lookup
[00:29:13] [PASSED] drm_test_framebuffer_lookup_inexistent
[00:29:13] [PASSED] drm_test_framebuffer_modifiers_not_supported
[00:29:13] ================= [PASSED] drm_framebuffer =================
[00:29:13] ================ drm_gem_shmem (8 subtests) ================
[00:29:13] [PASSED] drm_gem_shmem_test_obj_create
[00:29:13] [PASSED] drm_gem_shmem_test_obj_create_private
[00:29:13] [PASSED] drm_gem_shmem_test_pin_pages
[00:29:13] [PASSED] drm_gem_shmem_test_vmap
[00:29:13] [PASSED] drm_gem_shmem_test_get_pages_sgt
[00:29:13] [PASSED] drm_gem_shmem_test_get_sg_table
[00:29:13] [PASSED] drm_gem_shmem_test_madvise
[00:29:13] [PASSED] drm_gem_shmem_test_purge
[00:29:13] ================== [PASSED] drm_gem_shmem ==================
[00:29:13] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[00:29:13] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[00:29:13] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[00:29:13] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[00:29:13] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[00:29:13] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[00:29:13] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[00:29:13] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[00:29:13] [PASSED] Automatic
[00:29:13] [PASSED] Full
[00:29:13] [PASSED] Limited 16:235
[00:29:13] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[00:29:13] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[00:29:13] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[00:29:13] [PASSED] drm_test_check_disable_connector
[00:29:13] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[00:29:13] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[00:29:13] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[00:29:13] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[00:29:13] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[00:29:13] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[00:29:13] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[00:29:13] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[00:29:13] [PASSED] drm_test_check_output_bpc_dvi
[00:29:13] [PASSED] drm_test_check_output_bpc_format_vic_1
[00:29:13] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[00:29:13] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[00:29:13] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[00:29:13] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[00:29:13] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[00:29:13] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[00:29:13] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[00:29:13] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[00:29:13] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[00:29:13] [PASSED] drm_test_check_broadcast_rgb_value
[00:29:13] [PASSED] drm_test_check_bpc_8_value
[00:29:13] [PASSED] drm_test_check_bpc_10_value
[00:29:13] [PASSED] drm_test_check_bpc_12_value
[00:29:13] [PASSED] drm_test_check_format_value
[00:29:13] [PASSED] drm_test_check_tmds_char_value
[00:29:13] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[00:29:13] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[00:29:13] [PASSED] drm_test_check_mode_valid
[00:29:13] [PASSED] drm_test_check_mode_valid_reject
[00:29:13] [PASSED] drm_test_check_mode_valid_reject_rate
[00:29:13] [PASSED] drm_test_check_mode_valid_reject_max_clock
[00:29:13] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[00:29:13] ================= drm_managed (2 subtests) =================
[00:29:13] [PASSED] drm_test_managed_release_action
[00:29:13] [PASSED] drm_test_managed_run_action
[00:29:13] =================== [PASSED] drm_managed ===================
[00:29:13] =================== drm_mm (6 subtests) ====================
[00:29:13] [PASSED] drm_test_mm_init
[00:29:13] [PASSED] drm_test_mm_debug
[00:29:13] [PASSED] drm_test_mm_align32
[00:29:13] [PASSED] drm_test_mm_align64
[00:29:13] [PASSED] drm_test_mm_lowest
[00:29:13] [PASSED] drm_test_mm_highest
[00:29:13] ===================== [PASSED] drm_mm ======================
[00:29:13] ============= drm_modes_analog_tv (5 subtests) =============
[00:29:13] [PASSED] drm_test_modes_analog_tv_mono_576i
[00:29:13] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[00:29:13] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[00:29:13] [PASSED] drm_test_modes_analog_tv_pal_576i
[00:29:13] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[00:29:13] =============== [PASSED] drm_modes_analog_tv ===============
[00:29:13] ============== drm_plane_helper (2 subtests) ===============
[00:29:13] =============== drm_test_check_plane_state ================
[00:29:13] [PASSED] clipping_simple
[00:29:13] [PASSED] clipping_rotate_reflect
[00:29:13] [PASSED] positioning_simple
[00:29:13] [PASSED] upscaling
[00:29:13] [PASSED] downscaling
[00:29:13] [PASSED] rounding1
[00:29:13] [PASSED] rounding2
[00:29:13] [PASSED] rounding3
[00:29:13] [PASSED] rounding4
[00:29:13] =========== [PASSED] drm_test_check_plane_state ============
[00:29:13] =========== drm_test_check_invalid_plane_state ============
[00:29:13] [PASSED] positioning_invalid
[00:29:13] [PASSED] upscaling_invalid
[00:29:13] [PASSED] downscaling_invalid
[00:29:13] ======= [PASSED] drm_test_check_invalid_plane_state ========
[00:29:13] ================ [PASSED] drm_plane_helper =================
[00:29:13] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[00:29:13] ====== drm_test_connector_helper_tv_get_modes_check =======
[00:29:13] [PASSED] None
[00:29:13] [PASSED] PAL
[00:29:13] [PASSED] NTSC
[00:29:13] [PASSED] Both, NTSC Default
[00:29:13] [PASSED] Both, PAL Default
[00:29:13] [PASSED] Both, NTSC Default, with PAL on command-line
[00:29:13] [PASSED] Both, PAL Default, with NTSC on command-line
[00:29:13] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[00:29:13] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[00:29:13] ================== drm_rect (9 subtests) ===================
[00:29:13] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[00:29:13] [PASSED] drm_test_rect_clip_scaled_not_clipped
[00:29:13] [PASSED] drm_test_rect_clip_scaled_clipped
[00:29:13] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[00:29:13] ================= drm_test_rect_intersect =================
[00:29:13] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[00:29:13] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[00:29:13] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[00:29:13] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[00:29:13] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[00:29:13] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[00:29:13] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[00:29:13] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[00:29:13] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[00:29:13] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[00:29:13] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[00:29:13] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[00:29:13] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[00:29:13] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[00:29:13] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[00:29:13] ============= [PASSED] drm_test_rect_intersect =============
[00:29:13] ================ drm_test_rect_calc_hscale ================
[00:29:13] [PASSED] normal use
[00:29:13] [PASSED] out of max range
[00:29:13] [PASSED] out of min range
[00:29:13] [PASSED] zero dst
[00:29:13] [PASSED] negative src
[00:29:13] [PASSED] negative dst
[00:29:13] ============ [PASSED] drm_test_rect_calc_hscale ============
[00:29:13] ================ drm_test_rect_calc_vscale ================
[00:29:13] [PASSED] normal use
stty: 'standard input': Inappropriate ioctl for device
[00:29:13] [PASSED] out of max range
[00:29:13] [PASSED] out of min range
[00:29:13] [PASSED] zero dst
[00:29:13] [PASSED] negative src
[00:29:13] [PASSED] negative dst
[00:29:13] ============ [PASSED] drm_test_rect_calc_vscale ============
[00:29:13] ================== drm_test_rect_rotate ===================
[00:29:13] [PASSED] reflect-x
[00:29:13] [PASSED] reflect-y
[00:29:13] [PASSED] rotate-0
[00:29:13] [PASSED] rotate-90
[00:29:13] [PASSED] rotate-180
[00:29:13] [PASSED] rotate-270
[00:29:13] ============== [PASSED] drm_test_rect_rotate ===============
[00:29:13] ================ drm_test_rect_rotate_inv =================
[00:29:13] [PASSED] reflect-x
[00:29:13] [PASSED] reflect-y
[00:29:13] [PASSED] rotate-0
[00:29:13] [PASSED] rotate-90
[00:29:13] [PASSED] rotate-180
[00:29:13] [PASSED] rotate-270
[00:29:13] ============ [PASSED] drm_test_rect_rotate_inv =============
[00:29:13] ==================== [PASSED] drm_rect =====================
[00:29:13] ============ drm_sysfb_modeset_test (1 subtest) ============
[00:29:13] ============ drm_test_sysfb_build_fourcc_list =============
[00:29:13] [PASSED] no native formats
[00:29:13] [PASSED] XRGB8888 as native format
[00:29:13] [PASSED] remove duplicates
[00:29:13] [PASSED] convert alpha formats
[00:29:13] [PASSED] random formats
[00:29:13] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[00:29:13] ============= [PASSED] drm_sysfb_modeset_test ==============
[00:29:13] ============================================================
[00:29:13] Testing complete. Ran 622 tests: passed: 622
[00:29:13] Elapsed time: 27.220s total, 1.678s configuring, 25.069s building, 0.434s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[00:29:13] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[00:29:15] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[00:29:24] Starting KUnit Kernel (1/1)...
[00:29:24] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[00:29:24] ================= ttm_device (5 subtests) ==================
[00:29:24] [PASSED] ttm_device_init_basic
[00:29:24] [PASSED] ttm_device_init_multiple
[00:29:24] [PASSED] ttm_device_fini_basic
[00:29:24] [PASSED] ttm_device_init_no_vma_man
[00:29:24] ================== ttm_device_init_pools ==================
[00:29:24] [PASSED] No DMA allocations, no DMA32 required
[00:29:24] [PASSED] DMA allocations, DMA32 required
[00:29:24] [PASSED] No DMA allocations, DMA32 required
[00:29:24] [PASSED] DMA allocations, no DMA32 required
[00:29:24] ============== [PASSED] ttm_device_init_pools ==============
[00:29:24] =================== [PASSED] ttm_device ====================
[00:29:24] ================== ttm_pool (8 subtests) ===================
[00:29:24] ================== ttm_pool_alloc_basic ===================
[00:29:24] [PASSED] One page
[00:29:24] [PASSED] More than one page
[00:29:24] [PASSED] Above the allocation limit
[00:29:24] [PASSED] One page, with coherent DMA mappings enabled
[00:29:24] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[00:29:24] ============== [PASSED] ttm_pool_alloc_basic ===============
[00:29:24] ============== ttm_pool_alloc_basic_dma_addr ==============
[00:29:24] [PASSED] One page
[00:29:24] [PASSED] More than one page
[00:29:24] [PASSED] Above the allocation limit
[00:29:24] [PASSED] One page, with coherent DMA mappings enabled
[00:29:24] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[00:29:24] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[00:29:24] [PASSED] ttm_pool_alloc_order_caching_match
[00:29:24] [PASSED] ttm_pool_alloc_caching_mismatch
[00:29:24] [PASSED] ttm_pool_alloc_order_mismatch
[00:29:24] [PASSED] ttm_pool_free_dma_alloc
[00:29:24] [PASSED] ttm_pool_free_no_dma_alloc
[00:29:24] [PASSED] ttm_pool_fini_basic
[00:29:24] ==================== [PASSED] ttm_pool =====================
[00:29:24] ================ ttm_resource (8 subtests) =================
[00:29:24] ================= ttm_resource_init_basic =================
[00:29:24] [PASSED] Init resource in TTM_PL_SYSTEM
[00:29:24] [PASSED] Init resource in TTM_PL_VRAM
[00:29:24] [PASSED] Init resource in a private placement
[00:29:24] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[00:29:24] ============= [PASSED] ttm_resource_init_basic =============
[00:29:24] [PASSED] ttm_resource_init_pinned
[00:29:24] [PASSED] ttm_resource_fini_basic
[00:29:24] [PASSED] ttm_resource_manager_init_basic
[00:29:24] [PASSED] ttm_resource_manager_usage_basic
[00:29:24] [PASSED] ttm_resource_manager_set_used_basic
[00:29:24] [PASSED] ttm_sys_man_alloc_basic
[00:29:24] [PASSED] ttm_sys_man_free_basic
[00:29:24] ================== [PASSED] ttm_resource ===================
[00:29:24] =================== ttm_tt (15 subtests) ===================
[00:29:24] ==================== ttm_tt_init_basic ====================
[00:29:24] [PASSED] Page-aligned size
[00:29:24] [PASSED] Extra pages requested
[00:29:24] ================ [PASSED] ttm_tt_init_basic ================
[00:29:24] [PASSED] ttm_tt_init_misaligned
[00:29:24] [PASSED] ttm_tt_fini_basic
[00:29:24] [PASSED] ttm_tt_fini_sg
[00:29:24] [PASSED] ttm_tt_fini_shmem
[00:29:24] [PASSED] ttm_tt_create_basic
[00:29:24] [PASSED] ttm_tt_create_invalid_bo_type
[00:29:24] [PASSED] ttm_tt_create_ttm_exists
[00:29:24] [PASSED] ttm_tt_create_failed
[00:29:24] [PASSED] ttm_tt_destroy_basic
[00:29:24] [PASSED] ttm_tt_populate_null_ttm
[00:29:24] [PASSED] ttm_tt_populate_populated_ttm
[00:29:24] [PASSED] ttm_tt_unpopulate_basic
[00:29:24] [PASSED] ttm_tt_unpopulate_empty_ttm
[00:29:24] [PASSED] ttm_tt_swapin_basic
[00:29:24] ===================== [PASSED] ttm_tt ======================
[00:29:24] =================== ttm_bo (14 subtests) ===================
[00:29:24] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[00:29:24] [PASSED] Cannot be interrupted and sleeps
[00:29:24] [PASSED] Cannot be interrupted, locks straight away
[00:29:24] [PASSED] Can be interrupted, sleeps
[00:29:24] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[00:29:24] [PASSED] ttm_bo_reserve_locked_no_sleep
[00:29:24] [PASSED] ttm_bo_reserve_no_wait_ticket
[00:29:24] [PASSED] ttm_bo_reserve_double_resv
[00:29:24] [PASSED] ttm_bo_reserve_interrupted
[00:29:24] [PASSED] ttm_bo_reserve_deadlock
[00:29:24] [PASSED] ttm_bo_unreserve_basic
[00:29:24] [PASSED] ttm_bo_unreserve_pinned
[00:29:24] [PASSED] ttm_bo_unreserve_bulk
[00:29:24] [PASSED] ttm_bo_fini_basic
[00:29:24] [PASSED] ttm_bo_fini_shared_resv
[00:29:24] [PASSED] ttm_bo_pin_basic
[00:29:24] [PASSED] ttm_bo_pin_unpin_resource
[00:29:24] [PASSED] ttm_bo_multiple_pin_one_unpin
[00:29:24] ===================== [PASSED] ttm_bo ======================
[00:29:24] ============== ttm_bo_validate (21 subtests) ===============
[00:29:24] ============== ttm_bo_init_reserved_sys_man ===============
[00:29:24] [PASSED] Buffer object for userspace
[00:29:24] [PASSED] Kernel buffer object
[00:29:24] [PASSED] Shared buffer object
[00:29:24] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[00:29:24] ============== ttm_bo_init_reserved_mock_man ==============
[00:29:24] [PASSED] Buffer object for userspace
[00:29:24] [PASSED] Kernel buffer object
[00:29:24] [PASSED] Shared buffer object
[00:29:24] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[00:29:24] [PASSED] ttm_bo_init_reserved_resv
[00:29:24] ================== ttm_bo_validate_basic ==================
[00:29:24] [PASSED] Buffer object for userspace
[00:29:24] [PASSED] Kernel buffer object
[00:29:24] [PASSED] Shared buffer object
[00:29:24] ============== [PASSED] ttm_bo_validate_basic ==============
[00:29:24] [PASSED] ttm_bo_validate_invalid_placement
[00:29:24] ============= ttm_bo_validate_same_placement ==============
[00:29:24] [PASSED] System manager
[00:29:24] [PASSED] VRAM manager
[00:29:24] ========= [PASSED] ttm_bo_validate_same_placement ==========
[00:29:24] [PASSED] ttm_bo_validate_failed_alloc
[00:29:24] [PASSED] ttm_bo_validate_pinned
[00:29:24] [PASSED] ttm_bo_validate_busy_placement
[00:29:24] ================ ttm_bo_validate_multihop =================
[00:29:24] [PASSED] Buffer object for userspace
[00:29:24] [PASSED] Kernel buffer object
[00:29:24] [PASSED] Shared buffer object
[00:29:24] ============ [PASSED] ttm_bo_validate_multihop =============
[00:29:24] ========== ttm_bo_validate_no_placement_signaled ==========
[00:29:24] [PASSED] Buffer object in system domain, no page vector
[00:29:24] [PASSED] Buffer object in system domain with an existing page vector
[00:29:24] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[00:29:24] ======== ttm_bo_validate_no_placement_not_signaled ========
[00:29:24] [PASSED] Buffer object for userspace
[00:29:24] [PASSED] Kernel buffer object
[00:29:24] [PASSED] Shared buffer object
[00:29:24] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[00:29:24] [PASSED] ttm_bo_validate_move_fence_signaled
[00:29:25] ========= ttm_bo_validate_move_fence_not_signaled =========
[00:29:25] [PASSED] Waits for GPU
[00:29:25] [PASSED] Tries to lock straight away
[00:29:25] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[00:29:25] [PASSED] ttm_bo_validate_happy_evict
[00:29:25] [PASSED] ttm_bo_validate_all_pinned_evict
[00:29:25] [PASSED] ttm_bo_validate_allowed_only_evict
[00:29:25] [PASSED] ttm_bo_validate_deleted_evict
[00:29:25] [PASSED] ttm_bo_validate_busy_domain_evict
[00:29:25] [PASSED] ttm_bo_validate_evict_gutting
[00:29:25] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[00:29:25] ================= [PASSED] ttm_bo_validate =================
[00:29:25] ============================================================
[00:29:25] Testing complete. Ran 101 tests: passed: 101
[00:29:25] Elapsed time: 11.552s total, 1.725s configuring, 9.611s building, 0.181s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 14+ messages in thread
* ✓ Xe.CI.BAT: success for drm/i915/display: Enable system cache support for FBC
2025-11-23 16:01 [PATCH v3 0/2] drm/i915/display: Enable system cache support for FBC Vinod Govindapillai
` (3 preceding siblings ...)
2025-11-25 0:29 ` ✓ CI.KUnit: success " Patchwork
@ 2025-11-25 1:07 ` Patchwork
2025-11-25 3:06 ` ✗ Xe.CI.Full: failure " Patchwork
5 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2025-11-25 1:07 UTC (permalink / raw)
To: Govindapillai, Vinod; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 1571 bytes --]
== Series Details ==
Series: drm/i915/display: Enable system cache support for FBC
URL : https://patchwork.freedesktop.org/series/157944/
State : success
== Summary ==
CI Bug Log - changes from xe-4141-c701e79730169fab373fba7e759497d755fac592_BAT -> xe-pw-157944v1_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (12 -> 12)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in xe-pw-157944v1_BAT that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_flip@basic-plain-flip@a-edp1:
- bat-adlp-7: [PASS][1] -> [DMESG-WARN][2] ([Intel XE#4543]) +1 other test dmesg-warn
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4141-c701e79730169fab373fba7e759497d755fac592/bat-adlp-7/igt@kms_flip@basic-plain-flip@a-edp1.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/bat-adlp-7/igt@kms_flip@basic-plain-flip@a-edp1.html
[Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
Build changes
-------------
* Linux: xe-4141-c701e79730169fab373fba7e759497d755fac592 -> xe-pw-157944v1
IGT_8636: 254cd102396ff95d61f2ebe49fc09128878bf483 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-4141-c701e79730169fab373fba7e759497d755fac592: c701e79730169fab373fba7e759497d755fac592
xe-pw-157944v1: 157944v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/index.html
[-- Attachment #2: Type: text/html, Size: 2136 bytes --]
^ permalink raw reply [flat|nested] 14+ messages in thread
* ✗ Xe.CI.Full: failure for drm/i915/display: Enable system cache support for FBC
2025-11-23 16:01 [PATCH v3 0/2] drm/i915/display: Enable system cache support for FBC Vinod Govindapillai
` (4 preceding siblings ...)
2025-11-25 1:07 ` ✓ Xe.CI.BAT: " Patchwork
@ 2025-11-25 3:06 ` Patchwork
5 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2025-11-25 3:06 UTC (permalink / raw)
To: Govindapillai, Vinod; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 43452 bytes --]
== Series Details ==
Series: drm/i915/display: Enable system cache support for FBC
URL : https://patchwork.freedesktop.org/series/157944/
State : failure
== Summary ==
CI Bug Log - changes from xe-4141-c701e79730169fab373fba7e759497d755fac592_FULL -> xe-pw-157944v1_FULL
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with xe-pw-157944v1_FULL absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-157944v1_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (4 -> 4)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in xe-pw-157944v1_FULL:
### IGT changes ###
#### Possible regressions ####
* igt@kms_cursor_crc@cursor-suspend@pipe-a-hdmi-a-1:
- shard-adlp: NOTRUN -> [ABORT][1] +4 other tests abort
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-adlp-8/igt@kms_cursor_crc@cursor-suspend@pipe-a-hdmi-a-1.html
* igt@kms_lease@simple-lease@pipe-b-dp-2:
- shard-bmg: [PASS][2] -> [FAIL][3]
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4141-c701e79730169fab373fba7e759497d755fac592/shard-bmg-7/igt@kms_lease@simple-lease@pipe-b-dp-2.html
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-bmg-6/igt@kms_lease@simple-lease@pipe-b-dp-2.html
* igt@kms_vblank@ts-continuation-suspend@pipe-a-dp-4:
- shard-dg2-set2: NOTRUN -> [ABORT][4]
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-dg2-463/igt@kms_vblank@ts-continuation-suspend@pipe-a-dp-4.html
* igt@kms_vblank@ts-continuation-suspend@pipe-c-edp-1:
- shard-lnl: [PASS][5] -> [ABORT][6] +1 other test abort
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4141-c701e79730169fab373fba7e759497d755fac592/shard-lnl-5/igt@kms_vblank@ts-continuation-suspend@pipe-c-edp-1.html
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-lnl-1/igt@kms_vblank@ts-continuation-suspend@pipe-c-edp-1.html
* igt@xe_pm@s3-vm-bind-userptr:
- shard-bmg: [PASS][7] -> [ABORT][8]
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4141-c701e79730169fab373fba7e759497d755fac592/shard-bmg-2/igt@xe_pm@s3-vm-bind-userptr.html
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-bmg-6/igt@xe_pm@s3-vm-bind-userptr.html
- shard-dg2-set2: [PASS][9] -> [ABORT][10]
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4141-c701e79730169fab373fba7e759497d755fac592/shard-dg2-435/igt@xe_pm@s3-vm-bind-userptr.html
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-dg2-433/igt@xe_pm@s3-vm-bind-userptr.html
* igt@xe_pm@s4-basic-exec:
- shard-bmg: NOTRUN -> [ABORT][11]
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-bmg-2/igt@xe_pm@s4-basic-exec.html
* igt@xe_pm_residency@cpg-basic:
- shard-adlp: [PASS][12] -> [ABORT][13] +5 other tests abort
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4141-c701e79730169fab373fba7e759497d755fac592/shard-adlp-6/igt@xe_pm_residency@cpg-basic.html
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-adlp-9/igt@xe_pm_residency@cpg-basic.html
New tests
---------
New tests have been introduced between xe-4141-c701e79730169fab373fba7e759497d755fac592_FULL and xe-pw-157944v1_FULL:
### New IGT tests (17) ###
* igt@kms_content_protection@srm@pipe-a-dp-2:
- Statuses : 1 fail(s)
- Exec time: [112.08] s
* igt@kms_feature_discovery@display-1x:
- Statuses :
- Exec time: [None] s
* igt@kms_flip@absolute-wf_vblank-interruptible@d-dp2:
- Statuses : 1 pass(s)
- Exec time: [4.06] s
* igt@kms_flip@blocking-absolute-wf_vblank-interruptible@d-dp2:
- Statuses : 1 pass(s)
- Exec time: [4.06] s
* igt@kms_flip@dpms-off-confusion@d-dp2:
- Statuses : 1 pass(s)
- Exec time: [4.01] s
* igt@kms_flip@dpms-vs-vblank-race@d-dp2:
- Statuses : 1 pass(s)
- Exec time: [1.70] s
* igt@kms_flip@flip-vs-dpms-off-vs-modeset-interruptible@d-dp2:
- Statuses : 1 pass(s)
- Exec time: [0.72] s
* igt@kms_flip@flip-vs-modeset-vs-hang@d-dp2:
- Statuses : 1 pass(s)
- Exec time: [0.75] s
* igt@kms_flip@flip-vs-panning-vs-hang@d-dp2:
- Statuses : 1 pass(s)
- Exec time: [0.74] s
* igt@kms_flip@modeset-vs-vblank-race@d-dp2:
- Statuses : 1 pass(s)
- Exec time: [1.92] s
* igt@kms_flip@nonexisting-fb-interruptible@d-dp2:
- Statuses : 1 pass(s)
- Exec time: [0.23] s
* igt@kms_flip@plain-flip-fb-recreate-interruptible@d-dp2:
- Statuses : 1 pass(s)
- Exec time: [4.26] s
* igt@kms_flip@plain-flip-ts-check-interruptible@d-dp2:
- Statuses : 1 pass(s)
- Exec time: [4.28] s
* igt@kms_flip@single-buffer-flip-vs-dpms-off-vs-modeset-interruptible@d-dp2:
- Statuses : 1 pass(s)
- Exec time: [0.72] s
* igt@kms_flip@single-buffer-flip-vs-dpms-off-vs-modeset@d-dp2:
- Statuses : 1 pass(s)
- Exec time: [0.73] s
* igt@kms_plane_multiple@tiling-none@pipe-d-dp-2:
- Statuses : 1 pass(s)
- Exec time: [0.95] s
* igt@kms_plane_multiple@tiling-x@pipe-d-dp-2:
- Statuses : 1 pass(s)
- Exec time: [0.94] s
Known issues
------------
Here are the changes found in xe-pw-157944v1_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_async_flips@async-flip-suspend-resume@pipe-a-hdmi-a-1:
- shard-adlp: [PASS][14] -> [DMESG-WARN][15] ([Intel XE#2953] / [Intel XE#4173])
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4141-c701e79730169fab373fba7e759497d755fac592/shard-adlp-8/igt@kms_async_flips@async-flip-suspend-resume@pipe-a-hdmi-a-1.html
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-adlp-3/igt@kms_async_flips@async-flip-suspend-resume@pipe-a-hdmi-a-1.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-90:
- shard-bmg: NOTRUN -> [SKIP][16] ([Intel XE#2327]) +1 other test skip
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-bmg-2/igt@kms_big_fb@4-tiled-64bpp-rotate-90.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-adlp: NOTRUN -> [SKIP][17] ([Intel XE#1124]) +1 other test skip
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-adlp-3/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_big_fb@y-tiled-64bpp-rotate-90:
- shard-adlp: NOTRUN -> [SKIP][18] ([Intel XE#316]) +2 other tests skip
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-adlp-1/igt@kms_big_fb@y-tiled-64bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-bmg: NOTRUN -> [SKIP][19] ([Intel XE#1124]) +3 other tests skip
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-bmg-2/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_bw@connected-linear-tiling-3-displays-2160x1440p:
- shard-adlp: NOTRUN -> [SKIP][20] ([Intel XE#2191])
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-adlp-4/igt@kms_bw@connected-linear-tiling-3-displays-2160x1440p.html
* igt@kms_bw@connected-linear-tiling-4-displays-1920x1080p:
- shard-bmg: NOTRUN -> [SKIP][21] ([Intel XE#2314] / [Intel XE#2894])
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-bmg-1/igt@kms_bw@connected-linear-tiling-4-displays-1920x1080p.html
* igt@kms_bw@linear-tiling-2-displays-2560x1440p:
- shard-adlp: NOTRUN -> [SKIP][22] ([Intel XE#367])
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-adlp-3/igt@kms_bw@linear-tiling-2-displays-2560x1440p.html
* igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs:
- shard-bmg: NOTRUN -> [SKIP][23] ([Intel XE#2887]) +5 other tests skip
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-bmg-1/igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs.html
* igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs@pipe-d-hdmi-a-3:
- shard-bmg: NOTRUN -> [SKIP][24] ([Intel XE#2652] / [Intel XE#787]) +4 other tests skip
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-bmg-2/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs@pipe-d-hdmi-a-3.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-mc-ccs@pipe-d-hdmi-a-1:
- shard-adlp: NOTRUN -> [SKIP][25] ([Intel XE#455] / [Intel XE#787]) +17 other tests skip
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-adlp-8/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-mc-ccs@pipe-d-hdmi-a-1.html
* igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs@pipe-b-hdmi-a-1:
- shard-adlp: NOTRUN -> [SKIP][26] ([Intel XE#787]) +26 other tests skip
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-adlp-3/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs@pipe-b-hdmi-a-1.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs:
- shard-dg2-set2: [PASS][27] -> [INCOMPLETE][28] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4345])
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4141-c701e79730169fab373fba7e759497d755fac592/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-a-dp-4:
- shard-dg2-set2: [PASS][29] -> [INCOMPLETE][30] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212])
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4141-c701e79730169fab373fba7e759497d755fac592/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-a-dp-4.html
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-a-dp-4.html
* igt@kms_chamelium_color@ctm-red-to-blue:
- shard-bmg: NOTRUN -> [SKIP][31] ([Intel XE#2325]) +2 other tests skip
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-bmg-2/igt@kms_chamelium_color@ctm-red-to-blue.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- shard-bmg: NOTRUN -> [SKIP][32] ([Intel XE#2252]) +2 other tests skip
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-bmg-2/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
* igt@kms_chamelium_hpd@vga-hpd-fast:
- shard-adlp: NOTRUN -> [SKIP][33] ([Intel XE#373]) +2 other tests skip
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-adlp-3/igt@kms_chamelium_hpd@vga-hpd-fast.html
* igt@kms_content_protection@atomic:
- shard-bmg: NOTRUN -> [SKIP][34] ([Intel XE#2341]) +1 other test skip
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-bmg-2/igt@kms_content_protection@atomic.html
* igt@kms_cursor_crc@cursor-sliding-64x21:
- shard-bmg: NOTRUN -> [SKIP][35] ([Intel XE#2320]) +4 other tests skip
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-bmg-2/igt@kms_cursor_crc@cursor-sliding-64x21.html
* igt@kms_cursor_edge_walk@128x128-top-bottom:
- shard-adlp: NOTRUN -> [DMESG-WARN][36] ([Intel XE#2953] / [Intel XE#4173])
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-adlp-1/igt@kms_cursor_edge_walk@128x128-top-bottom.html
* igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic:
- shard-adlp: NOTRUN -> [SKIP][37] ([Intel XE#309]) +1 other test skip
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-adlp-1/igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic.html
* igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy:
- shard-bmg: [PASS][38] -> [SKIP][39] ([Intel XE#2291]) +3 other tests skip
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4141-c701e79730169fab373fba7e759497d755fac592/shard-bmg-8/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-bmg-6/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size:
- shard-bmg: NOTRUN -> [SKIP][40] ([Intel XE#2291])
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-bmg-2/igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-legacy:
- shard-bmg: [PASS][41] -> [FAIL][42] ([Intel XE#5299])
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4141-c701e79730169fab373fba7e759497d755fac592/shard-bmg-5/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-bmg-3/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
- shard-adlp: NOTRUN -> [SKIP][43] ([Intel XE#323])
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-adlp-3/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
* igt@kms_dp_link_training@uhbr-mst:
- shard-bmg: NOTRUN -> [SKIP][44] ([Intel XE#4354])
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-bmg-2/igt@kms_dp_link_training@uhbr-mst.html
* igt@kms_dp_linktrain_fallback@dsc-fallback:
- shard-adlp: NOTRUN -> [SKIP][45] ([Intel XE#4331])
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-adlp-4/igt@kms_dp_linktrain_fallback@dsc-fallback.html
* igt@kms_dsc@dsc-with-formats:
- shard-bmg: NOTRUN -> [SKIP][46] ([Intel XE#2244])
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-bmg-1/igt@kms_dsc@dsc-with-formats.html
* igt@kms_fbcon_fbt@psr:
- shard-bmg: NOTRUN -> [SKIP][47] ([Intel XE#776])
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-bmg-2/igt@kms_fbcon_fbt@psr.html
* igt@kms_flip@2x-flip-vs-absolute-wf_vblank:
- shard-bmg: NOTRUN -> [SKIP][48] ([Intel XE#2316])
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-bmg-2/igt@kms_flip@2x-flip-vs-absolute-wf_vblank.html
* igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible:
- shard-adlp: NOTRUN -> [SKIP][49] ([Intel XE#310]) +3 other tests skip
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-adlp-3/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible.html
* igt@kms_flip@2x-flip-vs-dpms-on-nop:
- shard-bmg: [PASS][50] -> [SKIP][51] ([Intel XE#2316]) +3 other tests skip
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4141-c701e79730169fab373fba7e759497d755fac592/shard-bmg-7/igt@kms_flip@2x-flip-vs-dpms-on-nop.html
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-bmg-6/igt@kms_flip@2x-flip-vs-dpms-on-nop.html
* igt@kms_flip@basic-plain-flip@d-hdmi-a1:
- shard-adlp: [PASS][52] -> [DMESG-WARN][53] ([Intel XE#4543]) +1 other test dmesg-warn
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4141-c701e79730169fab373fba7e759497d755fac592/shard-adlp-6/igt@kms_flip@basic-plain-flip@d-hdmi-a1.html
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-adlp-9/igt@kms_flip@basic-plain-flip@d-hdmi-a1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
- shard-lnl: [PASS][54] -> [FAIL][55] ([Intel XE#301])
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4141-c701e79730169fab373fba7e759497d755fac592/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
- shard-lnl: [PASS][56] -> [FAIL][57] ([Intel XE#301] / [Intel XE#3149]) +1 other test fail
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4141-c701e79730169fab373fba7e759497d755fac592/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
* igt@kms_frontbuffer_tracking@drrs-2p-pri-indfb-multidraw:
- shard-bmg: NOTRUN -> [SKIP][58] ([Intel XE#2311]) +8 other tests skip
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-bmg-1/igt@kms_frontbuffer_tracking@drrs-2p-pri-indfb-multidraw.html
* igt@kms_frontbuffer_tracking@drrs-2p-primscrn-indfb-pgflip-blt:
- shard-adlp: NOTRUN -> [SKIP][59] ([Intel XE#656]) +15 other tests skip
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-adlp-1/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-indfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-shrfb-draw-mmap-wc:
- shard-adlp: NOTRUN -> [DMESG-FAIL][60] ([Intel XE#4543]) +1 other test dmesg-fail
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-adlp-4/igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-modesetfrombusy:
- shard-bmg: NOTRUN -> [SKIP][61] ([Intel XE#4141])
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-modesetfrombusy.html
* igt@kms_frontbuffer_tracking@fbcdrrs-1p-offscreen-pri-shrfb-draw-render:
- shard-adlp: NOTRUN -> [SKIP][62] ([Intel XE#6312])
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-adlp-4/igt@kms_frontbuffer_tracking@fbcdrrs-1p-offscreen-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-shrfb-draw-mmap-wc:
- shard-bmg: NOTRUN -> [SKIP][63] ([Intel XE#2312]) +7 other tests skip
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcdrrs-suspend:
- shard-adlp: NOTRUN -> [SKIP][64] ([Intel XE#651]) +4 other tests skip
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-adlp-3/igt@kms_frontbuffer_tracking@fbcdrrs-suspend.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt:
- shard-adlp: NOTRUN -> [SKIP][65] ([Intel XE#653]) +7 other tests skip
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-adlp-3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@psr-suspend:
- shard-bmg: NOTRUN -> [SKIP][66] ([Intel XE#2313]) +6 other tests skip
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-bmg-2/igt@kms_frontbuffer_tracking@psr-suspend.html
* igt@kms_hdr@bpc-switch:
- shard-adlp: NOTRUN -> [SKIP][67] ([Intel XE#455]) +10 other tests skip
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-adlp-4/igt@kms_hdr@bpc-switch.html
* igt@kms_lease@simple-lease:
- shard-bmg: [PASS][68] -> [FAIL][69] ([Intel XE#6549])
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4141-c701e79730169fab373fba7e759497d755fac592/shard-bmg-7/igt@kms_lease@simple-lease.html
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-bmg-6/igt@kms_lease@simple-lease.html
* igt@kms_plane_lowres@tiling-yf:
- shard-bmg: NOTRUN -> [SKIP][70] ([Intel XE#2393])
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-bmg-2/igt@kms_plane_lowres@tiling-yf.html
* igt@kms_plane_multiple@2x-tiling-4:
- shard-bmg: [PASS][71] -> [SKIP][72] ([Intel XE#4596])
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4141-c701e79730169fab373fba7e759497d755fac592/shard-bmg-7/igt@kms_plane_multiple@2x-tiling-4.html
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-bmg-2/igt@kms_plane_multiple@2x-tiling-4.html
* igt@kms_pm_backlight@brightness-with-dpms:
- shard-adlp: NOTRUN -> [SKIP][73] ([Intel XE#2938])
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-adlp-4/igt@kms_pm_backlight@brightness-with-dpms.html
* igt@kms_pm_backlight@fade-with-dpms:
- shard-bmg: NOTRUN -> [SKIP][74] ([Intel XE#870])
[74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-bmg-2/igt@kms_pm_backlight@fade-with-dpms.html
* igt@kms_pm_dc@dc6-psr:
- shard-bmg: NOTRUN -> [SKIP][75] ([Intel XE#2392])
[75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-bmg-1/igt@kms_pm_dc@dc6-psr.html
* igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf:
- shard-bmg: NOTRUN -> [SKIP][76] ([Intel XE#1406] / [Intel XE#1489]) +1 other test skip
[76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-bmg-1/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf.html
* igt@kms_psr2_sf@psr2-overlay-plane-update-continuous-sf:
- shard-adlp: NOTRUN -> [SKIP][77] ([Intel XE#1406] / [Intel XE#1489]) +1 other test skip
[77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-adlp-3/igt@kms_psr2_sf@psr2-overlay-plane-update-continuous-sf.html
* igt@kms_psr2_su@page_flip-xrgb8888:
- shard-bmg: NOTRUN -> [SKIP][78] ([Intel XE#1406] / [Intel XE#2387]) +1 other test skip
[78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-bmg-2/igt@kms_psr2_su@page_flip-xrgb8888.html
* igt@kms_psr@pr-suspend:
- shard-bmg: NOTRUN -> [SKIP][79] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) +2 other tests skip
[79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-bmg-1/igt@kms_psr@pr-suspend.html
* igt@kms_psr@psr2-sprite-blt:
- shard-adlp: NOTRUN -> [SKIP][80] ([Intel XE#1406] / [Intel XE#2850] / [Intel XE#929]) +4 other tests skip
[80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-adlp-4/igt@kms_psr@psr2-sprite-blt.html
* igt@kms_rotation_crc@bad-pixel-format:
- shard-bmg: NOTRUN -> [SKIP][81] ([Intel XE#3414] / [Intel XE#3904]) +1 other test skip
[81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-bmg-1/igt@kms_rotation_crc@bad-pixel-format.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-180:
- shard-bmg: NOTRUN -> [SKIP][82] ([Intel XE#2330])
[82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-bmg-2/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
- shard-adlp: NOTRUN -> [SKIP][83] ([Intel XE#1127])
[83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-adlp-4/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
* igt@xe_ccs@ctrl-surf-copy:
- shard-adlp: NOTRUN -> [SKIP][84] ([Intel XE#455] / [Intel XE#488] / [Intel XE#5607])
[84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-adlp-4/igt@xe_ccs@ctrl-surf-copy.html
* igt@xe_ccs@large-ctrl-surf-copy:
- shard-adlp: NOTRUN -> [SKIP][85] ([Intel XE#3576] / [Intel XE#5610])
[85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-adlp-4/igt@xe_ccs@large-ctrl-surf-copy.html
* igt@xe_copy_basic@mem-page-copy-1:
- shard-adlp: NOTRUN -> [SKIP][86] ([Intel XE#5300])
[86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-adlp-3/igt@xe_copy_basic@mem-page-copy-1.html
* igt@xe_eu_stall@blocking-read:
- shard-adlp: NOTRUN -> [SKIP][87] ([Intel XE#5626])
[87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-adlp-4/igt@xe_eu_stall@blocking-read.html
* igt@xe_eudebug_online@stopped-thread:
- shard-bmg: NOTRUN -> [SKIP][88] ([Intel XE#4837]) +5 other tests skip
[88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-bmg-2/igt@xe_eudebug_online@stopped-thread.html
* igt@xe_evict@evict-beng-small-external-cm:
- shard-adlp: NOTRUN -> [SKIP][89] ([Intel XE#261] / [Intel XE#5564] / [Intel XE#688])
[89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-adlp-4/igt@xe_evict@evict-beng-small-external-cm.html
* igt@xe_evict@evict-mixed-many-threads-small:
- shard-adlp: NOTRUN -> [SKIP][90] ([Intel XE#261])
[90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-adlp-4/igt@xe_evict@evict-mixed-many-threads-small.html
* igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-rebind:
- shard-adlp: NOTRUN -> [SKIP][91] ([Intel XE#1392] / [Intel XE#5575]) +2 other tests skip
[91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-adlp-3/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-rebind.html
* igt@xe_exec_basic@multigpu-no-exec-basic:
- shard-bmg: NOTRUN -> [SKIP][92] ([Intel XE#2322]) +2 other tests skip
[92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-bmg-1/igt@xe_exec_basic@multigpu-no-exec-basic.html
* igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-invalidate-race-imm:
- shard-adlp: NOTRUN -> [SKIP][93] ([Intel XE#288] / [Intel XE#5561]) +14 other tests skip
[93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-adlp-1/igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-invalidate-race-imm.html
* igt@xe_exec_sip_eudebug@breakpoint-writesip-nodebug:
- shard-adlp: NOTRUN -> [SKIP][94] ([Intel XE#4837] / [Intel XE#5565]) +6 other tests skip
[94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-adlp-4/igt@xe_exec_sip_eudebug@breakpoint-writesip-nodebug.html
* igt@xe_exec_system_allocator@once-mmap-huge-nomemset:
- shard-adlp: NOTRUN -> [SKIP][95] ([Intel XE#4915]) +144 other tests skip
[95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-adlp-4/igt@xe_exec_system_allocator@once-mmap-huge-nomemset.html
* igt@xe_exec_system_allocator@threads-many-large-execqueues-mmap-new-huge:
- shard-bmg: NOTRUN -> [SKIP][96] ([Intel XE#4943]) +5 other tests skip
[96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-bmg-2/igt@xe_exec_system_allocator@threads-many-large-execqueues-mmap-new-huge.html
* igt@xe_live_ktest@xe_eudebug:
- shard-adlp: NOTRUN -> [SKIP][97] ([Intel XE#455] / [Intel XE#5712])
[97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-adlp-3/igt@xe_live_ktest@xe_eudebug.html
* igt@xe_oa@non-zero-reason:
- shard-adlp: NOTRUN -> [SKIP][98] ([Intel XE#3573]) +2 other tests skip
[98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-adlp-3/igt@xe_oa@non-zero-reason.html
* igt@xe_pat@pat-index-xehpc:
- shard-bmg: NOTRUN -> [SKIP][99] ([Intel XE#1420])
[99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-bmg-2/igt@xe_pat@pat-index-xehpc.html
* igt@xe_peer2peer@write:
- shard-adlp: NOTRUN -> [SKIP][100] ([Intel XE#1061])
[100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-adlp-4/igt@xe_peer2peer@write.html
* igt@xe_pm@d3cold-i2c:
- shard-bmg: NOTRUN -> [SKIP][101] ([Intel XE#5694])
[101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-bmg-2/igt@xe_pm@d3cold-i2c.html
* igt@xe_pm@d3cold-mocs:
- shard-bmg: NOTRUN -> [SKIP][102] ([Intel XE#2284])
[102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-bmg-2/igt@xe_pm@d3cold-mocs.html
* igt@xe_pxp@pxp-stale-bo-bind-post-rpm:
- shard-adlp: NOTRUN -> [SKIP][103] ([Intel XE#4733] / [Intel XE#5594])
[103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-adlp-3/igt@xe_pxp@pxp-stale-bo-bind-post-rpm.html
* igt@xe_query@multigpu-query-invalid-uc-fw-version-mbz:
- shard-adlp: NOTRUN -> [SKIP][104] ([Intel XE#944])
[104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-adlp-4/igt@xe_query@multigpu-query-invalid-uc-fw-version-mbz.html
* igt@xe_query@multigpu-query-mem-usage:
- shard-bmg: NOTRUN -> [SKIP][105] ([Intel XE#944]) +1 other test skip
[105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-bmg-1/igt@xe_query@multigpu-query-mem-usage.html
#### Possible fixes ####
* igt@kms_atomic_transition@plane-toggle-modeset-transition:
- shard-adlp: [FAIL][106] ([Intel XE#3908]) -> [PASS][107] +1 other test pass
[106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4141-c701e79730169fab373fba7e759497d755fac592/shard-adlp-2/igt@kms_atomic_transition@plane-toggle-modeset-transition.html
[107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-adlp-4/igt@kms_atomic_transition@plane-toggle-modeset-transition.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions:
- shard-bmg: [SKIP][108] ([Intel XE#2291]) -> [PASS][109]
[108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4141-c701e79730169fab373fba7e759497d755fac592/shard-bmg-6/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html
[109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-bmg-8/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html
* igt@kms_feature_discovery@display-2x:
- shard-bmg: [SKIP][110] ([Intel XE#2373]) -> [PASS][111]
[110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4141-c701e79730169fab373fba7e759497d755fac592/shard-bmg-6/igt@kms_feature_discovery@display-2x.html
[111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-bmg-8/igt@kms_feature_discovery@display-2x.html
* igt@kms_flip@2x-flip-vs-blocking-wf-vblank:
- shard-bmg: [SKIP][112] ([Intel XE#2316]) -> [PASS][113] +3 other tests pass
[112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4141-c701e79730169fab373fba7e759497d755fac592/shard-bmg-6/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html
[113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-bmg-8/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html
* igt@kms_vblank@ts-continuation-suspend:
- shard-adlp: [ABORT][114] -> [PASS][115] +5 other tests pass
[114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4141-c701e79730169fab373fba7e759497d755fac592/shard-adlp-1/igt@kms_vblank@ts-continuation-suspend.html
[115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-adlp-3/igt@kms_vblank@ts-continuation-suspend.html
* igt@kms_vblank@ts-continuation-suspend@pipe-a-edp-1:
- shard-lnl: [ABORT][116] -> [PASS][117]
[116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4141-c701e79730169fab373fba7e759497d755fac592/shard-lnl-5/igt@kms_vblank@ts-continuation-suspend@pipe-a-edp-1.html
[117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-lnl-1/igt@kms_vblank@ts-continuation-suspend@pipe-a-edp-1.html
* igt@kms_vblank@ts-continuation-suspend@pipe-a-hdmi-a-6:
- shard-dg2-set2: [ABORT][118] -> [PASS][119]
[118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4141-c701e79730169fab373fba7e759497d755fac592/shard-dg2-463/igt@kms_vblank@ts-continuation-suspend@pipe-a-hdmi-a-6.html
[119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-dg2-463/igt@kms_vblank@ts-continuation-suspend@pipe-a-hdmi-a-6.html
* igt@xe_pm@s2idle-vm-bind-unbind-all:
- shard-bmg: [ABORT][120] -> [PASS][121] +2 other tests pass
[120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4141-c701e79730169fab373fba7e759497d755fac592/shard-bmg-7/igt@xe_pm@s2idle-vm-bind-unbind-all.html
[121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-bmg-1/igt@xe_pm@s2idle-vm-bind-unbind-all.html
* igt@xe_pmu@engine-activity-accuracy-50@engine-drm_xe_engine_class_video_decode0:
- shard-lnl: [FAIL][122] ([Intel XE#6251]) -> [PASS][123]
[122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4141-c701e79730169fab373fba7e759497d755fac592/shard-lnl-3/igt@xe_pmu@engine-activity-accuracy-50@engine-drm_xe_engine_class_video_decode0.html
[123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-lnl-7/igt@xe_pmu@engine-activity-accuracy-50@engine-drm_xe_engine_class_video_decode0.html
#### Warnings ####
* igt@kms_async_flips@async-flip-suspend-resume:
- shard-adlp: [ABORT][124] -> [ABORT][125] ([Intel XE#2953])
[124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4141-c701e79730169fab373fba7e759497d755fac592/shard-adlp-8/igt@kms_async_flips@async-flip-suspend-resume.html
[125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-adlp-3/igt@kms_async_flips@async-flip-suspend-resume.html
* igt@kms_flip@2x-flip-vs-suspend:
- shard-bmg: [ABORT][126] -> [SKIP][127] ([Intel XE#2316])
[126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4141-c701e79730169fab373fba7e759497d755fac592/shard-bmg-7/igt@kms_flip@2x-flip-vs-suspend.html
[127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-bmg-2/igt@kms_flip@2x-flip-vs-suspend.html
* igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-mmap-wc:
- shard-bmg: [SKIP][128] ([Intel XE#2312]) -> [SKIP][129] ([Intel XE#2311]) +4 other tests skip
[128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4141-c701e79730169fab373fba7e759497d755fac592/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-mmap-wc.html
[129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-bmg-8/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render:
- shard-bmg: [SKIP][130] ([Intel XE#4141]) -> [SKIP][131] ([Intel XE#2312]) +4 other tests skip
[130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4141-c701e79730169fab373fba7e759497d755fac592/shard-bmg-8/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render.html
[131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-draw-render:
- shard-bmg: [SKIP][132] ([Intel XE#2311]) -> [SKIP][133] ([Intel XE#2312]) +6 other tests skip
[132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4141-c701e79730169fab373fba7e759497d755fac592/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-draw-render.html
[133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt:
- shard-bmg: [SKIP][134] ([Intel XE#2313]) -> [SKIP][135] ([Intel XE#2312]) +5 other tests skip
[134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4141-c701e79730169fab373fba7e759497d755fac592/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt.html
[135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt:
- shard-bmg: [SKIP][136] ([Intel XE#2312]) -> [SKIP][137] ([Intel XE#2313]) +5 other tests skip
[136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4141-c701e79730169fab373fba7e759497d755fac592/shard-bmg-6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html
[137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/shard-bmg-8/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html
[Intel XE#1061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1061
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127
[Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
[Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
[Intel XE#1420]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1420
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
[Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
[Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
[Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
[Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
[Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
[Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
[Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
[Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
[Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
[Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
[Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
[Intel XE#2330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2330
[Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
[Intel XE#2373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2373
[Intel XE#2387]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2387
[Intel XE#2392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2392
[Intel XE#2393]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2393
[Intel XE#261]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/261
[Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
[Intel XE#2705]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2705
[Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
[Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
[Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
[Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
[Intel XE#2938]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2938
[Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
[Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
[Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
[Intel XE#310]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/310
[Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
[Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
[Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
[Intel XE#323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/323
[Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
[Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
[Intel XE#3576]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3576
[Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
[Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
[Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
[Intel XE#3908]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3908
[Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
[Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
[Intel XE#4212]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4212
[Intel XE#4331]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4331
[Intel XE#4345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4345
[Intel XE#4354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4354
[Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
[Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
[Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
[Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
[Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
[Intel XE#488]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/488
[Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
[Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
[Intel XE#5299]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5299
[Intel XE#5300]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5300
[Intel XE#5561]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5561
[Intel XE#5564]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5564
[Intel XE#5565]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5565
[Intel XE#5575]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5575
[Intel XE#5594]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5594
[Intel XE#5607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5607
[Intel XE#5610]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5610
[Intel XE#5626]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5626
[Intel XE#5694]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5694
[Intel XE#5712]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5712
[Intel XE#6251]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6251
[Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
[Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
[Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
[Intel XE#6549]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6549
[Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
[Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
[Intel XE#776]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/776
[Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
[Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
[Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
[Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
Build changes
-------------
* Linux: xe-4141-c701e79730169fab373fba7e759497d755fac592 -> xe-pw-157944v1
IGT_8636: 254cd102396ff95d61f2ebe49fc09128878bf483 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-4141-c701e79730169fab373fba7e759497d755fac592: c701e79730169fab373fba7e759497d755fac592
xe-pw-157944v1: 157944v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157944v1/index.html
[-- Attachment #2: Type: text/html, Size: 49554 bytes --]
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v3 2/2] drm/i915/xe3p_lpd: Enable display use of system cache for FBC
2025-11-24 16:25 ` Jani Nikula
@ 2025-11-25 8:56 ` Govindapillai, Vinod
2025-11-25 9:21 ` Jani Nikula
0 siblings, 1 reply; 14+ messages in thread
From: Govindapillai, Vinod @ 2025-11-25 8:56 UTC (permalink / raw)
To: intel-xe@lists.freedesktop.org, Nikula, Jani,
intel-gfx@lists.freedesktop.org
Cc: Sousa, Gustavo, Roper, Matthew D, Syrjala, Ville
On Mon, 2025-11-24 at 18:25 +0200, Jani Nikula wrote:
> On Sun, 23 Nov 2025, Vinod Govindapillai
> <vinod.govindapillai@intel.com> wrote:
> > One of the FBC instances can utilize the reserved area of SoC
> > level cache for the fbc transactions to benefit reduced memory
> > system power especially in idle scenarios. Reserved area of the
> > system cache can be assigned to an fbc instance by configuring
> > the cacheability configuration register with offset of the
> > compressed frame buffer in stolen memoty of that fbc. There is
> > a limit to this reserved area which is programmable and for
> > xe3p_lpd the limit is defined as 2MB.
> >
> > v2: - better to track fbc sys cache usage from intel_display level,
> > sanitize the cacheability config register on probe (Matt)
> > - limit this for integrated graphics solutions, confirmed that
> > no default value set for cache range by hw (Gustavo)
> >
> > v3: - changes related to the use of fbc substruct in intel_display
> > - use intel_de_write() instead of intel_rmw() by hardcoding the
> > default value fields
>
> Overall issue: The fbc mutexes are per fbc instance, but nothing
> protects display->fbc.sys_cache_id.
The places where this sys_cache_id can be changed to a valid fbc
instance id + fbc cfb offset are protected by the fbc mutex as part of
intel_fbc_enable and intel_fbc_disable. That's is what I was mentioning
in my prev reply. And the places where this sys cache usage register
reset happens is outside the fbc context - where sanitize and remove
module gets called. I don't see a need to update the fbc.sys_cache_id
from anywhere else.
BR
Vinod
>
> BR,
> Jani.
>
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v3 2/2] drm/i915/xe3p_lpd: Enable display use of system cache for FBC
2025-11-25 8:56 ` Govindapillai, Vinod
@ 2025-11-25 9:21 ` Jani Nikula
0 siblings, 0 replies; 14+ messages in thread
From: Jani Nikula @ 2025-11-25 9:21 UTC (permalink / raw)
To: Govindapillai, Vinod, intel-xe@lists.freedesktop.org,
intel-gfx@lists.freedesktop.org
Cc: Sousa, Gustavo, Roper, Matthew D, Syrjala, Ville
On Tue, 25 Nov 2025, "Govindapillai, Vinod" <vinod.govindapillai@intel.com> wrote:
> On Mon, 2025-11-24 at 18:25 +0200, Jani Nikula wrote:
>> On Sun, 23 Nov 2025, Vinod Govindapillai
>> <vinod.govindapillai@intel.com> wrote:
>> > One of the FBC instances can utilize the reserved area of SoC
>> > level cache for the fbc transactions to benefit reduced memory
>> > system power especially in idle scenarios. Reserved area of the
>> > system cache can be assigned to an fbc instance by configuring
>> > the cacheability configuration register with offset of the
>> > compressed frame buffer in stolen memoty of that fbc. There is
>> > a limit to this reserved area which is programmable and for
>> > xe3p_lpd the limit is defined as 2MB.
>> >
>> > v2: - better to track fbc sys cache usage from intel_display level,
>> > sanitize the cacheability config register on probe (Matt)
>> > - limit this for integrated graphics solutions, confirmed that
>> > no default value set for cache range by hw (Gustavo)
>> >
>> > v3: - changes related to the use of fbc substruct in intel_display
>> > - use intel_de_write() instead of intel_rmw() by hardcoding the
>> > default value fields
>>
>> Overall issue: The fbc mutexes are per fbc instance, but nothing
>> protects display->fbc.sys_cache_id.
>
> The places where this sys_cache_id can be changed to a valid fbc
> instance id + fbc cfb offset are protected by the fbc mutex as part of
> intel_fbc_enable and intel_fbc_disable. That's is what I was mentioning
> in my prev reply. And the places where this sys cache usage register
> reset happens is outside the fbc context - where sanitize and remove
> module gets called. I don't see a need to update the fbc.sys_cache_id
> from anywhere else.
That's not the point. Each FBC instance has its own mutex. Two FBC
instance mutexes could be held at the same time. I don't think this is
the case during enable/disable, though. But the point remains, the
instance mutex can't protect something that's not part of the instance.
BR,
Jani.
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2025-11-25 9:21 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-11-23 16:01 [PATCH v3 0/2] drm/i915/display: Enable system cache support for FBC Vinod Govindapillai
2025-11-23 16:01 ` [PATCH v3 1/2] drm/i915/display: Use a sub-struct for fbc operations in intel_display Vinod Govindapillai
2025-11-24 10:54 ` Jani Nikula
2025-11-23 16:01 ` [PATCH v3 2/2] drm/i915/xe3p_lpd: Enable display use of system cache for FBC Vinod Govindapillai
2025-11-24 11:27 ` Jani Nikula
2025-11-24 13:32 ` Govindapillai, Vinod
2025-11-24 16:23 ` Jani Nikula
2025-11-24 16:25 ` Jani Nikula
2025-11-25 8:56 ` Govindapillai, Vinod
2025-11-25 9:21 ` Jani Nikula
2025-11-25 0:28 ` ✗ CI.checkpatch: warning for drm/i915/display: Enable system cache support " Patchwork
2025-11-25 0:29 ` ✓ CI.KUnit: success " Patchwork
2025-11-25 1:07 ` ✓ Xe.CI.BAT: " Patchwork
2025-11-25 3:06 ` ✗ Xe.CI.Full: failure " Patchwork
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