* [PATCH 0/2] drm/i915/psr: Refactor and extend SCL handling for VRRTG
@ 2026-05-15 7:36 Ankit Nautiyal
2026-05-15 7:36 ` [PATCH 1/2] drm/i915/psr: Simplify the conditions for SCL computation Ankit Nautiyal
` (4 more replies)
0 siblings, 5 replies; 7+ messages in thread
From: Ankit Nautiyal @ 2026-05-15 7:36 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jouni.hogander, Ankit Nautiyal
Simplify the PSR SCL (Set Context Latency) condition logic, then extend it
to support always-on VRR timing generator where SCL can be 0.
Ankit Nautiyal (2):
drm/i915/psr: Simplify the conditions for SCL computation
drm/i915/psr: Allow SCL=0 on platforms with always-on VRR TG
drivers/gpu/drm/i915/display/intel_psr.c | 14 ++++++--------
1 file changed, 6 insertions(+), 8 deletions(-)
--
2.45.2
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 1/2] drm/i915/psr: Simplify the conditions for SCL computation
2026-05-15 7:36 [PATCH 0/2] drm/i915/psr: Refactor and extend SCL handling for VRRTG Ankit Nautiyal
@ 2026-05-15 7:36 ` Ankit Nautiyal
2026-05-15 10:30 ` Jani Nikula
2026-05-15 7:36 ` [PATCH 2/2] drm/i915/psr: Allow SCL=0 on platforms with always-on VRR TG Ankit Nautiyal
` (3 subsequent siblings)
4 siblings, 1 reply; 7+ messages in thread
From: Ankit Nautiyal @ 2026-05-15 7:36 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jouni.hogander, Ankit Nautiyal
The SCL condition checks can be combined into one expression.
needs_sel_update is common for both display version branches, so check it
once and keep the version specific checks together.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 13 +++++--------
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 8f70b7dcd881..5bf1d782188c 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1477,15 +1477,12 @@ int _intel_psr_min_set_context_latency(const struct intel_crtc_state *crtc_state
* SRD_STATUS is used by PSR1 and Panel Replay DP on LunarLake.
*/
- if (DISPLAY_VER(display) >= 30 && (needs_panel_replay ||
- needs_sel_update))
+ if (needs_sel_update ||
+ (DISPLAY_VER(display) >= 30 && needs_panel_replay) ||
+ (DISPLAY_VER(display) < 30 && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)))
return 0;
- else if (DISPLAY_VER(display) < 30 && (needs_sel_update ||
- intel_crtc_has_type(crtc_state,
- INTEL_OUTPUT_EDP)))
- return 0;
- else
- return 1;
+
+ return 1;
}
static bool _wake_lines_fit_into_vblank(const struct intel_crtc_state *crtc_state,
--
2.45.2
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/2] drm/i915/psr: Allow SCL=0 on platforms with always-on VRR TG
2026-05-15 7:36 [PATCH 0/2] drm/i915/psr: Refactor and extend SCL handling for VRRTG Ankit Nautiyal
2026-05-15 7:36 ` [PATCH 1/2] drm/i915/psr: Simplify the conditions for SCL computation Ankit Nautiyal
@ 2026-05-15 7:36 ` Ankit Nautiyal
2026-05-15 7:56 ` ✗ CI.checkpatch: warning for drm/i915/psr: Refactor and extend SCL handling for VRRTG Patchwork
` (2 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Ankit Nautiyal @ 2026-05-15 7:36 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jouni.hogander, Ankit Nautiyal
For Legacy timing generator, if there are no panel replay/sel_update or other
SRD constraints, the Set context latency (SCL) window should be at least 1.
However, for VRR timing generator the SCL window can be 0. It has other
guardband constraints, but that are checked during guardband computation.
Allow SCL to be 0 for platforms that have VRR TG always on.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 5bf1d782188c..12c2e2a70bd8 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1477,7 +1477,8 @@ int _intel_psr_min_set_context_latency(const struct intel_crtc_state *crtc_state
* SRD_STATUS is used by PSR1 and Panel Replay DP on LunarLake.
*/
- if (needs_sel_update ||
+ if (intel_vrr_always_use_vrr_tg(display) ||
+ needs_sel_update ||
(DISPLAY_VER(display) >= 30 && needs_panel_replay) ||
(DISPLAY_VER(display) < 30 && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)))
return 0;
--
2.45.2
^ permalink raw reply related [flat|nested] 7+ messages in thread
* ✗ CI.checkpatch: warning for drm/i915/psr: Refactor and extend SCL handling for VRRTG
2026-05-15 7:36 [PATCH 0/2] drm/i915/psr: Refactor and extend SCL handling for VRRTG Ankit Nautiyal
2026-05-15 7:36 ` [PATCH 1/2] drm/i915/psr: Simplify the conditions for SCL computation Ankit Nautiyal
2026-05-15 7:36 ` [PATCH 2/2] drm/i915/psr: Allow SCL=0 on platforms with always-on VRR TG Ankit Nautiyal
@ 2026-05-15 7:56 ` Patchwork
2026-05-15 7:57 ` ✓ CI.KUnit: success " Patchwork
2026-05-15 8:35 ` ✓ Xe.CI.BAT: " Patchwork
4 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2026-05-15 7:56 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-xe
== Series Details ==
Series: drm/i915/psr: Refactor and extend SCL handling for VRRTG
URL : https://patchwork.freedesktop.org/series/166628/
State : warning
== Summary ==
+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
061140b9bc586ae7f40abc1249c97e1cc72d1b9d
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 6ba16d6d9a20013d2eb34b3f821c10a3ac7321ff
Author: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Date: Fri May 15 13:06:16 2026 +0530
drm/i915/psr: Allow SCL=0 on platforms with always-on VRR TG
For Legacy timing generator, if there are no panel replay/sel_update or other
SRD constraints, the Set context latency (SCL) window should be at least 1.
However, for VRR timing generator the SCL window can be 0. It has other
guardband constraints, but that are checked during guardband computation.
Allow SCL to be 0 for platforms that have VRR TG always on.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
+ /mt/dim checkpatch b9819223b7e92173091b674c2212252b99ea6c4b drm-intel
15ec86ffb0ba drm/i915/psr: Simplify the conditions for SCL computation
6ba16d6d9a20 drm/i915/psr: Allow SCL=0 on platforms with always-on VRR TG
-:6: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line (possible unwrapped commit description?)
#6:
For Legacy timing generator, if there are no panel replay/sel_update or other
total: 0 errors, 1 warnings, 0 checks, 9 lines checked
^ permalink raw reply [flat|nested] 7+ messages in thread
* ✓ CI.KUnit: success for drm/i915/psr: Refactor and extend SCL handling for VRRTG
2026-05-15 7:36 [PATCH 0/2] drm/i915/psr: Refactor and extend SCL handling for VRRTG Ankit Nautiyal
` (2 preceding siblings ...)
2026-05-15 7:56 ` ✗ CI.checkpatch: warning for drm/i915/psr: Refactor and extend SCL handling for VRRTG Patchwork
@ 2026-05-15 7:57 ` Patchwork
2026-05-15 8:35 ` ✓ Xe.CI.BAT: " Patchwork
4 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2026-05-15 7:57 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-xe
== Series Details ==
Series: drm/i915/psr: Refactor and extend SCL handling for VRRTG
URL : https://patchwork.freedesktop.org/series/166628/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[07:56:09] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[07:56:14] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[07:56:45] Starting KUnit Kernel (1/1)...
[07:56:45] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[07:56:45] ================== guc_buf (11 subtests) ===================
[07:56:45] [PASSED] test_smallest
[07:56:45] [PASSED] test_largest
[07:56:45] [PASSED] test_granular
[07:56:45] [PASSED] test_unique
[07:56:45] [PASSED] test_overlap
[07:56:45] [PASSED] test_reusable
[07:56:45] [PASSED] test_too_big
[07:56:45] [PASSED] test_flush
[07:56:45] [PASSED] test_lookup
[07:56:45] [PASSED] test_data
[07:56:45] [PASSED] test_class
[07:56:45] ===================== [PASSED] guc_buf =====================
[07:56:45] =================== guc_dbm (7 subtests) ===================
[07:56:45] [PASSED] test_empty
[07:56:45] [PASSED] test_default
[07:56:45] ======================== test_size ========================
[07:56:45] [PASSED] 4
[07:56:45] [PASSED] 8
[07:56:45] [PASSED] 32
[07:56:45] [PASSED] 256
[07:56:45] ==================== [PASSED] test_size ====================
[07:56:45] ======================= test_reuse ========================
[07:56:45] [PASSED] 4
[07:56:45] [PASSED] 8
[07:56:45] [PASSED] 32
[07:56:45] [PASSED] 256
[07:56:45] =================== [PASSED] test_reuse ====================
[07:56:45] =================== test_range_overlap ====================
[07:56:45] [PASSED] 4
[07:56:45] [PASSED] 8
[07:56:45] [PASSED] 32
[07:56:45] [PASSED] 256
[07:56:45] =============== [PASSED] test_range_overlap ================
[07:56:45] =================== test_range_compact ====================
[07:56:45] [PASSED] 4
[07:56:45] [PASSED] 8
[07:56:45] [PASSED] 32
[07:56:45] [PASSED] 256
[07:56:45] =============== [PASSED] test_range_compact ================
[07:56:45] ==================== test_range_spare =====================
[07:56:45] [PASSED] 4
[07:56:45] [PASSED] 8
[07:56:45] [PASSED] 32
[07:56:45] [PASSED] 256
[07:56:45] ================ [PASSED] test_range_spare =================
[07:56:45] ===================== [PASSED] guc_dbm =====================
[07:56:45] =================== guc_idm (6 subtests) ===================
[07:56:45] [PASSED] bad_init
[07:56:45] [PASSED] no_init
[07:56:45] [PASSED] init_fini
[07:56:45] [PASSED] check_used
[07:56:45] [PASSED] check_quota
[07:56:45] [PASSED] check_all
[07:56:45] ===================== [PASSED] guc_idm =====================
[07:56:45] ================== no_relay (3 subtests) ===================
[07:56:45] [PASSED] xe_drops_guc2pf_if_not_ready
[07:56:45] [PASSED] xe_drops_guc2vf_if_not_ready
[07:56:45] [PASSED] xe_rejects_send_if_not_ready
[07:56:45] ==================== [PASSED] no_relay =====================
[07:56:45] ================== pf_relay (14 subtests) ==================
[07:56:45] [PASSED] pf_rejects_guc2pf_too_short
[07:56:45] [PASSED] pf_rejects_guc2pf_too_long
[07:56:45] [PASSED] pf_rejects_guc2pf_no_payload
[07:56:45] [PASSED] pf_fails_no_payload
[07:56:45] [PASSED] pf_fails_bad_origin
[07:56:45] [PASSED] pf_fails_bad_type
[07:56:45] [PASSED] pf_txn_reports_error
[07:56:45] [PASSED] pf_txn_sends_pf2guc
[07:56:45] [PASSED] pf_sends_pf2guc
[07:56:45] [SKIPPED] pf_loopback_nop
[07:56:45] [SKIPPED] pf_loopback_echo
[07:56:45] [SKIPPED] pf_loopback_fail
[07:56:45] [SKIPPED] pf_loopback_busy
[07:56:45] [SKIPPED] pf_loopback_retry
[07:56:45] ==================== [PASSED] pf_relay =====================
[07:56:45] ================== vf_relay (3 subtests) ===================
[07:56:45] [PASSED] vf_rejects_guc2vf_too_short
[07:56:45] [PASSED] vf_rejects_guc2vf_too_long
[07:56:45] [PASSED] vf_rejects_guc2vf_no_payload
[07:56:45] ==================== [PASSED] vf_relay =====================
[07:56:45] ================ pf_gt_config (9 subtests) =================
[07:56:45] [PASSED] fair_contexts_1vf
[07:56:45] [PASSED] fair_doorbells_1vf
[07:56:45] [PASSED] fair_ggtt_1vf
[07:56:45] ====================== fair_vram_1vf ======================
[07:56:45] [PASSED] 3.50 GiB
[07:56:45] [PASSED] 11.5 GiB
[07:56:45] [PASSED] 15.5 GiB
[07:56:45] [PASSED] 31.5 GiB
[07:56:45] [PASSED] 63.5 GiB
[07:56:45] [PASSED] 1.91 GiB
[07:56:45] ================== [PASSED] fair_vram_1vf ==================
[07:56:45] ================ fair_vram_1vf_admin_only =================
[07:56:45] [PASSED] 3.50 GiB
[07:56:45] [PASSED] 11.5 GiB
[07:56:45] [PASSED] 15.5 GiB
[07:56:45] [PASSED] 31.5 GiB
[07:56:45] [PASSED] 63.5 GiB
[07:56:45] [PASSED] 1.91 GiB
[07:56:45] ============ [PASSED] fair_vram_1vf_admin_only =============
[07:56:45] ====================== fair_contexts ======================
[07:56:45] [PASSED] 1 VF
[07:56:45] [PASSED] 2 VFs
[07:56:45] [PASSED] 3 VFs
[07:56:45] [PASSED] 4 VFs
[07:56:45] [PASSED] 5 VFs
[07:56:45] [PASSED] 6 VFs
[07:56:45] [PASSED] 7 VFs
[07:56:45] [PASSED] 8 VFs
[07:56:45] [PASSED] 9 VFs
[07:56:45] [PASSED] 10 VFs
[07:56:45] [PASSED] 11 VFs
[07:56:45] [PASSED] 12 VFs
[07:56:45] [PASSED] 13 VFs
[07:56:45] [PASSED] 14 VFs
[07:56:45] [PASSED] 15 VFs
[07:56:45] [PASSED] 16 VFs
[07:56:45] [PASSED] 17 VFs
[07:56:45] [PASSED] 18 VFs
[07:56:45] [PASSED] 19 VFs
[07:56:45] [PASSED] 20 VFs
[07:56:45] [PASSED] 21 VFs
[07:56:45] [PASSED] 22 VFs
[07:56:45] [PASSED] 23 VFs
[07:56:45] [PASSED] 24 VFs
[07:56:45] [PASSED] 25 VFs
[07:56:45] [PASSED] 26 VFs
[07:56:45] [PASSED] 27 VFs
[07:56:45] [PASSED] 28 VFs
[07:56:45] [PASSED] 29 VFs
[07:56:45] [PASSED] 30 VFs
[07:56:45] [PASSED] 31 VFs
[07:56:45] [PASSED] 32 VFs
[07:56:45] [PASSED] 33 VFs
[07:56:45] [PASSED] 34 VFs
[07:56:45] [PASSED] 35 VFs
[07:56:45] [PASSED] 36 VFs
[07:56:45] [PASSED] 37 VFs
[07:56:45] [PASSED] 38 VFs
[07:56:45] [PASSED] 39 VFs
[07:56:45] [PASSED] 40 VFs
[07:56:45] [PASSED] 41 VFs
[07:56:45] [PASSED] 42 VFs
[07:56:45] [PASSED] 43 VFs
[07:56:45] [PASSED] 44 VFs
[07:56:45] [PASSED] 45 VFs
[07:56:45] [PASSED] 46 VFs
[07:56:45] [PASSED] 47 VFs
[07:56:45] [PASSED] 48 VFs
[07:56:45] [PASSED] 49 VFs
[07:56:45] [PASSED] 50 VFs
[07:56:45] [PASSED] 51 VFs
[07:56:45] [PASSED] 52 VFs
[07:56:45] [PASSED] 53 VFs
[07:56:45] [PASSED] 54 VFs
[07:56:45] [PASSED] 55 VFs
[07:56:45] [PASSED] 56 VFs
[07:56:45] [PASSED] 57 VFs
[07:56:45] [PASSED] 58 VFs
[07:56:45] [PASSED] 59 VFs
[07:56:45] [PASSED] 60 VFs
[07:56:45] [PASSED] 61 VFs
[07:56:45] [PASSED] 62 VFs
[07:56:45] [PASSED] 63 VFs
[07:56:45] ================== [PASSED] fair_contexts ==================
[07:56:45] ===================== fair_doorbells ======================
[07:56:45] [PASSED] 1 VF
[07:56:45] [PASSED] 2 VFs
[07:56:45] [PASSED] 3 VFs
[07:56:45] [PASSED] 4 VFs
[07:56:45] [PASSED] 5 VFs
[07:56:45] [PASSED] 6 VFs
[07:56:45] [PASSED] 7 VFs
[07:56:45] [PASSED] 8 VFs
[07:56:45] [PASSED] 9 VFs
[07:56:45] [PASSED] 10 VFs
[07:56:45] [PASSED] 11 VFs
[07:56:45] [PASSED] 12 VFs
[07:56:45] [PASSED] 13 VFs
[07:56:45] [PASSED] 14 VFs
[07:56:45] [PASSED] 15 VFs
[07:56:45] [PASSED] 16 VFs
[07:56:45] [PASSED] 17 VFs
[07:56:45] [PASSED] 18 VFs
[07:56:45] [PASSED] 19 VFs
[07:56:45] [PASSED] 20 VFs
[07:56:45] [PASSED] 21 VFs
[07:56:45] [PASSED] 22 VFs
[07:56:45] [PASSED] 23 VFs
[07:56:45] [PASSED] 24 VFs
[07:56:45] [PASSED] 25 VFs
[07:56:45] [PASSED] 26 VFs
[07:56:45] [PASSED] 27 VFs
[07:56:45] [PASSED] 28 VFs
[07:56:45] [PASSED] 29 VFs
[07:56:45] [PASSED] 30 VFs
[07:56:45] [PASSED] 31 VFs
[07:56:45] [PASSED] 32 VFs
[07:56:45] [PASSED] 33 VFs
[07:56:45] [PASSED] 34 VFs
[07:56:45] [PASSED] 35 VFs
[07:56:45] [PASSED] 36 VFs
[07:56:45] [PASSED] 37 VFs
[07:56:45] [PASSED] 38 VFs
[07:56:45] [PASSED] 39 VFs
[07:56:45] [PASSED] 40 VFs
[07:56:45] [PASSED] 41 VFs
[07:56:45] [PASSED] 42 VFs
[07:56:45] [PASSED] 43 VFs
[07:56:45] [PASSED] 44 VFs
[07:56:45] [PASSED] 45 VFs
[07:56:45] [PASSED] 46 VFs
[07:56:45] [PASSED] 47 VFs
[07:56:45] [PASSED] 48 VFs
[07:56:45] [PASSED] 49 VFs
[07:56:45] [PASSED] 50 VFs
[07:56:45] [PASSED] 51 VFs
[07:56:45] [PASSED] 52 VFs
[07:56:45] [PASSED] 53 VFs
[07:56:45] [PASSED] 54 VFs
[07:56:45] [PASSED] 55 VFs
[07:56:45] [PASSED] 56 VFs
[07:56:46] [PASSED] 57 VFs
[07:56:46] [PASSED] 58 VFs
[07:56:46] [PASSED] 59 VFs
[07:56:46] [PASSED] 60 VFs
[07:56:46] [PASSED] 61 VFs
[07:56:46] [PASSED] 62 VFs
[07:56:46] [PASSED] 63 VFs
[07:56:46] ================= [PASSED] fair_doorbells ==================
[07:56:46] ======================== fair_ggtt ========================
[07:56:46] [PASSED] 1 VF
[07:56:46] [PASSED] 2 VFs
[07:56:46] [PASSED] 3 VFs
[07:56:46] [PASSED] 4 VFs
[07:56:46] [PASSED] 5 VFs
[07:56:46] [PASSED] 6 VFs
[07:56:46] [PASSED] 7 VFs
[07:56:46] [PASSED] 8 VFs
[07:56:46] [PASSED] 9 VFs
[07:56:46] [PASSED] 10 VFs
[07:56:46] [PASSED] 11 VFs
[07:56:46] [PASSED] 12 VFs
[07:56:46] [PASSED] 13 VFs
[07:56:46] [PASSED] 14 VFs
[07:56:46] [PASSED] 15 VFs
[07:56:46] [PASSED] 16 VFs
[07:56:46] [PASSED] 17 VFs
[07:56:46] [PASSED] 18 VFs
[07:56:46] [PASSED] 19 VFs
[07:56:46] [PASSED] 20 VFs
[07:56:46] [PASSED] 21 VFs
[07:56:46] [PASSED] 22 VFs
[07:56:46] [PASSED] 23 VFs
[07:56:46] [PASSED] 24 VFs
[07:56:46] [PASSED] 25 VFs
[07:56:46] [PASSED] 26 VFs
[07:56:46] [PASSED] 27 VFs
[07:56:46] [PASSED] 28 VFs
[07:56:46] [PASSED] 29 VFs
[07:56:46] [PASSED] 30 VFs
[07:56:46] [PASSED] 31 VFs
[07:56:46] [PASSED] 32 VFs
[07:56:46] [PASSED] 33 VFs
[07:56:46] [PASSED] 34 VFs
[07:56:46] [PASSED] 35 VFs
[07:56:46] [PASSED] 36 VFs
[07:56:46] [PASSED] 37 VFs
[07:56:46] [PASSED] 38 VFs
[07:56:46] [PASSED] 39 VFs
[07:56:46] [PASSED] 40 VFs
[07:56:46] [PASSED] 41 VFs
[07:56:46] [PASSED] 42 VFs
[07:56:46] [PASSED] 43 VFs
[07:56:46] [PASSED] 44 VFs
[07:56:46] [PASSED] 45 VFs
[07:56:46] [PASSED] 46 VFs
[07:56:46] [PASSED] 47 VFs
[07:56:46] [PASSED] 48 VFs
[07:56:46] [PASSED] 49 VFs
[07:56:46] [PASSED] 50 VFs
[07:56:46] [PASSED] 51 VFs
[07:56:46] [PASSED] 52 VFs
[07:56:46] [PASSED] 53 VFs
[07:56:46] [PASSED] 54 VFs
[07:56:46] [PASSED] 55 VFs
[07:56:46] [PASSED] 56 VFs
[07:56:46] [PASSED] 57 VFs
[07:56:46] [PASSED] 58 VFs
[07:56:46] [PASSED] 59 VFs
[07:56:46] [PASSED] 60 VFs
[07:56:46] [PASSED] 61 VFs
[07:56:46] [PASSED] 62 VFs
[07:56:46] [PASSED] 63 VFs
[07:56:46] ==================== [PASSED] fair_ggtt ====================
[07:56:46] ======================== fair_vram ========================
[07:56:46] [PASSED] 1 VF
[07:56:46] [PASSED] 2 VFs
[07:56:46] [PASSED] 3 VFs
[07:56:46] [PASSED] 4 VFs
[07:56:46] [PASSED] 5 VFs
[07:56:46] [PASSED] 6 VFs
[07:56:46] [PASSED] 7 VFs
[07:56:46] [PASSED] 8 VFs
[07:56:46] [PASSED] 9 VFs
[07:56:46] [PASSED] 10 VFs
[07:56:46] [PASSED] 11 VFs
[07:56:46] [PASSED] 12 VFs
[07:56:46] [PASSED] 13 VFs
[07:56:46] [PASSED] 14 VFs
[07:56:46] [PASSED] 15 VFs
[07:56:46] [PASSED] 16 VFs
[07:56:46] [PASSED] 17 VFs
[07:56:46] [PASSED] 18 VFs
[07:56:46] [PASSED] 19 VFs
[07:56:46] [PASSED] 20 VFs
[07:56:46] [PASSED] 21 VFs
[07:56:46] [PASSED] 22 VFs
[07:56:46] [PASSED] 23 VFs
[07:56:46] [PASSED] 24 VFs
[07:56:46] [PASSED] 25 VFs
[07:56:46] [PASSED] 26 VFs
[07:56:46] [PASSED] 27 VFs
[07:56:46] [PASSED] 28 VFs
[07:56:46] [PASSED] 29 VFs
[07:56:46] [PASSED] 30 VFs
[07:56:46] [PASSED] 31 VFs
[07:56:46] [PASSED] 32 VFs
[07:56:46] [PASSED] 33 VFs
[07:56:46] [PASSED] 34 VFs
[07:56:46] [PASSED] 35 VFs
[07:56:46] [PASSED] 36 VFs
[07:56:46] [PASSED] 37 VFs
[07:56:46] [PASSED] 38 VFs
[07:56:46] [PASSED] 39 VFs
[07:56:46] [PASSED] 40 VFs
[07:56:46] [PASSED] 41 VFs
[07:56:46] [PASSED] 42 VFs
[07:56:46] [PASSED] 43 VFs
[07:56:46] [PASSED] 44 VFs
[07:56:46] [PASSED] 45 VFs
[07:56:46] [PASSED] 46 VFs
[07:56:46] [PASSED] 47 VFs
[07:56:46] [PASSED] 48 VFs
[07:56:46] [PASSED] 49 VFs
[07:56:46] [PASSED] 50 VFs
[07:56:46] [PASSED] 51 VFs
[07:56:46] [PASSED] 52 VFs
[07:56:46] [PASSED] 53 VFs
[07:56:46] [PASSED] 54 VFs
[07:56:46] [PASSED] 55 VFs
[07:56:46] [PASSED] 56 VFs
[07:56:46] [PASSED] 57 VFs
[07:56:46] [PASSED] 58 VFs
[07:56:46] [PASSED] 59 VFs
[07:56:46] [PASSED] 60 VFs
[07:56:46] [PASSED] 61 VFs
[07:56:46] [PASSED] 62 VFs
[07:56:46] [PASSED] 63 VFs
[07:56:46] ==================== [PASSED] fair_vram ====================
[07:56:46] ================== [PASSED] pf_gt_config ===================
[07:56:46] ===================== lmtt (1 subtest) =====================
[07:56:46] ======================== test_ops =========================
[07:56:46] [PASSED] 2-level
[07:56:46] [PASSED] multi-level
[07:56:46] ==================== [PASSED] test_ops =====================
[07:56:46] ====================== [PASSED] lmtt =======================
[07:56:46] ================= pf_service (11 subtests) =================
[07:56:46] [PASSED] pf_negotiate_any
[07:56:46] [PASSED] pf_negotiate_base_match
[07:56:46] [PASSED] pf_negotiate_base_newer
[07:56:46] [PASSED] pf_negotiate_base_next
[07:56:46] [SKIPPED] pf_negotiate_base_older
[07:56:46] [PASSED] pf_negotiate_base_prev
[07:56:46] [PASSED] pf_negotiate_latest_match
[07:56:46] [PASSED] pf_negotiate_latest_newer
[07:56:46] [PASSED] pf_negotiate_latest_next
[07:56:46] [SKIPPED] pf_negotiate_latest_older
[07:56:46] [SKIPPED] pf_negotiate_latest_prev
[07:56:46] =================== [PASSED] pf_service ====================
[07:56:46] ================= xe_guc_g2g (2 subtests) ==================
[07:56:46] ============== xe_live_guc_g2g_kunit_default ==============
[07:56:46] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[07:56:46] ============== xe_live_guc_g2g_kunit_allmem ===============
[07:56:46] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[07:56:46] =================== [SKIPPED] xe_guc_g2g ===================
[07:56:46] =================== xe_mocs (2 subtests) ===================
[07:56:46] ================ xe_live_mocs_kernel_kunit ================
[07:56:46] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[07:56:46] ================ xe_live_mocs_reset_kunit =================
[07:56:46] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[07:56:46] ==================== [SKIPPED] xe_mocs =====================
[07:56:46] ================= xe_migrate (2 subtests) ==================
[07:56:46] ================= xe_migrate_sanity_kunit =================
[07:56:46] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[07:56:46] ================== xe_validate_ccs_kunit ==================
[07:56:46] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[07:56:46] =================== [SKIPPED] xe_migrate ===================
[07:56:46] ================== xe_dma_buf (1 subtest) ==================
[07:56:46] ==================== xe_dma_buf_kunit =====================
[07:56:46] ================ [SKIPPED] xe_dma_buf_kunit ================
[07:56:46] =================== [SKIPPED] xe_dma_buf ===================
[07:56:46] ================= xe_bo_shrink (1 subtest) =================
[07:56:46] =================== xe_bo_shrink_kunit ====================
[07:56:46] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[07:56:46] ================== [SKIPPED] xe_bo_shrink ==================
[07:56:46] ==================== xe_bo (2 subtests) ====================
[07:56:46] ================== xe_ccs_migrate_kunit ===================
[07:56:46] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[07:56:46] ==================== xe_bo_evict_kunit ====================
[07:56:46] =============== [SKIPPED] xe_bo_evict_kunit ================
[07:56:46] ===================== [SKIPPED] xe_bo ======================
[07:56:46] ==================== args (13 subtests) ====================
[07:56:46] [PASSED] count_args_test
[07:56:46] [PASSED] call_args_example
[07:56:46] [PASSED] call_args_test
[07:56:46] [PASSED] drop_first_arg_example
[07:56:46] [PASSED] drop_first_arg_test
[07:56:46] [PASSED] first_arg_example
[07:56:46] [PASSED] first_arg_test
[07:56:46] [PASSED] last_arg_example
[07:56:46] [PASSED] last_arg_test
[07:56:46] [PASSED] pick_arg_example
[07:56:46] [PASSED] if_args_example
[07:56:46] [PASSED] if_args_test
[07:56:46] [PASSED] sep_comma_example
[07:56:46] ====================== [PASSED] args =======================
[07:56:46] =================== xe_pci (3 subtests) ====================
[07:56:46] ==================== check_graphics_ip ====================
[07:56:46] [PASSED] 12.00 Xe_LP
[07:56:46] [PASSED] 12.10 Xe_LP+
[07:56:46] [PASSED] 12.55 Xe_HPG
[07:56:46] [PASSED] 12.60 Xe_HPC
[07:56:46] [PASSED] 12.70 Xe_LPG
[07:56:46] [PASSED] 12.71 Xe_LPG
[07:56:46] [PASSED] 12.74 Xe_LPG+
[07:56:46] [PASSED] 20.01 Xe2_HPG
[07:56:46] [PASSED] 20.02 Xe2_HPG
[07:56:46] [PASSED] 20.04 Xe2_LPG
[07:56:46] [PASSED] 30.00 Xe3_LPG
[07:56:46] [PASSED] 30.01 Xe3_LPG
[07:56:46] [PASSED] 30.03 Xe3_LPG
[07:56:46] [PASSED] 30.04 Xe3_LPG
[07:56:46] [PASSED] 30.05 Xe3_LPG
[07:56:46] [PASSED] 35.10 Xe3p_LPG
[07:56:46] [PASSED] 35.11 Xe3p_XPC
[07:56:46] ================ [PASSED] check_graphics_ip ================
[07:56:46] ===================== check_media_ip ======================
[07:56:46] [PASSED] 12.00 Xe_M
[07:56:46] [PASSED] 12.55 Xe_HPM
[07:56:46] [PASSED] 13.00 Xe_LPM+
[07:56:46] [PASSED] 13.01 Xe2_HPM
[07:56:46] [PASSED] 20.00 Xe2_LPM
[07:56:46] [PASSED] 30.00 Xe3_LPM
[07:56:46] [PASSED] 30.02 Xe3_LPM
[07:56:46] [PASSED] 35.00 Xe3p_LPM
[07:56:46] [PASSED] 35.03 Xe3p_HPM
[07:56:46] ================= [PASSED] check_media_ip ==================
[07:56:46] =================== check_platform_desc ===================
[07:56:46] [PASSED] 0x9A60 (TIGERLAKE)
[07:56:46] [PASSED] 0x9A68 (TIGERLAKE)
[07:56:46] [PASSED] 0x9A70 (TIGERLAKE)
[07:56:46] [PASSED] 0x9A40 (TIGERLAKE)
[07:56:46] [PASSED] 0x9A49 (TIGERLAKE)
[07:56:46] [PASSED] 0x9A59 (TIGERLAKE)
[07:56:46] [PASSED] 0x9A78 (TIGERLAKE)
[07:56:46] [PASSED] 0x9AC0 (TIGERLAKE)
[07:56:46] [PASSED] 0x9AC9 (TIGERLAKE)
[07:56:46] [PASSED] 0x9AD9 (TIGERLAKE)
[07:56:46] [PASSED] 0x9AF8 (TIGERLAKE)
[07:56:46] [PASSED] 0x4C80 (ROCKETLAKE)
[07:56:46] [PASSED] 0x4C8A (ROCKETLAKE)
[07:56:46] [PASSED] 0x4C8B (ROCKETLAKE)
[07:56:46] [PASSED] 0x4C8C (ROCKETLAKE)
[07:56:46] [PASSED] 0x4C90 (ROCKETLAKE)
[07:56:46] [PASSED] 0x4C9A (ROCKETLAKE)
[07:56:46] [PASSED] 0x4680 (ALDERLAKE_S)
[07:56:46] [PASSED] 0x4682 (ALDERLAKE_S)
[07:56:46] [PASSED] 0x4688 (ALDERLAKE_S)
[07:56:46] [PASSED] 0x468A (ALDERLAKE_S)
[07:56:46] [PASSED] 0x468B (ALDERLAKE_S)
[07:56:46] [PASSED] 0x4690 (ALDERLAKE_S)
[07:56:46] [PASSED] 0x4692 (ALDERLAKE_S)
[07:56:46] [PASSED] 0x4693 (ALDERLAKE_S)
[07:56:46] [PASSED] 0x46A0 (ALDERLAKE_P)
[07:56:46] [PASSED] 0x46A1 (ALDERLAKE_P)
[07:56:46] [PASSED] 0x46A2 (ALDERLAKE_P)
[07:56:46] [PASSED] 0x46A3 (ALDERLAKE_P)
[07:56:46] [PASSED] 0x46A6 (ALDERLAKE_P)
[07:56:46] [PASSED] 0x46A8 (ALDERLAKE_P)
[07:56:46] [PASSED] 0x46AA (ALDERLAKE_P)
[07:56:46] [PASSED] 0x462A (ALDERLAKE_P)
[07:56:46] [PASSED] 0x4626 (ALDERLAKE_P)
[07:56:46] [PASSED] 0x4628 (ALDERLAKE_P)
[07:56:46] [PASSED] 0x46B0 (ALDERLAKE_P)
[07:56:46] [PASSED] 0x46B1 (ALDERLAKE_P)
[07:56:46] [PASSED] 0x46B2 (ALDERLAKE_P)
[07:56:46] [PASSED] 0x46B3 (ALDERLAKE_P)
[07:56:46] [PASSED] 0x46C0 (ALDERLAKE_P)
[07:56:46] [PASSED] 0x46C1 (ALDERLAKE_P)
[07:56:46] [PASSED] 0x46C2 (ALDERLAKE_P)
[07:56:46] [PASSED] 0x46C3 (ALDERLAKE_P)
[07:56:46] [PASSED] 0x46D0 (ALDERLAKE_N)
[07:56:46] [PASSED] 0x46D1 (ALDERLAKE_N)
[07:56:46] [PASSED] 0x46D2 (ALDERLAKE_N)
[07:56:46] [PASSED] 0x46D3 (ALDERLAKE_N)
[07:56:46] [PASSED] 0x46D4 (ALDERLAKE_N)
[07:56:46] [PASSED] 0xA721 (ALDERLAKE_P)
[07:56:46] [PASSED] 0xA7A1 (ALDERLAKE_P)
[07:56:46] [PASSED] 0xA7A9 (ALDERLAKE_P)
[07:56:46] [PASSED] 0xA7AC (ALDERLAKE_P)
[07:56:46] [PASSED] 0xA7AD (ALDERLAKE_P)
[07:56:46] [PASSED] 0xA720 (ALDERLAKE_P)
[07:56:46] [PASSED] 0xA7A0 (ALDERLAKE_P)
[07:56:46] [PASSED] 0xA7A8 (ALDERLAKE_P)
[07:56:46] [PASSED] 0xA7AA (ALDERLAKE_P)
[07:56:46] [PASSED] 0xA7AB (ALDERLAKE_P)
[07:56:46] [PASSED] 0xA780 (ALDERLAKE_S)
[07:56:46] [PASSED] 0xA781 (ALDERLAKE_S)
[07:56:46] [PASSED] 0xA782 (ALDERLAKE_S)
[07:56:46] [PASSED] 0xA783 (ALDERLAKE_S)
[07:56:46] [PASSED] 0xA788 (ALDERLAKE_S)
[07:56:46] [PASSED] 0xA789 (ALDERLAKE_S)
[07:56:46] [PASSED] 0xA78A (ALDERLAKE_S)
[07:56:46] [PASSED] 0xA78B (ALDERLAKE_S)
[07:56:46] [PASSED] 0x4905 (DG1)
[07:56:46] [PASSED] 0x4906 (DG1)
[07:56:46] [PASSED] 0x4907 (DG1)
[07:56:46] [PASSED] 0x4908 (DG1)
[07:56:46] [PASSED] 0x4909 (DG1)
[07:56:46] [PASSED] 0x56C0 (DG2)
[07:56:46] [PASSED] 0x56C2 (DG2)
[07:56:46] [PASSED] 0x56C1 (DG2)
[07:56:46] [PASSED] 0x7D51 (METEORLAKE)
[07:56:46] [PASSED] 0x7DD1 (METEORLAKE)
[07:56:46] [PASSED] 0x7D41 (METEORLAKE)
[07:56:46] [PASSED] 0x7D67 (METEORLAKE)
[07:56:46] [PASSED] 0xB640 (METEORLAKE)
[07:56:46] [PASSED] 0x56A0 (DG2)
[07:56:46] [PASSED] 0x56A1 (DG2)
[07:56:46] [PASSED] 0x56A2 (DG2)
[07:56:46] [PASSED] 0x56BE (DG2)
[07:56:46] [PASSED] 0x56BF (DG2)
[07:56:46] [PASSED] 0x5690 (DG2)
[07:56:46] [PASSED] 0x5691 (DG2)
[07:56:46] [PASSED] 0x5692 (DG2)
[07:56:46] [PASSED] 0x56A5 (DG2)
[07:56:46] [PASSED] 0x56A6 (DG2)
[07:56:46] [PASSED] 0x56B0 (DG2)
[07:56:46] [PASSED] 0x56B1 (DG2)
[07:56:46] [PASSED] 0x56BA (DG2)
[07:56:46] [PASSED] 0x56BB (DG2)
[07:56:46] [PASSED] 0x56BC (DG2)
[07:56:46] [PASSED] 0x56BD (DG2)
[07:56:46] [PASSED] 0x5693 (DG2)
[07:56:46] [PASSED] 0x5694 (DG2)
[07:56:46] [PASSED] 0x5695 (DG2)
[07:56:46] [PASSED] 0x56A3 (DG2)
[07:56:46] [PASSED] 0x56A4 (DG2)
[07:56:46] [PASSED] 0x56B2 (DG2)
[07:56:46] [PASSED] 0x56B3 (DG2)
[07:56:46] [PASSED] 0x5696 (DG2)
[07:56:46] [PASSED] 0x5697 (DG2)
[07:56:46] [PASSED] 0xB69 (PVC)
[07:56:46] [PASSED] 0xB6E (PVC)
[07:56:46] [PASSED] 0xBD4 (PVC)
[07:56:46] [PASSED] 0xBD5 (PVC)
[07:56:46] [PASSED] 0xBD6 (PVC)
[07:56:46] [PASSED] 0xBD7 (PVC)
[07:56:46] [PASSED] 0xBD8 (PVC)
[07:56:46] [PASSED] 0xBD9 (PVC)
[07:56:46] [PASSED] 0xBDA (PVC)
[07:56:46] [PASSED] 0xBDB (PVC)
[07:56:46] [PASSED] 0xBE0 (PVC)
[07:56:46] [PASSED] 0xBE1 (PVC)
[07:56:46] [PASSED] 0xBE5 (PVC)
[07:56:46] [PASSED] 0x7D40 (METEORLAKE)
[07:56:46] [PASSED] 0x7D45 (METEORLAKE)
[07:56:46] [PASSED] 0x7D55 (METEORLAKE)
[07:56:46] [PASSED] 0x7D60 (METEORLAKE)
[07:56:46] [PASSED] 0x7DD5 (METEORLAKE)
[07:56:46] [PASSED] 0x6420 (LUNARLAKE)
[07:56:46] [PASSED] 0x64A0 (LUNARLAKE)
[07:56:46] [PASSED] 0x64B0 (LUNARLAKE)
[07:56:46] [PASSED] 0xE202 (BATTLEMAGE)
[07:56:46] [PASSED] 0xE209 (BATTLEMAGE)
[07:56:46] [PASSED] 0xE20B (BATTLEMAGE)
[07:56:46] [PASSED] 0xE20C (BATTLEMAGE)
[07:56:46] [PASSED] 0xE20D (BATTLEMAGE)
[07:56:46] [PASSED] 0xE210 (BATTLEMAGE)
[07:56:46] [PASSED] 0xE211 (BATTLEMAGE)
[07:56:46] [PASSED] 0xE212 (BATTLEMAGE)
[07:56:46] [PASSED] 0xE216 (BATTLEMAGE)
[07:56:46] [PASSED] 0xE220 (BATTLEMAGE)
[07:56:46] [PASSED] 0xE221 (BATTLEMAGE)
[07:56:46] [PASSED] 0xE222 (BATTLEMAGE)
[07:56:46] [PASSED] 0xE223 (BATTLEMAGE)
[07:56:46] [PASSED] 0xB080 (PANTHERLAKE)
[07:56:46] [PASSED] 0xB081 (PANTHERLAKE)
[07:56:46] [PASSED] 0xB082 (PANTHERLAKE)
[07:56:46] [PASSED] 0xB083 (PANTHERLAKE)
[07:56:46] [PASSED] 0xB084 (PANTHERLAKE)
[07:56:46] [PASSED] 0xB085 (PANTHERLAKE)
[07:56:46] [PASSED] 0xB086 (PANTHERLAKE)
[07:56:46] [PASSED] 0xB087 (PANTHERLAKE)
[07:56:46] [PASSED] 0xB08F (PANTHERLAKE)
[07:56:46] [PASSED] 0xB090 (PANTHERLAKE)
[07:56:46] [PASSED] 0xB0A0 (PANTHERLAKE)
[07:56:46] [PASSED] 0xB0B0 (PANTHERLAKE)
[07:56:46] [PASSED] 0xFD80 (PANTHERLAKE)
[07:56:46] [PASSED] 0xFD81 (PANTHERLAKE)
[07:56:46] [PASSED] 0xD740 (NOVALAKE_S)
[07:56:46] [PASSED] 0xD741 (NOVALAKE_S)
[07:56:46] [PASSED] 0xD742 (NOVALAKE_S)
[07:56:46] [PASSED] 0xD743 (NOVALAKE_S)
[07:56:46] [PASSED] 0xD744 (NOVALAKE_S)
[07:56:46] [PASSED] 0xD745 (NOVALAKE_S)
[07:56:46] [PASSED] 0x674C (CRESCENTISLAND)
[07:56:46] [PASSED] 0x674D (CRESCENTISLAND)
[07:56:46] [PASSED] 0x674E (CRESCENTISLAND)
[07:56:46] [PASSED] 0x674F (CRESCENTISLAND)
[07:56:46] [PASSED] 0x6750 (CRESCENTISLAND)
[07:56:46] [PASSED] 0xD750 (NOVALAKE_P)
[07:56:46] [PASSED] 0xD751 (NOVALAKE_P)
[07:56:46] [PASSED] 0xD752 (NOVALAKE_P)
[07:56:46] [PASSED] 0xD753 (NOVALAKE_P)
[07:56:46] [PASSED] 0xD754 (NOVALAKE_P)
[07:56:46] [PASSED] 0xD755 (NOVALAKE_P)
[07:56:46] [PASSED] 0xD756 (NOVALAKE_P)
[07:56:46] [PASSED] 0xD757 (NOVALAKE_P)
[07:56:46] [PASSED] 0xD75F (NOVALAKE_P)
[07:56:46] =============== [PASSED] check_platform_desc ===============
[07:56:46] ===================== [PASSED] xe_pci ======================
[07:56:46] =================== xe_rtp (2 subtests) ====================
[07:56:46] =============== xe_rtp_process_to_sr_tests ================
[07:56:46] [PASSED] coalesce-same-reg
[07:56:46] [PASSED] no-match-no-add
[07:56:46] [PASSED] match-or
[07:56:46] [PASSED] match-or-xfail
[07:56:46] [PASSED] no-match-no-add-multiple-rules
[07:56:46] [PASSED] two-regs-two-entries
[07:56:46] [PASSED] clr-one-set-other
[07:56:46] [PASSED] set-field
[07:56:46] [PASSED] conflict-duplicate
[07:56:46] [PASSED] conflict-not-disjoint
[07:56:46] [PASSED] conflict-reg-type
[07:56:46] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[07:56:46] ================== xe_rtp_process_tests ===================
[07:56:46] [PASSED] active1
[07:56:46] [PASSED] active2
[07:56:46] [PASSED] active-inactive
[07:56:46] [PASSED] inactive-active
[07:56:46] [PASSED] inactive-1st_or_active-inactive
[07:56:46] [PASSED] inactive-2nd_or_active-inactive
[07:56:46] [PASSED] inactive-last_or_active-inactive
[07:56:46] [PASSED] inactive-no_or_active-inactive
[07:56:46] ============== [PASSED] xe_rtp_process_tests ===============
[07:56:46] ===================== [PASSED] xe_rtp ======================
[07:56:46] ==================== xe_wa (1 subtest) =====================
[07:56:46] ======================== xe_wa_gt =========================
[07:56:46] [PASSED] TIGERLAKE B0
[07:56:46] [PASSED] DG1 A0
[07:56:46] [PASSED] DG1 B0
[07:56:46] [PASSED] ALDERLAKE_S A0
[07:56:46] [PASSED] ALDERLAKE_S B0
[07:56:46] [PASSED] ALDERLAKE_S C0
[07:56:46] [PASSED] ALDERLAKE_S D0
[07:56:46] [PASSED] ALDERLAKE_P A0
[07:56:46] [PASSED] ALDERLAKE_P B0
[07:56:46] [PASSED] ALDERLAKE_P C0
[07:56:46] [PASSED] ALDERLAKE_S RPLS D0
[07:56:46] [PASSED] ALDERLAKE_P RPLU E0
[07:56:46] [PASSED] DG2 G10 C0
[07:56:46] [PASSED] DG2 G11 B1
[07:56:46] [PASSED] DG2 G12 A1
[07:56:46] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[07:56:46] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[07:56:46] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[07:56:46] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[07:56:46] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[07:56:46] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[07:56:46] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[07:56:46] ==================== [PASSED] xe_wa_gt =====================
[07:56:46] ====================== [PASSED] xe_wa ======================
[07:56:46] ============================================================
[07:56:46] Testing complete. Ran 601 tests: passed: 583, skipped: 18
[07:56:46] Elapsed time: 36.304s total, 4.296s configuring, 31.389s building, 0.614s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[07:56:46] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[07:56:48] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[07:57:12] Starting KUnit Kernel (1/1)...
[07:57:12] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[07:57:12] ============ drm_test_pick_cmdline (2 subtests) ============
[07:57:12] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[07:57:12] =============== drm_test_pick_cmdline_named ===============
[07:57:12] [PASSED] NTSC
[07:57:12] [PASSED] NTSC-J
[07:57:12] [PASSED] PAL
[07:57:12] [PASSED] PAL-M
[07:57:12] =========== [PASSED] drm_test_pick_cmdline_named ===========
[07:57:12] ============== [PASSED] drm_test_pick_cmdline ==============
[07:57:12] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[07:57:12] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[07:57:12] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[07:57:12] =========== drm_validate_clone_mode (2 subtests) ===========
[07:57:12] ============== drm_test_check_in_clone_mode ===============
[07:57:12] [PASSED] in_clone_mode
[07:57:12] [PASSED] not_in_clone_mode
[07:57:12] ========== [PASSED] drm_test_check_in_clone_mode ===========
[07:57:12] =============== drm_test_check_valid_clones ===============
[07:57:12] [PASSED] not_in_clone_mode
[07:57:12] [PASSED] valid_clone
[07:57:12] [PASSED] invalid_clone
[07:57:12] =========== [PASSED] drm_test_check_valid_clones ===========
[07:57:12] ============= [PASSED] drm_validate_clone_mode =============
[07:57:12] ============= drm_validate_modeset (1 subtest) =============
[07:57:12] [PASSED] drm_test_check_connector_changed_modeset
[07:57:12] ============== [PASSED] drm_validate_modeset ===============
[07:57:12] ====== drm_test_bridge_get_current_state (2 subtests) ======
[07:57:12] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[07:57:12] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[07:57:12] ======== [PASSED] drm_test_bridge_get_current_state ========
[07:57:12] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[07:57:12] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[07:57:12] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[07:57:12] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[07:57:12] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[07:57:12] ============== drm_bridge_alloc (2 subtests) ===============
[07:57:12] [PASSED] drm_test_drm_bridge_alloc_basic
[07:57:12] [PASSED] drm_test_drm_bridge_alloc_get_put
[07:57:12] ================ [PASSED] drm_bridge_alloc =================
[07:57:12] ============= drm_cmdline_parser (40 subtests) =============
[07:57:12] [PASSED] drm_test_cmdline_force_d_only
[07:57:12] [PASSED] drm_test_cmdline_force_D_only_dvi
[07:57:12] [PASSED] drm_test_cmdline_force_D_only_hdmi
[07:57:12] [PASSED] drm_test_cmdline_force_D_only_not_digital
[07:57:12] [PASSED] drm_test_cmdline_force_e_only
[07:57:12] [PASSED] drm_test_cmdline_res
[07:57:12] [PASSED] drm_test_cmdline_res_vesa
[07:57:12] [PASSED] drm_test_cmdline_res_vesa_rblank
[07:57:12] [PASSED] drm_test_cmdline_res_rblank
[07:57:12] [PASSED] drm_test_cmdline_res_bpp
[07:57:12] [PASSED] drm_test_cmdline_res_refresh
[07:57:12] [PASSED] drm_test_cmdline_res_bpp_refresh
[07:57:12] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[07:57:12] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[07:57:12] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[07:57:12] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[07:57:12] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[07:57:12] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[07:57:12] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[07:57:12] [PASSED] drm_test_cmdline_res_margins_force_on
[07:57:12] [PASSED] drm_test_cmdline_res_vesa_margins
[07:57:12] [PASSED] drm_test_cmdline_name
[07:57:12] [PASSED] drm_test_cmdline_name_bpp
[07:57:12] [PASSED] drm_test_cmdline_name_option
[07:57:12] [PASSED] drm_test_cmdline_name_bpp_option
[07:57:12] [PASSED] drm_test_cmdline_rotate_0
[07:57:12] [PASSED] drm_test_cmdline_rotate_90
[07:57:12] [PASSED] drm_test_cmdline_rotate_180
[07:57:12] [PASSED] drm_test_cmdline_rotate_270
[07:57:12] [PASSED] drm_test_cmdline_hmirror
[07:57:12] [PASSED] drm_test_cmdline_vmirror
[07:57:12] [PASSED] drm_test_cmdline_margin_options
[07:57:12] [PASSED] drm_test_cmdline_multiple_options
[07:57:12] [PASSED] drm_test_cmdline_bpp_extra_and_option
[07:57:12] [PASSED] drm_test_cmdline_extra_and_option
[07:57:12] [PASSED] drm_test_cmdline_freestanding_options
[07:57:12] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[07:57:12] [PASSED] drm_test_cmdline_panel_orientation
[07:57:12] ================ drm_test_cmdline_invalid =================
[07:57:12] [PASSED] margin_only
[07:57:12] [PASSED] interlace_only
[07:57:12] [PASSED] res_missing_x
[07:57:12] [PASSED] res_missing_y
[07:57:12] [PASSED] res_bad_y
[07:57:12] [PASSED] res_missing_y_bpp
[07:57:12] [PASSED] res_bad_bpp
[07:57:12] [PASSED] res_bad_refresh
[07:57:12] [PASSED] res_bpp_refresh_force_on_off
[07:57:12] [PASSED] res_invalid_mode
[07:57:12] [PASSED] res_bpp_wrong_place_mode
[07:57:12] [PASSED] name_bpp_refresh
[07:57:12] [PASSED] name_refresh
[07:57:12] [PASSED] name_refresh_wrong_mode
[07:57:12] [PASSED] name_refresh_invalid_mode
[07:57:12] [PASSED] rotate_multiple
[07:57:12] [PASSED] rotate_invalid_val
[07:57:12] [PASSED] rotate_truncated
[07:57:12] [PASSED] invalid_option
[07:57:12] [PASSED] invalid_tv_option
[07:57:12] [PASSED] truncated_tv_option
[07:57:12] ============ [PASSED] drm_test_cmdline_invalid =============
[07:57:12] =============== drm_test_cmdline_tv_options ===============
[07:57:12] [PASSED] NTSC
[07:57:12] [PASSED] NTSC_443
[07:57:12] [PASSED] NTSC_J
[07:57:12] [PASSED] PAL
[07:57:12] [PASSED] PAL_M
[07:57:12] [PASSED] PAL_N
[07:57:12] [PASSED] SECAM
[07:57:12] [PASSED] MONO_525
[07:57:12] [PASSED] MONO_625
[07:57:12] =========== [PASSED] drm_test_cmdline_tv_options ===========
[07:57:12] =============== [PASSED] drm_cmdline_parser ================
[07:57:12] ========== drmm_connector_hdmi_init (20 subtests) ==========
[07:57:12] [PASSED] drm_test_connector_hdmi_init_valid
[07:57:12] [PASSED] drm_test_connector_hdmi_init_bpc_8
[07:57:12] [PASSED] drm_test_connector_hdmi_init_bpc_10
[07:57:12] [PASSED] drm_test_connector_hdmi_init_bpc_12
[07:57:12] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[07:57:12] [PASSED] drm_test_connector_hdmi_init_bpc_null
[07:57:12] [PASSED] drm_test_connector_hdmi_init_formats_empty
[07:57:12] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[07:57:12] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[07:57:12] [PASSED] supported_formats=0x9 yuv420_allowed=1
[07:57:12] [PASSED] supported_formats=0x9 yuv420_allowed=0
[07:57:12] [PASSED] supported_formats=0x5 yuv420_allowed=1
[07:57:12] [PASSED] supported_formats=0x5 yuv420_allowed=0
[07:57:12] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[07:57:12] [PASSED] drm_test_connector_hdmi_init_null_ddc
[07:57:12] [PASSED] drm_test_connector_hdmi_init_null_product
[07:57:12] [PASSED] drm_test_connector_hdmi_init_null_vendor
[07:57:12] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[07:57:12] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[07:57:12] [PASSED] drm_test_connector_hdmi_init_product_valid
[07:57:12] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[07:57:12] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[07:57:12] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[07:57:12] ========= drm_test_connector_hdmi_init_type_valid =========
[07:57:12] [PASSED] HDMI-A
[07:57:12] [PASSED] HDMI-B
[07:57:12] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[07:57:12] ======== drm_test_connector_hdmi_init_type_invalid ========
[07:57:12] [PASSED] Unknown
[07:57:12] [PASSED] VGA
[07:57:12] [PASSED] DVI-I
[07:57:12] [PASSED] DVI-D
[07:57:12] [PASSED] DVI-A
[07:57:12] [PASSED] Composite
[07:57:12] [PASSED] SVIDEO
[07:57:12] [PASSED] LVDS
[07:57:12] [PASSED] Component
[07:57:12] [PASSED] DIN
[07:57:12] [PASSED] DP
[07:57:12] [PASSED] TV
[07:57:12] [PASSED] eDP
[07:57:12] [PASSED] Virtual
[07:57:12] [PASSED] DSI
[07:57:12] [PASSED] DPI
[07:57:12] [PASSED] Writeback
[07:57:12] [PASSED] SPI
[07:57:12] [PASSED] USB
[07:57:12] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[07:57:12] ============ [PASSED] drmm_connector_hdmi_init =============
[07:57:12] ============= drmm_connector_init (3 subtests) =============
[07:57:12] [PASSED] drm_test_drmm_connector_init
[07:57:12] [PASSED] drm_test_drmm_connector_init_null_ddc
[07:57:12] ========= drm_test_drmm_connector_init_type_valid =========
[07:57:12] [PASSED] Unknown
[07:57:12] [PASSED] VGA
[07:57:12] [PASSED] DVI-I
[07:57:12] [PASSED] DVI-D
[07:57:12] [PASSED] DVI-A
[07:57:12] [PASSED] Composite
[07:57:12] [PASSED] SVIDEO
[07:57:12] [PASSED] LVDS
[07:57:12] [PASSED] Component
[07:57:12] [PASSED] DIN
[07:57:12] [PASSED] DP
[07:57:12] [PASSED] HDMI-A
[07:57:12] [PASSED] HDMI-B
[07:57:12] [PASSED] TV
[07:57:12] [PASSED] eDP
[07:57:12] [PASSED] Virtual
[07:57:12] [PASSED] DSI
[07:57:12] [PASSED] DPI
[07:57:12] [PASSED] Writeback
[07:57:12] [PASSED] SPI
[07:57:12] [PASSED] USB
[07:57:12] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[07:57:12] =============== [PASSED] drmm_connector_init ===============
[07:57:12] ========= drm_connector_dynamic_init (6 subtests) ==========
[07:57:12] [PASSED] drm_test_drm_connector_dynamic_init
[07:57:12] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[07:57:12] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[07:57:12] [PASSED] drm_test_drm_connector_dynamic_init_properties
[07:57:12] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[07:57:12] [PASSED] Unknown
[07:57:12] [PASSED] VGA
[07:57:12] [PASSED] DVI-I
[07:57:12] [PASSED] DVI-D
[07:57:12] [PASSED] DVI-A
[07:57:12] [PASSED] Composite
[07:57:12] [PASSED] SVIDEO
[07:57:12] [PASSED] LVDS
[07:57:12] [PASSED] Component
[07:57:12] [PASSED] DIN
[07:57:12] [PASSED] DP
[07:57:12] [PASSED] HDMI-A
[07:57:12] [PASSED] HDMI-B
[07:57:12] [PASSED] TV
[07:57:12] [PASSED] eDP
[07:57:12] [PASSED] Virtual
[07:57:12] [PASSED] DSI
[07:57:12] [PASSED] DPI
[07:57:12] [PASSED] Writeback
[07:57:12] [PASSED] SPI
[07:57:12] [PASSED] USB
[07:57:12] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[07:57:12] ======== drm_test_drm_connector_dynamic_init_name =========
[07:57:12] [PASSED] Unknown
[07:57:12] [PASSED] VGA
[07:57:12] [PASSED] DVI-I
[07:57:12] [PASSED] DVI-D
[07:57:12] [PASSED] DVI-A
[07:57:12] [PASSED] Composite
[07:57:12] [PASSED] SVIDEO
[07:57:12] [PASSED] LVDS
[07:57:12] [PASSED] Component
[07:57:12] [PASSED] DIN
[07:57:12] [PASSED] DP
[07:57:12] [PASSED] HDMI-A
[07:57:12] [PASSED] HDMI-B
[07:57:12] [PASSED] TV
[07:57:12] [PASSED] eDP
[07:57:12] [PASSED] Virtual
[07:57:12] [PASSED] DSI
[07:57:12] [PASSED] DPI
[07:57:12] [PASSED] Writeback
[07:57:12] [PASSED] SPI
[07:57:12] [PASSED] USB
[07:57:12] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[07:57:12] =========== [PASSED] drm_connector_dynamic_init ============
[07:57:12] ==== drm_connector_dynamic_register_early (4 subtests) =====
[07:57:12] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[07:57:12] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[07:57:12] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[07:57:12] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[07:57:12] ====== [PASSED] drm_connector_dynamic_register_early =======
[07:57:12] ======= drm_connector_dynamic_register (7 subtests) ========
[07:57:12] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[07:57:12] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[07:57:12] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[07:57:12] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[07:57:12] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[07:57:12] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[07:57:12] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[07:57:12] ========= [PASSED] drm_connector_dynamic_register ==========
[07:57:12] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[07:57:12] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[07:57:12] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[07:57:12] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[07:57:12] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[07:57:12] ========== drm_test_get_tv_mode_from_name_valid ===========
[07:57:12] [PASSED] NTSC
[07:57:12] [PASSED] NTSC-443
[07:57:12] [PASSED] NTSC-J
[07:57:12] [PASSED] PAL
[07:57:12] [PASSED] PAL-M
[07:57:12] [PASSED] PAL-N
[07:57:12] [PASSED] SECAM
[07:57:12] [PASSED] Mono
[07:57:12] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[07:57:12] [PASSED] drm_test_get_tv_mode_from_name_truncated
[07:57:12] ============ [PASSED] drm_get_tv_mode_from_name ============
[07:57:12] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[07:57:12] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[07:57:12] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[07:57:12] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[07:57:12] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[07:57:12] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[07:57:12] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[07:57:12] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[07:57:12] [PASSED] VIC 96
[07:57:12] [PASSED] VIC 97
[07:57:12] [PASSED] VIC 101
[07:57:12] [PASSED] VIC 102
[07:57:12] [PASSED] VIC 106
[07:57:12] [PASSED] VIC 107
[07:57:12] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[07:57:12] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[07:57:12] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[07:57:12] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[07:57:12] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[07:57:12] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[07:57:12] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[07:57:12] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[07:57:12] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[07:57:12] [PASSED] Automatic
[07:57:12] [PASSED] Full
[07:57:12] [PASSED] Limited 16:235
[07:57:12] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[07:57:12] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[07:57:12] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[07:57:12] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[07:57:12] === drm_test_drm_hdmi_connector_get_output_format_name ====
[07:57:12] [PASSED] RGB
[07:57:12] [PASSED] YUV 4:2:0
[07:57:12] [PASSED] YUV 4:2:2
[07:57:12] [PASSED] YUV 4:4:4
[07:57:12] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[07:57:12] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[07:57:12] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[07:57:12] ============= drm_damage_helper (21 subtests) ==============
[07:57:12] [PASSED] drm_test_damage_iter_no_damage
[07:57:12] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[07:57:12] [PASSED] drm_test_damage_iter_no_damage_src_moved
[07:57:12] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[07:57:12] [PASSED] drm_test_damage_iter_no_damage_not_visible
[07:57:12] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[07:57:12] [PASSED] drm_test_damage_iter_no_damage_no_fb
[07:57:12] [PASSED] drm_test_damage_iter_simple_damage
[07:57:12] [PASSED] drm_test_damage_iter_single_damage
[07:57:12] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[07:57:12] [PASSED] drm_test_damage_iter_single_damage_outside_src
[07:57:12] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[07:57:12] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[07:57:12] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[07:57:12] [PASSED] drm_test_damage_iter_single_damage_src_moved
[07:57:12] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[07:57:12] [PASSED] drm_test_damage_iter_damage
[07:57:12] [PASSED] drm_test_damage_iter_damage_one_intersect
[07:57:12] [PASSED] drm_test_damage_iter_damage_one_outside
[07:57:12] [PASSED] drm_test_damage_iter_damage_src_moved
[07:57:12] [PASSED] drm_test_damage_iter_damage_not_visible
[07:57:12] ================ [PASSED] drm_damage_helper ================
[07:57:12] ============== drm_dp_mst_helper (3 subtests) ==============
[07:57:12] ============== drm_test_dp_mst_calc_pbn_mode ==============
[07:57:12] [PASSED] Clock 154000 BPP 30 DSC disabled
[07:57:12] [PASSED] Clock 234000 BPP 30 DSC disabled
[07:57:12] [PASSED] Clock 297000 BPP 24 DSC disabled
[07:57:12] [PASSED] Clock 332880 BPP 24 DSC enabled
[07:57:12] [PASSED] Clock 324540 BPP 24 DSC enabled
[07:57:12] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[07:57:12] ============== drm_test_dp_mst_calc_pbn_div ===============
[07:57:12] [PASSED] Link rate 2000000 lane count 4
[07:57:12] [PASSED] Link rate 2000000 lane count 2
[07:57:12] [PASSED] Link rate 2000000 lane count 1
[07:57:12] [PASSED] Link rate 1350000 lane count 4
[07:57:12] [PASSED] Link rate 1350000 lane count 2
[07:57:12] [PASSED] Link rate 1350000 lane count 1
[07:57:12] [PASSED] Link rate 1000000 lane count 4
[07:57:12] [PASSED] Link rate 1000000 lane count 2
[07:57:12] [PASSED] Link rate 1000000 lane count 1
[07:57:12] [PASSED] Link rate 810000 lane count 4
[07:57:12] [PASSED] Link rate 810000 lane count 2
[07:57:12] [PASSED] Link rate 810000 lane count 1
[07:57:12] [PASSED] Link rate 540000 lane count 4
[07:57:12] [PASSED] Link rate 540000 lane count 2
[07:57:12] [PASSED] Link rate 540000 lane count 1
[07:57:12] [PASSED] Link rate 270000 lane count 4
[07:57:12] [PASSED] Link rate 270000 lane count 2
[07:57:12] [PASSED] Link rate 270000 lane count 1
[07:57:12] [PASSED] Link rate 162000 lane count 4
[07:57:12] [PASSED] Link rate 162000 lane count 2
[07:57:12] [PASSED] Link rate 162000 lane count 1
[07:57:12] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[07:57:12] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[07:57:12] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[07:57:12] [PASSED] DP_POWER_UP_PHY with port number
[07:57:12] [PASSED] DP_POWER_DOWN_PHY with port number
[07:57:12] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[07:57:12] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[07:57:12] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[07:57:12] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[07:57:12] [PASSED] DP_QUERY_PAYLOAD with port number
[07:57:12] [PASSED] DP_QUERY_PAYLOAD with VCPI
[07:57:12] [PASSED] DP_REMOTE_DPCD_READ with port number
[07:57:12] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[07:57:12] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[07:57:12] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[07:57:12] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[07:57:12] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[07:57:12] [PASSED] DP_REMOTE_I2C_READ with port number
[07:57:12] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[07:57:12] [PASSED] DP_REMOTE_I2C_READ with transactions array
[07:57:12] [PASSED] DP_REMOTE_I2C_WRITE with port number
[07:57:12] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[07:57:12] [PASSED] DP_REMOTE_I2C_WRITE with data array
[07:57:12] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[07:57:12] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[07:57:12] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[07:57:12] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[07:57:12] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[07:57:12] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[07:57:12] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[07:57:12] ================ [PASSED] drm_dp_mst_helper ================
[07:57:12] ================== drm_exec (7 subtests) ===================
[07:57:12] [PASSED] sanitycheck
[07:57:12] [PASSED] test_lock
[07:57:12] [PASSED] test_lock_unlock
[07:57:12] [PASSED] test_duplicates
[07:57:12] [PASSED] test_prepare
[07:57:12] [PASSED] test_prepare_array
[07:57:12] [PASSED] test_multiple_loops
[07:57:12] ==================== [PASSED] drm_exec =====================
[07:57:12] =========== drm_format_helper_test (17 subtests) ===========
[07:57:12] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[07:57:12] [PASSED] single_pixel_source_buffer
[07:57:12] [PASSED] single_pixel_clip_rectangle
[07:57:12] [PASSED] well_known_colors
[07:57:12] [PASSED] destination_pitch
[07:57:12] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[07:57:12] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[07:57:12] [PASSED] single_pixel_source_buffer
[07:57:12] [PASSED] single_pixel_clip_rectangle
[07:57:12] [PASSED] well_known_colors
[07:57:12] [PASSED] destination_pitch
[07:57:12] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[07:57:12] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[07:57:12] [PASSED] single_pixel_source_buffer
[07:57:12] [PASSED] single_pixel_clip_rectangle
[07:57:12] [PASSED] well_known_colors
[07:57:12] [PASSED] destination_pitch
[07:57:12] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[07:57:12] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[07:57:12] [PASSED] single_pixel_source_buffer
[07:57:12] [PASSED] single_pixel_clip_rectangle
[07:57:12] [PASSED] well_known_colors
[07:57:12] [PASSED] destination_pitch
[07:57:12] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[07:57:12] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[07:57:12] [PASSED] single_pixel_source_buffer
[07:57:12] [PASSED] single_pixel_clip_rectangle
[07:57:12] [PASSED] well_known_colors
[07:57:12] [PASSED] destination_pitch
[07:57:12] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[07:57:12] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[07:57:12] [PASSED] single_pixel_source_buffer
[07:57:12] [PASSED] single_pixel_clip_rectangle
[07:57:12] [PASSED] well_known_colors
[07:57:12] [PASSED] destination_pitch
[07:57:12] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[07:57:12] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[07:57:12] [PASSED] single_pixel_source_buffer
[07:57:12] [PASSED] single_pixel_clip_rectangle
[07:57:12] [PASSED] well_known_colors
[07:57:12] [PASSED] destination_pitch
[07:57:12] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[07:57:12] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[07:57:12] [PASSED] single_pixel_source_buffer
[07:57:12] [PASSED] single_pixel_clip_rectangle
[07:57:12] [PASSED] well_known_colors
[07:57:12] [PASSED] destination_pitch
[07:57:12] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[07:57:12] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[07:57:12] [PASSED] single_pixel_source_buffer
[07:57:12] [PASSED] single_pixel_clip_rectangle
[07:57:12] [PASSED] well_known_colors
[07:57:12] [PASSED] destination_pitch
[07:57:12] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[07:57:12] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[07:57:12] [PASSED] single_pixel_source_buffer
[07:57:12] [PASSED] single_pixel_clip_rectangle
[07:57:12] [PASSED] well_known_colors
[07:57:12] [PASSED] destination_pitch
[07:57:12] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[07:57:12] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[07:57:12] [PASSED] single_pixel_source_buffer
[07:57:12] [PASSED] single_pixel_clip_rectangle
[07:57:12] [PASSED] well_known_colors
[07:57:12] [PASSED] destination_pitch
[07:57:12] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[07:57:12] ============== drm_test_fb_xrgb8888_to_mono ===============
[07:57:12] [PASSED] single_pixel_source_buffer
[07:57:12] [PASSED] single_pixel_clip_rectangle
[07:57:12] [PASSED] well_known_colors
[07:57:12] [PASSED] destination_pitch
[07:57:12] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[07:57:12] ==================== drm_test_fb_swab =====================
[07:57:12] [PASSED] single_pixel_source_buffer
[07:57:12] [PASSED] single_pixel_clip_rectangle
[07:57:12] [PASSED] well_known_colors
[07:57:12] [PASSED] destination_pitch
[07:57:12] ================ [PASSED] drm_test_fb_swab =================
[07:57:12] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[07:57:12] [PASSED] single_pixel_source_buffer
[07:57:12] [PASSED] single_pixel_clip_rectangle
[07:57:12] [PASSED] well_known_colors
[07:57:12] [PASSED] destination_pitch
[07:57:12] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[07:57:12] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[07:57:12] [PASSED] single_pixel_source_buffer
[07:57:12] [PASSED] single_pixel_clip_rectangle
[07:57:12] [PASSED] well_known_colors
[07:57:12] [PASSED] destination_pitch
[07:57:12] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[07:57:12] ================= drm_test_fb_clip_offset =================
[07:57:12] [PASSED] pass through
[07:57:12] [PASSED] horizontal offset
[07:57:12] [PASSED] vertical offset
[07:57:12] [PASSED] horizontal and vertical offset
[07:57:12] [PASSED] horizontal offset (custom pitch)
[07:57:12] [PASSED] vertical offset (custom pitch)
[07:57:12] [PASSED] horizontal and vertical offset (custom pitch)
[07:57:12] ============= [PASSED] drm_test_fb_clip_offset =============
[07:57:12] =================== drm_test_fb_memcpy ====================
[07:57:12] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[07:57:12] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[07:57:12] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[07:57:12] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[07:57:12] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[07:57:12] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[07:57:12] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[07:57:12] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[07:57:12] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[07:57:12] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[07:57:12] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[07:57:12] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[07:57:12] =============== [PASSED] drm_test_fb_memcpy ================
[07:57:12] ============= [PASSED] drm_format_helper_test ==============
[07:57:12] ================= drm_format (18 subtests) =================
[07:57:12] [PASSED] drm_test_format_block_width_invalid
[07:57:12] [PASSED] drm_test_format_block_width_one_plane
[07:57:12] [PASSED] drm_test_format_block_width_two_plane
[07:57:12] [PASSED] drm_test_format_block_width_three_plane
[07:57:12] [PASSED] drm_test_format_block_width_tiled
[07:57:12] [PASSED] drm_test_format_block_height_invalid
[07:57:12] [PASSED] drm_test_format_block_height_one_plane
[07:57:12] [PASSED] drm_test_format_block_height_two_plane
[07:57:12] [PASSED] drm_test_format_block_height_three_plane
[07:57:12] [PASSED] drm_test_format_block_height_tiled
[07:57:12] [PASSED] drm_test_format_min_pitch_invalid
[07:57:12] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[07:57:12] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[07:57:12] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[07:57:12] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[07:57:12] [PASSED] drm_test_format_min_pitch_two_plane
[07:57:12] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[07:57:12] [PASSED] drm_test_format_min_pitch_tiled
[07:57:12] =================== [PASSED] drm_format ====================
[07:57:12] ============== drm_framebuffer (10 subtests) ===============
[07:57:12] ========== drm_test_framebuffer_check_src_coords ==========
[07:57:12] [PASSED] Success: source fits into fb
[07:57:12] [PASSED] Fail: overflowing fb with x-axis coordinate
[07:57:12] [PASSED] Fail: overflowing fb with y-axis coordinate
[07:57:12] [PASSED] Fail: overflowing fb with source width
[07:57:12] [PASSED] Fail: overflowing fb with source height
[07:57:12] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[07:57:12] [PASSED] drm_test_framebuffer_cleanup
[07:57:12] =============== drm_test_framebuffer_create ===============
[07:57:12] [PASSED] ABGR8888 normal sizes
[07:57:12] [PASSED] ABGR8888 max sizes
[07:57:12] [PASSED] ABGR8888 pitch greater than min required
[07:57:12] [PASSED] ABGR8888 pitch less than min required
[07:57:12] [PASSED] ABGR8888 Invalid width
[07:57:12] [PASSED] ABGR8888 Invalid buffer handle
[07:57:12] [PASSED] No pixel format
[07:57:12] [PASSED] ABGR8888 Width 0
[07:57:12] [PASSED] ABGR8888 Height 0
[07:57:12] [PASSED] ABGR8888 Out of bound height * pitch combination
[07:57:12] [PASSED] ABGR8888 Large buffer offset
[07:57:12] [PASSED] ABGR8888 Buffer offset for inexistent plane
[07:57:12] [PASSED] ABGR8888 Invalid flag
[07:57:12] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[07:57:12] [PASSED] ABGR8888 Valid buffer modifier
[07:57:12] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[07:57:12] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[07:57:12] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[07:57:12] [PASSED] NV12 Normal sizes
[07:57:12] [PASSED] NV12 Max sizes
[07:57:12] [PASSED] NV12 Invalid pitch
[07:57:12] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[07:57:12] [PASSED] NV12 different modifier per-plane
[07:57:12] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[07:57:12] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[07:57:12] [PASSED] NV12 Modifier for inexistent plane
[07:57:12] [PASSED] NV12 Handle for inexistent plane
[07:57:12] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[07:57:12] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[07:57:12] [PASSED] YVU420 Normal sizes
[07:57:12] [PASSED] YVU420 Max sizes
[07:57:12] [PASSED] YVU420 Invalid pitch
[07:57:12] [PASSED] YVU420 Different pitches
[07:57:12] [PASSED] YVU420 Different buffer offsets/pitches
[07:57:12] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[07:57:12] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[07:57:12] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[07:57:12] [PASSED] YVU420 Valid modifier
[07:57:12] [PASSED] YVU420 Different modifiers per plane
[07:57:12] [PASSED] YVU420 Modifier for inexistent plane
[07:57:12] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[07:57:12] [PASSED] X0L2 Normal sizes
[07:57:12] [PASSED] X0L2 Max sizes
[07:57:12] [PASSED] X0L2 Invalid pitch
[07:57:12] [PASSED] X0L2 Pitch greater than minimum required
[07:57:12] [PASSED] X0L2 Handle for inexistent plane
[07:57:12] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[07:57:12] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[07:57:12] [PASSED] X0L2 Valid modifier
[07:57:12] [PASSED] X0L2 Modifier for inexistent plane
[07:57:12] =========== [PASSED] drm_test_framebuffer_create ===========
[07:57:12] [PASSED] drm_test_framebuffer_free
[07:57:12] [PASSED] drm_test_framebuffer_init
[07:57:12] [PASSED] drm_test_framebuffer_init_bad_format
[07:57:12] [PASSED] drm_test_framebuffer_init_dev_mismatch
[07:57:12] [PASSED] drm_test_framebuffer_lookup
[07:57:12] [PASSED] drm_test_framebuffer_lookup_inexistent
[07:57:12] [PASSED] drm_test_framebuffer_modifiers_not_supported
[07:57:12] ================= [PASSED] drm_framebuffer =================
[07:57:12] ================ drm_gem_shmem (8 subtests) ================
[07:57:12] [PASSED] drm_gem_shmem_test_obj_create
[07:57:12] [PASSED] drm_gem_shmem_test_obj_create_private
[07:57:12] [PASSED] drm_gem_shmem_test_pin_pages
[07:57:12] [PASSED] drm_gem_shmem_test_vmap
[07:57:12] [PASSED] drm_gem_shmem_test_get_sg_table
[07:57:12] [PASSED] drm_gem_shmem_test_get_pages_sgt
[07:57:12] [PASSED] drm_gem_shmem_test_madvise
[07:57:12] [PASSED] drm_gem_shmem_test_purge
[07:57:12] ================== [PASSED] drm_gem_shmem ==================
[07:57:12] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[07:57:12] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[07:57:12] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[07:57:12] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[07:57:12] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[07:57:12] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[07:57:12] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[07:57:12] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[07:57:12] [PASSED] Automatic
[07:57:12] [PASSED] Full
[07:57:12] [PASSED] Limited 16:235
[07:57:12] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[07:57:12] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[07:57:12] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[07:57:12] [PASSED] drm_test_check_disable_connector
[07:57:12] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[07:57:12] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[07:57:12] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[07:57:12] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[07:57:12] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[07:57:12] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[07:57:12] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[07:57:12] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[07:57:12] [PASSED] drm_test_check_output_bpc_dvi
[07:57:12] [PASSED] drm_test_check_output_bpc_format_vic_1
[07:57:12] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[07:57:12] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[07:57:12] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[07:57:12] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[07:57:12] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[07:57:12] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[07:57:12] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[07:57:12] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[07:57:12] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[07:57:12] [PASSED] drm_test_check_broadcast_rgb_value
[07:57:12] [PASSED] drm_test_check_bpc_8_value
[07:57:12] [PASSED] drm_test_check_bpc_10_value
[07:57:12] [PASSED] drm_test_check_bpc_12_value
[07:57:12] [PASSED] drm_test_check_format_value
[07:57:12] [PASSED] drm_test_check_tmds_char_value
[07:57:12] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[07:57:12] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[07:57:12] [PASSED] drm_test_check_mode_valid
[07:57:12] [PASSED] drm_test_check_mode_valid_reject
[07:57:12] [PASSED] drm_test_check_mode_valid_reject_rate
[07:57:12] [PASSED] drm_test_check_mode_valid_reject_max_clock
[07:57:12] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[07:57:12] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[07:57:12] [PASSED] drm_test_check_infoframes
[07:57:12] [PASSED] drm_test_check_reject_avi_infoframe
[07:57:12] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[07:57:12] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[07:57:12] [PASSED] drm_test_check_reject_audio_infoframe
[07:57:12] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[07:57:12] ================= drm_managed (2 subtests) =================
[07:57:12] [PASSED] drm_test_managed_release_action
[07:57:12] [PASSED] drm_test_managed_run_action
[07:57:12] =================== [PASSED] drm_managed ===================
[07:57:12] =================== drm_mm (6 subtests) ====================
[07:57:12] [PASSED] drm_test_mm_init
[07:57:12] [PASSED] drm_test_mm_debug
[07:57:12] [PASSED] drm_test_mm_align32
[07:57:12] [PASSED] drm_test_mm_align64
[07:57:12] [PASSED] drm_test_mm_lowest
[07:57:12] [PASSED] drm_test_mm_highest
[07:57:12] ===================== [PASSED] drm_mm ======================
[07:57:12] ============= drm_modes_analog_tv (5 subtests) =============
[07:57:12] [PASSED] drm_test_modes_analog_tv_mono_576i
[07:57:12] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[07:57:12] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[07:57:12] [PASSED] drm_test_modes_analog_tv_pal_576i
[07:57:12] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[07:57:12] =============== [PASSED] drm_modes_analog_tv ===============
[07:57:12] ============== drm_plane_helper (2 subtests) ===============
[07:57:12] =============== drm_test_check_plane_state ================
[07:57:12] [PASSED] clipping_simple
[07:57:12] [PASSED] clipping_rotate_reflect
[07:57:12] [PASSED] positioning_simple
[07:57:12] [PASSED] upscaling
[07:57:12] [PASSED] downscaling
[07:57:12] [PASSED] rounding1
[07:57:12] [PASSED] rounding2
[07:57:12] [PASSED] rounding3
[07:57:12] [PASSED] rounding4
[07:57:12] =========== [PASSED] drm_test_check_plane_state ============
[07:57:12] =========== drm_test_check_invalid_plane_state ============
[07:57:12] [PASSED] positioning_invalid
[07:57:12] [PASSED] upscaling_invalid
[07:57:12] [PASSED] downscaling_invalid
[07:57:12] ======= [PASSED] drm_test_check_invalid_plane_state ========
[07:57:12] ================ [PASSED] drm_plane_helper =================
[07:57:12] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[07:57:12] ====== drm_test_connector_helper_tv_get_modes_check =======
[07:57:12] [PASSED] None
[07:57:12] [PASSED] PAL
[07:57:12] [PASSED] NTSC
[07:57:12] [PASSED] Both, NTSC Default
[07:57:12] [PASSED] Both, PAL Default
[07:57:12] [PASSED] Both, NTSC Default, with PAL on command-line
[07:57:12] [PASSED] Both, PAL Default, with NTSC on command-line
[07:57:12] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[07:57:12] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[07:57:12] ================== drm_rect (9 subtests) ===================
[07:57:12] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[07:57:12] [PASSED] drm_test_rect_clip_scaled_not_clipped
[07:57:12] [PASSED] drm_test_rect_clip_scaled_clipped
[07:57:12] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[07:57:12] ================= drm_test_rect_intersect =================
[07:57:12] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[07:57:12] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[07:57:12] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[07:57:12] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[07:57:12] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[07:57:12] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[07:57:12] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[07:57:12] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[07:57:12] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[07:57:12] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[07:57:12] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[07:57:12] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[07:57:12] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[07:57:12] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[07:57:12] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[07:57:12] ============= [PASSED] drm_test_rect_intersect =============
[07:57:12] ================ drm_test_rect_calc_hscale ================
[07:57:12] [PASSED] normal use
[07:57:12] [PASSED] out of max range
[07:57:12] [PASSED] out of min range
[07:57:12] [PASSED] zero dst
[07:57:12] [PASSED] negative src
[07:57:12] [PASSED] negative dst
[07:57:12] ============ [PASSED] drm_test_rect_calc_hscale ============
[07:57:12] ================ drm_test_rect_calc_vscale ================
[07:57:12] [PASSED] normal use
[07:57:12] [PASSED] out of max range
[07:57:12] [PASSED] out of min range
[07:57:12] [PASSED] zero dst
[07:57:12] [PASSED] negative src
[07:57:12] [PASSED] negative dst
[07:57:12] ============ [PASSED] drm_test_rect_calc_vscale ============
[07:57:12] ================== drm_test_rect_rotate ===================
[07:57:12] [PASSED] reflect-x
[07:57:12] [PASSED] reflect-y
[07:57:12] [PASSED] rotate-0
[07:57:12] [PASSED] rotate-90
[07:57:12] [PASSED] rotate-180
[07:57:12] [PASSED] rotate-270
[07:57:12] ============== [PASSED] drm_test_rect_rotate ===============
[07:57:12] ================ drm_test_rect_rotate_inv =================
[07:57:12] [PASSED] reflect-x
[07:57:12] [PASSED] reflect-y
[07:57:12] [PASSED] rotate-0
[07:57:12] [PASSED] rotate-90
[07:57:12] [PASSED] rotate-180
[07:57:12] [PASSED] rotate-270
[07:57:12] ============ [PASSED] drm_test_rect_rotate_inv =============
[07:57:12] ==================== [PASSED] drm_rect =====================
[07:57:12] ============ drm_sysfb_modeset_test (1 subtest) ============
[07:57:12] ============ drm_test_sysfb_build_fourcc_list =============
[07:57:12] [PASSED] no native formats
[07:57:12] [PASSED] XRGB8888 as native format
[07:57:12] [PASSED] remove duplicates
[07:57:12] [PASSED] convert alpha formats
[07:57:12] [PASSED] random formats
[07:57:12] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[07:57:12] ============= [PASSED] drm_sysfb_modeset_test ==============
[07:57:12] ================== drm_fixp (2 subtests) ===================
[07:57:12] [PASSED] drm_test_int2fixp
[07:57:12] [PASSED] drm_test_sm2fixp
[07:57:12] ==================== [PASSED] drm_fixp =====================
[07:57:12] ============================================================
[07:57:12] Testing complete. Ran 621 tests: passed: 621
[07:57:12] Elapsed time: 26.197s total, 1.761s configuring, 24.218s building, 0.183s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[07:57:12] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[07:57:14] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[07:57:23] Starting KUnit Kernel (1/1)...
[07:57:23] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[07:57:23] ================= ttm_device (5 subtests) ==================
[07:57:23] [PASSED] ttm_device_init_basic
[07:57:23] [PASSED] ttm_device_init_multiple
[07:57:23] [PASSED] ttm_device_fini_basic
[07:57:23] [PASSED] ttm_device_init_no_vma_man
[07:57:23] ================== ttm_device_init_pools ==================
[07:57:23] [PASSED] No DMA allocations, no DMA32 required
[07:57:23] [PASSED] DMA allocations, DMA32 required
[07:57:23] [PASSED] No DMA allocations, DMA32 required
[07:57:23] [PASSED] DMA allocations, no DMA32 required
[07:57:23] ============== [PASSED] ttm_device_init_pools ==============
[07:57:23] =================== [PASSED] ttm_device ====================
[07:57:23] ================== ttm_pool (8 subtests) ===================
[07:57:23] ================== ttm_pool_alloc_basic ===================
[07:57:23] [PASSED] One page
[07:57:23] [PASSED] More than one page
[07:57:23] [PASSED] Above the allocation limit
[07:57:23] [PASSED] One page, with coherent DMA mappings enabled
[07:57:23] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[07:57:23] ============== [PASSED] ttm_pool_alloc_basic ===============
[07:57:23] ============== ttm_pool_alloc_basic_dma_addr ==============
[07:57:23] [PASSED] One page
[07:57:23] [PASSED] More than one page
[07:57:23] [PASSED] Above the allocation limit
[07:57:23] [PASSED] One page, with coherent DMA mappings enabled
[07:57:23] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[07:57:23] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[07:57:23] [PASSED] ttm_pool_alloc_order_caching_match
[07:57:23] [PASSED] ttm_pool_alloc_caching_mismatch
[07:57:23] [PASSED] ttm_pool_alloc_order_mismatch
[07:57:23] [PASSED] ttm_pool_free_dma_alloc
[07:57:23] [PASSED] ttm_pool_free_no_dma_alloc
[07:57:23] [PASSED] ttm_pool_fini_basic
[07:57:23] ==================== [PASSED] ttm_pool =====================
[07:57:23] ================ ttm_resource (8 subtests) =================
[07:57:23] ================= ttm_resource_init_basic =================
[07:57:23] [PASSED] Init resource in TTM_PL_SYSTEM
[07:57:23] [PASSED] Init resource in TTM_PL_VRAM
[07:57:23] [PASSED] Init resource in a private placement
[07:57:23] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[07:57:23] ============= [PASSED] ttm_resource_init_basic =============
[07:57:23] [PASSED] ttm_resource_init_pinned
[07:57:23] [PASSED] ttm_resource_fini_basic
[07:57:23] [PASSED] ttm_resource_manager_init_basic
[07:57:23] [PASSED] ttm_resource_manager_usage_basic
[07:57:23] [PASSED] ttm_resource_manager_set_used_basic
[07:57:23] [PASSED] ttm_sys_man_alloc_basic
[07:57:23] [PASSED] ttm_sys_man_free_basic
[07:57:23] ================== [PASSED] ttm_resource ===================
[07:57:23] =================== ttm_tt (15 subtests) ===================
[07:57:23] ==================== ttm_tt_init_basic ====================
[07:57:23] [PASSED] Page-aligned size
[07:57:23] [PASSED] Extra pages requested
[07:57:23] ================ [PASSED] ttm_tt_init_basic ================
[07:57:23] [PASSED] ttm_tt_init_misaligned
[07:57:23] [PASSED] ttm_tt_fini_basic
[07:57:23] [PASSED] ttm_tt_fini_sg
[07:57:23] [PASSED] ttm_tt_fini_shmem
[07:57:23] [PASSED] ttm_tt_create_basic
[07:57:23] [PASSED] ttm_tt_create_invalid_bo_type
[07:57:23] [PASSED] ttm_tt_create_ttm_exists
[07:57:23] [PASSED] ttm_tt_create_failed
[07:57:23] [PASSED] ttm_tt_destroy_basic
[07:57:23] [PASSED] ttm_tt_populate_null_ttm
[07:57:23] [PASSED] ttm_tt_populate_populated_ttm
[07:57:23] [PASSED] ttm_tt_unpopulate_basic
[07:57:23] [PASSED] ttm_tt_unpopulate_empty_ttm
[07:57:23] [PASSED] ttm_tt_swapin_basic
[07:57:23] ===================== [PASSED] ttm_tt ======================
[07:57:23] =================== ttm_bo (14 subtests) ===================
[07:57:23] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[07:57:23] [PASSED] Cannot be interrupted and sleeps
[07:57:23] [PASSED] Cannot be interrupted, locks straight away
[07:57:23] [PASSED] Can be interrupted, sleeps
[07:57:23] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[07:57:23] [PASSED] ttm_bo_reserve_locked_no_sleep
[07:57:23] [PASSED] ttm_bo_reserve_no_wait_ticket
[07:57:23] [PASSED] ttm_bo_reserve_double_resv
[07:57:23] [PASSED] ttm_bo_reserve_interrupted
[07:57:23] [PASSED] ttm_bo_reserve_deadlock
[07:57:23] [PASSED] ttm_bo_unreserve_basic
[07:57:23] [PASSED] ttm_bo_unreserve_pinned
[07:57:23] [PASSED] ttm_bo_unreserve_bulk
[07:57:23] [PASSED] ttm_bo_fini_basic
[07:57:23] [PASSED] ttm_bo_fini_shared_resv
[07:57:23] [PASSED] ttm_bo_pin_basic
[07:57:23] [PASSED] ttm_bo_pin_unpin_resource
[07:57:23] [PASSED] ttm_bo_multiple_pin_one_unpin
[07:57:23] ===================== [PASSED] ttm_bo ======================
[07:57:23] ============== ttm_bo_validate (22 subtests) ===============
[07:57:23] ============== ttm_bo_init_reserved_sys_man ===============
[07:57:23] [PASSED] Buffer object for userspace
[07:57:23] [PASSED] Kernel buffer object
[07:57:23] [PASSED] Shared buffer object
[07:57:23] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[07:57:23] ============== ttm_bo_init_reserved_mock_man ==============
[07:57:23] [PASSED] Buffer object for userspace
[07:57:23] [PASSED] Kernel buffer object
[07:57:23] [PASSED] Shared buffer object
[07:57:23] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[07:57:23] [PASSED] ttm_bo_init_reserved_resv
[07:57:23] ================== ttm_bo_validate_basic ==================
[07:57:23] [PASSED] Buffer object for userspace
[07:57:23] [PASSED] Kernel buffer object
[07:57:23] [PASSED] Shared buffer object
[07:57:23] ============== [PASSED] ttm_bo_validate_basic ==============
[07:57:23] [PASSED] ttm_bo_validate_invalid_placement
[07:57:23] ============= ttm_bo_validate_same_placement ==============
[07:57:23] [PASSED] System manager
[07:57:23] [PASSED] VRAM manager
[07:57:23] ========= [PASSED] ttm_bo_validate_same_placement ==========
[07:57:23] [PASSED] ttm_bo_validate_failed_alloc
[07:57:23] [PASSED] ttm_bo_validate_pinned
[07:57:23] [PASSED] ttm_bo_validate_busy_placement
[07:57:23] ================ ttm_bo_validate_multihop =================
[07:57:23] [PASSED] Buffer object for userspace
[07:57:23] [PASSED] Kernel buffer object
[07:57:23] [PASSED] Shared buffer object
[07:57:23] ============ [PASSED] ttm_bo_validate_multihop =============
[07:57:23] ========== ttm_bo_validate_no_placement_signaled ==========
[07:57:23] [PASSED] Buffer object in system domain, no page vector
[07:57:23] [PASSED] Buffer object in system domain with an existing page vector
[07:57:23] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[07:57:23] ======== ttm_bo_validate_no_placement_not_signaled ========
[07:57:23] [PASSED] Buffer object for userspace
[07:57:23] [PASSED] Kernel buffer object
[07:57:23] [PASSED] Shared buffer object
[07:57:23] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[07:57:23] [PASSED] ttm_bo_validate_move_fence_signaled
[07:57:23] ========= ttm_bo_validate_move_fence_not_signaled =========
[07:57:23] [PASSED] Waits for GPU
[07:57:23] [PASSED] Tries to lock straight away
[07:57:23] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[07:57:23] [PASSED] ttm_bo_validate_swapout
[07:57:23] [PASSED] ttm_bo_validate_happy_evict
[07:57:23] [PASSED] ttm_bo_validate_all_pinned_evict
[07:57:23] [PASSED] ttm_bo_validate_allowed_only_evict
[07:57:23] [PASSED] ttm_bo_validate_deleted_evict
[07:57:23] [PASSED] ttm_bo_validate_busy_domain_evict
[07:57:23] [PASSED] ttm_bo_validate_evict_gutting
[07:57:23] [PASSED] ttm_bo_validate_recrusive_evict
[07:57:23] ================= [PASSED] ttm_bo_validate =================
[07:57:23] ============================================================
[07:57:23] Testing complete. Ran 102 tests: passed: 102
[07:57:23] Elapsed time: 11.366s total, 1.722s configuring, 9.429s building, 0.185s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 7+ messages in thread
* ✓ Xe.CI.BAT: success for drm/i915/psr: Refactor and extend SCL handling for VRRTG
2026-05-15 7:36 [PATCH 0/2] drm/i915/psr: Refactor and extend SCL handling for VRRTG Ankit Nautiyal
` (3 preceding siblings ...)
2026-05-15 7:57 ` ✓ CI.KUnit: success " Patchwork
@ 2026-05-15 8:35 ` Patchwork
4 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2026-05-15 8:35 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 879 bytes --]
== Series Details ==
Series: drm/i915/psr: Refactor and extend SCL handling for VRRTG
URL : https://patchwork.freedesktop.org/series/166628/
State : success
== Summary ==
CI Bug Log - changes from xe-5067-b9819223b7e92173091b674c2212252b99ea6c4b_BAT -> xe-pw-166628v1_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (13 -> 13)
------------------------------
No changes in participating hosts
Changes
-------
No changes found
Build changes
-------------
* Linux: xe-5067-b9819223b7e92173091b674c2212252b99ea6c4b -> xe-pw-166628v1
IGT_8914: 8914
xe-5067-b9819223b7e92173091b674c2212252b99ea6c4b: b9819223b7e92173091b674c2212252b99ea6c4b
xe-pw-166628v1: 166628v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166628v1/index.html
[-- Attachment #2: Type: text/html, Size: 1427 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] drm/i915/psr: Simplify the conditions for SCL computation
2026-05-15 7:36 ` [PATCH 1/2] drm/i915/psr: Simplify the conditions for SCL computation Ankit Nautiyal
@ 2026-05-15 10:30 ` Jani Nikula
0 siblings, 0 replies; 7+ messages in thread
From: Jani Nikula @ 2026-05-15 10:30 UTC (permalink / raw)
To: Ankit Nautiyal, intel-gfx, intel-xe; +Cc: jouni.hogander, Ankit Nautiyal
On Fri, 15 May 2026, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
> The SCL condition checks can be combined into one expression.
> needs_sel_update is common for both display version branches, so check it
> once and keep the version specific checks together.
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 13 +++++--------
> 1 file changed, 5 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 8f70b7dcd881..5bf1d782188c 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1477,15 +1477,12 @@ int _intel_psr_min_set_context_latency(const struct intel_crtc_state *crtc_state
> * SRD_STATUS is used by PSR1 and Panel Replay DP on LunarLake.
> */
>
> - if (DISPLAY_VER(display) >= 30 && (needs_panel_replay ||
> - needs_sel_update))
> + if (needs_sel_update ||
> + (DISPLAY_VER(display) >= 30 && needs_panel_replay) ||
> + (DISPLAY_VER(display) < 30 && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)))
> return 0;
> - else if (DISPLAY_VER(display) < 30 && (needs_sel_update ||
> - intel_crtc_has_type(crtc_state,
> - INTEL_OUTPUT_EDP)))
> - return 0;
> - else
> - return 1;
The function has a bunch of simple "if foo return bar" statements.
Please don't combine more stuff together, but rather split them up.
if (needs_sel_update)
return 0;
if (DISPLAY_VER(display) < 30 && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
return 0;
if (DISPLAY_VER(display) >= 30 && needs_panel_reply)
return 0;
Please consider which one is easier and faster to read and understand.
BR,
Jani.
> +
> + return 1;
> }
>
> static bool _wake_lines_fit_into_vblank(const struct intel_crtc_state *crtc_state,
--
Jani Nikula, Intel
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2026-05-15 7:36 [PATCH 0/2] drm/i915/psr: Refactor and extend SCL handling for VRRTG Ankit Nautiyal
2026-05-15 7:36 ` [PATCH 1/2] drm/i915/psr: Simplify the conditions for SCL computation Ankit Nautiyal
2026-05-15 10:30 ` Jani Nikula
2026-05-15 7:36 ` [PATCH 2/2] drm/i915/psr: Allow SCL=0 on platforms with always-on VRR TG Ankit Nautiyal
2026-05-15 7:56 ` ✗ CI.checkpatch: warning for drm/i915/psr: Refactor and extend SCL handling for VRRTG Patchwork
2026-05-15 7:57 ` ✓ CI.KUnit: success " Patchwork
2026-05-15 8:35 ` ✓ Xe.CI.BAT: " Patchwork
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