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From: "Nautiyal, Ankit K" <ankit.k.nautiyal@intel.com>
To: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>,
	<intel-gfx@lists.freedesktop.org>
Cc: <intel-xe@lists.freedesktop.org>, <ville.syrjala@linux.intel.com>
Subject: Re: [PATCH v8 07/18] drm/i915/vrr: Add compute config for DC Balance params
Date: Wed, 26 Nov 2025 13:00:54 +0530	[thread overview]
Message-ID: <613e3982-9dc1-40be-ae08-4ba62d78b5e0@intel.com> (raw)
In-Reply-To: <cb8a8373-19af-4749-9638-ccee5620c61c@intel.com>


On 11/26/2025 9:39 AM, Nautiyal, Ankit K wrote:
>
> On 11/17/2025 11:14 AM, Mitul Golani wrote:
>> Compute DC Balance parameters and tunable params based on
>> experiments.
>>
>> --v2:
>> - Document tunable params. (Ankit)
>>
>> --v3:
>> - Add line spaces to compute config. (Ankit)
>> - Remove redundancy checks.
>>
>> --v4:
>> - Separate out conpute config to separate function.
>> - As all the valuse are being computed in scanlines, and slope
>> is still in usec, convert and store it to scanlines.
>>
>> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_vrr.c | 38 ++++++++++++++++++++++++
>>   1 file changed, 38 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c 
>> b/drivers/gpu/drm/i915/display/intel_vrr.c
>> index 650077eb280f..7cb484dd96df 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
>> @@ -6,6 +6,7 @@
>>     #include <drm/drm_print.h>
>>   +#include "intel_crtc.h"
>>   #include "intel_de.h"
>>   #include "intel_display_regs.h"
>>   #include "intel_display_types.h"
>> @@ -20,6 +21,14 @@
>>   #define FIXED_POINT_PRECISION        100
>>   #define CMRR_PRECISION_TOLERANCE    10
>>   +/*
>> + * Tunable parameters for DC Balance correction.
>> + * These are captured based on experimentations.
>> + */
>> +#define DCB_CORRECTION_SENSITIVITY    30
>> +#define DCB_CORRECTION_AGGRESSIVENESS    1000
>
>
> As mentioned in comment in last version, we can just have this value 
> as 1000 * 10 instead of multiplying 10 where we are using this macro.
>
> This is a bit unclear to me. More about this below.
>
>
>> +#define DCB_BLANK_TARGET        50
>> +
>>   bool intel_vrr_is_capable(struct intel_connector *connector)
>>   {
>>       struct intel_display *display = to_intel_display(connector);
>> @@ -342,6 +351,33 @@ int intel_vrr_compute_vmax(struct 
>> intel_connector *connector,
>>       return vmax;
>>   }
>>   +static void
>> +intel_vrr_dc_balance_compute_config(struct intel_crtc_state 
>> *crtc_state)
>> +{
>> +    int val;
>> +    struct drm_display_mode *adjusted_mode = 
>> &crtc_state->hw.adjusted_mode;
>> +
>> +    if (!crtc_state->vrr.dc_balance.enable)
>> +        return;
>
> Here check should be for crtc_state->vrr.enable, and 
> HAS_VRR_DC_BALANCE(display) and return early if these are not true.
> I think this vrr.dc_balance.enable should be set in this function, 
> perhaps not in this patch, but in the last patch.
> Currently its set in intel_vrr_compute_vrr_timings() in #patch17.
>
>
>
>> +
>> +    crtc_state->vrr.dc_balance.vmax = crtc_state->vrr.vmax;
>> +    crtc_state->vrr.dc_balance.vmin = crtc_state->vrr.vmin;
>> +    crtc_state->vrr.dc_balance.max_increase =
>> +        crtc_state->vrr.vmax - crtc_state->vrr.vmin;
>> +    crtc_state->vrr.dc_balance.max_decrease =
>> +        crtc_state->vrr.vmax - crtc_state->vrr.vmin;
>
>> + crtc_state->vrr.dc_balance.guardband =
>> +        DIV_ROUND_UP(crtc_state->vrr.dc_balance.vmax *
>> +                 DCB_CORRECTION_SENSITIVITY, 100);
>> +    val = DIV_ROUND_UP(DCB_CORRECTION_AGGRESSIVENESS * 10,
>> +               crtc_state->vrr.dc_balance.guardband);
>> +    crtc_state->vrr.dc_balance.slope =
>> +        intel_usecs_to_scanlines(adjusted_mode, val);
>
>
> This needs to be written with more clarity.
>
> Perhaps need some comments to explain what is happening.
>
> DCB_CORRECTION_AGGRESSIVENESS is the number of millisecs to adjust 
> when balance is twice the guardband, as per our settings we perhaps 
> want 10msec.
>
> Slope is the ratio between Agressiveness msecs : Guardband msecs.
> We can use ratio of agressiveness usecs : guardband usecs.
>
> Currently guardband is in lines, (30% of vmax lines to be precise)
>
> guardband_usecs = intel_usecs_to_scanlines(adjusted_mode, 
> crtc_state->vrr.dc_balance.guardband);


(face palm).. I meant:

guardband_usecs = intel_scanlines_to_usecs(adjusted_mode-> 
crtc_state->vrr.dc_balance.guardband)

Sorry for the confusion.


Regards,

Ankit


> agressiveness usecs = (10 msec) * 1000 = 10000 usecs;
>
> slope = DIV_ROUND_UP(agressiveness_usecs, guardband_usecs)
>
> So IMO name the macro     10 * 1000
> Use slope as ratio DCB_CORRECTION_AGGRESSIVENESS_USECS : guardband_usecs
>
> Regards,
> Ankit
>
>
>> + crtc_state->vrr.dc_balance.vblank_target =
>> +        DIV_ROUND_UP((crtc_state->vrr.vmax - crtc_state->vrr.vmin) *
>> +                 DCB_BLANK_TARGET, 100);
>> +}
>> +
>>   void
>>   intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
>>                struct drm_connector_state *conn_state)
>> @@ -399,6 +435,8 @@ intel_vrr_compute_config(struct intel_crtc_state 
>> *crtc_state,
>>               (crtc_state->hw.adjusted_mode.crtc_vtotal -
>>                crtc_state->hw.adjusted_mode.crtc_vsync_end);
>>       }
>> +
>> +    intel_vrr_dc_balance_compute_config(crtc_state);
>>   }
>>     static int

  reply	other threads:[~2025-11-26  7:31 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-17  5:44 [PATCH v8 00/18] Enable/Disable DC balance along with VRR DSB Mitul Golani
2025-11-17  5:44 ` [PATCH v8 01/18] drm/i915/display: Add source param for dc balance Mitul Golani
2025-11-26  3:16   ` Nautiyal, Ankit K
2025-11-17  5:44 ` [PATCH v8 02/18] drm/i915/dmc: Add pipe dmc registers and bits for DC Balance Mitul Golani
2025-11-26  3:17   ` Nautiyal, Ankit K
2025-11-26  3:18   ` Nautiyal, Ankit K
2025-11-17  5:44 ` [PATCH v8 03/18] drm/i915/vrr: Add VRR DC balance registers Mitul Golani
2025-11-26  3:19   ` Nautiyal, Ankit K
2025-11-17  5:44 ` [PATCH v8 04/18] drm/i915/vrr: Add functions to read out vmin/vmax stuff Mitul Golani
2025-11-17  5:44 ` [PATCH v8 05/18] drm/i915/vrr: Add DC Balance params to crtc_state Mitul Golani
2025-11-17  5:44 ` [PATCH v8 06/18] drm/i915/vrr: Add state dump for DC Balance params Mitul Golani
2025-11-26  3:21   ` Nautiyal, Ankit K
2025-11-17  5:44 ` [PATCH v8 07/18] drm/i915/vrr: Add compute config " Mitul Golani
2025-11-26  4:09   ` Nautiyal, Ankit K
2025-11-26  7:30     ` Nautiyal, Ankit K [this message]
2025-11-17  5:44 ` [PATCH v8 08/18] drm/i915/vrr: Add function to reset DC balance accumulated params Mitul Golani
2025-11-26  4:12   ` Nautiyal, Ankit K
2025-11-17  5:44 ` [PATCH v8 09/18] drm/i915/display: Add DC Balance flip count operations Mitul Golani
2025-11-26  4:14   ` Nautiyal, Ankit K
2025-11-17  5:44 ` [PATCH v8 10/18] drm/i915/vrr: Write DC balance params to hw registers Mitul Golani
2025-11-26  4:25   ` Nautiyal, Ankit K
2025-11-17  5:44 ` [PATCH v8 11/18] drm/i915/vblank: Extract vrr_vblank_start() Mitul Golani
2025-11-17  5:44 ` [PATCH v8 12/18] drm/i915/vrr: Implement vblank evasion with DC balancing Mitul Golani
2025-11-17  5:44 ` [PATCH v8 13/18] drm/i915/display: Wait for VRR PUSH status update Mitul Golani
2025-11-26  4:29   ` Nautiyal, Ankit K
2025-11-17  5:44 ` [PATCH v8 14/18] drm/i915/dsb: Add pipedmc dc balance enable/disable Mitul Golani
2025-11-17  5:44 ` [PATCH v8 15/18] drm/i915/vrr: Pause DC Balancing for DSB commits Mitul Golani
2025-11-17  5:44 ` [PATCH v8 16/18] drm/i915/display: Add function to configure event for dc balance Mitul Golani
2025-11-26  4:32   ` Nautiyal, Ankit K
2025-11-17  5:44 ` [PATCH v8 17/18] drm/i915/vrr: Enable DC Balance Mitul Golani
2025-11-26  4:36   ` Nautiyal, Ankit K
2025-11-26  4:45   ` Nautiyal, Ankit K
2025-11-17  5:44 ` [PATCH v8 18/18] drm/i915/vrr: Add function to check if DC Balance Possible Mitul Golani
2025-11-26  4:37   ` Nautiyal, Ankit K

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