Re: [PATCH v3 8/9] drm/i915/psr: Allow Panel Replay and PSR2 with joiner

["Hogander, Jouni" <jouni.hogander@intel.com>]

On Fri, 2026-10-23 at 10:00 +0000, Mika Kahola wrote:
> PSR is rejected outright whenever the joiner is in use. Panel Replay
> and
> PSR2 selective update do work with the joiner, so only keep rejecting
> plain PSR1.
> 
> The eDP Panel Replay pipe A/B restriction only looks at the primary
> pipe. joiner_pipes is a contiguous mask anchored at the primary pipe,
> so
> a joined config on pipe B extends to pipe C, which has no PSR/Panel
> Replay register block. Test the whole joined pipe mask instead, which
> is
> a no-op without the joiner.
> 
> PSR1/PSR2 have no equivalent pipe A/B check today. That is a
> pre-existing gap independent of the joiner and is left alone here.
> 
> v2: Drop psr_joiner_config_valid(), it duplicated the existing eDP
> Panel
>     Replay pipe A/B check and wrongly applied it to DP Panel Replay
> (Jouni)
>     Extend that existing check to the joined pipe mask instead
> (Jouni)
>     Keep only the joiner specific checks: PSR1 and YUV 4:2:0 (Jouni)
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>

I couldn't find any mention in Bspec about joiner and PSR2 + HW
tracking. Anyways Not sure if there is even need for handling that case
. There is probably no eDP panels with need for joiner in that old HW:

Reviewed-by: Jouni Högander <jouni.hogander@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 34 +++++++++++++++-------
> --
>  1 file changed, 21 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index f1d52c39d8834..288836d4a993c 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1598,6 +1598,13 @@ static bool
> intel_sel_update_config_valid(struct intel_crtc_state *crtc_state,
>  	struct intel_dp *intel_dp = intel_attached_dp(connector);
>  	struct intel_display *display = to_intel_display(intel_dp);
>  
> +	if (crtc_state->joiner_pipes && !crtc_state-
> >dsc.compression_enable &&
> +	    crtc_state->output_format ==
> INTEL_OUTPUT_FORMAT_YCBCR420) {
> +		drm_dbg_kms(display->drm,
> +			    "Selective update not enabled,
> uncompressed joiner does not support YUV 4:2:0\n");
> +		goto unsupported;
> +	}
> +
>  	if (HAS_PSR2_SEL_FETCH(display) &&
>  	    !intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state)
> &&
>  	    !HAS_PSR_HW_TRACKING(display)) {
> @@ -1745,8 +1752,8 @@ static bool _panel_replay_compute_config(struct
> intel_crtc_state *crtc_state,
>  
>  	/* Remaining checks are for eDP only */
>  
> -	if (to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_A &&
> -	    to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_B)
> +	/* Every joined pipe needs its own PSR/Panel Replay register
> block. */
> +	if (intel_crtc_joined_pipe_mask(crtc_state) & ~(BIT(PIPE_A)
> | BIT(PIPE_B)))
>  		return false;
>  
>  	/* 128b/132b Panel Replay is not supported on eDP */
> @@ -1890,17 +1897,6 @@ void intel_psr_compute_config(struct intel_dp
> *intel_dp,
>  		return;
>  	}
>  
> -	/*
> -	 * FIXME figure out what is wrong with PSR+joiner and
> -	 * fix it. Presumably something related to the fact that
> -	 * PSR is a transcoder level feature.
> -	 */
> -	if (crtc_state->joiner_pipes) {
> -		drm_dbg_kms(display->drm,
> -			    "PSR disabled due to joiner\n");
> -		return;
> -	}
> -
>  	/* Only used for state verification. */
>  	crtc_state->panel_replay_dsc_support = connector-
> >dp.panel_replay_caps.dsc_support;
>  	crtc_state->has_panel_replay =
> _panel_replay_compute_config(crtc_state, conn_state);
> @@ -1912,6 +1908,14 @@ void intel_psr_compute_config(struct intel_dp
> *intel_dp,
>  		return;
>  
>  	crtc_state->has_sel_update =
> intel_sel_update_config_valid(crtc_state, conn_state);
> +
> +	/* Plain PSR1 is not supported with joiner. */
> +	if (crtc_state->joiner_pipes && !crtc_state-
> >has_panel_replay &&
> +	    !crtc_state->has_sel_update) {
> +		drm_dbg_kms(display->drm,
> +			    "PSR disabled, PSR1 not supported with
> joiner\n");
> +		crtc_state->has_psr = false;
> +	}
>  }
>  
>  void intel_psr_get_config(struct intel_encoder *encoder,
> @@ -4755,6 +4759,10 @@ void intel_psr_compute_config_late(struct
> intel_dp *intel_dp,
>  		crtc_state->has_sel_update = false;
>  		crtc_state->enable_psr2_su_region_et = false;
>  		crtc_state->enable_psr2_sel_fetch = false;
> +
> +		/* Plain PSR1 is not supported with joiner. */
> +		if (crtc_state->joiner_pipes)
> +			crtc_state->has_psr = false;
>  	}
>  
>  	/* Wa_18037818876 */