* ✗ CI.checkpatch: warning for Make Display free from i915_reg.h (rev3)
2026-01-29 21:13 [v3 00/19] Make Display free from i915_reg.h Uma Shankar
@ 2026-01-29 21:07 ` Patchwork
2026-01-29 21:08 ` ✓ CI.KUnit: success " Patchwork
` (21 subsequent siblings)
22 siblings, 0 replies; 43+ messages in thread
From: Patchwork @ 2026-01-29 21:07 UTC (permalink / raw)
To: Uma Shankar; +Cc: intel-xe
== Series Details ==
Series: Make Display free from i915_reg.h (rev3)
URL : https://patchwork.freedesktop.org/series/159130/
State : warning
== Summary ==
+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
1f57ba1afceae32108bd24770069f764d940a0e4
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 899c000b99cdda0365b2f6085d85a9329632faba
Author: Uma Shankar <uma.shankar@intel.com>
Date: Fri Jan 30 02:43:58 2026 +0530
drm/{i915, xe}: Remove i915_reg.h from display
Make display files free from including i915_reg.h.
v2: Include modular per component headers (Jani)
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
+ /mt/dim checkpatch bd9c2b8a3a5b7bd8c38108929bfabd7a40dc922b drm-intel
5fda81c2af1f drm/i915: Extract display registers from i915_reg.h to display
-:36: WARNING:LONG_LINE: line length of 124 exceeds 100 columns
#36: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:2030:
+#define TRANS_CHICKEN2_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_CHICKEN2_FRAME_START_DELAY_MASK, (x)) /* 0-3 */
total: 0 errors, 1 warnings, 0 checks, 47 lines checked
0aecd5769cd7 drm/i915: Extract South chicken registers from i915_reg.h to display
8c53cb92ba4e drm/i915: Extract display interrupt definitions
0c70b3b905b6 drm/i915: Extract DSPCLK_GATE_D from i915_reg to display
6c0c48442ac5 drm/{i915, xe}: Extract pcode definitions to common header
-:152: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#152:
new file mode 100644
-:209: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#209: FILE: include/drm/intel/intel_pcode.h:53:
+#define DISPLAY_TO_PCODE_PIPE_COUNT(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_PIPE_COUNT_MASK, (x))
total: 0 errors, 2 warnings, 0 checks, 231 lines checked
eb932927e5c1 drm/i915: Remove i915_reg.h from intel_display_device.c
a57d529fa014 drm/i915: Remove i915_reg.h from intel_dram.c
a9bb8b7d1c87 drm/i915: Remove i915_reg.h from intel_display.c
f38f201602de drm/i915: Remove i915_reg.h from intel_overlay.c
-:150: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#150:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 142 lines checked
101c0d55ecd3 drm/i915: Remove i915_reg.h from g4x_dp.c
b55f967f9b6a drm/i915: Remove i915_reg.h from i9xx_wm.c
-:104: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#104:
new file mode 100644
-:123: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#123: FILE: include/drm/intel/intel_gmd_misc_regs.h:15:
+#define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts
+ will not assert AGPBUSY# and will only
-:124: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#124: FILE: include/drm/intel/intel_gmd_misc_regs.h:16:
+ be delivered when out of C3. */
total: 0 errors, 3 warnings, 0 checks, 91 lines checked
7ba3665c0e9c drm/{i915, xe}: Remove i915_reg.h from g4x_hdmi.c
18f52a56c7a5 drm/i915: Remove i915_reg.h from intel_rom.c
8cc5f02b26a6 drm/i915: Remove i915_reg.h from intel_psr.c
d6184898a4cd drm/i915: Remove i915_reg.h from intel_fifo_underrun.c
05530b931529 drm/i915: Remove i915_reg.h from intel_display_irq.c
d31faf5aa50c drm/i915: Remove i915_reg.h from intel_display_power_well.c
af6005da10dd drm/i915: Remove i915_reg.h from intel_modeset_setup.c
899c000b99cd drm/{i915, xe}: Remove i915_reg.h from display
^ permalink raw reply [flat|nested] 43+ messages in thread
* ✓ CI.KUnit: success for Make Display free from i915_reg.h (rev3)
2026-01-29 21:13 [v3 00/19] Make Display free from i915_reg.h Uma Shankar
2026-01-29 21:07 ` ✗ CI.checkpatch: warning for Make Display free from i915_reg.h (rev3) Patchwork
@ 2026-01-29 21:08 ` Patchwork
2026-01-29 21:13 ` [v3 01/19] drm/i915: Extract display registers from i915_reg.h to display Uma Shankar
` (20 subsequent siblings)
22 siblings, 0 replies; 43+ messages in thread
From: Patchwork @ 2026-01-29 21:08 UTC (permalink / raw)
To: Uma Shankar; +Cc: intel-xe
== Series Details ==
Series: Make Display free from i915_reg.h (rev3)
URL : https://patchwork.freedesktop.org/series/159130/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[21:06:50] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:06:55] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[21:07:33] Starting KUnit Kernel (1/1)...
[21:07:33] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:07:34] ================== guc_buf (11 subtests) ===================
[21:07:34] [PASSED] test_smallest
[21:07:34] [PASSED] test_largest
[21:07:34] [PASSED] test_granular
[21:07:34] [PASSED] test_unique
[21:07:34] [PASSED] test_overlap
[21:07:34] [PASSED] test_reusable
[21:07:34] [PASSED] test_too_big
[21:07:34] [PASSED] test_flush
[21:07:34] [PASSED] test_lookup
[21:07:34] [PASSED] test_data
[21:07:34] [PASSED] test_class
[21:07:34] ===================== [PASSED] guc_buf =====================
[21:07:34] =================== guc_dbm (7 subtests) ===================
[21:07:34] [PASSED] test_empty
[21:07:34] [PASSED] test_default
[21:07:34] ======================== test_size ========================
[21:07:34] [PASSED] 4
[21:07:34] [PASSED] 8
[21:07:34] [PASSED] 32
[21:07:34] [PASSED] 256
[21:07:34] ==================== [PASSED] test_size ====================
[21:07:34] ======================= test_reuse ========================
[21:07:34] [PASSED] 4
[21:07:34] [PASSED] 8
[21:07:34] [PASSED] 32
[21:07:34] [PASSED] 256
[21:07:34] =================== [PASSED] test_reuse ====================
[21:07:34] =================== test_range_overlap ====================
[21:07:34] [PASSED] 4
[21:07:34] [PASSED] 8
[21:07:34] [PASSED] 32
[21:07:34] [PASSED] 256
[21:07:34] =============== [PASSED] test_range_overlap ================
[21:07:34] =================== test_range_compact ====================
[21:07:34] [PASSED] 4
[21:07:34] [PASSED] 8
[21:07:34] [PASSED] 32
[21:07:34] [PASSED] 256
[21:07:34] =============== [PASSED] test_range_compact ================
[21:07:34] ==================== test_range_spare =====================
[21:07:34] [PASSED] 4
[21:07:34] [PASSED] 8
[21:07:34] [PASSED] 32
[21:07:34] [PASSED] 256
[21:07:34] ================ [PASSED] test_range_spare =================
[21:07:34] ===================== [PASSED] guc_dbm =====================
[21:07:34] =================== guc_idm (6 subtests) ===================
[21:07:34] [PASSED] bad_init
[21:07:34] [PASSED] no_init
[21:07:34] [PASSED] init_fini
[21:07:34] [PASSED] check_used
[21:07:34] [PASSED] check_quota
[21:07:34] [PASSED] check_all
[21:07:34] ===================== [PASSED] guc_idm =====================
[21:07:34] ================== no_relay (3 subtests) ===================
[21:07:34] [PASSED] xe_drops_guc2pf_if_not_ready
[21:07:34] [PASSED] xe_drops_guc2vf_if_not_ready
[21:07:34] [PASSED] xe_rejects_send_if_not_ready
[21:07:34] ==================== [PASSED] no_relay =====================
[21:07:34] ================== pf_relay (14 subtests) ==================
[21:07:34] [PASSED] pf_rejects_guc2pf_too_short
[21:07:34] [PASSED] pf_rejects_guc2pf_too_long
[21:07:34] [PASSED] pf_rejects_guc2pf_no_payload
[21:07:34] [PASSED] pf_fails_no_payload
[21:07:34] [PASSED] pf_fails_bad_origin
[21:07:34] [PASSED] pf_fails_bad_type
[21:07:34] [PASSED] pf_txn_reports_error
[21:07:34] [PASSED] pf_txn_sends_pf2guc
[21:07:34] [PASSED] pf_sends_pf2guc
[21:07:34] [SKIPPED] pf_loopback_nop
[21:07:34] [SKIPPED] pf_loopback_echo
[21:07:34] [SKIPPED] pf_loopback_fail
[21:07:34] [SKIPPED] pf_loopback_busy
[21:07:34] [SKIPPED] pf_loopback_retry
[21:07:34] ==================== [PASSED] pf_relay =====================
[21:07:34] ================== vf_relay (3 subtests) ===================
[21:07:34] [PASSED] vf_rejects_guc2vf_too_short
[21:07:34] [PASSED] vf_rejects_guc2vf_too_long
[21:07:34] [PASSED] vf_rejects_guc2vf_no_payload
[21:07:34] ==================== [PASSED] vf_relay =====================
[21:07:34] ================ pf_gt_config (6 subtests) =================
[21:07:34] [PASSED] fair_contexts_1vf
[21:07:34] [PASSED] fair_doorbells_1vf
[21:07:34] [PASSED] fair_ggtt_1vf
[21:07:34] ====================== fair_contexts ======================
[21:07:34] [PASSED] 1 VF
[21:07:34] [PASSED] 2 VFs
[21:07:34] [PASSED] 3 VFs
[21:07:34] [PASSED] 4 VFs
[21:07:34] [PASSED] 5 VFs
[21:07:34] [PASSED] 6 VFs
[21:07:34] [PASSED] 7 VFs
[21:07:34] [PASSED] 8 VFs
[21:07:34] [PASSED] 9 VFs
[21:07:34] [PASSED] 10 VFs
[21:07:34] [PASSED] 11 VFs
[21:07:34] [PASSED] 12 VFs
[21:07:34] [PASSED] 13 VFs
[21:07:34] [PASSED] 14 VFs
[21:07:34] [PASSED] 15 VFs
[21:07:34] [PASSED] 16 VFs
[21:07:34] [PASSED] 17 VFs
[21:07:34] [PASSED] 18 VFs
[21:07:34] [PASSED] 19 VFs
[21:07:34] [PASSED] 20 VFs
[21:07:34] [PASSED] 21 VFs
[21:07:34] [PASSED] 22 VFs
[21:07:34] [PASSED] 23 VFs
[21:07:34] [PASSED] 24 VFs
[21:07:34] [PASSED] 25 VFs
[21:07:34] [PASSED] 26 VFs
[21:07:34] [PASSED] 27 VFs
[21:07:34] [PASSED] 28 VFs
[21:07:34] [PASSED] 29 VFs
[21:07:34] [PASSED] 30 VFs
[21:07:34] [PASSED] 31 VFs
[21:07:34] [PASSED] 32 VFs
[21:07:34] [PASSED] 33 VFs
[21:07:34] [PASSED] 34 VFs
[21:07:34] [PASSED] 35 VFs
[21:07:34] [PASSED] 36 VFs
[21:07:34] [PASSED] 37 VFs
[21:07:34] [PASSED] 38 VFs
[21:07:34] [PASSED] 39 VFs
[21:07:34] [PASSED] 40 VFs
[21:07:34] [PASSED] 41 VFs
[21:07:34] [PASSED] 42 VFs
[21:07:34] [PASSED] 43 VFs
[21:07:34] [PASSED] 44 VFs
[21:07:34] [PASSED] 45 VFs
[21:07:34] [PASSED] 46 VFs
[21:07:34] [PASSED] 47 VFs
[21:07:34] [PASSED] 48 VFs
[21:07:34] [PASSED] 49 VFs
[21:07:34] [PASSED] 50 VFs
[21:07:34] [PASSED] 51 VFs
[21:07:34] [PASSED] 52 VFs
[21:07:34] [PASSED] 53 VFs
[21:07:34] [PASSED] 54 VFs
[21:07:34] [PASSED] 55 VFs
[21:07:34] [PASSED] 56 VFs
[21:07:34] [PASSED] 57 VFs
[21:07:34] [PASSED] 58 VFs
[21:07:34] [PASSED] 59 VFs
[21:07:34] [PASSED] 60 VFs
[21:07:34] [PASSED] 61 VFs
[21:07:34] [PASSED] 62 VFs
[21:07:34] [PASSED] 63 VFs
[21:07:34] ================== [PASSED] fair_contexts ==================
[21:07:34] ===================== fair_doorbells ======================
[21:07:34] [PASSED] 1 VF
[21:07:34] [PASSED] 2 VFs
[21:07:34] [PASSED] 3 VFs
[21:07:34] [PASSED] 4 VFs
[21:07:34] [PASSED] 5 VFs
[21:07:34] [PASSED] 6 VFs
[21:07:34] [PASSED] 7 VFs
[21:07:34] [PASSED] 8 VFs
[21:07:34] [PASSED] 9 VFs
[21:07:34] [PASSED] 10 VFs
[21:07:34] [PASSED] 11 VFs
[21:07:34] [PASSED] 12 VFs
[21:07:34] [PASSED] 13 VFs
[21:07:34] [PASSED] 14 VFs
[21:07:34] [PASSED] 15 VFs
[21:07:34] [PASSED] 16 VFs
[21:07:34] [PASSED] 17 VFs
[21:07:34] [PASSED] 18 VFs
[21:07:34] [PASSED] 19 VFs
[21:07:34] [PASSED] 20 VFs
[21:07:34] [PASSED] 21 VFs
[21:07:34] [PASSED] 22 VFs
[21:07:34] [PASSED] 23 VFs
[21:07:34] [PASSED] 24 VFs
[21:07:34] [PASSED] 25 VFs
[21:07:34] [PASSED] 26 VFs
[21:07:34] [PASSED] 27 VFs
[21:07:34] [PASSED] 28 VFs
[21:07:34] [PASSED] 29 VFs
[21:07:34] [PASSED] 30 VFs
[21:07:34] [PASSED] 31 VFs
[21:07:34] [PASSED] 32 VFs
[21:07:34] [PASSED] 33 VFs
[21:07:34] [PASSED] 34 VFs
[21:07:34] [PASSED] 35 VFs
[21:07:34] [PASSED] 36 VFs
[21:07:34] [PASSED] 37 VFs
[21:07:34] [PASSED] 38 VFs
[21:07:34] [PASSED] 39 VFs
[21:07:34] [PASSED] 40 VFs
[21:07:34] [PASSED] 41 VFs
[21:07:34] [PASSED] 42 VFs
[21:07:34] [PASSED] 43 VFs
[21:07:34] [PASSED] 44 VFs
[21:07:34] [PASSED] 45 VFs
[21:07:34] [PASSED] 46 VFs
[21:07:34] [PASSED] 47 VFs
[21:07:34] [PASSED] 48 VFs
[21:07:34] [PASSED] 49 VFs
[21:07:34] [PASSED] 50 VFs
[21:07:34] [PASSED] 51 VFs
[21:07:34] [PASSED] 52 VFs
[21:07:34] [PASSED] 53 VFs
[21:07:34] [PASSED] 54 VFs
[21:07:34] [PASSED] 55 VFs
[21:07:34] [PASSED] 56 VFs
[21:07:34] [PASSED] 57 VFs
[21:07:34] [PASSED] 58 VFs
[21:07:34] [PASSED] 59 VFs
[21:07:34] [PASSED] 60 VFs
[21:07:34] [PASSED] 61 VFs
[21:07:34] [PASSED] 62 VFs
[21:07:34] [PASSED] 63 VFs
[21:07:34] ================= [PASSED] fair_doorbells ==================
[21:07:34] ======================== fair_ggtt ========================
[21:07:34] [PASSED] 1 VF
[21:07:34] [PASSED] 2 VFs
[21:07:34] [PASSED] 3 VFs
[21:07:34] [PASSED] 4 VFs
[21:07:34] [PASSED] 5 VFs
[21:07:34] [PASSED] 6 VFs
[21:07:34] [PASSED] 7 VFs
[21:07:34] [PASSED] 8 VFs
[21:07:34] [PASSED] 9 VFs
[21:07:34] [PASSED] 10 VFs
[21:07:34] [PASSED] 11 VFs
[21:07:34] [PASSED] 12 VFs
[21:07:34] [PASSED] 13 VFs
[21:07:34] [PASSED] 14 VFs
[21:07:34] [PASSED] 15 VFs
[21:07:34] [PASSED] 16 VFs
[21:07:34] [PASSED] 17 VFs
[21:07:34] [PASSED] 18 VFs
[21:07:34] [PASSED] 19 VFs
[21:07:34] [PASSED] 20 VFs
[21:07:34] [PASSED] 21 VFs
[21:07:34] [PASSED] 22 VFs
[21:07:34] [PASSED] 23 VFs
[21:07:34] [PASSED] 24 VFs
[21:07:34] [PASSED] 25 VFs
[21:07:34] [PASSED] 26 VFs
[21:07:34] [PASSED] 27 VFs
[21:07:34] [PASSED] 28 VFs
[21:07:34] [PASSED] 29 VFs
[21:07:34] [PASSED] 30 VFs
[21:07:34] [PASSED] 31 VFs
[21:07:34] [PASSED] 32 VFs
[21:07:34] [PASSED] 33 VFs
[21:07:34] [PASSED] 34 VFs
[21:07:34] [PASSED] 35 VFs
[21:07:34] [PASSED] 36 VFs
[21:07:34] [PASSED] 37 VFs
[21:07:34] [PASSED] 38 VFs
[21:07:34] [PASSED] 39 VFs
[21:07:34] [PASSED] 40 VFs
[21:07:34] [PASSED] 41 VFs
[21:07:34] [PASSED] 42 VFs
[21:07:34] [PASSED] 43 VFs
[21:07:34] [PASSED] 44 VFs
[21:07:34] [PASSED] 45 VFs
[21:07:34] [PASSED] 46 VFs
[21:07:34] [PASSED] 47 VFs
[21:07:34] [PASSED] 48 VFs
[21:07:34] [PASSED] 49 VFs
[21:07:34] [PASSED] 50 VFs
[21:07:34] [PASSED] 51 VFs
[21:07:34] [PASSED] 52 VFs
[21:07:34] [PASSED] 53 VFs
[21:07:34] [PASSED] 54 VFs
[21:07:34] [PASSED] 55 VFs
[21:07:34] [PASSED] 56 VFs
[21:07:34] [PASSED] 57 VFs
[21:07:34] [PASSED] 58 VFs
[21:07:34] [PASSED] 59 VFs
[21:07:34] [PASSED] 60 VFs
[21:07:34] [PASSED] 61 VFs
[21:07:34] [PASSED] 62 VFs
[21:07:34] [PASSED] 63 VFs
[21:07:34] ==================== [PASSED] fair_ggtt ====================
[21:07:34] ================== [PASSED] pf_gt_config ===================
[21:07:34] ===================== lmtt (1 subtest) =====================
[21:07:34] ======================== test_ops =========================
[21:07:34] [PASSED] 2-level
[21:07:34] [PASSED] multi-level
[21:07:34] ==================== [PASSED] test_ops =====================
[21:07:34] ====================== [PASSED] lmtt =======================
[21:07:34] ================= pf_service (11 subtests) =================
[21:07:34] [PASSED] pf_negotiate_any
[21:07:34] [PASSED] pf_negotiate_base_match
[21:07:34] [PASSED] pf_negotiate_base_newer
[21:07:34] [PASSED] pf_negotiate_base_next
[21:07:34] [SKIPPED] pf_negotiate_base_older
[21:07:34] [PASSED] pf_negotiate_base_prev
[21:07:34] [PASSED] pf_negotiate_latest_match
[21:07:34] [PASSED] pf_negotiate_latest_newer
[21:07:34] [PASSED] pf_negotiate_latest_next
[21:07:34] [SKIPPED] pf_negotiate_latest_older
[21:07:34] [SKIPPED] pf_negotiate_latest_prev
[21:07:34] =================== [PASSED] pf_service ====================
[21:07:34] ================= xe_guc_g2g (2 subtests) ==================
[21:07:34] ============== xe_live_guc_g2g_kunit_default ==============
[21:07:34] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[21:07:34] ============== xe_live_guc_g2g_kunit_allmem ===============
[21:07:34] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[21:07:34] =================== [SKIPPED] xe_guc_g2g ===================
[21:07:34] =================== xe_mocs (2 subtests) ===================
[21:07:34] ================ xe_live_mocs_kernel_kunit ================
[21:07:34] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[21:07:34] ================ xe_live_mocs_reset_kunit =================
[21:07:34] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[21:07:34] ==================== [SKIPPED] xe_mocs =====================
[21:07:34] ================= xe_migrate (2 subtests) ==================
[21:07:34] ================= xe_migrate_sanity_kunit =================
[21:07:34] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[21:07:34] ================== xe_validate_ccs_kunit ==================
[21:07:34] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[21:07:34] =================== [SKIPPED] xe_migrate ===================
[21:07:34] ================== xe_dma_buf (1 subtest) ==================
[21:07:34] ==================== xe_dma_buf_kunit =====================
[21:07:34] ================ [SKIPPED] xe_dma_buf_kunit ================
[21:07:34] =================== [SKIPPED] xe_dma_buf ===================
[21:07:34] ================= xe_bo_shrink (1 subtest) =================
[21:07:34] =================== xe_bo_shrink_kunit ====================
[21:07:34] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[21:07:34] ================== [SKIPPED] xe_bo_shrink ==================
[21:07:34] ==================== xe_bo (2 subtests) ====================
[21:07:34] ================== xe_ccs_migrate_kunit ===================
[21:07:34] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[21:07:34] ==================== xe_bo_evict_kunit ====================
[21:07:34] =============== [SKIPPED] xe_bo_evict_kunit ================
[21:07:34] ===================== [SKIPPED] xe_bo ======================
[21:07:34] ==================== args (13 subtests) ====================
[21:07:34] [PASSED] count_args_test
[21:07:34] [PASSED] call_args_example
[21:07:34] [PASSED] call_args_test
[21:07:34] [PASSED] drop_first_arg_example
[21:07:34] [PASSED] drop_first_arg_test
[21:07:34] [PASSED] first_arg_example
[21:07:34] [PASSED] first_arg_test
[21:07:34] [PASSED] last_arg_example
[21:07:34] [PASSED] last_arg_test
[21:07:34] [PASSED] pick_arg_example
[21:07:34] [PASSED] if_args_example
[21:07:34] [PASSED] if_args_test
[21:07:34] [PASSED] sep_comma_example
[21:07:34] ====================== [PASSED] args =======================
[21:07:34] =================== xe_pci (3 subtests) ====================
[21:07:34] ==================== check_graphics_ip ====================
[21:07:34] [PASSED] 12.00 Xe_LP
[21:07:34] [PASSED] 12.10 Xe_LP+
[21:07:34] [PASSED] 12.55 Xe_HPG
[21:07:34] [PASSED] 12.60 Xe_HPC
[21:07:34] [PASSED] 12.70 Xe_LPG
[21:07:34] [PASSED] 12.71 Xe_LPG
[21:07:34] [PASSED] 12.74 Xe_LPG+
[21:07:34] [PASSED] 20.01 Xe2_HPG
[21:07:34] [PASSED] 20.02 Xe2_HPG
[21:07:34] [PASSED] 20.04 Xe2_LPG
[21:07:34] [PASSED] 30.00 Xe3_LPG
[21:07:34] [PASSED] 30.01 Xe3_LPG
[21:07:34] [PASSED] 30.03 Xe3_LPG
[21:07:34] [PASSED] 30.04 Xe3_LPG
[21:07:34] [PASSED] 30.05 Xe3_LPG
[21:07:34] [PASSED] 35.11 Xe3p_XPC
[21:07:34] ================ [PASSED] check_graphics_ip ================
[21:07:34] ===================== check_media_ip ======================
[21:07:34] [PASSED] 12.00 Xe_M
[21:07:34] [PASSED] 12.55 Xe_HPM
[21:07:34] [PASSED] 13.00 Xe_LPM+
[21:07:34] [PASSED] 13.01 Xe2_HPM
[21:07:34] [PASSED] 20.00 Xe2_LPM
[21:07:34] [PASSED] 30.00 Xe3_LPM
[21:07:34] [PASSED] 30.02 Xe3_LPM
[21:07:34] [PASSED] 35.00 Xe3p_LPM
[21:07:34] [PASSED] 35.03 Xe3p_HPM
[21:07:34] ================= [PASSED] check_media_ip ==================
[21:07:34] =================== check_platform_desc ===================
[21:07:34] [PASSED] 0x9A60 (TIGERLAKE)
[21:07:34] [PASSED] 0x9A68 (TIGERLAKE)
[21:07:34] [PASSED] 0x9A70 (TIGERLAKE)
[21:07:34] [PASSED] 0x9A40 (TIGERLAKE)
[21:07:34] [PASSED] 0x9A49 (TIGERLAKE)
[21:07:34] [PASSED] 0x9A59 (TIGERLAKE)
[21:07:34] [PASSED] 0x9A78 (TIGERLAKE)
[21:07:34] [PASSED] 0x9AC0 (TIGERLAKE)
[21:07:34] [PASSED] 0x9AC9 (TIGERLAKE)
[21:07:34] [PASSED] 0x9AD9 (TIGERLAKE)
[21:07:34] [PASSED] 0x9AF8 (TIGERLAKE)
[21:07:34] [PASSED] 0x4C80 (ROCKETLAKE)
[21:07:34] [PASSED] 0x4C8A (ROCKETLAKE)
[21:07:34] [PASSED] 0x4C8B (ROCKETLAKE)
[21:07:34] [PASSED] 0x4C8C (ROCKETLAKE)
[21:07:34] [PASSED] 0x4C90 (ROCKETLAKE)
[21:07:34] [PASSED] 0x4C9A (ROCKETLAKE)
[21:07:34] [PASSED] 0x4680 (ALDERLAKE_S)
[21:07:34] [PASSED] 0x4682 (ALDERLAKE_S)
[21:07:34] [PASSED] 0x4688 (ALDERLAKE_S)
[21:07:34] [PASSED] 0x468A (ALDERLAKE_S)
[21:07:34] [PASSED] 0x468B (ALDERLAKE_S)
[21:07:34] [PASSED] 0x4690 (ALDERLAKE_S)
[21:07:34] [PASSED] 0x4692 (ALDERLAKE_S)
[21:07:34] [PASSED] 0x4693 (ALDERLAKE_S)
[21:07:34] [PASSED] 0x46A0 (ALDERLAKE_P)
[21:07:34] [PASSED] 0x46A1 (ALDERLAKE_P)
[21:07:34] [PASSED] 0x46A2 (ALDERLAKE_P)
[21:07:34] [PASSED] 0x46A3 (ALDERLAKE_P)
[21:07:34] [PASSED] 0x46A6 (ALDERLAKE_P)
[21:07:34] [PASSED] 0x46A8 (ALDERLAKE_P)
[21:07:34] [PASSED] 0x46AA (ALDERLAKE_P)
[21:07:34] [PASSED] 0x462A (ALDERLAKE_P)
[21:07:34] [PASSED] 0x4626 (ALDERLAKE_P)
[21:07:34] [PASSED] 0x4628 (ALDERLAKE_P)
stty: 'standard input': Inappropriate ioctl for device
[21:07:34] [PASSED] 0x46B0 (ALDERLAKE_P)
[21:07:34] [PASSED] 0x46B1 (ALDERLAKE_P)
[21:07:34] [PASSED] 0x46B2 (ALDERLAKE_P)
[21:07:34] [PASSED] 0x46B3 (ALDERLAKE_P)
[21:07:34] [PASSED] 0x46C0 (ALDERLAKE_P)
[21:07:34] [PASSED] 0x46C1 (ALDERLAKE_P)
[21:07:34] [PASSED] 0x46C2 (ALDERLAKE_P)
[21:07:34] [PASSED] 0x46C3 (ALDERLAKE_P)
[21:07:34] [PASSED] 0x46D0 (ALDERLAKE_N)
[21:07:34] [PASSED] 0x46D1 (ALDERLAKE_N)
[21:07:34] [PASSED] 0x46D2 (ALDERLAKE_N)
[21:07:34] [PASSED] 0x46D3 (ALDERLAKE_N)
[21:07:34] [PASSED] 0x46D4 (ALDERLAKE_N)
[21:07:34] [PASSED] 0xA721 (ALDERLAKE_P)
[21:07:34] [PASSED] 0xA7A1 (ALDERLAKE_P)
[21:07:34] [PASSED] 0xA7A9 (ALDERLAKE_P)
[21:07:34] [PASSED] 0xA7AC (ALDERLAKE_P)
[21:07:34] [PASSED] 0xA7AD (ALDERLAKE_P)
[21:07:34] [PASSED] 0xA720 (ALDERLAKE_P)
[21:07:34] [PASSED] 0xA7A0 (ALDERLAKE_P)
[21:07:34] [PASSED] 0xA7A8 (ALDERLAKE_P)
[21:07:34] [PASSED] 0xA7AA (ALDERLAKE_P)
[21:07:34] [PASSED] 0xA7AB (ALDERLAKE_P)
[21:07:34] [PASSED] 0xA780 (ALDERLAKE_S)
[21:07:34] [PASSED] 0xA781 (ALDERLAKE_S)
[21:07:34] [PASSED] 0xA782 (ALDERLAKE_S)
[21:07:34] [PASSED] 0xA783 (ALDERLAKE_S)
[21:07:34] [PASSED] 0xA788 (ALDERLAKE_S)
[21:07:34] [PASSED] 0xA789 (ALDERLAKE_S)
[21:07:34] [PASSED] 0xA78A (ALDERLAKE_S)
[21:07:34] [PASSED] 0xA78B (ALDERLAKE_S)
[21:07:34] [PASSED] 0x4905 (DG1)
[21:07:34] [PASSED] 0x4906 (DG1)
[21:07:34] [PASSED] 0x4907 (DG1)
[21:07:34] [PASSED] 0x4908 (DG1)
[21:07:34] [PASSED] 0x4909 (DG1)
[21:07:34] [PASSED] 0x56C0 (DG2)
[21:07:34] [PASSED] 0x56C2 (DG2)
[21:07:34] [PASSED] 0x56C1 (DG2)
[21:07:34] [PASSED] 0x7D51 (METEORLAKE)
[21:07:34] [PASSED] 0x7DD1 (METEORLAKE)
[21:07:34] [PASSED] 0x7D41 (METEORLAKE)
[21:07:34] [PASSED] 0x7D67 (METEORLAKE)
[21:07:34] [PASSED] 0xB640 (METEORLAKE)
[21:07:34] [PASSED] 0x56A0 (DG2)
[21:07:34] [PASSED] 0x56A1 (DG2)
[21:07:34] [PASSED] 0x56A2 (DG2)
[21:07:34] [PASSED] 0x56BE (DG2)
[21:07:34] [PASSED] 0x56BF (DG2)
[21:07:34] [PASSED] 0x5690 (DG2)
[21:07:34] [PASSED] 0x5691 (DG2)
[21:07:34] [PASSED] 0x5692 (DG2)
[21:07:34] [PASSED] 0x56A5 (DG2)
[21:07:34] [PASSED] 0x56A6 (DG2)
[21:07:34] [PASSED] 0x56B0 (DG2)
[21:07:34] [PASSED] 0x56B1 (DG2)
[21:07:34] [PASSED] 0x56BA (DG2)
[21:07:34] [PASSED] 0x56BB (DG2)
[21:07:34] [PASSED] 0x56BC (DG2)
[21:07:34] [PASSED] 0x56BD (DG2)
[21:07:34] [PASSED] 0x5693 (DG2)
[21:07:34] [PASSED] 0x5694 (DG2)
[21:07:34] [PASSED] 0x5695 (DG2)
[21:07:34] [PASSED] 0x56A3 (DG2)
[21:07:34] [PASSED] 0x56A4 (DG2)
[21:07:34] [PASSED] 0x56B2 (DG2)
[21:07:34] [PASSED] 0x56B3 (DG2)
[21:07:34] [PASSED] 0x5696 (DG2)
[21:07:34] [PASSED] 0x5697 (DG2)
[21:07:34] [PASSED] 0xB69 (PVC)
[21:07:34] [PASSED] 0xB6E (PVC)
[21:07:34] [PASSED] 0xBD4 (PVC)
[21:07:34] [PASSED] 0xBD5 (PVC)
[21:07:34] [PASSED] 0xBD6 (PVC)
[21:07:34] [PASSED] 0xBD7 (PVC)
[21:07:34] [PASSED] 0xBD8 (PVC)
[21:07:34] [PASSED] 0xBD9 (PVC)
[21:07:34] [PASSED] 0xBDA (PVC)
[21:07:34] [PASSED] 0xBDB (PVC)
[21:07:34] [PASSED] 0xBE0 (PVC)
[21:07:34] [PASSED] 0xBE1 (PVC)
[21:07:34] [PASSED] 0xBE5 (PVC)
[21:07:34] [PASSED] 0x7D40 (METEORLAKE)
[21:07:34] [PASSED] 0x7D45 (METEORLAKE)
[21:07:34] [PASSED] 0x7D55 (METEORLAKE)
[21:07:34] [PASSED] 0x7D60 (METEORLAKE)
[21:07:34] [PASSED] 0x7DD5 (METEORLAKE)
[21:07:34] [PASSED] 0x6420 (LUNARLAKE)
[21:07:34] [PASSED] 0x64A0 (LUNARLAKE)
[21:07:34] [PASSED] 0x64B0 (LUNARLAKE)
[21:07:34] [PASSED] 0xE202 (BATTLEMAGE)
[21:07:34] [PASSED] 0xE209 (BATTLEMAGE)
[21:07:34] [PASSED] 0xE20B (BATTLEMAGE)
[21:07:34] [PASSED] 0xE20C (BATTLEMAGE)
[21:07:34] [PASSED] 0xE20D (BATTLEMAGE)
[21:07:34] [PASSED] 0xE210 (BATTLEMAGE)
[21:07:34] [PASSED] 0xE211 (BATTLEMAGE)
[21:07:34] [PASSED] 0xE212 (BATTLEMAGE)
[21:07:34] [PASSED] 0xE216 (BATTLEMAGE)
[21:07:34] [PASSED] 0xE220 (BATTLEMAGE)
[21:07:34] [PASSED] 0xE221 (BATTLEMAGE)
[21:07:34] [PASSED] 0xE222 (BATTLEMAGE)
[21:07:34] [PASSED] 0xE223 (BATTLEMAGE)
[21:07:34] [PASSED] 0xB080 (PANTHERLAKE)
[21:07:34] [PASSED] 0xB081 (PANTHERLAKE)
[21:07:34] [PASSED] 0xB082 (PANTHERLAKE)
[21:07:34] [PASSED] 0xB083 (PANTHERLAKE)
[21:07:34] [PASSED] 0xB084 (PANTHERLAKE)
[21:07:34] [PASSED] 0xB085 (PANTHERLAKE)
[21:07:34] [PASSED] 0xB086 (PANTHERLAKE)
[21:07:34] [PASSED] 0xB087 (PANTHERLAKE)
[21:07:34] [PASSED] 0xB08F (PANTHERLAKE)
[21:07:34] [PASSED] 0xB090 (PANTHERLAKE)
[21:07:34] [PASSED] 0xB0A0 (PANTHERLAKE)
[21:07:34] [PASSED] 0xB0B0 (PANTHERLAKE)
[21:07:34] [PASSED] 0xFD80 (PANTHERLAKE)
[21:07:34] [PASSED] 0xFD81 (PANTHERLAKE)
[21:07:34] [PASSED] 0xD740 (NOVALAKE_S)
[21:07:34] [PASSED] 0xD741 (NOVALAKE_S)
[21:07:34] [PASSED] 0xD742 (NOVALAKE_S)
[21:07:34] [PASSED] 0xD743 (NOVALAKE_S)
[21:07:34] [PASSED] 0xD744 (NOVALAKE_S)
[21:07:34] [PASSED] 0xD745 (NOVALAKE_S)
[21:07:34] [PASSED] 0x674C (CRESCENTISLAND)
[21:07:34] =============== [PASSED] check_platform_desc ===============
[21:07:34] ===================== [PASSED] xe_pci ======================
[21:07:34] =================== xe_rtp (2 subtests) ====================
[21:07:34] =============== xe_rtp_process_to_sr_tests ================
[21:07:34] [PASSED] coalesce-same-reg
[21:07:34] [PASSED] no-match-no-add
[21:07:34] [PASSED] match-or
[21:07:34] [PASSED] match-or-xfail
[21:07:34] [PASSED] no-match-no-add-multiple-rules
[21:07:34] [PASSED] two-regs-two-entries
[21:07:34] [PASSED] clr-one-set-other
[21:07:34] [PASSED] set-field
[21:07:34] [PASSED] conflict-duplicate
[21:07:34] [PASSED] conflict-not-disjoint
[21:07:34] [PASSED] conflict-reg-type
[21:07:34] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[21:07:34] ================== xe_rtp_process_tests ===================
[21:07:34] [PASSED] active1
[21:07:34] [PASSED] active2
[21:07:34] [PASSED] active-inactive
[21:07:34] [PASSED] inactive-active
[21:07:34] [PASSED] inactive-1st_or_active-inactive
[21:07:34] [PASSED] inactive-2nd_or_active-inactive
[21:07:34] [PASSED] inactive-last_or_active-inactive
[21:07:34] [PASSED] inactive-no_or_active-inactive
[21:07:34] ============== [PASSED] xe_rtp_process_tests ===============
[21:07:34] ===================== [PASSED] xe_rtp ======================
[21:07:34] ==================== xe_wa (1 subtest) =====================
[21:07:34] ======================== xe_wa_gt =========================
[21:07:34] [PASSED] TIGERLAKE B0
[21:07:34] [PASSED] DG1 A0
[21:07:34] [PASSED] DG1 B0
[21:07:34] [PASSED] ALDERLAKE_S A0
[21:07:34] [PASSED] ALDERLAKE_S B0
[21:07:34] [PASSED] ALDERLAKE_S C0
[21:07:34] [PASSED] ALDERLAKE_S D0
[21:07:34] [PASSED] ALDERLAKE_P A0
[21:07:34] [PASSED] ALDERLAKE_P B0
[21:07:34] [PASSED] ALDERLAKE_P C0
[21:07:34] [PASSED] ALDERLAKE_S RPLS D0
[21:07:34] [PASSED] ALDERLAKE_P RPLU E0
[21:07:34] [PASSED] DG2 G10 C0
[21:07:34] [PASSED] DG2 G11 B1
[21:07:34] [PASSED] DG2 G12 A1
[21:07:34] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[21:07:34] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[21:07:34] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[21:07:34] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[21:07:34] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[21:07:34] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[21:07:34] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[21:07:34] ==================== [PASSED] xe_wa_gt =====================
[21:07:34] ====================== [PASSED] xe_wa ======================
[21:07:34] ============================================================
[21:07:34] Testing complete. Ran 512 tests: passed: 494, skipped: 18
[21:07:34] Elapsed time: 43.742s total, 4.305s configuring, 38.920s building, 0.489s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[21:07:34] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:07:36] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[21:08:06] Starting KUnit Kernel (1/1)...
[21:08:06] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:08:06] ============ drm_test_pick_cmdline (2 subtests) ============
[21:08:06] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[21:08:06] =============== drm_test_pick_cmdline_named ===============
[21:08:06] [PASSED] NTSC
[21:08:06] [PASSED] NTSC-J
[21:08:06] [PASSED] PAL
[21:08:06] [PASSED] PAL-M
[21:08:06] =========== [PASSED] drm_test_pick_cmdline_named ===========
[21:08:06] ============== [PASSED] drm_test_pick_cmdline ==============
[21:08:06] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[21:08:06] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[21:08:06] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[21:08:06] =========== drm_validate_clone_mode (2 subtests) ===========
[21:08:06] ============== drm_test_check_in_clone_mode ===============
[21:08:06] [PASSED] in_clone_mode
[21:08:06] [PASSED] not_in_clone_mode
[21:08:06] ========== [PASSED] drm_test_check_in_clone_mode ===========
[21:08:06] =============== drm_test_check_valid_clones ===============
[21:08:06] [PASSED] not_in_clone_mode
[21:08:06] [PASSED] valid_clone
[21:08:06] [PASSED] invalid_clone
[21:08:06] =========== [PASSED] drm_test_check_valid_clones ===========
[21:08:06] ============= [PASSED] drm_validate_clone_mode =============
[21:08:06] ============= drm_validate_modeset (1 subtest) =============
[21:08:06] [PASSED] drm_test_check_connector_changed_modeset
[21:08:06] ============== [PASSED] drm_validate_modeset ===============
[21:08:06] ====== drm_test_bridge_get_current_state (2 subtests) ======
[21:08:06] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[21:08:06] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[21:08:06] ======== [PASSED] drm_test_bridge_get_current_state ========
[21:08:06] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[21:08:06] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[21:08:06] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[21:08:06] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[21:08:06] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[21:08:06] ============== drm_bridge_alloc (2 subtests) ===============
[21:08:06] [PASSED] drm_test_drm_bridge_alloc_basic
[21:08:06] [PASSED] drm_test_drm_bridge_alloc_get_put
[21:08:06] ================ [PASSED] drm_bridge_alloc =================
[21:08:06] ================== drm_buddy (9 subtests) ==================
[21:08:06] [PASSED] drm_test_buddy_alloc_limit
[21:08:06] [PASSED] drm_test_buddy_alloc_optimistic
[21:08:06] [PASSED] drm_test_buddy_alloc_pessimistic
[21:08:06] [PASSED] drm_test_buddy_alloc_pathological
[21:08:06] [PASSED] drm_test_buddy_alloc_contiguous
[21:08:06] [PASSED] drm_test_buddy_alloc_clear
[21:08:06] [PASSED] drm_test_buddy_alloc_range_bias
[21:08:06] [PASSED] drm_test_buddy_fragmentation_performance
[21:08:06] [PASSED] drm_test_buddy_alloc_exceeds_max_order
[21:08:06] ==================== [PASSED] drm_buddy ====================
[21:08:06] ============= drm_cmdline_parser (40 subtests) =============
[21:08:06] [PASSED] drm_test_cmdline_force_d_only
[21:08:06] [PASSED] drm_test_cmdline_force_D_only_dvi
[21:08:06] [PASSED] drm_test_cmdline_force_D_only_hdmi
[21:08:06] [PASSED] drm_test_cmdline_force_D_only_not_digital
[21:08:06] [PASSED] drm_test_cmdline_force_e_only
[21:08:06] [PASSED] drm_test_cmdline_res
[21:08:06] [PASSED] drm_test_cmdline_res_vesa
[21:08:06] [PASSED] drm_test_cmdline_res_vesa_rblank
[21:08:06] [PASSED] drm_test_cmdline_res_rblank
[21:08:06] [PASSED] drm_test_cmdline_res_bpp
[21:08:06] [PASSED] drm_test_cmdline_res_refresh
[21:08:06] [PASSED] drm_test_cmdline_res_bpp_refresh
[21:08:06] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[21:08:06] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[21:08:06] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[21:08:06] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[21:08:06] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[21:08:06] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[21:08:06] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[21:08:06] [PASSED] drm_test_cmdline_res_margins_force_on
[21:08:06] [PASSED] drm_test_cmdline_res_vesa_margins
[21:08:06] [PASSED] drm_test_cmdline_name
[21:08:06] [PASSED] drm_test_cmdline_name_bpp
[21:08:06] [PASSED] drm_test_cmdline_name_option
[21:08:06] [PASSED] drm_test_cmdline_name_bpp_option
[21:08:06] [PASSED] drm_test_cmdline_rotate_0
[21:08:06] [PASSED] drm_test_cmdline_rotate_90
[21:08:06] [PASSED] drm_test_cmdline_rotate_180
[21:08:06] [PASSED] drm_test_cmdline_rotate_270
[21:08:06] [PASSED] drm_test_cmdline_hmirror
[21:08:06] [PASSED] drm_test_cmdline_vmirror
[21:08:06] [PASSED] drm_test_cmdline_margin_options
[21:08:06] [PASSED] drm_test_cmdline_multiple_options
[21:08:06] [PASSED] drm_test_cmdline_bpp_extra_and_option
[21:08:06] [PASSED] drm_test_cmdline_extra_and_option
[21:08:06] [PASSED] drm_test_cmdline_freestanding_options
[21:08:06] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[21:08:06] [PASSED] drm_test_cmdline_panel_orientation
[21:08:06] ================ drm_test_cmdline_invalid =================
[21:08:06] [PASSED] margin_only
[21:08:06] [PASSED] interlace_only
[21:08:06] [PASSED] res_missing_x
[21:08:06] [PASSED] res_missing_y
[21:08:06] [PASSED] res_bad_y
[21:08:06] [PASSED] res_missing_y_bpp
[21:08:06] [PASSED] res_bad_bpp
[21:08:06] [PASSED] res_bad_refresh
[21:08:06] [PASSED] res_bpp_refresh_force_on_off
[21:08:06] [PASSED] res_invalid_mode
[21:08:06] [PASSED] res_bpp_wrong_place_mode
[21:08:06] [PASSED] name_bpp_refresh
[21:08:06] [PASSED] name_refresh
[21:08:06] [PASSED] name_refresh_wrong_mode
[21:08:06] [PASSED] name_refresh_invalid_mode
[21:08:06] [PASSED] rotate_multiple
[21:08:06] [PASSED] rotate_invalid_val
[21:08:06] [PASSED] rotate_truncated
[21:08:06] [PASSED] invalid_option
[21:08:06] [PASSED] invalid_tv_option
[21:08:06] [PASSED] truncated_tv_option
[21:08:06] ============ [PASSED] drm_test_cmdline_invalid =============
[21:08:06] =============== drm_test_cmdline_tv_options ===============
[21:08:06] [PASSED] NTSC
[21:08:06] [PASSED] NTSC_443
[21:08:06] [PASSED] NTSC_J
[21:08:06] [PASSED] PAL
[21:08:06] [PASSED] PAL_M
[21:08:06] [PASSED] PAL_N
[21:08:06] [PASSED] SECAM
[21:08:06] [PASSED] MONO_525
[21:08:06] [PASSED] MONO_625
[21:08:06] =========== [PASSED] drm_test_cmdline_tv_options ===========
[21:08:06] =============== [PASSED] drm_cmdline_parser ================
[21:08:06] ========== drmm_connector_hdmi_init (20 subtests) ==========
[21:08:06] [PASSED] drm_test_connector_hdmi_init_valid
[21:08:06] [PASSED] drm_test_connector_hdmi_init_bpc_8
[21:08:06] [PASSED] drm_test_connector_hdmi_init_bpc_10
[21:08:06] [PASSED] drm_test_connector_hdmi_init_bpc_12
[21:08:06] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[21:08:06] [PASSED] drm_test_connector_hdmi_init_bpc_null
[21:08:06] [PASSED] drm_test_connector_hdmi_init_formats_empty
[21:08:06] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[21:08:06] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[21:08:06] [PASSED] supported_formats=0x9 yuv420_allowed=1
[21:08:06] [PASSED] supported_formats=0x9 yuv420_allowed=0
[21:08:06] [PASSED] supported_formats=0x3 yuv420_allowed=1
[21:08:06] [PASSED] supported_formats=0x3 yuv420_allowed=0
[21:08:06] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[21:08:06] [PASSED] drm_test_connector_hdmi_init_null_ddc
[21:08:06] [PASSED] drm_test_connector_hdmi_init_null_product
[21:08:06] [PASSED] drm_test_connector_hdmi_init_null_vendor
[21:08:06] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[21:08:06] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[21:08:06] [PASSED] drm_test_connector_hdmi_init_product_valid
[21:08:06] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[21:08:06] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[21:08:06] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[21:08:06] ========= drm_test_connector_hdmi_init_type_valid =========
[21:08:06] [PASSED] HDMI-A
[21:08:06] [PASSED] HDMI-B
[21:08:06] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[21:08:06] ======== drm_test_connector_hdmi_init_type_invalid ========
[21:08:06] [PASSED] Unknown
[21:08:06] [PASSED] VGA
[21:08:06] [PASSED] DVI-I
[21:08:06] [PASSED] DVI-D
[21:08:06] [PASSED] DVI-A
[21:08:06] [PASSED] Composite
[21:08:06] [PASSED] SVIDEO
[21:08:06] [PASSED] LVDS
[21:08:06] [PASSED] Component
[21:08:06] [PASSED] DIN
[21:08:06] [PASSED] DP
[21:08:06] [PASSED] TV
[21:08:06] [PASSED] eDP
[21:08:06] [PASSED] Virtual
[21:08:06] [PASSED] DSI
[21:08:06] [PASSED] DPI
[21:08:06] [PASSED] Writeback
[21:08:06] [PASSED] SPI
[21:08:06] [PASSED] USB
[21:08:06] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[21:08:06] ============ [PASSED] drmm_connector_hdmi_init =============
[21:08:06] ============= drmm_connector_init (3 subtests) =============
[21:08:06] [PASSED] drm_test_drmm_connector_init
[21:08:06] [PASSED] drm_test_drmm_connector_init_null_ddc
[21:08:06] ========= drm_test_drmm_connector_init_type_valid =========
[21:08:06] [PASSED] Unknown
[21:08:06] [PASSED] VGA
[21:08:06] [PASSED] DVI-I
[21:08:06] [PASSED] DVI-D
[21:08:06] [PASSED] DVI-A
[21:08:06] [PASSED] Composite
[21:08:06] [PASSED] SVIDEO
[21:08:06] [PASSED] LVDS
[21:08:06] [PASSED] Component
[21:08:06] [PASSED] DIN
[21:08:06] [PASSED] DP
[21:08:06] [PASSED] HDMI-A
[21:08:06] [PASSED] HDMI-B
[21:08:06] [PASSED] TV
[21:08:06] [PASSED] eDP
[21:08:06] [PASSED] Virtual
[21:08:06] [PASSED] DSI
[21:08:06] [PASSED] DPI
[21:08:06] [PASSED] Writeback
[21:08:06] [PASSED] SPI
[21:08:06] [PASSED] USB
[21:08:06] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[21:08:06] =============== [PASSED] drmm_connector_init ===============
[21:08:06] ========= drm_connector_dynamic_init (6 subtests) ==========
[21:08:06] [PASSED] drm_test_drm_connector_dynamic_init
[21:08:06] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[21:08:06] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[21:08:06] [PASSED] drm_test_drm_connector_dynamic_init_properties
[21:08:06] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[21:08:06] [PASSED] Unknown
[21:08:06] [PASSED] VGA
[21:08:06] [PASSED] DVI-I
[21:08:06] [PASSED] DVI-D
[21:08:06] [PASSED] DVI-A
[21:08:06] [PASSED] Composite
[21:08:06] [PASSED] SVIDEO
[21:08:06] [PASSED] LVDS
[21:08:06] [PASSED] Component
[21:08:06] [PASSED] DIN
[21:08:06] [PASSED] DP
[21:08:06] [PASSED] HDMI-A
[21:08:06] [PASSED] HDMI-B
[21:08:06] [PASSED] TV
[21:08:06] [PASSED] eDP
[21:08:06] [PASSED] Virtual
[21:08:06] [PASSED] DSI
[21:08:06] [PASSED] DPI
[21:08:06] [PASSED] Writeback
[21:08:06] [PASSED] SPI
[21:08:06] [PASSED] USB
[21:08:06] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[21:08:06] ======== drm_test_drm_connector_dynamic_init_name =========
[21:08:06] [PASSED] Unknown
[21:08:06] [PASSED] VGA
[21:08:06] [PASSED] DVI-I
[21:08:06] [PASSED] DVI-D
[21:08:06] [PASSED] DVI-A
[21:08:06] [PASSED] Composite
[21:08:06] [PASSED] SVIDEO
[21:08:06] [PASSED] LVDS
[21:08:06] [PASSED] Component
[21:08:06] [PASSED] DIN
[21:08:06] [PASSED] DP
[21:08:06] [PASSED] HDMI-A
[21:08:06] [PASSED] HDMI-B
[21:08:06] [PASSED] TV
[21:08:06] [PASSED] eDP
[21:08:06] [PASSED] Virtual
[21:08:06] [PASSED] DSI
[21:08:06] [PASSED] DPI
[21:08:06] [PASSED] Writeback
[21:08:06] [PASSED] SPI
[21:08:06] [PASSED] USB
[21:08:06] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[21:08:06] =========== [PASSED] drm_connector_dynamic_init ============
[21:08:06] ==== drm_connector_dynamic_register_early (4 subtests) =====
[21:08:06] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[21:08:06] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[21:08:06] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[21:08:06] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[21:08:06] ====== [PASSED] drm_connector_dynamic_register_early =======
[21:08:06] ======= drm_connector_dynamic_register (7 subtests) ========
[21:08:06] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[21:08:06] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[21:08:06] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[21:08:06] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[21:08:06] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[21:08:06] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[21:08:06] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[21:08:06] ========= [PASSED] drm_connector_dynamic_register ==========
[21:08:06] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[21:08:06] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[21:08:06] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[21:08:06] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[21:08:06] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[21:08:06] ========== drm_test_get_tv_mode_from_name_valid ===========
[21:08:06] [PASSED] NTSC
[21:08:06] [PASSED] NTSC-443
[21:08:06] [PASSED] NTSC-J
[21:08:06] [PASSED] PAL
[21:08:06] [PASSED] PAL-M
[21:08:06] [PASSED] PAL-N
[21:08:06] [PASSED] SECAM
[21:08:06] [PASSED] Mono
[21:08:06] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[21:08:06] [PASSED] drm_test_get_tv_mode_from_name_truncated
[21:08:06] ============ [PASSED] drm_get_tv_mode_from_name ============
[21:08:06] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[21:08:06] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[21:08:06] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[21:08:06] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[21:08:06] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[21:08:06] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[21:08:06] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[21:08:06] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[21:08:06] [PASSED] VIC 96
[21:08:06] [PASSED] VIC 97
[21:08:06] [PASSED] VIC 101
[21:08:06] [PASSED] VIC 102
[21:08:06] [PASSED] VIC 106
[21:08:06] [PASSED] VIC 107
[21:08:06] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[21:08:06] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[21:08:06] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[21:08:06] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[21:08:06] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[21:08:06] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[21:08:06] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[21:08:06] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[21:08:06] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[21:08:06] [PASSED] Automatic
[21:08:06] [PASSED] Full
[21:08:06] [PASSED] Limited 16:235
[21:08:06] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[21:08:06] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[21:08:06] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[21:08:06] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[21:08:06] === drm_test_drm_hdmi_connector_get_output_format_name ====
[21:08:06] [PASSED] RGB
[21:08:06] [PASSED] YUV 4:2:0
[21:08:06] [PASSED] YUV 4:2:2
[21:08:06] [PASSED] YUV 4:4:4
[21:08:06] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[21:08:06] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[21:08:06] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[21:08:06] ============= drm_damage_helper (21 subtests) ==============
[21:08:06] [PASSED] drm_test_damage_iter_no_damage
[21:08:06] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[21:08:06] [PASSED] drm_test_damage_iter_no_damage_src_moved
[21:08:06] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[21:08:06] [PASSED] drm_test_damage_iter_no_damage_not_visible
[21:08:06] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[21:08:06] [PASSED] drm_test_damage_iter_no_damage_no_fb
[21:08:06] [PASSED] drm_test_damage_iter_simple_damage
[21:08:06] [PASSED] drm_test_damage_iter_single_damage
[21:08:06] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[21:08:06] [PASSED] drm_test_damage_iter_single_damage_outside_src
[21:08:06] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[21:08:06] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[21:08:06] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[21:08:06] [PASSED] drm_test_damage_iter_single_damage_src_moved
[21:08:06] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[21:08:06] [PASSED] drm_test_damage_iter_damage
[21:08:06] [PASSED] drm_test_damage_iter_damage_one_intersect
[21:08:06] [PASSED] drm_test_damage_iter_damage_one_outside
[21:08:06] [PASSED] drm_test_damage_iter_damage_src_moved
[21:08:06] [PASSED] drm_test_damage_iter_damage_not_visible
[21:08:06] ================ [PASSED] drm_damage_helper ================
[21:08:06] ============== drm_dp_mst_helper (3 subtests) ==============
[21:08:06] ============== drm_test_dp_mst_calc_pbn_mode ==============
[21:08:06] [PASSED] Clock 154000 BPP 30 DSC disabled
[21:08:06] [PASSED] Clock 234000 BPP 30 DSC disabled
[21:08:06] [PASSED] Clock 297000 BPP 24 DSC disabled
[21:08:06] [PASSED] Clock 332880 BPP 24 DSC enabled
[21:08:06] [PASSED] Clock 324540 BPP 24 DSC enabled
[21:08:06] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[21:08:06] ============== drm_test_dp_mst_calc_pbn_div ===============
[21:08:06] [PASSED] Link rate 2000000 lane count 4
[21:08:06] [PASSED] Link rate 2000000 lane count 2
[21:08:06] [PASSED] Link rate 2000000 lane count 1
[21:08:06] [PASSED] Link rate 1350000 lane count 4
[21:08:06] [PASSED] Link rate 1350000 lane count 2
[21:08:06] [PASSED] Link rate 1350000 lane count 1
[21:08:06] [PASSED] Link rate 1000000 lane count 4
[21:08:06] [PASSED] Link rate 1000000 lane count 2
[21:08:06] [PASSED] Link rate 1000000 lane count 1
[21:08:06] [PASSED] Link rate 810000 lane count 4
[21:08:06] [PASSED] Link rate 810000 lane count 2
[21:08:06] [PASSED] Link rate 810000 lane count 1
[21:08:06] [PASSED] Link rate 540000 lane count 4
[21:08:06] [PASSED] Link rate 540000 lane count 2
[21:08:06] [PASSED] Link rate 540000 lane count 1
[21:08:06] [PASSED] Link rate 270000 lane count 4
[21:08:06] [PASSED] Link rate 270000 lane count 2
[21:08:06] [PASSED] Link rate 270000 lane count 1
[21:08:06] [PASSED] Link rate 162000 lane count 4
[21:08:06] [PASSED] Link rate 162000 lane count 2
[21:08:06] [PASSED] Link rate 162000 lane count 1
[21:08:06] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[21:08:06] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[21:08:06] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[21:08:06] [PASSED] DP_POWER_UP_PHY with port number
[21:08:06] [PASSED] DP_POWER_DOWN_PHY with port number
[21:08:06] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[21:08:06] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[21:08:06] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[21:08:06] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[21:08:06] [PASSED] DP_QUERY_PAYLOAD with port number
[21:08:06] [PASSED] DP_QUERY_PAYLOAD with VCPI
[21:08:06] [PASSED] DP_REMOTE_DPCD_READ with port number
[21:08:06] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[21:08:06] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[21:08:06] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[21:08:06] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[21:08:06] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[21:08:06] [PASSED] DP_REMOTE_I2C_READ with port number
[21:08:06] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[21:08:06] [PASSED] DP_REMOTE_I2C_READ with transactions array
[21:08:06] [PASSED] DP_REMOTE_I2C_WRITE with port number
[21:08:06] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[21:08:06] [PASSED] DP_REMOTE_I2C_WRITE with data array
[21:08:06] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[21:08:06] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[21:08:06] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[21:08:06] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[21:08:06] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[21:08:06] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[21:08:06] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[21:08:06] ================ [PASSED] drm_dp_mst_helper ================
[21:08:06] ================== drm_exec (7 subtests) ===================
[21:08:06] [PASSED] sanitycheck
[21:08:06] [PASSED] test_lock
[21:08:06] [PASSED] test_lock_unlock
[21:08:06] [PASSED] test_duplicates
[21:08:06] [PASSED] test_prepare
[21:08:06] [PASSED] test_prepare_array
[21:08:06] [PASSED] test_multiple_loops
[21:08:06] ==================== [PASSED] drm_exec =====================
[21:08:06] =========== drm_format_helper_test (17 subtests) ===========
[21:08:06] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[21:08:06] [PASSED] single_pixel_source_buffer
[21:08:06] [PASSED] single_pixel_clip_rectangle
[21:08:06] [PASSED] well_known_colors
[21:08:06] [PASSED] destination_pitch
[21:08:06] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[21:08:06] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[21:08:06] [PASSED] single_pixel_source_buffer
[21:08:06] [PASSED] single_pixel_clip_rectangle
[21:08:06] [PASSED] well_known_colors
[21:08:06] [PASSED] destination_pitch
[21:08:06] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[21:08:06] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[21:08:06] [PASSED] single_pixel_source_buffer
[21:08:06] [PASSED] single_pixel_clip_rectangle
[21:08:06] [PASSED] well_known_colors
[21:08:06] [PASSED] destination_pitch
[21:08:06] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[21:08:06] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[21:08:06] [PASSED] single_pixel_source_buffer
[21:08:06] [PASSED] single_pixel_clip_rectangle
[21:08:06] [PASSED] well_known_colors
[21:08:06] [PASSED] destination_pitch
[21:08:06] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[21:08:06] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[21:08:06] [PASSED] single_pixel_source_buffer
[21:08:06] [PASSED] single_pixel_clip_rectangle
[21:08:06] [PASSED] well_known_colors
[21:08:06] [PASSED] destination_pitch
[21:08:06] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[21:08:06] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[21:08:06] [PASSED] single_pixel_source_buffer
[21:08:06] [PASSED] single_pixel_clip_rectangle
[21:08:06] [PASSED] well_known_colors
[21:08:06] [PASSED] destination_pitch
[21:08:06] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[21:08:06] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[21:08:06] [PASSED] single_pixel_source_buffer
[21:08:06] [PASSED] single_pixel_clip_rectangle
[21:08:06] [PASSED] well_known_colors
[21:08:06] [PASSED] destination_pitch
[21:08:06] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[21:08:06] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[21:08:06] [PASSED] single_pixel_source_buffer
[21:08:06] [PASSED] single_pixel_clip_rectangle
[21:08:06] [PASSED] well_known_colors
[21:08:06] [PASSED] destination_pitch
[21:08:06] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[21:08:06] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[21:08:06] [PASSED] single_pixel_source_buffer
[21:08:06] [PASSED] single_pixel_clip_rectangle
[21:08:06] [PASSED] well_known_colors
[21:08:06] [PASSED] destination_pitch
[21:08:06] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[21:08:06] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[21:08:06] [PASSED] single_pixel_source_buffer
[21:08:06] [PASSED] single_pixel_clip_rectangle
[21:08:06] [PASSED] well_known_colors
[21:08:06] [PASSED] destination_pitch
[21:08:06] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[21:08:06] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[21:08:06] [PASSED] single_pixel_source_buffer
[21:08:06] [PASSED] single_pixel_clip_rectangle
[21:08:06] [PASSED] well_known_colors
[21:08:06] [PASSED] destination_pitch
[21:08:06] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[21:08:06] ============== drm_test_fb_xrgb8888_to_mono ===============
[21:08:06] [PASSED] single_pixel_source_buffer
[21:08:06] [PASSED] single_pixel_clip_rectangle
[21:08:06] [PASSED] well_known_colors
[21:08:06] [PASSED] destination_pitch
[21:08:06] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[21:08:06] ==================== drm_test_fb_swab =====================
[21:08:06] [PASSED] single_pixel_source_buffer
[21:08:06] [PASSED] single_pixel_clip_rectangle
[21:08:06] [PASSED] well_known_colors
[21:08:06] [PASSED] destination_pitch
[21:08:06] ================ [PASSED] drm_test_fb_swab =================
[21:08:06] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[21:08:06] [PASSED] single_pixel_source_buffer
[21:08:06] [PASSED] single_pixel_clip_rectangle
[21:08:06] [PASSED] well_known_colors
[21:08:06] [PASSED] destination_pitch
[21:08:06] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[21:08:06] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[21:08:06] [PASSED] single_pixel_source_buffer
[21:08:06] [PASSED] single_pixel_clip_rectangle
[21:08:06] [PASSED] well_known_colors
[21:08:06] [PASSED] destination_pitch
[21:08:06] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[21:08:06] ================= drm_test_fb_clip_offset =================
[21:08:06] [PASSED] pass through
[21:08:06] [PASSED] horizontal offset
[21:08:06] [PASSED] vertical offset
[21:08:06] [PASSED] horizontal and vertical offset
[21:08:06] [PASSED] horizontal offset (custom pitch)
[21:08:06] [PASSED] vertical offset (custom pitch)
[21:08:06] [PASSED] horizontal and vertical offset (custom pitch)
[21:08:06] ============= [PASSED] drm_test_fb_clip_offset =============
[21:08:06] =================== drm_test_fb_memcpy ====================
[21:08:06] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[21:08:06] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[21:08:06] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[21:08:06] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[21:08:06] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[21:08:06] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[21:08:06] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[21:08:06] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[21:08:06] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[21:08:06] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[21:08:06] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[21:08:06] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[21:08:06] =============== [PASSED] drm_test_fb_memcpy ================
[21:08:06] ============= [PASSED] drm_format_helper_test ==============
[21:08:06] ================= drm_format (18 subtests) =================
[21:08:06] [PASSED] drm_test_format_block_width_invalid
[21:08:06] [PASSED] drm_test_format_block_width_one_plane
[21:08:06] [PASSED] drm_test_format_block_width_two_plane
[21:08:06] [PASSED] drm_test_format_block_width_three_plane
[21:08:06] [PASSED] drm_test_format_block_width_tiled
[21:08:06] [PASSED] drm_test_format_block_height_invalid
[21:08:06] [PASSED] drm_test_format_block_height_one_plane
[21:08:06] [PASSED] drm_test_format_block_height_two_plane
[21:08:06] [PASSED] drm_test_format_block_height_three_plane
[21:08:06] [PASSED] drm_test_format_block_height_tiled
[21:08:06] [PASSED] drm_test_format_min_pitch_invalid
[21:08:06] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[21:08:06] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[21:08:06] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[21:08:06] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[21:08:06] [PASSED] drm_test_format_min_pitch_two_plane
[21:08:06] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[21:08:06] [PASSED] drm_test_format_min_pitch_tiled
[21:08:06] =================== [PASSED] drm_format ====================
[21:08:06] ============== drm_framebuffer (10 subtests) ===============
[21:08:06] ========== drm_test_framebuffer_check_src_coords ==========
[21:08:06] [PASSED] Success: source fits into fb
[21:08:06] [PASSED] Fail: overflowing fb with x-axis coordinate
[21:08:06] [PASSED] Fail: overflowing fb with y-axis coordinate
[21:08:06] [PASSED] Fail: overflowing fb with source width
[21:08:06] [PASSED] Fail: overflowing fb with source height
[21:08:06] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[21:08:06] [PASSED] drm_test_framebuffer_cleanup
[21:08:06] =============== drm_test_framebuffer_create ===============
[21:08:06] [PASSED] ABGR8888 normal sizes
[21:08:06] [PASSED] ABGR8888 max sizes
[21:08:06] [PASSED] ABGR8888 pitch greater than min required
[21:08:06] [PASSED] ABGR8888 pitch less than min required
[21:08:06] [PASSED] ABGR8888 Invalid width
[21:08:06] [PASSED] ABGR8888 Invalid buffer handle
[21:08:06] [PASSED] No pixel format
[21:08:06] [PASSED] ABGR8888 Width 0
[21:08:06] [PASSED] ABGR8888 Height 0
[21:08:06] [PASSED] ABGR8888 Out of bound height * pitch combination
[21:08:06] [PASSED] ABGR8888 Large buffer offset
[21:08:06] [PASSED] ABGR8888 Buffer offset for inexistent plane
[21:08:06] [PASSED] ABGR8888 Invalid flag
[21:08:06] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[21:08:06] [PASSED] ABGR8888 Valid buffer modifier
[21:08:06] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[21:08:06] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[21:08:06] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[21:08:06] [PASSED] NV12 Normal sizes
[21:08:06] [PASSED] NV12 Max sizes
[21:08:06] [PASSED] NV12 Invalid pitch
[21:08:06] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[21:08:06] [PASSED] NV12 different modifier per-plane
[21:08:06] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[21:08:06] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[21:08:06] [PASSED] NV12 Modifier for inexistent plane
[21:08:06] [PASSED] NV12 Handle for inexistent plane
[21:08:06] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[21:08:06] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[21:08:06] [PASSED] YVU420 Normal sizes
[21:08:06] [PASSED] YVU420 Max sizes
[21:08:06] [PASSED] YVU420 Invalid pitch
[21:08:06] [PASSED] YVU420 Different pitches
[21:08:06] [PASSED] YVU420 Different buffer offsets/pitches
[21:08:06] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[21:08:06] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[21:08:06] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[21:08:06] [PASSED] YVU420 Valid modifier
[21:08:06] [PASSED] YVU420 Different modifiers per plane
[21:08:06] [PASSED] YVU420 Modifier for inexistent plane
[21:08:06] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[21:08:06] [PASSED] X0L2 Normal sizes
[21:08:06] [PASSED] X0L2 Max sizes
[21:08:06] [PASSED] X0L2 Invalid pitch
[21:08:06] [PASSED] X0L2 Pitch greater than minimum required
[21:08:06] [PASSED] X0L2 Handle for inexistent plane
[21:08:06] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[21:08:06] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[21:08:06] [PASSED] X0L2 Valid modifier
[21:08:06] [PASSED] X0L2 Modifier for inexistent plane
[21:08:06] =========== [PASSED] drm_test_framebuffer_create ===========
[21:08:06] [PASSED] drm_test_framebuffer_free
[21:08:06] [PASSED] drm_test_framebuffer_init
[21:08:06] [PASSED] drm_test_framebuffer_init_bad_format
[21:08:06] [PASSED] drm_test_framebuffer_init_dev_mismatch
[21:08:06] [PASSED] drm_test_framebuffer_lookup
[21:08:06] [PASSED] drm_test_framebuffer_lookup_inexistent
[21:08:06] [PASSED] drm_test_framebuffer_modifiers_not_supported
[21:08:06] ================= [PASSED] drm_framebuffer =================
[21:08:06] ================ drm_gem_shmem (8 subtests) ================
[21:08:06] [PASSED] drm_gem_shmem_test_obj_create
[21:08:06] [PASSED] drm_gem_shmem_test_obj_create_private
[21:08:06] [PASSED] drm_gem_shmem_test_pin_pages
[21:08:06] [PASSED] drm_gem_shmem_test_vmap
[21:08:06] [PASSED] drm_gem_shmem_test_get_sg_table
[21:08:06] [PASSED] drm_gem_shmem_test_get_pages_sgt
[21:08:06] [PASSED] drm_gem_shmem_test_madvise
[21:08:06] [PASSED] drm_gem_shmem_test_purge
[21:08:06] ================== [PASSED] drm_gem_shmem ==================
[21:08:06] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[21:08:06] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[21:08:06] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[21:08:06] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[21:08:06] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[21:08:06] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[21:08:06] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[21:08:06] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[21:08:06] [PASSED] Automatic
[21:08:06] [PASSED] Full
[21:08:06] [PASSED] Limited 16:235
[21:08:06] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[21:08:06] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[21:08:06] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[21:08:06] [PASSED] drm_test_check_disable_connector
[21:08:06] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[21:08:06] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[21:08:06] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[21:08:06] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[21:08:06] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[21:08:06] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[21:08:06] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[21:08:06] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[21:08:06] [PASSED] drm_test_check_output_bpc_dvi
[21:08:06] [PASSED] drm_test_check_output_bpc_format_vic_1
[21:08:06] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[21:08:06] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[21:08:06] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[21:08:06] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[21:08:06] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[21:08:06] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[21:08:06] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[21:08:06] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[21:08:06] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[21:08:06] [PASSED] drm_test_check_broadcast_rgb_value
[21:08:06] [PASSED] drm_test_check_bpc_8_value
[21:08:06] [PASSED] drm_test_check_bpc_10_value
[21:08:06] [PASSED] drm_test_check_bpc_12_value
[21:08:06] [PASSED] drm_test_check_format_value
[21:08:06] [PASSED] drm_test_check_tmds_char_value
[21:08:06] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[21:08:06] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[21:08:06] [PASSED] drm_test_check_mode_valid
[21:08:06] [PASSED] drm_test_check_mode_valid_reject
[21:08:06] [PASSED] drm_test_check_mode_valid_reject_rate
[21:08:06] [PASSED] drm_test_check_mode_valid_reject_max_clock
[21:08:06] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[21:08:06] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[21:08:06] [PASSED] drm_test_check_infoframes
[21:08:06] [PASSED] drm_test_check_reject_avi_infoframe
[21:08:06] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[21:08:06] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[21:08:06] [PASSED] drm_test_check_reject_audio_infoframe
[21:08:06] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[21:08:06] ================= drm_managed (2 subtests) =================
[21:08:06] [PASSED] drm_test_managed_release_action
[21:08:06] [PASSED] drm_test_managed_run_action
[21:08:06] =================== [PASSED] drm_managed ===================
[21:08:06] =================== drm_mm (6 subtests) ====================
[21:08:06] [PASSED] drm_test_mm_init
[21:08:06] [PASSED] drm_test_mm_debug
[21:08:06] [PASSED] drm_test_mm_align32
[21:08:06] [PASSED] drm_test_mm_align64
[21:08:06] [PASSED] drm_test_mm_lowest
[21:08:06] [PASSED] drm_test_mm_highest
[21:08:06] ===================== [PASSED] drm_mm ======================
[21:08:06] ============= drm_modes_analog_tv (5 subtests) =============
[21:08:06] [PASSED] drm_test_modes_analog_tv_mono_576i
[21:08:06] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[21:08:06] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[21:08:06] [PASSED] drm_test_modes_analog_tv_pal_576i
[21:08:06] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[21:08:06] =============== [PASSED] drm_modes_analog_tv ===============
[21:08:06] ============== drm_plane_helper (2 subtests) ===============
[21:08:06] =============== drm_test_check_plane_state ================
[21:08:06] [PASSED] clipping_simple
[21:08:06] [PASSED] clipping_rotate_reflect
[21:08:06] [PASSED] positioning_simple
[21:08:06] [PASSED] upscaling
[21:08:06] [PASSED] downscaling
[21:08:06] [PASSED] rounding1
[21:08:06] [PASSED] rounding2
[21:08:06] [PASSED] rounding3
[21:08:06] [PASSED] rounding4
[21:08:06] =========== [PASSED] drm_test_check_plane_state ============
[21:08:06] =========== drm_test_check_invalid_plane_state ============
[21:08:06] [PASSED] positioning_invalid
[21:08:06] [PASSED] upscaling_invalid
[21:08:06] [PASSED] downscaling_invalid
[21:08:06] ======= [PASSED] drm_test_check_invalid_plane_state ========
[21:08:06] ================ [PASSED] drm_plane_helper =================
[21:08:06] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[21:08:06] ====== drm_test_connector_helper_tv_get_modes_check =======
[21:08:06] [PASSED] None
[21:08:06] [PASSED] PAL
[21:08:06] [PASSED] NTSC
[21:08:06] [PASSED] Both, NTSC Default
[21:08:06] [PASSED] Both, PAL Default
[21:08:06] [PASSED] Both, NTSC Default, with PAL on command-line
[21:08:06] [PASSED] Both, PAL Default, with NTSC on command-line
[21:08:06] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[21:08:06] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[21:08:06] ================== drm_rect (9 subtests) ===================
[21:08:06] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[21:08:06] [PASSED] drm_test_rect_clip_scaled_not_clipped
[21:08:06] [PASSED] drm_test_rect_clip_scaled_clipped
[21:08:06] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[21:08:06] ================= drm_test_rect_intersect =================
[21:08:06] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[21:08:06] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[21:08:06] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[21:08:06] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[21:08:06] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[21:08:06] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[21:08:06] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[21:08:06] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[21:08:06] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[21:08:06] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[21:08:06] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[21:08:06] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[21:08:06] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[21:08:06] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[21:08:06] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
stty: 'standard input': Inappropriate ioctl for device
[21:08:06] ============= [PASSED] drm_test_rect_intersect =============
[21:08:06] ================ drm_test_rect_calc_hscale ================
[21:08:06] [PASSED] normal use
[21:08:06] [PASSED] out of max range
[21:08:06] [PASSED] out of min range
[21:08:06] [PASSED] zero dst
[21:08:06] [PASSED] negative src
[21:08:06] [PASSED] negative dst
[21:08:06] ============ [PASSED] drm_test_rect_calc_hscale ============
[21:08:06] ================ drm_test_rect_calc_vscale ================
[21:08:06] [PASSED] normal use
[21:08:06] [PASSED] out of max range
[21:08:06] [PASSED] out of min range
[21:08:06] [PASSED] zero dst
[21:08:06] [PASSED] negative src
[21:08:06] [PASSED] negative dst
[21:08:06] ============ [PASSED] drm_test_rect_calc_vscale ============
[21:08:06] ================== drm_test_rect_rotate ===================
[21:08:06] [PASSED] reflect-x
[21:08:06] [PASSED] reflect-y
[21:08:06] [PASSED] rotate-0
[21:08:06] [PASSED] rotate-90
[21:08:06] [PASSED] rotate-180
[21:08:06] [PASSED] rotate-270
[21:08:06] ============== [PASSED] drm_test_rect_rotate ===============
[21:08:06] ================ drm_test_rect_rotate_inv =================
[21:08:06] [PASSED] reflect-x
[21:08:06] [PASSED] reflect-y
[21:08:06] [PASSED] rotate-0
[21:08:06] [PASSED] rotate-90
[21:08:06] [PASSED] rotate-180
[21:08:06] [PASSED] rotate-270
[21:08:06] ============ [PASSED] drm_test_rect_rotate_inv =============
[21:08:06] ==================== [PASSED] drm_rect =====================
[21:08:06] ============ drm_sysfb_modeset_test (1 subtest) ============
[21:08:06] ============ drm_test_sysfb_build_fourcc_list =============
[21:08:06] [PASSED] no native formats
[21:08:06] [PASSED] XRGB8888 as native format
[21:08:06] [PASSED] remove duplicates
[21:08:06] [PASSED] convert alpha formats
[21:08:06] [PASSED] random formats
[21:08:06] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[21:08:06] ============= [PASSED] drm_sysfb_modeset_test ==============
[21:08:06] ================== drm_fixp (2 subtests) ===================
[21:08:06] [PASSED] drm_test_int2fixp
[21:08:06] [PASSED] drm_test_sm2fixp
[21:08:06] ==================== [PASSED] drm_fixp =====================
[21:08:06] ============================================================
[21:08:06] Testing complete. Ran 630 tests: passed: 630
[21:08:07] Elapsed time: 32.469s total, 1.629s configuring, 30.373s building, 0.411s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[21:08:07] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:08:08] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[21:08:18] Starting KUnit Kernel (1/1)...
[21:08:18] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:08:18] ================= ttm_device (5 subtests) ==================
[21:08:18] [PASSED] ttm_device_init_basic
[21:08:18] [PASSED] ttm_device_init_multiple
[21:08:18] [PASSED] ttm_device_fini_basic
[21:08:18] [PASSED] ttm_device_init_no_vma_man
[21:08:18] ================== ttm_device_init_pools ==================
[21:08:18] [PASSED] No DMA allocations, no DMA32 required
[21:08:18] [PASSED] DMA allocations, DMA32 required
[21:08:18] [PASSED] No DMA allocations, DMA32 required
[21:08:18] [PASSED] DMA allocations, no DMA32 required
[21:08:18] ============== [PASSED] ttm_device_init_pools ==============
[21:08:18] =================== [PASSED] ttm_device ====================
[21:08:18] ================== ttm_pool (8 subtests) ===================
[21:08:18] ================== ttm_pool_alloc_basic ===================
[21:08:18] [PASSED] One page
[21:08:18] [PASSED] More than one page
[21:08:18] [PASSED] Above the allocation limit
[21:08:18] [PASSED] One page, with coherent DMA mappings enabled
[21:08:18] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[21:08:18] ============== [PASSED] ttm_pool_alloc_basic ===============
[21:08:18] ============== ttm_pool_alloc_basic_dma_addr ==============
[21:08:18] [PASSED] One page
[21:08:18] [PASSED] More than one page
[21:08:18] [PASSED] Above the allocation limit
[21:08:18] [PASSED] One page, with coherent DMA mappings enabled
[21:08:18] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[21:08:18] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[21:08:18] [PASSED] ttm_pool_alloc_order_caching_match
[21:08:18] [PASSED] ttm_pool_alloc_caching_mismatch
[21:08:18] [PASSED] ttm_pool_alloc_order_mismatch
[21:08:18] [PASSED] ttm_pool_free_dma_alloc
[21:08:18] [PASSED] ttm_pool_free_no_dma_alloc
[21:08:18] [PASSED] ttm_pool_fini_basic
[21:08:18] ==================== [PASSED] ttm_pool =====================
[21:08:18] ================ ttm_resource (8 subtests) =================
[21:08:18] ================= ttm_resource_init_basic =================
[21:08:18] [PASSED] Init resource in TTM_PL_SYSTEM
[21:08:18] [PASSED] Init resource in TTM_PL_VRAM
[21:08:18] [PASSED] Init resource in a private placement
[21:08:18] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[21:08:18] ============= [PASSED] ttm_resource_init_basic =============
[21:08:18] [PASSED] ttm_resource_init_pinned
[21:08:18] [PASSED] ttm_resource_fini_basic
[21:08:18] [PASSED] ttm_resource_manager_init_basic
[21:08:18] [PASSED] ttm_resource_manager_usage_basic
[21:08:18] [PASSED] ttm_resource_manager_set_used_basic
[21:08:18] [PASSED] ttm_sys_man_alloc_basic
[21:08:18] [PASSED] ttm_sys_man_free_basic
[21:08:18] ================== [PASSED] ttm_resource ===================
[21:08:18] =================== ttm_tt (15 subtests) ===================
[21:08:18] ==================== ttm_tt_init_basic ====================
[21:08:18] [PASSED] Page-aligned size
[21:08:18] [PASSED] Extra pages requested
[21:08:18] ================ [PASSED] ttm_tt_init_basic ================
[21:08:18] [PASSED] ttm_tt_init_misaligned
[21:08:18] [PASSED] ttm_tt_fini_basic
[21:08:18] [PASSED] ttm_tt_fini_sg
[21:08:18] [PASSED] ttm_tt_fini_shmem
[21:08:18] [PASSED] ttm_tt_create_basic
[21:08:18] [PASSED] ttm_tt_create_invalid_bo_type
[21:08:18] [PASSED] ttm_tt_create_ttm_exists
[21:08:18] [PASSED] ttm_tt_create_failed
[21:08:18] [PASSED] ttm_tt_destroy_basic
[21:08:18] [PASSED] ttm_tt_populate_null_ttm
[21:08:18] [PASSED] ttm_tt_populate_populated_ttm
[21:08:18] [PASSED] ttm_tt_unpopulate_basic
[21:08:18] [PASSED] ttm_tt_unpopulate_empty_ttm
[21:08:18] [PASSED] ttm_tt_swapin_basic
[21:08:18] ===================== [PASSED] ttm_tt ======================
[21:08:18] =================== ttm_bo (14 subtests) ===================
[21:08:18] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[21:08:18] [PASSED] Cannot be interrupted and sleeps
[21:08:18] [PASSED] Cannot be interrupted, locks straight away
[21:08:18] [PASSED] Can be interrupted, sleeps
[21:08:18] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[21:08:18] [PASSED] ttm_bo_reserve_locked_no_sleep
[21:08:18] [PASSED] ttm_bo_reserve_no_wait_ticket
[21:08:18] [PASSED] ttm_bo_reserve_double_resv
[21:08:18] [PASSED] ttm_bo_reserve_interrupted
[21:08:18] [PASSED] ttm_bo_reserve_deadlock
[21:08:18] [PASSED] ttm_bo_unreserve_basic
[21:08:18] [PASSED] ttm_bo_unreserve_pinned
[21:08:18] [PASSED] ttm_bo_unreserve_bulk
[21:08:18] [PASSED] ttm_bo_fini_basic
[21:08:18] [PASSED] ttm_bo_fini_shared_resv
[21:08:18] [PASSED] ttm_bo_pin_basic
[21:08:18] [PASSED] ttm_bo_pin_unpin_resource
[21:08:18] [PASSED] ttm_bo_multiple_pin_one_unpin
[21:08:18] ===================== [PASSED] ttm_bo ======================
[21:08:18] ============== ttm_bo_validate (21 subtests) ===============
[21:08:18] ============== ttm_bo_init_reserved_sys_man ===============
[21:08:18] [PASSED] Buffer object for userspace
[21:08:18] [PASSED] Kernel buffer object
[21:08:18] [PASSED] Shared buffer object
[21:08:18] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[21:08:18] ============== ttm_bo_init_reserved_mock_man ==============
[21:08:18] [PASSED] Buffer object for userspace
[21:08:18] [PASSED] Kernel buffer object
[21:08:18] [PASSED] Shared buffer object
[21:08:18] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[21:08:18] [PASSED] ttm_bo_init_reserved_resv
[21:08:18] ================== ttm_bo_validate_basic ==================
[21:08:18] [PASSED] Buffer object for userspace
[21:08:18] [PASSED] Kernel buffer object
[21:08:18] [PASSED] Shared buffer object
[21:08:18] ============== [PASSED] ttm_bo_validate_basic ==============
[21:08:18] [PASSED] ttm_bo_validate_invalid_placement
[21:08:18] ============= ttm_bo_validate_same_placement ==============
[21:08:18] [PASSED] System manager
[21:08:18] [PASSED] VRAM manager
[21:08:18] ========= [PASSED] ttm_bo_validate_same_placement ==========
[21:08:18] [PASSED] ttm_bo_validate_failed_alloc
[21:08:18] [PASSED] ttm_bo_validate_pinned
[21:08:18] [PASSED] ttm_bo_validate_busy_placement
[21:08:18] ================ ttm_bo_validate_multihop =================
[21:08:18] [PASSED] Buffer object for userspace
[21:08:18] [PASSED] Kernel buffer object
[21:08:18] [PASSED] Shared buffer object
[21:08:18] ============ [PASSED] ttm_bo_validate_multihop =============
[21:08:18] ========== ttm_bo_validate_no_placement_signaled ==========
[21:08:18] [PASSED] Buffer object in system domain, no page vector
[21:08:18] [PASSED] Buffer object in system domain with an existing page vector
[21:08:18] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[21:08:18] ======== ttm_bo_validate_no_placement_not_signaled ========
[21:08:18] [PASSED] Buffer object for userspace
[21:08:18] [PASSED] Kernel buffer object
[21:08:18] [PASSED] Shared buffer object
[21:08:18] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[21:08:18] [PASSED] ttm_bo_validate_move_fence_signaled
[21:08:18] ========= ttm_bo_validate_move_fence_not_signaled =========
[21:08:18] [PASSED] Waits for GPU
[21:08:18] [PASSED] Tries to lock straight away
[21:08:18] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[21:08:18] [PASSED] ttm_bo_validate_happy_evict
[21:08:18] [PASSED] ttm_bo_validate_all_pinned_evict
[21:08:18] [PASSED] ttm_bo_validate_allowed_only_evict
[21:08:18] [PASSED] ttm_bo_validate_deleted_evict
[21:08:18] [PASSED] ttm_bo_validate_busy_domain_evict
[21:08:18] [PASSED] ttm_bo_validate_evict_gutting
[21:08:18] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[21:08:18] ================= [PASSED] ttm_bo_validate =================
[21:08:18] ============================================================
[21:08:18] Testing complete. Ran 101 tests: passed: 101
[21:08:18] Elapsed time: 11.619s total, 1.635s configuring, 9.767s building, 0.176s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 43+ messages in thread
* [v3 00/19] Make Display free from i915_reg.h
@ 2026-01-29 21:13 Uma Shankar
2026-01-29 21:07 ` ✗ CI.checkpatch: warning for Make Display free from i915_reg.h (rev3) Patchwork
` (22 more replies)
0 siblings, 23 replies; 43+ messages in thread
From: Uma Shankar @ 2026-01-29 21:13 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, ville.syrjala, Uma Shankar
Move the common register definition to per feature header
which makes display files free from including i915_reg.h.
This will help avoid dupicate definitions and includes and can
serve as a common file for xe, i915 and display module.
v3:
- Create per feature modular headers instead of 1 common header (Jani)
- Commit message and header fixes (Jani)
v2:
- Moved display definitions needed for gvt and clock gating
to display header (Jani)
- Fixed redundant includes
Uma Shankar (19):
drm/i915: Extract display registers from i915_reg.h to display
drm/i915: Extract South chicken registers from i915_reg.h to display
drm/i915: Extract display interrupt definitions
drm/i915: Extract DSPCLK_GATE_D from i915_reg to display
drm/{i915, xe}: Extract pcode definitions to common header
drm/i915: Remove i915_reg.h from intel_display_device.c
drm/i915: Remove i915_reg.h from intel_dram.c
drm/i915: Remove i915_reg.h from intel_display.c
drm/i915: Remove i915_reg.h from intel_overlay.c
drm/i915: Remove i915_reg.h from g4x_dp.c
drm/i915: Remove i915_reg.h from i9xx_wm.c
drm/{i915, xe}: Remove i915_reg.h from g4x_hdmi.c
drm/i915: Remove i915_reg.h from intel_rom.c
drm/i915: Remove i915_reg.h from intel_psr.c
drm/i915: Remove i915_reg.h from intel_fifo_underrun.c
drm/i915: Remove i915_reg.h from intel_display_irq.c
drm/i915: Remove i915_reg.h from intel_display_power_well.c
drm/i915: Remove i915_reg.h from intel_modeset_setup.c
drm/{i915, xe}: Remove i915_reg.h from display
drivers/gpu/drm/i915/display/g4x_dp.c | 2 +-
drivers/gpu/drm/i915/display/g4x_hdmi.c | 1 -
drivers/gpu/drm/i915/display/hsw_ips.c | 2 +-
drivers/gpu/drm/i915/display/i9xx_plane.c | 1 -
drivers/gpu/drm/i915/display/i9xx_wm.c | 2 +-
drivers/gpu/drm/i915/display/icl_dsi.c | 1 -
.../gpu/drm/i915/display/intel_backlight.c | 1 -
drivers/gpu/drm/i915/display/intel_bw.c | 2 +-
drivers/gpu/drm/i915/display/intel_casf.c | 1 -
drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 1 -
drivers/gpu/drm/i915/display/intel_display.c | 1 -
.../drm/i915/display/intel_display_debugfs.c | 1 -
.../drm/i915/display/intel_display_device.c | 7 +-
.../gpu/drm/i915/display/intel_display_irq.c | 2 +-
.../drm/i915/display/intel_display_power.c | 2 +-
.../i915/display/intel_display_power_well.c | 2 +-
.../gpu/drm/i915/display/intel_display_regs.h | 267 +++++++++-
.../gpu/drm/i915/display/intel_display_rps.c | 2 +-
.../gpu/drm/i915/display/intel_display_wa.c | 1 -
drivers/gpu/drm/i915/display/intel_dmc.c | 1 -
drivers/gpu/drm/i915/display/intel_dram.c | 2 +-
drivers/gpu/drm/i915/display/intel_fdi.c | 1 -
.../drm/i915/display/intel_fifo_underrun.c | 1 -
drivers/gpu/drm/i915/display/intel_gmbus.c | 1 -
drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
.../gpu/drm/i915/display/intel_hotplug_irq.c | 1 -
drivers/gpu/drm/i915/display/intel_lt_phy.c | 1 -
.../drm/i915/display/intel_modeset_setup.c | 1 -
drivers/gpu/drm/i915/display/intel_overlay.c | 2 +-
.../gpu/drm/i915/display/intel_pch_display.c | 1 -
.../gpu/drm/i915/display/intel_pch_refclk.c | 1 -
drivers/gpu/drm/i915/display/intel_pps.c | 1 -
drivers/gpu/drm/i915/display/intel_psr.c | 1 -
drivers/gpu/drm/i915/display/intel_rom.c | 3 +-
drivers/gpu/drm/i915/display/intel_tc.c | 1 -
drivers/gpu/drm/i915/display/skl_watermark.c | 2 +-
drivers/gpu/drm/i915/display/vlv_dsi.c | 1 -
drivers/gpu/drm/i915/gt/intel_gt.c | 1 +
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 2 +
drivers/gpu/drm/i915/gt/intel_rc6.c | 1 +
.../gpu/drm/i915/gt/intel_ring_submission.c | 1 +
drivers/gpu/drm/i915/gvt/handlers.c | 1 +
drivers/gpu/drm/i915/gvt/interrupt.c | 1 +
drivers/gpu/drm/i915/i915_irq.c | 1 +
drivers/gpu/drm/i915/i915_reg.h | 465 +-----------------
drivers/gpu/drm/i915/intel_clock_gating.c | 3 +-
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 2 +
drivers/gpu/drm/i915/vlv_suspend.c | 1 +
include/drm/intel/intel_gmd_interrupt.h | 92 ++++
include/drm/intel/intel_gmd_misc_regs.h | 21 +
include/drm/intel/intel_pcode.h | 114 +++++
52 files changed, 525 insertions(+), 506 deletions(-)
create mode 100644 include/drm/intel/intel_gmd_interrupt.h
create mode 100644 include/drm/intel/intel_gmd_misc_regs.h
create mode 100644 include/drm/intel/intel_pcode.h
--
2.50.1
^ permalink raw reply [flat|nested] 43+ messages in thread
* [v3 01/19] drm/i915: Extract display registers from i915_reg.h to display
2026-01-29 21:13 [v3 00/19] Make Display free from i915_reg.h Uma Shankar
2026-01-29 21:07 ` ✗ CI.checkpatch: warning for Make Display free from i915_reg.h (rev3) Patchwork
2026-01-29 21:08 ` ✓ CI.KUnit: success " Patchwork
@ 2026-01-29 21:13 ` Uma Shankar
2026-01-29 21:13 ` [v3 02/19] drm/i915: Extract South chicken " Uma Shankar
` (19 subsequent siblings)
22 siblings, 0 replies; 43+ messages in thread
From: Uma Shankar @ 2026-01-29 21:13 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, ville.syrjala, Uma Shankar
There are certain register definitions which are defined in i915_reg.h
which are exclusively needed by display. Move the same to display
headers to remove i915_reg.h includes from display. This is a step
towards making display independent of i915.
intel_clock_gating.c can include display header directly, since its
usage is planned to be re-factored and will be moved within display.
v3: Updated subject and commit message (Jani)
v2: Drop common header in include and use display_regs.h (Jani)
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_regs.h | 10 ++++++++++
drivers/gpu/drm/i915/display/intel_pch_display.c | 1 -
drivers/gpu/drm/i915/i915_reg.h | 10 ----------
drivers/gpu/drm/i915/intel_clock_gating.c | 2 +-
4 files changed, 11 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 9e0d853f4b61..9f8fbfb2e115 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -2021,6 +2021,16 @@
#define TRANS_BPC_6 REG_FIELD_PREP(TRANS_BPC_MASK, 2)
#define TRANS_BPC_12 REG_FIELD_PREP(TRANS_BPC_MASK, 3)
+#define _TRANSA_CHICKEN2 0xf0064
+#define _TRANSB_CHICKEN2 0xf1064
+#define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
+#define TRANS_CHICKEN2_TIMING_OVERRIDE REG_BIT(31)
+#define TRANS_CHICKEN2_FDI_POLARITY_REVERSED REG_BIT(29)
+#define TRANS_CHICKEN2_FRAME_START_DELAY_MASK REG_GENMASK(28, 27)
+#define TRANS_CHICKEN2_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_CHICKEN2_FRAME_START_DELAY_MASK, (x)) /* 0-3 */
+#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER REG_BIT(26)
+#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH REG_BIT(25)
+
#define PCH_DP_B _MMIO(0xe4100)
#define PCH_DP_C _MMIO(0xe4200)
#define PCH_DP_D _MMIO(0xe4300)
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index 16619f7be5f8..69c7952a1413 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -6,7 +6,6 @@
#include <drm/drm_print.h>
#include "g4x_dp.h"
-#include "i915_reg.h"
#include "intel_crt.h"
#include "intel_crt_regs.h"
#include "intel_de.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f928db78a3fa..f65f50bf44ba 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1023,16 +1023,6 @@
#define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE REG_BIT(10)
#define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE REG_BIT(4)
-#define _TRANSA_CHICKEN2 0xf0064
-#define _TRANSB_CHICKEN2 0xf1064
-#define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
-#define TRANS_CHICKEN2_TIMING_OVERRIDE REG_BIT(31)
-#define TRANS_CHICKEN2_FDI_POLARITY_REVERSED REG_BIT(29)
-#define TRANS_CHICKEN2_FRAME_START_DELAY_MASK REG_GENMASK(28, 27)
-#define TRANS_CHICKEN2_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_CHICKEN2_FRAME_START_DELAY_MASK, (x)) /* 0-3 */
-#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER REG_BIT(26)
-#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH REG_BIT(25)
-
#define SOUTH_CHICKEN1 _MMIO(0xc2000)
#define FDIA_PHASE_SYNC_SHIFT_OVR 19
#define FDIA_PHASE_SYNC_SHIFT_EN 18
diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
index 7336934bb934..4e18d5a22112 100644
--- a/drivers/gpu/drm/i915/intel_clock_gating.c
+++ b/drivers/gpu/drm/i915/intel_clock_gating.c
@@ -30,7 +30,7 @@
#include "display/i9xx_plane_regs.h"
#include "display/intel_display.h"
#include "display/intel_display_core.h"
-
+#include "display/intel_display_regs.h"
#include "gt/intel_engine_regs.h"
#include "gt/intel_gt.h"
#include "gt/intel_gt_mcr.h"
--
2.50.1
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [v3 02/19] drm/i915: Extract South chicken registers from i915_reg.h to display
2026-01-29 21:13 [v3 00/19] Make Display free from i915_reg.h Uma Shankar
` (2 preceding siblings ...)
2026-01-29 21:13 ` [v3 01/19] drm/i915: Extract display registers from i915_reg.h to display Uma Shankar
@ 2026-01-29 21:13 ` Uma Shankar
2026-01-29 21:13 ` [v3 03/19] drm/i915: Extract display interrupt definitions Uma Shankar
` (18 subsequent siblings)
22 siblings, 0 replies; 43+ messages in thread
From: Uma Shankar @ 2026-01-29 21:13 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, ville.syrjala, Uma Shankar
Extract South Chicken registers from i915_reg.h to display header.
This allows intel_pch_refclk.c not to include i915_reg.h
v3: Drop whitespace changes, commit header updated (Jani)
v2: Drop common header in include and use display_regs.h (Jani)
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
.../gpu/drm/i915/display/intel_display_regs.h | 27 +++++++++++++++++++
.../gpu/drm/i915/display/intel_pch_refclk.c | 1 -
drivers/gpu/drm/i915/i915_reg.h | 27 -------------------
3 files changed, 27 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 9f8fbfb2e115..db428e10d441 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -2864,6 +2864,33 @@ enum skl_power_gate {
#define SFUSE_STRAP_DDIC_DETECTED (1 << 1)
#define SFUSE_STRAP_DDID_DETECTED (1 << 0)
+#define SOUTH_CHICKEN1 _MMIO(0xc2000)
+#define FDIA_PHASE_SYNC_SHIFT_OVR 19
+#define FDIA_PHASE_SYNC_SHIFT_EN 18
+#define INVERT_DDIE_HPD REG_BIT(28)
+#define INVERT_DDID_HPD_MTP REG_BIT(27)
+#define INVERT_TC4_HPD REG_BIT(26)
+#define INVERT_TC3_HPD REG_BIT(25)
+#define INVERT_TC2_HPD REG_BIT(24)
+#define INVERT_TC1_HPD REG_BIT(23)
+#define INVERT_DDID_HPD (1 << 18)
+#define INVERT_DDIC_HPD (1 << 17)
+#define INVERT_DDIB_HPD (1 << 16)
+#define INVERT_DDIA_HPD (1 << 15)
+#define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
+#define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
+#define FDI_BC_BIFURCATION_SELECT (1 << 12)
+#define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8)
+#define CHASSIS_CLK_REQ_DURATION(x) ((x) << 8)
+#define SBCLK_RUN_REFCLK_DIS (1 << 7)
+#define ICP_SECOND_PPS_IO_SELECT REG_BIT(2)
+#define SPT_PWM_GRANULARITY (1 << 0)
+#define SOUTH_CHICKEN2 _MMIO(0xc2004)
+#define FDI_MPHY_IOSFSB_RESET_STATUS (1 << 13)
+#define FDI_MPHY_IOSFSB_RESET_CTL (1 << 12)
+#define LPT_PWM_GRANULARITY (1 << 5)
+#define DPLS_EDP_PPS_FIX_DIS (1 << 0)
+
/* Gen4+ Timestamp and Pipe Frame time stamp registers */
#define GEN4_TIMESTAMP _MMIO(0x2358)
#define ILK_TIMESTAMP_HI _MMIO(0x70070)
diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
index 9a89bb6dcf65..5f88663ef5e8 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
@@ -5,7 +5,6 @@
#include <drm/drm_print.h>
-#include "i915_reg.h"
#include "intel_de.h"
#include "intel_display_regs.h"
#include "intel_display_types.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f65f50bf44ba..c2efa50f080d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1023,33 +1023,6 @@
#define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE REG_BIT(10)
#define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE REG_BIT(4)
-#define SOUTH_CHICKEN1 _MMIO(0xc2000)
-#define FDIA_PHASE_SYNC_SHIFT_OVR 19
-#define FDIA_PHASE_SYNC_SHIFT_EN 18
-#define INVERT_DDIE_HPD REG_BIT(28)
-#define INVERT_DDID_HPD_MTP REG_BIT(27)
-#define INVERT_TC4_HPD REG_BIT(26)
-#define INVERT_TC3_HPD REG_BIT(25)
-#define INVERT_TC2_HPD REG_BIT(24)
-#define INVERT_TC1_HPD REG_BIT(23)
-#define INVERT_DDID_HPD (1 << 18)
-#define INVERT_DDIC_HPD (1 << 17)
-#define INVERT_DDIB_HPD (1 << 16)
-#define INVERT_DDIA_HPD (1 << 15)
-#define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
-#define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
-#define FDI_BC_BIFURCATION_SELECT (1 << 12)
-#define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8)
-#define CHASSIS_CLK_REQ_DURATION(x) ((x) << 8)
-#define SBCLK_RUN_REFCLK_DIS (1 << 7)
-#define ICP_SECOND_PPS_IO_SELECT REG_BIT(2)
-#define SPT_PWM_GRANULARITY (1 << 0)
-#define SOUTH_CHICKEN2 _MMIO(0xc2004)
-#define FDI_MPHY_IOSFSB_RESET_STATUS (1 << 13)
-#define FDI_MPHY_IOSFSB_RESET_CTL (1 << 12)
-#define LPT_PWM_GRANULARITY (1 << 5)
-#define DPLS_EDP_PPS_FIX_DIS (1 << 0)
-
#define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020)
#define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31)
#define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30)
--
2.50.1
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [v3 03/19] drm/i915: Extract display interrupt definitions
2026-01-29 21:13 [v3 00/19] Make Display free from i915_reg.h Uma Shankar
` (3 preceding siblings ...)
2026-01-29 21:13 ` [v3 02/19] drm/i915: Extract South chicken " Uma Shankar
@ 2026-01-29 21:13 ` Uma Shankar
2026-01-29 21:13 ` [v3 04/19] drm/i915: Extract DSPCLK_GATE_D from i915_reg to display Uma Shankar
` (17 subsequent siblings)
22 siblings, 0 replies; 43+ messages in thread
From: Uma Shankar @ 2026-01-29 21:13 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, ville.syrjala, Uma Shankar
Extract DE Interrupt registers from i915_reg.h to display header.
This allows intel_display_rps.c not to include i915_reg.h
v2: Update commit message (Jani)
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
.../gpu/drm/i915/display/intel_display_regs.h | 33 +++++++++++++++++++
.../gpu/drm/i915/display/intel_display_rps.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 33 -------------------
3 files changed, 34 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index db428e10d441..d496e0ddd910 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -1333,6 +1333,39 @@
GEN8_DE_PORT_IER, \
GEN8_DE_PORT_IIR)
+/* interrupts */
+#define DE_MASTER_IRQ_CONTROL (1 << 31)
+#define DE_SPRITEB_FLIP_DONE (1 << 29)
+#define DE_SPRITEA_FLIP_DONE (1 << 28)
+#define DE_PLANEB_FLIP_DONE (1 << 27)
+#define DE_PLANEA_FLIP_DONE (1 << 26)
+#define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
+#define DE_PCU_EVENT (1 << 25)
+#define DE_GTT_FAULT (1 << 24)
+#define DE_POISON (1 << 23)
+#define DE_PERFORM_COUNTER (1 << 22)
+#define DE_PCH_EVENT (1 << 21)
+#define DE_AUX_CHANNEL_A (1 << 20)
+#define DE_DP_A_HOTPLUG (1 << 19)
+#define DE_GSE (1 << 18)
+#define DE_PIPEB_VBLANK (1 << 15)
+#define DE_PIPEB_EVEN_FIELD (1 << 14)
+#define DE_PIPEB_ODD_FIELD (1 << 13)
+#define DE_PIPEB_LINE_COMPARE (1 << 12)
+#define DE_PIPEB_VSYNC (1 << 11)
+#define DE_PIPEB_CRC_DONE (1 << 10)
+#define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
+#define DE_PIPEA_VBLANK (1 << 7)
+#define DE_PIPE_VBLANK(pipe) (1 << (7 + 8 * (pipe)))
+#define DE_PIPEA_EVEN_FIELD (1 << 6)
+#define DE_PIPEA_ODD_FIELD (1 << 5)
+#define DE_PIPEA_LINE_COMPARE (1 << 4)
+#define DE_PIPEA_VSYNC (1 << 3)
+#define DE_PIPEA_CRC_DONE (1 << 2)
+#define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8 * (pipe)))
+#define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
+#define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8 * (pipe)))
+
#define GEN8_DE_MISC_ISR _MMIO(0x44460)
#define GEN8_DE_MISC_IMR _MMIO(0x44464)
#define GEN8_DE_MISC_IIR _MMIO(0x44468)
diff --git a/drivers/gpu/drm/i915/display/intel_display_rps.c b/drivers/gpu/drm/i915/display/intel_display_rps.c
index e77811396474..bf00266dae4b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_rps.c
+++ b/drivers/gpu/drm/i915/display/intel_display_rps.c
@@ -8,8 +8,8 @@
#include <drm/drm_crtc.h>
#include <drm/drm_vblank.h>
-#include "i915_reg.h"
#include "intel_display_core.h"
+#include "intel_display_regs.h"
#include "intel_display_irq.h"
#include "intel_display_rps.h"
#include "intel_display_types.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c2efa50f080d..3f4203a69bcd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -805,39 +805,6 @@
#define RM_TIMEOUT_REG_CAPTURE _MMIO(0x420E0)
#define MMIO_TIMEOUT_US(us) ((us) << 0)
-/* interrupts */
-#define DE_MASTER_IRQ_CONTROL (1 << 31)
-#define DE_SPRITEB_FLIP_DONE (1 << 29)
-#define DE_SPRITEA_FLIP_DONE (1 << 28)
-#define DE_PLANEB_FLIP_DONE (1 << 27)
-#define DE_PLANEA_FLIP_DONE (1 << 26)
-#define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
-#define DE_PCU_EVENT (1 << 25)
-#define DE_GTT_FAULT (1 << 24)
-#define DE_POISON (1 << 23)
-#define DE_PERFORM_COUNTER (1 << 22)
-#define DE_PCH_EVENT (1 << 21)
-#define DE_AUX_CHANNEL_A (1 << 20)
-#define DE_DP_A_HOTPLUG (1 << 19)
-#define DE_GSE (1 << 18)
-#define DE_PIPEB_VBLANK (1 << 15)
-#define DE_PIPEB_EVEN_FIELD (1 << 14)
-#define DE_PIPEB_ODD_FIELD (1 << 13)
-#define DE_PIPEB_LINE_COMPARE (1 << 12)
-#define DE_PIPEB_VSYNC (1 << 11)
-#define DE_PIPEB_CRC_DONE (1 << 10)
-#define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
-#define DE_PIPEA_VBLANK (1 << 7)
-#define DE_PIPE_VBLANK(pipe) (1 << (7 + 8 * (pipe)))
-#define DE_PIPEA_EVEN_FIELD (1 << 6)
-#define DE_PIPEA_ODD_FIELD (1 << 5)
-#define DE_PIPEA_LINE_COMPARE (1 << 4)
-#define DE_PIPEA_VSYNC (1 << 3)
-#define DE_PIPEA_CRC_DONE (1 << 2)
-#define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8 * (pipe)))
-#define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
-#define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8 * (pipe)))
-
#define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */
#define MASTER_INTERRUPT_ENABLE (1 << 31)
--
2.50.1
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [v3 04/19] drm/i915: Extract DSPCLK_GATE_D from i915_reg to display
2026-01-29 21:13 [v3 00/19] Make Display free from i915_reg.h Uma Shankar
` (4 preceding siblings ...)
2026-01-29 21:13 ` [v3 03/19] drm/i915: Extract display interrupt definitions Uma Shankar
@ 2026-01-29 21:13 ` Uma Shankar
2026-01-29 21:13 ` [v3 05/19] drm/{i915, xe}: Extract pcode definitions to common header Uma Shankar
` (16 subsequent siblings)
22 siblings, 0 replies; 43+ messages in thread
From: Uma Shankar @ 2026-01-29 21:13 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, ville.syrjala, Uma Shankar
Move DSPCLK_GATE_D register definition to display header.
This allows intel_gmbus.c not to include i915_reg.h.
v3: Update commit header and message (Jani)
v2: Drop common header in include and use display_regs.h (Jani)
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
.../gpu/drm/i915/display/intel_display_regs.h | 50 +++++++++++++++++++
drivers/gpu/drm/i915/display/intel_gmbus.c | 1 -
drivers/gpu/drm/i915/i915_reg.h | 50 -------------------
3 files changed, 50 insertions(+), 51 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index d496e0ddd910..f90d52f7e5be 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -160,6 +160,47 @@
#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
+#define DSPCLK_GATE_D _MMIO(0x6200)
+#define VLV_DSPCLK_GATE_D _MMIO(VLV_DISPLAY_BASE + 0x6200)
+# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
+# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
+# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
+# define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
+# define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
+# define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
+# define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
+# define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 24) /* pnv */
+# define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
+# define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
+# define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
+# define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
+# define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
+# define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
+# define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
+# define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
+# define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
+# define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
+# define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
+# define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
+# define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
+# define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
+# define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
+# define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
+# define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
+# define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
+# define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
+# define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
+# define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
+/*
+ * This bit must be set on the 830 to prevent hangs when turning off the
+ * overlay scaler.
+ */
+# define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
+# define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
+# define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
+# define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
+# define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
+
/* Additional CHV pll/phy registers */
#define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240)
#define DPLL_PORTD_READY_MASK (0xf)
@@ -2924,6 +2965,15 @@ enum skl_power_gate {
#define LPT_PWM_GRANULARITY (1 << 5)
#define DPLS_EDP_PPS_FIX_DIS (1 << 0)
+#define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020)
+#define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31)
+#define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30)
+#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29)
+#define PCH_DPMGUNIT_CLOCK_GATE_DISABLE (1 << 15)
+#define PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14)
+#define CNP_PWM_CGE_GATING_DISABLE (1 << 13)
+#define PCH_LP_PARTITION_LEVEL_DISABLE (1 << 12)
+
/* Gen4+ Timestamp and Pipe Frame time stamp registers */
#define GEN4_TIMESTAMP _MMIO(0x2358)
#define ILK_TIMESTAMP_HI _MMIO(0x70070)
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
index 2caff677600c..81b6c6991323 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -35,7 +35,6 @@
#include <drm/drm_print.h>
#include <drm/display/drm_hdcp_helper.h>
-#include "i915_reg.h"
#include "intel_de.h"
#include "intel_display_regs.h"
#include "intel_display_types.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3f4203a69bcd..26e5504dbc67 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -613,47 +613,6 @@
#define DSTATE_GFX_CLOCK_GATING (1 << 1)
#define DSTATE_DOT_CLOCK_GATING (1 << 0)
-#define DSPCLK_GATE_D _MMIO(0x6200)
-#define VLV_DSPCLK_GATE_D _MMIO(VLV_DISPLAY_BASE + 0x6200)
-# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
-# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
-# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
-# define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
-# define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
-# define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
-# define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
-# define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 24) /* pnv */
-# define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
-# define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
-# define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
-# define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
-# define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
-# define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
-# define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
-# define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
-# define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
-# define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
-# define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
-# define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
-# define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
-# define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
-# define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
-# define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
-# define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
-# define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
-# define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
-# define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
-# define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
-/*
- * This bit must be set on the 830 to prevent hangs when turning off the
- * overlay scaler.
- */
-# define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
-# define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
-# define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
-# define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
-# define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
-
#define RENCLK_GATE_D1 _MMIO(0x6204)
# define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
# define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
@@ -990,15 +949,6 @@
#define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE REG_BIT(10)
#define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE REG_BIT(4)
-#define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020)
-#define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31)
-#define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30)
-#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29)
-#define PCH_DPMGUNIT_CLOCK_GATE_DISABLE (1 << 15)
-#define PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14)
-#define CNP_PWM_CGE_GATING_DISABLE (1 << 13)
-#define PCH_LP_PARTITION_LEVEL_DISABLE (1 << 12)
-
#define VLV_PMWGICZ _MMIO(0x1300a4)
#define HSW_EDRAM_CAP _MMIO(0x120010)
--
2.50.1
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [v3 05/19] drm/{i915, xe}: Extract pcode definitions to common header
2026-01-29 21:13 [v3 00/19] Make Display free from i915_reg.h Uma Shankar
` (5 preceding siblings ...)
2026-01-29 21:13 ` [v3 04/19] drm/i915: Extract DSPCLK_GATE_D from i915_reg to display Uma Shankar
@ 2026-01-29 21:13 ` Uma Shankar
2026-02-03 12:00 ` Jani Nikula
2026-01-29 21:13 ` [v3 06/19] drm/i915: Remove i915_reg.h from intel_display_device.c Uma Shankar
` (15 subsequent siblings)
22 siblings, 1 reply; 43+ messages in thread
From: Uma Shankar @ 2026-01-29 21:13 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, ville.syrjala, Uma Shankar
There are certain register definitions which are commonly shared
by i915, xe and display. Extract the same to a common header to
avoid duplication.
Move GEN6_PCODE_MAILBOX to common pcode header to make intel_cdclk.c
free from including i915_reg.h.
v2: Make the header granular and per feature (Jani)
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 101 +------------------
include/drm/intel/intel_pcode.h | 108 +++++++++++++++++++++
3 files changed, 110 insertions(+), 101 deletions(-)
create mode 100644 include/drm/intel/intel_pcode.h
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 9217050a76e0..606256027264 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -27,9 +27,9 @@
#include <drm/drm_fixed.h>
#include <drm/drm_print.h>
+#include <drm/intel/intel_pcode.h>
#include "hsw_ips.h"
-#include "i915_reg.h"
#include "intel_atomic.h"
#include "intel_audio.h"
#include "intel_cdclk.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 26e5504dbc67..c7361e82a0c6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -25,6 +25,7 @@
#ifndef _I915_REG_H_
#define _I915_REG_H_
+#include <drm/intel/intel_pcode.h>
#include "i915_reg_defs.h"
#include "display/intel_display_reg_defs.h"
@@ -957,106 +958,6 @@
#define EDRAM_WAYS_IDX(cap) (((cap) >> 5) & 0x7)
#define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3)
-#define GEN6_PCODE_MAILBOX _MMIO(0x138124)
-#define GEN6_PCODE_READY (1 << 31)
-#define GEN6_PCODE_MB_PARAM2 REG_GENMASK(23, 16)
-#define GEN6_PCODE_MB_PARAM1 REG_GENMASK(15, 8)
-#define GEN6_PCODE_MB_COMMAND REG_GENMASK(7, 0)
-#define GEN6_PCODE_ERROR_MASK 0xFF
-#define GEN6_PCODE_SUCCESS 0x0
-#define GEN6_PCODE_ILLEGAL_CMD 0x1
-#define GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2
-#define GEN6_PCODE_TIMEOUT 0x3
-#define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF
-#define GEN7_PCODE_TIMEOUT 0x2
-#define GEN7_PCODE_ILLEGAL_DATA 0x3
-#define GEN11_PCODE_ILLEGAL_SUBCOMMAND 0x4
-#define GEN11_PCODE_LOCKED 0x6
-#define GEN11_PCODE_REJECTED 0x11
-#define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
-#define GEN6_PCODE_WRITE_RC6VIDS 0x4
-#define GEN6_PCODE_READ_RC6VIDS 0x5
-#define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
-#define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
-#define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18
-#define GEN9_PCODE_READ_MEM_LATENCY 0x6
-#define GEN9_MEM_LATENCY_LEVEL_3_7_MASK REG_GENMASK(31, 24)
-#define GEN9_MEM_LATENCY_LEVEL_2_6_MASK REG_GENMASK(23, 16)
-#define GEN9_MEM_LATENCY_LEVEL_1_5_MASK REG_GENMASK(15, 8)
-#define GEN9_MEM_LATENCY_LEVEL_0_4_MASK REG_GENMASK(7, 0)
-#define SKL_PCODE_LOAD_HDCP_KEYS 0x5
-#define SKL_PCODE_CDCLK_CONTROL 0x7
-#define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3
-#define SKL_CDCLK_READY_FOR_CHANGE 0x1
-#define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
-#define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
-#define GEN6_READ_OC_PARAMS 0xc
-#define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd
-#define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8)
-#define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8))
-#define ADL_PCODE_MEM_SS_READ_PSF_GV_INFO ((0) | (0x2 << 8))
-#define DISPLAY_TO_PCODE_CDCLK_MAX 0x28D
-#define DISPLAY_TO_PCODE_VOLTAGE_MASK REG_GENMASK(1, 0)
-#define DISPLAY_TO_PCODE_VOLTAGE_MAX DISPLAY_TO_PCODE_VOLTAGE_MASK
-#define DISPLAY_TO_PCODE_CDCLK_VALID REG_BIT(27)
-#define DISPLAY_TO_PCODE_PIPE_COUNT_VALID REG_BIT(31)
-#define DISPLAY_TO_PCODE_CDCLK_MASK REG_GENMASK(25, 16)
-#define DISPLAY_TO_PCODE_PIPE_COUNT_MASK REG_GENMASK(30, 28)
-#define DISPLAY_TO_PCODE_CDCLK(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_CDCLK_MASK, (x))
-#define DISPLAY_TO_PCODE_PIPE_COUNT(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_PIPE_COUNT_MASK, (x))
-#define DISPLAY_TO_PCODE_VOLTAGE(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_VOLTAGE_MASK, (x))
-#define DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, num_pipes, voltage_level) \
- ((DISPLAY_TO_PCODE_CDCLK(cdclk)) | \
- (DISPLAY_TO_PCODE_PIPE_COUNT(num_pipes)) | \
- (DISPLAY_TO_PCODE_VOLTAGE(voltage_level)))
-#define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe
-#define ICL_PCODE_REP_QGV_MASK REG_GENMASK(1, 0)
-#define ICL_PCODE_REP_QGV_SAFE REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 0)
-#define ICL_PCODE_REP_QGV_POLL REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 1)
-#define ICL_PCODE_REP_QGV_REJECTED REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 2)
-#define ADLS_PCODE_REP_PSF_MASK REG_GENMASK(3, 2)
-#define ADLS_PCODE_REP_PSF_SAFE REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 0)
-#define ADLS_PCODE_REP_PSF_POLL REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 1)
-#define ADLS_PCODE_REP_PSF_REJECTED REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 2)
-#define ICL_PCODE_REQ_QGV_PT_MASK REG_GENMASK(7, 0)
-#define ICL_PCODE_REQ_QGV_PT(x) REG_FIELD_PREP(ICL_PCODE_REQ_QGV_PT_MASK, (x))
-#define ADLS_PCODE_REQ_PSF_PT_MASK REG_GENMASK(10, 8)
-#define ADLS_PCODE_REQ_PSF_PT(x) REG_FIELD_PREP(ADLS_PCODE_REQ_PSF_PT_MASK, (x))
-#define GEN6_PCODE_READ_D_COMP 0x10
-#define GEN6_PCODE_WRITE_D_COMP 0x11
-#define ICL_PCODE_EXIT_TCCOLD 0x12
-#define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
-#define DISPLAY_IPS_CONTROL 0x19
-#define TGL_PCODE_TCCOLD 0x26
-#define TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED REG_BIT(0)
-#define TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ 0
-#define TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ REG_BIT(0)
- /* See also IPS_CTL */
-#define IPS_PCODE_CONTROL (1 << 30)
-#define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
-#define GEN9_PCODE_SAGV_CONTROL 0x21
-#define GEN9_SAGV_DISABLE 0x0
-#define GEN9_SAGV_IS_DISABLED 0x1
-#define GEN9_SAGV_ENABLE 0x3
-#define DG1_PCODE_STATUS 0x7E
-#define DG1_UNCORE_GET_INIT_STATUS 0x0
-#define DG1_UNCORE_INIT_STATUS_COMPLETE 0x1
-#define PCODE_POWER_SETUP 0x7C
-#define POWER_SETUP_SUBCOMMAND_READ_I1 0x4
-#define POWER_SETUP_SUBCOMMAND_WRITE_I1 0x5
-#define POWER_SETUP_I1_WATTS REG_BIT(31)
-#define POWER_SETUP_I1_SHIFT 6 /* 10.6 fixed point format */
-#define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0)
-#define POWER_SETUP_SUBCOMMAND_G8_ENABLE 0x6
-#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
-#define XEHP_PCODE_FREQUENCY_CONFIG 0x6e /* pvc */
-/* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
-#define PCODE_MBOX_FC_SC_READ_FUSED_P0 0x0
-#define PCODE_MBOX_FC_SC_READ_FUSED_PN 0x1
-/* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */
-/* XEHP_PCODE_FREQUENCY_CONFIG param2 */
-#define PCODE_MBOX_DOMAIN_NONE 0x0
-#define PCODE_MBOX_DOMAIN_MEDIAFF 0x3
#define GEN6_PCODE_DATA _MMIO(0x138128)
#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
diff --git a/include/drm/intel/intel_pcode.h b/include/drm/intel/intel_pcode.h
new file mode 100644
index 000000000000..8e9a574c87d9
--- /dev/null
+++ b/include/drm/intel/intel_pcode.h
@@ -0,0 +1,108 @@
+/* SPDX-License-Identifier: MIT */
+/* Copyright © 2026 Intel Corporation */
+
+#ifndef _INTEL_GMD_COMMON_REG_H_
+#define _INTEL_GMD_COMMON_REG_H_
+
+#define GEN6_PCODE_MAILBOX _MMIO(0x138124)
+#define GEN6_PCODE_READY (1 << 31)
+#define GEN6_PCODE_MB_PARAM2 REG_GENMASK(23, 16)
+#define GEN6_PCODE_MB_PARAM1 REG_GENMASK(15, 8)
+#define GEN6_PCODE_MB_COMMAND REG_GENMASK(7, 0)
+#define GEN6_PCODE_ERROR_MASK 0xFF
+#define GEN6_PCODE_SUCCESS 0x0
+#define GEN6_PCODE_ILLEGAL_CMD 0x1
+#define GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2
+#define GEN6_PCODE_TIMEOUT 0x3
+#define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF
+#define GEN7_PCODE_TIMEOUT 0x2
+#define GEN7_PCODE_ILLEGAL_DATA 0x3
+#define GEN11_PCODE_ILLEGAL_SUBCOMMAND 0x4
+#define GEN11_PCODE_LOCKED 0x6
+#define GEN11_PCODE_REJECTED 0x11
+#define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
+#define GEN6_PCODE_WRITE_RC6VIDS 0x4
+#define GEN6_PCODE_READ_RC6VIDS 0x5
+#define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
+#define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
+#define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18
+#define GEN9_PCODE_READ_MEM_LATENCY 0x6
+#define GEN9_MEM_LATENCY_LEVEL_3_7_MASK REG_GENMASK(31, 24)
+#define GEN9_MEM_LATENCY_LEVEL_2_6_MASK REG_GENMASK(23, 16)
+#define GEN9_MEM_LATENCY_LEVEL_1_5_MASK REG_GENMASK(15, 8)
+#define GEN9_MEM_LATENCY_LEVEL_0_4_MASK REG_GENMASK(7, 0)
+#define SKL_PCODE_LOAD_HDCP_KEYS 0x5
+#define SKL_PCODE_CDCLK_CONTROL 0x7
+#define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3
+#define SKL_CDCLK_READY_FOR_CHANGE 0x1
+#define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
+#define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
+#define GEN6_READ_OC_PARAMS 0xc
+#define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd
+#define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8)
+#define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8))
+#define ADL_PCODE_MEM_SS_READ_PSF_GV_INFO ((0) | (0x2 << 8))
+#define DISPLAY_TO_PCODE_CDCLK_MAX 0x28D
+#define DISPLAY_TO_PCODE_VOLTAGE_MASK REG_GENMASK(1, 0)
+#define DISPLAY_TO_PCODE_VOLTAGE_MAX DISPLAY_TO_PCODE_VOLTAGE_MASK
+#define DISPLAY_TO_PCODE_CDCLK_VALID REG_BIT(27)
+#define DISPLAY_TO_PCODE_PIPE_COUNT_VALID REG_BIT(31)
+#define DISPLAY_TO_PCODE_CDCLK_MASK REG_GENMASK(25, 16)
+#define DISPLAY_TO_PCODE_PIPE_COUNT_MASK REG_GENMASK(30, 28)
+#define DISPLAY_TO_PCODE_CDCLK(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_CDCLK_MASK, (x))
+#define DISPLAY_TO_PCODE_PIPE_COUNT(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_PIPE_COUNT_MASK, (x))
+#define DISPLAY_TO_PCODE_VOLTAGE(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_VOLTAGE_MASK, (x))
+#define DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, num_pipes, voltage_level) \
+ ((DISPLAY_TO_PCODE_CDCLK(cdclk)) | \
+ (DISPLAY_TO_PCODE_PIPE_COUNT(num_pipes)) | \
+ (DISPLAY_TO_PCODE_VOLTAGE(voltage_level)))
+#define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe
+#define ICL_PCODE_REP_QGV_MASK REG_GENMASK(1, 0)
+#define ICL_PCODE_REP_QGV_SAFE REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 0)
+#define ICL_PCODE_REP_QGV_POLL REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 1)
+#define ICL_PCODE_REP_QGV_REJECTED REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 2)
+#define ADLS_PCODE_REP_PSF_MASK REG_GENMASK(3, 2)
+#define ADLS_PCODE_REP_PSF_SAFE REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 0)
+#define ADLS_PCODE_REP_PSF_POLL REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 1)
+#define ADLS_PCODE_REP_PSF_REJECTED REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 2)
+#define ICL_PCODE_REQ_QGV_PT_MASK REG_GENMASK(7, 0)
+#define ICL_PCODE_REQ_QGV_PT(x) REG_FIELD_PREP(ICL_PCODE_REQ_QGV_PT_MASK, (x))
+#define ADLS_PCODE_REQ_PSF_PT_MASK REG_GENMASK(10, 8)
+#define ADLS_PCODE_REQ_PSF_PT(x) REG_FIELD_PREP(ADLS_PCODE_REQ_PSF_PT_MASK, (x))
+#define GEN6_PCODE_READ_D_COMP 0x10
+#define GEN6_PCODE_WRITE_D_COMP 0x11
+#define ICL_PCODE_EXIT_TCCOLD 0x12
+#define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
+#define DISPLAY_IPS_CONTROL 0x19
+#define TGL_PCODE_TCCOLD 0x26
+#define TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED REG_BIT(0)
+#define TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ 0
+#define TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ REG_BIT(0)
+/* See also IPS_CTL */
+#define IPS_PCODE_CONTROL (1 << 30)
+#define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
+#define GEN9_PCODE_SAGV_CONTROL 0x21
+#define GEN9_SAGV_DISABLE 0x0
+#define GEN9_SAGV_IS_DISABLED 0x1
+#define GEN9_SAGV_ENABLE 0x3
+#define DG1_PCODE_STATUS 0x7E
+#define DG1_UNCORE_GET_INIT_STATUS 0x0
+#define DG1_UNCORE_INIT_STATUS_COMPLETE 0x1
+#define PCODE_POWER_SETUP 0x7C
+#define POWER_SETUP_SUBCOMMAND_READ_I1 0x4
+#define POWER_SETUP_SUBCOMMAND_WRITE_I1 0x5
+#define POWER_SETUP_I1_WATTS REG_BIT(31)
+#define POWER_SETUP_I1_SHIFT 6 /* 10.6 fixed point format */
+#define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0)
+#define POWER_SETUP_SUBCOMMAND_G8_ENABLE 0x6
+#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
+#define XEHP_PCODE_FREQUENCY_CONFIG 0x6e /* pvc */
+/* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
+#define PCODE_MBOX_FC_SC_READ_FUSED_P0 0x0
+#define PCODE_MBOX_FC_SC_READ_FUSED_PN 0x1
+/* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */
+/* XEHP_PCODE_FREQUENCY_CONFIG param2 */
+#define PCODE_MBOX_DOMAIN_NONE 0x0
+#define PCODE_MBOX_DOMAIN_MEDIAFF 0x3
+
+#endif
--
2.50.1
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [v3 06/19] drm/i915: Remove i915_reg.h from intel_display_device.c
2026-01-29 21:13 [v3 00/19] Make Display free from i915_reg.h Uma Shankar
` (6 preceding siblings ...)
2026-01-29 21:13 ` [v3 05/19] drm/{i915, xe}: Extract pcode definitions to common header Uma Shankar
@ 2026-01-29 21:13 ` Uma Shankar
2026-02-03 12:06 ` Jani Nikula
2026-01-29 21:13 ` [v3 07/19] drm/i915: Remove i915_reg.h from intel_dram.c Uma Shankar
` (14 subsequent siblings)
22 siblings, 1 reply; 43+ messages in thread
From: Uma Shankar @ 2026-01-29 21:13 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, ville.syrjala, Uma Shankar
Move GU_CNTL_PROTECTED and GMD_ID_DISPLAY to common header,
this helps intel_display_device.c free from i915_reg.h dependency.
v2: Move GMD_ID_DISPLAY to display header instead of common (Jani)
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_device.c | 7 +++----
drivers/gpu/drm/i915/display/intel_display_regs.h | 8 ++++++++
drivers/gpu/drm/i915/i915_reg.h | 4 ----
3 files changed, 11 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
index 471f236c9ddf..d449528bfc7f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -10,7 +10,6 @@
#include <drm/drm_print.h>
#include <drm/intel/pciids.h>
-#include "i915_reg.h"
#include "intel_cx0_phy_regs.h"
#include "intel_de.h"
#include "intel_display.h"
@@ -1539,9 +1538,9 @@ probe_gmdid_display(struct intel_display *display, struct intel_display_ip_ver *
return NULL;
}
- gmd_id.ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val);
- gmd_id.rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val);
- gmd_id.step = REG_FIELD_GET(GMD_ID_STEP, val);
+ gmd_id.ver = REG_FIELD_GET(GMD_ID_DISPLAY_ARCH_MASK, val);
+ gmd_id.rel = REG_FIELD_GET(GMD_ID_DISPLAY_RELEASE_MASK, val);
+ gmd_id.step = REG_FIELD_GET(GMD_ID_DISPLAY_STEP, val);
for (i = 0; i < ARRAY_SIZE(gmdid_display_map); i++) {
if (gmd_id.ver == gmdid_display_map[i].ver &&
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index f90d52f7e5be..0d7788db4a7f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -6,6 +6,9 @@
#include "intel_display_reg_defs.h"
+#define GU_CNTL_PROTECTED _MMIO(0x10100C)
+#define DEPRESENT REG_BIT(9)
+
#define _GEN7_PIPEA_DE_LOAD_SL 0x70068
#define _GEN7_PIPEB_DE_LOAD_SL 0x71068
#define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL)
@@ -1626,6 +1629,11 @@
#define GLK_DFSM_DISPLAY_DSC_DISABLE (1 << 7)
#define XE2LPD_DFSM_DBUF_OVERLAP_DISABLE (1 << 3)
+#define GMD_ID_DISPLAY _MMIO(0x510a0)
+#define GMD_ID_DISPLAY_ARCH_MASK REG_GENMASK(31, 22)
+#define GMD_ID_DISPLAY_RELEASE_MASK REG_GENMASK(21, 14)
+#define GMD_ID_DISPLAY_STEP REG_GENMASK(5, 0)
+
#define XE2LPD_DE_CAP _MMIO(0x41100)
#define XE2LPD_DE_CAP_3DLUT_MASK REG_GENMASK(31, 30)
#define XE2LPD_DE_CAP_DSC_MASK REG_GENMASK(29, 28)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c7361e82a0c6..4341308c3b2b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -117,9 +117,6 @@
* #define GEN8_BAR _MMIO(0xb888)
*/
-#define GU_CNTL_PROTECTED _MMIO(0x10100C)
-#define DEPRESENT REG_BIT(9)
-
#define GU_CNTL _MMIO(0x101010)
#define LMEM_INIT REG_BIT(7)
#define DRIVERFLR REG_BIT(31)
@@ -926,7 +923,6 @@
#define MASK_WAKEMEM REG_BIT(13)
#define DDI_CLOCK_REG_ACCESS REG_BIT(7)
-#define GMD_ID_DISPLAY _MMIO(0x510a0)
#define GMD_ID_ARCH_MASK REG_GENMASK(31, 22)
#define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14)
#define GMD_ID_STEP REG_GENMASK(5, 0)
--
2.50.1
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [v3 07/19] drm/i915: Remove i915_reg.h from intel_dram.c
2026-01-29 21:13 [v3 00/19] Make Display free from i915_reg.h Uma Shankar
` (7 preceding siblings ...)
2026-01-29 21:13 ` [v3 06/19] drm/i915: Remove i915_reg.h from intel_display_device.c Uma Shankar
@ 2026-01-29 21:13 ` Uma Shankar
2026-02-03 11:50 ` Jani Nikula
2026-01-29 21:13 ` [v3 08/19] drm/i915: Remove i915_reg.h from intel_display.c Uma Shankar
` (13 subsequent siblings)
22 siblings, 1 reply; 43+ messages in thread
From: Uma Shankar @ 2026-01-29 21:13 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, ville.syrjala, Uma Shankar
Make intel_dram.c free from including i915_reg.h.
v2: Move mem config register to newly added pcode header (Jani)
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_dram.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 6 ------
include/drm/intel/intel_pcode.h | 6 ++++++
3 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dram.c b/drivers/gpu/drm/i915/display/intel_dram.c
index 3b9879714ea9..3366e18f594e 100644
--- a/drivers/gpu/drm/i915/display/intel_dram.c
+++ b/drivers/gpu/drm/i915/display/intel_dram.c
@@ -7,8 +7,8 @@
#include <drm/drm_managed.h>
#include <drm/drm_print.h>
+#include <drm/intel/intel_pcode.h>
-#include "i915_reg.h"
#include "intel_display_core.h"
#include "intel_display_utils.h"
#include "intel_dram.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4341308c3b2b..bc466d8c8c60 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1010,12 +1010,6 @@
#define OROM_OFFSET _MMIO(0x1020c0)
#define OROM_OFFSET_MASK REG_GENMASK(20, 16)
-#define MTL_MEM_SS_INFO_GLOBAL _MMIO(0x45700)
-#define XE3P_ECC_IMPACTING_DE REG_BIT(12)
-#define MTL_N_OF_ENABLED_QGV_POINTS_MASK REG_GENMASK(11, 8)
-#define MTL_N_OF_POPULATED_CH_MASK REG_GENMASK(7, 4)
-#define MTL_DDR_TYPE_MASK REG_GENMASK(3, 0)
-
#define MTL_MEDIA_GSI_BASE 0x380000
#endif /* _I915_REG_H_ */
diff --git a/include/drm/intel/intel_pcode.h b/include/drm/intel/intel_pcode.h
index 8e9a574c87d9..f6f894ba9b20 100644
--- a/include/drm/intel/intel_pcode.h
+++ b/include/drm/intel/intel_pcode.h
@@ -105,4 +105,10 @@
#define PCODE_MBOX_DOMAIN_NONE 0x0
#define PCODE_MBOX_DOMAIN_MEDIAFF 0x3
+#define MTL_MEM_SS_INFO_GLOBAL _MMIO(0x45700)
+#define XE3P_ECC_IMPACTING_DE REG_BIT(12)
+#define MTL_N_OF_ENABLED_QGV_POINTS_MASK REG_GENMASK(11, 8)
+#define MTL_N_OF_POPULATED_CH_MASK REG_GENMASK(7, 4)
+#define MTL_DDR_TYPE_MASK REG_GENMASK(3, 0)
+
#endif
--
2.50.1
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [v3 08/19] drm/i915: Remove i915_reg.h from intel_display.c
2026-01-29 21:13 [v3 00/19] Make Display free from i915_reg.h Uma Shankar
` (8 preceding siblings ...)
2026-01-29 21:13 ` [v3 07/19] drm/i915: Remove i915_reg.h from intel_dram.c Uma Shankar
@ 2026-01-29 21:13 ` Uma Shankar
2026-01-29 21:13 ` [v3 09/19] drm/i915: Remove i915_reg.h from intel_overlay.c Uma Shankar
` (12 subsequent siblings)
22 siblings, 0 replies; 43+ messages in thread
From: Uma Shankar @ 2026-01-29 21:13 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, ville.syrjala, Uma Shankar
Move CHICKEN_PIPESL_1 register definition to display header.
This allows intel_display.c free of i915_reg.h include.
v3: Fix commit header (Jani)
v2: Drop common header in include and use display_regs.h (Jani)
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 1 -
.../gpu/drm/i915/display/intel_display_regs.h | 23 +++++++++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 22 ------------------
3 files changed, 23 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 7491e00e3858..b7d4ac7e5ff9 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -50,7 +50,6 @@
#include "g4x_hdmi.h"
#include "hsw_ips.h"
#include "i915_config.h"
-#include "i915_reg.h"
#include "i9xx_plane.h"
#include "i9xx_plane_regs.h"
#include "i9xx_wm.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 0d7788db4a7f..706024c2a463 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -1543,6 +1543,29 @@
#define CHICKEN_FBC_STRIDE_MASK REG_GENMASK(12, 0)
#define CHICKEN_FBC_STRIDE(x) REG_FIELD_PREP(CHICKEN_FBC_STRIDE_MASK, (x))
+#define _CHICKEN_PIPESL_1_A 0x420b0
+#define _CHICKEN_PIPESL_1_B 0x420b4
+#define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
+#define HSW_PRI_STRETCH_MAX_MASK REG_GENMASK(28, 27)
+#define HSW_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 0)
+#define HSW_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 1)
+#define HSW_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 2)
+#define HSW_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 3)
+#define HSW_SPR_STRETCH_MAX_MASK REG_GENMASK(26, 25)
+#define HSW_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 0)
+#define HSW_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 1)
+#define HSW_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 2)
+#define HSW_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 3)
+#define HSW_FBCQ_DIS REG_BIT(22)
+#define HSW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(15) /* hsw */
+#define SKL_PSR_MASK_PLANE_FLIP REG_BIT(11) /* skl+ */
+#define SKL_PLANE1_STRETCH_MAX_MASK REG_GENMASK(1, 0)
+#define SKL_PLANE1_STRETCH_MAX_X8 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 0)
+#define SKL_PLANE1_STRETCH_MAX_X4 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 1)
+#define SKL_PLANE1_STRETCH_MAX_X2 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 2)
+#define SKL_PLANE1_STRETCH_MAX_X1 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 3)
+#define BDW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(0) /* bdw */
+
#define _CHICKEN_TRANS_A 0x420c0
#define _CHICKEN_TRANS_B 0x420c4
#define _CHICKEN_TRANS_C 0x420c8
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bc466d8c8c60..10928e8406dc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -879,28 +879,6 @@
#define CHICKEN_PAR2_1 _MMIO(0x42090)
#define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT REG_BIT(14)
-#define _CHICKEN_PIPESL_1_A 0x420b0
-#define _CHICKEN_PIPESL_1_B 0x420b4
-#define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
-#define HSW_PRI_STRETCH_MAX_MASK REG_GENMASK(28, 27)
-#define HSW_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 0)
-#define HSW_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 1)
-#define HSW_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 2)
-#define HSW_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 3)
-#define HSW_SPR_STRETCH_MAX_MASK REG_GENMASK(26, 25)
-#define HSW_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 0)
-#define HSW_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 1)
-#define HSW_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 2)
-#define HSW_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 3)
-#define HSW_FBCQ_DIS REG_BIT(22)
-#define HSW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(15) /* hsw */
-#define SKL_PSR_MASK_PLANE_FLIP REG_BIT(11) /* skl+ */
-#define SKL_PLANE1_STRETCH_MAX_MASK REG_GENMASK(1, 0)
-#define SKL_PLANE1_STRETCH_MAX_X8 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 0)
-#define SKL_PLANE1_STRETCH_MAX_X4 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 1)
-#define SKL_PLANE1_STRETCH_MAX_X2 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 2)
-#define SKL_PLANE1_STRETCH_MAX_X1 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 3)
-#define BDW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(0) /* bdw */
#define DISP_ARB_CTL _MMIO(0x45000)
#define DISP_FBC_MEMORY_WAKE REG_BIT(31)
--
2.50.1
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [v3 09/19] drm/i915: Remove i915_reg.h from intel_overlay.c
2026-01-29 21:13 [v3 00/19] Make Display free from i915_reg.h Uma Shankar
` (9 preceding siblings ...)
2026-01-29 21:13 ` [v3 08/19] drm/i915: Remove i915_reg.h from intel_display.c Uma Shankar
@ 2026-01-29 21:13 ` Uma Shankar
2026-02-03 12:39 ` Jani Nikula
2026-01-29 21:13 ` [v3 10/19] drm/i915: Remove i915_reg.h from g4x_dp.c Uma Shankar
` (11 subsequent siblings)
22 siblings, 1 reply; 43+ messages in thread
From: Uma Shankar @ 2026-01-29 21:13 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, ville.syrjala, Uma Shankar
Move GEN2_ISR and some interrupt definitions to common header.
This removes dependency of i915_reg.h from intel_overlay.c.
v2: Create a separate file for common interrupts (Jani)
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
.../gpu/drm/i915/display/intel_display_irq.c | 1 +
.../gpu/drm/i915/display/intel_display_regs.h | 2 +
drivers/gpu/drm/i915/display/intel_overlay.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt.c | 1 +
.../gpu/drm/i915/gt/intel_ring_submission.c | 1 +
drivers/gpu/drm/i915/i915_irq.c | 1 +
drivers/gpu/drm/i915/i915_reg.h | 37 ----------------
include/drm/intel/intel_gmd_interrupt.h | 43 +++++++++++++++++++
8 files changed, 50 insertions(+), 38 deletions(-)
create mode 100644 include/drm/intel/intel_gmd_interrupt.h
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 0a71840041de..31c78dc3d63b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -5,6 +5,7 @@
#include <drm/drm_print.h>
#include <drm/drm_vblank.h>
+#include <drm/intel/intel_gmd_interrupt.h>
#include "i915_reg.h"
#include "icl_dsi_regs.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 706024c2a463..40538910cb09 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -94,6 +94,8 @@
#define VLV_ERROR_PAGE_TABLE (1 << 4)
#define VLV_ERROR_CLAIM (1 << 0)
+#define GEN2_ISR _MMIO(0x20ac)
+
#define VLV_ERROR_REGS I915_ERROR_REGS(VLV_EMR, VLV_EIR)
#define _MBUS_ABOX0_CTL 0x45038
diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c
index 88eb7ae5765c..3a45836b8373 100644
--- a/drivers/gpu/drm/i915/display/intel_overlay.c
+++ b/drivers/gpu/drm/i915/display/intel_overlay.c
@@ -28,6 +28,7 @@
#include <drm/drm_fourcc.h>
#include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_interrupt.h>
#include "gem/i915_gem_internal.h"
#include "gem/i915_gem_object_frontbuffer.h"
@@ -37,7 +38,6 @@
#include "gt/intel_ring.h"
#include "i915_drv.h"
-#include "i915_reg.h"
#include "intel_color_regs.h"
#include "intel_de.h"
#include "intel_display_regs.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index ac527d878820..998dea65fcff 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -5,6 +5,7 @@
#include <drm/drm_managed.h>
#include <drm/intel/intel-gtt.h>
+#include <drm/intel/intel_gmd_interrupt.h>
#include "gem/i915_gem_internal.h"
#include "gem/i915_gem_lmem.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 8314a4b0505e..7391c9b2ceb5 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -4,6 +4,7 @@
*/
#include <drm/drm_cache.h>
+#include <drm/intel/intel_gmd_interrupt.h>
#include "gem/i915_gem_internal.h"
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 3fe978d4ea53..2acdd739335f 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -34,6 +34,7 @@
#include <drm/drm_drv.h>
#include <drm/drm_print.h>
#include <drm/intel/display_parent_interface.h>
+#include <drm/intel/intel_gmd_interrupt.h>
#include "display/intel_display_irq.h"
#include "display/intel_hotplug.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 10928e8406dc..22b68ddfa7b4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -365,7 +365,6 @@
#define GEN2_IER _MMIO(0x20a0)
#define GEN2_IIR _MMIO(0x20a4)
#define GEN2_IMR _MMIO(0x20a8)
-#define GEN2_ISR _MMIO(0x20ac)
#define GEN2_IRQ_REGS I915_IRQ_REGS(GEN2_IMR, \
GEN2_IER, \
@@ -522,42 +521,6 @@
/* These are all the "old" interrupts */
#define ILK_BSD_USER_INTERRUPT (1 << 5)
-#define I915_PM_INTERRUPT (1 << 31)
-#define I915_ISP_INTERRUPT (1 << 22)
-#define I915_LPE_PIPE_B_INTERRUPT (1 << 21)
-#define I915_LPE_PIPE_A_INTERRUPT (1 << 20)
-#define I915_MIPIC_INTERRUPT (1 << 19)
-#define I915_MIPIA_INTERRUPT (1 << 18)
-#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 18)
-#define I915_DISPLAY_PORT_INTERRUPT (1 << 17)
-#define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1 << 16)
-#define I915_MASTER_ERROR_INTERRUPT (1 << 15)
-#define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1 << 14)
-#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1 << 14) /* p-state */
-#define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1 << 13)
-#define I915_HWB_OOM_INTERRUPT (1 << 13)
-#define I915_LPE_PIPE_C_INTERRUPT (1 << 12)
-#define I915_SYNC_STATUS_INTERRUPT (1 << 12)
-#define I915_MISC_INTERRUPT (1 << 11)
-#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1 << 11)
-#define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1 << 10)
-#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1 << 10)
-#define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1 << 9)
-#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1 << 9)
-#define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1 << 8)
-#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1 << 8)
-#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1 << 7)
-#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1 << 6)
-#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1 << 5)
-#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1 << 4)
-#define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1 << 3)
-#define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1 << 2)
-#define I915_DEBUG_INTERRUPT (1 << 2)
-#define I915_WINVALID_INTERRUPT (1 << 1)
-#define I915_USER_INTERRUPT (1 << 1)
-#define I915_ASLE_INTERRUPT (1 << 0)
-#define I915_BSD_USER_INTERRUPT (1 << 25)
-
#define GEN6_BSD_RNCID _MMIO(0x12198)
#define GEN7_FF_THREAD_MODE _MMIO(0x20a0)
diff --git a/include/drm/intel/intel_gmd_interrupt.h b/include/drm/intel/intel_gmd_interrupt.h
new file mode 100644
index 000000000000..eae0acade16a
--- /dev/null
+++ b/include/drm/intel/intel_gmd_interrupt.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: MIT */
+/* Copyright © 2026 Intel Corporation */
+
+#ifndef _INTEL_GMD_INTERRUPT_H_
+#define _INTEL_GMD_INTERRUPT_H_
+
+#define I915_PM_INTERRUPT (1 << 31)
+#define I915_ISP_INTERRUPT (1 << 22)
+#define I915_LPE_PIPE_B_INTERRUPT (1 << 21)
+#define I915_LPE_PIPE_A_INTERRUPT (1 << 20)
+#define I915_MIPIC_INTERRUPT (1 << 19)
+#define I915_MIPIA_INTERRUPT (1 << 18)
+#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 18)
+#define I915_DISPLAY_PORT_INTERRUPT (1 << 17)
+#define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1 << 16)
+#define I915_MASTER_ERROR_INTERRUPT (1 << 15)
+#define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1 << 14)
+#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1 << 14) /* p-state */
+#define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1 << 13)
+#define I915_HWB_OOM_INTERRUPT (1 << 13)
+#define I915_LPE_PIPE_C_INTERRUPT (1 << 12)
+#define I915_SYNC_STATUS_INTERRUPT (1 << 12)
+#define I915_MISC_INTERRUPT (1 << 11)
+#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1 << 11)
+#define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1 << 10)
+#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1 << 10)
+#define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1 << 9)
+#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1 << 9)
+#define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1 << 8)
+#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1 << 8)
+#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1 << 7)
+#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1 << 6)
+#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1 << 5)
+#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1 << 4)
+#define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1 << 3)
+#define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1 << 2)
+#define I915_DEBUG_INTERRUPT (1 << 2)
+#define I915_WINVALID_INTERRUPT (1 << 1)
+#define I915_USER_INTERRUPT (1 << 1)
+#define I915_ASLE_INTERRUPT (1 << 0)
+#define I915_BSD_USER_INTERRUPT (1 << 25)
+
+#endif
--
2.50.1
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [v3 10/19] drm/i915: Remove i915_reg.h from g4x_dp.c
2026-01-29 21:13 [v3 00/19] Make Display free from i915_reg.h Uma Shankar
` (10 preceding siblings ...)
2026-01-29 21:13 ` [v3 09/19] drm/i915: Remove i915_reg.h from intel_overlay.c Uma Shankar
@ 2026-01-29 21:13 ` Uma Shankar
2026-02-03 12:40 ` Jani Nikula
2026-01-29 21:13 ` [v3 11/19] drm/i915: Remove i915_reg.h from i9xx_wm.c Uma Shankar
` (10 subsequent siblings)
22 siblings, 1 reply; 43+ messages in thread
From: Uma Shankar @ 2026-01-29 21:13 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, ville.syrjala, Uma Shankar
Move DE_IRQ_REGS to display header to make g4x_dp.c
free from i915_reg.h dependency. These registers are
only used by display and gvt.
v2: Move DE interrupt regs from common to display header (Jani)
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/g4x_dp.c | 2 +-
.../gpu/drm/i915/display/intel_display_regs.h | 16 ++++++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 15 ---------------
3 files changed, 17 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
index 4cb753177fd8..017c6dd8f9f6 100644
--- a/drivers/gpu/drm/i915/display/g4x_dp.c
+++ b/drivers/gpu/drm/i915/display/g4x_dp.c
@@ -8,9 +8,9 @@
#include <linux/string_helpers.h>
#include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_interrupt.h>
#include "g4x_dp.h"
-#include "i915_reg.h"
#include "intel_audio.h"
#include "intel_backlight.h"
#include "intel_connector.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 40538910cb09..0164dcbb709f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -1049,6 +1049,15 @@
#define SWF3(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4)
#define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4)
+#define DEISR _MMIO(0x44000)
+#define DEIMR _MMIO(0x44004)
+#define DEIIR _MMIO(0x44008)
+#define DEIER _MMIO(0x4400c)
+
+#define DE_IRQ_REGS I915_IRQ_REGS(DEIMR, \
+ DEIER, \
+ DEIIR)
+
#define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030)
#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
#define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */
@@ -1792,6 +1801,13 @@
SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \
SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1))
+/* PCH */
+
+#define SDEISR _MMIO(0xc4000)
+#define SDEIMR _MMIO(0xc4004)
+#define SDEIIR _MMIO(0xc4008)
+#define SDEIER _MMIO(0xc400c)
+
#define SDE_IRQ_REGS I915_IRQ_REGS(SDEIMR, \
SDEIER, \
SDEIIR)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 22b68ddfa7b4..6cb72e6e9086 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -728,15 +728,6 @@
#define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */
#define MASTER_INTERRUPT_ENABLE (1 << 31)
-#define DEISR _MMIO(0x44000)
-#define DEIMR _MMIO(0x44004)
-#define DEIIR _MMIO(0x44008)
-#define DEIER _MMIO(0x4400c)
-
-#define DE_IRQ_REGS I915_IRQ_REGS(DEIMR, \
- DEIER, \
- DEIIR)
-
#define GTISR _MMIO(0x44010)
#define GTIMR _MMIO(0x44014)
#define GTIIR _MMIO(0x44018)
@@ -868,12 +859,6 @@
#define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14)
#define GMD_ID_STEP REG_GENMASK(5, 0)
-/* PCH */
-
-#define SDEISR _MMIO(0xc4000)
-#define SDEIMR _MMIO(0xc4004)
-#define SDEIIR _MMIO(0xc4008)
-#define SDEIER _MMIO(0xc400c)
/* Icelake PPS_DATA and _ECC DIP Registers.
* These are available for transcoders B,C and eDP.
--
2.50.1
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [v3 11/19] drm/i915: Remove i915_reg.h from i9xx_wm.c
2026-01-29 21:13 [v3 00/19] Make Display free from i915_reg.h Uma Shankar
` (11 preceding siblings ...)
2026-01-29 21:13 ` [v3 10/19] drm/i915: Remove i915_reg.h from g4x_dp.c Uma Shankar
@ 2026-01-29 21:13 ` Uma Shankar
2026-02-03 12:42 ` Jani Nikula
2026-02-03 16:27 ` Ville Syrjälä
2026-01-29 21:13 ` [v3 12/19] drm/{i915, xe}: Remove i915_reg.h from g4x_hdmi.c Uma Shankar
` (9 subsequent siblings)
22 siblings, 2 replies; 43+ messages in thread
From: Uma Shankar @ 2026-01-29 21:13 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, ville.syrjala, Uma Shankar
Move FW_BLC_SELF to common header to make i9xx_wm.c
free from i915_reg.h include. Introduce a common
intel_gmd_misc_regs.h to define common miscellaneous
register definitions across graphics and display.
v2: Introdue a common misc header for GMD
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/i9xx_wm.c | 2 +-
.../gpu/drm/i915/display/intel_display_regs.h | 8 ++++++-
drivers/gpu/drm/i915/i915_reg.h | 20 +-----------------
include/drm/intel/intel_gmd_misc_regs.h | 21 +++++++++++++++++++
4 files changed, 30 insertions(+), 21 deletions(-)
create mode 100644 include/drm/intel/intel_gmd_misc_regs.h
diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
index 39dfceb438ae..24f898efa9dd 100644
--- a/drivers/gpu/drm/i915/display/i9xx_wm.c
+++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
@@ -6,8 +6,8 @@
#include <linux/iopoll.h>
#include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_misc_regs.h>
-#include "i915_reg.h"
#include "i9xx_wm.h"
#include "i9xx_wm_regs.h"
#include "intel_atomic.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 0164dcbb709f..680020e590cb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -4,6 +4,7 @@
#ifndef __INTEL_DISPLAY_REGS_H__
#define __INTEL_DISPLAY_REGS_H__
+#include <drm/intel/intel_gmd_misc_regs.h>
#include "intel_display_reg_defs.h"
#define GU_CNTL_PROTECTED _MMIO(0x10100C)
@@ -3119,6 +3120,11 @@ enum skl_power_gate {
#define MTL_TRAS_MASK REG_GENMASK(16, 8)
#define MTL_TRDPRE_MASK REG_GENMASK(7, 0)
-
+#define FW_BLC _MMIO(0x20d8)
+#define FW_BLC2 _MMIO(0x20dc)
+#define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */
+#define FW_BLC_SELF_EN_MASK REG_BIT(31)
+#define FW_BLC_SELF_FIFO_MASK REG_BIT(16) /* 945 only */
+#define FW_BLC_SELF_EN REG_BIT(15) /* 945 only */
#endif /* __INTEL_DISPLAY_REGS_H__ */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6cb72e6e9086..b4b749e52b5b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -26,6 +26,7 @@
#define _I915_REG_H_
#include <drm/intel/intel_pcode.h>
+#include <drm/intel/intel_gmd_misc_regs.h>
#include "i915_reg_defs.h"
#include "display/intel_display_reg_defs.h"
@@ -394,24 +395,10 @@
#define GEN2_ERROR_REGS I915_ERROR_REGS(EMR, EIR)
-#define INSTPM _MMIO(0x20c0)
-#define INSTPM_SELF_EN (1 << 12) /* 915GM only */
-#define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts
- will not assert AGPBUSY# and will only
- be delivered when out of C3. */
-#define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */
-#define INSTPM_TLB_INVALIDATE (1 << 9)
-#define INSTPM_SYNC_FLUSH (1 << 5)
#define MEM_MODE _MMIO(0x20cc)
#define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */
#define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */
#define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) /* 85x only */
-#define FW_BLC _MMIO(0x20d8)
-#define FW_BLC2 _MMIO(0x20dc)
-#define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */
-#define FW_BLC_SELF_EN_MASK REG_BIT(31)
-#define FW_BLC_SELF_FIFO_MASK REG_BIT(16) /* 945 only */
-#define FW_BLC_SELF_EN REG_BIT(15) /* 945 only */
#define MM_BURST_LENGTH 0x00700000
#define MM_FIFO_WATERMARK 0x0001F000
#define LM_BURST_LENGTH 0x00000700
@@ -834,11 +821,6 @@
#define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT REG_BIT(14)
-#define DISP_ARB_CTL _MMIO(0x45000)
-#define DISP_FBC_MEMORY_WAKE REG_BIT(31)
-#define DISP_TILE_SURFACE_SWIZZLING REG_BIT(13)
-#define DISP_FBC_WM_DIS REG_BIT(15)
-
#define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
#define _LATENCY_REPORTING_REMOVED_PIPE_D REG_BIT(31)
#define SKL_SELECT_ALTERNATE_DC_EXIT REG_BIT(30)
diff --git a/include/drm/intel/intel_gmd_misc_regs.h b/include/drm/intel/intel_gmd_misc_regs.h
new file mode 100644
index 000000000000..377f4e383699
--- /dev/null
+++ b/include/drm/intel/intel_gmd_misc_regs.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: MIT */
+/* Copyright © 2026 Intel Corporation */
+
+#ifndef _INTEL_GMD_MISC_REG_H_
+#define _INTEL_GMD_MISC_REG_H_
+
+#define DISP_ARB_CTL _MMIO(0x45000)
+#define DISP_FBC_MEMORY_WAKE REG_BIT(31)
+#define DISP_TILE_SURFACE_SWIZZLING REG_BIT(13)
+#define DISP_FBC_WM_DIS REG_BIT(15)
+
+#define INSTPM _MMIO(0x20c0)
+#define INSTPM_SELF_EN (1 << 12) /* 915GM only */
+#define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts
+ will not assert AGPBUSY# and will only
+ be delivered when out of C3. */
+#define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */
+#define INSTPM_TLB_INVALIDATE (1 << 9)
+#define INSTPM_SYNC_FLUSH (1 << 5)
+
+#endif
--
2.50.1
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [v3 12/19] drm/{i915, xe}: Remove i915_reg.h from g4x_hdmi.c
2026-01-29 21:13 [v3 00/19] Make Display free from i915_reg.h Uma Shankar
` (12 preceding siblings ...)
2026-01-29 21:13 ` [v3 11/19] drm/i915: Remove i915_reg.h from i9xx_wm.c Uma Shankar
@ 2026-01-29 21:13 ` Uma Shankar
2026-01-29 21:13 ` [v3 13/19] drm/i915: Remove i915_reg.h from intel_rom.c Uma Shankar
` (8 subsequent siblings)
22 siblings, 0 replies; 43+ messages in thread
From: Uma Shankar @ 2026-01-29 21:13 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, ville.syrjala, Uma Shankar
Move TRANS_CHICKEN1 reg to display header to make g4x_hdmi.c
free from i915_reg.h dependency.
v2: Remove from common header in include and use display_regs.h (Jani)
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/g4x_hdmi.c | 1 -
drivers/gpu/drm/i915/display/intel_display_regs.h | 12 ++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 12 ------------
3 files changed, 12 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.c b/drivers/gpu/drm/i915/display/g4x_hdmi.c
index 8b22447e8e23..5fe5067c4237 100644
--- a/drivers/gpu/drm/i915/display/g4x_hdmi.c
+++ b/drivers/gpu/drm/i915/display/g4x_hdmi.c
@@ -8,7 +8,6 @@
#include <drm/drm_print.h>
#include "g4x_hdmi.h"
-#include "i915_reg.h"
#include "intel_atomic.h"
#include "intel_audio.h"
#include "intel_connector.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 680020e590cb..5679a83ff19b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -2145,6 +2145,18 @@
#define TRANS_BPC_6 REG_FIELD_PREP(TRANS_BPC_MASK, 2)
#define TRANS_BPC_12 REG_FIELD_PREP(TRANS_BPC_MASK, 3)
+/* Icelake PPS_DATA and _ECC DIP Registers.
+ * These are available for transcoders B,C and eDP.
+ * Adding the _A so as to reuse the _MMIO_TRANS2
+ * definition, with which it offsets to the right location.
+ */
+
+#define _TRANSA_CHICKEN1 0xf0060
+#define _TRANSB_CHICKEN1 0xf1060
+#define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
+#define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE REG_BIT(10)
+#define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE REG_BIT(4)
+
#define _TRANSA_CHICKEN2 0xf0064
#define _TRANSB_CHICKEN2 0xf1064
#define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b4b749e52b5b..635726f01e9a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -842,18 +842,6 @@
#define GMD_ID_STEP REG_GENMASK(5, 0)
-/* Icelake PPS_DATA and _ECC DIP Registers.
- * These are available for transcoders B,C and eDP.
- * Adding the _A so as to reuse the _MMIO_TRANS2
- * definition, with which it offsets to the right location.
- */
-
-#define _TRANSA_CHICKEN1 0xf0060
-#define _TRANSB_CHICKEN1 0xf1060
-#define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
-#define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE REG_BIT(10)
-#define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE REG_BIT(4)
-
#define VLV_PMWGICZ _MMIO(0x1300a4)
#define HSW_EDRAM_CAP _MMIO(0x120010)
--
2.50.1
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [v3 13/19] drm/i915: Remove i915_reg.h from intel_rom.c
2026-01-29 21:13 [v3 00/19] Make Display free from i915_reg.h Uma Shankar
` (13 preceding siblings ...)
2026-01-29 21:13 ` [v3 12/19] drm/{i915, xe}: Remove i915_reg.h from g4x_hdmi.c Uma Shankar
@ 2026-01-29 21:13 ` Uma Shankar
2026-02-03 16:22 ` Ville Syrjälä
2026-01-29 21:13 ` [v3 14/19] drm/i915: Remove i915_reg.h from intel_psr.c Uma Shankar
` (7 subsequent siblings)
22 siblings, 1 reply; 43+ messages in thread
From: Uma Shankar @ 2026-01-29 21:13 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, ville.syrjala, Uma Shankar
Make intel_rom.c free from including i915_reg.h.
v3: Update patch header
v2: Use display header instead of gmd common include (Jani)
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_regs.h | 8 ++++++++
drivers/gpu/drm/i915/display/intel_rom.c | 3 +--
drivers/gpu/drm/i915/i915_reg.h | 8 --------
3 files changed, 9 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 5679a83ff19b..3707c5999ffb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -10,6 +10,14 @@
#define GU_CNTL_PROTECTED _MMIO(0x10100C)
#define DEPRESENT REG_BIT(9)
+#define PRIMARY_SPI_TRIGGER _MMIO(0x102040)
+#define PRIMARY_SPI_ADDRESS _MMIO(0x102080)
+#define PRIMARY_SPI_REGIONID _MMIO(0x102084)
+#define SPI_STATIC_REGIONS _MMIO(0x102090)
+#define OPTIONROM_SPI_REGIONID_MASK REG_GENMASK(7, 0)
+#define OROM_OFFSET _MMIO(0x1020c0)
+#define OROM_OFFSET_MASK REG_GENMASK(20, 16)
+
#define _GEN7_PIPEA_DE_LOAD_SL 0x70068
#define _GEN7_PIPEB_DE_LOAD_SL 0x71068
#define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL)
diff --git a/drivers/gpu/drm/i915/display/intel_rom.c b/drivers/gpu/drm/i915/display/intel_rom.c
index c8f615315310..d7de53acaba9 100644
--- a/drivers/gpu/drm/i915/display/intel_rom.c
+++ b/drivers/gpu/drm/i915/display/intel_rom.c
@@ -7,10 +7,9 @@
#include <drm/drm_device.h>
-#include "i915_reg.h"
-
#include "intel_rom.h"
#include "intel_uncore.h"
+#include "intel_display_regs.h"
struct intel_rom {
/* for PCI ROM */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 635726f01e9a..f896ece3b568 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -898,14 +898,6 @@
#define SGGI_DIS REG_BIT(15)
#define SGR_DIS REG_BIT(13)
-#define PRIMARY_SPI_TRIGGER _MMIO(0x102040)
-#define PRIMARY_SPI_ADDRESS _MMIO(0x102080)
-#define PRIMARY_SPI_REGIONID _MMIO(0x102084)
-#define SPI_STATIC_REGIONS _MMIO(0x102090)
-#define OPTIONROM_SPI_REGIONID_MASK REG_GENMASK(7, 0)
-#define OROM_OFFSET _MMIO(0x1020c0)
-#define OROM_OFFSET_MASK REG_GENMASK(20, 16)
-
#define MTL_MEDIA_GSI_BASE 0x380000
#endif /* _I915_REG_H_ */
--
2.50.1
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [v3 14/19] drm/i915: Remove i915_reg.h from intel_psr.c
2026-01-29 21:13 [v3 00/19] Make Display free from i915_reg.h Uma Shankar
` (14 preceding siblings ...)
2026-01-29 21:13 ` [v3 13/19] drm/i915: Remove i915_reg.h from intel_rom.c Uma Shankar
@ 2026-01-29 21:13 ` Uma Shankar
2026-01-29 21:13 ` [v3 15/19] drm/i915: Remove i915_reg.h from intel_fifo_underrun.c Uma Shankar
` (6 subsequent siblings)
22 siblings, 0 replies; 43+ messages in thread
From: Uma Shankar @ 2026-01-29 21:13 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, ville.syrjala, Uma Shankar
Move some chicken registers to display header to make
intel_psr.c free from including i915_reg.h.
v3: Update commit header
v2: Use display header instead of gmd common include (Jani)
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
.../gpu/drm/i915/display/intel_display_regs.h | 26 +++++++++++++++++
drivers/gpu/drm/i915/display/intel_psr.c | 1 -
drivers/gpu/drm/i915/i915_reg.h | 28 -------------------
3 files changed, 26 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 3707c5999ffb..23626ee2d4ce 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -366,6 +366,32 @@
#define OGAMC1 _MMIO(0x30020)
#define OGAMC0 _MMIO(0x30024)
+#define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
+#define _LATENCY_REPORTING_REMOVED_PIPE_D REG_BIT(31)
+#define SKL_SELECT_ALTERNATE_DC_EXIT REG_BIT(30)
+#define _LATENCY_REPORTING_REMOVED_PIPE_C REG_BIT(25)
+#define _LATENCY_REPORTING_REMOVED_PIPE_B REG_BIT(24)
+#define _LATENCY_REPORTING_REMOVED_PIPE_A REG_BIT(23)
+#define LATENCY_REPORTING_REMOVED(pipe) _PICK((pipe), \
+ _LATENCY_REPORTING_REMOVED_PIPE_A, \
+ _LATENCY_REPORTING_REMOVED_PIPE_B, \
+ _LATENCY_REPORTING_REMOVED_PIPE_C, \
+ _LATENCY_REPORTING_REMOVED_PIPE_D)
+#define ICL_DELAY_PMRSP REG_BIT(22)
+#define DISABLE_FLR_SRC REG_BIT(15)
+#define MASK_WAKEMEM REG_BIT(13)
+#define DDI_CLOCK_REG_ACCESS REG_BIT(7)
+
+#define CHICKEN_PAR1_1 _MMIO(0x42080)
+#define IGNORE_KVMR_PIPE_A REG_BIT(23)
+#define KBL_ARB_FILL_SPARE_22 REG_BIT(22)
+#define DIS_RAM_BYPASS_PSR2_MAN_TRACK REG_BIT(16)
+#define SKL_DE_COMPRESSED_HASH_MODE REG_BIT(15)
+#define HSW_MASK_VBL_TO_PIPE_IN_SRD REG_BIT(15) /* hsw/bdw */
+#define FORCE_ARB_IDLE_PLANES REG_BIT(14)
+#define SKL_EDP_PSR_FIX_RDWRAP REG_BIT(3)
+#define IGNORE_PSR2_HW_TRACKING REG_BIT(1)
+
#define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C)
#define BXT_GMBUS_GATING_DIS (1 << 14)
#define DG2_DPFC_GATING_DIS REG_BIT(31)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 62208ffc5101..bde7dbfe15a8 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -29,7 +29,6 @@
#include <drm/drm_print.h>
#include <drm/drm_vblank.h>
-#include "i915_reg.h"
#include "intel_alpm.h"
#include "intel_atomic.h"
#include "intel_crtc.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f896ece3b568..b23ac1b8f495 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -807,41 +807,13 @@
#define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE REG_BIT(5)
#define CHICKEN3_DGMG_DONE_FIX_DISABLE REG_BIT(2)
-#define CHICKEN_PAR1_1 _MMIO(0x42080)
-#define IGNORE_KVMR_PIPE_A REG_BIT(23)
-#define KBL_ARB_FILL_SPARE_22 REG_BIT(22)
-#define DIS_RAM_BYPASS_PSR2_MAN_TRACK REG_BIT(16)
-#define SKL_DE_COMPRESSED_HASH_MODE REG_BIT(15)
-#define HSW_MASK_VBL_TO_PIPE_IN_SRD REG_BIT(15) /* hsw/bdw */
-#define FORCE_ARB_IDLE_PLANES REG_BIT(14)
-#define SKL_EDP_PSR_FIX_RDWRAP REG_BIT(3)
-#define IGNORE_PSR2_HW_TRACKING REG_BIT(1)
-
#define CHICKEN_PAR2_1 _MMIO(0x42090)
#define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT REG_BIT(14)
-
-#define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
-#define _LATENCY_REPORTING_REMOVED_PIPE_D REG_BIT(31)
-#define SKL_SELECT_ALTERNATE_DC_EXIT REG_BIT(30)
-#define _LATENCY_REPORTING_REMOVED_PIPE_C REG_BIT(25)
-#define _LATENCY_REPORTING_REMOVED_PIPE_B REG_BIT(24)
-#define _LATENCY_REPORTING_REMOVED_PIPE_A REG_BIT(23)
-#define LATENCY_REPORTING_REMOVED(pipe) _PICK((pipe), \
- _LATENCY_REPORTING_REMOVED_PIPE_A, \
- _LATENCY_REPORTING_REMOVED_PIPE_B, \
- _LATENCY_REPORTING_REMOVED_PIPE_C, \
- _LATENCY_REPORTING_REMOVED_PIPE_D)
-#define ICL_DELAY_PMRSP REG_BIT(22)
-#define DISABLE_FLR_SRC REG_BIT(15)
-#define MASK_WAKEMEM REG_BIT(13)
-#define DDI_CLOCK_REG_ACCESS REG_BIT(7)
-
#define GMD_ID_ARCH_MASK REG_GENMASK(31, 22)
#define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14)
#define GMD_ID_STEP REG_GENMASK(5, 0)
-
#define VLV_PMWGICZ _MMIO(0x1300a4)
#define HSW_EDRAM_CAP _MMIO(0x120010)
--
2.50.1
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [v3 15/19] drm/i915: Remove i915_reg.h from intel_fifo_underrun.c
2026-01-29 21:13 [v3 00/19] Make Display free from i915_reg.h Uma Shankar
` (15 preceding siblings ...)
2026-01-29 21:13 ` [v3 14/19] drm/i915: Remove i915_reg.h from intel_psr.c Uma Shankar
@ 2026-01-29 21:13 ` Uma Shankar
2026-02-03 12:47 ` Jani Nikula
2026-01-29 21:13 ` [v3 16/19] drm/i915: Remove i915_reg.h from intel_display_irq.c Uma Shankar
` (5 subsequent siblings)
22 siblings, 1 reply; 43+ messages in thread
From: Uma Shankar @ 2026-01-29 21:13 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, ville.syrjala, Uma Shankar
Move GEN7_ERR_INT reg to common header to make intel_fifo_underrun.c
free from including i915_reg.h.
v2: Move GEN7_ERR_INT regs to display header (Jani)
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
.../gpu/drm/i915/display/intel_display_regs.h | 23 +++++++++++++++++++
.../drm/i915/display/intel_fifo_underrun.c | 1 -
drivers/gpu/drm/i915/i915_reg.h | 23 -------------------
3 files changed, 23 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 23626ee2d4ce..ab2ef267c9ce 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -91,6 +91,29 @@
#define DERRMR_PIPEC_VBLANK (1 << 21)
#define DERRMR_PIPEC_HBLANK (1 << 22)
+#define GEN7_ERR_INT _MMIO(0x44040)
+#define ERR_INT_POISON (1 << 31)
+#define ERR_INT_INVALID_GTT_PTE (1 << 29)
+#define ERR_INT_INVALID_PTE_DATA (1 << 28)
+#define ERR_INT_SPRITE_C_FAULT (1 << 23)
+#define ERR_INT_PRIMARY_C_FAULT (1 << 22)
+#define ERR_INT_CURSOR_C_FAULT (1 << 21)
+#define ERR_INT_SPRITE_B_FAULT (1 << 20)
+#define ERR_INT_PRIMARY_B_FAULT (1 << 19)
+#define ERR_INT_CURSOR_B_FAULT (1 << 18)
+#define ERR_INT_SPRITE_A_FAULT (1 << 17)
+#define ERR_INT_PRIMARY_A_FAULT (1 << 16)
+#define ERR_INT_CURSOR_A_FAULT (1 << 15)
+#define ERR_INT_MMIO_UNCLAIMED (1 << 13)
+#define ERR_INT_PIPE_CRC_DONE_C (1 << 8)
+#define ERR_INT_FIFO_UNDERRUN_C (1 << 6)
+#define ERR_INT_PIPE_CRC_DONE_B (1 << 5)
+#define ERR_INT_FIFO_UNDERRUN_B (1 << 3)
+#define ERR_INT_PIPE_CRC_DONE_A (1 << 2)
+#define ERR_INT_PIPE_CRC_DONE(pipe) (1 << (2 + (pipe) * 3))
+#define ERR_INT_FIFO_UNDERRUN_A (1 << 0)
+#define ERR_INT_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3))
+
#define VLV_IRQ_REGS I915_IRQ_REGS(VLV_IMR, \
VLV_IER, \
VLV_IIR)
diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
index b413b3e871d8..bf047180def9 100644
--- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
+++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
@@ -29,7 +29,6 @@
#include <drm/drm_print.h>
-#include "i915_reg.h"
#include "intel_de.h"
#include "intel_display_irq.h"
#include "intel_display_regs.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b23ac1b8f495..611ae5861450 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -327,29 +327,6 @@
#define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070)
#define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074)
-#define GEN7_ERR_INT _MMIO(0x44040)
-#define ERR_INT_POISON (1 << 31)
-#define ERR_INT_INVALID_GTT_PTE (1 << 29)
-#define ERR_INT_INVALID_PTE_DATA (1 << 28)
-#define ERR_INT_SPRITE_C_FAULT (1 << 23)
-#define ERR_INT_PRIMARY_C_FAULT (1 << 22)
-#define ERR_INT_CURSOR_C_FAULT (1 << 21)
-#define ERR_INT_SPRITE_B_FAULT (1 << 20)
-#define ERR_INT_PRIMARY_B_FAULT (1 << 19)
-#define ERR_INT_CURSOR_B_FAULT (1 << 18)
-#define ERR_INT_SPRITE_A_FAULT (1 << 17)
-#define ERR_INT_PRIMARY_A_FAULT (1 << 16)
-#define ERR_INT_CURSOR_A_FAULT (1 << 15)
-#define ERR_INT_MMIO_UNCLAIMED (1 << 13)
-#define ERR_INT_PIPE_CRC_DONE_C (1 << 8)
-#define ERR_INT_FIFO_UNDERRUN_C (1 << 6)
-#define ERR_INT_PIPE_CRC_DONE_B (1 << 5)
-#define ERR_INT_FIFO_UNDERRUN_B (1 << 3)
-#define ERR_INT_PIPE_CRC_DONE_A (1 << 2)
-#define ERR_INT_PIPE_CRC_DONE(pipe) (1 << (2 + (pipe) * 3))
-#define ERR_INT_FIFO_UNDERRUN_A (1 << 0)
-#define ERR_INT_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3))
-
#define FPGA_DBG _MMIO(0x42300)
#define FPGA_DBG_RM_NOCLAIM REG_BIT(31)
--
2.50.1
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [v3 16/19] drm/i915: Remove i915_reg.h from intel_display_irq.c
2026-01-29 21:13 [v3 00/19] Make Display free from i915_reg.h Uma Shankar
` (16 preceding siblings ...)
2026-01-29 21:13 ` [v3 15/19] drm/i915: Remove i915_reg.h from intel_fifo_underrun.c Uma Shankar
@ 2026-01-29 21:13 ` Uma Shankar
2026-01-29 21:13 ` [v3 17/19] drm/i915: Remove i915_reg.h from intel_display_power_well.c Uma Shankar
` (4 subsequent siblings)
22 siblings, 0 replies; 43+ messages in thread
From: Uma Shankar @ 2026-01-29 21:13 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, ville.syrjala, Uma Shankar
Move VLV_IRQ_REGS to common header for interrupt to make
intel_display_irq.c free from including i915_reg.h.
v2: Move interrupt to dedicated header (Jani)
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
.../gpu/drm/i915/display/intel_display_irq.c | 1 -
.../gpu/drm/i915/display/intel_display_regs.h | 5 ++
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 2 +
drivers/gpu/drm/i915/gt/intel_rc6.c | 1 +
drivers/gpu/drm/i915/gvt/handlers.c | 1 +
drivers/gpu/drm/i915/gvt/interrupt.c | 1 +
drivers/gpu/drm/i915/i915_reg.h | 52 -------------------
drivers/gpu/drm/i915/intel_clock_gating.c | 1 +
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 2 +
drivers/gpu/drm/i915/vlv_suspend.c | 1 +
include/drm/intel/intel_gmd_interrupt.h | 49 +++++++++++++++++
11 files changed, 63 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 31c78dc3d63b..5d80f0f4779c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -7,7 +7,6 @@
#include <drm/drm_vblank.h>
#include <drm/intel/intel_gmd_interrupt.h>
-#include "i915_reg.h"
#include "icl_dsi_regs.h"
#include "intel_crtc.h"
#include "intel_de.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index ab2ef267c9ce..4a9b7560ce8c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -1479,6 +1479,11 @@
#define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
#define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8 * (pipe)))
+/* Display Internal Timeout Register */
+#define RM_TIMEOUT _MMIO(0x42060)
+#define RM_TIMEOUT_REG_CAPTURE _MMIO(0x420E0)
+#define MMIO_TIMEOUT_US(us) ((us) << 0)
+
#define GEN8_DE_MISC_ISR _MMIO(0x44460)
#define GEN8_DE_MISC_IMR _MMIO(0x44464)
#define GEN8_DE_MISC_IIR _MMIO(0x44468)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index 75e802e10be2..702d8558aa69 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -5,6 +5,8 @@
#include <linux/sched/clock.h>
+#include <drm/intel/intel_gmd_interrupt.h>
+
#include "i915_drv.h"
#include "i915_irq.h"
#include "i915_reg.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index 286d49ecc449..dfda675f633a 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -7,6 +7,7 @@
#include <linux/string_helpers.h>
#include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_interrupt.h>
#include "display/vlv_clock.h"
#include "gem/i915_gem_region.h"
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 6f860c320afc..28541b0c7cb9 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -40,6 +40,7 @@
#include <drm/display/drm_dp.h>
#include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_interrupt.h>
#include "display/bxt_dpio_phy_regs.h"
#include "display/i9xx_plane_regs.h"
diff --git a/drivers/gpu/drm/i915/gvt/interrupt.c b/drivers/gpu/drm/i915/gvt/interrupt.c
index 91d22b1c62e2..92c4e2762032 100644
--- a/drivers/gpu/drm/i915/gvt/interrupt.c
+++ b/drivers/gpu/drm/i915/gvt/interrupt.c
@@ -32,6 +32,7 @@
#include <linux/eventfd.h>
#include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_interrupt.h>
#include "display/intel_display_regs.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 611ae5861450..9cd7fce09ebe 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -337,9 +337,6 @@
#define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030)
#define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034)
-#define SCPD0 _MMIO(0x209c) /* 915+ only */
-#define SCPD_FBC_IGNORE_3D (1 << 6)
-#define CSTATE_RENDER_CLOCK_GATE_DISABLE (1 << 5)
#define GEN2_IER _MMIO(0x20a0)
#define GEN2_IIR _MMIO(0x20a4)
#define GEN2_IMR _MMIO(0x20a8)
@@ -352,13 +349,6 @@
#define GINT_DIS (1 << 22)
#define GCFG_DIS (1 << 8)
#define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064)
-#define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084)
-#define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0)
-#define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4)
-#define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8)
-#define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac)
-#define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120)
-#define VLV_PCBR_ADDR_SHIFT 12
#define EIR _MMIO(0x20b0)
#define EMR _MMIO(0x20b4)
@@ -684,11 +674,6 @@
#define PCH_3DCGDIS1 _MMIO(0x46024)
# define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
-/* Display Internal Timeout Register */
-#define RM_TIMEOUT _MMIO(0x42060)
-#define RM_TIMEOUT_REG_CAPTURE _MMIO(0x420E0)
-#define MMIO_TIMEOUT_US(us) ((us) << 0)
-
#define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */
#define MASTER_INTERRUPT_ENABLE (1 << 31)
@@ -701,24 +686,6 @@
GTIER, \
GTIIR)
-#define GEN8_MASTER_IRQ _MMIO(0x44200)
-#define GEN8_MASTER_IRQ_CONTROL (1 << 31)
-#define GEN8_PCU_IRQ (1 << 30)
-#define GEN8_DE_PCH_IRQ (1 << 23)
-#define GEN8_DE_MISC_IRQ (1 << 22)
-#define GEN8_DE_PORT_IRQ (1 << 20)
-#define GEN8_DE_PIPE_C_IRQ (1 << 18)
-#define GEN8_DE_PIPE_B_IRQ (1 << 17)
-#define GEN8_DE_PIPE_A_IRQ (1 << 16)
-#define GEN8_DE_PIPE_IRQ(pipe) (1 << (16 + (pipe)))
-#define GEN8_GT_VECS_IRQ (1 << 6)
-#define GEN8_GT_GUC_IRQ (1 << 5)
-#define GEN8_GT_PM_IRQ (1 << 4)
-#define GEN8_GT_VCS1_IRQ (1 << 3) /* NB: VCS2 in bspec! */
-#define GEN8_GT_VCS0_IRQ (1 << 2) /* NB: VCS1 in bpsec! */
-#define GEN8_GT_BCS_IRQ (1 << 1)
-#define GEN8_GT_RCS_IRQ (1 << 0)
-
#define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which)))
#define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which)))
#define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
@@ -744,25 +711,6 @@
GEN8_PCU_IER, \
GEN8_PCU_IIR)
-#define GEN11_GU_MISC_ISR _MMIO(0x444f0)
-#define GEN11_GU_MISC_IMR _MMIO(0x444f4)
-#define GEN11_GU_MISC_IIR _MMIO(0x444f8)
-#define GEN11_GU_MISC_IER _MMIO(0x444fc)
-#define GEN11_GU_MISC_GSE (1 << 27)
-
-#define GEN11_GU_MISC_IRQ_REGS I915_IRQ_REGS(GEN11_GU_MISC_IMR, \
- GEN11_GU_MISC_IER, \
- GEN11_GU_MISC_IIR)
-
-#define GEN11_GFX_MSTR_IRQ _MMIO(0x190010)
-#define GEN11_MASTER_IRQ (1 << 31)
-#define GEN11_PCU_IRQ (1 << 30)
-#define GEN11_GU_MISC_IRQ (1 << 29)
-#define GEN11_DISPLAY_IRQ (1 << 16)
-#define GEN11_GT_DW_IRQ(x) (1 << (x))
-#define GEN11_GT_DW1_IRQ (1 << 1)
-#define GEN11_GT_DW0_IRQ (1 << 0)
-
#define DG1_MSTR_TILE_INTR _MMIO(0x190008)
#define DG1_MSTR_IRQ REG_BIT(31)
#define DG1_MSTR_TILE(t) REG_BIT(t)
diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
index 4e18d5a22112..627185c6d110 100644
--- a/drivers/gpu/drm/i915/intel_clock_gating.c
+++ b/drivers/gpu/drm/i915/intel_clock_gating.c
@@ -26,6 +26,7 @@
*/
#include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_interrupt.h>
#include "display/i9xx_plane_regs.h"
#include "display/intel_display.h"
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index c0154fd77fc9..b20d4eb0bfd2 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -3,6 +3,8 @@
* Copyright © 2020 Intel Corporation
*/
+#include <drm/intel/intel_gmd_interrupt.h>
+
#include "display/bxt_dpio_phy_regs.h"
#include "display/i9xx_plane_regs.h"
#include "display/i9xx_wm_regs.h"
diff --git a/drivers/gpu/drm/i915/vlv_suspend.c b/drivers/gpu/drm/i915/vlv_suspend.c
index bace7b38329b..e350f588cec1 100644
--- a/drivers/gpu/drm/i915/vlv_suspend.c
+++ b/drivers/gpu/drm/i915/vlv_suspend.c
@@ -7,6 +7,7 @@
#include <linux/kernel.h>
#include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_interrupt.h>
#include "gt/intel_gt_regs.h"
diff --git a/include/drm/intel/intel_gmd_interrupt.h b/include/drm/intel/intel_gmd_interrupt.h
index eae0acade16a..5c77b0aa96a2 100644
--- a/include/drm/intel/intel_gmd_interrupt.h
+++ b/include/drm/intel/intel_gmd_interrupt.h
@@ -40,4 +40,53 @@
#define I915_ASLE_INTERRUPT (1 << 0)
#define I915_BSD_USER_INTERRUPT (1 << 25)
+#define GEN8_MASTER_IRQ _MMIO(0x44200)
+#define GEN8_MASTER_IRQ_CONTROL (1 << 31)
+#define GEN8_PCU_IRQ (1 << 30)
+#define GEN8_DE_PCH_IRQ (1 << 23)
+#define GEN8_DE_MISC_IRQ (1 << 22)
+#define GEN8_DE_PORT_IRQ (1 << 20)
+#define GEN8_DE_PIPE_C_IRQ (1 << 18)
+#define GEN8_DE_PIPE_B_IRQ (1 << 17)
+#define GEN8_DE_PIPE_A_IRQ (1 << 16)
+#define GEN8_DE_PIPE_IRQ(pipe) (1 << (16 + (pipe)))
+#define GEN8_GT_VECS_IRQ (1 << 6)
+#define GEN8_GT_GUC_IRQ (1 << 5)
+#define GEN8_GT_PM_IRQ (1 << 4)
+#define GEN8_GT_VCS1_IRQ (1 << 3) /* NB: VCS2 in bspec! */
+#define GEN8_GT_VCS0_IRQ (1 << 2) /* NB: VCS1 in bpsec! */
+#define GEN8_GT_BCS_IRQ (1 << 1)
+#define GEN8_GT_RCS_IRQ (1 << 0)
+
+#define GEN11_GU_MISC_ISR _MMIO(0x444f0)
+#define GEN11_GU_MISC_IMR _MMIO(0x444f4)
+#define GEN11_GU_MISC_IIR _MMIO(0x444f8)
+#define GEN11_GU_MISC_IER _MMIO(0x444fc)
+#define GEN11_GU_MISC_GSE (1 << 27)
+
+#define GEN11_GU_MISC_IRQ_REGS I915_IRQ_REGS(GEN11_GU_MISC_IMR, \
+ GEN11_GU_MISC_IER, \
+ GEN11_GU_MISC_IIR)
+
+#define GEN11_GFX_MSTR_IRQ _MMIO(0x190010)
+#define GEN11_MASTER_IRQ (1 << 31)
+#define GEN11_PCU_IRQ (1 << 30)
+#define GEN11_GU_MISC_IRQ (1 << 29)
+#define GEN11_DISPLAY_IRQ (1 << 16)
+#define GEN11_GT_DW_IRQ(x) (1 << (x))
+#define GEN11_GT_DW1_IRQ (1 << 1)
+#define GEN11_GT_DW0_IRQ (1 << 0)
+
+#define SCPD0 _MMIO(0x209c) /* 915+ only */
+#define SCPD_FBC_IGNORE_3D (1 << 6)
+#define CSTATE_RENDER_CLOCK_GATE_DISABLE (1 << 5)
+
+#define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084)
+#define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0)
+#define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4)
+#define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8)
+#define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac)
+#define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120)
+#define VLV_PCBR_ADDR_SHIFT 12
+
#endif
--
2.50.1
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [v3 17/19] drm/i915: Remove i915_reg.h from intel_display_power_well.c
2026-01-29 21:13 [v3 00/19] Make Display free from i915_reg.h Uma Shankar
` (17 preceding siblings ...)
2026-01-29 21:13 ` [v3 16/19] drm/i915: Remove i915_reg.h from intel_display_irq.c Uma Shankar
@ 2026-01-29 21:13 ` Uma Shankar
2026-02-03 12:49 ` Jani Nikula
2026-02-03 16:34 ` Ville Syrjälä
2026-01-29 21:13 ` [v3 18/19] drm/i915: Remove i915_reg.h from intel_modeset_setup.c Uma Shankar
` (3 subsequent siblings)
22 siblings, 2 replies; 43+ messages in thread
From: Uma Shankar @ 2026-01-29 21:13 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, ville.syrjala, Uma Shankar
Make intel_display_power_well.c free from including i915_reg.h.
v2: Include specific pcode header, drop common header (Jani)
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_power_well.c | 2 +-
drivers/gpu/drm/i915/display/intel_display_regs.h | 2 ++
drivers/gpu/drm/i915/i915_reg.h | 3 ---
3 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 6f9bc6f9615e..f98de1baa63d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -6,8 +6,8 @@
#include <linux/iopoll.h>
#include <drm/drm_print.h>
+#include <drm/intel/intel_pcode.h>
-#include "i915_reg.h"
#include "intel_backlight_regs.h"
#include "intel_combo_phy.h"
#include "intel_combo_phy_regs.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 4a9b7560ce8c..758749c5c322 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -359,6 +359,8 @@
#define FW_CSPWRDWNEN (1 << 15)
#define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504)
+/* Disable display A/B trickle feed */
+#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
#define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508)
#define CDCLK_FREQ_SHIFT 4
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9cd7fce09ebe..e4fc61dcd384 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -428,9 +428,6 @@
#define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
#define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
-/* Disable display A/B trickle feed */
-#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
-
/* Set display plane priority */
#define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
#define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
--
2.50.1
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [v3 18/19] drm/i915: Remove i915_reg.h from intel_modeset_setup.c
2026-01-29 21:13 [v3 00/19] Make Display free from i915_reg.h Uma Shankar
` (18 preceding siblings ...)
2026-01-29 21:13 ` [v3 17/19] drm/i915: Remove i915_reg.h from intel_display_power_well.c Uma Shankar
@ 2026-01-29 21:13 ` Uma Shankar
2026-01-29 21:13 ` [v3 19/19] drm/{i915, xe}: Remove i915_reg.h from display Uma Shankar
` (2 subsequent siblings)
22 siblings, 0 replies; 43+ messages in thread
From: Uma Shankar @ 2026-01-29 21:13 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, ville.syrjala, Uma Shankar
Move GEN9_CLKGATE_DIS_0 reg to display header to make
intel_modeset_setup.c free from i915_reg.h include.
v2: Remove from gmd common header and use display_regs.h (Jani)
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_regs.h | 14 ++++++++++++++
drivers/gpu/drm/i915/display/intel_modeset_setup.c | 1 -
drivers/gpu/drm/i915/i915_reg.h | 14 --------------
3 files changed, 14 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 758749c5c322..ba1fb4c392e7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -417,6 +417,20 @@
#define SKL_EDP_PSR_FIX_RDWRAP REG_BIT(3)
#define IGNORE_PSR2_HW_TRACKING REG_BIT(1)
+/*
+ * GEN9 clock gating regs
+ */
+#define GEN9_CLKGATE_DIS_0 _MMIO(0x46530)
+#define DARBF_GATING_DIS REG_BIT(27)
+#define DMG_GATING_DIS REG_BIT(21)
+#define MTL_PIPEDMC_GATING_DIS(pipe) REG_BIT(15 - (pipe))
+#define PWM2_GATING_DIS REG_BIT(14)
+#define PWM1_GATING_DIS REG_BIT(13)
+
+#define GEN9_CLKGATE_DIS_3 _MMIO(0x46538)
+#define TGL_VRH_GATING_DIS REG_BIT(31)
+#define DPT_GATING_DIS REG_BIT(22)
+
#define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C)
#define BXT_GMBUS_GATING_DIS (1 << 14)
#define DG2_DPFC_GATING_DIS REG_BIT(31)
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index d10cbf69a5f8..9b0becee221c 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -11,7 +11,6 @@
#include <drm/drm_print.h>
#include <drm/drm_vblank.h>
-#include "i915_reg.h"
#include "i9xx_wm.h"
#include "intel_atomic.h"
#include "intel_bw.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e4fc61dcd384..c360843a2e35 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -629,20 +629,6 @@
#define VLV_CLK_CTL2 _MMIO(0x101104)
#define CLK_CTL2_CZCOUNT_30NS_SHIFT 28
-/*
- * GEN9 clock gating regs
- */
-#define GEN9_CLKGATE_DIS_0 _MMIO(0x46530)
-#define DARBF_GATING_DIS REG_BIT(27)
-#define DMG_GATING_DIS REG_BIT(21)
-#define MTL_PIPEDMC_GATING_DIS(pipe) REG_BIT(15 - (pipe))
-#define PWM2_GATING_DIS REG_BIT(14)
-#define PWM1_GATING_DIS REG_BIT(13)
-
-#define GEN9_CLKGATE_DIS_3 _MMIO(0x46538)
-#define TGL_VRH_GATING_DIS REG_BIT(31)
-#define DPT_GATING_DIS REG_BIT(22)
-
#define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028)
#define PIPEB_LINE_COMPARE_INT_EN REG_BIT(29)
#define PIPEB_HLINE_INT_EN REG_BIT(28)
--
2.50.1
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [v3 19/19] drm/{i915, xe}: Remove i915_reg.h from display
2026-01-29 21:13 [v3 00/19] Make Display free from i915_reg.h Uma Shankar
` (19 preceding siblings ...)
2026-01-29 21:13 ` [v3 18/19] drm/i915: Remove i915_reg.h from intel_modeset_setup.c Uma Shankar
@ 2026-01-29 21:13 ` Uma Shankar
2026-02-03 12:50 ` Jani Nikula
2026-01-29 21:27 ` ✗ CI.checksparse: warning for Make Display free from i915_reg.h (rev3) Patchwork
2026-01-29 21:45 ` ✓ Xe.CI.BAT: success " Patchwork
22 siblings, 1 reply; 43+ messages in thread
From: Uma Shankar @ 2026-01-29 21:13 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, ville.syrjala, Uma Shankar
Make display files free from including i915_reg.h.
v2: Include modular per component headers (Jani)
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/hsw_ips.c | 2 +-
drivers/gpu/drm/i915/display/i9xx_plane.c | 1 -
drivers/gpu/drm/i915/display/icl_dsi.c | 1 -
drivers/gpu/drm/i915/display/intel_backlight.c | 1 -
drivers/gpu/drm/i915/display/intel_bw.c | 2 +-
drivers/gpu/drm/i915/display/intel_casf.c | 1 -
drivers/gpu/drm/i915/display/intel_ddi.c | 1 -
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 1 -
drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
drivers/gpu/drm/i915/display/intel_display_wa.c | 1 -
drivers/gpu/drm/i915/display/intel_dmc.c | 1 -
drivers/gpu/drm/i915/display/intel_fdi.c | 1 -
drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
drivers/gpu/drm/i915/display/intel_hotplug_irq.c | 1 -
drivers/gpu/drm/i915/display/intel_lt_phy.c | 1 -
drivers/gpu/drm/i915/display/intel_pps.c | 1 -
drivers/gpu/drm/i915/display/intel_tc.c | 1 -
drivers/gpu/drm/i915/display/skl_watermark.c | 2 +-
drivers/gpu/drm/i915/display/vlv_dsi.c | 1 -
19 files changed, 5 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/hsw_ips.c b/drivers/gpu/drm/i915/display/hsw_ips.c
index 0caaea2e64e1..5697fa4eb11f 100644
--- a/drivers/gpu/drm/i915/display/hsw_ips.c
+++ b/drivers/gpu/drm/i915/display/hsw_ips.c
@@ -6,9 +6,9 @@
#include <linux/debugfs.h>
#include <drm/drm_print.h>
+#include <drm/intel/intel_pcode.h>
#include "hsw_ips.h"
-#include "i915_reg.h"
#include "intel_color_regs.h"
#include "intel_de.h"
#include "intel_display_regs.h"
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
index b1fecf178906..9c16753a1f3b 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -10,7 +10,6 @@
#include <drm/drm_fourcc.h>
#include <drm/drm_print.h>
-#include "i915_reg.h"
#include "i9xx_plane.h"
#include "i9xx_plane_regs.h"
#include "intel_atomic.h"
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index c8e0333706c1..7cf511a6c0f9 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -34,7 +34,6 @@
#include <drm/drm_print.h>
#include <drm/drm_probe_helper.h>
-#include "i915_reg.h"
#include "icl_dsi.h"
#include "icl_dsi_regs.h"
#include "intel_atomic.h"
diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c b/drivers/gpu/drm/i915/display/intel_backlight.c
index a68fdbd2acb9..34e95f05936e 100644
--- a/drivers/gpu/drm/i915/display/intel_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_backlight.c
@@ -12,7 +12,6 @@
#include <drm/drm_file.h>
#include <drm/drm_print.h>
-#include "i915_reg.h"
#include "intel_backlight.h"
#include "intel_backlight_regs.h"
#include "intel_connector.h"
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 8d84445c69f1..71149d8bcd73 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -5,8 +5,8 @@
#include <drm/drm_atomic_state_helper.h>
#include <drm/drm_print.h>
+#include <drm/intel/intel_pcode.h>
-#include "i915_reg.h"
#include "intel_bw.h"
#include "intel_crtc.h"
#include "intel_display_core.h"
diff --git a/drivers/gpu/drm/i915/display/intel_casf.c b/drivers/gpu/drm/i915/display/intel_casf.c
index 0fe4398a1a4e..b167af31de5b 100644
--- a/drivers/gpu/drm/i915/display/intel_casf.c
+++ b/drivers/gpu/drm/i915/display/intel_casf.c
@@ -3,7 +3,6 @@
#include <drm/drm_print.h>
-#include "i915_reg.h"
#include "intel_casf.h"
#include "intel_casf_regs.h"
#include "intel_de.h"
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index d8739e2bb004..3f0c9c7fd5f8 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -34,7 +34,6 @@
#include <drm/drm_print.h>
#include <drm/drm_privacy_screen_consumer.h>
-#include "i915_reg.h"
#include "icl_dsi.h"
#include "intel_alpm.h"
#include "intel_audio.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index aba13e8a9051..1ce28a31affb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -15,7 +15,6 @@
#include <drm/drm_print.h>
#include "hsw_ips.h"
-#include "i915_reg.h"
#include "i9xx_wm_regs.h"
#include "intel_alpm.h"
#include "intel_bo.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 06adf6afbec0..a6e9f1c8d2dc 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -7,8 +7,8 @@
#include <linux/string_helpers.h>
#include <drm/drm_print.h>
+#include <drm/intel/intel_pcode.h>
-#include "i915_reg.h"
#include "intel_backlight_regs.h"
#include "intel_cdclk.h"
#include "intel_clock_gating.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c b/drivers/gpu/drm/i915/display/intel_display_wa.c
index 2eb4af62d556..d9788a979561 100644
--- a/drivers/gpu/drm/i915/display/intel_display_wa.c
+++ b/drivers/gpu/drm/i915/display/intel_display_wa.c
@@ -5,7 +5,6 @@
#include <drm/drm_print.h>
-#include "i915_reg.h"
#include "intel_de.h"
#include "intel_display_core.h"
#include "intel_display_regs.h"
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 1182bc9a2e6d..8df06b993890 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -29,7 +29,6 @@
#include <drm/drm_file.h>
#include <drm/drm_print.h>
-#include "i915_reg.h"
#include "intel_crtc.h"
#include "intel_de.h"
#include "intel_display_power_well.h"
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
index 5bb0090dd5ed..24ce8a7842c7 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -8,7 +8,6 @@
#include <drm/drm_fixed.h>
#include <drm/drm_print.h>
-#include "i915_reg.h"
#include "intel_atomic.h"
#include "intel_crtc.h"
#include "intel_ddi.h"
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index b7479ced7871..6110a582437c 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -17,8 +17,8 @@
#include <drm/display/drm_hdcp_helper.h>
#include <drm/drm_print.h>
#include <drm/intel/i915_component.h>
+#include <drm/intel/intel_pcode.h>
-#include "i915_reg.h"
#include "intel_connector.h"
#include "intel_de.h"
#include "intel_display_jiffies.h"
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
index 82c39e4ffa37..8865cb2ac569 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
@@ -5,7 +5,6 @@
#include <drm/drm_print.h>
-#include "i915_reg.h"
#include "intel_de.h"
#include "intel_display_irq.h"
#include "intel_display_regs.h"
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 04f63bdd0b87..1df23447fd84 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -5,7 +5,6 @@
#include <drm/drm_print.h>
-#include "i915_reg.h"
#include "intel_cx0_phy.h"
#include "intel_cx0_phy_regs.h"
#include "intel_ddi.h"
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index b217ec7aa758..2d799af73bb7 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -9,7 +9,6 @@
#include <drm/drm_print.h>
#include "g4x_dp.h"
-#include "i915_reg.h"
#include "intel_de.h"
#include "intel_display_jiffies.h"
#include "intel_display_power_well.h"
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 064f572bbc85..78ed9c58a72f 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -7,7 +7,6 @@
#include <drm/drm_print.h>
-#include "i915_reg.h"
#include "intel_atomic.h"
#include "intel_cx0_phy_regs.h"
#include "intel_ddi.h"
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index b41da10f0f85..9efb94b4cbdb 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -7,8 +7,8 @@
#include <drm/drm_blend.h>
#include <drm/drm_print.h>
+#include <drm/intel/intel_pcode.h>
-#include "i915_reg.h"
#include "i9xx_wm.h"
#include "intel_atomic.h"
#include "intel_bw.h"
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
index d705af3bf8ba..67f0082d3a69 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
@@ -33,7 +33,6 @@
#include <drm/drm_print.h>
#include <drm/drm_probe_helper.h>
-#include "i915_reg.h"
#include "intel_atomic.h"
#include "intel_backlight.h"
#include "intel_connector.h"
--
2.50.1
^ permalink raw reply related [flat|nested] 43+ messages in thread
* ✗ CI.checksparse: warning for Make Display free from i915_reg.h (rev3)
2026-01-29 21:13 [v3 00/19] Make Display free from i915_reg.h Uma Shankar
` (20 preceding siblings ...)
2026-01-29 21:13 ` [v3 19/19] drm/{i915, xe}: Remove i915_reg.h from display Uma Shankar
@ 2026-01-29 21:27 ` Patchwork
2026-01-29 21:45 ` ✓ Xe.CI.BAT: success " Patchwork
22 siblings, 0 replies; 43+ messages in thread
From: Patchwork @ 2026-01-29 21:27 UTC (permalink / raw)
To: Uma Shankar; +Cc: intel-xe
== Series Details ==
Series: Make Display free from i915_reg.h (rev3)
URL : https://patchwork.freedesktop.org/series/159130/
State : warning
== Summary ==
+ trap cleanup EXIT
+ KERNEL=/kernel
+ MT=/root/linux/maintainer-tools
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools /root/linux/maintainer-tools
Cloning into '/root/linux/maintainer-tools'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ make -C /root/linux/maintainer-tools
make: Entering directory '/root/linux/maintainer-tools'
cc -O2 -g -Wextra -o remap-log remap-log.c
make: Leaving directory '/root/linux/maintainer-tools'
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ /root/linux/maintainer-tools/dim sparse --fast bd9c2b8a3a5b7bd8c38108929bfabd7a40dc922b
Sparse version: 0.6.4 (Ubuntu: 0.6.4-4ubuntu3)
Fast mode used, each commit won't be checked separately.
+drivers/gpu/drm/i915/display/g4x_dp.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/g4x_hdmi.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/i9xx_wm.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_display_trace.h):
+drivers/gpu/drm/i915/display/intel_cdclk.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_combo_phy.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_crt.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_cx0_phy.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_display.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_display_device.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_display_irq.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_display_trace.h):
+drivers/gpu/drm/i915/display/intel_display_power_map.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_display_power_well.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_display_rps.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dp.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dp_hdcp.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dpio_phy.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dpll.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dpll_mgr.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dp_mst.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dpt_common.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dp_test.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_drrs.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dsb.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dsi_vbt.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dvo.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_fbc.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_display_trace.h):
+drivers/gpu/drm/i915/display/intel_fifo_underrun.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_display_trace.h):
+drivers/gpu/drm/i915/display/intel_gmbus.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_hdmi.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_lspcon.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_modeset_setup.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_overlay.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_pch_display.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_pch_refclk.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_pfit.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_pipe_crc.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_pmdemand.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_display_trace.h):
+drivers/gpu/drm/i915/display/intel_psr.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_sdvo.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_snps_phy.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_tv.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_vblank.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_vrr.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/skl_scaler.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_display_trace.h):
+drivers/gpu/drm/i915/display/skl_universal_plane.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/gt/intel_reset.c:1569:12: warning: context imbalance in '_intel_gt_reset_lock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:193:1: error: bad constant expression
+drivers/gpu/drm/i915/i915_irq.c:468:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:468:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:476:16: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:476:16: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:481:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:481:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:481:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:519:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:519:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:527:16: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:527:16: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:532:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:532:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:532:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:576:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:576:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:579:15: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:579:15: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:583:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:583:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:590:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:590:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:590:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:590:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/intel_uncore.c:1930:1: warning: context imbalance in 'fwtable_read8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1931:1: warning: context imbalance in 'fwtable_read16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1932:1: warning: context imbalance in 'fwtable_read32' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1933:1: warning: context imbalance in 'fwtable_read64' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1998:1: warning: context imbalance in 'gen6_write8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1999:1: warning: context imbalance in 'gen6_write16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2000:1: warning: context imbalance in 'gen6_write32' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2020:1: warning: context imbalance in 'fwtable_write8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2021:1: warning: context imbalance in 'fwtable_write16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2022:1: warning: context imbalance in 'fwtable_write32' - unexpected unlock
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 43+ messages in thread
* ✓ Xe.CI.BAT: success for Make Display free from i915_reg.h (rev3)
2026-01-29 21:13 [v3 00/19] Make Display free from i915_reg.h Uma Shankar
` (21 preceding siblings ...)
2026-01-29 21:27 ` ✗ CI.checksparse: warning for Make Display free from i915_reg.h (rev3) Patchwork
@ 2026-01-29 21:45 ` Patchwork
22 siblings, 0 replies; 43+ messages in thread
From: Patchwork @ 2026-01-29 21:45 UTC (permalink / raw)
To: Uma Shankar; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 863 bytes --]
== Series Details ==
Series: Make Display free from i915_reg.h (rev3)
URL : https://patchwork.freedesktop.org/series/159130/
State : success
== Summary ==
CI Bug Log - changes from xe-4472-bd9c2b8a3a5b7bd8c38108929bfabd7a40dc922b_BAT -> xe-pw-159130v3_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Changes
-------
No changes found
Build changes
-------------
* Linux: xe-4472-bd9c2b8a3a5b7bd8c38108929bfabd7a40dc922b -> xe-pw-159130v3
IGT_8725: 8725
xe-4472-bd9c2b8a3a5b7bd8c38108929bfabd7a40dc922b: bd9c2b8a3a5b7bd8c38108929bfabd7a40dc922b
xe-pw-159130v3: 159130v3
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v3/index.html
[-- Attachment #2: Type: text/html, Size: 1411 bytes --]
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [v3 07/19] drm/i915: Remove i915_reg.h from intel_dram.c
2026-01-29 21:13 ` [v3 07/19] drm/i915: Remove i915_reg.h from intel_dram.c Uma Shankar
@ 2026-02-03 11:50 ` Jani Nikula
0 siblings, 0 replies; 43+ messages in thread
From: Jani Nikula @ 2026-02-03 11:50 UTC (permalink / raw)
To: Uma Shankar, intel-gfx, intel-xe; +Cc: ville.syrjala, Uma Shankar
On Fri, 30 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> Make intel_dram.c free from including i915_reg.h.
>
> v2: Move mem config register to newly added pcode header (Jani)
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dram.c | 2 +-
> drivers/gpu/drm/i915/i915_reg.h | 6 ------
> include/drm/intel/intel_pcode.h | 6 ++++++
> 3 files changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dram.c b/drivers/gpu/drm/i915/display/intel_dram.c
> index 3b9879714ea9..3366e18f594e 100644
> --- a/drivers/gpu/drm/i915/display/intel_dram.c
> +++ b/drivers/gpu/drm/i915/display/intel_dram.c
> @@ -7,8 +7,8 @@
>
> #include <drm/drm_managed.h>
> #include <drm/drm_print.h>
> +#include <drm/intel/intel_pcode.h>
>
> -#include "i915_reg.h"
> #include "intel_display_core.h"
> #include "intel_display_utils.h"
> #include "intel_dram.h"
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4341308c3b2b..bc466d8c8c60 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1010,12 +1010,6 @@
> #define OROM_OFFSET _MMIO(0x1020c0)
> #define OROM_OFFSET_MASK REG_GENMASK(20, 16)
>
> -#define MTL_MEM_SS_INFO_GLOBAL _MMIO(0x45700)
> -#define XE3P_ECC_IMPACTING_DE REG_BIT(12)
> -#define MTL_N_OF_ENABLED_QGV_POINTS_MASK REG_GENMASK(11, 8)
> -#define MTL_N_OF_POPULATED_CH_MASK REG_GENMASK(7, 4)
> -#define MTL_DDR_TYPE_MASK REG_GENMASK(3, 0)
> -
> #define MTL_MEDIA_GSI_BASE 0x380000
>
> #endif /* _I915_REG_H_ */
> diff --git a/include/drm/intel/intel_pcode.h b/include/drm/intel/intel_pcode.h
> index 8e9a574c87d9..f6f894ba9b20 100644
> --- a/include/drm/intel/intel_pcode.h
> +++ b/include/drm/intel/intel_pcode.h
> @@ -105,4 +105,10 @@
> #define PCODE_MBOX_DOMAIN_NONE 0x0
> #define PCODE_MBOX_DOMAIN_MEDIAFF 0x3
>
> +#define MTL_MEM_SS_INFO_GLOBAL _MMIO(0x45700)
> +#define XE3P_ECC_IMPACTING_DE REG_BIT(12)
> +#define MTL_N_OF_ENABLED_QGV_POINTS_MASK REG_GENMASK(11, 8)
> +#define MTL_N_OF_POPULATED_CH_MASK REG_GENMASK(7, 4)
> +#define MTL_DDR_TYPE_MASK REG_GENMASK(3, 0)
This isn't related to pcode, and this is only used in display. Why here?
BR,
Jani.
> +
> #endif
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [v3 05/19] drm/{i915, xe}: Extract pcode definitions to common header
2026-01-29 21:13 ` [v3 05/19] drm/{i915, xe}: Extract pcode definitions to common header Uma Shankar
@ 2026-02-03 12:00 ` Jani Nikula
0 siblings, 0 replies; 43+ messages in thread
From: Jani Nikula @ 2026-02-03 12:00 UTC (permalink / raw)
To: Uma Shankar, intel-gfx, intel-xe; +Cc: ville.syrjala, Uma Shankar
On Fri, 30 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> There are certain register definitions which are commonly shared
> by i915, xe and display. Extract the same to a common header to
> avoid duplication.
>
> Move GEN6_PCODE_MAILBOX to common pcode header to make intel_cdclk.c
> free from including i915_reg.h.
>
> v2: Make the header granular and per feature (Jani)
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
> drivers/gpu/drm/i915/i915_reg.h | 101 +------------------
> include/drm/intel/intel_pcode.h | 108 +++++++++++++++++++++
> 3 files changed, 110 insertions(+), 101 deletions(-)
> create mode 100644 include/drm/intel/intel_pcode.h
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 9217050a76e0..606256027264 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -27,9 +27,9 @@
>
> #include <drm/drm_fixed.h>
> #include <drm/drm_print.h>
> +#include <drm/intel/intel_pcode.h>
>
> #include "hsw_ips.h"
> -#include "i915_reg.h"
> #include "intel_atomic.h"
> #include "intel_audio.h"
> #include "intel_cdclk.h"
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 26e5504dbc67..c7361e82a0c6 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -25,6 +25,7 @@
> #ifndef _I915_REG_H_
> #define _I915_REG_H_
>
> +#include <drm/intel/intel_pcode.h>
I was thinking it would be better to include this only where needed, not
from i915_reg.h. It also improves granularity.
> diff --git a/include/drm/intel/intel_pcode.h b/include/drm/intel/intel_pcode.h
> new file mode 100644
> index 000000000000..8e9a574c87d9
> --- /dev/null
> +++ b/include/drm/intel/intel_pcode.h
Maybe call it intel_pcode_regs.h to emphasize it's only about registers?
> @@ -0,0 +1,108 @@
> +/* SPDX-License-Identifier: MIT */
> +/* Copyright © 2026 Intel Corporation */
> +
> +#ifndef _INTEL_GMD_COMMON_REG_H_
> +#define _INTEL_GMD_COMMON_REG_H_
Please adjust this too.
BR,
Jani.
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [v3 06/19] drm/i915: Remove i915_reg.h from intel_display_device.c
2026-01-29 21:13 ` [v3 06/19] drm/i915: Remove i915_reg.h from intel_display_device.c Uma Shankar
@ 2026-02-03 12:06 ` Jani Nikula
0 siblings, 0 replies; 43+ messages in thread
From: Jani Nikula @ 2026-02-03 12:06 UTC (permalink / raw)
To: Uma Shankar, intel-gfx, intel-xe; +Cc: ville.syrjala, Uma Shankar
On Fri, 30 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> Move GU_CNTL_PROTECTED and GMD_ID_DISPLAY to common header,
> this helps intel_display_device.c free from i915_reg.h dependency.
>
> v2: Move GMD_ID_DISPLAY to display header instead of common (Jani)
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display_device.c | 7 +++----
> drivers/gpu/drm/i915/display/intel_display_regs.h | 8 ++++++++
> drivers/gpu/drm/i915/i915_reg.h | 4 ----
> 3 files changed, 11 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
> index 471f236c9ddf..d449528bfc7f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> @@ -10,7 +10,6 @@
> #include <drm/drm_print.h>
> #include <drm/intel/pciids.h>
>
> -#include "i915_reg.h"
> #include "intel_cx0_phy_regs.h"
> #include "intel_de.h"
> #include "intel_display.h"
> @@ -1539,9 +1538,9 @@ probe_gmdid_display(struct intel_display *display, struct intel_display_ip_ver *
> return NULL;
> }
>
> - gmd_id.ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val);
> - gmd_id.rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val);
> - gmd_id.step = REG_FIELD_GET(GMD_ID_STEP, val);
> + gmd_id.ver = REG_FIELD_GET(GMD_ID_DISPLAY_ARCH_MASK, val);
> + gmd_id.rel = REG_FIELD_GET(GMD_ID_DISPLAY_RELEASE_MASK, val);
> + gmd_id.step = REG_FIELD_GET(GMD_ID_DISPLAY_STEP, val);
>
> for (i = 0; i < ARRAY_SIZE(gmdid_display_map); i++) {
> if (gmd_id.ver == gmdid_display_map[i].ver &&
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index f90d52f7e5be..0d7788db4a7f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -6,6 +6,9 @@
>
> #include "intel_display_reg_defs.h"
>
> +#define GU_CNTL_PROTECTED _MMIO(0x10100C)
> +#define DEPRESENT REG_BIT(9)
> +
> #define _GEN7_PIPEA_DE_LOAD_SL 0x70068
> #define _GEN7_PIPEB_DE_LOAD_SL 0x71068
> #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL)
> @@ -1626,6 +1629,11 @@
> #define GLK_DFSM_DISPLAY_DSC_DISABLE (1 << 7)
> #define XE2LPD_DFSM_DBUF_OVERLAP_DISABLE (1 << 3)
>
> +#define GMD_ID_DISPLAY _MMIO(0x510a0)
> +#define GMD_ID_DISPLAY_ARCH_MASK REG_GENMASK(31, 22)
> +#define GMD_ID_DISPLAY_RELEASE_MASK REG_GENMASK(21, 14)
> +#define GMD_ID_DISPLAY_STEP REG_GENMASK(5, 0)
> +
> #define XE2LPD_DE_CAP _MMIO(0x41100)
> #define XE2LPD_DE_CAP_3DLUT_MASK REG_GENMASK(31, 30)
> #define XE2LPD_DE_CAP_DSC_MASK REG_GENMASK(29, 28)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c7361e82a0c6..4341308c3b2b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -117,9 +117,6 @@
> * #define GEN8_BAR _MMIO(0xb888)
> */
>
> -#define GU_CNTL_PROTECTED _MMIO(0x10100C)
> -#define DEPRESENT REG_BIT(9)
> -
> #define GU_CNTL _MMIO(0x101010)
> #define LMEM_INIT REG_BIT(7)
> #define DRIVERFLR REG_BIT(31)
> @@ -926,7 +923,6 @@
> #define MASK_WAKEMEM REG_BIT(13)
> #define DDI_CLOCK_REG_ACCESS REG_BIT(7)
>
> -#define GMD_ID_DISPLAY _MMIO(0x510a0)
> #define GMD_ID_ARCH_MASK REG_GENMASK(31, 22)
> #define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14)
> #define GMD_ID_STEP REG_GENMASK(5, 0)
I guess these could now go next to
#define GMD_ID_GRAPHICS _MMIO(0xd8c)
#define GMD_ID_MEDIA _MMIO(MTL_MEDIA_GSI_BASE + 0xd8c)
in gt/intel_gt_regs.h, but can be a follow-up too.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [v3 09/19] drm/i915: Remove i915_reg.h from intel_overlay.c
2026-01-29 21:13 ` [v3 09/19] drm/i915: Remove i915_reg.h from intel_overlay.c Uma Shankar
@ 2026-02-03 12:39 ` Jani Nikula
0 siblings, 0 replies; 43+ messages in thread
From: Jani Nikula @ 2026-02-03 12:39 UTC (permalink / raw)
To: Uma Shankar, intel-gfx, intel-xe; +Cc: ville.syrjala, Uma Shankar
On Fri, 30 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> Move GEN2_ISR and some interrupt definitions to common header.
> This removes dependency of i915_reg.h from intel_overlay.c.
>
> v2: Create a separate file for common interrupts (Jani)
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> .../gpu/drm/i915/display/intel_display_irq.c | 1 +
> .../gpu/drm/i915/display/intel_display_regs.h | 2 +
> drivers/gpu/drm/i915/display/intel_overlay.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_gt.c | 1 +
> .../gpu/drm/i915/gt/intel_ring_submission.c | 1 +
> drivers/gpu/drm/i915/i915_irq.c | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 37 ----------------
> include/drm/intel/intel_gmd_interrupt.h | 43 +++++++++++++++++++
> 8 files changed, 50 insertions(+), 38 deletions(-)
> create mode 100644 include/drm/intel/intel_gmd_interrupt.h
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
> index 0a71840041de..31c78dc3d63b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
> @@ -5,6 +5,7 @@
>
> #include <drm/drm_print.h>
> #include <drm/drm_vblank.h>
> +#include <drm/intel/intel_gmd_interrupt.h>
>
> #include "i915_reg.h"
> #include "icl_dsi_regs.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index 706024c2a463..40538910cb09 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -94,6 +94,8 @@
> #define VLV_ERROR_PAGE_TABLE (1 << 4)
> #define VLV_ERROR_CLAIM (1 << 0)
>
> +#define GEN2_ISR _MMIO(0x20ac)
> +
> #define VLV_ERROR_REGS I915_ERROR_REGS(VLV_EMR, VLV_EIR)
>
> #define _MBUS_ABOX0_CTL 0x45038
> diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c
> index 88eb7ae5765c..3a45836b8373 100644
> --- a/drivers/gpu/drm/i915/display/intel_overlay.c
> +++ b/drivers/gpu/drm/i915/display/intel_overlay.c
> @@ -28,6 +28,7 @@
>
> #include <drm/drm_fourcc.h>
> #include <drm/drm_print.h>
> +#include <drm/intel/intel_gmd_interrupt.h>
>
> #include "gem/i915_gem_internal.h"
> #include "gem/i915_gem_object_frontbuffer.h"
> @@ -37,7 +38,6 @@
> #include "gt/intel_ring.h"
>
> #include "i915_drv.h"
> -#include "i915_reg.h"
> #include "intel_color_regs.h"
> #include "intel_de.h"
> #include "intel_display_regs.h"
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index ac527d878820..998dea65fcff 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -5,6 +5,7 @@
>
> #include <drm/drm_managed.h>
> #include <drm/intel/intel-gtt.h>
> +#include <drm/intel/intel_gmd_interrupt.h>
>
> #include "gem/i915_gem_internal.h"
> #include "gem/i915_gem_lmem.h"
> diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> index 8314a4b0505e..7391c9b2ceb5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> @@ -4,6 +4,7 @@
> */
>
> #include <drm/drm_cache.h>
> +#include <drm/intel/intel_gmd_interrupt.h>
>
> #include "gem/i915_gem_internal.h"
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 3fe978d4ea53..2acdd739335f 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -34,6 +34,7 @@
> #include <drm/drm_drv.h>
> #include <drm/drm_print.h>
> #include <drm/intel/display_parent_interface.h>
> +#include <drm/intel/intel_gmd_interrupt.h>
>
> #include "display/intel_display_irq.h"
> #include "display/intel_hotplug.h"
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 10928e8406dc..22b68ddfa7b4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -365,7 +365,6 @@
> #define GEN2_IER _MMIO(0x20a0)
> #define GEN2_IIR _MMIO(0x20a4)
> #define GEN2_IMR _MMIO(0x20a8)
> -#define GEN2_ISR _MMIO(0x20ac)
>
> #define GEN2_IRQ_REGS I915_IRQ_REGS(GEN2_IMR, \
> GEN2_IER, \
> @@ -522,42 +521,6 @@
> /* These are all the "old" interrupts */
> #define ILK_BSD_USER_INTERRUPT (1 << 5)
>
> -#define I915_PM_INTERRUPT (1 << 31)
> -#define I915_ISP_INTERRUPT (1 << 22)
> -#define I915_LPE_PIPE_B_INTERRUPT (1 << 21)
> -#define I915_LPE_PIPE_A_INTERRUPT (1 << 20)
> -#define I915_MIPIC_INTERRUPT (1 << 19)
> -#define I915_MIPIA_INTERRUPT (1 << 18)
> -#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 18)
> -#define I915_DISPLAY_PORT_INTERRUPT (1 << 17)
> -#define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1 << 16)
> -#define I915_MASTER_ERROR_INTERRUPT (1 << 15)
> -#define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1 << 14)
> -#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1 << 14) /* p-state */
> -#define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1 << 13)
> -#define I915_HWB_OOM_INTERRUPT (1 << 13)
> -#define I915_LPE_PIPE_C_INTERRUPT (1 << 12)
> -#define I915_SYNC_STATUS_INTERRUPT (1 << 12)
> -#define I915_MISC_INTERRUPT (1 << 11)
> -#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1 << 11)
> -#define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1 << 10)
> -#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1 << 10)
> -#define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1 << 9)
> -#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1 << 9)
> -#define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1 << 8)
> -#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1 << 8)
> -#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1 << 7)
> -#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1 << 6)
> -#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1 << 5)
> -#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1 << 4)
> -#define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1 << 3)
> -#define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1 << 2)
> -#define I915_DEBUG_INTERRUPT (1 << 2)
> -#define I915_WINVALID_INTERRUPT (1 << 1)
> -#define I915_USER_INTERRUPT (1 << 1)
> -#define I915_ASLE_INTERRUPT (1 << 0)
> -#define I915_BSD_USER_INTERRUPT (1 << 25)
> -
> #define GEN6_BSD_RNCID _MMIO(0x12198)
>
> #define GEN7_FF_THREAD_MODE _MMIO(0x20a0)
> diff --git a/include/drm/intel/intel_gmd_interrupt.h b/include/drm/intel/intel_gmd_interrupt.h
> new file mode 100644
> index 000000000000..eae0acade16a
> --- /dev/null
> +++ b/include/drm/intel/intel_gmd_interrupt.h
Here too I think I'd name this *_regs.h.
Other than that,
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> @@ -0,0 +1,43 @@
> +/* SPDX-License-Identifier: MIT */
> +/* Copyright © 2026 Intel Corporation */
> +
> +#ifndef _INTEL_GMD_INTERRUPT_H_
> +#define _INTEL_GMD_INTERRUPT_H_
> +
> +#define I915_PM_INTERRUPT (1 << 31)
> +#define I915_ISP_INTERRUPT (1 << 22)
> +#define I915_LPE_PIPE_B_INTERRUPT (1 << 21)
> +#define I915_LPE_PIPE_A_INTERRUPT (1 << 20)
> +#define I915_MIPIC_INTERRUPT (1 << 19)
> +#define I915_MIPIA_INTERRUPT (1 << 18)
> +#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 18)
> +#define I915_DISPLAY_PORT_INTERRUPT (1 << 17)
> +#define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1 << 16)
> +#define I915_MASTER_ERROR_INTERRUPT (1 << 15)
> +#define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1 << 14)
> +#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1 << 14) /* p-state */
> +#define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1 << 13)
> +#define I915_HWB_OOM_INTERRUPT (1 << 13)
> +#define I915_LPE_PIPE_C_INTERRUPT (1 << 12)
> +#define I915_SYNC_STATUS_INTERRUPT (1 << 12)
> +#define I915_MISC_INTERRUPT (1 << 11)
> +#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1 << 11)
> +#define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1 << 10)
> +#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1 << 10)
> +#define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1 << 9)
> +#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1 << 9)
> +#define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1 << 8)
> +#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1 << 8)
> +#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1 << 7)
> +#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1 << 6)
> +#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1 << 5)
> +#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1 << 4)
> +#define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1 << 3)
> +#define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1 << 2)
> +#define I915_DEBUG_INTERRUPT (1 << 2)
> +#define I915_WINVALID_INTERRUPT (1 << 1)
> +#define I915_USER_INTERRUPT (1 << 1)
> +#define I915_ASLE_INTERRUPT (1 << 0)
> +#define I915_BSD_USER_INTERRUPT (1 << 25)
> +
> +#endif
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [v3 10/19] drm/i915: Remove i915_reg.h from g4x_dp.c
2026-01-29 21:13 ` [v3 10/19] drm/i915: Remove i915_reg.h from g4x_dp.c Uma Shankar
@ 2026-02-03 12:40 ` Jani Nikula
2026-02-05 7:29 ` Shankar, Uma
0 siblings, 1 reply; 43+ messages in thread
From: Jani Nikula @ 2026-02-03 12:40 UTC (permalink / raw)
To: Uma Shankar, intel-gfx, intel-xe; +Cc: ville.syrjala, Uma Shankar
On Fri, 30 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> Move DE_IRQ_REGS to display header to make g4x_dp.c
> free from i915_reg.h dependency. These registers are
> only used by display and gvt.
>
> v2: Move DE interrupt regs from common to display header (Jani)
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/i915/display/g4x_dp.c | 2 +-
> .../gpu/drm/i915/display/intel_display_regs.h | 16 ++++++++++++++++
> drivers/gpu/drm/i915/i915_reg.h | 15 ---------------
> 3 files changed, 17 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
> index 4cb753177fd8..017c6dd8f9f6 100644
> --- a/drivers/gpu/drm/i915/display/g4x_dp.c
> +++ b/drivers/gpu/drm/i915/display/g4x_dp.c
> @@ -8,9 +8,9 @@
> #include <linux/string_helpers.h>
>
> #include <drm/drm_print.h>
> +#include <drm/intel/intel_gmd_interrupt.h>
How's this required in this patch? Nothing's being moved there in this
patch?
BR,
Jani.
>
> #include "g4x_dp.h"
> -#include "i915_reg.h"
> #include "intel_audio.h"
> #include "intel_backlight.h"
> #include "intel_connector.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index 40538910cb09..0164dcbb709f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -1049,6 +1049,15 @@
> #define SWF3(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4)
> #define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4)
>
> +#define DEISR _MMIO(0x44000)
> +#define DEIMR _MMIO(0x44004)
> +#define DEIIR _MMIO(0x44008)
> +#define DEIER _MMIO(0x4400c)
> +
> +#define DE_IRQ_REGS I915_IRQ_REGS(DEIMR, \
> + DEIER, \
> + DEIIR)
> +
> #define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030)
> #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
> #define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */
> @@ -1792,6 +1801,13 @@
> SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \
> SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1))
>
> +/* PCH */
> +
> +#define SDEISR _MMIO(0xc4000)
> +#define SDEIMR _MMIO(0xc4004)
> +#define SDEIIR _MMIO(0xc4008)
> +#define SDEIER _MMIO(0xc400c)
> +
> #define SDE_IRQ_REGS I915_IRQ_REGS(SDEIMR, \
> SDEIER, \
> SDEIIR)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 22b68ddfa7b4..6cb72e6e9086 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -728,15 +728,6 @@
> #define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */
> #define MASTER_INTERRUPT_ENABLE (1 << 31)
>
> -#define DEISR _MMIO(0x44000)
> -#define DEIMR _MMIO(0x44004)
> -#define DEIIR _MMIO(0x44008)
> -#define DEIER _MMIO(0x4400c)
> -
> -#define DE_IRQ_REGS I915_IRQ_REGS(DEIMR, \
> - DEIER, \
> - DEIIR)
> -
> #define GTISR _MMIO(0x44010)
> #define GTIMR _MMIO(0x44014)
> #define GTIIR _MMIO(0x44018)
> @@ -868,12 +859,6 @@
> #define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14)
> #define GMD_ID_STEP REG_GENMASK(5, 0)
>
> -/* PCH */
> -
> -#define SDEISR _MMIO(0xc4000)
> -#define SDEIMR _MMIO(0xc4004)
> -#define SDEIIR _MMIO(0xc4008)
> -#define SDEIER _MMIO(0xc400c)
>
> /* Icelake PPS_DATA and _ECC DIP Registers.
> * These are available for transcoders B,C and eDP.
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [v3 11/19] drm/i915: Remove i915_reg.h from i9xx_wm.c
2026-01-29 21:13 ` [v3 11/19] drm/i915: Remove i915_reg.h from i9xx_wm.c Uma Shankar
@ 2026-02-03 12:42 ` Jani Nikula
2026-02-05 7:31 ` Shankar, Uma
2026-02-03 16:27 ` Ville Syrjälä
1 sibling, 1 reply; 43+ messages in thread
From: Jani Nikula @ 2026-02-03 12:42 UTC (permalink / raw)
To: Uma Shankar, intel-gfx, intel-xe; +Cc: ville.syrjala, Uma Shankar
On Fri, 30 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> Move FW_BLC_SELF to common header to make i9xx_wm.c
> free from i915_reg.h include. Introduce a common
> intel_gmd_misc_regs.h to define common miscellaneous
> register definitions across graphics and display.
>
> v2: Introdue a common misc header for GMD
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/i915/display/i9xx_wm.c | 2 +-
> .../gpu/drm/i915/display/intel_display_regs.h | 8 ++++++-
> drivers/gpu/drm/i915/i915_reg.h | 20 +-----------------
> include/drm/intel/intel_gmd_misc_regs.h | 21 +++++++++++++++++++
> 4 files changed, 30 insertions(+), 21 deletions(-)
> create mode 100644 include/drm/intel/intel_gmd_misc_regs.h
>
> diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
> index 39dfceb438ae..24f898efa9dd 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_wm.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
> @@ -6,8 +6,8 @@
> #include <linux/iopoll.h>
>
> #include <drm/drm_print.h>
> +#include <drm/intel/intel_gmd_misc_regs.h>
>
> -#include "i915_reg.h"
> #include "i9xx_wm.h"
> #include "i9xx_wm_regs.h"
> #include "intel_atomic.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index 0164dcbb709f..680020e590cb 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -4,6 +4,7 @@
> #ifndef __INTEL_DISPLAY_REGS_H__
> #define __INTEL_DISPLAY_REGS_H__
>
> +#include <drm/intel/intel_gmd_misc_regs.h>
Please only include where needed.
> #include "intel_display_reg_defs.h"
>
> #define GU_CNTL_PROTECTED _MMIO(0x10100C)
> @@ -3119,6 +3120,11 @@ enum skl_power_gate {
> #define MTL_TRAS_MASK REG_GENMASK(16, 8)
> #define MTL_TRDPRE_MASK REG_GENMASK(7, 0)
>
> -
> +#define FW_BLC _MMIO(0x20d8)
> +#define FW_BLC2 _MMIO(0x20dc)
> +#define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */
> +#define FW_BLC_SELF_EN_MASK REG_BIT(31)
> +#define FW_BLC_SELF_FIFO_MASK REG_BIT(16) /* 945 only */
> +#define FW_BLC_SELF_EN REG_BIT(15) /* 945 only */
>
> #endif /* __INTEL_DISPLAY_REGS_H__ */
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 6cb72e6e9086..b4b749e52b5b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -26,6 +26,7 @@
> #define _I915_REG_H_
>
> #include <drm/intel/intel_pcode.h>
> +#include <drm/intel/intel_gmd_misc_regs.h>
Please only include where needed.
> #include "i915_reg_defs.h"
> #include "display/intel_display_reg_defs.h"
>
> @@ -394,24 +395,10 @@
>
> #define GEN2_ERROR_REGS I915_ERROR_REGS(EMR, EIR)
>
> -#define INSTPM _MMIO(0x20c0)
> -#define INSTPM_SELF_EN (1 << 12) /* 915GM only */
> -#define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts
> - will not assert AGPBUSY# and will only
> - be delivered when out of C3. */
> -#define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */
> -#define INSTPM_TLB_INVALIDATE (1 << 9)
> -#define INSTPM_SYNC_FLUSH (1 << 5)
> #define MEM_MODE _MMIO(0x20cc)
> #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */
> #define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */
> #define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) /* 85x only */
> -#define FW_BLC _MMIO(0x20d8)
> -#define FW_BLC2 _MMIO(0x20dc)
> -#define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */
> -#define FW_BLC_SELF_EN_MASK REG_BIT(31)
> -#define FW_BLC_SELF_FIFO_MASK REG_BIT(16) /* 945 only */
> -#define FW_BLC_SELF_EN REG_BIT(15) /* 945 only */
> #define MM_BURST_LENGTH 0x00700000
> #define MM_FIFO_WATERMARK 0x0001F000
> #define LM_BURST_LENGTH 0x00000700
> @@ -834,11 +821,6 @@
> #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT REG_BIT(14)
>
>
> -#define DISP_ARB_CTL _MMIO(0x45000)
> -#define DISP_FBC_MEMORY_WAKE REG_BIT(31)
> -#define DISP_TILE_SURFACE_SWIZZLING REG_BIT(13)
> -#define DISP_FBC_WM_DIS REG_BIT(15)
> -
> #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
> #define _LATENCY_REPORTING_REMOVED_PIPE_D REG_BIT(31)
> #define SKL_SELECT_ALTERNATE_DC_EXIT REG_BIT(30)
> diff --git a/include/drm/intel/intel_gmd_misc_regs.h b/include/drm/intel/intel_gmd_misc_regs.h
> new file mode 100644
> index 000000000000..377f4e383699
> --- /dev/null
> +++ b/include/drm/intel/intel_gmd_misc_regs.h
> @@ -0,0 +1,21 @@
> +/* SPDX-License-Identifier: MIT */
> +/* Copyright © 2026 Intel Corporation */
> +
> +#ifndef _INTEL_GMD_MISC_REG_H_
> +#define _INTEL_GMD_MISC_REG_H_
Should be REGS_H to match the file name.
> +
> +#define DISP_ARB_CTL _MMIO(0x45000)
> +#define DISP_FBC_MEMORY_WAKE REG_BIT(31)
> +#define DISP_TILE_SURFACE_SWIZZLING REG_BIT(13)
> +#define DISP_FBC_WM_DIS REG_BIT(15)
> +
> +#define INSTPM _MMIO(0x20c0)
> +#define INSTPM_SELF_EN (1 << 12) /* 915GM only */
> +#define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts
> + will not assert AGPBUSY# and will only
> + be delivered when out of C3. */
> +#define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */
> +#define INSTPM_TLB_INVALIDATE (1 << 9)
> +#define INSTPM_SYNC_FLUSH (1 << 5)
> +
> +#endif
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [v3 15/19] drm/i915: Remove i915_reg.h from intel_fifo_underrun.c
2026-01-29 21:13 ` [v3 15/19] drm/i915: Remove i915_reg.h from intel_fifo_underrun.c Uma Shankar
@ 2026-02-03 12:47 ` Jani Nikula
0 siblings, 0 replies; 43+ messages in thread
From: Jani Nikula @ 2026-02-03 12:47 UTC (permalink / raw)
To: Uma Shankar, intel-gfx, intel-xe; +Cc: ville.syrjala, Uma Shankar
On Fri, 30 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> Move GEN7_ERR_INT reg to common header to make intel_fifo_underrun.c
> free from including i915_reg.h.
>
> v2: Move GEN7_ERR_INT regs to display header (Jani)
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> .../gpu/drm/i915/display/intel_display_regs.h | 23 +++++++++++++++++++
> .../drm/i915/display/intel_fifo_underrun.c | 1 -
> drivers/gpu/drm/i915/i915_reg.h | 23 -------------------
> 3 files changed, 23 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index 23626ee2d4ce..ab2ef267c9ce 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -91,6 +91,29 @@
> #define DERRMR_PIPEC_VBLANK (1 << 21)
> #define DERRMR_PIPEC_HBLANK (1 << 22)
>
> +#define GEN7_ERR_INT _MMIO(0x44040)
> +#define ERR_INT_POISON (1 << 31)
> +#define ERR_INT_INVALID_GTT_PTE (1 << 29)
> +#define ERR_INT_INVALID_PTE_DATA (1 << 28)
> +#define ERR_INT_SPRITE_C_FAULT (1 << 23)
> +#define ERR_INT_PRIMARY_C_FAULT (1 << 22)
> +#define ERR_INT_CURSOR_C_FAULT (1 << 21)
> +#define ERR_INT_SPRITE_B_FAULT (1 << 20)
> +#define ERR_INT_PRIMARY_B_FAULT (1 << 19)
> +#define ERR_INT_CURSOR_B_FAULT (1 << 18)
> +#define ERR_INT_SPRITE_A_FAULT (1 << 17)
> +#define ERR_INT_PRIMARY_A_FAULT (1 << 16)
> +#define ERR_INT_CURSOR_A_FAULT (1 << 15)
> +#define ERR_INT_MMIO_UNCLAIMED (1 << 13)
> +#define ERR_INT_PIPE_CRC_DONE_C (1 << 8)
> +#define ERR_INT_FIFO_UNDERRUN_C (1 << 6)
> +#define ERR_INT_PIPE_CRC_DONE_B (1 << 5)
> +#define ERR_INT_FIFO_UNDERRUN_B (1 << 3)
> +#define ERR_INT_PIPE_CRC_DONE_A (1 << 2)
> +#define ERR_INT_PIPE_CRC_DONE(pipe) (1 << (2 + (pipe) * 3))
> +#define ERR_INT_FIFO_UNDERRUN_A (1 << 0)
> +#define ERR_INT_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3))
> +
> #define VLV_IRQ_REGS I915_IRQ_REGS(VLV_IMR, \
> VLV_IER, \
> VLV_IIR)
> diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> index b413b3e871d8..bf047180def9 100644
> --- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> +++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> @@ -29,7 +29,6 @@
>
> #include <drm/drm_print.h>
>
> -#include "i915_reg.h"
> #include "intel_de.h"
> #include "intel_display_irq.h"
> #include "intel_display_regs.h"
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b23ac1b8f495..611ae5861450 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -327,29 +327,6 @@
> #define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070)
> #define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074)
>
> -#define GEN7_ERR_INT _MMIO(0x44040)
> -#define ERR_INT_POISON (1 << 31)
> -#define ERR_INT_INVALID_GTT_PTE (1 << 29)
> -#define ERR_INT_INVALID_PTE_DATA (1 << 28)
> -#define ERR_INT_SPRITE_C_FAULT (1 << 23)
> -#define ERR_INT_PRIMARY_C_FAULT (1 << 22)
> -#define ERR_INT_CURSOR_C_FAULT (1 << 21)
> -#define ERR_INT_SPRITE_B_FAULT (1 << 20)
> -#define ERR_INT_PRIMARY_B_FAULT (1 << 19)
> -#define ERR_INT_CURSOR_B_FAULT (1 << 18)
> -#define ERR_INT_SPRITE_A_FAULT (1 << 17)
> -#define ERR_INT_PRIMARY_A_FAULT (1 << 16)
> -#define ERR_INT_CURSOR_A_FAULT (1 << 15)
> -#define ERR_INT_MMIO_UNCLAIMED (1 << 13)
> -#define ERR_INT_PIPE_CRC_DONE_C (1 << 8)
> -#define ERR_INT_FIFO_UNDERRUN_C (1 << 6)
> -#define ERR_INT_PIPE_CRC_DONE_B (1 << 5)
> -#define ERR_INT_FIFO_UNDERRUN_B (1 << 3)
> -#define ERR_INT_PIPE_CRC_DONE_A (1 << 2)
> -#define ERR_INT_PIPE_CRC_DONE(pipe) (1 << (2 + (pipe) * 3))
> -#define ERR_INT_FIFO_UNDERRUN_A (1 << 0)
> -#define ERR_INT_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3))
> -
> #define FPGA_DBG _MMIO(0x42300)
> #define FPGA_DBG_RM_NOCLAIM REG_BIT(31)
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [v3 17/19] drm/i915: Remove i915_reg.h from intel_display_power_well.c
2026-01-29 21:13 ` [v3 17/19] drm/i915: Remove i915_reg.h from intel_display_power_well.c Uma Shankar
@ 2026-02-03 12:49 ` Jani Nikula
2026-02-05 7:40 ` Shankar, Uma
2026-02-03 16:34 ` Ville Syrjälä
1 sibling, 1 reply; 43+ messages in thread
From: Jani Nikula @ 2026-02-03 12:49 UTC (permalink / raw)
To: Uma Shankar, intel-gfx, intel-xe; +Cc: ville.syrjala, Uma Shankar
On Fri, 30 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> Make intel_display_power_well.c free from including i915_reg.h.
>
> v2: Include specific pcode header, drop common header (Jani)
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display_power_well.c | 2 +-
> drivers/gpu/drm/i915/display/intel_display_regs.h | 2 ++
> drivers/gpu/drm/i915/i915_reg.h | 3 ---
> 3 files changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index 6f9bc6f9615e..f98de1baa63d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -6,8 +6,8 @@
> #include <linux/iopoll.h>
>
> #include <drm/drm_print.h>
> +#include <drm/intel/intel_pcode.h>
Hmm, nothing's being moved there in this patch, so this change feels
unrelated.
BR,
Jani.
>
> -#include "i915_reg.h"
> #include "intel_backlight_regs.h"
> #include "intel_combo_phy.h"
> #include "intel_combo_phy_regs.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index 4a9b7560ce8c..758749c5c322 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -359,6 +359,8 @@
> #define FW_CSPWRDWNEN (1 << 15)
>
> #define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504)
> +/* Disable display A/B trickle feed */
> +#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
>
> #define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508)
> #define CDCLK_FREQ_SHIFT 4
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9cd7fce09ebe..e4fc61dcd384 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -428,9 +428,6 @@
> #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
> #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
>
> -/* Disable display A/B trickle feed */
> -#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
> -
> /* Set display plane priority */
> #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
> #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [v3 19/19] drm/{i915, xe}: Remove i915_reg.h from display
2026-01-29 21:13 ` [v3 19/19] drm/{i915, xe}: Remove i915_reg.h from display Uma Shankar
@ 2026-02-03 12:50 ` Jani Nikula
2026-02-05 7:48 ` Shankar, Uma
0 siblings, 1 reply; 43+ messages in thread
From: Jani Nikula @ 2026-02-03 12:50 UTC (permalink / raw)
To: Uma Shankar, intel-gfx, intel-xe; +Cc: ville.syrjala, Uma Shankar
On Fri, 30 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> Make display files free from including i915_reg.h.
>
> v2: Include modular per component headers (Jani)
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/i915/display/hsw_ips.c | 2 +-
> drivers/gpu/drm/i915/display/i9xx_plane.c | 1 -
> drivers/gpu/drm/i915/display/icl_dsi.c | 1 -
> drivers/gpu/drm/i915/display/intel_backlight.c | 1 -
> drivers/gpu/drm/i915/display/intel_bw.c | 2 +-
> drivers/gpu/drm/i915/display/intel_casf.c | 1 -
> drivers/gpu/drm/i915/display/intel_ddi.c | 1 -
> drivers/gpu/drm/i915/display/intel_display_debugfs.c | 1 -
> drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
> drivers/gpu/drm/i915/display/intel_display_wa.c | 1 -
> drivers/gpu/drm/i915/display/intel_dmc.c | 1 -
> drivers/gpu/drm/i915/display/intel_fdi.c | 1 -
> drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
> drivers/gpu/drm/i915/display/intel_hotplug_irq.c | 1 -
> drivers/gpu/drm/i915/display/intel_lt_phy.c | 1 -
> drivers/gpu/drm/i915/display/intel_pps.c | 1 -
> drivers/gpu/drm/i915/display/intel_tc.c | 1 -
> drivers/gpu/drm/i915/display/skl_watermark.c | 2 +-
> drivers/gpu/drm/i915/display/vlv_dsi.c | 1 -
> 19 files changed, 5 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/hsw_ips.c b/drivers/gpu/drm/i915/display/hsw_ips.c
> index 0caaea2e64e1..5697fa4eb11f 100644
> --- a/drivers/gpu/drm/i915/display/hsw_ips.c
> +++ b/drivers/gpu/drm/i915/display/hsw_ips.c
> @@ -6,9 +6,9 @@
> #include <linux/debugfs.h>
>
> #include <drm/drm_print.h>
> +#include <drm/intel/intel_pcode.h>
Nothing's being added there in this patch, so this feels
unrelated. Ditto below.
I think it'll lead to a better overall series if intel_pcode.h (or
intel_pcode_regs.h) isn't included in i915_reg.h but rather everywhere
it's needed.
BR,
Jani.
>
> #include "hsw_ips.h"
> -#include "i915_reg.h"
> #include "intel_color_regs.h"
> #include "intel_de.h"
> #include "intel_display_regs.h"
> diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
> index b1fecf178906..9c16753a1f3b 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_plane.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
> @@ -10,7 +10,6 @@
> #include <drm/drm_fourcc.h>
> #include <drm/drm_print.h>
>
> -#include "i915_reg.h"
> #include "i9xx_plane.h"
> #include "i9xx_plane_regs.h"
> #include "intel_atomic.h"
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index c8e0333706c1..7cf511a6c0f9 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -34,7 +34,6 @@
> #include <drm/drm_print.h>
> #include <drm/drm_probe_helper.h>
>
> -#include "i915_reg.h"
> #include "icl_dsi.h"
> #include "icl_dsi_regs.h"
> #include "intel_atomic.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c b/drivers/gpu/drm/i915/display/intel_backlight.c
> index a68fdbd2acb9..34e95f05936e 100644
> --- a/drivers/gpu/drm/i915/display/intel_backlight.c
> +++ b/drivers/gpu/drm/i915/display/intel_backlight.c
> @@ -12,7 +12,6 @@
> #include <drm/drm_file.h>
> #include <drm/drm_print.h>
>
> -#include "i915_reg.h"
> #include "intel_backlight.h"
> #include "intel_backlight_regs.h"
> #include "intel_connector.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index 8d84445c69f1..71149d8bcd73 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -5,8 +5,8 @@
>
> #include <drm/drm_atomic_state_helper.h>
> #include <drm/drm_print.h>
> +#include <drm/intel/intel_pcode.h>
>
> -#include "i915_reg.h"
> #include "intel_bw.h"
> #include "intel_crtc.h"
> #include "intel_display_core.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_casf.c b/drivers/gpu/drm/i915/display/intel_casf.c
> index 0fe4398a1a4e..b167af31de5b 100644
> --- a/drivers/gpu/drm/i915/display/intel_casf.c
> +++ b/drivers/gpu/drm/i915/display/intel_casf.c
> @@ -3,7 +3,6 @@
>
> #include <drm/drm_print.h>
>
> -#include "i915_reg.h"
> #include "intel_casf.h"
> #include "intel_casf_regs.h"
> #include "intel_de.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index d8739e2bb004..3f0c9c7fd5f8 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -34,7 +34,6 @@
> #include <drm/drm_print.h>
> #include <drm/drm_privacy_screen_consumer.h>
>
> -#include "i915_reg.h"
> #include "icl_dsi.h"
> #include "intel_alpm.h"
> #include "intel_audio.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index aba13e8a9051..1ce28a31affb 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -15,7 +15,6 @@
> #include <drm/drm_print.h>
>
> #include "hsw_ips.h"
> -#include "i915_reg.h"
> #include "i9xx_wm_regs.h"
> #include "intel_alpm.h"
> #include "intel_bo.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 06adf6afbec0..a6e9f1c8d2dc 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -7,8 +7,8 @@
> #include <linux/string_helpers.h>
>
> #include <drm/drm_print.h>
> +#include <drm/intel/intel_pcode.h>
>
> -#include "i915_reg.h"
> #include "intel_backlight_regs.h"
> #include "intel_cdclk.h"
> #include "intel_clock_gating.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c b/drivers/gpu/drm/i915/display/intel_display_wa.c
> index 2eb4af62d556..d9788a979561 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_wa.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_wa.c
> @@ -5,7 +5,6 @@
>
> #include <drm/drm_print.h>
>
> -#include "i915_reg.h"
> #include "intel_de.h"
> #include "intel_display_core.h"
> #include "intel_display_regs.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> index 1182bc9a2e6d..8df06b993890 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -29,7 +29,6 @@
> #include <drm/drm_file.h>
> #include <drm/drm_print.h>
>
> -#include "i915_reg.h"
> #include "intel_crtc.h"
> #include "intel_de.h"
> #include "intel_display_power_well.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
> index 5bb0090dd5ed..24ce8a7842c7 100644
> --- a/drivers/gpu/drm/i915/display/intel_fdi.c
> +++ b/drivers/gpu/drm/i915/display/intel_fdi.c
> @@ -8,7 +8,6 @@
> #include <drm/drm_fixed.h>
> #include <drm/drm_print.h>
>
> -#include "i915_reg.h"
> #include "intel_atomic.h"
> #include "intel_crtc.h"
> #include "intel_ddi.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index b7479ced7871..6110a582437c 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -17,8 +17,8 @@
> #include <drm/display/drm_hdcp_helper.h>
> #include <drm/drm_print.h>
> #include <drm/intel/i915_component.h>
> +#include <drm/intel/intel_pcode.h>
>
> -#include "i915_reg.h"
> #include "intel_connector.h"
> #include "intel_de.h"
> #include "intel_display_jiffies.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> index 82c39e4ffa37..8865cb2ac569 100644
> --- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> @@ -5,7 +5,6 @@
>
> #include <drm/drm_print.h>
>
> -#include "i915_reg.h"
> #include "intel_de.h"
> #include "intel_display_irq.h"
> #include "intel_display_regs.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index 04f63bdd0b87..1df23447fd84 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -5,7 +5,6 @@
>
> #include <drm/drm_print.h>
>
> -#include "i915_reg.h"
> #include "intel_cx0_phy.h"
> #include "intel_cx0_phy_regs.h"
> #include "intel_ddi.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
> index b217ec7aa758..2d799af73bb7 100644
> --- a/drivers/gpu/drm/i915/display/intel_pps.c
> +++ b/drivers/gpu/drm/i915/display/intel_pps.c
> @@ -9,7 +9,6 @@
> #include <drm/drm_print.h>
>
> #include "g4x_dp.h"
> -#include "i915_reg.h"
> #include "intel_de.h"
> #include "intel_display_jiffies.h"
> #include "intel_display_power_well.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
> index 064f572bbc85..78ed9c58a72f 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.c
> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> @@ -7,7 +7,6 @@
>
> #include <drm/drm_print.h>
>
> -#include "i915_reg.h"
> #include "intel_atomic.h"
> #include "intel_cx0_phy_regs.h"
> #include "intel_ddi.h"
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index b41da10f0f85..9efb94b4cbdb 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -7,8 +7,8 @@
>
> #include <drm/drm_blend.h>
> #include <drm/drm_print.h>
> +#include <drm/intel/intel_pcode.h>
>
> -#include "i915_reg.h"
> #include "i9xx_wm.h"
> #include "intel_atomic.h"
> #include "intel_bw.h"
> diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
> index d705af3bf8ba..67f0082d3a69 100644
> --- a/drivers/gpu/drm/i915/display/vlv_dsi.c
> +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
> @@ -33,7 +33,6 @@
> #include <drm/drm_print.h>
> #include <drm/drm_probe_helper.h>
>
> -#include "i915_reg.h"
> #include "intel_atomic.h"
> #include "intel_backlight.h"
> #include "intel_connector.h"
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [v3 13/19] drm/i915: Remove i915_reg.h from intel_rom.c
2026-01-29 21:13 ` [v3 13/19] drm/i915: Remove i915_reg.h from intel_rom.c Uma Shankar
@ 2026-02-03 16:22 ` Ville Syrjälä
2026-02-05 7:38 ` Shankar, Uma
0 siblings, 1 reply; 43+ messages in thread
From: Ville Syrjälä @ 2026-02-03 16:22 UTC (permalink / raw)
To: Uma Shankar; +Cc: intel-gfx, intel-xe, jani.nikula
On Fri, Jan 30, 2026 at 02:43:52AM +0530, Uma Shankar wrote:
> Make intel_rom.c free from including i915_reg.h.
>
> v3: Update patch header
>
> v2: Use display header instead of gmd common include (Jani)
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display_regs.h | 8 ++++++++
> drivers/gpu/drm/i915/display/intel_rom.c | 3 +--
> drivers/gpu/drm/i915/i915_reg.h | 8 --------
> 3 files changed, 9 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index 5679a83ff19b..3707c5999ffb 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -10,6 +10,14 @@
> #define GU_CNTL_PROTECTED _MMIO(0x10100C)
> #define DEPRESENT REG_BIT(9)
>
> +#define PRIMARY_SPI_TRIGGER _MMIO(0x102040)
> +#define PRIMARY_SPI_ADDRESS _MMIO(0x102080)
> +#define PRIMARY_SPI_REGIONID _MMIO(0x102084)
> +#define SPI_STATIC_REGIONS _MMIO(0x102090)
> +#define OPTIONROM_SPI_REGIONID_MASK REG_GENMASK(7, 0)
> +#define OROM_OFFSET _MMIO(0x1020c0)
> +#define OROM_OFFSET_MASK REG_GENMASK(20, 16)
Those don't look like display registers to me. Should probably
live in some more specific header.
> +
> #define _GEN7_PIPEA_DE_LOAD_SL 0x70068
> #define _GEN7_PIPEB_DE_LOAD_SL 0x71068
> #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL)
> diff --git a/drivers/gpu/drm/i915/display/intel_rom.c b/drivers/gpu/drm/i915/display/intel_rom.c
> index c8f615315310..d7de53acaba9 100644
> --- a/drivers/gpu/drm/i915/display/intel_rom.c
> +++ b/drivers/gpu/drm/i915/display/intel_rom.c
> @@ -7,10 +7,9 @@
>
> #include <drm/drm_device.h>
>
> -#include "i915_reg.h"
> -
> #include "intel_rom.h"
> #include "intel_uncore.h"
> +#include "intel_display_regs.h"
>
> struct intel_rom {
> /* for PCI ROM */
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 635726f01e9a..f896ece3b568 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -898,14 +898,6 @@
> #define SGGI_DIS REG_BIT(15)
> #define SGR_DIS REG_BIT(13)
>
> -#define PRIMARY_SPI_TRIGGER _MMIO(0x102040)
> -#define PRIMARY_SPI_ADDRESS _MMIO(0x102080)
> -#define PRIMARY_SPI_REGIONID _MMIO(0x102084)
> -#define SPI_STATIC_REGIONS _MMIO(0x102090)
> -#define OPTIONROM_SPI_REGIONID_MASK REG_GENMASK(7, 0)
> -#define OROM_OFFSET _MMIO(0x1020c0)
> -#define OROM_OFFSET_MASK REG_GENMASK(20, 16)
> -
> #define MTL_MEDIA_GSI_BASE 0x380000
>
> #endif /* _I915_REG_H_ */
> --
> 2.50.1
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [v3 11/19] drm/i915: Remove i915_reg.h from i9xx_wm.c
2026-01-29 21:13 ` [v3 11/19] drm/i915: Remove i915_reg.h from i9xx_wm.c Uma Shankar
2026-02-03 12:42 ` Jani Nikula
@ 2026-02-03 16:27 ` Ville Syrjälä
2026-02-05 7:36 ` Shankar, Uma
1 sibling, 1 reply; 43+ messages in thread
From: Ville Syrjälä @ 2026-02-03 16:27 UTC (permalink / raw)
To: Uma Shankar; +Cc: intel-gfx, intel-xe, jani.nikula
On Fri, Jan 30, 2026 at 02:43:50AM +0530, Uma Shankar wrote:
> Move FW_BLC_SELF to common header to make i9xx_wm.c
> free from i915_reg.h include. Introduce a common
> intel_gmd_misc_regs.h to define common miscellaneous
> register definitions across graphics and display.
>
> v2: Introdue a common misc header for GMD
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/i915/display/i9xx_wm.c | 2 +-
> .../gpu/drm/i915/display/intel_display_regs.h | 8 ++++++-
> drivers/gpu/drm/i915/i915_reg.h | 20 +-----------------
> include/drm/intel/intel_gmd_misc_regs.h | 21 +++++++++++++++++++
> 4 files changed, 30 insertions(+), 21 deletions(-)
> create mode 100644 include/drm/intel/intel_gmd_misc_regs.h
>
> diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
> index 39dfceb438ae..24f898efa9dd 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_wm.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
> @@ -6,8 +6,8 @@
> #include <linux/iopoll.h>
>
> #include <drm/drm_print.h>
> +#include <drm/intel/intel_gmd_misc_regs.h>
>
> -#include "i915_reg.h"
> #include "i9xx_wm.h"
> #include "i9xx_wm_regs.h"
> #include "intel_atomic.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index 0164dcbb709f..680020e590cb 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -4,6 +4,7 @@
> #ifndef __INTEL_DISPLAY_REGS_H__
> #define __INTEL_DISPLAY_REGS_H__
>
> +#include <drm/intel/intel_gmd_misc_regs.h>
> #include "intel_display_reg_defs.h"
>
> #define GU_CNTL_PROTECTED _MMIO(0x10100C)
> @@ -3119,6 +3120,11 @@ enum skl_power_gate {
> #define MTL_TRAS_MASK REG_GENMASK(16, 8)
> #define MTL_TRDPRE_MASK REG_GENMASK(7, 0)
>
> -
> +#define FW_BLC _MMIO(0x20d8)
> +#define FW_BLC2 _MMIO(0x20dc)
> +#define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */
> +#define FW_BLC_SELF_EN_MASK REG_BIT(31)
> +#define FW_BLC_SELF_FIFO_MASK REG_BIT(16) /* 945 only */
> +#define FW_BLC_SELF_EN REG_BIT(15) /* 945 only */
>
> #endif /* __INTEL_DISPLAY_REGS_H__ */
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 6cb72e6e9086..b4b749e52b5b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -26,6 +26,7 @@
> #define _I915_REG_H_
>
> #include <drm/intel/intel_pcode.h>
> +#include <drm/intel/intel_gmd_misc_regs.h>
> #include "i915_reg_defs.h"
> #include "display/intel_display_reg_defs.h"
>
> @@ -394,24 +395,10 @@
>
> #define GEN2_ERROR_REGS I915_ERROR_REGS(EMR, EIR)
>
> -#define INSTPM _MMIO(0x20c0)
> -#define INSTPM_SELF_EN (1 << 12) /* 915GM only */
> -#define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts
> - will not assert AGPBUSY# and will only
> - be delivered when out of C3. */
> -#define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */
> -#define INSTPM_TLB_INVALIDATE (1 << 9)
> -#define INSTPM_SYNC_FLUSH (1 << 5)
> #define MEM_MODE _MMIO(0x20cc)
> #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */
> #define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */
> #define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) /* 85x only */
> -#define FW_BLC _MMIO(0x20d8)
> -#define FW_BLC2 _MMIO(0x20dc)
> -#define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */
> -#define FW_BLC_SELF_EN_MASK REG_BIT(31)
> -#define FW_BLC_SELF_FIFO_MASK REG_BIT(16) /* 945 only */
> -#define FW_BLC_SELF_EN REG_BIT(15) /* 945 only */
> #define MM_BURST_LENGTH 0x00700000
> #define MM_FIFO_WATERMARK 0x0001F000
> #define LM_BURST_LENGTH 0x00000700
> @@ -834,11 +821,6 @@
> #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT REG_BIT(14)
>
>
> -#define DISP_ARB_CTL _MMIO(0x45000)
> -#define DISP_FBC_MEMORY_WAKE REG_BIT(31)
> -#define DISP_TILE_SURFACE_SWIZZLING REG_BIT(13)
> -#define DISP_FBC_WM_DIS REG_BIT(15)
> -
> #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
> #define _LATENCY_REPORTING_REMOVED_PIPE_D REG_BIT(31)
> #define SKL_SELECT_ALTERNATE_DC_EXIT REG_BIT(30)
> diff --git a/include/drm/intel/intel_gmd_misc_regs.h b/include/drm/intel/intel_gmd_misc_regs.h
> new file mode 100644
> index 000000000000..377f4e383699
> --- /dev/null
> +++ b/include/drm/intel/intel_gmd_misc_regs.h
> @@ -0,0 +1,21 @@
> +/* SPDX-License-Identifier: MIT */
> +/* Copyright © 2026 Intel Corporation */
> +
> +#ifndef _INTEL_GMD_MISC_REG_H_
> +#define _INTEL_GMD_MISC_REG_H_
What is a "GMD"?
> +
> +#define DISP_ARB_CTL _MMIO(0x45000)
> +#define DISP_FBC_MEMORY_WAKE REG_BIT(31)
> +#define DISP_TILE_SURFACE_SWIZZLING REG_BIT(13)
> +#define DISP_FBC_WM_DIS REG_BIT(15)
That's just a regular display register. I suspect most of the
other registers relatd to the arbiter/etc. are in
intel_display_regs.h
> +
> +#define INSTPM _MMIO(0x20c0)
> +#define INSTPM_SELF_EN (1 << 12) /* 915GM only */
> +#define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts
> + will not assert AGPBUSY# and will only
> + be delivered when out of C3. */
> +#define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */
> +#define INSTPM_TLB_INVALIDATE (1 << 9)
> +#define INSTPM_SYNC_FLUSH (1 << 5)
This is not even a display register.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [v3 17/19] drm/i915: Remove i915_reg.h from intel_display_power_well.c
2026-01-29 21:13 ` [v3 17/19] drm/i915: Remove i915_reg.h from intel_display_power_well.c Uma Shankar
2026-02-03 12:49 ` Jani Nikula
@ 2026-02-03 16:34 ` Ville Syrjälä
2026-02-05 7:44 ` Shankar, Uma
1 sibling, 1 reply; 43+ messages in thread
From: Ville Syrjälä @ 2026-02-03 16:34 UTC (permalink / raw)
To: Uma Shankar; +Cc: intel-gfx, intel-xe, jani.nikula
On Fri, Jan 30, 2026 at 02:43:56AM +0530, Uma Shankar wrote:
> Make intel_display_power_well.c free from including i915_reg.h.
>
> v2: Include specific pcode header, drop common header (Jani)
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display_power_well.c | 2 +-
> drivers/gpu/drm/i915/display/intel_display_regs.h | 2 ++
> drivers/gpu/drm/i915/i915_reg.h | 3 ---
> 3 files changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index 6f9bc6f9615e..f98de1baa63d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -6,8 +6,8 @@
> #include <linux/iopoll.h>
>
> #include <drm/drm_print.h>
> +#include <drm/intel/intel_pcode.h>
>
> -#include "i915_reg.h"
> #include "intel_backlight_regs.h"
> #include "intel_combo_phy.h"
> #include "intel_combo_phy_regs.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index 4a9b7560ce8c..758749c5c322 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -359,6 +359,8 @@
> #define FW_CSPWRDWNEN (1 << 15)
>
> #define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504)
> +/* Disable display A/B trickle feed */
> +#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
>
> #define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508)
> #define CDCLK_FREQ_SHIFT 4
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9cd7fce09ebe..e4fc61dcd384 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -428,9 +428,6 @@
> #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
> #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
>
> -/* Disable display A/B trickle feed */
> -#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
> -
Instead of confusing where this bit lives on most platforms
(MI_ARB_STATE) we should probably just add a separate defition
for the VLV bit (since it has a separate register offset definition
as well).
> /* Set display plane priority */
> #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
> #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
> --
> 2.50.1
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 43+ messages in thread
* RE: [v3 10/19] drm/i915: Remove i915_reg.h from g4x_dp.c
2026-02-03 12:40 ` Jani Nikula
@ 2026-02-05 7:29 ` Shankar, Uma
0 siblings, 0 replies; 43+ messages in thread
From: Shankar, Uma @ 2026-02-05 7:29 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx@lists.freedesktop.org,
intel-xe@lists.freedesktop.org
Cc: ville.syrjala@linux.intel.com
> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Tuesday, February 3, 2026 6:10 PM
> To: Shankar, Uma <uma.shankar@intel.com>; intel-gfx@lists.freedesktop.org;
> intel-xe@lists.freedesktop.org
> Cc: ville.syrjala@linux.intel.com; Shankar, Uma <uma.shankar@intel.com>
> Subject: Re: [v3 10/19] drm/i915: Remove i915_reg.h from g4x_dp.c
>
> On Fri, 30 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> > Move DE_IRQ_REGS to display header to make g4x_dp.c free from
> > i915_reg.h dependency. These registers are only used by display and
> > gvt.
> >
> > v2: Move DE interrupt regs from common to display header (Jani)
> >
> > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/g4x_dp.c | 2 +-
> > .../gpu/drm/i915/display/intel_display_regs.h | 16 ++++++++++++++++
> > drivers/gpu/drm/i915/i915_reg.h | 15 ---------------
> > 3 files changed, 17 insertions(+), 16 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c
> > b/drivers/gpu/drm/i915/display/g4x_dp.c
> > index 4cb753177fd8..017c6dd8f9f6 100644
> > --- a/drivers/gpu/drm/i915/display/g4x_dp.c
> > +++ b/drivers/gpu/drm/i915/display/g4x_dp.c
> > @@ -8,9 +8,9 @@
> > #include <linux/string_helpers.h>
> >
> > #include <drm/drm_print.h>
> > +#include <drm/intel/intel_gmd_interrupt.h>
>
> How's this required in this patch? Nothing's being moved there in this patch?
Yeah, this got left over during cleanup. Thanks for pointing out.
Will fix it.
Regards,
Uma Shankar
> BR,
> Jani.
>
> >
> > #include "g4x_dp.h"
> > -#include "i915_reg.h"
> > #include "intel_audio.h"
> > #include "intel_backlight.h"
> > #include "intel_connector.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h
> > b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > index 40538910cb09..0164dcbb709f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > @@ -1049,6 +1049,15 @@
> > #define SWF3(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) +
> 0x72414 + (i) * 4)
> > #define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4)
> >
> > +#define DEISR _MMIO(0x44000)
> > +#define DEIMR _MMIO(0x44004)
> > +#define DEIIR _MMIO(0x44008)
> > +#define DEIER _MMIO(0x4400c)
> > +
> > +#define DE_IRQ_REGS I915_IRQ_REGS(DEIMR, \
> > + DEIER, \
> > + DEIIR)
> > +
> > #define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030)
> > #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
> > #define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */
> > @@ -1792,6 +1801,13 @@
> >
> SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \
> >
> SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1))
> >
> > +/* PCH */
> > +
> > +#define SDEISR _MMIO(0xc4000)
> > +#define SDEIMR _MMIO(0xc4004)
> > +#define SDEIIR _MMIO(0xc4008)
> > +#define SDEIER _MMIO(0xc400c)
> > +
> > #define SDE_IRQ_REGS I915_IRQ_REGS(SDEIMR, \
> > SDEIER, \
> > SDEIIR)
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index 22b68ddfa7b4..6cb72e6e9086
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -728,15 +728,6 @@
> > #define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master
> IER */
> > #define MASTER_INTERRUPT_ENABLE (1 << 31)
> >
> > -#define DEISR _MMIO(0x44000)
> > -#define DEIMR _MMIO(0x44004)
> > -#define DEIIR _MMIO(0x44008)
> > -#define DEIER _MMIO(0x4400c)
> > -
> > -#define DE_IRQ_REGS I915_IRQ_REGS(DEIMR, \
> > - DEIER, \
> > - DEIIR)
> > -
> > #define GTISR _MMIO(0x44010)
> > #define GTIMR _MMIO(0x44014)
> > #define GTIIR _MMIO(0x44018)
> > @@ -868,12 +859,6 @@
> > #define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14)
> > #define GMD_ID_STEP REG_GENMASK(5, 0)
> >
> > -/* PCH */
> > -
> > -#define SDEISR _MMIO(0xc4000)
> > -#define SDEIMR _MMIO(0xc4004)
> > -#define SDEIIR _MMIO(0xc4008)
> > -#define SDEIER _MMIO(0xc400c)
> >
> > /* Icelake PPS_DATA and _ECC DIP Registers.
> > * These are available for transcoders B,C and eDP.
>
> --
> Jani Nikula, Intel
^ permalink raw reply [flat|nested] 43+ messages in thread
* RE: [v3 11/19] drm/i915: Remove i915_reg.h from i9xx_wm.c
2026-02-03 12:42 ` Jani Nikula
@ 2026-02-05 7:31 ` Shankar, Uma
0 siblings, 0 replies; 43+ messages in thread
From: Shankar, Uma @ 2026-02-05 7:31 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx@lists.freedesktop.org,
intel-xe@lists.freedesktop.org
Cc: ville.syrjala@linux.intel.com
> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Tuesday, February 3, 2026 6:12 PM
> To: Shankar, Uma <uma.shankar@intel.com>; intel-gfx@lists.freedesktop.org;
> intel-xe@lists.freedesktop.org
> Cc: ville.syrjala@linux.intel.com; Shankar, Uma <uma.shankar@intel.com>
> Subject: Re: [v3 11/19] drm/i915: Remove i915_reg.h from i9xx_wm.c
>
> On Fri, 30 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> > Move FW_BLC_SELF to common header to make i9xx_wm.c free from
> > i915_reg.h include. Introduce a common intel_gmd_misc_regs.h to define
> > common miscellaneous register definitions across graphics and display.
> >
> > v2: Introdue a common misc header for GMD
> >
> > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/i9xx_wm.c | 2 +-
> > .../gpu/drm/i915/display/intel_display_regs.h | 8 ++++++-
> > drivers/gpu/drm/i915/i915_reg.h | 20 +-----------------
> > include/drm/intel/intel_gmd_misc_regs.h | 21 +++++++++++++++++++
> > 4 files changed, 30 insertions(+), 21 deletions(-) create mode
> > 100644 include/drm/intel/intel_gmd_misc_regs.h
> >
> > diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c
> > b/drivers/gpu/drm/i915/display/i9xx_wm.c
> > index 39dfceb438ae..24f898efa9dd 100644
> > --- a/drivers/gpu/drm/i915/display/i9xx_wm.c
> > +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
> > @@ -6,8 +6,8 @@
> > #include <linux/iopoll.h>
> >
> > #include <drm/drm_print.h>
> > +#include <drm/intel/intel_gmd_misc_regs.h>
> >
> > -#include "i915_reg.h"
> > #include "i9xx_wm.h"
> > #include "i9xx_wm_regs.h"
> > #include "intel_atomic.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h
> > b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > index 0164dcbb709f..680020e590cb 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > @@ -4,6 +4,7 @@
> > #ifndef __INTEL_DISPLAY_REGS_H__
> > #define __INTEL_DISPLAY_REGS_H__
> >
> > +#include <drm/intel/intel_gmd_misc_regs.h>
>
> Please only include where needed.
Sure, will update.
> > #include "intel_display_reg_defs.h"
> >
> > #define GU_CNTL_PROTECTED _MMIO(0x10100C)
> > @@ -3119,6 +3120,11 @@ enum skl_power_gate {
> > #define MTL_TRAS_MASK REG_GENMASK(16, 8)
> > #define MTL_TRDPRE_MASK REG_GENMASK(7, 0)
> >
> > -
> > +#define FW_BLC _MMIO(0x20d8)
> > +#define FW_BLC2 _MMIO(0x20dc)
> > +#define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */
> > +#define FW_BLC_SELF_EN_MASK REG_BIT(31)
> > +#define FW_BLC_SELF_FIFO_MASK REG_BIT(16) /* 945 only */
> > +#define FW_BLC_SELF_EN REG_BIT(15) /* 945 only */
> >
> > #endif /* __INTEL_DISPLAY_REGS_H__ */ diff --git
> > a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 6cb72e6e9086..b4b749e52b5b 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -26,6 +26,7 @@
> > #define _I915_REG_H_
> >
> > #include <drm/intel/intel_pcode.h>
> > +#include <drm/intel/intel_gmd_misc_regs.h>
>
> Please only include where needed.
Will do.
> > #include "i915_reg_defs.h"
> > #include "display/intel_display_reg_defs.h"
> >
> > @@ -394,24 +395,10 @@
> >
> > #define GEN2_ERROR_REGS I915_ERROR_REGS(EMR, EIR)
> >
> > -#define INSTPM _MMIO(0x20c0)
> > -#define INSTPM_SELF_EN (1 << 12) /* 915GM only */
> > -#define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled,
> pending interrupts
> > - will not assert AGPBUSY# and will only
> > - be delivered when out of C3. */
> > -#define INSTPM_FORCE_ORDERING (1 << 7) /*
> GEN6+ */
> > -#define INSTPM_TLB_INVALIDATE (1 << 9)
> > -#define INSTPM_SYNC_FLUSH (1 << 5)
> > #define MEM_MODE _MMIO(0x20cc)
> > #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */
> > #define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845
> only */
> > #define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) /* 85x only */
> > -#define FW_BLC _MMIO(0x20d8)
> > -#define FW_BLC2 _MMIO(0x20dc)
> > -#define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */
> > -#define FW_BLC_SELF_EN_MASK REG_BIT(31)
> > -#define FW_BLC_SELF_FIFO_MASK REG_BIT(16) /* 945 only */
> > -#define FW_BLC_SELF_EN REG_BIT(15) /* 945 only */
> > #define MM_BURST_LENGTH 0x00700000
> > #define MM_FIFO_WATERMARK 0x0001F000
> > #define LM_BURST_LENGTH 0x00000700
> > @@ -834,11 +821,6 @@
> > #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT
> REG_BIT(14)
> >
> >
> > -#define DISP_ARB_CTL _MMIO(0x45000)
> > -#define DISP_FBC_MEMORY_WAKE REG_BIT(31)
> > -#define DISP_TILE_SURFACE_SWIZZLING REG_BIT(13)
> > -#define DISP_FBC_WM_DIS REG_BIT(15)
> > -
> > #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
> > #define _LATENCY_REPORTING_REMOVED_PIPE_D REG_BIT(31)
> > #define SKL_SELECT_ALTERNATE_DC_EXIT REG_BIT(30)
> > diff --git a/include/drm/intel/intel_gmd_misc_regs.h
> > b/include/drm/intel/intel_gmd_misc_regs.h
> > new file mode 100644
> > index 000000000000..377f4e383699
> > --- /dev/null
> > +++ b/include/drm/intel/intel_gmd_misc_regs.h
> > @@ -0,0 +1,21 @@
> > +/* SPDX-License-Identifier: MIT */
> > +/* Copyright © 2026 Intel Corporation */
> > +
> > +#ifndef _INTEL_GMD_MISC_REG_H_
> > +#define _INTEL_GMD_MISC_REG_H_
>
> Should be REGS_H to match the file name.
Sure, will fix.
Regards,
Uma Shankar
> > +
> > +#define DISP_ARB_CTL _MMIO(0x45000)
> > +#define DISP_FBC_MEMORY_WAKE REG_BIT(31)
> > +#define DISP_TILE_SURFACE_SWIZZLING REG_BIT(13)
> > +#define DISP_FBC_WM_DIS REG_BIT(15)
> > +
> > +#define INSTPM _MMIO(0x20c0)
> > +#define INSTPM_SELF_EN (1 << 12) /* 915GM only */
> > +#define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled,
> pending interrupts
> > + will not assert AGPBUSY# and will only
> > + be delivered when out of C3. */
> > +#define INSTPM_FORCE_ORDERING (1 << 7) /*
> GEN6+ */
> > +#define INSTPM_TLB_INVALIDATE (1 << 9)
> > +#define INSTPM_SYNC_FLUSH (1 << 5)
> > +
> > +#endif
>
> --
> Jani Nikula, Intel
^ permalink raw reply [flat|nested] 43+ messages in thread
* RE: [v3 11/19] drm/i915: Remove i915_reg.h from i9xx_wm.c
2026-02-03 16:27 ` Ville Syrjälä
@ 2026-02-05 7:36 ` Shankar, Uma
0 siblings, 0 replies; 43+ messages in thread
From: Shankar, Uma @ 2026-02-05 7:36 UTC (permalink / raw)
To: Ville Syrjälä
Cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org,
Nikula, Jani
> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: Tuesday, February 3, 2026 9:57 PM
> To: Shankar, Uma <uma.shankar@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org; Nikula, Jani
> <jani.nikula@intel.com>
> Subject: Re: [v3 11/19] drm/i915: Remove i915_reg.h from i9xx_wm.c
>
> On Fri, Jan 30, 2026 at 02:43:50AM +0530, Uma Shankar wrote:
> > Move FW_BLC_SELF to common header to make i9xx_wm.c free from
> > i915_reg.h include. Introduce a common intel_gmd_misc_regs.h to define
> > common miscellaneous register definitions across graphics and display.
> >
> > v2: Introdue a common misc header for GMD
> >
> > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/i9xx_wm.c | 2 +-
> > .../gpu/drm/i915/display/intel_display_regs.h | 8 ++++++-
> > drivers/gpu/drm/i915/i915_reg.h | 20 +-----------------
> > include/drm/intel/intel_gmd_misc_regs.h | 21 +++++++++++++++++++
> > 4 files changed, 30 insertions(+), 21 deletions(-) create mode
> > 100644 include/drm/intel/intel_gmd_misc_regs.h
> >
> > diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c
> > b/drivers/gpu/drm/i915/display/i9xx_wm.c
> > index 39dfceb438ae..24f898efa9dd 100644
> > --- a/drivers/gpu/drm/i915/display/i9xx_wm.c
> > +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
> > @@ -6,8 +6,8 @@
> > #include <linux/iopoll.h>
> >
> > #include <drm/drm_print.h>
> > +#include <drm/intel/intel_gmd_misc_regs.h>
> >
> > -#include "i915_reg.h"
> > #include "i9xx_wm.h"
> > #include "i9xx_wm_regs.h"
> > #include "intel_atomic.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h
> > b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > index 0164dcbb709f..680020e590cb 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > @@ -4,6 +4,7 @@
> > #ifndef __INTEL_DISPLAY_REGS_H__
> > #define __INTEL_DISPLAY_REGS_H__
> >
> > +#include <drm/intel/intel_gmd_misc_regs.h>
> > #include "intel_display_reg_defs.h"
> >
> > #define GU_CNTL_PROTECTED _MMIO(0x10100C)
> > @@ -3119,6 +3120,11 @@ enum skl_power_gate {
> > #define MTL_TRAS_MASK REG_GENMASK(16, 8)
> > #define MTL_TRDPRE_MASK REG_GENMASK(7, 0)
> >
> > -
> > +#define FW_BLC _MMIO(0x20d8)
> > +#define FW_BLC2 _MMIO(0x20dc)
> > +#define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */
> > +#define FW_BLC_SELF_EN_MASK REG_BIT(31)
> > +#define FW_BLC_SELF_FIFO_MASK REG_BIT(16) /* 945 only */
> > +#define FW_BLC_SELF_EN REG_BIT(15) /* 945 only */
> >
> > #endif /* __INTEL_DISPLAY_REGS_H__ */ diff --git
> > a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 6cb72e6e9086..b4b749e52b5b 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -26,6 +26,7 @@
> > #define _I915_REG_H_
> >
> > #include <drm/intel/intel_pcode.h>
> > +#include <drm/intel/intel_gmd_misc_regs.h>
> > #include "i915_reg_defs.h"
> > #include "display/intel_display_reg_defs.h"
> >
> > @@ -394,24 +395,10 @@
> >
> > #define GEN2_ERROR_REGS I915_ERROR_REGS(EMR, EIR)
> >
> > -#define INSTPM _MMIO(0x20c0)
> > -#define INSTPM_SELF_EN (1 << 12) /* 915GM only */
> > -#define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled,
> pending interrupts
> > - will not assert AGPBUSY# and will only
> > - be delivered when out of C3. */
> > -#define INSTPM_FORCE_ORDERING (1 << 7) /*
> GEN6+ */
> > -#define INSTPM_TLB_INVALIDATE (1 << 9)
> > -#define INSTPM_SYNC_FLUSH (1 << 5)
> > #define MEM_MODE _MMIO(0x20cc)
> > #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */
> > #define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845
> only */
> > #define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) /* 85x only */
> > -#define FW_BLC _MMIO(0x20d8)
> > -#define FW_BLC2 _MMIO(0x20dc)
> > -#define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */
> > -#define FW_BLC_SELF_EN_MASK REG_BIT(31)
> > -#define FW_BLC_SELF_FIFO_MASK REG_BIT(16) /* 945 only */
> > -#define FW_BLC_SELF_EN REG_BIT(15) /* 945 only */
> > #define MM_BURST_LENGTH 0x00700000
> > #define MM_FIFO_WATERMARK 0x0001F000
> > #define LM_BURST_LENGTH 0x00000700
> > @@ -834,11 +821,6 @@
> > #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT
> REG_BIT(14)
> >
> >
> > -#define DISP_ARB_CTL _MMIO(0x45000)
> > -#define DISP_FBC_MEMORY_WAKE REG_BIT(31)
> > -#define DISP_TILE_SURFACE_SWIZZLING REG_BIT(13)
> > -#define DISP_FBC_WM_DIS REG_BIT(15)
> > -
> > #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
> > #define _LATENCY_REPORTING_REMOVED_PIPE_D REG_BIT(31)
> > #define SKL_SELECT_ALTERNATE_DC_EXIT REG_BIT(30)
> > diff --git a/include/drm/intel/intel_gmd_misc_regs.h
> > b/include/drm/intel/intel_gmd_misc_regs.h
> > new file mode 100644
> > index 000000000000..377f4e383699
> > --- /dev/null
> > +++ b/include/drm/intel/intel_gmd_misc_regs.h
> > @@ -0,0 +1,21 @@
> > +/* SPDX-License-Identifier: MIT */
> > +/* Copyright © 2026 Intel Corporation */
> > +
> > +#ifndef _INTEL_GMD_MISC_REG_H_
> > +#define _INTEL_GMD_MISC_REG_H_
>
> What is a "GMD"?
For all common ones, I have used Graphics Media Display (GMD) as referred by
bspec as well.
> > +
> > +#define DISP_ARB_CTL _MMIO(0x45000)
> > +#define DISP_FBC_MEMORY_WAKE REG_BIT(31)
> > +#define DISP_TILE_SURFACE_SWIZZLING REG_BIT(13)
> > +#define DISP_FBC_WM_DIS REG_BIT(15)
>
> That's just a regular display register. I suspect most of the other registers relatd to
> the arbiter/etc. are in intel_display_regs.h
Yeah I also thought so, but this is used by intel_ggtt_fencing.c. Hence had to keep it
in the common header.
> > +
> > +#define INSTPM _MMIO(0x20c0)
> > +#define INSTPM_SELF_EN (1 << 12) /* 915GM only */
> > +#define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled,
> pending interrupts
> > + will not assert AGPBUSY# and will only
> > + be delivered when out of C3. */
> > +#define INSTPM_FORCE_ORDERING (1 << 7) /*
> GEN6+ */
> > +#define INSTPM_TLB_INVALIDATE (1 << 9)
> > +#define INSTPM_SYNC_FLUSH (1 << 5)
>
> This is not even a display register.
Yeah, but this is being used in intel_display_debugfs and in i9xx_wm.c.
So had to keep in a common header.
Regards,
Uma Shankar
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 43+ messages in thread
* RE: [v3 13/19] drm/i915: Remove i915_reg.h from intel_rom.c
2026-02-03 16:22 ` Ville Syrjälä
@ 2026-02-05 7:38 ` Shankar, Uma
0 siblings, 0 replies; 43+ messages in thread
From: Shankar, Uma @ 2026-02-05 7:38 UTC (permalink / raw)
To: Ville Syrjälä
Cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org,
Nikula, Jani
> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: Tuesday, February 3, 2026 9:52 PM
> To: Shankar, Uma <uma.shankar@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org; Nikula, Jani
> <jani.nikula@intel.com>
> Subject: Re: [v3 13/19] drm/i915: Remove i915_reg.h from intel_rom.c
>
> On Fri, Jan 30, 2026 at 02:43:52AM +0530, Uma Shankar wrote:
> > Make intel_rom.c free from including i915_reg.h.
> >
> > v3: Update patch header
> >
> > v2: Use display header instead of gmd common include (Jani)
> >
> > Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display_regs.h | 8 ++++++++
> > drivers/gpu/drm/i915/display/intel_rom.c | 3 +--
> > drivers/gpu/drm/i915/i915_reg.h | 8 --------
> > 3 files changed, 9 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h
> > b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > index 5679a83ff19b..3707c5999ffb 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > @@ -10,6 +10,14 @@
> > #define GU_CNTL_PROTECTED _MMIO(0x10100C)
> > #define DEPRESENT REG_BIT(9)
> >
> > +#define PRIMARY_SPI_TRIGGER _MMIO(0x102040)
> > +#define PRIMARY_SPI_ADDRESS _MMIO(0x102080)
> > +#define PRIMARY_SPI_REGIONID _MMIO(0x102084)
> > +#define SPI_STATIC_REGIONS _MMIO(0x102090)
> > +#define OPTIONROM_SPI_REGIONID_MASK
> REG_GENMASK(7, 0)
> > +#define OROM_OFFSET _MMIO(0x1020c0)
> > +#define OROM_OFFSET_MASK REG_GENMASK(20, 16)
>
> Those don't look like display registers to me. Should probably live in some more
> specific header.
Sure, will create a new file intel_oprom_regs.h to keep these out of display header.
Hope this is fine.
Regards,
Uma Shankar
> > +
> > #define _GEN7_PIPEA_DE_LOAD_SL 0x70068
> > #define _GEN7_PIPEB_DE_LOAD_SL 0x71068
> > #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe,
> > _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL) diff --git
> > a/drivers/gpu/drm/i915/display/intel_rom.c
> > b/drivers/gpu/drm/i915/display/intel_rom.c
> > index c8f615315310..d7de53acaba9 100644
> > --- a/drivers/gpu/drm/i915/display/intel_rom.c
> > +++ b/drivers/gpu/drm/i915/display/intel_rom.c
> > @@ -7,10 +7,9 @@
> >
> > #include <drm/drm_device.h>
> >
> > -#include "i915_reg.h"
> > -
> > #include "intel_rom.h"
> > #include "intel_uncore.h"
> > +#include "intel_display_regs.h"
> >
> > struct intel_rom {
> > /* for PCI ROM */
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index 635726f01e9a..f896ece3b568
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -898,14 +898,6 @@
> > #define SGGI_DIS REG_BIT(15)
> > #define SGR_DIS REG_BIT(13)
> >
> > -#define PRIMARY_SPI_TRIGGER _MMIO(0x102040)
> > -#define PRIMARY_SPI_ADDRESS _MMIO(0x102080)
> > -#define PRIMARY_SPI_REGIONID _MMIO(0x102084)
> > -#define SPI_STATIC_REGIONS _MMIO(0x102090)
> > -#define OPTIONROM_SPI_REGIONID_MASK
> REG_GENMASK(7, 0)
> > -#define OROM_OFFSET _MMIO(0x1020c0)
> > -#define OROM_OFFSET_MASK REG_GENMASK(20, 16)
> > -
> > #define MTL_MEDIA_GSI_BASE 0x380000
> >
> > #endif /* _I915_REG_H_ */
> > --
> > 2.50.1
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 43+ messages in thread
* RE: [v3 17/19] drm/i915: Remove i915_reg.h from intel_display_power_well.c
2026-02-03 12:49 ` Jani Nikula
@ 2026-02-05 7:40 ` Shankar, Uma
0 siblings, 0 replies; 43+ messages in thread
From: Shankar, Uma @ 2026-02-05 7:40 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx@lists.freedesktop.org,
intel-xe@lists.freedesktop.org
Cc: ville.syrjala@linux.intel.com
> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Tuesday, February 3, 2026 6:19 PM
> To: Shankar, Uma <uma.shankar@intel.com>; intel-gfx@lists.freedesktop.org;
> intel-xe@lists.freedesktop.org
> Cc: ville.syrjala@linux.intel.com; Shankar, Uma <uma.shankar@intel.com>
> Subject: Re: [v3 17/19] drm/i915: Remove i915_reg.h from
> intel_display_power_well.c
>
> On Fri, 30 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> > Make intel_display_power_well.c free from including i915_reg.h.
> >
> > v2: Include specific pcode header, drop common header (Jani)
> >
> > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display_power_well.c | 2 +-
> > drivers/gpu/drm/i915/display/intel_display_regs.h | 2 ++
> > drivers/gpu/drm/i915/i915_reg.h | 3 ---
> > 3 files changed, 3 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > index 6f9bc6f9615e..f98de1baa63d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > @@ -6,8 +6,8 @@
> > #include <linux/iopoll.h>
> >
> > #include <drm/drm_print.h>
> > +#include <drm/intel/intel_pcode.h>
>
> Hmm, nothing's being moved there in this patch, so this change feels unrelated.
Yeah, this got missed. Thanks Jani for spotting it.
Will fix.
Regards,
Uma Shankar
> BR,
> Jani.
>
> >
> > -#include "i915_reg.h"
> > #include "intel_backlight_regs.h"
> > #include "intel_combo_phy.h"
> > #include "intel_combo_phy_regs.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h
> > b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > index 4a9b7560ce8c..758749c5c322 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > @@ -359,6 +359,8 @@
> > #define FW_CSPWRDWNEN (1 << 15)
> >
> > #define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504)
> > +/* Disable display A/B trickle feed */
> > +#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
> >
> > #define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE +
> 0x6508)
> > #define CDCLK_FREQ_SHIFT 4
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index 9cd7fce09ebe..e4fc61dcd384
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -428,9 +428,6 @@
> > #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /*
> default */
> > #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
> >
> > -/* Disable display A/B trickle feed */
> > -#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
> > -
> > /* Set display plane priority */
> > #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display
> A > display B */
> > #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display
> B > display A */
>
> --
> Jani Nikula, Intel
^ permalink raw reply [flat|nested] 43+ messages in thread
* RE: [v3 17/19] drm/i915: Remove i915_reg.h from intel_display_power_well.c
2026-02-03 16:34 ` Ville Syrjälä
@ 2026-02-05 7:44 ` Shankar, Uma
0 siblings, 0 replies; 43+ messages in thread
From: Shankar, Uma @ 2026-02-05 7:44 UTC (permalink / raw)
To: Ville Syrjälä
Cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org,
Nikula, Jani
> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: Tuesday, February 3, 2026 10:05 PM
> To: Shankar, Uma <uma.shankar@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org; Nikula, Jani
> <jani.nikula@intel.com>
> Subject: Re: [v3 17/19] drm/i915: Remove i915_reg.h from
> intel_display_power_well.c
>
> On Fri, Jan 30, 2026 at 02:43:56AM +0530, Uma Shankar wrote:
> > Make intel_display_power_well.c free from including i915_reg.h.
> >
> > v2: Include specific pcode header, drop common header (Jani)
> >
> > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display_power_well.c | 2 +-
> > drivers/gpu/drm/i915/display/intel_display_regs.h | 2 ++
> > drivers/gpu/drm/i915/i915_reg.h | 3 ---
> > 3 files changed, 3 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > index 6f9bc6f9615e..f98de1baa63d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > @@ -6,8 +6,8 @@
> > #include <linux/iopoll.h>
> >
> > #include <drm/drm_print.h>
> > +#include <drm/intel/intel_pcode.h>
> >
> > -#include "i915_reg.h"
> > #include "intel_backlight_regs.h"
> > #include "intel_combo_phy.h"
> > #include "intel_combo_phy_regs.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h
> > b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > index 4a9b7560ce8c..758749c5c322 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > @@ -359,6 +359,8 @@
> > #define FW_CSPWRDWNEN (1 << 15)
> >
> > #define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504)
> > +/* Disable display A/B trickle feed */
> > +#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
> >
> > #define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE +
> 0x6508)
> > #define CDCLK_FREQ_SHIFT 4
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index 9cd7fce09ebe..e4fc61dcd384
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -428,9 +428,6 @@
> > #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /*
> default */
> > #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
> >
> > -/* Disable display A/B trickle feed */
> > -#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
> > -
>
> Instead of confusing where this bit lives on most platforms
> (MI_ARB_STATE) we should probably just add a separate defition for the VLV bit
> (since it has a separate register offset definition as well).
Sure, will fix it.
Regards,
Uma Shankar
> > /* Set display plane priority */
> > #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display
> A > display B */
> > #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display
> B > display A */
> > --
> > 2.50.1
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 43+ messages in thread
* RE: [v3 19/19] drm/{i915, xe}: Remove i915_reg.h from display
2026-02-03 12:50 ` Jani Nikula
@ 2026-02-05 7:48 ` Shankar, Uma
0 siblings, 0 replies; 43+ messages in thread
From: Shankar, Uma @ 2026-02-05 7:48 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx@lists.freedesktop.org,
intel-xe@lists.freedesktop.org
Cc: ville.syrjala@linux.intel.com
> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Tuesday, February 3, 2026 6:21 PM
> To: Shankar, Uma <uma.shankar@intel.com>; intel-gfx@lists.freedesktop.org;
> intel-xe@lists.freedesktop.org
> Cc: ville.syrjala@linux.intel.com; Shankar, Uma <uma.shankar@intel.com>
> Subject: Re: [v3 19/19] drm/{i915, xe}: Remove i915_reg.h from display
>
> On Fri, 30 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> > Make display files free from including i915_reg.h.
> >
> > v2: Include modular per component headers (Jani)
> >
> > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/hsw_ips.c | 2 +-
> > drivers/gpu/drm/i915/display/i9xx_plane.c | 1 -
> > drivers/gpu/drm/i915/display/icl_dsi.c | 1 -
> > drivers/gpu/drm/i915/display/intel_backlight.c | 1 -
> > drivers/gpu/drm/i915/display/intel_bw.c | 2 +-
> > drivers/gpu/drm/i915/display/intel_casf.c | 1 -
> > drivers/gpu/drm/i915/display/intel_ddi.c | 1 -
> > drivers/gpu/drm/i915/display/intel_display_debugfs.c | 1 -
> > drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
> > drivers/gpu/drm/i915/display/intel_display_wa.c | 1 -
> > drivers/gpu/drm/i915/display/intel_dmc.c | 1 -
> > drivers/gpu/drm/i915/display/intel_fdi.c | 1 -
> > drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
> > drivers/gpu/drm/i915/display/intel_hotplug_irq.c | 1 -
> > drivers/gpu/drm/i915/display/intel_lt_phy.c | 1 -
> > drivers/gpu/drm/i915/display/intel_pps.c | 1 -
> > drivers/gpu/drm/i915/display/intel_tc.c | 1 -
> > drivers/gpu/drm/i915/display/skl_watermark.c | 2 +-
> > drivers/gpu/drm/i915/display/vlv_dsi.c | 1 -
> > 19 files changed, 5 insertions(+), 19 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/hsw_ips.c
> > b/drivers/gpu/drm/i915/display/hsw_ips.c
> > index 0caaea2e64e1..5697fa4eb11f 100644
> > --- a/drivers/gpu/drm/i915/display/hsw_ips.c
> > +++ b/drivers/gpu/drm/i915/display/hsw_ips.c
> > @@ -6,9 +6,9 @@
> > #include <linux/debugfs.h>
> >
> > #include <drm/drm_print.h>
> > +#include <drm/intel/intel_pcode.h>
>
> Nothing's being added there in this patch, so this feels unrelated. Ditto below.
>
> I think it'll lead to a better overall series if intel_pcode.h (or
> intel_pcode_regs.h) isn't included in i915_reg.h but rather everywhere it's needed.
Yes Jani, will fix this and have it included only where needed.
Regards,
Uma Shankar
> BR,
> Jani.
>
>
> >
> > #include "hsw_ips.h"
> > -#include "i915_reg.h"
> > #include "intel_color_regs.h"
> > #include "intel_de.h"
> > #include "intel_display_regs.h"
> > diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
> > b/drivers/gpu/drm/i915/display/i9xx_plane.c
> > index b1fecf178906..9c16753a1f3b 100644
> > --- a/drivers/gpu/drm/i915/display/i9xx_plane.c
> > +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
> > @@ -10,7 +10,6 @@
> > #include <drm/drm_fourcc.h>
> > #include <drm/drm_print.h>
> >
> > -#include "i915_reg.h"
> > #include "i9xx_plane.h"
> > #include "i9xx_plane_regs.h"
> > #include "intel_atomic.h"
> > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> > b/drivers/gpu/drm/i915/display/icl_dsi.c
> > index c8e0333706c1..7cf511a6c0f9 100644
> > --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> > @@ -34,7 +34,6 @@
> > #include <drm/drm_print.h>
> > #include <drm/drm_probe_helper.h>
> >
> > -#include "i915_reg.h"
> > #include "icl_dsi.h"
> > #include "icl_dsi_regs.h"
> > #include "intel_atomic.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c
> > b/drivers/gpu/drm/i915/display/intel_backlight.c
> > index a68fdbd2acb9..34e95f05936e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_backlight.c
> > +++ b/drivers/gpu/drm/i915/display/intel_backlight.c
> > @@ -12,7 +12,6 @@
> > #include <drm/drm_file.h>
> > #include <drm/drm_print.h>
> >
> > -#include "i915_reg.h"
> > #include "intel_backlight.h"
> > #include "intel_backlight_regs.h"
> > #include "intel_connector.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> > b/drivers/gpu/drm/i915/display/intel_bw.c
> > index 8d84445c69f1..71149d8bcd73 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bw.c
> > +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> > @@ -5,8 +5,8 @@
> >
> > #include <drm/drm_atomic_state_helper.h> #include <drm/drm_print.h>
> > +#include <drm/intel/intel_pcode.h>
> >
> > -#include "i915_reg.h"
> > #include "intel_bw.h"
> > #include "intel_crtc.h"
> > #include "intel_display_core.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_casf.c
> > b/drivers/gpu/drm/i915/display/intel_casf.c
> > index 0fe4398a1a4e..b167af31de5b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_casf.c
> > +++ b/drivers/gpu/drm/i915/display/intel_casf.c
> > @@ -3,7 +3,6 @@
> >
> > #include <drm/drm_print.h>
> >
> > -#include "i915_reg.h"
> > #include "intel_casf.h"
> > #include "intel_casf_regs.h"
> > #include "intel_de.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index d8739e2bb004..3f0c9c7fd5f8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -34,7 +34,6 @@
> > #include <drm/drm_print.h>
> > #include <drm/drm_privacy_screen_consumer.h>
> >
> > -#include "i915_reg.h"
> > #include "icl_dsi.h"
> > #include "intel_alpm.h"
> > #include "intel_audio.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > index aba13e8a9051..1ce28a31affb 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > @@ -15,7 +15,6 @@
> > #include <drm/drm_print.h>
> >
> > #include "hsw_ips.h"
> > -#include "i915_reg.h"
> > #include "i9xx_wm_regs.h"
> > #include "intel_alpm.h"
> > #include "intel_bo.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> > b/drivers/gpu/drm/i915/display/intel_display_power.c
> > index 06adf6afbec0..a6e9f1c8d2dc 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > @@ -7,8 +7,8 @@
> > #include <linux/string_helpers.h>
> >
> > #include <drm/drm_print.h>
> > +#include <drm/intel/intel_pcode.h>
> >
> > -#include "i915_reg.h"
> > #include "intel_backlight_regs.h"
> > #include "intel_cdclk.h"
> > #include "intel_clock_gating.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c
> > b/drivers/gpu/drm/i915/display/intel_display_wa.c
> > index 2eb4af62d556..d9788a979561 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_wa.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_wa.c
> > @@ -5,7 +5,6 @@
> >
> > #include <drm/drm_print.h>
> >
> > -#include "i915_reg.h"
> > #include "intel_de.h"
> > #include "intel_display_core.h"
> > #include "intel_display_regs.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
> > b/drivers/gpu/drm/i915/display/intel_dmc.c
> > index 1182bc9a2e6d..8df06b993890 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> > @@ -29,7 +29,6 @@
> > #include <drm/drm_file.h>
> > #include <drm/drm_print.h>
> >
> > -#include "i915_reg.h"
> > #include "intel_crtc.h"
> > #include "intel_de.h"
> > #include "intel_display_power_well.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c
> > b/drivers/gpu/drm/i915/display/intel_fdi.c
> > index 5bb0090dd5ed..24ce8a7842c7 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fdi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fdi.c
> > @@ -8,7 +8,6 @@
> > #include <drm/drm_fixed.h>
> > #include <drm/drm_print.h>
> >
> > -#include "i915_reg.h"
> > #include "intel_atomic.h"
> > #include "intel_crtc.h"
> > #include "intel_ddi.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > index b7479ced7871..6110a582437c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > @@ -17,8 +17,8 @@
> > #include <drm/display/drm_hdcp_helper.h> #include <drm/drm_print.h>
> > #include <drm/intel/i915_component.h>
> > +#include <drm/intel/intel_pcode.h>
> >
> > -#include "i915_reg.h"
> > #include "intel_connector.h"
> > #include "intel_de.h"
> > #include "intel_display_jiffies.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> > b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> > index 82c39e4ffa37..8865cb2ac569 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> > @@ -5,7 +5,6 @@
> >
> > #include <drm/drm_print.h>
> >
> > -#include "i915_reg.h"
> > #include "intel_de.h"
> > #include "intel_display_irq.h"
> > #include "intel_display_regs.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > index 04f63bdd0b87..1df23447fd84 100644
> > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > @@ -5,7 +5,6 @@
> >
> > #include <drm/drm_print.h>
> >
> > -#include "i915_reg.h"
> > #include "intel_cx0_phy.h"
> > #include "intel_cx0_phy_regs.h"
> > #include "intel_ddi.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
> > b/drivers/gpu/drm/i915/display/intel_pps.c
> > index b217ec7aa758..2d799af73bb7 100644
> > --- a/drivers/gpu/drm/i915/display/intel_pps.c
> > +++ b/drivers/gpu/drm/i915/display/intel_pps.c
> > @@ -9,7 +9,6 @@
> > #include <drm/drm_print.h>
> >
> > #include "g4x_dp.h"
> > -#include "i915_reg.h"
> > #include "intel_de.h"
> > #include "intel_display_jiffies.h"
> > #include "intel_display_power_well.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
> > b/drivers/gpu/drm/i915/display/intel_tc.c
> > index 064f572bbc85..78ed9c58a72f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_tc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> > @@ -7,7 +7,6 @@
> >
> > #include <drm/drm_print.h>
> >
> > -#include "i915_reg.h"
> > #include "intel_atomic.h"
> > #include "intel_cx0_phy_regs.h"
> > #include "intel_ddi.h"
> > diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
> > b/drivers/gpu/drm/i915/display/skl_watermark.c
> > index b41da10f0f85..9efb94b4cbdb 100644
> > --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> > +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> > @@ -7,8 +7,8 @@
> >
> > #include <drm/drm_blend.h>
> > #include <drm/drm_print.h>
> > +#include <drm/intel/intel_pcode.h>
> >
> > -#include "i915_reg.h"
> > #include "i9xx_wm.h"
> > #include "intel_atomic.h"
> > #include "intel_bw.h"
> > diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c
> > b/drivers/gpu/drm/i915/display/vlv_dsi.c
> > index d705af3bf8ba..67f0082d3a69 100644
> > --- a/drivers/gpu/drm/i915/display/vlv_dsi.c
> > +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
> > @@ -33,7 +33,6 @@
> > #include <drm/drm_print.h>
> > #include <drm/drm_probe_helper.h>
> >
> > -#include "i915_reg.h"
> > #include "intel_atomic.h"
> > #include "intel_backlight.h"
> > #include "intel_connector.h"
>
> --
> Jani Nikula, Intel
^ permalink raw reply [flat|nested] 43+ messages in thread
end of thread, other threads:[~2026-02-05 7:48 UTC | newest]
Thread overview: 43+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-01-29 21:13 [v3 00/19] Make Display free from i915_reg.h Uma Shankar
2026-01-29 21:07 ` ✗ CI.checkpatch: warning for Make Display free from i915_reg.h (rev3) Patchwork
2026-01-29 21:08 ` ✓ CI.KUnit: success " Patchwork
2026-01-29 21:13 ` [v3 01/19] drm/i915: Extract display registers from i915_reg.h to display Uma Shankar
2026-01-29 21:13 ` [v3 02/19] drm/i915: Extract South chicken " Uma Shankar
2026-01-29 21:13 ` [v3 03/19] drm/i915: Extract display interrupt definitions Uma Shankar
2026-01-29 21:13 ` [v3 04/19] drm/i915: Extract DSPCLK_GATE_D from i915_reg to display Uma Shankar
2026-01-29 21:13 ` [v3 05/19] drm/{i915, xe}: Extract pcode definitions to common header Uma Shankar
2026-02-03 12:00 ` Jani Nikula
2026-01-29 21:13 ` [v3 06/19] drm/i915: Remove i915_reg.h from intel_display_device.c Uma Shankar
2026-02-03 12:06 ` Jani Nikula
2026-01-29 21:13 ` [v3 07/19] drm/i915: Remove i915_reg.h from intel_dram.c Uma Shankar
2026-02-03 11:50 ` Jani Nikula
2026-01-29 21:13 ` [v3 08/19] drm/i915: Remove i915_reg.h from intel_display.c Uma Shankar
2026-01-29 21:13 ` [v3 09/19] drm/i915: Remove i915_reg.h from intel_overlay.c Uma Shankar
2026-02-03 12:39 ` Jani Nikula
2026-01-29 21:13 ` [v3 10/19] drm/i915: Remove i915_reg.h from g4x_dp.c Uma Shankar
2026-02-03 12:40 ` Jani Nikula
2026-02-05 7:29 ` Shankar, Uma
2026-01-29 21:13 ` [v3 11/19] drm/i915: Remove i915_reg.h from i9xx_wm.c Uma Shankar
2026-02-03 12:42 ` Jani Nikula
2026-02-05 7:31 ` Shankar, Uma
2026-02-03 16:27 ` Ville Syrjälä
2026-02-05 7:36 ` Shankar, Uma
2026-01-29 21:13 ` [v3 12/19] drm/{i915, xe}: Remove i915_reg.h from g4x_hdmi.c Uma Shankar
2026-01-29 21:13 ` [v3 13/19] drm/i915: Remove i915_reg.h from intel_rom.c Uma Shankar
2026-02-03 16:22 ` Ville Syrjälä
2026-02-05 7:38 ` Shankar, Uma
2026-01-29 21:13 ` [v3 14/19] drm/i915: Remove i915_reg.h from intel_psr.c Uma Shankar
2026-01-29 21:13 ` [v3 15/19] drm/i915: Remove i915_reg.h from intel_fifo_underrun.c Uma Shankar
2026-02-03 12:47 ` Jani Nikula
2026-01-29 21:13 ` [v3 16/19] drm/i915: Remove i915_reg.h from intel_display_irq.c Uma Shankar
2026-01-29 21:13 ` [v3 17/19] drm/i915: Remove i915_reg.h from intel_display_power_well.c Uma Shankar
2026-02-03 12:49 ` Jani Nikula
2026-02-05 7:40 ` Shankar, Uma
2026-02-03 16:34 ` Ville Syrjälä
2026-02-05 7:44 ` Shankar, Uma
2026-01-29 21:13 ` [v3 18/19] drm/i915: Remove i915_reg.h from intel_modeset_setup.c Uma Shankar
2026-01-29 21:13 ` [v3 19/19] drm/{i915, xe}: Remove i915_reg.h from display Uma Shankar
2026-02-03 12:50 ` Jani Nikula
2026-02-05 7:48 ` Shankar, Uma
2026-01-29 21:27 ` ✗ CI.checksparse: warning for Make Display free from i915_reg.h (rev3) Patchwork
2026-01-29 21:45 ` ✓ Xe.CI.BAT: success " Patchwork
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