Re: [PATCH v6 0/5] Refactor default device atomic settings

[Lionel Landwerlin <lionel.g.landwerlin@intel.com>]

On 03/05/2024 12:54, Nirmoy Das wrote:
> Hi Lionel,
>
> On 5/3/2024 11:47 AM, Lionel Landwerlin wrote:
>> Hi Nirmoy,
>>
>> I've updated our Mesa MR for this : 
>> https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28823
>>
>> But then I started to wonder if we needed to do anything at all with 
>> this v6.
>
> No, there is nothing to do for traditional APIs.
>
>
>> The only scenario I'm not sure about is this : a BO is created with 2 
>> placements LMEM+SMEM. When Xe migrates the BO from LMEM to SMEM due 
>> to LMEM pressure, does it set AE bit in the PTE?
>> And then if promoted back to LMEM, is the PTE config DM=1 and AE=0 
>> again?
>
>
> For traditional API( not using fault/LR VM) then both backend will 
> have AE=1, so on LMEM pressure if the buffer is backed by SMEM, it 
> will have AE=1 as well.
>
>
> Regards,
>
> Nirmoy


Thanks a lot Nirmoy.


Then I think with this series we should have everything working in Mesa 
without having to change a single line of UMD.


-Lionel


>
>>
>> Thanks,
>>
>> -Lionel
>>
>> On 30/04/2024 19:25, Nirmoy Das wrote:
>>> The default behavior of device atomics depends on the
>>> VM type and buffer allocation types. Device atomics are
>>> expected to function with all types of allocations for
>>> traditional applications/APIs. Additionally, in compute/SVM
>>> API scenarios with fault mode or LR mode VMs, device atomics
>>> must work with single-region allocations. In all other cases
>>> device atomics should be disabled by default. PVC needs special
>>> care as it doesn't support device atomics on SMEM.
>>>
>>> v6: Only check LR mode to determine compute API as fault
>>>      mode requires LR mode(Jose)
>>>      Set AE=1 on SMEM+LMEM allocation when a buffer is migrated
>>>      to LMEM from SMEM(Brian)
>>>
>>> v5: Fix broken atomics on PVC from v4 changes.
>>>
>>> v4: Previous assumption that device atomics should be disabled
>>>      by default on SMEM only BO was wrong as traditional applications
>>>      will not use such allocations for CPU atomics. So remove the
>>>      VM bind flag and the query uAPI and instead refactor default 
>>> device
>>>      atomics settings as per VM type and buffer allocations.
>>>
>>>
>>> v3: Capture ret value of xe_vm_bind_ioctl_validate_bo(Matt B).
>>>      Remove redundant coh_mode param from 
>>> xe_vm_bind_ioctl_validate_bo().
>>>      Remove has_device_atomics_on_smem from xe_graphics_desc(Jose).
>>>      Replace DRM_XE_QUERY_CONFIG_SUPP_DEV_ATOMIC_ON_SMEM with
>>>      config flag DRM_XE_QUERY_CONFIG_FLAG_HAS_DEV_ATOMIC_ON_SMEM(Jose).
>>>      Mention that PTE_AE will not be applied to userptr(Matt R)
>>>
>>> v2: Add BO helper func in xe_vm_bind_ioctl()(Matt B).
>>>      Use XE_IOCTL_DBG for checks(Matt B).
>>>      Move platform checks with help of adding flags in
>>>      intel_device_info(Matt B).
>>>      Add document for DRM_XE_VM_BIND_FLAG_DEVICE_ATOMICS(Matt B).
>>>      Create query uAPI for this newly added VM bind flag(Jose, Lionel).
>>>
>>> Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
>>> Cc: Brian Welty <brian.welty@intel.com>
>>> Cc: Fei Yang <fei.yang@intel.com>
>>> Cc: Jose Souza <jose.souza@intel.com>
>>> Cc: Lionel G Landwerlin <lionel.g.landwerlin@intel.com>
>>> Cc: Matt Roper <matthew.d.roper@intel.com>
>>> Cc: Matthew Brost <matthew.brost@intel.com>
>>> Cc: Michal Mrozek <michal.mrozek@intel.com>
>>> Cc: Oak Zeng <oak.zeng@intel.com>
>>> Cc: Thomas Hellstr_m <thomas.hellstrom@linux.intel.com>
>>>
>>> Nirmoy Das (5):
>>>    drm/xe: Introduce has_atomic_enable_pte_bit device info
>>>    drm/xe: Move vm bind bo validation to a helper function
>>>    drm/xe: Introduce has_device_atomics_on_smem device info
>>>    drm/xe: Add function to check if BO has single placement
>>>    drm/xe: Refactor default device atomic settings
>>>
>>>   drivers/gpu/drm/xe/xe_bo.c           | 14 +++++
>>>   drivers/gpu/drm/xe/xe_bo.h           |  1 +
>>>   drivers/gpu/drm/xe/xe_device_types.h |  4 ++
>>>   drivers/gpu/drm/xe/xe_pci.c          |  5 ++
>>>   drivers/gpu/drm/xe/xe_pci_types.h    |  1 +
>>>   drivers/gpu/drm/xe/xe_pt.c           | 37 +++++++++++--
>>>   drivers/gpu/drm/xe/xe_vm.c           | 79 
>>> ++++++++++++++++------------
>>>   7 files changed, 103 insertions(+), 38 deletions(-)
>>>
>>