[PATCH v2 0/5] VRAM health check + CCS fix

[PATCH v2 0/5] VRAM health check + CCS fix

[Matthew Auld]

Add a basic VRAM health check routine, which does some basic sanity
checking on the last VRAM page. This could be extended in the future.
This seems to reproduce the same CCS issue as Linus, on my b570.

This also picks up the fix from Linus. I went with leaving it as-is,
but that means we need to fixup the identity mapping to support 4K
pages for the tail part of usable VRAM.

It doesn't look like anything in our CI actually has the CCS alignment
issue present, so merging the fix from Linus without the identity map
changes likely shouldn't trigger any asserts, if that does end up
coming in via another tree, AFAICT.

v2:
 - Give more details around what the VRAM health check actually does
   and how it catches the CCS bug (Matt B).
 - Tweak the CCS base + alignment print (Matt B).
 - Drop the fix from Linus; this is now already in drm-tip.
 - Add some hardening for VRAM CPU mapping also.

-- 
2.55.0

[PATCH v2 1/5] drm/xe/migrate: support 4K PTEs for identity map

[Matthew Auld]

When VRAM limit (usable_size) is no longer 2M aligned (e.g. because flat
CCS storage size rounds it down to 4K), we must map the tail of the
identity mapping using 4K pages.

This removes the 2M alignment assert (which pops) and introduces a 4K
fallback in the identity map programming loop to handle the last 2M
chunk of usable VRAM.

Might be possible to skip backporting this. The assert that pops should
be harmless and is only on debug builds plus only a stray write would
hit CCS, which technically get mapped.

Assisted-by: Gemini:gemini-3.1-pro-preview
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
---
 drivers/gpu/drm/xe/xe_migrate.c | 57 +++++++++++++++++++++------------
 1 file changed, 37 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
index 75b83687f1b5..0bf000d7c901 100644
--- a/drivers/gpu/drm/xe/xe_migrate.c
+++ b/drivers/gpu/drm/xe/xe_migrate.c
@@ -87,7 +87,7 @@ struct xe_migrate {
 #define MAX_PREEMPTDISABLE_TRANSFER SZ_8M /* Around 1ms. */
 #define MAX_CCS_LIMITED_TRANSFER SZ_4M /* XE_PAGE_SIZE * (FIELD_MAX(XE2_CCS_SIZE_MASK) + 1) */
 #define NUM_KERNEL_PDE 15
-#define NUM_PT_SLOTS 32
+#define NUM_PT_SLOTS 48
 #define LEVEL0_PAGE_TABLE_ENCODE_SIZE SZ_2M
 #define MAX_NUM_PTE 512
 #define IDENTITY_OFFSET 256ULL
@@ -163,22 +163,20 @@ static u64 xe_migrate_vram_ofs(struct xe_device *xe, u64 addr, bool is_comp_pte)
 }
 
 static void xe_migrate_program_identity(struct xe_device *xe, struct xe_vm *vm, struct xe_bo *bo,
-					u64 map_ofs, u64 vram_offset, u16 pat_index, u64 pt_2m_ofs)
+					u64 map_ofs, u64 vram_offset, u16 pat_index, u64 pt_2m_ofs,
+					u64 pt_4k_ofs)
 {
 	struct xe_vram_region *vram = xe->mem.vram;
 	resource_size_t dpa_base = xe_vram_region_dpa_base(vram);
 	u64 pos, ofs, flags;
 	u64 entry;
-	/* XXX: Unclear if this should be usable_size? */
-	u64 vram_limit = xe_vram_region_actual_physical_size(vram) + dpa_base;
+	u64 vram_limit = xe_vram_region_usable_size(vram) + dpa_base;
 	u32 level = 2;
 
 	ofs = map_ofs + XE_PAGE_SIZE * level + vram_offset * 8;
 	flags = vm->pt_ops->pte_encode_addr(xe, 0, pat_index, level,
 					    true, 0);
 
-	xe_assert(xe, IS_ALIGNED(xe_vram_region_usable_size(vram), SZ_2M));
-
 	/*
 	 * Use 1GB pages when possible, last chunk always use 2M
 	 * pages as mixing reserved memory (stolen, WOCPM) with a single
@@ -196,8 +194,24 @@ static void xe_migrate_program_identity(struct xe_device *xe, struct xe_vm *vm,
 							    true, 0);
 
 			for (ofs = pt_2m_ofs; pos < vram_limit;
-			     pos += SZ_2M, ofs += 8)
+			     pos += SZ_2M, ofs += 8) {
+				if (pos + SZ_2M > vram_limit) {
+					entry = vm->pt_ops->pde_encode_bo(bo, pt_4k_ofs);
+					xe_map_wr(xe, &bo->vmap, ofs, u64, entry);
+
+					flags = vm->pt_ops->pte_encode_addr(xe, 0,
+									    pat_index,
+									    level - 2,
+									    true, 0);
+
+					for (ofs = pt_4k_ofs; pos < vram_limit;
+					     pos += SZ_4K, ofs += 8)
+						xe_map_wr(xe, &bo->vmap, ofs, u64, pos | flags);
+					break;
+				}
+
 				xe_map_wr(xe, &bo->vmap, ofs, u64, pos | flags);
+			}
 			break;	/* Ensure pos == vram_limit assert correct */
 		}
 
@@ -242,16 +256,17 @@ static void xe_migrate_prepare_vm(struct xe_tile *tile, struct xe_migrate *m,
 	u16 pat_index = xe_cache_pat_idx(xe, XE_CACHE_WB);
 	u8 id = tile->id;
 	u32 num_entries = NUM_PT_SLOTS, num_level = vm->pt_root[id]->level;
-#define VRAM_IDENTITY_MAP_COUNT	2
-	u32 num_setup = num_level + VRAM_IDENTITY_MAP_COUNT;
-#undef VRAM_IDENTITY_MAP_COUNT
+#define VRAM_IDENTITY_MAP_PT_COUNT	4
+	u32 num_setup = num_level + VRAM_IDENTITY_MAP_PT_COUNT;
+#undef VRAM_IDENTITY_MAP_PT_COUNT
 	u32 map_ofs, level, i;
 	struct xe_bo *bo = m->pt_bo, *batch = tile->mem.kernel_bb_pool->bo;
-	u64 entry, pt29_ofs;
+	u64 entry;
 
-	/* PT30 & PT31 reserved for 2M identity map */
-	pt29_ofs = xe_bo_size(bo) - 3 * XE_PAGE_SIZE;
-	entry = vm->pt_ops->pde_encode_bo(bo, pt29_ofs);
+	/* PT44..PT47 reserved for 4K and 2M identity map */
+	u64 l1_pt_ofs = xe_bo_size(bo) - 5 * XE_PAGE_SIZE;
+
+	entry = vm->pt_ops->pde_encode_bo(bo, l1_pt_ofs);
 	xe_pt_write(xe, &vm->pt_root[id]->bo->vmap, 0, entry);
 
 	map_ofs = (num_entries - num_setup) * XE_PAGE_SIZE;
@@ -347,11 +362,12 @@ static void xe_migrate_prepare_vm(struct xe_tile *tile, struct xe_migrate *m,
 
 	/* Identity map the entire vram at 256GiB offset */
 	if (IS_DGFX(xe)) {
-		u64 pt30_ofs = xe_bo_size(bo) - 2 * XE_PAGE_SIZE;
+		u64 pt46_ofs = xe_bo_size(bo) - 2 * XE_PAGE_SIZE;
 		resource_size_t actual_phy_size = xe_vram_region_actual_physical_size(xe->mem.vram);
 
+		u64 pt44_ofs = xe_bo_size(bo) - 4 * XE_PAGE_SIZE;
 		xe_migrate_program_identity(xe, vm, bo, map_ofs, IDENTITY_OFFSET,
-					    pat_index, pt30_ofs);
+					    pat_index, pt46_ofs, pt44_ofs);
 		xe_assert(xe, actual_phy_size <= (MAX_NUM_PTE - IDENTITY_OFFSET) * SZ_1G);
 
 		/*
@@ -362,12 +378,13 @@ static void xe_migrate_prepare_vm(struct xe_tile *tile, struct xe_migrate *m,
 			u16 comp_pat_index = xe_cache_pat_idx(xe, XE_CACHE_NONE_COMPRESSION);
 			u64 vram_offset = IDENTITY_OFFSET +
 				DIV_ROUND_UP_ULL(actual_phy_size, SZ_1G);
-			u64 pt31_ofs = xe_bo_size(bo) - XE_PAGE_SIZE;
+			u64 pt47_ofs = xe_bo_size(bo) - XE_PAGE_SIZE;
 
 			xe_assert(xe, actual_phy_size <= (MAX_NUM_PTE - IDENTITY_OFFSET -
 							  IDENTITY_OFFSET / 2) * SZ_1G);
+			u64 pt45_ofs = xe_bo_size(bo) - 3 * XE_PAGE_SIZE;
 			xe_migrate_program_identity(xe, vm, bo, map_ofs, vram_offset,
-						    comp_pat_index, pt31_ofs);
+						    comp_pat_index, pt47_ofs, pt45_ofs);
 		}
 	}
 
@@ -381,8 +398,8 @@ static void xe_migrate_suballoc_manager_init(struct xe_migrate *m, u32 map_ofs)
 	 * Example layout created above, with root level = 3:
 	 * [PT0...PT7]: kernel PT's for copy/clear; 64 or 4KiB PTE's
 	 * [PT8]: Kernel PT for VM_BIND, 4 KiB PTE's
-	 * [PT9...PT26]: Userspace PT's for VM_BIND, 4 KiB PTE's
-	 * [PT27 = PDE 0] [PT28 = PDE 1] [PT29 = PDE 2] [PT30 & PT31 = 2M vram identity map]
+	 * [PT9...PT40]: Userspace PT's for VM_BIND, 4 KiB PTE's
+	 * [PT41 = PDE 0] [PT44...PT47 = 4K and 2M vram identity maps]
 	 *
 	 * This makes the lowest part of the VM point to the pagetables.
 	 * Hence the lowest 2M in the vm should point to itself, with a few writes
-- 
2.55.0

[PATCH v2 2/5] drm/xe/vram: report FLAT_CCS base misalignment

[Matthew Auld]

So we can easily check if a machine had the CCS bug, when looking back
over bug reports where we have the same machine with newer kernel.

Example print for a machine with the CCS bug:

  FLAT_CCS base:27bbff800, aligned:no

v2 (Matt B):
  - Unconditionally print the base + alignment

Fixes: 37173392741c ("drm/xe/vram: fix ccs offset calculation")
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: stable@kernel.org
---
 drivers/gpu/drm/xe/xe_vram.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_vram.c b/drivers/gpu/drm/xe/xe_vram.c
index 7b4478fb1697..56cff1e44530 100644
--- a/drivers/gpu/drm/xe/xe_vram.c
+++ b/drivers/gpu/drm/xe/xe_vram.c
@@ -90,6 +90,9 @@ static int get_flat_ccs_offset(struct xe_gt *gt, u64 tile_size, u64 *poffset)
 		offset |= offset_lo << 6; /* HW view bits 31:6 */
 		offset *= num_enabled; /* convert to SW view */
 
+		drm_info(&xe->drm, "FLAT_CCS base:%llx, aligned:%s\n", offset,
+			 str_yes_no(IS_ALIGNED(offset, SZ_128K)));
+
 		/*
 		 * Everything below this offset is handed to the VRAM
 		 * allocator, so it has to be the *first* address the
-- 
2.55.0

[PATCH v2 3/5] drm/xe/vram: revamp CPU VRAM mapping

[Matthew Auld]

Previously, we called devm_ioremap_wc() for the entire PCI LMEM BAR (which
can be significantly larger than usable memory, e.g., mapping 16G for a
10G card), and then simply assigned subsets of this global mapping to each
tile.

By moving the devm_ioremap_wc() call into vram_region_init() and mapping
on a per-tile basis, we restrict the virtual address space to exactly
the usable_size of each tile. The other big win is that the core kernel
will place a guard page at the end of each per-tile mapping to help
catch OOB CPU writes (e.g. into the flat CCS storage) by triggering an
immediate page fault instead of silent memory corruption.

As a consequence the global vram->mapping is now NULL. But that was
unused anyway, with CPU access already correctly routed through the per
tile mapping.

Assisted-by: Gemini:gemini-3.1-pro-preview
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/xe/xe_vram.c | 14 +++++++++-----
 1 file changed, 9 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_vram.c b/drivers/gpu/drm/xe/xe_vram.c
index 56cff1e44530..04d831b101bd 100644
--- a/drivers/gpu/drm/xe/xe_vram.c
+++ b/drivers/gpu/drm/xe/xe_vram.c
@@ -55,9 +55,6 @@ static int determine_lmem_bar_size(struct xe_device *xe, struct xe_vram_region *
 	/* XXX: Need to change when xe link code is ready */
 	lmem_bar->dpa_base = 0;
 
-	/* set up a map to the total memory area. */
-	lmem_bar->mapping = devm_ioremap_wc(&pdev->dev, lmem_bar->io_start, lmem_bar->io_size);
-
 	return 0;
 }
 
@@ -196,7 +193,7 @@ static void vram_fini(void *arg)
 	struct xe_tile *tile;
 	int id;
 
-	xe->mem.vram->mapping = NULL;
+	xe_assert(xe, !xe->mem.vram->mapping);
 
 	for_each_tile(tile, xe, id) {
 		tile->mem.vram->mapping = NULL;
@@ -257,8 +254,15 @@ static int vram_region_init(struct xe_device *xe, struct xe_vram_region *vram,
 		return -ENODEV;
 	}
 
+	if (vram != xe->mem.vram) {
+		struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
+
+		vram->mapping = devm_ioremap_wc(&pdev->dev, vram->io_start, vram->io_size);
+		if (!vram->mapping)
+			return -ENOMEM;
+	}
+
 	vram->dpa_base = lmem_bar->dpa_base + offset;
-	vram->mapping = lmem_bar->mapping + offset;
 	vram->usable_size = usable_size;
 
 	print_vram_region_info(xe, vram);
-- 
2.55.0

Re: [PATCH v2 3/5] drm/xe/vram: revamp CPU VRAM mapping

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The commit intentionally leaves the global VRAM mapping (`xe->mem.vram->mapping`) uninitialized (NULL), but the display panic handler (`xe_panic_page_set_pixel()`) still attempts to use it. This will cause an invalid memory access during a kernel panic, resulting in a nested fault and preventing the panic screen from being drawn.
--

commit c5769f31bf8cec4dae25246aba506ccb4445b29b
Author: Matthew Auld <matthew.auld@intel.com>

    drm/xe/vram: revamp CPU VRAM mapping
    
    Previously, we called devm_ioremap_wc() for the entire PCI LMEM BAR (which
    can be significantly larger than usable memory, e.g., mapping 16G for a
    10G card), and then simply assigned subsets of this global mapping to each
    tile. By moving the devm_ioremap_wc() call into vram_region_init() and
    mapping on a per-tile basis, we restrict the virtual address space to exactly
    the usable_size of each tile. As a consequence the global vram->mapping is
    now NULL.

> diff --git a/drivers/gpu/drm/xe/xe_vram.c b/drivers/gpu/drm/xe/xe_vram.c
> index 56cff1e44530b..04d831b101bd1 100644
> --- a/drivers/gpu/drm/xe/xe_vram.c
> +++ b/drivers/gpu/drm/xe/xe_vram.c
[ ... ]
> @@ -257,8 +254,15 @@ static int vram_region_init(struct xe_device *xe, struct xe_vram_region *vram,
>  		return -ENODEV;
>  	}
>  
> +	if (vram != xe->mem.vram) {
> +		struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
> +
> +		vram->mapping = devm_ioremap_wc(&pdev->dev, vram->io_start, vram->io_size);
> +		if (!vram->mapping)
> +			return -ENOMEM;
> +	}
> +
>  	vram->dpa_base = lmem_bar->dpa_base + offset;
> -	vram->mapping = lmem_bar->mapping + offset;
>  	vram->usable_size = usable_size;

[Severity: High]
Does this change break the drm_panic display handler by leaving the global
xe->mem.vram->mapping as NULL?

Looking at drivers/gpu/drm/xe/display/xe_panic.c, xe_panic_page_set_pixel()
appears to explicitly use the global vram->mapping to compute the IOMEM
address for drawing pixels when the framebuffer is in VRAM:

		if (xe_bo_is_vram(bo)) {
			/* Display is always mapped on root tile */
			struct xe_vram_region *vram = xe_bo_device(bo)->mem.vram;

			if (panic->page < 0 || new_page < panic->page) {
				xe_res_first(bo->ttm.resource, new_page * PAGE_SIZE,
					     bo->ttm.base.size - new_page * PAGE_SIZE, &panic->res);
			} else {
				xe_res_next(&panic->res, PAGE_SIZE * (new_page - panic->page));
			}
			iosys_map_set_vaddr_iomem(&panic->vmap,
						  vram->mapping + panic->res.start);

If vram->mapping is NULL, this could cause an invalid memory access when
dereferenced by iosys_map_wr() during a kernel panic, resulting in a nested
fault and preventing the panic screen from being displayed.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260902103931.826063-7-matthew.auld@intel.com?part=3

Re: [PATCH v2 3/5] drm/xe/vram: revamp CPU VRAM mapping

[Matthew Auld]

On 02/09/2026 11:49, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [High] The commit intentionally leaves the global VRAM mapping (`xe->mem.vram->mapping`) uninitialized (NULL), but the display panic handler (`xe_panic_page_set_pixel()`) still attempts to use it. This will cause an invalid memory access during a kernel panic, resulting in a nested fault and preventing the panic screen from being drawn.
> --
> 
> commit c5769f31bf8cec4dae25246aba506ccb4445b29b
> Author: Matthew Auld <matthew.auld@intel.com>
> 
>      drm/xe/vram: revamp CPU VRAM mapping
>      
>      Previously, we called devm_ioremap_wc() for the entire PCI LMEM BAR (which
>      can be significantly larger than usable memory, e.g., mapping 16G for a
>      10G card), and then simply assigned subsets of this global mapping to each
>      tile. By moving the devm_ioremap_wc() call into vram_region_init() and
>      mapping on a per-tile basis, we restrict the virtual address space to exactly
>      the usable_size of each tile. As a consequence the global vram->mapping is
>      now NULL.
> 
>> diff --git a/drivers/gpu/drm/xe/xe_vram.c b/drivers/gpu/drm/xe/xe_vram.c
>> index 56cff1e44530b..04d831b101bd1 100644
>> --- a/drivers/gpu/drm/xe/xe_vram.c
>> +++ b/drivers/gpu/drm/xe/xe_vram.c
> [ ... ]
>> @@ -257,8 +254,15 @@ static int vram_region_init(struct xe_device *xe, struct xe_vram_region *vram,
>>   		return -ENODEV;
>>   	}
>>   
>> +	if (vram != xe->mem.vram) {
>> +		struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
>> +
>> +		vram->mapping = devm_ioremap_wc(&pdev->dev, vram->io_start, vram->io_size);
>> +		if (!vram->mapping)
>> +			return -ENOMEM;
>> +	}
>> +
>>   	vram->dpa_base = lmem_bar->dpa_base + offset;
>> -	vram->mapping = lmem_bar->mapping + offset;
>>   	vram->usable_size = usable_size;
> 
> [Severity: High]
> Does this change break the drm_panic display handler by leaving the global
> xe->mem.vram->mapping as NULL?
> 
> Looking at drivers/gpu/drm/xe/display/xe_panic.c, xe_panic_page_set_pixel()
> appears to explicitly use the global vram->mapping to compute the IOMEM
> address for drawing pixels when the framebuffer is in VRAM:
> 
> 		if (xe_bo_is_vram(bo)) {
> 			/* Display is always mapped on root tile */
> 			struct xe_vram_region *vram = xe_bo_device(bo)->mem.vram;
> 
> 			if (panic->page < 0 || new_page < panic->page) {
> 				xe_res_first(bo->ttm.resource, new_page * PAGE_SIZE,
> 					     bo->ttm.base.size - new_page * PAGE_SIZE, &panic->res);
> 			} else {
> 				xe_res_next(&panic->res, PAGE_SIZE * (new_page - panic->page));
> 			}
> 			iosys_map_set_vaddr_iomem(&panic->vmap,
> 						  vram->mapping + panic->res.start);
> 
> If vram->mapping is NULL, this could cause an invalid memory access when
> dereferenced by iosys_map_wr() during a kernel panic, resulting in a nested
> fault and preventing the panic screen from being displayed.

Indeed. I think we can just go via the root tile instead.

> 

[PATCH v2 4/5] drm/xe: add force option for global invalidation

[Matthew Auld]

The flush is gated by the WA, since there would no valid use for it
otherwise, but for some very special usecases allow bypassing the WA.

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
---
 drivers/gpu/drm/xe/display/xe_dsb_buffer.c | 2 +-
 drivers/gpu/drm/xe/display/xe_fb_pin.c     | 2 +-
 drivers/gpu/drm/xe/xe_device.c             | 6 +++---
 drivers/gpu/drm/xe/xe_device.h             | 2 +-
 4 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/xe/display/xe_dsb_buffer.c b/drivers/gpu/drm/xe/display/xe_dsb_buffer.c
index a7158c73a14c..82974e933e8d 100644
--- a/drivers/gpu/drm/xe/display/xe_dsb_buffer.c
+++ b/drivers/gpu/drm/xe/display/xe_dsb_buffer.c
@@ -88,7 +88,7 @@ static void xe_dsb_buffer_flush_map(struct intel_dsb_buffer *dsb_buf)
 	 * both for weak ordering archs and discrete cards.
 	 */
 	xe_device_wmb(xe);
-	xe_device_l2_flush(xe);
+	xe_device_l2_flush(xe, false);
 }
 
 const struct intel_display_dsb_interface xe_display_dsb_interface = {
diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c
index 73469ea5f333..b46a2c32ac07 100644
--- a/drivers/gpu/drm/xe/display/xe_fb_pin.c
+++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c
@@ -203,7 +203,7 @@ static int __xe_pin_fb_vma_dpt(struct drm_gem_object *obj,
 	vma->node = dpt->ggtt_node[tile0->id];
 
 	/* Ensure DPT writes are flushed */
-	xe_device_l2_flush(xe);
+	xe_device_l2_flush(xe, false);
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index 396d02eb2af8..fa98b2d12204 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -1270,7 +1270,7 @@ bool xe_device_is_l2_flush_optimized(struct xe_device *xe)
 	return false;
 }
 
-void xe_device_l2_flush(struct xe_device *xe)
+void xe_device_l2_flush(struct xe_device *xe, bool force)
 {
 	struct xe_gt *gt;
 
@@ -1278,7 +1278,7 @@ void xe_device_l2_flush(struct xe_device *xe)
 	if (!gt)
 		return;
 
-	if (!XE_GT_WA(gt, 16023588340))
+	if (!force && !XE_GT_WA(gt, 16023588340))
 		return;
 
 	CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FW_GT);
@@ -1333,7 +1333,7 @@ void xe_device_td_flush(struct xe_device *xe)
 
 	if (XE_GT_WA(root_gt, 16023588340)) {
 		/* A transient flush is not sufficient: flush the L2 */
-		xe_device_l2_flush(xe);
+		xe_device_l2_flush(xe, false);
 	} else {
 		xe_guc_pc_apply_flush_freq_limit(&root_gt->uc.guc.pc);
 		tdf_request_sync(xe);
diff --git a/drivers/gpu/drm/xe/xe_device.h b/drivers/gpu/drm/xe/xe_device.h
index 6c4cfaebc44a..6d3d6d5eba29 100644
--- a/drivers/gpu/drm/xe/xe_device.h
+++ b/drivers/gpu/drm/xe/xe_device.h
@@ -205,7 +205,7 @@ u64 xe_device_uncanonicalize_addr(struct xe_device *xe, u64 address);
 
 bool xe_device_is_l2_flush_optimized(struct xe_device *xe);
 void xe_device_td_flush(struct xe_device *xe);
-void xe_device_l2_flush(struct xe_device *xe);
+void xe_device_l2_flush(struct xe_device *xe, bool force);
 
 static inline bool xe_device_wedged(struct xe_device *xe)
 {
-- 
2.55.0

[PATCH v2 5/5] drm/xe/vram: add early VRAM health check

[Matthew Auld]

During early probe, use the last page as a canary for BAR sizing, CCS
sizing, identity map setup etc. If something is wrong the last page is
where we will likely find it. Hit it with everything we have. For now
this is gated behind a debug config option, so shouldn't trigger on
production.

Main motivation is around CCS sizing where on some BMG cards the CCS
offset is programmed misaligned, for whatever reason, and our handling
of that was busted, as found by Linus, leading to some amount of CCS
storage getting pulled into the allocator as normal VRAM.

Nothing in our CI farm has such a misaligned offset it would seem,
however I did get this to pop on my b570, which does also have the
misaligned CCS offset:

  Tile 0: Running VRAM memtest...
  Tile 0: VRAM bounds overlap CCS region! VRAM sizing is incorrect.

With the fix from Linus, this goes away:

  Tile 0: Running VRAM memtest...
  Tile 0: VRAM memtest completed.

For the VRAM health check itself, this adds:

  - CPU access to the last page (BAR).
  - GPU access to the last page (identity map).
  - CCS overlap check. This one is more involved, but overall idea is
    fill the last page with a known pattern, and also save the CCS state
    for the first 4M of VRAM to some scratch memory. We then zero the CCS
    storage for that same range, all using the proper CCS copy instruction.
    At this point we readback the last page, and check if the pattern we
    wrote changed. Finally we restore the CCS state. This works since CCS
    1:1 maps with VRAM, so the start of the raw CCS, should map to the
    start of VRAM. This successfully catches the issue that Linus found
    and fixed.

Assisted-by: Gemini:gemini-3.1-pro-preview
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Stuart Summers <stuart.summers@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/xe/xe_device.c     |   8 +
 drivers/gpu/drm/xe/xe_migrate.c    |  64 ++++++++
 drivers/gpu/drm/xe/xe_migrate.h    |   6 +
 drivers/gpu/drm/xe/xe_tile_types.h |   4 +
 drivers/gpu/drm/xe/xe_vram.c       | 241 +++++++++++++++++++++++++++++
 drivers/gpu/drm/xe/xe_vram.h       |  10 ++
 6 files changed, 333 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index fa98b2d12204..8583b2e9ecf4 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -1051,6 +1051,10 @@ int xe_device_probe(struct xe_device *xe)
 	if (err)
 		return err;
 
+	err = xe_vram_reserve_memtest_bo(xe);
+	if (err)
+		return err;
+
 	for_each_tile(tile, xe, id) {
 		err = xe_tile_init(tile);
 		if (err)
@@ -1067,6 +1071,10 @@ int xe_device_probe(struct xe_device *xe)
 			return err;
 	}
 
+	err = xe_vram_memtest(xe);
+	if (err)
+		return err;
+
 	err = xe_pagefault_init(xe);
 	if (err)
 		return err;
diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
index 0bf000d7c901..ff45c24d8889 100644
--- a/drivers/gpu/drm/xe/xe_migrate.c
+++ b/drivers/gpu/drm/xe/xe_migrate.c
@@ -2650,3 +2650,67 @@ void xe_migrate_job_lock_assert(struct xe_exec_queue *q)
 #if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)
 #include "tests/xe_migrate.c"
 #endif
+
+#if IS_ENABLED(CONFIG_DRM_XE_DEBUG_MEM)
+int xe_migrate_debug_ccs_overlap(struct xe_migrate *m,
+				 struct xe_bo *scratch_bo,
+				 bool write_to_ccs)
+{
+	struct xe_device *xe = tile_to_xe(m->tile);
+	struct xe_gt *gt = m->tile->primary_gt;
+	struct dma_fence *fence;
+	struct xe_bb *bb;
+	struct xe_sched_job *job;
+	u64 first_page_dpa, clear_L0_ofs, scratch_dpa, scratch_L0_ofs;
+
+	if (!xe_device_has_flat_ccs(xe))
+		return -EINVAL;
+
+	first_page_dpa = xe_vram_region_dpa_base(m->tile->mem.vram);
+	clear_L0_ofs = xe_migrate_vram_ofs(xe, first_page_dpa, true);
+
+	scratch_dpa = xe_bo_addr(scratch_bo, 0, XE_PAGE_SIZE);
+	scratch_L0_ofs = xe_migrate_vram_ofs(xe, scratch_dpa, false);
+
+	bb = xe_bb_new(gt, EMIT_COPY_CCS_DW + 1, xe->info.has_usm);
+	if (IS_ERR(bb)) {
+		drm_warn(&xe->drm, "Failed to create bb for VRAM overlap check\n");
+		return PTR_ERR(bb);
+	}
+
+	/* 4MB payload = 8KB CCS metadata */
+	if (write_to_ccs) {
+		emit_copy_ccs(gt, bb, clear_L0_ofs, true,
+			      scratch_L0_ofs, false, SZ_4M);
+	} else {
+		emit_copy_ccs(gt, bb, scratch_L0_ofs, false,
+			      clear_L0_ofs, true, SZ_4M);
+	}
+
+	bb->cs[bb->len++] = MI_BATCH_BUFFER_END;
+
+	job = xe_bb_create_migration_job(m->q, bb,
+					 xe_migrate_batch_base(m, xe->info.has_usm),
+					 0);
+	if (!IS_ERR(job)) {
+		xe_sched_job_add_migrate_flush(job, MI_FLUSH_DW_CCS);
+
+		mutex_lock(&m->job_mutex);
+		xe_sched_job_arm(job);
+
+		fence = dma_fence_get(&job->drm.s_fence->finished);
+		xe_sched_job_push(job);
+		mutex_unlock(&m->job_mutex);
+
+		dma_fence_wait(fence, false);
+		dma_fence_put(fence);
+	} else {
+		drm_warn(&xe->drm, "Failed to create job for VRAM overlap check\n");
+		xe_bb_free(bb, NULL);
+		return PTR_ERR(job);
+	}
+
+	xe_bb_free(bb, NULL);
+	return 0;
+}
+#endif
diff --git a/drivers/gpu/drm/xe/xe_migrate.h b/drivers/gpu/drm/xe/xe_migrate.h
index c3a268b01768..a9acc62f78f0 100644
--- a/drivers/gpu/drm/xe/xe_migrate.h
+++ b/drivers/gpu/drm/xe/xe_migrate.h
@@ -182,4 +182,10 @@ static inline void xe_migrate_job_lock_assert(struct xe_exec_queue *q)
 void xe_migrate_job_lock(struct xe_migrate *m, struct xe_exec_queue *q);
 void xe_migrate_job_unlock(struct xe_migrate *m, struct xe_exec_queue *q);
 
+#if IS_ENABLED(CONFIG_DRM_XE_DEBUG_MEM)
+int xe_migrate_debug_ccs_overlap(struct xe_migrate *m,
+				 struct xe_bo *scratch_bo,
+				 bool write_to_ccs);
+#endif
+
 #endif
diff --git a/drivers/gpu/drm/xe/xe_tile_types.h b/drivers/gpu/drm/xe/xe_tile_types.h
index 0048100ccb72..e1368c04846a 100644
--- a/drivers/gpu/drm/xe/xe_tile_types.h
+++ b/drivers/gpu/drm/xe/xe_tile_types.h
@@ -97,6 +97,10 @@ struct xe_tile {
 		 * Only main GT has page reclaim list allocations.
 		 */
 		struct xe_sa_manager *reclaim_pool;
+#if IS_ENABLED(CONFIG_DRM_XE_DEBUG_MEM)
+		/** @mem.memtest_bo: VRAM overlap check BO */
+		struct xe_bo *memtest_bo;
+#endif
 	} mem;
 
 	/** @sriov: tile level virtualization data */
diff --git a/drivers/gpu/drm/xe/xe_vram.c b/drivers/gpu/drm/xe/xe_vram.c
index 04d831b101bd..dcedd8cfd731 100644
--- a/drivers/gpu/drm/xe/xe_vram.c
+++ b/drivers/gpu/drm/xe/xe_vram.c
@@ -17,8 +17,11 @@
 #include "xe_device.h"
 #include "xe_force_wake.h"
 #include "xe_gt_mcr.h"
+#include "xe_map.h"
+#include "xe_migrate.h"
 #include "xe_mmio.h"
 #include "xe_sriov.h"
+#include "xe_tile.h"
 #include "xe_tile_sriov_vf.h"
 #include "xe_ttm_vram_mgr.h"
 #include "xe_vram.h"
@@ -407,3 +410,241 @@ resource_size_t xe_vram_region_actual_physical_size(const struct xe_vram_region
 	return vram ? vram->actual_physical_size : 0;
 }
 EXPORT_SYMBOL_IF_KUNIT(xe_vram_region_actual_physical_size);
+
+#if IS_ENABLED(CONFIG_DRM_XE_DEBUG_MEM)
+static void memtest_bo_cleanup(void *arg)
+{
+	struct xe_device *xe = arg;
+
+	xe_vram_free_memtest_bos(xe);
+}
+
+int xe_vram_reserve_memtest_bo(struct xe_device *xe)
+{
+	struct xe_tile *tile;
+	u8 id;
+
+	if (IS_SRIOV_VF(xe))
+		return 0;
+
+	for_each_tile(tile, xe, id) {
+		u64 vram_size;
+
+		if (!tile->mem.vram)
+			continue;
+
+		if (tile->mem.vram->io_size < tile->mem.vram->usable_size) {
+			drm_info(&xe->drm,
+				 "Tile %d: Small-BAR system detected, skipping VRAM memtest\n",
+				 id);
+			continue;
+		}
+
+		vram_size = tile->mem.vram->usable_size;
+
+		tile->mem.memtest_bo = xe_bo_create_pin_map_at_novm(xe, tile, SZ_64K,
+								    vram_size - SZ_64K,
+								    ttm_bo_type_kernel,
+								    XE_BO_FLAG_VRAM_IF_DGFX(tile),
+								    0, false);
+		if (IS_ERR(tile->mem.memtest_bo)) {
+			drm_warn(&xe->drm, "Tile %d: Failed to reserve memtest BO\n", id);
+			tile->mem.memtest_bo = NULL;
+			continue;
+		}
+
+		drm_info(&xe->drm, "Tile %d: Reserved memtest BO at offset 0x%llx\n",
+			 id, vram_size - SZ_64K);
+	}
+
+	return devm_add_action_or_reset(xe->drm.dev, memtest_bo_cleanup, xe);
+}
+
+void xe_vram_free_memtest_bos(struct xe_device *xe)
+{
+	struct xe_tile *tile;
+	u8 id;
+
+	for_each_tile(tile, xe, id) {
+		if (tile->mem.memtest_bo) {
+			xe_bo_unpin_map_no_vm(tile->mem.memtest_bo);
+			tile->mem.memtest_bo = NULL;
+		}
+	}
+}
+
+int xe_vram_memtest(struct xe_device *xe)
+{
+	struct xe_tile *tile;
+	u8 id;
+	int err = 0;
+
+	if (IS_SRIOV_VF(xe))
+		return 0;
+
+	for_each_tile(tile, xe, id) {
+		struct xe_bo *last_page_bo = tile->mem.memtest_bo;
+		struct dma_fence *fence;
+		bool overlap = false;
+		int i;
+		u8 val;
+
+		if (!last_page_bo || !tile->migrate)
+			continue;
+
+		drm_info(&xe->drm, "Tile %d: Running VRAM memtest...\n", id);
+
+		/* CPU write and readback first and last byte of the last page */
+		xe_map_wr(xe, &last_page_bo->vmap, 0, u8, 0xA5);
+		xe_map_wr(xe, &last_page_bo->vmap, SZ_64K - 1, u8, 0x5A);
+
+		val = xe_map_rd(xe, &last_page_bo->vmap, 0, u8);
+		if (drm_WARN(&xe->drm, val != 0xA5,
+			     "Tile %d: CPU memtest failed at offset 0 (expected 0xA5, got 0x%02x)\n",
+			     id, val)) {
+			err = -EIO;
+			goto unpin;
+		}
+
+		val = xe_map_rd(xe, &last_page_bo->vmap, SZ_64K - 1, u8);
+		if (drm_WARN(&xe->drm, val != 0x5A,
+			     "Tile %d: CPU memtest failed at offset 65535 (expected 0x5A, got 0x%02x)\n",
+			     id, val)) {
+			err = -EIO;
+			goto unpin;
+		}
+
+		/* Non-CCS access via GPU on the last page */
+		xe_bo_lock(last_page_bo, false);
+		fence = xe_migrate_clear(tile->migrate, last_page_bo,
+					 last_page_bo->ttm.resource,
+					 XE_MIGRATE_CLEAR_FLAG_BO_DATA);
+		xe_bo_unlock(last_page_bo);
+
+		if (!IS_ERR(fence)) {
+			dma_fence_wait(fence, false);
+			dma_fence_put(fence);
+		} else {
+			err = PTR_ERR(fence);
+			goto unpin;
+		}
+
+		val = xe_map_rd(xe, &last_page_bo->vmap, 0, u8);
+		if (drm_WARN(&xe->drm, val != 0x00,
+			     "Tile %d: GPU memtest clear failed at offset 0 (expected 0x00, got 0x%02x)\n",
+			     id, val)) {
+			err = -EIO;
+			goto unpin;
+		}
+
+		/*
+		 * Check for CCS overlap on the root tile.
+		 *
+		 * TODO: maybe extend if we ever get multi-tile + CCS. Pay
+		 * special attention to the l2 flush below. Currently that is
+		 * hard coded to the root tile.
+		 */
+		if (!id && xe_device_has_flat_ccs(xe) &&
+		    GRAPHICS_VERx100(xe) >= 2000) {
+			struct xe_bo *scratch_bo_before;
+			struct xe_bo *scratch_bo_after;
+
+			scratch_bo_before = xe_bo_create_pin_map_novm(xe, tile, SZ_64K,
+								      ttm_bo_type_kernel,
+								      XE_BO_FLAG_VRAM_IF_DGFX(tile),
+								      false);
+			if (IS_ERR(scratch_bo_before)) {
+				err = PTR_ERR(scratch_bo_before);
+				goto unpin;
+			}
+
+			scratch_bo_after = xe_bo_create_pin_map_novm(xe, tile, SZ_64K,
+								     ttm_bo_type_kernel,
+								     XE_BO_FLAG_VRAM_IF_DGFX(tile),
+								     false);
+			if (IS_ERR(scratch_bo_after)) {
+				xe_bo_unpin_map_no_vm(scratch_bo_before);
+				err = PTR_ERR(scratch_bo_after);
+				goto unpin;
+			}
+
+			/* Save original CCS metadata for PA 0 + */
+			err = xe_migrate_debug_ccs_overlap(tile->migrate, scratch_bo_before, false);
+			if (err) {
+				xe_bo_unpin_map_no_vm(scratch_bo_before);
+				xe_bo_unpin_map_no_vm(scratch_bo_after);
+				goto unpin;
+			}
+
+			/*
+			 * Fill last page. If there is CCS overlap in the last
+			 * page this will snag the raw CCS storage.
+			 */
+			xe_map_memset(xe, &last_page_bo->vmap, 0, 0x5A, SZ_64K);
+			xe_device_wmb(xe);
+
+			/*
+			 * Global invalidation. Some BMG SKUs will cache the BAR
+			 * writes in the GPU side VRAM cache. Make sure above
+			 * writes are fully flushed out to VRAM, so this is
+			 * hopefully more well behaved with the CCS unit, if
+			 * there is indeed CCS overlap with normal VRAM. Since
+			 * there is a separate CCS cache, the CCS unit might not
+			 * respect the GPU VRAM cache for CCS accesses, so opt
+			 * for being super careful here.
+			 */
+			xe_device_l2_flush(xe, true);
+
+			/* Use GPU to clear CCS state for PA 0 */
+			xe_map_memset(xe, &scratch_bo_after->vmap, 0, 0x00, SZ_64K);
+			err = xe_migrate_debug_ccs_overlap(tile->migrate, scratch_bo_after, true);
+			if (err) {
+				xe_bo_unpin_map_no_vm(scratch_bo_before);
+				xe_bo_unpin_map_no_vm(scratch_bo_after);
+				goto unpin;
+			}
+			/*
+			 * Global invalidation. Ensure CCS caches really are
+			 * nuked and the raw CCS data is visible in VRAM, for
+			 * the below access.
+			 */
+			xe_device_l2_flush(xe, true);
+
+			/* Check if last_page_bo was corrupted by the GPU CCS clear */
+			for (i = 0; i < SZ_64K; i += 8) {
+				u64 payload = xe_map_rd(xe, &last_page_bo->vmap, i, u64);
+
+				if (payload != 0x5A5A5A5A5A5A5A5AULL) {
+					overlap = true;
+					break;
+				}
+			}
+
+			/* Restore original CCS metadata for PA 0 + */
+			err = xe_migrate_debug_ccs_overlap(tile->migrate, scratch_bo_before, true);
+			if (err)
+				drm_warn(&xe->drm, "Failed to restore CCS metadata\n");
+
+			xe_bo_unpin_map_no_vm(scratch_bo_before);
+			xe_bo_unpin_map_no_vm(scratch_bo_after);
+		}
+
+		if (drm_WARN(&xe->drm, overlap,
+			     "Tile %d: VRAM bounds overlap CCS region! VRAM sizing is incorrect.\n",
+			     id)) {
+			err = -EINVAL;
+			goto unpin;
+		}
+
+		drm_info(&xe->drm, "Tile %d: VRAM memtest completed.\n", id);
+
+unpin:
+		if (err)
+			break;
+	}
+
+	xe_vram_free_memtest_bos(xe);
+
+	return err;
+}
+#endif
diff --git a/drivers/gpu/drm/xe/xe_vram.h b/drivers/gpu/drm/xe/xe_vram.h
index dd1c8bf17922..38425d81f777 100644
--- a/drivers/gpu/drm/xe/xe_vram.h
+++ b/drivers/gpu/drm/xe/xe_vram.h
@@ -23,4 +23,14 @@ resource_size_t xe_vram_region_dpa_base(const struct xe_vram_region *vram);
 resource_size_t xe_vram_region_usable_size(const struct xe_vram_region *vram);
 resource_size_t xe_vram_region_actual_physical_size(const struct xe_vram_region *vram);
 
+#if IS_ENABLED(CONFIG_DRM_XE_DEBUG_MEM)
+int xe_vram_reserve_memtest_bo(struct xe_device *xe);
+void xe_vram_free_memtest_bos(struct xe_device *xe);
+int xe_vram_memtest(struct xe_device *xe);
+#else
+static inline int xe_vram_reserve_memtest_bo(struct xe_device *xe) { return 0; }
+static inline void xe_vram_free_memtest_bos(struct xe_device *xe) {}
+static inline int xe_vram_memtest(struct xe_device *xe) { return 0; }
+#endif
+
 #endif
-- 
2.55.0

✓ CI.KUnit: success for VRAM health check + CCS fix (rev2)

[Patchwork]

== Series Details ==

Series: VRAM health check + CCS fix (rev2)
URL   : https://patchwork.freedesktop.org/series/172984/
State : success

== Summary ==

+ trap cleanup EXIT
+ kunitconfigs=('/kernel/drivers/gpu/tests/.kunitconfig' '/kernel/drivers/gpu/drm/xe/.kunitconfig' '/kernel/drivers/gpu/drm/tests/.kunitconfig' '/kernel/drivers/gpu/drm/ttm/tests/.kunitconfig' '/kernel/drivers/dma-buf/.kunitconfig')
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/tests/.kunitconfig
[10:45:43] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[10:45:48] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[10:46:08] Starting KUnit Kernel (1/1)...
[10:46:08] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[10:46:08] ============= refcount_interrupt (4 subtests) ==============
[10:46:08] [PASSED] test_single_irq_change
[10:46:08] [PASSED] test_nested_irq_change
[10:46:08] [PASSED] test_multiple_irq_change
[10:46:08] [PASSED] test_irq_save
[10:46:08] =============== [PASSED] refcount_interrupt ================
[10:46:08] ================= gpu_buddy (14 subtests) ==================
[10:46:08] [PASSED] gpu_test_buddy_alloc_limit
[10:46:08] [PASSED] gpu_test_buddy_alloc_optimistic
[10:46:08] [PASSED] gpu_test_buddy_alloc_pessimistic
[10:46:08] [PASSED] gpu_test_buddy_alloc_pathological
[10:46:08] [PASSED] gpu_test_buddy_alloc_contiguous
[10:46:08] [PASSED] gpu_test_buddy_alloc_clear
[10:46:08] [PASSED] gpu_test_buddy_alloc_range
[10:46:09] [PASSED] gpu_test_buddy_alloc_range_bias
[10:46:09] [PASSED] gpu_test_buddy_fragmentation_performance
[10:46:10] [PASSED] gpu_test_buddy_dirty_tracker_performance
[10:46:10] [PASSED] gpu_test_buddy_alloc_exceeds_max_order
[10:46:10] [PASSED] gpu_test_buddy_offset_aligned_allocation
[10:46:10] [PASSED] gpu_test_buddy_subtree_offset_alignment_stress
[10:46:10] [PASSED] gpu_test_buddy_addr_to_block
[10:46:10] ==================== [PASSED] gpu_buddy ====================
[10:46:10] ============================================================
[10:46:10] Testing complete. Ran 18 tests: passed: 18
[10:46:10] Elapsed time: 26.984s total, 4.405s configuring, 20.561s building, 1.971s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/xe/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[10:46:10] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[10:46:12] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[10:46:47] Starting KUnit Kernel (1/1)...
[10:46:47] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[10:46:47] ============= refcount_interrupt (4 subtests) ==============
[10:46:47] [PASSED] test_single_irq_change
[10:46:47] [PASSED] test_nested_irq_change
[10:46:47] [PASSED] test_multiple_irq_change
[10:46:47] [PASSED] test_irq_save
[10:46:47] =============== [PASSED] refcount_interrupt ================
[10:46:47] ================== guc_buf (11 subtests) ===================
[10:46:47] [PASSED] test_smallest
[10:46:47] [PASSED] test_largest
[10:46:47] [PASSED] test_granular
[10:46:47] [PASSED] test_unique
[10:46:47] [PASSED] test_overlap
[10:46:47] [PASSED] test_reusable
[10:46:47] [PASSED] test_too_big
[10:46:47] [PASSED] test_flush
[10:46:47] [PASSED] test_lookup
[10:46:47] [PASSED] test_data
[10:46:47] [PASSED] test_class
[10:46:47] ===================== [PASSED] guc_buf =====================
[10:46:47] =================== guc_dbm (7 subtests) ===================
[10:46:47] [PASSED] test_empty
[10:46:47] [PASSED] test_default
[10:46:47] ======================== test_size  ========================
[10:46:47] [PASSED] 4
[10:46:47] [PASSED] 8
[10:46:47] [PASSED] 32
[10:46:47] [PASSED] 256
[10:46:47] ==================== [PASSED] test_size ====================
[10:46:47] ======================= test_reuse  ========================
[10:46:47] [PASSED] 4
[10:46:47] [PASSED] 8
[10:46:47] [PASSED] 32
[10:46:47] [PASSED] 256
[10:46:47] =================== [PASSED] test_reuse ====================
[10:46:47] =================== test_range_overlap  ====================
[10:46:47] [PASSED] 4
[10:46:47] [PASSED] 8
[10:46:47] [PASSED] 32
[10:46:47] [PASSED] 256
[10:46:47] =============== [PASSED] test_range_overlap ================
[10:46:47] =================== test_range_compact  ====================
[10:46:47] [PASSED] 4
[10:46:47] [PASSED] 8
[10:46:47] [PASSED] 32
[10:46:47] [PASSED] 256
[10:46:47] =============== [PASSED] test_range_compact ================
[10:46:47] ==================== test_range_spare  =====================
[10:46:47] [PASSED] 4
[10:46:47] [PASSED] 8
[10:46:47] [PASSED] 32
[10:46:47] [PASSED] 256
[10:46:47] ================ [PASSED] test_range_spare =================
[10:46:47] ===================== [PASSED] guc_dbm =====================
[10:46:47] =================== guc_idm (6 subtests) ===================
[10:46:47] [PASSED] bad_init
[10:46:47] [PASSED] no_init
[10:46:47] [PASSED] init_fini
[10:46:47] [PASSED] check_used
[10:46:47] [PASSED] check_quota
[10:46:47] [PASSED] check_all
[10:46:47] ===================== [PASSED] guc_idm =====================
[10:46:47] =============== guc_klv_helpers (9 subtests) ===============
[10:46:47] [PASSED] test_count
[10:46:47] [PASSED] test_encode_u32
[10:46:47] [PASSED] test_encode_u64
[10:46:47] [PASSED] test_encode_string
[10:46:47] [PASSED] test_encode_object_raw
[10:46:47] [PASSED] test_encode_object_klv
[10:46:47] [PASSED] test_encode_object_nested
[10:46:47] [PASSED] test_encode_object_basic
[10:46:47] [PASSED] test_print
[10:46:47] ================= [PASSED] guc_klv_helpers =================
[10:46:47] =================== xe_log (4 subtests) ====================
[10:46:47] [PASSED] demo_cper
[10:46:47] [PASSED] demo_dmesg
[10:46:47] ======================= test_dmesg  ========================
[10:46:47] [PASSED] test_fatal
[10:46:47] [PASSED] test_fatal_tile
[10:46:47] [PASSED] test_fatal_gt
[10:46:47] [PASSED] test_fatal_comp
[10:46:47] [PASSED] test_fatal_comp_tile
[10:46:47] [PASSED] test_fatal_comp_gt
[10:46:47] [PASSED] test_fatal_all
[10:46:47] [PASSED] test_recoverable
[10:46:47] [PASSED] test_recoverable_tile
[10:46:47] [PASSED] test_recoverable_gt
[10:46:47] [PASSED] test_recoverable_comp
[10:46:47] [PASSED] test_recoverable_comp_tile
[10:46:47] [PASSED] test_recoverable_comp_gt
[10:46:47] [PASSED] test_recoverable_all
[10:46:47] [PASSED] test_info
[10:46:47] [PASSED] test_info_tile
[10:46:47] [PASSED] test_info_gt
[10:46:47] [PASSED] test_info_err
[10:46:47] [PASSED] test_info_comp
[10:46:47] [PASSED] test_info_comp_tile
[10:46:47] [PASSED] test_info_comp_gt
[10:46:47] [PASSED] test_info_all
[10:46:47] [PASSED] test_hw_fatal
[10:46:47] [PASSED] test_hw_recoverable
[10:46:47] [PASSED] test_hw_corrected
[10:46:47] [PASSED] test_hw_informational
[10:46:47] =================== [PASSED] test_dmesg ====================
[10:46:47] ====================== test_invalid  =======================
[10:46:47] [SKIPPED] no-component no-location no-warn (requires CONFIG_DRM_XE_DEBUG)
[10:46:47] [SKIPPED] reserved location (requires CONFIG_DRM_XE_DEBUG)
[10:46:47] [SKIPPED] unknown location (requires CONFIG_DRM_XE_DEBUG)
[10:46:47] [SKIPPED] nonzero-device-id location (requires CONFIG_DRM_XE_DEBUG)
[10:46:47] [SKIPPED] invalid-tile-id location (requires CONFIG_DRM_XE_DEBUG)
[10:46:47] [SKIPPED] invalid-gt-id location (requires CONFIG_DRM_XE_DEBUG)
[10:46:47] [SKIPPED] unknown component class (requires CONFIG_DRM_XE_DEBUG)
[10:46:47] [SKIPPED] unknown system component (requires CONFIG_DRM_XE_DEBUG)
[10:46:47] [SKIPPED] unknown hardware component (requires CONFIG_DRM_XE_DEBUG)
[10:46:47] [SKIPPED] unknown component and location (requires CONFIG_DRM_XE_DEBUG)
[10:46:47] ================== [SKIPPED] test_invalid ==================
[10:46:47] ===================== [PASSED] xe_log ======================
[10:46:47] ================== no_relay (3 subtests) ===================
[10:46:47] [PASSED] xe_drops_guc2pf_if_not_ready
[10:46:47] [PASSED] xe_drops_guc2vf_if_not_ready
[10:46:47] [PASSED] xe_rejects_send_if_not_ready
[10:46:47] ==================== [PASSED] no_relay =====================
[10:46:47] ================== pf_relay (14 subtests) ==================
[10:46:47] [PASSED] pf_rejects_guc2pf_too_short
[10:46:47] [PASSED] pf_rejects_guc2pf_too_long
[10:46:47] [PASSED] pf_rejects_guc2pf_no_payload
[10:46:47] [PASSED] pf_fails_no_payload
[10:46:47] [PASSED] pf_fails_bad_origin
[10:46:47] [PASSED] pf_fails_bad_type
[10:46:47] [PASSED] pf_txn_reports_error
[10:46:47] [PASSED] pf_txn_sends_pf2guc
[10:46:47] [PASSED] pf_sends_pf2guc
[10:46:47] [SKIPPED] pf_loopback_nop (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[10:46:47] [SKIPPED] pf_loopback_echo (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[10:46:47] [SKIPPED] pf_loopback_fail (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[10:46:47] [SKIPPED] pf_loopback_busy (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[10:46:47] [SKIPPED] pf_loopback_retry (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[10:46:47] ==================== [PASSED] pf_relay =====================
[10:46:47] ================== vf_relay (3 subtests) ===================
[10:46:47] [PASSED] vf_rejects_guc2vf_too_short
[10:46:47] [PASSED] vf_rejects_guc2vf_too_long
[10:46:47] [PASSED] vf_rejects_guc2vf_no_payload
[10:46:47] ==================== [PASSED] vf_relay =====================
[10:46:47] ================ pf_gt_config (9 subtests) =================
[10:46:47] [PASSED] fair_contexts_1vf
[10:46:47] [PASSED] fair_doorbells_1vf
[10:46:47] [PASSED] fair_ggtt_1vf
[10:46:47] ====================== fair_vram_1vf  ======================
[10:46:47] [PASSED] 3.50 GiB
[10:46:47] [PASSED] 11.5 GiB
[10:46:47] [PASSED] 15.5 GiB
[10:46:47] [PASSED] 31.5 GiB
[10:46:47] [PASSED] 63.5 GiB
[10:46:47] [PASSED] 1.91 GiB
[10:46:47] ================== [PASSED] fair_vram_1vf ==================
[10:46:47] ================ fair_vram_1vf_admin_only  =================
[10:46:47] [PASSED] 3.50 GiB
[10:46:47] [PASSED] 11.5 GiB
[10:46:47] [PASSED] 15.5 GiB
[10:46:47] [PASSED] 31.5 GiB
[10:46:47] [PASSED] 63.5 GiB
[10:46:47] [PASSED] 1.91 GiB
[10:46:47] ============ [PASSED] fair_vram_1vf_admin_only =============
[10:46:47] ====================== fair_contexts  ======================
[10:46:47] [PASSED] 1 VF
[10:46:47] [PASSED] 2 VFs
[10:46:47] [PASSED] 3 VFs
[10:46:47] [PASSED] 4 VFs
[10:46:47] [PASSED] 5 VFs
[10:46:47] [PASSED] 6 VFs
[10:46:47] [PASSED] 7 VFs
[10:46:47] [PASSED] 8 VFs
[10:46:47] [PASSED] 9 VFs
[10:46:47] [PASSED] 10 VFs
[10:46:47] [PASSED] 11 VFs
[10:46:47] [PASSED] 12 VFs
[10:46:47] [PASSED] 13 VFs
[10:46:47] [PASSED] 14 VFs
[10:46:47] [PASSED] 15 VFs
[10:46:47] [PASSED] 16 VFs
[10:46:47] [PASSED] 17 VFs
[10:46:47] [PASSED] 18 VFs
[10:46:47] [PASSED] 19 VFs
[10:46:47] [PASSED] 20 VFs
[10:46:47] [PASSED] 21 VFs
[10:46:47] [PASSED] 22 VFs
[10:46:47] [PASSED] 23 VFs
[10:46:47] [PASSED] 24 VFs
[10:46:47] [PASSED] 25 VFs
[10:46:47] [PASSED] 26 VFs
[10:46:47] [PASSED] 27 VFs
[10:46:47] [PASSED] 28 VFs
[10:46:47] [PASSED] 29 VFs
[10:46:47] [PASSED] 30 VFs
[10:46:47] [PASSED] 31 VFs
[10:46:47] [PASSED] 32 VFs
[10:46:47] [PASSED] 33 VFs
[10:46:47] [PASSED] 34 VFs
[10:46:47] [PASSED] 35 VFs
[10:46:47] [PASSED] 36 VFs
[10:46:47] [PASSED] 37 VFs
[10:46:47] [PASSED] 38 VFs
[10:46:47] [PASSED] 39 VFs
[10:46:47] [PASSED] 40 VFs
[10:46:47] [PASSED] 41 VFs
[10:46:47] [PASSED] 42 VFs
[10:46:47] [PASSED] 43 VFs
[10:46:47] [PASSED] 44 VFs
[10:46:47] [PASSED] 45 VFs
[10:46:47] [PASSED] 46 VFs
[10:46:47] [PASSED] 47 VFs
[10:46:47] [PASSED] 48 VFs
[10:46:47] [PASSED] 49 VFs
[10:46:47] [PASSED] 50 VFs
[10:46:47] [PASSED] 51 VFs
[10:46:47] [PASSED] 52 VFs
[10:46:47] [PASSED] 53 VFs
[10:46:47] [PASSED] 54 VFs
[10:46:47] [PASSED] 55 VFs
[10:46:47] [PASSED] 56 VFs
[10:46:47] [PASSED] 57 VFs
[10:46:47] [PASSED] 58 VFs
[10:46:47] [PASSED] 59 VFs
[10:46:47] [PASSED] 60 VFs
[10:46:47] [PASSED] 61 VFs
[10:46:47] [PASSED] 62 VFs
[10:46:47] [PASSED] 63 VFs
[10:46:47] ================== [PASSED] fair_contexts ==================
[10:46:47] ===================== fair_doorbells  ======================
[10:46:47] [PASSED] 1 VF
[10:46:47] [PASSED] 2 VFs
[10:46:47] [PASSED] 3 VFs
[10:46:47] [PASSED] 4 VFs
[10:46:47] [PASSED] 5 VFs
[10:46:47] [PASSED] 6 VFs
[10:46:47] [PASSED] 7 VFs
[10:46:47] [PASSED] 8 VFs
[10:46:47] [PASSED] 9 VFs
[10:46:47] [PASSED] 10 VFs
[10:46:47] [PASSED] 11 VFs
[10:46:47] [PASSED] 12 VFs
[10:46:47] [PASSED] 13 VFs
[10:46:47] [PASSED] 14 VFs
[10:46:47] [PASSED] 15 VFs
[10:46:47] [PASSED] 16 VFs
[10:46:47] [PASSED] 17 VFs
[10:46:47] [PASSED] 18 VFs
[10:46:47] [PASSED] 19 VFs
[10:46:47] [PASSED] 20 VFs
[10:46:47] [PASSED] 21 VFs
[10:46:47] [PASSED] 22 VFs
[10:46:47] [PASSED] 23 VFs
[10:46:47] [PASSED] 24 VFs
[10:46:47] [PASSED] 25 VFs
[10:46:47] [PASSED] 26 VFs
[10:46:47] [PASSED] 27 VFs
[10:46:47] [PASSED] 28 VFs
[10:46:47] [PASSED] 29 VFs
[10:46:47] [PASSED] 30 VFs
[10:46:47] [PASSED] 31 VFs
[10:46:47] [PASSED] 32 VFs
[10:46:47] [PASSED] 33 VFs
[10:46:47] [PASSED] 34 VFs
[10:46:47] [PASSED] 35 VFs
[10:46:47] [PASSED] 36 VFs
[10:46:47] [PASSED] 37 VFs
[10:46:47] [PASSED] 38 VFs
[10:46:47] [PASSED] 39 VFs
[10:46:47] [PASSED] 40 VFs
[10:46:47] [PASSED] 41 VFs
[10:46:47] [PASSED] 42 VFs
[10:46:47] [PASSED] 43 VFs
[10:46:47] [PASSED] 44 VFs
[10:46:47] [PASSED] 45 VFs
[10:46:47] [PASSED] 46 VFs
[10:46:47] [PASSED] 47 VFs
[10:46:47] [PASSED] 48 VFs
[10:46:47] [PASSED] 49 VFs
[10:46:47] [PASSED] 50 VFs
[10:46:47] [PASSED] 51 VFs
[10:46:47] [PASSED] 52 VFs
[10:46:47] [PASSED] 53 VFs
[10:46:47] [PASSED] 54 VFs
[10:46:47] [PASSED] 55 VFs
[10:46:47] [PASSED] 56 VFs
[10:46:47] [PASSED] 57 VFs
[10:46:47] [PASSED] 58 VFs
[10:46:47] [PASSED] 59 VFs
[10:46:47] [PASSED] 60 VFs
[10:46:47] [PASSED] 61 VFs
[10:46:47] [PASSED] 62 VFs
[10:46:47] [PASSED] 63 VFs
[10:46:47] ================= [PASSED] fair_doorbells ==================
[10:46:47] ======================== fair_ggtt  ========================
[10:46:47] [PASSED] 1 VF
[10:46:47] [PASSED] 2 VFs
[10:46:47] [PASSED] 3 VFs
[10:46:47] [PASSED] 4 VFs
[10:46:47] [PASSED] 5 VFs
[10:46:47] [PASSED] 6 VFs
[10:46:47] [PASSED] 7 VFs
[10:46:47] [PASSED] 8 VFs
[10:46:47] [PASSED] 9 VFs
[10:46:47] [PASSED] 10 VFs
[10:46:47] [PASSED] 11 VFs
[10:46:47] [PASSED] 12 VFs
[10:46:47] [PASSED] 13 VFs
[10:46:47] [PASSED] 14 VFs
[10:46:47] [PASSED] 15 VFs
[10:46:47] [PASSED] 16 VFs
[10:46:47] [PASSED] 17 VFs
[10:46:47] [PASSED] 18 VFs
[10:46:47] [PASSED] 19 VFs
[10:46:47] [PASSED] 20 VFs
[10:46:47] [PASSED] 21 VFs
[10:46:47] [PASSED] 22 VFs
[10:46:47] [PASSED] 23 VFs
[10:46:47] [PASSED] 24 VFs
[10:46:47] [PASSED] 25 VFs
[10:46:47] [PASSED] 26 VFs
[10:46:47] [PASSED] 27 VFs
[10:46:47] [PASSED] 28 VFs
[10:46:47] [PASSED] 29 VFs
[10:46:47] [PASSED] 30 VFs
[10:46:47] [PASSED] 31 VFs
[10:46:47] [PASSED] 32 VFs
[10:46:47] [PASSED] 33 VFs
[10:46:47] [PASSED] 34 VFs
[10:46:47] [PASSED] 35 VFs
[10:46:47] [PASSED] 36 VFs
[10:46:47] [PASSED] 37 VFs
[10:46:47] [PASSED] 38 VFs
[10:46:47] [PASSED] 39 VFs
[10:46:47] [PASSED] 40 VFs
[10:46:47] [PASSED] 41 VFs
[10:46:47] [PASSED] 42 VFs
[10:46:47] [PASSED] 43 VFs
[10:46:47] [PASSED] 44 VFs
[10:46:47] [PASSED] 45 VFs
[10:46:47] [PASSED] 46 VFs
[10:46:47] [PASSED] 47 VFs
[10:46:47] [PASSED] 48 VFs
[10:46:47] [PASSED] 49 VFs
[10:46:47] [PASSED] 50 VFs
[10:46:47] [PASSED] 51 VFs
[10:46:47] [PASSED] 52 VFs
[10:46:47] [PASSED] 53 VFs
[10:46:47] [PASSED] 54 VFs
[10:46:47] [PASSED] 55 VFs
[10:46:47] [PASSED] 56 VFs
[10:46:47] [PASSED] 57 VFs
[10:46:47] [PASSED] 58 VFs
[10:46:47] [PASSED] 59 VFs
[10:46:47] [PASSED] 60 VFs
[10:46:47] [PASSED] 61 VFs
[10:46:47] [PASSED] 62 VFs
[10:46:47] [PASSED] 63 VFs
[10:46:47] ==================== [PASSED] fair_ggtt ====================
[10:46:47] ======================== fair_vram  ========================
[10:46:47] [PASSED] 1 VF
[10:46:47] [PASSED] 2 VFs
[10:46:47] [PASSED] 3 VFs
[10:46:47] [PASSED] 4 VFs
[10:46:47] [PASSED] 5 VFs
[10:46:47] [PASSED] 6 VFs
[10:46:47] [PASSED] 7 VFs
[10:46:47] [PASSED] 8 VFs
[10:46:47] [PASSED] 9 VFs
[10:46:47] [PASSED] 10 VFs
[10:46:47] [PASSED] 11 VFs
[10:46:47] [PASSED] 12 VFs
[10:46:47] [PASSED] 13 VFs
[10:46:47] [PASSED] 14 VFs
[10:46:47] [PASSED] 15 VFs
[10:46:47] [PASSED] 16 VFs
[10:46:47] [PASSED] 17 VFs
[10:46:47] [PASSED] 18 VFs
[10:46:47] [PASSED] 19 VFs
[10:46:47] [PASSED] 20 VFs
[10:46:47] [PASSED] 21 VFs
[10:46:47] [PASSED] 22 VFs
[10:46:47] [PASSED] 23 VFs
[10:46:47] [PASSED] 24 VFs
[10:46:47] [PASSED] 25 VFs
[10:46:47] [PASSED] 26 VFs
[10:46:47] [PASSED] 27 VFs
[10:46:47] [PASSED] 28 VFs
[10:46:47] [PASSED] 29 VFs
[10:46:47] [PASSED] 30 VFs
[10:46:47] [PASSED] 31 VFs
[10:46:47] [PASSED] 32 VFs
[10:46:47] [PASSED] 33 VFs
[10:46:47] [PASSED] 34 VFs
[10:46:47] [PASSED] 35 VFs
[10:46:47] [PASSED] 36 VFs
[10:46:47] [PASSED] 37 VFs
[10:46:47] [PASSED] 38 VFs
[10:46:47] [PASSED] 39 VFs
[10:46:47] [PASSED] 40 VFs
[10:46:47] [PASSED] 41 VFs
[10:46:47] [PASSED] 42 VFs
[10:46:47] [PASSED] 43 VFs
[10:46:47] [PASSED] 44 VFs
[10:46:47] [PASSED] 45 VFs
[10:46:47] [PASSED] 46 VFs
[10:46:47] [PASSED] 47 VFs
[10:46:47] [PASSED] 48 VFs
[10:46:47] [PASSED] 49 VFs
[10:46:47] [PASSED] 50 VFs
[10:46:47] [PASSED] 51 VFs
[10:46:47] [PASSED] 52 VFs
[10:46:47] [PASSED] 53 VFs
[10:46:47] [PASSED] 54 VFs
[10:46:47] [PASSED] 55 VFs
[10:46:47] [PASSED] 56 VFs
[10:46:47] [PASSED] 57 VFs
[10:46:47] [PASSED] 58 VFs
[10:46:47] [PASSED] 59 VFs
[10:46:47] [PASSED] 60 VFs
[10:46:47] [PASSED] 61 VFs
[10:46:47] [PASSED] 62 VFs
[10:46:47] [PASSED] 63 VFs
[10:46:47] ==================== [PASSED] fair_vram ====================
[10:46:47] ================== [PASSED] pf_gt_config ===================
[10:46:47] ===================== lmtt (1 subtest) =====================
[10:46:47] ======================== test_ops  =========================
[10:46:47] [PASSED] 2-level
[10:46:47] [PASSED] multi-level
[10:46:47] ==================== [PASSED] test_ops =====================
[10:46:47] ====================== [PASSED] lmtt =======================
[10:46:47] ================= sriov_packet (1 subtest) =================
[10:46:47] [PASSED] test_descriptor_init
[10:46:47] ================== [PASSED] sriov_packet ===================
[10:46:47] ================= pf_service (11 subtests) =================
[10:46:47] [PASSED] pf_negotiate_any
[10:46:47] [PASSED] pf_negotiate_base_match
[10:46:47] [PASSED] pf_negotiate_base_newer
[10:46:47] [PASSED] pf_negotiate_base_next
[10:46:47] [SKIPPED] pf_negotiate_base_older (no older minor)
[10:46:47] [PASSED] pf_negotiate_base_prev
[10:46:47] [PASSED] pf_negotiate_latest_match
[10:46:47] [PASSED] pf_negotiate_latest_newer
[10:46:47] [PASSED] pf_negotiate_latest_next
[10:46:47] [SKIPPED] pf_negotiate_latest_older (no older minor)
[10:46:47] [SKIPPED] pf_negotiate_latest_prev (no prev major)
[10:46:47] =================== [PASSED] pf_service ====================
[10:46:47] ================= xe_guc_g2g (2 subtests) ==================
[10:46:47] ============== xe_live_guc_g2g_kunit_default  ==============
[10:46:47] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[10:46:47] ============== xe_live_guc_g2g_kunit_allmem  ===============
[10:46:47] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[10:46:47] =================== [SKIPPED] xe_guc_g2g ===================
[10:46:47] =================== xe_mocs (2 subtests) ===================
[10:46:47] ================ xe_live_mocs_kernel_kunit  ================
[10:46:47] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[10:46:47] ================ xe_live_mocs_reset_kunit  =================
[10:46:47] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[10:46:47] ==================== [SKIPPED] xe_mocs =====================
[10:46:47] ================= xe_migrate (2 subtests) ==================
[10:46:47] ================= xe_migrate_sanity_kunit  =================
[10:46:47] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[10:46:47] ================== xe_validate_ccs_kunit  ==================
[10:46:47] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[10:46:47] =================== [SKIPPED] xe_migrate ===================
[10:46:47] ================== xe_dma_buf (1 subtest) ==================
[10:46:47] ==================== xe_dma_buf_kunit  =====================
[10:46:47] ================ [SKIPPED] xe_dma_buf_kunit ================
[10:46:47] =================== [SKIPPED] xe_dma_buf ===================
[10:46:47] ================= xe_bo_shrink (1 subtest) =================
[10:46:47] =================== xe_bo_shrink_kunit  ====================
[10:46:47] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[10:46:47] ================== [SKIPPED] xe_bo_shrink ==================
[10:46:47] ==================== xe_bo (2 subtests) ====================
[10:46:47] ================== xe_ccs_migrate_kunit  ===================
[10:46:47] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[10:46:47] ==================== xe_bo_evict_kunit  ====================
[10:46:47] =============== [SKIPPED] xe_bo_evict_kunit ================
[10:46:47] ===================== [SKIPPED] xe_bo ======================
[10:46:47] =================== xe_any (9 subtests) ====================
[10:46:47] [PASSED] test_to_xe
[10:46:47] [PASSED] test_to_dev
[10:46:47] [PASSED] test_to_pdev
[10:46:47] [PASSED] test_to_drm
[10:46:47] [PASSED] test_if_pdev
[10:46:47] [PASSED] test_if_xe
[10:46:47] [PASSED] test_if_tile
[10:46:47] [PASSED] test_if_gt
[10:46:47] [PASSED] test_to_id
[10:46:47] ===================== [PASSED] xe_any ======================
[10:46:47] ==================== args (13 subtests) ====================
[10:46:47] [PASSED] count_args_test
[10:46:47] [PASSED] call_args_example
[10:46:47] [PASSED] call_args_test
[10:46:47] [PASSED] drop_first_arg_example
[10:46:47] [PASSED] drop_first_arg_test
[10:46:47] [PASSED] first_arg_example
[10:46:47] [PASSED] first_arg_test
[10:46:47] [PASSED] last_arg_example
[10:46:47] [PASSED] last_arg_test
[10:46:47] [PASSED] pick_arg_example
[10:46:47] [PASSED] if_args_example
[10:46:47] [PASSED] if_args_test
[10:46:47] [PASSED] sep_comma_example
[10:46:47] ====================== [PASSED] args =======================
[10:46:47] =================== xe_pci (3 subtests) ====================
[10:46:47] ==================== check_graphics_ip  ====================
[10:46:47] [PASSED] 12.00 Xe_LP
[10:46:47] [PASSED] 12.10 Xe_LP+
[10:46:47] [PASSED] 12.55 Xe_HPG
[10:46:47] [PASSED] 12.60 Xe_HPC
[10:46:47] [PASSED] 12.70 Xe_LPG
[10:46:47] [PASSED] 12.71 Xe_LPG
[10:46:47] [PASSED] 12.74 Xe_LPG+
[10:46:47] [PASSED] 20.01 Xe2_HPG
[10:46:47] [PASSED] 20.02 Xe2_HPG
[10:46:47] [PASSED] 20.04 Xe2_LPG
[10:46:47] [PASSED] 30.00 Xe3_LPG
[10:46:47] [PASSED] 30.01 Xe3_LPG
[10:46:47] [PASSED] 30.03 Xe3_LPG
[10:46:47] [PASSED] 30.04 Xe3_LPG
[10:46:47] [PASSED] 30.05 Xe3_LPG
[10:46:47] [PASSED] 35.10 Xe3p_LPG
[10:46:47] [PASSED] 35.11 Xe3p_XPC
[10:46:47] ================ [PASSED] check_graphics_ip ================
[10:46:47] ===================== check_media_ip  ======================
[10:46:47] [PASSED] 12.00 Xe_M
[10:46:47] [PASSED] 12.55 Xe_HPM
[10:46:47] [PASSED] 13.00 Xe_LPM+
[10:46:47] [PASSED] 13.01 Xe2_HPM
[10:46:47] [PASSED] 20.00 Xe2_LPM
[10:46:47] [PASSED] 30.00 Xe3_LPM
[10:46:47] [PASSED] 30.02 Xe3_LPM
[10:46:47] [PASSED] 35.00 Xe3p_LPM
[10:46:47] [PASSED] 35.03 Xe3p_HPM
[10:46:47] ================= [PASSED] check_media_ip ==================
[10:46:47] =================== check_platform_desc  ===================
[10:46:47] [PASSED] 0x9A60 (TIGERLAKE)
[10:46:47] [PASSED] 0x9A68 (TIGERLAKE)
[10:46:47] [PASSED] 0x9A70 (TIGERLAKE)
[10:46:47] [PASSED] 0x9A40 (TIGERLAKE)
[10:46:47] [PASSED] 0x9A49 (TIGERLAKE)
[10:46:47] [PASSED] 0x9A59 (TIGERLAKE)
[10:46:47] [PASSED] 0x9A78 (TIGERLAKE)
[10:46:47] [PASSED] 0x9AC0 (TIGERLAKE)
[10:46:47] [PASSED] 0x9AC9 (TIGERLAKE)
[10:46:47] [PASSED] 0x9AD9 (TIGERLAKE)
[10:46:47] [PASSED] 0x9AF8 (TIGERLAKE)
[10:46:47] [PASSED] 0x4C80 (ROCKETLAKE)
[10:46:47] [PASSED] 0x4C8A (ROCKETLAKE)
[10:46:47] [PASSED] 0x4C8B (ROCKETLAKE)
[10:46:47] [PASSED] 0x4C8C (ROCKETLAKE)
[10:46:47] [PASSED] 0x4C90 (ROCKETLAKE)
[10:46:47] [PASSED] 0x4C9A (ROCKETLAKE)
[10:46:47] [PASSED] 0x4680 (ALDERLAKE_S)
[10:46:47] [PASSED] 0x4682 (ALDERLAKE_S)
[10:46:47] [PASSED] 0x4688 (ALDERLAKE_S)
[10:46:47] [PASSED] 0x468A (ALDERLAKE_S)
[10:46:47] [PASSED] 0x468B (ALDERLAKE_S)
[10:46:47] [PASSED] 0x4690 (ALDERLAKE_S)
[10:46:47] [PASSED] 0x4692 (ALDERLAKE_S)
[10:46:47] [PASSED] 0x4693 (ALDERLAKE_S)
[10:46:47] [PASSED] 0x46A0 (ALDERLAKE_P)
[10:46:47] [PASSED] 0x46A1 (ALDERLAKE_P)
[10:46:47] [PASSED] 0x46A2 (ALDERLAKE_P)
[10:46:47] [PASSED] 0x46A3 (ALDERLAKE_P)
[10:46:47] [PASSED] 0x46A6 (ALDERLAKE_P)
[10:46:47] [PASSED] 0x46A8 (ALDERLAKE_P)
[10:46:47] [PASSED] 0x46AA (ALDERLAKE_P)
[10:46:47] [PASSED] 0x462A (ALDERLAKE_P)
[10:46:47] [PASSED] 0x4626 (ALDERLAKE_P)
[10:46:47] [PASSED] 0x4628 (ALDERLAKE_P)
[10:46:47] [PASSED] 0x46B0 (ALDERLAKE_P)
[10:46:47] [PASSED] 0x46B1 (ALDERLAKE_P)
[10:46:47] [PASSED] 0x46B2 (ALDERLAKE_P)
[10:46:47] [PASSED] 0x46B3 (ALDERLAKE_P)
[10:46:47] [PASSED] 0x46C0 (ALDERLAKE_P)
[10:46:47] [PASSED] 0x46C1 (ALDERLAKE_P)
[10:46:47] [PASSED] 0x46C2 (ALDERLAKE_P)
[10:46:47] [PASSED] 0x46C3 (ALDERLAKE_P)
[10:46:47] [PASSED] 0x46D0 (ALDERLAKE_N)
[10:46:47] [PASSED] 0x46D1 (ALDERLAKE_N)
[10:46:47] [PASSED] 0x46D2 (ALDERLAKE_N)
[10:46:47] [PASSED] 0x46D3 (ALDERLAKE_N)
[10:46:47] [PASSED] 0x46D4 (ALDERLAKE_N)
[10:46:47] [PASSED] 0xA721 (ALDERLAKE_P)
[10:46:47] [PASSED] 0xA7A1 (ALDERLAKE_P)
[10:46:47] [PASSED] 0xA7A9 (ALDERLAKE_P)
[10:46:47] [PASSED] 0xA7AC (ALDERLAKE_P)
[10:46:47] [PASSED] 0xA7AD (ALDERLAKE_P)
[10:46:47] [PASSED] 0xA720 (ALDERLAKE_P)
[10:46:47] [PASSED] 0xA7A0 (ALDERLAKE_P)
[10:46:47] [PASSED] 0xA7A8 (ALDERLAKE_P)
[10:46:47] [PASSED] 0xA7AA (ALDERLAKE_P)
[10:46:47] [PASSED] 0xA7AB (ALDERLAKE_P)
[10:46:47] [PASSED] 0xA780 (ALDERLAKE_S)
[10:46:47] [PASSED] 0xA781 (ALDERLAKE_S)
[10:46:47] [PASSED] 0xA782 (ALDERLAKE_S)
[10:46:47] [PASSED] 0xA783 (ALDERLAKE_S)
[10:46:47] [PASSED] 0xA788 (ALDERLAKE_S)
[10:46:47] [PASSED] 0xA789 (ALDERLAKE_S)
[10:46:47] [PASSED] 0xA78A (ALDERLAKE_S)
[10:46:47] [PASSED] 0xA78B (ALDERLAKE_S)
[10:46:47] [PASSED] 0x4905 (DG1)
[10:46:47] [PASSED] 0x4906 (DG1)
[10:46:47] [PASSED] 0x4907 (DG1)
[10:46:47] [PASSED] 0x4908 (DG1)
[10:46:47] [PASSED] 0x4909 (DG1)
[10:46:47] [PASSED] 0x56C0 (DG2)
[10:46:47] [PASSED] 0x56C2 (DG2)
[10:46:47] [PASSED] 0x56C1 (DG2)
[10:46:47] [PASSED] 0x7D51 (METEORLAKE)
[10:46:47] [PASSED] 0x7DD1 (METEORLAKE)
[10:46:47] [PASSED] 0x7D41 (METEORLAKE)
[10:46:47] [PASSED] 0x7D67 (METEORLAKE)
[10:46:47] [PASSED] 0xB640 (METEORLAKE)
[10:46:47] [PASSED] 0x56A0 (DG2)
[10:46:47] [PASSED] 0x56A1 (DG2)
[10:46:47] [PASSED] 0x56A2 (DG2)
[10:46:47] [PASSED] 0x56BE (DG2)
[10:46:47] [PASSED] 0x56BF (DG2)
[10:46:47] [PASSED] 0x5690 (DG2)
[10:46:47] [PASSED] 0x5691 (DG2)
[10:46:47] [PASSED] 0x5692 (DG2)
[10:46:47] [PASSED] 0x56A5 (DG2)
[10:46:47] [PASSED] 0x56A6 (DG2)
[10:46:47] [PASSED] 0x56B0 (DG2)
[10:46:47] [PASSED] 0x56B1 (DG2)
[10:46:47] [PASSED] 0x56BA (DG2)
[10:46:47] [PASSED] 0x56BB (DG2)
[10:46:47] [PASSED] 0x56BC (DG2)
[10:46:47] [PASSED] 0x56BD (DG2)
[10:46:47] [PASSED] 0x5693 (DG2)
[10:46:47] [PASSED] 0x5694 (DG2)
[10:46:47] [PASSED] 0x5695 (DG2)
[10:46:47] [PASSED] 0x56A3 (DG2)
[10:46:47] [PASSED] 0x56A4 (DG2)
[10:46:47] [PASSED] 0x56B2 (DG2)
[10:46:47] [PASSED] 0x56B3 (DG2)
[10:46:47] [PASSED] 0x5696 (DG2)
[10:46:47] [PASSED] 0x5697 (DG2)
[10:46:47] [PASSED] 0xB69 (PVC)
[10:46:47] [PASSED] 0xB6E (PVC)
[10:46:47] [PASSED] 0xBD4 (PVC)
[10:46:47] [PASSED] 0xBD5 (PVC)
[10:46:47] [PASSED] 0xBD6 (PVC)
[10:46:47] [PASSED] 0xBD7 (PVC)
[10:46:47] [PASSED] 0xBD8 (PVC)
[10:46:47] [PASSED] 0xBD9 (PVC)
[10:46:47] [PASSED] 0xBDA (PVC)
[10:46:47] [PASSED] 0xBDB (PVC)
[10:46:47] [PASSED] 0xBE0 (PVC)
[10:46:47] [PASSED] 0xBE1 (PVC)
[10:46:47] [PASSED] 0xBE5 (PVC)
[10:46:47] [PASSED] 0x7D40 (METEORLAKE)
[10:46:47] [PASSED] 0x7D45 (METEORLAKE)
[10:46:47] [PASSED] 0x7D55 (METEORLAKE)
[10:46:47] [PASSED] 0x7D60 (METEORLAKE)
[10:46:47] [PASSED] 0x7DD5 (METEORLAKE)
[10:46:47] [PASSED] 0x6420 (LUNARLAKE)
[10:46:47] [PASSED] 0x64A0 (LUNARLAKE)
[10:46:47] [PASSED] 0x64B0 (LUNARLAKE)
[10:46:47] [PASSED] 0xE202 (BATTLEMAGE)
[10:46:47] [PASSED] 0xE209 (BATTLEMAGE)
[10:46:47] [PASSED] 0xE20B (BATTLEMAGE)
[10:46:47] [PASSED] 0xE20C (BATTLEMAGE)
[10:46:47] [PASSED] 0xE20D (BATTLEMAGE)
[10:46:47] [PASSED] 0xE210 (BATTLEMAGE)
[10:46:47] [PASSED] 0xE211 (BATTLEMAGE)
[10:46:47] [PASSED] 0xE212 (BATTLEMAGE)
[10:46:47] [PASSED] 0xE216 (BATTLEMAGE)
[10:46:47] [PASSED] 0xE220 (BATTLEMAGE)
[10:46:47] [PASSED] 0xE221 (BATTLEMAGE)
[10:46:47] [PASSED] 0xE222 (BATTLEMAGE)
[10:46:47] [PASSED] 0xE223 (BATTLEMAGE)
[10:46:47] [PASSED] 0xB080 (PANTHERLAKE)
[10:46:47] [PASSED] 0xB081 (PANTHERLAKE)
[10:46:47] [PASSED] 0xB082 (PANTHERLAKE)
[10:46:47] [PASSED] 0xB083 (PANTHERLAKE)
[10:46:47] [PASSED] 0xB084 (PANTHERLAKE)
[10:46:47] [PASSED] 0xB085 (PANTHERLAKE)
[10:46:47] [PASSED] 0xB086 (PANTHERLAKE)
[10:46:47] [PASSED] 0xB087 (PANTHERLAKE)
[10:46:47] [PASSED] 0xB08F (PANTHERLAKE)
[10:46:47] [PASSED] 0xB090 (PANTHERLAKE)
[10:46:47] [PASSED] 0xB0A0 (PANTHERLAKE)
[10:46:47] [PASSED] 0xB0B0 (PANTHERLAKE)
[10:46:47] [PASSED] 0xFD80 (PANTHERLAKE)
[10:46:47] [PASSED] 0xFD81 (PANTHERLAKE)
[10:46:47] [PASSED] 0xD740 (NOVALAKE_S)
[10:46:47] [PASSED] 0xD741 (NOVALAKE_S)
[10:46:47] [PASSED] 0xD742 (NOVALAKE_S)
[10:46:47] [PASSED] 0xD743 (NOVALAKE_S)
[10:46:47] [PASSED] 0xD745 (NOVALAKE_S)
[10:46:47] [PASSED] 0xD74A (NOVALAKE_S)
[10:46:47] [PASSED] 0xD74B (NOVALAKE_S)
[10:46:47] [PASSED] 0x674C (CRESCENTISLAND)
[10:46:47] [PASSED] 0x674D (CRESCENTISLAND)
[10:46:47] [PASSED] 0x674E (CRESCENTISLAND)
[10:46:47] [PASSED] 0x674F (CRESCENTISLAND)
[10:46:47] [PASSED] 0x6750 (CRESCENTISLAND)
[10:46:47] [PASSED] 0xD750 (NOVALAKE_P)
[10:46:47] [PASSED] 0xD751 (NOVALAKE_P)
[10:46:47] [PASSED] 0xD752 (NOVALAKE_P)
[10:46:47] [PASSED] 0xD753 (NOVALAKE_P)
[10:46:47] [PASSED] 0xD754 (NOVALAKE_P)
[10:46:47] [PASSED] 0xD755 (NOVALAKE_P)
[10:46:47] [PASSED] 0xD756 (NOVALAKE_P)
[10:46:47] [PASSED] 0xD757 (NOVALAKE_P)
[10:46:47] [PASSED] 0xD75F (NOVALAKE_P)
[10:46:47] =============== [PASSED] check_platform_desc ===============
[10:46:47] ===================== [PASSED] xe_pci ======================
[10:46:47] ============= xe_rtp_tables_test (5 subtests) ==============
[10:46:47] ================== xe_rtp_table_gt_test  ===================
[10:46:47] [PASSED] gt_was/14011060649
[10:46:47] [PASSED] gt_was/14011059788
[10:46:47] [PASSED] gt_was/14015795083
[10:46:47] [PASSED] gt_was/16021867713
[10:46:47] [PASSED] gt_was/14019449301
[10:46:47] [PASSED] gt_was/16028005424
[10:46:47] [PASSED] gt_was/14026578760
[10:46:47] [PASSED] gt_was/1409420604
[10:46:47] [PASSED] gt_was/1408615072
[10:46:47] [PASSED] gt_was/22010523718
[10:46:47] [PASSED] gt_was/14011006942
[10:46:47] [PASSED] gt_was/14014830051
[10:46:47] [PASSED] gt_was/18018781329
[10:46:47] [PASSED] gt_was/1509235366
[10:46:47] [PASSED] gt_was/18018781329
[10:46:47] [PASSED] gt_was/16016694945
[10:46:47] [PASSED] gt_was/14018575942
[10:46:47] [PASSED] gt_was/22016670082
[10:46:47] [PASSED] gt_was/22016670082
[10:46:47] [PASSED] gt_was/14017421178
[10:46:47] [PASSED] gt_was/16025250150
[10:46:47] [PASSED] gt_was/14021871409
[10:46:47] [PASSED] gt_was/16021865536
[10:46:47] [PASSED] gt_was/14021486841
[10:46:47] [PASSED] gt_was/14025160223
[10:46:47] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[10:46:47] [PASSED] gt_was/14025635424
[10:46:47] [PASSED] gt_was/16028005424
[10:46:47] ============== [PASSED] xe_rtp_table_gt_test ===============
[10:46:47] ================== xe_rtp_table_gt_test  ===================
[10:46:47] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[10:46:47] [PASSED] gt_tunings/Tuning: 32B Access Enable
[10:46:47] [PASSED] gt_tunings/Tuning: L3 cache
[10:46:47] [PASSED] gt_tunings/Tuning: L3 cache - media
[10:46:47] [PASSED] gt_tunings/Tuning: Compression Overfetch
[10:46:47] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[10:46:47] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[10:46:47] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[10:46:47] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[10:46:47] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[10:46:47] [PASSED] gt_tunings/Tuning: Stateless compression control
[10:46:47] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[10:46:47] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[10:46:47] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[10:46:47] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[10:46:47] ============== [PASSED] xe_rtp_table_gt_test ===============
[10:46:47] ================== xe_rtp_table_oob_test  ==================
[10:46:47] [PASSED] oob_was/1607983814
[10:46:47] [PASSED] oob_was/16010904313
[10:46:47] [PASSED] oob_was/18022495364
[10:46:47] [PASSED] oob_was/22012773006
[10:46:47] [PASSED] oob_was/14014475959
[10:46:47] [PASSED] oob_was/22011391025
[10:46:47] [PASSED] oob_was/22012727170
[10:46:47] [PASSED] oob_was/22012727685
[10:46:47] [PASSED] oob_was/22016596838
[10:46:47] [PASSED] oob_was/18020744125
[10:46:47] [PASSED] oob_was/1409600907
[10:46:47] [PASSED] oob_was/22014953428
[10:46:47] [PASSED] oob_was/16017236439
[10:46:47] [PASSED] oob_was/14019821291
[10:46:47] [PASSED] oob_was/14015076503
[10:46:47] [PASSED] oob_was/14018913170
[10:46:47] [PASSED] oob_was/14018094691
[10:46:47] [PASSED] oob_was/18024947630
[10:46:47] [PASSED] oob_was/16022287689
[10:46:47] [PASSED] oob_was/13011645652
[10:46:47] [PASSED] oob_was/14022293748
[10:46:47] [PASSED] oob_was/22019794406
[10:46:47] [PASSED] oob_was/22019338487
[10:46:47] [PASSED] oob_was/16023588340
[10:46:47] [PASSED] oob_was/14019789679
[10:46:47] [PASSED] oob_was/14022866841
[10:46:47] [PASSED] oob_was/16021333562
[10:46:47] [PASSED] oob_was/14016712196
[10:46:47] [PASSED] oob_was/14015568240
[10:46:47] [PASSED] oob_was/18013179988
[10:46:47] [PASSED] oob_was/1508761755
[10:46:47] [PASSED] oob_was/16023105232
[10:46:47] [PASSED] oob_was/16026508708
[10:46:47] [PASSED] oob_was/14020001231
[10:46:47] [PASSED] oob_was/16023683509
[10:46:47] [PASSED] oob_was/14025515070
[10:46:47] [PASSED] oob_was/15015404425_disable
[10:46:47] [PASSED] oob_was/16026007364
[10:46:47] [PASSED] oob_was/14020316580
[10:46:47] [PASSED] oob_was/14025883347
[10:46:47] [PASSED] oob_was/16029380221
[10:46:47] [PASSED] oob_was/22022079272
[10:46:47] [PASSED] oob_was/16029897822
[10:46:47] [PASSED] oob_was/14027054324
[10:46:47] ============== [PASSED] xe_rtp_table_oob_test ==============
[10:46:47] ================ xe_rtp_table_dev_oob_test  ================
[10:46:47] [PASSED] device_oob_was/22010954014
[10:46:47] [PASSED] device_oob_was/15015404425
[10:46:47] [PASSED] device_oob_was/22019338487_display
[10:46:47] [PASSED] device_oob_was/14022085890
[10:46:47] [PASSED] device_oob_was/14026539277
[10:46:47] [PASSED] device_oob_was/14026633728
[10:46:47] [PASSED] device_oob_was/14026746987
[10:46:47] [PASSED] device_oob_was/14026779378
[10:46:47] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[10:46:47] ========== xe_rtp_table_missing_upper_bound_test  ==========
[10:46:47] [PASSED] register_whitelist/WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865
[10:46:47] [PASSED] register_whitelist/1508744258, 14012131227, 1808121037
[10:46:47] [PASSED] register_whitelist/1806527549
[10:46:47] [PASSED] register_whitelist/allow_read_ctx_timestamp
[10:46:47] [PASSED] register_whitelist/allow_read_queue_timestamp
[10:46:47] [PASSED] register_whitelist/16014440446
[10:46:47] [PASSED] register_whitelist/16017236439
[10:46:47] [PASSED] register_whitelist/16020183090
[10:46:47] [PASSED] register_whitelist/14024997852
[10:46:47] [PASSED] register_whitelist/14024997852
[10:46:47] ====== [PASSED] xe_rtp_table_missing_upper_bound_test ======
[10:46:47] =============== [PASSED] xe_rtp_tables_test ================
[10:46:47] =================== xe_rtp (3 subtests) ====================
[10:46:47] =================== xe_rtp_rules_tests  ====================
[10:46:47] [PASSED] no
[10:46:47] [PASSED] yes
[10:46:47] [PASSED] no-and-no
[10:46:47] [PASSED] no-and-yes
[10:46:47] [PASSED] yes-and-no
[10:46:47] [PASSED] yes-and-yes
[10:46:47] [PASSED] no-or-no
[10:46:47] [PASSED] no-or-yes
[10:46:47] [PASSED] yes-or-no
[10:46:47] [PASSED] yes-or-yes
[10:46:47] [PASSED] no-yes-or-yes-no
[10:46:47] [PASSED] no-yes-or-yes-yes
[10:46:47] [PASSED] yes-yes-or-no-yes
[10:46:47] [PASSED] yes-yes-or-yes-yes
[10:46:47] [PASSED] no-no-or-yes-or-no
[10:46:47] [PASSED] or
[10:46:47] [PASSED] or-yes
[10:46:47] [PASSED] or-no
[10:46:47] [PASSED] yes-or
[10:46:47] [PASSED] no-or
[10:46:47] [PASSED] no-or-or-yes
[10:46:47] [PASSED] yes-or-or-no
[10:46:47] [PASSED] no-or-or-no
[10:46:47] [PASSED] missing-context-engine-class
[10:46:47] [PASSED] missing-context-engine-class-or-yes
[10:46:47] [PASSED] missing-context-engine-class-or-or-yes
[10:46:47] =============== [PASSED] xe_rtp_rules_tests ================
[10:46:47] =============== xe_rtp_process_to_sr_tests  ================
[10:46:47] [PASSED] coalesce-same-reg
[10:46:47] [PASSED] coalesce-same-reg-literal-and-func
[10:46:47] [PASSED] no-match-no-add
[10:46:47] [PASSED] two-regs-two-entries
[10:46:47] [PASSED] clr-one-set-other
[10:46:47] [PASSED] set-field
[10:46:47] [PASSED] conflict-duplicate
[10:46:47] [PASSED] conflict-not-disjoint
[10:46:47] [PASSED] conflict-not-disjoint-literal-and-func
[10:46:47] [PASSED] conflict-reg-type
[10:46:47] [PASSED] bad-mcr-reg-forced-to-regular
[10:46:47] [PASSED] bad-regular-reg-forced-to-mcr
[10:46:47] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[10:46:47] ================== xe_rtp_process_tests  ===================
[10:46:47] [PASSED] active1
[10:46:47] [PASSED] active2
[10:46:47] [PASSED] active-inactive
[10:46:47] [PASSED] inactive-active
[10:46:47] [PASSED] inactive-active-inactive
[10:46:47] [PASSED] inactive-inactive-inactive
[10:46:47] ============== [PASSED] xe_rtp_process_tests ===============
[10:46:47] ===================== [PASSED] xe_rtp ======================
[10:46:47] ==================== xe_wa (1 subtest) =====================
[10:46:47] ======================== xe_wa_gt  =========================
[10:46:47] [PASSED] TIGERLAKE B0
[10:46:47] [PASSED] DG1 A0
[10:46:47] [PASSED] DG1 B0
[10:46:47] [PASSED] ALDERLAKE_S A0
[10:46:47] [PASSED] ALDERLAKE_S B0
[10:46:47] [PASSED] ALDERLAKE_S C0
[10:46:47] [PASSED] ALDERLAKE_S D0
[10:46:47] [PASSED] ALDERLAKE_P A0
[10:46:47] [PASSED] ALDERLAKE_P B0
[10:46:47] [PASSED] ALDERLAKE_P C0
[10:46:47] [PASSED] ALDERLAKE_S RPLS D0
[10:46:47] [PASSED] ALDERLAKE_P RPLU E0
[10:46:47] [PASSED] DG2 G10 C0
[10:46:47] [PASSED] DG2 G11 B1
[10:46:47] [PASSED] DG2 G12 A1
[10:46:47] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[10:46:47] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[10:46:47] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[10:46:47] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[10:46:47] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[10:46:47] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[10:46:47] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[10:46:47] ==================== [PASSED] xe_wa_gt =====================
[10:46:47] ====================== [PASSED] xe_wa ======================
[10:46:47] ============================================================
[10:46:47] Testing complete. Ran 793 tests: passed: 765, skipped: 28
[10:46:47] Elapsed time: 36.989s total, 1.835s configuring, 34.438s building, 0.693s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[10:46:47] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[10:46:49] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[10:47:14] Starting KUnit Kernel (1/1)...
[10:47:14] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[10:47:15] ============= refcount_interrupt (4 subtests) ==============
[10:47:15] [PASSED] test_single_irq_change
[10:47:15] [PASSED] test_nested_irq_change
[10:47:15] [PASSED] test_multiple_irq_change
[10:47:15] [PASSED] test_irq_save
[10:47:15] =============== [PASSED] refcount_interrupt ================
[10:47:15] ============ drm_test_pick_cmdline (2 subtests) ============
[10:47:15] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[10:47:15] =============== drm_test_pick_cmdline_named  ===============
[10:47:15] [PASSED] NTSC
[10:47:15] [PASSED] NTSC-J
[10:47:15] [PASSED] PAL
[10:47:15] [PASSED] PAL-M
[10:47:15] =========== [PASSED] drm_test_pick_cmdline_named ===========
[10:47:15] ============== [PASSED] drm_test_pick_cmdline ==============
[10:47:15] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[10:47:15] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[10:47:15] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[10:47:15] =========== drm_validate_clone_mode (2 subtests) ===========
[10:47:15] ============== drm_test_check_in_clone_mode  ===============
[10:47:15] [PASSED] in_clone_mode
[10:47:15] [PASSED] not_in_clone_mode
[10:47:15] ========== [PASSED] drm_test_check_in_clone_mode ===========
[10:47:15] =============== drm_test_check_valid_clones  ===============
[10:47:15] [PASSED] not_in_clone_mode
[10:47:15] [PASSED] valid_clone
[10:47:15] [PASSED] invalid_clone
[10:47:15] =========== [PASSED] drm_test_check_valid_clones ===========
[10:47:15] ============= [PASSED] drm_validate_clone_mode =============
[10:47:15] ============= drm_validate_modeset (1 subtest) =============
[10:47:15] [PASSED] drm_test_check_connector_changed_modeset
[10:47:15] ============== [PASSED] drm_validate_modeset ===============
[10:47:15] ====== drm_test_bridge_get_current_state (1 subtest) =======
[10:47:15] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[10:47:15] ======== [PASSED] drm_test_bridge_get_current_state ========
[10:47:15] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[10:47:15] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[10:47:15] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[10:47:15] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[10:47:15] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[10:47:15] ============== drm_bridge_alloc (2 subtests) ===============
[10:47:15] [PASSED] drm_test_drm_bridge_alloc_basic
[10:47:15] [PASSED] drm_test_drm_bridge_alloc_get_put
[10:47:15] ================ [PASSED] drm_bridge_alloc =================
[10:47:15] ============= drm_bridge_bus_fmt (5 subtests) ==============
[10:47:15] [PASSED] drm_test_bridge_rgb_yuv_rgb
[10:47:15] [PASSED] drm_test_bridge_must_convert_to_yuv444
[10:47:15] [PASSED] drm_test_bridge_hdmi_auto_rgb
[10:47:15] [PASSED] drm_test_bridge_auto_first
[10:47:15] [PASSED] drm_test_bridge_rgb_yuv_no_path
[10:47:15] =============== [PASSED] drm_bridge_bus_fmt ================
[10:47:15] ============= drm_cmdline_parser (40 subtests) =============
[10:47:15] [PASSED] drm_test_cmdline_force_d_only
[10:47:15] [PASSED] drm_test_cmdline_force_D_only_dvi
[10:47:15] [PASSED] drm_test_cmdline_force_D_only_hdmi
[10:47:15] [PASSED] drm_test_cmdline_force_D_only_not_digital
[10:47:15] [PASSED] drm_test_cmdline_force_e_only
[10:47:15] [PASSED] drm_test_cmdline_res
[10:47:15] [PASSED] drm_test_cmdline_res_vesa
[10:47:15] [PASSED] drm_test_cmdline_res_vesa_rblank
[10:47:15] [PASSED] drm_test_cmdline_res_rblank
[10:47:15] [PASSED] drm_test_cmdline_res_bpp
[10:47:15] [PASSED] drm_test_cmdline_res_refresh
[10:47:15] [PASSED] drm_test_cmdline_res_bpp_refresh
[10:47:15] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[10:47:15] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[10:47:15] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[10:47:15] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[10:47:15] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[10:47:15] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[10:47:15] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[10:47:15] [PASSED] drm_test_cmdline_res_margins_force_on
[10:47:15] [PASSED] drm_test_cmdline_res_vesa_margins
[10:47:15] [PASSED] drm_test_cmdline_name
[10:47:15] [PASSED] drm_test_cmdline_name_bpp
[10:47:15] [PASSED] drm_test_cmdline_name_option
[10:47:15] [PASSED] drm_test_cmdline_name_bpp_option
[10:47:15] [PASSED] drm_test_cmdline_rotate_0
[10:47:15] [PASSED] drm_test_cmdline_rotate_90
[10:47:15] [PASSED] drm_test_cmdline_rotate_180
[10:47:15] [PASSED] drm_test_cmdline_rotate_270
[10:47:15] [PASSED] drm_test_cmdline_hmirror
[10:47:15] [PASSED] drm_test_cmdline_vmirror
[10:47:15] [PASSED] drm_test_cmdline_margin_options
[10:47:15] [PASSED] drm_test_cmdline_multiple_options
[10:47:15] [PASSED] drm_test_cmdline_bpp_extra_and_option
[10:47:15] [PASSED] drm_test_cmdline_extra_and_option
[10:47:15] [PASSED] drm_test_cmdline_freestanding_options
[10:47:15] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[10:47:15] [PASSED] drm_test_cmdline_panel_orientation
[10:47:15] ================ drm_test_cmdline_invalid  =================
[10:47:15] [PASSED] margin_only
[10:47:15] [PASSED] interlace_only
[10:47:15] [PASSED] res_missing_x
[10:47:15] [PASSED] res_missing_y
[10:47:15] [PASSED] res_bad_y
[10:47:15] [PASSED] res_missing_y_bpp
[10:47:15] [PASSED] res_bad_bpp
[10:47:15] [PASSED] res_bad_refresh
[10:47:15] [PASSED] res_bpp_refresh_force_on_off
[10:47:15] [PASSED] res_invalid_mode
[10:47:15] [PASSED] res_bpp_wrong_place_mode
[10:47:15] [PASSED] name_bpp_refresh
[10:47:15] [PASSED] name_refresh
[10:47:15] [PASSED] name_refresh_wrong_mode
[10:47:15] [PASSED] name_refresh_invalid_mode
[10:47:15] [PASSED] rotate_multiple
[10:47:15] [PASSED] rotate_invalid_val
[10:47:15] [PASSED] rotate_truncated
[10:47:15] [PASSED] invalid_option
[10:47:15] [PASSED] invalid_tv_option
[10:47:15] [PASSED] truncated_tv_option
[10:47:15] ============ [PASSED] drm_test_cmdline_invalid =============
[10:47:15] =============== drm_test_cmdline_tv_options  ===============
[10:47:15] [PASSED] NTSC
[10:47:15] [PASSED] NTSC_443
[10:47:15] [PASSED] NTSC_J
[10:47:15] [PASSED] PAL
[10:47:15] [PASSED] PAL_M
[10:47:15] [PASSED] PAL_N
[10:47:15] [PASSED] SECAM
[10:47:15] [PASSED] MONO_525
[10:47:15] [PASSED] MONO_625
[10:47:15] =========== [PASSED] drm_test_cmdline_tv_options ===========
[10:47:15] =============== [PASSED] drm_cmdline_parser ================
[10:47:15] ========== drmm_connector_hdmi_init (20 subtests) ==========
[10:47:15] [PASSED] drm_test_connector_hdmi_init_valid
[10:47:15] [PASSED] drm_test_connector_hdmi_init_bpc_8
[10:47:15] [PASSED] drm_test_connector_hdmi_init_bpc_10
[10:47:15] [PASSED] drm_test_connector_hdmi_init_bpc_12
[10:47:15] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[10:47:15] [PASSED] drm_test_connector_hdmi_init_bpc_null
[10:47:15] [PASSED] drm_test_connector_hdmi_init_formats_empty
[10:47:15] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[10:47:15] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[10:47:15] [PASSED] supported_formats=0x9 yuv420_allowed=1
[10:47:15] [PASSED] supported_formats=0x9 yuv420_allowed=0
[10:47:15] [PASSED] supported_formats=0x5 yuv420_allowed=1
[10:47:15] [PASSED] supported_formats=0x5 yuv420_allowed=0
[10:47:15] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[10:47:15] [PASSED] drm_test_connector_hdmi_init_null_ddc
[10:47:15] [PASSED] drm_test_connector_hdmi_init_null_product
[10:47:15] [PASSED] drm_test_connector_hdmi_init_null_vendor
[10:47:15] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[10:47:15] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[10:47:15] [PASSED] drm_test_connector_hdmi_init_product_valid
[10:47:15] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[10:47:15] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[10:47:15] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[10:47:15] ========= drm_test_connector_hdmi_init_type_valid  =========
[10:47:15] [PASSED] HDMI-A
[10:47:15] [PASSED] HDMI-B
[10:47:15] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[10:47:15] ======== drm_test_connector_hdmi_init_type_invalid  ========
[10:47:15] [PASSED] Unknown
[10:47:15] [PASSED] VGA
[10:47:15] [PASSED] DVI-I
[10:47:15] [PASSED] DVI-D
[10:47:15] [PASSED] DVI-A
[10:47:15] [PASSED] Composite
[10:47:15] [PASSED] SVIDEO
[10:47:15] [PASSED] LVDS
[10:47:15] [PASSED] Component
[10:47:15] [PASSED] DIN
[10:47:15] [PASSED] DP
[10:47:15] [PASSED] TV
[10:47:15] [PASSED] eDP
[10:47:15] [PASSED] Virtual
[10:47:15] [PASSED] DSI
[10:47:15] [PASSED] DPI
[10:47:15] [PASSED] Writeback
[10:47:15] [PASSED] SPI
[10:47:15] [PASSED] USB
[10:47:15] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[10:47:15] ============ [PASSED] drmm_connector_hdmi_init =============
[10:47:15] ============= drmm_connector_init (3 subtests) =============
[10:47:15] [PASSED] drm_test_drmm_connector_init
[10:47:15] [PASSED] drm_test_drmm_connector_init_null_ddc
[10:47:15] ========= drm_test_drmm_connector_init_type_valid  =========
[10:47:15] [PASSED] Unknown
[10:47:15] [PASSED] VGA
[10:47:15] [PASSED] DVI-I
[10:47:15] [PASSED] DVI-D
[10:47:15] [PASSED] DVI-A
[10:47:15] [PASSED] Composite
[10:47:15] [PASSED] SVIDEO
[10:47:15] [PASSED] LVDS
[10:47:15] [PASSED] Component
[10:47:15] [PASSED] DIN
[10:47:15] [PASSED] DP
[10:47:15] [PASSED] HDMI-A
[10:47:15] [PASSED] HDMI-B
[10:47:15] [PASSED] TV
[10:47:15] [PASSED] eDP
[10:47:15] [PASSED] Virtual
[10:47:15] [PASSED] DSI
[10:47:15] [PASSED] DPI
[10:47:15] [PASSED] Writeback
[10:47:15] [PASSED] SPI
[10:47:15] [PASSED] USB
[10:47:15] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[10:47:15] =============== [PASSED] drmm_connector_init ===============
[10:47:15] ========= drm_connector_dynamic_init (6 subtests) ==========
[10:47:15] [PASSED] drm_test_drm_connector_dynamic_init
[10:47:15] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[10:47:15] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[10:47:15] [PASSED] drm_test_drm_connector_dynamic_init_properties
[10:47:15] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[10:47:15] [PASSED] Unknown
[10:47:15] [PASSED] VGA
[10:47:15] [PASSED] DVI-I
[10:47:15] [PASSED] DVI-D
[10:47:15] [PASSED] DVI-A
[10:47:15] [PASSED] Composite
[10:47:15] [PASSED] SVIDEO
[10:47:15] [PASSED] LVDS
[10:47:15] [PASSED] Component
[10:47:15] [PASSED] DIN
[10:47:15] [PASSED] DP
[10:47:15] [PASSED] HDMI-A
[10:47:15] [PASSED] HDMI-B
[10:47:15] [PASSED] TV
[10:47:15] [PASSED] eDP
[10:47:15] [PASSED] Virtual
[10:47:15] [PASSED] DSI
[10:47:15] [PASSED] DPI
[10:47:15] [PASSED] Writeback
[10:47:15] [PASSED] SPI
[10:47:15] [PASSED] USB
[10:47:15] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[10:47:15] ======== drm_test_drm_connector_dynamic_init_name  =========
[10:47:15] [PASSED] Unknown
[10:47:15] [PASSED] VGA
[10:47:15] [PASSED] DVI-I
[10:47:15] [PASSED] DVI-D
[10:47:15] [PASSED] DVI-A
[10:47:15] [PASSED] Composite
[10:47:15] [PASSED] SVIDEO
[10:47:15] [PASSED] LVDS
[10:47:15] [PASSED] Component
[10:47:15] [PASSED] DIN
[10:47:15] [PASSED] DP
[10:47:15] [PASSED] HDMI-A
[10:47:15] [PASSED] HDMI-B
[10:47:15] [PASSED] TV
[10:47:15] [PASSED] eDP
[10:47:15] [PASSED] Virtual
[10:47:15] [PASSED] DSI
[10:47:15] [PASSED] DPI
[10:47:15] [PASSED] Writeback
[10:47:15] [PASSED] SPI
[10:47:15] [PASSED] USB
[10:47:15] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[10:47:15] =========== [PASSED] drm_connector_dynamic_init ============
[10:47:15] ==== drm_connector_dynamic_register_early (4 subtests) =====
[10:47:15] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[10:47:15] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[10:47:15] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[10:47:15] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[10:47:15] ====== [PASSED] drm_connector_dynamic_register_early =======
[10:47:15] ======= drm_connector_dynamic_register (7 subtests) ========
[10:47:15] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[10:47:15] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[10:47:15] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[10:47:15] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[10:47:15] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[10:47:15] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[10:47:15] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[10:47:15] ========= [PASSED] drm_connector_dynamic_register ==========
[10:47:15] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[10:47:15] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[10:47:15] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[10:47:15] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[10:47:15] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[10:47:15] ========== drm_test_get_tv_mode_from_name_valid  ===========
[10:47:15] [PASSED] NTSC
[10:47:15] [PASSED] NTSC-443
[10:47:15] [PASSED] NTSC-J
[10:47:15] [PASSED] PAL
[10:47:15] [PASSED] PAL-M
[10:47:15] [PASSED] PAL-N
[10:47:15] [PASSED] SECAM
[10:47:15] [PASSED] Mono
[10:47:15] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[10:47:15] [PASSED] drm_test_get_tv_mode_from_name_truncated
[10:47:15] ============ [PASSED] drm_get_tv_mode_from_name ============
[10:47:15] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[10:47:15] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[10:47:15] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[10:47:15] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[10:47:15] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[10:47:15] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[10:47:15] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[10:47:15] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[10:47:15] [PASSED] VIC 96
[10:47:15] [PASSED] VIC 97
[10:47:15] [PASSED] VIC 101
[10:47:15] [PASSED] VIC 102
[10:47:15] [PASSED] VIC 106
[10:47:15] [PASSED] VIC 107
[10:47:15] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[10:47:15] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[10:47:15] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[10:47:15] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[10:47:15] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[10:47:15] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[10:47:15] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[10:47:15] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[10:47:15] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[10:47:15] [PASSED] Automatic
[10:47:15] [PASSED] Full
[10:47:15] [PASSED] Limited 16:235
[10:47:15] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[10:47:15] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[10:47:15] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[10:47:15] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[10:47:15] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[10:47:15] [PASSED] RGB
[10:47:15] [PASSED] YUV 4:2:0
[10:47:15] [PASSED] YUV 4:2:2
[10:47:15] [PASSED] YUV 4:4:4
[10:47:15] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[10:47:15] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[10:47:15] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[10:47:15] ============= drm_damage_helper (21 subtests) ==============
[10:47:15] [PASSED] drm_test_damage_iter_no_damage
[10:47:15] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[10:47:15] [PASSED] drm_test_damage_iter_no_damage_src_moved
[10:47:15] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[10:47:15] [PASSED] drm_test_damage_iter_no_damage_not_visible
[10:47:15] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[10:47:15] [PASSED] drm_test_damage_iter_no_damage_no_fb
[10:47:15] [PASSED] drm_test_damage_iter_simple_damage
[10:47:15] [PASSED] drm_test_damage_iter_single_damage
[10:47:15] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[10:47:15] [PASSED] drm_test_damage_iter_single_damage_outside_src
[10:47:15] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[10:47:15] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[10:47:15] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[10:47:15] [PASSED] drm_test_damage_iter_single_damage_src_moved
[10:47:15] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[10:47:15] [PASSED] drm_test_damage_iter_damage
[10:47:15] [PASSED] drm_test_damage_iter_damage_one_intersect
[10:47:15] [PASSED] drm_test_damage_iter_damage_one_outside
[10:47:15] [PASSED] drm_test_damage_iter_damage_src_moved
[10:47:15] [PASSED] drm_test_damage_iter_damage_not_visible
[10:47:15] ================ [PASSED] drm_damage_helper ================
[10:47:15] ============== drm_dp_mst_helper (3 subtests) ==============
[10:47:15] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[10:47:15] [PASSED] Clock 154000 BPP 30 DSC disabled
[10:47:15] [PASSED] Clock 234000 BPP 30 DSC disabled
[10:47:15] [PASSED] Clock 297000 BPP 24 DSC disabled
[10:47:15] [PASSED] Clock 332880 BPP 24 DSC enabled
[10:47:15] [PASSED] Clock 324540 BPP 24 DSC enabled
[10:47:15] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[10:47:15] ============== drm_test_dp_mst_calc_pbn_div  ===============
[10:47:15] [PASSED] Link rate 2000000 lane count 4
[10:47:15] [PASSED] Link rate 2000000 lane count 2
[10:47:15] [PASSED] Link rate 2000000 lane count 1
[10:47:15] [PASSED] Link rate 1350000 lane count 4
[10:47:15] [PASSED] Link rate 1350000 lane count 2
[10:47:15] [PASSED] Link rate 1350000 lane count 1
[10:47:15] [PASSED] Link rate 1000000 lane count 4
[10:47:15] [PASSED] Link rate 1000000 lane count 2
[10:47:15] [PASSED] Link rate 1000000 lane count 1
[10:47:15] [PASSED] Link rate 810000 lane count 4
[10:47:15] [PASSED] Link rate 810000 lane count 2
[10:47:15] [PASSED] Link rate 810000 lane count 1
[10:47:15] [PASSED] Link rate 540000 lane count 4
[10:47:15] [PASSED] Link rate 540000 lane count 2
[10:47:15] [PASSED] Link rate 540000 lane count 1
[10:47:15] [PASSED] Link rate 270000 lane count 4
[10:47:15] [PASSED] Link rate 270000 lane count 2
[10:47:15] [PASSED] Link rate 270000 lane count 1
[10:47:15] [PASSED] Link rate 162000 lane count 4
[10:47:15] [PASSED] Link rate 162000 lane count 2
[10:47:15] [PASSED] Link rate 162000 lane count 1
[10:47:15] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[10:47:15] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[10:47:15] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[10:47:15] [PASSED] DP_POWER_UP_PHY with port number
[10:47:15] [PASSED] DP_POWER_DOWN_PHY with port number
[10:47:15] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[10:47:15] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[10:47:15] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[10:47:15] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[10:47:15] [PASSED] DP_QUERY_PAYLOAD with port number
[10:47:15] [PASSED] DP_QUERY_PAYLOAD with VCPI
[10:47:15] [PASSED] DP_REMOTE_DPCD_READ with port number
[10:47:15] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[10:47:15] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[10:47:15] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[10:47:15] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[10:47:15] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[10:47:15] [PASSED] DP_REMOTE_I2C_READ with port number
[10:47:15] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[10:47:15] [PASSED] DP_REMOTE_I2C_READ with transactions array
[10:47:15] [PASSED] DP_REMOTE_I2C_WRITE with port number
[10:47:15] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[10:47:15] [PASSED] DP_REMOTE_I2C_WRITE with data array
[10:47:15] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[10:47:15] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[10:47:15] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[10:47:15] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[10:47:15] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[10:47:15] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[10:47:15] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[10:47:15] ================ [PASSED] drm_dp_mst_helper ================
[10:47:15] ================== drm_exec (7 subtests) ===================
[10:47:15] [PASSED] sanitycheck
[10:47:15] [PASSED] test_lock
[10:47:15] [PASSED] test_lock_unlock
[10:47:15] [PASSED] test_duplicates
[10:47:15] [PASSED] test_prepare
[10:47:15] [PASSED] test_prepare_array
[10:47:15] [PASSED] test_multiple_loops
[10:47:15] ==================== [PASSED] drm_exec =====================
[10:47:15] =========== drm_format_helper_test (17 subtests) ===========
[10:47:15] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[10:47:15] [PASSED] single_pixel_source_buffer
[10:47:15] [PASSED] single_pixel_clip_rectangle
[10:47:15] [PASSED] well_known_colors
[10:47:15] [PASSED] destination_pitch
[10:47:15] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[10:47:15] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[10:47:15] [PASSED] single_pixel_source_buffer
[10:47:15] [PASSED] single_pixel_clip_rectangle
[10:47:15] [PASSED] well_known_colors
[10:47:15] [PASSED] destination_pitch
[10:47:15] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[10:47:15] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[10:47:15] [PASSED] single_pixel_source_buffer
[10:47:15] [PASSED] single_pixel_clip_rectangle
[10:47:15] [PASSED] well_known_colors
[10:47:15] [PASSED] destination_pitch
[10:47:15] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[10:47:15] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[10:47:15] [PASSED] single_pixel_source_buffer
[10:47:15] [PASSED] single_pixel_clip_rectangle
[10:47:15] [PASSED] well_known_colors
[10:47:15] [PASSED] destination_pitch
[10:47:15] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[10:47:15] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[10:47:15] [PASSED] single_pixel_source_buffer
[10:47:15] [PASSED] single_pixel_clip_rectangle
[10:47:15] [PASSED] well_known_colors
[10:47:15] [PASSED] destination_pitch
[10:47:15] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[10:47:15] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[10:47:15] [PASSED] single_pixel_source_buffer
[10:47:15] [PASSED] single_pixel_clip_rectangle
[10:47:15] [PASSED] well_known_colors
[10:47:15] [PASSED] destination_pitch
[10:47:15] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[10:47:15] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[10:47:15] [PASSED] single_pixel_source_buffer
[10:47:15] [PASSED] single_pixel_clip_rectangle
[10:47:15] [PASSED] well_known_colors
[10:47:15] [PASSED] destination_pitch
[10:47:15] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[10:47:15] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[10:47:15] [PASSED] single_pixel_source_buffer
[10:47:15] [PASSED] single_pixel_clip_rectangle
[10:47:15] [PASSED] well_known_colors
[10:47:15] [PASSED] destination_pitch
[10:47:15] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[10:47:15] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[10:47:15] [PASSED] single_pixel_source_buffer
[10:47:15] [PASSED] single_pixel_clip_rectangle
[10:47:15] [PASSED] well_known_colors
[10:47:15] [PASSED] destination_pitch
[10:47:15] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[10:47:15] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[10:47:15] [PASSED] single_pixel_source_buffer
[10:47:15] [PASSED] single_pixel_clip_rectangle
[10:47:15] [PASSED] well_known_colors
[10:47:15] [PASSED] destination_pitch
[10:47:15] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[10:47:15] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[10:47:15] [PASSED] single_pixel_source_buffer
[10:47:15] [PASSED] single_pixel_clip_rectangle
[10:47:15] [PASSED] well_known_colors
[10:47:15] [PASSED] destination_pitch
[10:47:15] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[10:47:15] ============== drm_test_fb_xrgb8888_to_mono  ===============
[10:47:15] [PASSED] single_pixel_source_buffer
[10:47:15] [PASSED] single_pixel_clip_rectangle
[10:47:15] [PASSED] well_known_colors
[10:47:15] [PASSED] destination_pitch
[10:47:15] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[10:47:15] ==================== drm_test_fb_swab  =====================
[10:47:15] [PASSED] single_pixel_source_buffer
[10:47:15] [PASSED] single_pixel_clip_rectangle
[10:47:15] [PASSED] well_known_colors
[10:47:15] [PASSED] destination_pitch
[10:47:15] ================ [PASSED] drm_test_fb_swab =================
[10:47:15] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[10:47:15] [PASSED] single_pixel_source_buffer
[10:47:15] [PASSED] single_pixel_clip_rectangle
[10:47:15] [PASSED] well_known_colors
[10:47:15] [PASSED] destination_pitch
[10:47:15] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[10:47:15] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[10:47:15] [PASSED] single_pixel_source_buffer
[10:47:15] [PASSED] single_pixel_clip_rectangle
[10:47:15] [PASSED] well_known_colors
[10:47:15] [PASSED] destination_pitch
[10:47:15] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[10:47:15] ================= drm_test_fb_clip_offset  =================
[10:47:15] [PASSED] pass through
[10:47:15] [PASSED] horizontal offset
[10:47:15] [PASSED] vertical offset
[10:47:15] [PASSED] horizontal and vertical offset
[10:47:15] [PASSED] horizontal offset (custom pitch)
[10:47:15] [PASSED] vertical offset (custom pitch)
[10:47:15] [PASSED] horizontal and vertical offset (custom pitch)
[10:47:15] ============= [PASSED] drm_test_fb_clip_offset =============
[10:47:15] =================== drm_test_fb_memcpy  ====================
[10:47:15] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[10:47:15] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[10:47:15] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[10:47:15] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[10:47:15] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[10:47:15] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[10:47:15] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[10:47:15] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[10:47:15] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[10:47:15] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[10:47:15] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[10:47:15] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[10:47:15] =============== [PASSED] drm_test_fb_memcpy ================
[10:47:15] ============= [PASSED] drm_format_helper_test ==============
[10:47:15] ================= drm_format (18 subtests) =================
[10:47:15] [PASSED] drm_test_format_block_width_invalid
[10:47:15] [PASSED] drm_test_format_block_width_one_plane
[10:47:15] [PASSED] drm_test_format_block_width_two_plane
[10:47:15] [PASSED] drm_test_format_block_width_three_plane
[10:47:15] [PASSED] drm_test_format_block_width_tiled
[10:47:15] [PASSED] drm_test_format_block_height_invalid
[10:47:15] [PASSED] drm_test_format_block_height_one_plane
[10:47:15] [PASSED] drm_test_format_block_height_two_plane
[10:47:15] [PASSED] drm_test_format_block_height_three_plane
[10:47:15] [PASSED] drm_test_format_block_height_tiled
[10:47:15] [PASSED] drm_test_format_min_pitch_invalid
[10:47:15] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[10:47:15] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[10:47:15] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[10:47:15] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[10:47:15] [PASSED] drm_test_format_min_pitch_two_plane
[10:47:15] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[10:47:15] [PASSED] drm_test_format_min_pitch_tiled
[10:47:15] =================== [PASSED] drm_format ====================
[10:47:15] ============== drm_framebuffer (10 subtests) ===============
[10:47:15] ========== drm_test_framebuffer_check_src_coords  ==========
[10:47:15] [PASSED] Success: source fits into fb
[10:47:15] [PASSED] Fail: overflowing fb with x-axis coordinate
[10:47:15] [PASSED] Fail: overflowing fb with y-axis coordinate
[10:47:15] [PASSED] Fail: overflowing fb with source width
[10:47:15] [PASSED] Fail: overflowing fb with source height
[10:47:15] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[10:47:15] [PASSED] drm_test_framebuffer_cleanup
[10:47:15] =============== drm_test_framebuffer_create  ===============
[10:47:15] [PASSED] ABGR8888 normal sizes
[10:47:15] [PASSED] ABGR8888 max sizes
[10:47:15] [PASSED] ABGR8888 pitch greater than min required
[10:47:15] [PASSED] ABGR8888 pitch less than min required
[10:47:15] [PASSED] ABGR8888 Invalid width
[10:47:15] [PASSED] ABGR8888 Invalid buffer handle
[10:47:15] [PASSED] No pixel format
[10:47:15] [PASSED] ABGR8888 Width 0
[10:47:15] [PASSED] ABGR8888 Height 0
[10:47:15] [PASSED] ABGR8888 Out of bound height * pitch combination
[10:47:15] [PASSED] ABGR8888 Large buffer offset
[10:47:15] [PASSED] ABGR8888 Buffer offset for inexistent plane
[10:47:15] [PASSED] ABGR8888 Invalid flag
[10:47:15] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[10:47:15] [PASSED] ABGR8888 Valid buffer modifier
[10:47:15] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[10:47:15] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[10:47:15] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[10:47:15] [PASSED] NV12 Normal sizes
[10:47:15] [PASSED] NV12 Max sizes
[10:47:15] [PASSED] NV12 Invalid pitch
[10:47:15] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[10:47:15] [PASSED] NV12 different  modifier per-plane
[10:47:15] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[10:47:15] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[10:47:15] [PASSED] NV12 Modifier for inexistent plane
[10:47:15] [PASSED] NV12 Handle for inexistent plane
[10:47:15] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[10:47:15] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[10:47:15] [PASSED] YVU420 Normal sizes
[10:47:15] [PASSED] YVU420 Max sizes
[10:47:15] [PASSED] YVU420 Invalid pitch
[10:47:15] [PASSED] YVU420 Different pitches
[10:47:15] [PASSED] YVU420 Different buffer offsets/pitches
[10:47:15] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[10:47:15] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[10:47:15] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[10:47:15] [PASSED] YVU420 Valid modifier
[10:47:15] [PASSED] YVU420 Different modifiers per plane
[10:47:15] [PASSED] YVU420 Modifier for inexistent plane
[10:47:15] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[10:47:15] [PASSED] X0L2 Normal sizes
[10:47:15] [PASSED] X0L2 Max sizes
[10:47:15] [PASSED] X0L2 Invalid pitch
[10:47:15] [PASSED] X0L2 Pitch greater than minimum required
[10:47:15] [PASSED] X0L2 Handle for inexistent plane
[10:47:15] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[10:47:15] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[10:47:15] [PASSED] X0L2 Valid modifier
[10:47:15] [PASSED] X0L2 Modifier for inexistent plane
[10:47:15] =========== [PASSED] drm_test_framebuffer_create ===========
[10:47:15] [PASSED] drm_test_framebuffer_free
[10:47:15] [PASSED] drm_test_framebuffer_init
[10:47:15] [PASSED] drm_test_framebuffer_init_bad_format
[10:47:15] [PASSED] drm_test_framebuffer_init_dev_mismatch
[10:47:15] [PASSED] drm_test_framebuffer_lookup
[10:47:15] [PASSED] drm_test_framebuffer_lookup_inexistent
[10:47:15] [PASSED] drm_test_framebuffer_modifiers_not_supported
[10:47:15] ================= [PASSED] drm_framebuffer =================
[10:47:15] ================ drm_gem_shmem (8 subtests) ================
[10:47:15] [PASSED] drm_gem_shmem_test_obj_create
[10:47:15] [PASSED] drm_gem_shmem_test_obj_create_private
[10:47:15] [PASSED] drm_gem_shmem_test_pin_pages
[10:47:15] [PASSED] drm_gem_shmem_test_vmap
[10:47:15] [PASSED] drm_gem_shmem_test_get_sg_table
[10:47:15] [PASSED] drm_gem_shmem_test_get_pages_sgt
[10:47:15] [PASSED] drm_gem_shmem_test_madvise
[10:47:15] [PASSED] drm_gem_shmem_test_purge
[10:47:15] ================== [PASSED] drm_gem_shmem ==================
[10:47:15] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[10:47:15] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[10:47:15] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[10:47:15] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[10:47:15] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[10:47:15] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[10:47:15] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[10:47:15] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[10:47:15] [PASSED] Automatic
[10:47:15] [PASSED] Full
[10:47:15] [PASSED] Limited 16:235
[10:47:15] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[10:47:15] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[10:47:15] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[10:47:15] [PASSED] drm_test_check_disable_connector
[10:47:15] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[10:47:15] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[10:47:15] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[10:47:15] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[10:47:15] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[10:47:15] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[10:47:15] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[10:47:15] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[10:47:15] [PASSED] drm_test_check_output_bpc_dvi
[10:47:15] [PASSED] drm_test_check_output_bpc_format_vic_1
[10:47:15] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[10:47:15] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[10:47:15] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[10:47:15] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[10:47:15] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[10:47:15] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[10:47:15] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[10:47:15] ============ drm_test_check_hdmi_color_format  =============
[10:47:15] [PASSED] AUTO -> RGB
[10:47:15] [PASSED] YCBCR422 -> YUV422
[10:47:15] [PASSED] YCBCR420 -> YUV420
[10:47:15] [PASSED] YCBCR444 -> YUV444
[10:47:15] [PASSED] RGB -> RGB
[10:47:15] ======== [PASSED] drm_test_check_hdmi_color_format =========
[10:47:15] ======== drm_test_check_hdmi_color_format_420_only  ========
[10:47:15] [PASSED] RGB should fail
[10:47:15] [PASSED] YUV444 should fail
[10:47:15] [PASSED] YUV422 should fail
[10:47:15] [PASSED] YUV420 should work
[10:47:15] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[10:47:15] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[10:47:15] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[10:47:15] [PASSED] drm_test_check_broadcast_rgb_value
[10:47:15] [PASSED] drm_test_check_bpc_8_value
[10:47:15] [PASSED] drm_test_check_bpc_10_value
[10:47:15] [PASSED] drm_test_check_bpc_12_value
[10:47:15] [PASSED] drm_test_check_format_value
[10:47:15] [PASSED] drm_test_check_tmds_char_value
[10:47:15] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[10:47:15] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[10:47:15] [PASSED] drm_test_check_mode_valid
[10:47:15] [PASSED] drm_test_check_mode_valid_reject
[10:47:15] [PASSED] drm_test_check_mode_valid_reject_rate
[10:47:15] [PASSED] drm_test_check_mode_valid_reject_max_clock
[10:47:15] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[10:47:15] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[10:47:15] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[10:47:15] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[10:47:15] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[10:47:15] [PASSED] drm_test_check_infoframes
[10:47:15] [PASSED] drm_test_check_reject_avi_infoframe
[10:47:15] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[10:47:15] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[10:47:15] [PASSED] drm_test_check_reject_audio_infoframe
[10:47:15] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[10:47:15] ================= drm_managed (2 subtests) =================
[10:47:15] [PASSED] drm_test_managed_release_action
[10:47:15] [PASSED] drm_test_managed_run_action
[10:47:15] =================== [PASSED] drm_managed ===================
[10:47:15] =================== drm_mm (6 subtests) ====================
[10:47:15] [PASSED] drm_test_mm_init
[10:47:15] [PASSED] drm_test_mm_debug
[10:47:15] [PASSED] drm_test_mm_align32
[10:47:15] [PASSED] drm_test_mm_align64
[10:47:15] [PASSED] drm_test_mm_lowest
[10:47:15] [PASSED] drm_test_mm_highest
[10:47:15] ===================== [PASSED] drm_mm ======================
[10:47:15] ============= drm_modes_analog_tv (5 subtests) =============
[10:47:15] [PASSED] drm_test_modes_analog_tv_mono_576i
[10:47:15] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[10:47:15] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[10:47:15] [PASSED] drm_test_modes_analog_tv_pal_576i
[10:47:15] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[10:47:15] =============== [PASSED] drm_modes_analog_tv ===============
[10:47:15] ============== drm_plane_helper (2 subtests) ===============
[10:47:15] =============== drm_test_check_plane_state  ================
[10:47:15] [PASSED] clipping_simple
[10:47:15] [PASSED] clipping_rotate_reflect
[10:47:15] [PASSED] positioning_simple
[10:47:15] [PASSED] upscaling
[10:47:15] [PASSED] downscaling
[10:47:15] [PASSED] rounding1
[10:47:15] [PASSED] rounding2
[10:47:15] [PASSED] rounding3
[10:47:15] [PASSED] rounding4
[10:47:15] =========== [PASSED] drm_test_check_plane_state ============
[10:47:15] =========== drm_test_check_invalid_plane_state  ============
[10:47:15] [PASSED] positioning_invalid
[10:47:15] [PASSED] upscaling_invalid
[10:47:15] [PASSED] downscaling_invalid
[10:47:15] ======= [PASSED] drm_test_check_invalid_plane_state ========
[10:47:15] ================ [PASSED] drm_plane_helper =================
[10:47:15] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[10:47:15] ====== drm_test_connector_helper_tv_get_modes_check  =======
[10:47:15] [PASSED] None
[10:47:15] [PASSED] PAL
[10:47:15] [PASSED] NTSC
[10:47:15] [PASSED] Both, NTSC Default
[10:47:15] [PASSED] Both, PAL Default
[10:47:15] [PASSED] Both, NTSC Default, with PAL on command-line
[10:47:15] [PASSED] Both, PAL Default, with NTSC on command-line
[10:47:15] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[10:47:15] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[10:47:15] ================== drm_rect (9 subtests) ===================
[10:47:15] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[10:47:15] [PASSED] drm_test_rect_clip_scaled_not_clipped
[10:47:15] [PASSED] drm_test_rect_clip_scaled_clipped
[10:47:15] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[10:47:15] ================= drm_test_rect_intersect  =================
[10:47:15] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[10:47:15] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[10:47:15] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[10:47:15] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[10:47:15] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[10:47:15] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[10:47:15] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[10:47:15] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[10:47:15] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[10:47:15] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[10:47:15] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[10:47:15] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[10:47:15] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[10:47:15] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[10:47:15] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[10:47:15] ============= [PASSED] drm_test_rect_intersect =============
[10:47:15] ================ drm_test_rect_calc_hscale  ================
[10:47:15] [PASSED] normal use
[10:47:15] [PASSED] out of max range
[10:47:15] [PASSED] out of min range
[10:47:15] [PASSED] zero dst
[10:47:15] [PASSED] negative src
[10:47:15] [PASSED] negative dst
[10:47:15] ============ [PASSED] drm_test_rect_calc_hscale ============
[10:47:15] ================ drm_test_rect_calc_vscale  ================
[10:47:15] [PASSED] normal use
[10:47:15] [PASSED] out of max range
[10:47:15] [PASSED] out of min range
[10:47:15] [PASSED] zero dst
[10:47:15] [PASSED] negative src
[10:47:15] [PASSED] negative dst
[10:47:15] ============ [PASSED] drm_test_rect_calc_vscale ============
[10:47:15] ================== drm_test_rect_rotate  ===================
[10:47:15] [PASSED] reflect-x
[10:47:15] [PASSED] reflect-y
[10:47:15] [PASSED] rotate-0
[10:47:15] [PASSED] rotate-90
[10:47:15] [PASSED] rotate-180
[10:47:15] [PASSED] rotate-270
[10:47:15] ============== [PASSED] drm_test_rect_rotate ===============
[10:47:15] ================ drm_test_rect_rotate_inv  =================
[10:47:15] [PASSED] reflect-x
[10:47:15] [PASSED] reflect-y
[10:47:15] [PASSED] rotate-0
[10:47:15] [PASSED] rotate-90
[10:47:15] [PASSED] rotate-180
[10:47:15] [PASSED] rotate-270
[10:47:15] ============ [PASSED] drm_test_rect_rotate_inv =============
[10:47:15] ==================== [PASSED] drm_rect =====================
[10:47:15] ============ drm_sysfb_modeset_test (1 subtest) ============
[10:47:15] ============ drm_test_sysfb_build_fourcc_list  =============
[10:47:15] [PASSED] no native formats
[10:47:15] [PASSED] XRGB8888 as native format
[10:47:15] [PASSED] remove duplicates
[10:47:15] [PASSED] convert alpha formats
[10:47:15] [PASSED] random formats
[10:47:15] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[10:47:15] ============= [PASSED] drm_sysfb_modeset_test ==============
[10:47:15] ================== drm_fixp (2 subtests) ===================
[10:47:15] [PASSED] drm_test_int2fixp
[10:47:15] [PASSED] drm_test_sm2fixp
[10:47:15] ==================== [PASSED] drm_fixp =====================
[10:47:15] ============================================================
[10:47:15] Testing complete. Ran 641 tests: passed: 641
[10:47:15] Elapsed time: 27.214s total, 1.826s configuring, 25.220s building, 0.146s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[10:47:15] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[10:47:17] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[10:47:27] Starting KUnit Kernel (1/1)...
[10:47:27] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[10:47:27] ============= refcount_interrupt (4 subtests) ==============
[10:47:27] [PASSED] test_single_irq_change
[10:47:27] [PASSED] test_nested_irq_change
[10:47:27] [PASSED] test_multiple_irq_change
[10:47:27] [PASSED] test_irq_save
[10:47:27] =============== [PASSED] refcount_interrupt ================
[10:47:27] ================= ttm_device (5 subtests) ==================
[10:47:27] [PASSED] ttm_device_init_basic
[10:47:27] [PASSED] ttm_device_init_multiple
[10:47:27] [PASSED] ttm_device_fini_basic
[10:47:27] [PASSED] ttm_device_init_no_vma_man
[10:47:27] ================== ttm_device_init_pools  ==================
[10:47:27] [PASSED] No DMA allocations, no DMA32 required
[10:47:27] [PASSED] DMA allocations, DMA32 required
[10:47:27] [PASSED] No DMA allocations, DMA32 required
[10:47:27] [PASSED] DMA allocations, no DMA32 required
[10:47:27] ============== [PASSED] ttm_device_init_pools ==============
[10:47:27] =================== [PASSED] ttm_device ====================
[10:47:27] ================== ttm_pool (8 subtests) ===================
[10:47:27] ================== ttm_pool_alloc_basic  ===================
[10:47:27] [PASSED] One page
[10:47:27] [PASSED] More than one page
[10:47:27] [PASSED] Above the allocation limit
[10:47:27] [PASSED] One page, with coherent DMA mappings enabled
[10:47:27] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[10:47:27] ============== [PASSED] ttm_pool_alloc_basic ===============
[10:47:27] ============== ttm_pool_alloc_basic_dma_addr  ==============
[10:47:27] [PASSED] One page
[10:47:27] [PASSED] More than one page
[10:47:27] [PASSED] Above the allocation limit
[10:47:27] [PASSED] One page, with coherent DMA mappings enabled
[10:47:27] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[10:47:27] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[10:47:27] [PASSED] ttm_pool_alloc_order_caching_match
[10:47:27] [PASSED] ttm_pool_alloc_caching_mismatch
[10:47:27] [PASSED] ttm_pool_alloc_order_mismatch
[10:47:27] [PASSED] ttm_pool_free_dma_alloc
[10:47:27] [PASSED] ttm_pool_free_no_dma_alloc
[10:47:27] [PASSED] ttm_pool_fini_basic
[10:47:27] ==================== [PASSED] ttm_pool =====================
[10:47:27] ================ ttm_resource (8 subtests) =================
[10:47:27] ================= ttm_resource_init_basic  =================
[10:47:27] [PASSED] Init resource in TTM_PL_SYSTEM
[10:47:27] [PASSED] Init resource in TTM_PL_VRAM
[10:47:27] [PASSED] Init resource in a private placement
[10:47:27] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[10:47:27] ============= [PASSED] ttm_resource_init_basic =============
[10:47:27] [PASSED] ttm_resource_init_pinned
[10:47:27] [PASSED] ttm_resource_fini_basic
[10:47:27] [PASSED] ttm_resource_manager_init_basic
[10:47:27] [PASSED] ttm_resource_manager_usage_basic
[10:47:27] [PASSED] ttm_resource_manager_set_used_basic
[10:47:27] [PASSED] ttm_sys_man_alloc_basic
[10:47:27] [PASSED] ttm_sys_man_free_basic
[10:47:27] ================== [PASSED] ttm_resource ===================
[10:47:27] =================== ttm_tt (15 subtests) ===================
[10:47:27] ==================== ttm_tt_init_basic  ====================
[10:47:27] [PASSED] Page-aligned size
[10:47:27] [PASSED] Extra pages requested
[10:47:27] ================ [PASSED] ttm_tt_init_basic ================
[10:47:27] [PASSED] ttm_tt_init_misaligned
[10:47:27] [PASSED] ttm_tt_fini_basic
[10:47:27] [PASSED] ttm_tt_fini_sg
[10:47:27] [PASSED] ttm_tt_fini_shmem
[10:47:27] [PASSED] ttm_tt_create_basic
[10:47:27] [PASSED] ttm_tt_create_invalid_bo_type
[10:47:27] [PASSED] ttm_tt_create_ttm_exists
[10:47:27] [PASSED] ttm_tt_create_failed
[10:47:27] [PASSED] ttm_tt_destroy_basic
[10:47:27] [PASSED] ttm_tt_populate_null_ttm
[10:47:27] [PASSED] ttm_tt_populate_populated_ttm
[10:47:27] [PASSED] ttm_tt_unpopulate_basic
[10:47:27] [PASSED] ttm_tt_unpopulate_empty_ttm
[10:47:27] [PASSED] ttm_tt_swapin_basic
[10:47:27] ===================== [PASSED] ttm_tt ======================
[10:47:27] =================== ttm_bo (14 subtests) ===================
[10:47:27] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[10:47:27] [PASSED] Cannot be interrupted and sleeps
[10:47:27] [PASSED] Cannot be interrupted, locks straight away
[10:47:27] [PASSED] Can be interrupted, sleeps
[10:47:27] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[10:47:27] [PASSED] ttm_bo_reserve_locked_no_sleep
[10:47:27] [PASSED] ttm_bo_reserve_no_wait_ticket
[10:47:27] [PASSED] ttm_bo_reserve_double_resv
[10:47:27] [PASSED] ttm_bo_reserve_interrupted
[10:47:27] [PASSED] ttm_bo_reserve_deadlock
[10:47:27] [PASSED] ttm_bo_unreserve_basic
[10:47:27] [PASSED] ttm_bo_unreserve_pinned
[10:47:27] [PASSED] ttm_bo_unreserve_bulk
[10:47:27] [PASSED] ttm_bo_fini_basic
[10:47:27] [PASSED] ttm_bo_fini_shared_resv
[10:47:27] [PASSED] ttm_bo_pin_basic
[10:47:27] [PASSED] ttm_bo_pin_unpin_resource
[10:47:27] [PASSED] ttm_bo_multiple_pin_one_unpin
[10:47:27] ===================== [PASSED] ttm_bo ======================
[10:47:27] ============== ttm_bo_validate (22 subtests) ===============
[10:47:27] ============== ttm_bo_init_reserved_sys_man  ===============
[10:47:27] [PASSED] Buffer object for userspace
[10:47:27] [PASSED] Kernel buffer object
[10:47:27] [PASSED] Shared buffer object
[10:47:27] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[10:47:27] ============== ttm_bo_init_reserved_mock_man  ==============
[10:47:27] [PASSED] Buffer object for userspace
[10:47:27] [PASSED] Kernel buffer object
[10:47:27] [PASSED] Shared buffer object
[10:47:27] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[10:47:27] [PASSED] ttm_bo_init_reserved_resv
[10:47:27] ================== ttm_bo_validate_basic  ==================
[10:47:27] [PASSED] Buffer object for userspace
[10:47:27] [PASSED] Kernel buffer object
[10:47:27] [PASSED] Shared buffer object
[10:47:27] ============== [PASSED] ttm_bo_validate_basic ==============
[10:47:27] [PASSED] ttm_bo_validate_invalid_placement
[10:47:27] ============= ttm_bo_validate_same_placement  ==============
[10:47:27] [PASSED] System manager
[10:47:27] [PASSED] VRAM manager
[10:47:27] ========= [PASSED] ttm_bo_validate_same_placement ==========
[10:47:27] [PASSED] ttm_bo_validate_failed_alloc
[10:47:27] [PASSED] ttm_bo_validate_pinned
[10:47:27] [PASSED] ttm_bo_validate_busy_placement
[10:47:27] ================ ttm_bo_validate_multihop  =================
[10:47:27] [PASSED] Buffer object for userspace
[10:47:27] [PASSED] Kernel buffer object
[10:47:27] [PASSED] Shared buffer object
[10:47:27] ============ [PASSED] ttm_bo_validate_multihop =============
[10:47:27] ========== ttm_bo_validate_no_placement_signaled  ==========
[10:47:27] [PASSED] Buffer object in system domain, no page vector
[10:47:27] [PASSED] Buffer object in system domain with an existing page vector
[10:47:27] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[10:47:27] ======== ttm_bo_validate_no_placement_not_signaled  ========
[10:47:27] [PASSED] Buffer object for userspace
[10:47:27] [PASSED] Kernel buffer object
[10:47:27] [PASSED] Shared buffer object
[10:47:27] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[10:47:27] [PASSED] ttm_bo_validate_move_fence_signaled
[10:47:27] ========= ttm_bo_validate_move_fence_not_signaled  =========
[10:47:27] [PASSED] Waits for GPU
[10:47:27] [PASSED] Tries to lock straight away
[10:47:27] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[10:47:27] [PASSED] ttm_bo_validate_swapout
[10:47:27] [PASSED] ttm_bo_validate_happy_evict
[10:47:27] [PASSED] ttm_bo_validate_all_pinned_evict
[10:47:27] [PASSED] ttm_bo_validate_allowed_only_evict
[10:47:27] [PASSED] ttm_bo_validate_deleted_evict
[10:47:27] [PASSED] ttm_bo_validate_busy_domain_evict
[10:47:27] [PASSED] ttm_bo_validate_evict_gutting
[10:47:27] [PASSED] ttm_bo_validate_recrusive_evict
[10:47:27] ================= [PASSED] ttm_bo_validate =================
[10:47:27] ============================================================
[10:47:27] Testing complete. Ran 106 tests: passed: 106
[10:47:27] Elapsed time: 11.965s total, 1.834s configuring, 9.917s building, 0.186s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/dma-buf/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/dma-buf/.kunitconfig
[10:47:27] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[10:47:29] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[10:47:37] Starting KUnit Kernel (1/1)...
[10:47:37] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[10:47:37] ============= refcount_interrupt (4 subtests) ==============
[10:47:37] [PASSED] test_single_irq_change
[10:47:37] [PASSED] test_nested_irq_change
[10:47:37] [PASSED] test_multiple_irq_change
[10:47:37] [PASSED] test_irq_save
[10:47:37] =============== [PASSED] refcount_interrupt ================
[10:47:37] =============== dma-buf-fence (12 subtests) ================
[10:47:37] [PASSED] test_sanitycheck
[10:47:37] [PASSED] test_signaling
[10:47:37] [PASSED] test_add_callback
[10:47:37] [PASSED] test_late_add_callback
[10:47:37] [PASSED] test_rm_callback
[10:47:37] [PASSED] test_late_rm_callback
[10:47:37] [PASSED] test_status
[10:47:37] [PASSED] test_error
[10:47:37] [PASSED] test_wait
[10:47:37] [PASSED] test_wait_timeout
[10:47:37] [PASSED] test_stub
[10:47:37] [SKIPPED] test_race_signal_callback (requires at least 2 CPUs)
[10:47:37] ================== [PASSED] dma-buf-fence ==================
[10:47:37] ============ dma-buf-fence-chain (11 subtests) =============
[10:47:37] [PASSED] test_sanitycheck
[10:47:37] [PASSED] test_find_seqno
[10:47:37] [PASSED] test_find_signaled
[10:47:37] [PASSED] test_find_out_of_order
[10:47:42] [PASSED] test_find_gap
[10:47:42] [PASSED] test_find_race
[10:47:42] [PASSED] test_signal_forward
[10:47:43] [PASSED] test_signal_backward
[10:47:43] [PASSED] test_wait_forward
[10:47:43] [PASSED] test_wait_backward
[10:47:43] [PASSED] test_wait_random
[10:47:43] =============== [PASSED] dma-buf-fence-chain ===============
[10:47:43] ============ dma-buf-fence-unwrap (10 subtests) ============
[10:47:43] [PASSED] test_sanitycheck
[10:47:43] [PASSED] test_unwrap_array
[10:47:43] [PASSED] test_unwrap_chain
[10:47:43] [PASSED] test_unwrap_chain_array
[10:47:43] [PASSED] test_unwrap_merge
[10:47:43] [PASSED] test_unwrap_merge_duplicate
[10:47:43] [PASSED] test_unwrap_merge_seqno
[10:47:43] [PASSED] test_unwrap_merge_order
[10:47:43] [PASSED] test_unwrap_merge_complex
[10:47:43] [PASSED] test_unwrap_merge_complex_seqno
[10:47:43] ============== [PASSED] dma-buf-fence-unwrap ===============
[10:47:43] ================ dma-buf-resv (5 subtests) =================
[10:47:43] [PASSED] test_sanitycheck
[10:47:43] ===================== test_signaling  ======================
[10:47:43] [PASSED] kernel
[10:47:43] [PASSED] write
[10:47:43] [PASSED] read
[10:47:43] [PASSED] bookkeep
[10:47:43] ================= [PASSED] test_signaling ==================
[10:47:43] ====================== test_for_each  ======================
[10:47:43] [PASSED] kernel
[10:47:43] [PASSED] write
[10:47:43] [PASSED] read
[10:47:43] [PASSED] bookkeep
[10:47:43] ================== [PASSED] test_for_each ==================
[10:47:43] ================= test_for_each_unlocked  ==================
[10:47:43] [PASSED] kernel
[10:47:43] [PASSED] write
[10:47:43] [PASSED] read
[10:47:43] [PASSED] bookkeep
[10:47:43] ============= [PASSED] test_for_each_unlocked ==============
[10:47:43] ===================== test_get_fences  =====================
[10:47:43] [PASSED] kernel
[10:47:43] [PASSED] write
[10:47:43] [PASSED] read
[10:47:43] [PASSED] bookkeep
[10:47:43] ================= [PASSED] test_get_fences =================
[10:47:43] ================== [PASSED] dma-buf-resv ===================
[10:47:43] ============================================================
[10:47:43] Testing complete. Ran 54 tests: passed: 53, skipped: 1
[10:47:43] Elapsed time: 15.726s total, 1.783s configuring, 8.622s building, 5.278s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✗ Xe.CI.BAT: failure for VRAM health check + CCS fix (rev2)

[Patchwork]

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== Series Details ==

Series: VRAM health check + CCS fix (rev2)
URL   : https://patchwork.freedesktop.org/series/172984/
State : failure

== Summary ==

CI Bug Log - changes from xe-5672-f6e82e1b1b96ea7150f101ce93f139e1ff131d67_BAT -> xe-pw-172984v2_BAT
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-172984v2_BAT absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-172984v2_BAT, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (12 -> 12)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-172984v2_BAT:

### IGT changes ###

#### Possible regressions ####

  * igt@xe_waitfence@reltime:
    - bat-ptl-2:          [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5672-f6e82e1b1b96ea7150f101ce93f139e1ff131d67/bat-ptl-2/igt@xe_waitfence@reltime.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v2/bat-ptl-2/igt@xe_waitfence@reltime.html

  
Known issues
------------

  Here are the changes found in xe-pw-172984v2_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@core_hotunplug@unbind-rebind:
    - bat-nvls-1:         [PASS][3] -> [DMESG-WARN][4] ([Intel XE#8762] / [Intel XE#9069])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5672-f6e82e1b1b96ea7150f101ce93f139e1ff131d67/bat-nvls-1/igt@core_hotunplug@unbind-rebind.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v2/bat-nvls-1/igt@core_hotunplug@unbind-rebind.html

  
#### Possible fixes ####

  * igt@xe_waitfence@engine:
    - bat-wcl-1:          [FAIL][5] ([Intel XE#9103]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5672-f6e82e1b1b96ea7150f101ce93f139e1ff131d67/bat-wcl-1/igt@xe_waitfence@engine.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v2/bat-wcl-1/igt@xe_waitfence@engine.html

  
  [Intel XE#8762]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8762
  [Intel XE#9069]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9069
  [Intel XE#9103]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9103


Build changes
-------------

  * Linux: xe-5672-f6e82e1b1b96ea7150f101ce93f139e1ff131d67 -> xe-pw-172984v2

  IGT_9079: 9079
  xe-5672-f6e82e1b1b96ea7150f101ce93f139e1ff131d67: f6e82e1b1b96ea7150f101ce93f139e1ff131d67
  xe-pw-172984v2: 172984v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v2/index.html

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